From 698ba367a105d9c0db637f29a6b7dedc92ca4ec4 Mon Sep 17 00:00:00 2001 From: Andrei Vlad LUTAS Date: Tue, 21 Jul 2020 11:19:18 +0300 Subject: [PATCH] Initial commit. --- .gitignore | 65 + .vsconfig | 21 + Makefile | 22 + README.md | 50 +- bddisasm.sln | 87 + bddisasm/Makefile | 123 + bddisasm/bddisasm.c | 5050 + bddisasm/bddisasm.vcproj | 474 + bddisasm/bddisasm.vcxproj | 458 + bddisasm/bddisasm.vcxproj.filters | 81 + bddisasm/crt.c | 44 + bddisasm/include/instructions.h | 35360 ++ bddisasm/include/mnemonics.h | 282 + bddisasm/include/nd_crt.h | 90 + bddisasm/include/prefixes.h | 34 + bddisasm/include/table_evex.h | 12254 + bddisasm/include/table_root.h | 15555 + bddisasm/include/table_vex.h | 11644 + bddisasm/include/table_xop.h | 1541 + bddisasm/include/tabledefs.h | 480 + bddisasm_test/README.md | 12 + bddisasm_test/amx/amx1_64 | Bin 0 -> 98 bytes bddisasm_test/amx/amx1_64.asm | 23 + bddisasm_test/amx/amx1_64.result | 263 + bddisasm_test/avx/avx2_64 | Bin 0 -> 2198 bytes bddisasm_test/avx/avx2_64.asm | 302 + bddisasm_test/avx/avx2_64.result | 5540 + bddisasm_test/avx/avx2gather_64 | Bin 0 -> 100 bytes bddisasm_test/avx/avx2gather_64.asm | 12 + bddisasm_test/avx/avx2gather_64.result | 180 + bddisasm_test/avx/avx_64 | Bin 0 -> 15667 bytes bddisasm_test/avx/avx_64.asm | 2200 + bddisasm_test/avx/avx_64.result | 40788 +++ bddisasm_test/avx/f16c_64 | 4 + bddisasm_test/avx/f16c_64.asm | 11 + bddisasm_test/avx/f16c_64.result | 136 + bddisasm_test/avx/fma4_64 | 1 + bddisasm_test/avx/fma4_64.asm | 133 + bddisasm_test/avx/fma4_64.result | 2240 + bddisasm_test/avx/fma_64 | 1 + bddisasm_test/avx/fma_64.asm | 198 + bddisasm_test/avx/fma_64.result | 3360 + bddisasm_test/avx512/avx512bitalg_64 | 1 + bddisasm_test/avx512/avx512bitalg_64.asm | 122 + bddisasm_test/avx512/avx512bitalg_64.result | 2358 + bddisasm_test/avx512/avx512bw_64 | Bin 0 -> 24734 bytes bddisasm_test/avx512/avx512bw_64.asm | 3492 + bddisasm_test/avx512/avx512bw_64.result | 71037 ++++ bddisasm_test/avx512/avx512cd_64 | 1 + bddisasm_test/avx512/avx512cd_64.asm | 248 + bddisasm_test/avx512/avx512cd_64.result | 4902 + bddisasm_test/avx512/avx512dq_64 | Bin 0 -> 13518 bytes bddisasm_test/avx512/avx512dq_64.asm | 1926 + bddisasm_test/avx512/avx512dq_64.result | 39404 ++ bddisasm_test/avx512/avx512er_64 | 1 + bddisasm_test/avx512/avx512er_64.asm | 226 + bddisasm_test/avx512/avx512er_64.result | 4504 + bddisasm_test/avx512/avx512f_64 | Bin 0 -> 94145 bytes bddisasm_test/avx512/avx512f_64.asm | 13534 + bddisasm_test/avx512/avx512f_64.result | 277669 +++++++++++++++ bddisasm_test/avx512/avx512fma_64 | 1 + bddisasm_test/avx512/avx512fma_64.asm | 122 + bddisasm_test/avx512/avx512fma_64.result | 2520 + bddisasm_test/avx512/avx512pf_64 | Bin 0 -> 176 bytes bddisasm_test/avx512/avx512pf_64.asm | 18 + bddisasm_test/avx512/avx512pf_64.result | 320 + bddisasm_test/avx512/avx512vbmi_64 | 1 + bddisasm_test/avx512/avx512vbmi_64.asm | 926 + bddisasm_test/avx512/avx512vbmi_64.result | 23586 ++ bddisasm_test/avx512/avx512vnni_64 | 1 + bddisasm_test/avx512/avx512vnni_64.asm | 242 + bddisasm_test/avx512/avx512vnni_64.result | 5040 + bddisasm_test/basic/address_16 | Bin 0 -> 71 bytes bddisasm_test/basic/address_16.asm | 31 + bddisasm_test/basic/address_16.result | 255 + bddisasm_test/basic/address_32 | Bin 0 -> 73 bytes bddisasm_test/basic/address_32.asm | 32 + bddisasm_test/basic/address_32.result | 255 + bddisasm_test/basic/address_64 | Bin 0 -> 195 bytes bddisasm_test/basic/address_64.asm | 81 + bddisasm_test/basic/address_64.result | 525 + bddisasm_test/basic/aes_64 | 5 + bddisasm_test/basic/aes_64.asm | 57 + bddisasm_test/basic/aes_64.result | 696 + bddisasm_test/basic/basic1_64 | Bin 0 -> 1600 bytes bddisasm_test/basic/basic1_64.asm | 562 + bddisasm_test/basic/basic1_64.result | 9088 + bddisasm_test/basic/basic2_64 | 7 + bddisasm_test/basic/basic2_64.asm | 171 + bddisasm_test/basic/basic2_64.result | 2604 + bddisasm_test/basic/bmi_64 | 4 + bddisasm_test/basic/bmi_64.asm | 57 + bddisasm_test/basic/bmi_64.result | 974 + bddisasm_test/basic/branch_16 | Bin 0 -> 118 bytes bddisasm_test/basic/branch_16.asm | 51 + bddisasm_test/basic/branch_16.result | 744 + bddisasm_test/basic/branch_32 | Bin 0 -> 120 bytes bddisasm_test/basic/branch_32.asm | 54 + bddisasm_test/basic/branch_32.result | 784 + bddisasm_test/basic/branch_64 | Bin 0 -> 70 bytes bddisasm_test/basic/branch_64.asm | 41 + bddisasm_test/basic/branch_64.result | 577 + bddisasm_test/basic/cet_64 | Bin 0 -> 49 bytes bddisasm_test/basic/cet_64.asm | 13 + bddisasm_test/basic/cet_64.result | 164 + bddisasm_test/basic/enqcmd_64 | Bin 0 -> 19 bytes bddisasm_test/basic/enqcmd_64.asm | 6 + bddisasm_test/basic/enqcmd_64.result | 73 + bddisasm_test/basic/fpu_64 | 1 + bddisasm_test/basic/fpu_64.asm | 157 + bddisasm_test/basic/fpu_64.result | 2449 + bddisasm_test/basic/gfni_64 | 26 + bddisasm_test/basic/gfni_64.asm | 57 + bddisasm_test/basic/gfni_64.result | 766 + bddisasm_test/basic/invlpgb_64 | 1 + bddisasm_test/basic/invlpgb_64.asm | 4 + bddisasm_test/basic/invlpgb_64.result | 29 + bddisasm_test/basic/misc_16 | Bin 0 -> 118 bytes bddisasm_test/basic/misc_16.asm | 65 + bddisasm_test/basic/misc_16.result | 765 + bddisasm_test/basic/misc_32 | Bin 0 -> 120 bytes bddisasm_test/basic/misc_32.asm | 65 + bddisasm_test/basic/misc_32.result | 765 + bddisasm_test/basic/misc_64 | 1 + bddisasm_test/basic/misc_64.asm | 92 + bddisasm_test/basic/misc_64.result | 1053 + bddisasm_test/basic/mpx_64 | 1 + bddisasm_test/basic/mpx_64.asm | 15 + bddisasm_test/basic/mpx_64.result | 203 + bddisasm_test/basic/prefixes_64 | Bin 0 -> 292 bytes bddisasm_test/basic/prefixes_64.asm | 91 + bddisasm_test/basic/prefixes_64.result | 1282 + bddisasm_test/basic/sha_64 | 2 + bddisasm_test/basic/sha_64.asm | 17 + bddisasm_test/basic/sha_64.result | 235 + bddisasm_test/basic/snp_64 | 1 + bddisasm_test/basic/snp_64.asm | 6 + bddisasm_test/basic/snp_64.result | 73 + bddisasm_test/basic/stack_16 | Bin 0 -> 65 bytes bddisasm_test/basic/stack_16.asm | 39 + bddisasm_test/basic/stack_16.result | 501 + bddisasm_test/basic/stack_32 | Bin 0 -> 67 bytes bddisasm_test/basic/stack_32.asm | 41 + bddisasm_test/basic/stack_32.result | 531 + bddisasm_test/basic/stack_64 | Bin 0 -> 62 bytes bddisasm_test/basic/stack_64.asm | 32 + bddisasm_test/basic/stack_64.result | 396 + bddisasm_test/basic/svm_64 | 1 + bddisasm_test/basic/svm_64.asm | 11 + bddisasm_test/basic/svm_64.result | 122 + bddisasm_test/basic/system_16 | Bin 0 -> 115 bytes bddisasm_test/basic/system_16.asm | 51 + bddisasm_test/basic/system_16.result | 559 + bddisasm_test/basic/system_32 | Bin 0 -> 113 bytes bddisasm_test/basic/system_32.asm | 51 + bddisasm_test/basic/system_32.result | 559 + bddisasm_test/basic/system_64 | Bin 0 -> 135 bytes bddisasm_test/basic/system_64.asm | 56 + bddisasm_test/basic/system_64.result | 621 + bddisasm_test/basic/tsx_64 | Bin 0 -> 23 bytes bddisasm_test/basic/tsx_64.asm | 8 + bddisasm_test/basic/tsx_64.result | 86 + bddisasm_test/basic/vmx_64 | Bin 0 -> 59 bytes bddisasm_test/basic/vmx_64.asm | 15 + bddisasm_test/basic/vmx_64.result | 221 + bddisasm_test/simd/3dnow_64 | 1 + bddisasm_test/simd/3dnow_64.asm | 53 + bddisasm_test/simd/3dnow_64.result | 775 + bddisasm_test/simd/mmx_64 | Bin 0 -> 570 bytes bddisasm_test/simd/mmx_64.asm | 178 + bddisasm_test/simd/mmx_64.result | 2678 + bddisasm_test/simd/sse2_64 | 41 + bddisasm_test/simd/sse2_64.asm | 287 + bddisasm_test/simd/sse2_64.result | 4703 + bddisasm_test/simd/sse3_64 | Bin 0 -> 267 bytes bddisasm_test/simd/sse3_64.asm | 55 + bddisasm_test/simd/sse3_64.result | 861 + bddisasm_test/simd/sse4_64 | 64 + bddisasm_test/simd/sse4_64.asm | 131 + bddisasm_test/simd/sse4_64.result | 2206 + bddisasm_test/special/amx_64 | Bin 0 -> 252 bytes bddisasm_test/special/amx_64.asm | 46 + bddisasm_test/special/amx_64.result | 1860 + bddisasm_test/special/avx2gather_1_64 | Bin 0 -> 10 bytes bddisasm_test/special/avx2gather_1_64.asm | 3 + bddisasm_test/special/avx2gather_1_64.result | 84 + bddisasm_test/special/avx2gather_2_64 | Bin 0 -> 10 bytes bddisasm_test/special/avx2gather_2_64.asm | 3 + bddisasm_test/special/avx2gather_2_64.result | 98 + bddisasm_test/special/avx2gather_3_64 | Bin 0 -> 10 bytes bddisasm_test/special/avx2gather_3_64.asm | 3 + bddisasm_test/special/avx2gather_3_64.result | 98 + bddisasm_test/special/cr8_32 | 1 + bddisasm_test/special/cr8_32.asm | 8 + bddisasm_test/special/cr8_32.result | 28 + bddisasm_test/special/invalid_32 | 1 + bddisasm_test/special/invalid_32.asm | 19 + bddisasm_test/special/invalid_32.result | 644 + bddisasm_test/special/invalid_64 | 1 + bddisasm_test/special/invalid_64.asm | 19 + bddisasm_test/special/invalid_64.result | 233 + bddisasm_test/special/long_64 | 1 + bddisasm_test/special/long_64.asm | 9 + bddisasm_test/special/long_64.result | 229 + bddisasm_test/special/movcrdr_64 | Bin 0 -> 68 bytes bddisasm_test/special/movcrdr_64.asm | 19 + bddisasm_test/special/movcrdr_64.result | 464 + bddisasm_test/special/only_32 | 1 + bddisasm_test/special/only_32.asm | 21 + bddisasm_test/special/only_32.result | 353 + bddisasm_test/special/only_64 | 1 + bddisasm_test/special/only_64.asm | 15 + bddisasm_test/special/only_64.result | 162 + bddisasm_test/test_all.py | 126 + bdshemu/Makefile | 123 + bdshemu/bdshemu.c | 2712 + bdshemu/bdshemu.vcxproj | 413 + bdshemu/bdshemu.vcxproj.filters | 30 + bdshemu_fuzz/Makefile | 73 + bdshemu_fuzz/README.md | 49 + bdshemu_fuzz/bdshemu_fuzzer.c | 218 + bdshemu_fuzz/in-32/test_32_str01 | 1 + bdshemu_fuzz/in-32/test_32_str02 | 1 + bdshemu_fuzz/in-32/test_32_str03 | Bin 0 -> 13 bytes bdshemu_fuzz/in-32/test_32_str04 | 1 + bdshemu_fuzz/in-32/test_32_sys01 | 1 + bdshemu_fuzz/in-32/test_64_basic01 | Bin 0 -> 12 bytes bdshemu_fuzz/in-32/test_64_basic04 | 1 + bdshemu_fuzz/in-32/test_64_basic05 | 1 + bdshemu_fuzz/in-32/test_64_basic06 | 1 + bdshemu_fuzz/in-32/test_64_basic07 | 1 + bdshemu_fuzz/in-32/test_64_basic08 | 1 + bdshemu_fuzz/in-32/test_64_basic09 | 1 + bdshemu_fuzz/in-32/test_64_branch1 | 2 + bdshemu_fuzz/in-32/test_64_branch2 | Bin 0 -> 20 bytes bdshemu_fuzz/in-32/test_64_branch3 | 2 + bdshemu_fuzz/in-32/test_64_branch4 | Bin 0 -> 14 bytes bdshemu_fuzz/in-32/test_64_div | 1 + bdshemu_fuzz/in-32/test_64_flags | 1 + bdshemu_fuzz/in-32/test_64_loadrip01 | Bin 0 -> 7 bytes bdshemu_fuzz/in-32/test_64_loadrip02 | 1 + bdshemu_fuzz/in-32/test_64_loadrip03 | Bin 0 -> 12 bytes bdshemu_fuzz/in-32/test_64_mov | 1 + bdshemu_fuzz/in-32/test_64_nopsled01 | 1 + bdshemu_fuzz/in-32/test_64_nopsled02 | 1 + bdshemu_fuzz/in-32/test_64_selfwrite02 | Bin 0 -> 11 bytes bdshemu_fuzz/in-32/test_64_selfwrite03 | Bin 0 -> 18 bytes bdshemu_fuzz/in-32/test_64_string | Bin 0 -> 15 bytes bdshemu_fuzz/in-32/test_64_sys01 | 1 + bdshemu_fuzz/in-32/test_64_sys02 | 1 + bdshemu_fuzz/in-32/test_64_sys03 | 1 + bdshemu_fuzz/in-64/test_32_str01 | 1 + bdshemu_fuzz/in-64/test_32_str02 | 1 + bdshemu_fuzz/in-64/test_32_str04 | 1 + bdshemu_fuzz/in-64/test_32_sys01 | 1 + bdshemu_fuzz/in-64/test_64_basic01 | Bin 0 -> 12 bytes bdshemu_fuzz/in-64/test_64_basic02 | Bin 0 -> 13 bytes bdshemu_fuzz/in-64/test_64_basic03 | Bin 0 -> 13 bytes bdshemu_fuzz/in-64/test_64_basic04 | 1 + bdshemu_fuzz/in-64/test_64_basic05 | 1 + bdshemu_fuzz/in-64/test_64_basic06 | 1 + bdshemu_fuzz/in-64/test_64_basic07 | 1 + bdshemu_fuzz/in-64/test_64_basic08 | 1 + bdshemu_fuzz/in-64/test_64_branch1 | 2 + bdshemu_fuzz/in-64/test_64_branch2 | Bin 0 -> 21 bytes bdshemu_fuzz/in-64/test_64_branch3 | 2 + bdshemu_fuzz/in-64/test_64_branch4 | Bin 0 -> 15 bytes bdshemu_fuzz/in-64/test_64_div | 1 + bdshemu_fuzz/in-64/test_64_flags | 1 + bdshemu_fuzz/in-64/test_64_loadrip01 | Bin 0 -> 7 bytes bdshemu_fuzz/in-64/test_64_loadrip02 | 1 + bdshemu_fuzz/in-64/test_64_loadrip03 | Bin 0 -> 12 bytes bdshemu_fuzz/in-64/test_64_mov | 1 + bdshemu_fuzz/in-64/test_64_nopsled01 | 1 + bdshemu_fuzz/in-64/test_64_nopsled02 | 1 + bdshemu_fuzz/in-64/test_64_selfwrite02 | Bin 0 -> 16 bytes bdshemu_fuzz/in-64/test_64_selfwrite03 | Bin 0 -> 27 bytes bdshemu_fuzz/in-64/test_64_string | Bin 0 -> 172 bytes bdshemu_fuzz/in-64/test_64_sys01 | 1 + bdshemu_fuzz/in-64/test_64_sys02 | 1 + bdshemu_fuzz/in-64/test_64_sys03 | 1 + bdshemu_test/README.md | 11 + bdshemu_test/basic/test_32_str01 | 1 + bdshemu_test/basic/test_32_str01.asm | 6 + bdshemu_test/basic/test_32_str01.result | 19 + bdshemu_test/basic/test_32_str02 | 1 + bdshemu_test/basic/test_32_str02.asm | 7 + bdshemu_test/basic/test_32_str02.result | 26 + bdshemu_test/basic/test_32_str03 | Bin 0 -> 13 bytes bdshemu_test/basic/test_32_str03.asm | 8 + bdshemu_test/basic/test_32_str03.result | 31 + bdshemu_test/basic/test_32_str04 | 1 + bdshemu_test/basic/test_32_str04.asm | 13 + bdshemu_test/basic/test_32_str04.result | 67 + bdshemu_test/basic/test_32_sys01 | 1 + bdshemu_test/basic/test_32_sys01.asm | 4 + bdshemu_test/basic/test_32_sys01.result | 8 + bdshemu_test/basic/test_64_basic01 | Bin 0 -> 13 bytes bdshemu_test/basic/test_64_basic01.asm | 6 + bdshemu_test/basic/test_64_basic01.result | 13 + bdshemu_test/basic/test_64_basic02 | Bin 0 -> 14 bytes bdshemu_test/basic/test_64_basic02.asm | 9 + bdshemu_test/basic/test_64_basic02.result | 19 + bdshemu_test/basic/test_64_basic03 | Bin 0 -> 20 bytes bdshemu_test/basic/test_64_basic03.asm | 8 + bdshemu_test/basic/test_64_basic03.result | 19 + bdshemu_test/basic/test_64_basic04 | 1 + bdshemu_test/basic/test_64_basic04.asm | 8 + bdshemu_test/basic/test_64_basic04.result | 19 + bdshemu_test/basic/test_64_basic05 | 1 + bdshemu_test/basic/test_64_basic05.asm | 8 + bdshemu_test/basic/test_64_basic05.result | 19 + bdshemu_test/basic/test_64_basic06 | 1 + bdshemu_test/basic/test_64_basic06.asm | 12 + bdshemu_test/basic/test_64_basic06.result | 13 + bdshemu_test/basic/test_64_basic07 | 1 + bdshemu_test/basic/test_64_basic07.asm | 4 + bdshemu_test/basic/test_64_basic07.result | 7 + bdshemu_test/basic/test_64_basic08 | 1 + bdshemu_test/basic/test_64_basic08.asm | 6 + bdshemu_test/basic/test_64_basic08.result | 13 + bdshemu_test/basic/test_64_basic09 | 1 + bdshemu_test/basic/test_64_basic09.asm | 6 + bdshemu_test/basic/test_64_basic09.result | 13 + bdshemu_test/basic/test_64_branch1 | Bin 0 -> 21 bytes bdshemu_test/basic/test_64_branch1.asm | 10 + bdshemu_test/basic/test_64_branch1.result | 25 + bdshemu_test/basic/test_64_branch2 | Bin 0 -> 21 bytes bdshemu_test/basic/test_64_branch2.asm | 10 + bdshemu_test/basic/test_64_branch2.result | 38 + bdshemu_test/basic/test_64_branch3 | Bin 0 -> 15 bytes bdshemu_test/basic/test_64_branch3.asm | 9 + bdshemu_test/basic/test_64_branch3.result | 19 + bdshemu_test/basic/test_64_branch4 | Bin 0 -> 15 bytes bdshemu_test/basic/test_64_branch4.asm | 9 + bdshemu_test/basic/test_64_branch4.result | 32 + bdshemu_test/basic/test_64_div | 1 + bdshemu_test/basic/test_64_div.asm | 6 + bdshemu_test/basic/test_64_div.result | 19 + bdshemu_test/basic/test_64_eicar | Bin 0 -> 109 bytes bdshemu_test/basic/test_64_eicar.asm | 10 + bdshemu_test/basic/test_64_eicar.result | 7 + bdshemu_test/basic/test_64_flags | Bin 0 -> 92 bytes bdshemu_test/basic/test_64_flags.asm | 41 + bdshemu_test/basic/test_64_flags.result | 175 + bdshemu_test/basic/test_64_loadrip01 | Bin 0 -> 7 bytes bdshemu_test/basic/test_64_loadrip01.asm | 7 + bdshemu_test/basic/test_64_loadrip01.result | 20 + bdshemu_test/basic/test_64_loadrip02 | 1 + bdshemu_test/basic/test_64_loadrip02.asm | 8 + bdshemu_test/basic/test_64_loadrip02.result | 32 + bdshemu_test/basic/test_64_loadrip03 | Bin 0 -> 12 bytes bdshemu_test/basic/test_64_loadrip03.asm | 8 + bdshemu_test/basic/test_64_loadrip03.result | 26 + bdshemu_test/basic/test_64_moffset | 1 + bdshemu_test/basic/test_64_moffset.asm | 5 + bdshemu_test/basic/test_64_moffset.result | 7 + bdshemu_test/basic/test_64_mov | 1 + bdshemu_test/basic/test_64_mov.asm | 22 + bdshemu_test/basic/test_64_mov.result | 91 + bdshemu_test/basic/test_64_nopsled01 | 1 + bdshemu_test/basic/test_64_nopsled01.asm | 20 + bdshemu_test/basic/test_64_nopsled01.result | 103 + bdshemu_test/basic/test_64_nopsled02 | 1 + bdshemu_test/basic/test_64_nopsled02.asm | 36 + bdshemu_test/basic/test_64_nopsled02.result | 199 + bdshemu_test/basic/test_64_nopsled03 | 1 + bdshemu_test/basic/test_64_nopsled03.asm | 4 + bdshemu_test/basic/test_64_nopsled03.result | 24578 ++ bdshemu_test/basic/test_64_selfwrite01 | Bin 0 -> 16 bytes bdshemu_test/basic/test_64_selfwrite01.asm | 12 + bdshemu_test/basic/test_64_selfwrite01.result | 37 + bdshemu_test/basic/test_64_selfwrite02 | Bin 0 -> 16 bytes bdshemu_test/basic/test_64_selfwrite02.asm | 12 + bdshemu_test/basic/test_64_selfwrite02.result | 44 + bdshemu_test/basic/test_64_selfwrite03 | Bin 0 -> 27 bytes bdshemu_test/basic/test_64_selfwrite03.asm | 10 + bdshemu_test/basic/test_64_selfwrite03.result | 74 + bdshemu_test/basic/test_64_string | Bin 0 -> 172 bytes bdshemu_test/basic/test_64_string.asm | 44 + bdshemu_test/basic/test_64_string.result | 169 + bdshemu_test/basic/test_64_sys01 | 1 + bdshemu_test/basic/test_64_sys01.asm | 4 + bdshemu_test/basic/test_64_sys01.result | 8 + bdshemu_test/basic/test_64_sys02 | 1 + bdshemu_test/basic/test_64_sys02.asm | 4 + bdshemu_test/basic/test_64_sys02.result | 8 + bdshemu_test/basic/test_64_sys03 | 1 + bdshemu_test/basic/test_64_sys03.asm | 4 + bdshemu_test/basic/test_64_sys03.result | 7 + bdshemu_test/test_all.py | 56 + disasmtool/disasmtool.c | 1922 + disasmtool/disasmtool.vcxproj | 217 + disasmtool/disasmtool.vcxproj.filters | 22 + disasmtool_lix/CMakeLists.txt | 172 + disasmtool_lix/Makefile | 39 + disasmtool_lix/disasm.hpp | 84 + disasmtool_lix/disasmtool.cpp | 736 + disasmtool_lix/dumpers.cpp | 1839 + disasmtool_lix/external/argparse.h | 276 + disasmtool_lix/rapidjson.cpp | 1174 + docs/Makefile | 20 + docs/make.bat | 35 + docs/source/conf.py | 53 + docs/source/index.rst | 401 + inc/bddisasm.h | 1454 + inc/bdshemu/bdshemu.h | 279 + inc/constants.h | 1687 + inc/cpuidflags.h | 107 + inc/disasmstatus.h | 57 + inc/disasmtypes.h | 20 + inc/registers.h | 148 + inc/version.h | 12 + isagenerator/Makefile | 4 + isagenerator/README.md | 184 + isagenerator/disasmlib.py | 1349 + isagenerator/generate_tables.py | 1262 + isagenerator/instructions/cpuid.dat | 112 + isagenerator/instructions/flags.dat | 95 + isagenerator/instructions/modes.dat | 78 + isagenerator/instructions/prefixes.dat | 35 + isagenerator/instructions/table_0F.dat | 668 + isagenerator/instructions/table_0F_38.dat | 128 + isagenerator/instructions/table_0F_3A.dat | 68 + isagenerator/instructions/table_3dnow.dat | 28 + isagenerator/instructions/table_base.dat | 445 + isagenerator/instructions/table_evex1.dat | 254 + isagenerator/instructions/table_evex2.dat | 343 + isagenerator/instructions/table_evex3.dat | 120 + isagenerator/instructions/table_fpu.dat | 175 + isagenerator/instructions/table_vex1.dat | 306 + isagenerator/instructions/table_vex2.dat | 212 + isagenerator/instructions/table_vex3.dat | 125 + isagenerator/instructions/table_xop.dat | 193 + isagenerator/isagenerator.vcxproj | 166 + isagenerator/isagenerator.vcxproj.filters | 84 + pydis/README.md | 21 + pydis/_pydis/_pydis.c | 1131 + pydis/_pydis/pydis.c | 34 + pydis/_pydis/pydis.h | 20 + pydis/pydis/__init__.py | 7 + pydis/pydis/__main__.py | 11 + pydis/pydis/__version__.py | 9 + pydis/pydis/app.py | 15 + pydis/pydis/core.py | 52 + pydis/pydis/disasm.py | 71 + pydis/pydis/helpers.py | 156 + pydis/setup.py | 53 + 448 files changed, 686845 insertions(+), 15 deletions(-) create mode 100644 .gitignore create mode 100644 .vsconfig create mode 100644 Makefile create mode 100644 bddisasm.sln create mode 100644 bddisasm/Makefile create mode 100644 bddisasm/bddisasm.c create mode 100644 bddisasm/bddisasm.vcproj create mode 100644 bddisasm/bddisasm.vcxproj create mode 100644 bddisasm/bddisasm.vcxproj.filters create mode 100644 bddisasm/crt.c create mode 100644 bddisasm/include/instructions.h create mode 100644 bddisasm/include/mnemonics.h create mode 100644 bddisasm/include/nd_crt.h create mode 100644 bddisasm/include/prefixes.h create mode 100644 bddisasm/include/table_evex.h create mode 100644 bddisasm/include/table_root.h create mode 100644 bddisasm/include/table_vex.h create mode 100644 bddisasm/include/table_xop.h create mode 100644 bddisasm/include/tabledefs.h create mode 100644 bddisasm_test/README.md create mode 100644 bddisasm_test/amx/amx1_64 create mode 100644 bddisasm_test/amx/amx1_64.asm create mode 100644 bddisasm_test/amx/amx1_64.result create mode 100644 bddisasm_test/avx/avx2_64 create mode 100644 bddisasm_test/avx/avx2_64.asm create mode 100644 bddisasm_test/avx/avx2_64.result create mode 100644 bddisasm_test/avx/avx2gather_64 create mode 100644 bddisasm_test/avx/avx2gather_64.asm create mode 100644 bddisasm_test/avx/avx2gather_64.result create mode 100644 bddisasm_test/avx/avx_64 create mode 100644 bddisasm_test/avx/avx_64.asm create mode 100644 bddisasm_test/avx/avx_64.result create mode 100644 bddisasm_test/avx/f16c_64 create mode 100644 bddisasm_test/avx/f16c_64.asm create mode 100644 bddisasm_test/avx/f16c_64.result create mode 100644 bddisasm_test/avx/fma4_64 create mode 100644 bddisasm_test/avx/fma4_64.asm create mode 100644 bddisasm_test/avx/fma4_64.result create mode 100644 bddisasm_test/avx/fma_64 create mode 100644 bddisasm_test/avx/fma_64.asm create mode 100644 bddisasm_test/avx/fma_64.result create mode 100644 bddisasm_test/avx512/avx512bitalg_64 create mode 100644 bddisasm_test/avx512/avx512bitalg_64.asm create mode 100644 bddisasm_test/avx512/avx512bitalg_64.result create mode 100644 bddisasm_test/avx512/avx512bw_64 create mode 100644 bddisasm_test/avx512/avx512bw_64.asm create mode 100644 bddisasm_test/avx512/avx512bw_64.result create mode 100644 bddisasm_test/avx512/avx512cd_64 create mode 100644 bddisasm_test/avx512/avx512cd_64.asm create mode 100644 bddisasm_test/avx512/avx512cd_64.result create mode 100644 bddisasm_test/avx512/avx512dq_64 create mode 100644 bddisasm_test/avx512/avx512dq_64.asm create mode 100644 bddisasm_test/avx512/avx512dq_64.result create mode 100644 bddisasm_test/avx512/avx512er_64 create mode 100644 bddisasm_test/avx512/avx512er_64.asm create mode 100644 bddisasm_test/avx512/avx512er_64.result create mode 100644 bddisasm_test/avx512/avx512f_64 create mode 100644 bddisasm_test/avx512/avx512f_64.asm create mode 100644 bddisasm_test/avx512/avx512f_64.result create mode 100644 bddisasm_test/avx512/avx512fma_64 create mode 100644 bddisasm_test/avx512/avx512fma_64.asm create mode 100644 bddisasm_test/avx512/avx512fma_64.result create mode 100644 bddisasm_test/avx512/avx512pf_64 create mode 100644 bddisasm_test/avx512/avx512pf_64.asm create mode 100644 bddisasm_test/avx512/avx512pf_64.result create mode 100644 bddisasm_test/avx512/avx512vbmi_64 create mode 100644 bddisasm_test/avx512/avx512vbmi_64.asm create mode 100644 bddisasm_test/avx512/avx512vbmi_64.result create mode 100644 bddisasm_test/avx512/avx512vnni_64 create mode 100644 bddisasm_test/avx512/avx512vnni_64.asm create mode 100644 bddisasm_test/avx512/avx512vnni_64.result create mode 100644 bddisasm_test/basic/address_16 create mode 100644 bddisasm_test/basic/address_16.asm create mode 100644 bddisasm_test/basic/address_16.result create mode 100644 bddisasm_test/basic/address_32 create mode 100644 bddisasm_test/basic/address_32.asm create mode 100644 bddisasm_test/basic/address_32.result create mode 100644 bddisasm_test/basic/address_64 create mode 100644 bddisasm_test/basic/address_64.asm create mode 100644 bddisasm_test/basic/address_64.result create mode 100644 bddisasm_test/basic/aes_64 create mode 100644 bddisasm_test/basic/aes_64.asm create mode 100644 bddisasm_test/basic/aes_64.result create mode 100644 bddisasm_test/basic/basic1_64 create mode 100644 bddisasm_test/basic/basic1_64.asm create mode 100644 bddisasm_test/basic/basic1_64.result create mode 100644 bddisasm_test/basic/basic2_64 create mode 100644 bddisasm_test/basic/basic2_64.asm create mode 100644 bddisasm_test/basic/basic2_64.result create mode 100644 bddisasm_test/basic/bmi_64 create mode 100644 bddisasm_test/basic/bmi_64.asm create mode 100644 bddisasm_test/basic/bmi_64.result create mode 100644 bddisasm_test/basic/branch_16 create mode 100644 bddisasm_test/basic/branch_16.asm create mode 100644 bddisasm_test/basic/branch_16.result create mode 100644 bddisasm_test/basic/branch_32 create mode 100644 bddisasm_test/basic/branch_32.asm create mode 100644 bddisasm_test/basic/branch_32.result create mode 100644 bddisasm_test/basic/branch_64 create mode 100644 bddisasm_test/basic/branch_64.asm create mode 100644 bddisasm_test/basic/branch_64.result create mode 100644 bddisasm_test/basic/cet_64 create mode 100644 bddisasm_test/basic/cet_64.asm create mode 100644 bddisasm_test/basic/cet_64.result create mode 100644 bddisasm_test/basic/enqcmd_64 create mode 100644 bddisasm_test/basic/enqcmd_64.asm create mode 100644 bddisasm_test/basic/enqcmd_64.result create mode 100644 bddisasm_test/basic/fpu_64 create mode 100644 bddisasm_test/basic/fpu_64.asm create mode 100644 bddisasm_test/basic/fpu_64.result create mode 100644 bddisasm_test/basic/gfni_64 create mode 100644 bddisasm_test/basic/gfni_64.asm create mode 100644 bddisasm_test/basic/gfni_64.result create mode 100644 bddisasm_test/basic/invlpgb_64 create mode 100644 bddisasm_test/basic/invlpgb_64.asm create mode 100644 bddisasm_test/basic/invlpgb_64.result create mode 100644 bddisasm_test/basic/misc_16 create mode 100644 bddisasm_test/basic/misc_16.asm create mode 100644 bddisasm_test/basic/misc_16.result create mode 100644 bddisasm_test/basic/misc_32 create mode 100644 bddisasm_test/basic/misc_32.asm create mode 100644 bddisasm_test/basic/misc_32.result create mode 100644 bddisasm_test/basic/misc_64 create mode 100644 bddisasm_test/basic/misc_64.asm create mode 100644 bddisasm_test/basic/misc_64.result create mode 100644 bddisasm_test/basic/mpx_64 create mode 100644 bddisasm_test/basic/mpx_64.asm create mode 100644 bddisasm_test/basic/mpx_64.result create mode 100644 bddisasm_test/basic/prefixes_64 create mode 100644 bddisasm_test/basic/prefixes_64.asm create mode 100644 bddisasm_test/basic/prefixes_64.result create mode 100644 bddisasm_test/basic/sha_64 create mode 100644 bddisasm_test/basic/sha_64.asm create mode 100644 bddisasm_test/basic/sha_64.result create mode 100644 bddisasm_test/basic/snp_64 create mode 100644 bddisasm_test/basic/snp_64.asm create mode 100644 bddisasm_test/basic/snp_64.result create mode 100644 bddisasm_test/basic/stack_16 create mode 100644 bddisasm_test/basic/stack_16.asm create mode 100644 bddisasm_test/basic/stack_16.result create mode 100644 bddisasm_test/basic/stack_32 create mode 100644 bddisasm_test/basic/stack_32.asm create mode 100644 bddisasm_test/basic/stack_32.result create mode 100644 bddisasm_test/basic/stack_64 create mode 100644 bddisasm_test/basic/stack_64.asm create mode 100644 bddisasm_test/basic/stack_64.result create mode 100644 bddisasm_test/basic/svm_64 create mode 100644 bddisasm_test/basic/svm_64.asm create mode 100644 bddisasm_test/basic/svm_64.result create mode 100644 bddisasm_test/basic/system_16 create mode 100644 bddisasm_test/basic/system_16.asm create mode 100644 bddisasm_test/basic/system_16.result create mode 100644 bddisasm_test/basic/system_32 create mode 100644 bddisasm_test/basic/system_32.asm create mode 100644 bddisasm_test/basic/system_32.result create mode 100644 bddisasm_test/basic/system_64 create mode 100644 bddisasm_test/basic/system_64.asm create mode 100644 bddisasm_test/basic/system_64.result create mode 100644 bddisasm_test/basic/tsx_64 create mode 100644 bddisasm_test/basic/tsx_64.asm create mode 100644 bddisasm_test/basic/tsx_64.result create mode 100644 bddisasm_test/basic/vmx_64 create mode 100644 bddisasm_test/basic/vmx_64.asm create mode 100644 bddisasm_test/basic/vmx_64.result create mode 100644 bddisasm_test/simd/3dnow_64 create mode 100644 bddisasm_test/simd/3dnow_64.asm create mode 100644 bddisasm_test/simd/3dnow_64.result create mode 100644 bddisasm_test/simd/mmx_64 create mode 100644 bddisasm_test/simd/mmx_64.asm create mode 100644 bddisasm_test/simd/mmx_64.result create mode 100644 bddisasm_test/simd/sse2_64 create mode 100644 bddisasm_test/simd/sse2_64.asm create mode 100644 bddisasm_test/simd/sse2_64.result create mode 100644 bddisasm_test/simd/sse3_64 create mode 100644 bddisasm_test/simd/sse3_64.asm create mode 100644 bddisasm_test/simd/sse3_64.result create mode 100644 bddisasm_test/simd/sse4_64 create mode 100644 bddisasm_test/simd/sse4_64.asm create mode 100644 bddisasm_test/simd/sse4_64.result create mode 100644 bddisasm_test/special/amx_64 create mode 100644 bddisasm_test/special/amx_64.asm create mode 100644 bddisasm_test/special/amx_64.result create mode 100644 bddisasm_test/special/avx2gather_1_64 create mode 100644 bddisasm_test/special/avx2gather_1_64.asm create mode 100644 bddisasm_test/special/avx2gather_1_64.result create mode 100644 bddisasm_test/special/avx2gather_2_64 create mode 100644 bddisasm_test/special/avx2gather_2_64.asm create mode 100644 bddisasm_test/special/avx2gather_2_64.result create mode 100644 bddisasm_test/special/avx2gather_3_64 create mode 100644 bddisasm_test/special/avx2gather_3_64.asm create mode 100644 bddisasm_test/special/avx2gather_3_64.result create mode 100644 bddisasm_test/special/cr8_32 create mode 100644 bddisasm_test/special/cr8_32.asm create mode 100644 bddisasm_test/special/cr8_32.result create mode 100644 bddisasm_test/special/invalid_32 create mode 100644 bddisasm_test/special/invalid_32.asm create mode 100644 bddisasm_test/special/invalid_32.result create mode 100644 bddisasm_test/special/invalid_64 create mode 100644 bddisasm_test/special/invalid_64.asm create mode 100644 bddisasm_test/special/invalid_64.result create mode 100644 bddisasm_test/special/long_64 create mode 100644 bddisasm_test/special/long_64.asm create mode 100644 bddisasm_test/special/long_64.result create mode 100644 bddisasm_test/special/movcrdr_64 create mode 100644 bddisasm_test/special/movcrdr_64.asm create mode 100644 bddisasm_test/special/movcrdr_64.result create mode 100644 bddisasm_test/special/only_32 create mode 100644 bddisasm_test/special/only_32.asm create mode 100644 bddisasm_test/special/only_32.result create mode 100644 bddisasm_test/special/only_64 create mode 100644 bddisasm_test/special/only_64.asm create mode 100644 bddisasm_test/special/only_64.result create mode 100644 bddisasm_test/test_all.py create mode 100644 bdshemu/Makefile create mode 100644 bdshemu/bdshemu.c create mode 100644 bdshemu/bdshemu.vcxproj create mode 100644 bdshemu/bdshemu.vcxproj.filters create mode 100644 bdshemu_fuzz/Makefile create mode 100644 bdshemu_fuzz/README.md create mode 100644 bdshemu_fuzz/bdshemu_fuzzer.c create mode 100644 bdshemu_fuzz/in-32/test_32_str01 create mode 100644 bdshemu_fuzz/in-32/test_32_str02 create mode 100644 bdshemu_fuzz/in-32/test_32_str03 create mode 100644 bdshemu_fuzz/in-32/test_32_str04 create mode 100644 bdshemu_fuzz/in-32/test_32_sys01 create mode 100644 bdshemu_fuzz/in-32/test_64_basic01 create mode 100644 bdshemu_fuzz/in-32/test_64_basic04 create mode 100644 bdshemu_fuzz/in-32/test_64_basic05 create mode 100644 bdshemu_fuzz/in-32/test_64_basic06 create mode 100644 bdshemu_fuzz/in-32/test_64_basic07 create mode 100644 bdshemu_fuzz/in-32/test_64_basic08 create mode 100644 bdshemu_fuzz/in-32/test_64_basic09 create mode 100644 bdshemu_fuzz/in-32/test_64_branch1 create mode 100644 bdshemu_fuzz/in-32/test_64_branch2 create mode 100644 bdshemu_fuzz/in-32/test_64_branch3 create mode 100644 bdshemu_fuzz/in-32/test_64_branch4 create mode 100644 bdshemu_fuzz/in-32/test_64_div create mode 100644 bdshemu_fuzz/in-32/test_64_flags create mode 100644 bdshemu_fuzz/in-32/test_64_loadrip01 create mode 100644 bdshemu_fuzz/in-32/test_64_loadrip02 create mode 100644 bdshemu_fuzz/in-32/test_64_loadrip03 create mode 100644 bdshemu_fuzz/in-32/test_64_mov create mode 100644 bdshemu_fuzz/in-32/test_64_nopsled01 create mode 100644 bdshemu_fuzz/in-32/test_64_nopsled02 create mode 100644 bdshemu_fuzz/in-32/test_64_selfwrite02 create mode 100644 bdshemu_fuzz/in-32/test_64_selfwrite03 create mode 100644 bdshemu_fuzz/in-32/test_64_string create mode 100644 bdshemu_fuzz/in-32/test_64_sys01 create mode 100644 bdshemu_fuzz/in-32/test_64_sys02 create mode 100644 bdshemu_fuzz/in-32/test_64_sys03 create mode 100644 bdshemu_fuzz/in-64/test_32_str01 create mode 100644 bdshemu_fuzz/in-64/test_32_str02 create mode 100644 bdshemu_fuzz/in-64/test_32_str04 create mode 100644 bdshemu_fuzz/in-64/test_32_sys01 create mode 100644 bdshemu_fuzz/in-64/test_64_basic01 create mode 100644 bdshemu_fuzz/in-64/test_64_basic02 create mode 100644 bdshemu_fuzz/in-64/test_64_basic03 create mode 100644 bdshemu_fuzz/in-64/test_64_basic04 create mode 100644 bdshemu_fuzz/in-64/test_64_basic05 create mode 100644 bdshemu_fuzz/in-64/test_64_basic06 create mode 100644 bdshemu_fuzz/in-64/test_64_basic07 create mode 100644 bdshemu_fuzz/in-64/test_64_basic08 create mode 100644 bdshemu_fuzz/in-64/test_64_branch1 create mode 100644 bdshemu_fuzz/in-64/test_64_branch2 create mode 100644 bdshemu_fuzz/in-64/test_64_branch3 create mode 100644 bdshemu_fuzz/in-64/test_64_branch4 create mode 100644 bdshemu_fuzz/in-64/test_64_div create mode 100644 bdshemu_fuzz/in-64/test_64_flags create mode 100644 bdshemu_fuzz/in-64/test_64_loadrip01 create mode 100644 bdshemu_fuzz/in-64/test_64_loadrip02 create mode 100644 bdshemu_fuzz/in-64/test_64_loadrip03 create mode 100644 bdshemu_fuzz/in-64/test_64_mov create mode 100644 bdshemu_fuzz/in-64/test_64_nopsled01 create mode 100644 bdshemu_fuzz/in-64/test_64_nopsled02 create mode 100644 bdshemu_fuzz/in-64/test_64_selfwrite02 create mode 100644 bdshemu_fuzz/in-64/test_64_selfwrite03 create mode 100644 bdshemu_fuzz/in-64/test_64_string create mode 100644 bdshemu_fuzz/in-64/test_64_sys01 create mode 100644 bdshemu_fuzz/in-64/test_64_sys02 create mode 100644 bdshemu_fuzz/in-64/test_64_sys03 create mode 100644 bdshemu_test/README.md create mode 100644 bdshemu_test/basic/test_32_str01 create mode 100644 bdshemu_test/basic/test_32_str01.asm create mode 100644 bdshemu_test/basic/test_32_str01.result create mode 100644 bdshemu_test/basic/test_32_str02 create mode 100644 bdshemu_test/basic/test_32_str02.asm create mode 100644 bdshemu_test/basic/test_32_str02.result create mode 100644 bdshemu_test/basic/test_32_str03 create mode 100644 bdshemu_test/basic/test_32_str03.asm create mode 100644 bdshemu_test/basic/test_32_str03.result create mode 100644 bdshemu_test/basic/test_32_str04 create mode 100644 bdshemu_test/basic/test_32_str04.asm create mode 100644 bdshemu_test/basic/test_32_str04.result create mode 100644 bdshemu_test/basic/test_32_sys01 create mode 100644 bdshemu_test/basic/test_32_sys01.asm create mode 100644 bdshemu_test/basic/test_32_sys01.result create mode 100644 bdshemu_test/basic/test_64_basic01 create mode 100644 bdshemu_test/basic/test_64_basic01.asm create mode 100644 bdshemu_test/basic/test_64_basic01.result create mode 100644 bdshemu_test/basic/test_64_basic02 create mode 100644 bdshemu_test/basic/test_64_basic02.asm create mode 100644 bdshemu_test/basic/test_64_basic02.result create mode 100644 bdshemu_test/basic/test_64_basic03 create mode 100644 bdshemu_test/basic/test_64_basic03.asm create mode 100644 bdshemu_test/basic/test_64_basic03.result create mode 100644 bdshemu_test/basic/test_64_basic04 create mode 100644 bdshemu_test/basic/test_64_basic04.asm create mode 100644 bdshemu_test/basic/test_64_basic04.result create mode 100644 bdshemu_test/basic/test_64_basic05 create mode 100644 bdshemu_test/basic/test_64_basic05.asm create mode 100644 bdshemu_test/basic/test_64_basic05.result create mode 100644 bdshemu_test/basic/test_64_basic06 create mode 100644 bdshemu_test/basic/test_64_basic06.asm create mode 100644 bdshemu_test/basic/test_64_basic06.result create mode 100644 bdshemu_test/basic/test_64_basic07 create mode 100644 bdshemu_test/basic/test_64_basic07.asm create mode 100644 bdshemu_test/basic/test_64_basic07.result create mode 100644 bdshemu_test/basic/test_64_basic08 create mode 100644 bdshemu_test/basic/test_64_basic08.asm create mode 100644 bdshemu_test/basic/test_64_basic08.result create mode 100644 bdshemu_test/basic/test_64_basic09 create mode 100644 bdshemu_test/basic/test_64_basic09.asm create mode 100644 bdshemu_test/basic/test_64_basic09.result create mode 100644 bdshemu_test/basic/test_64_branch1 create mode 100644 bdshemu_test/basic/test_64_branch1.asm create mode 100644 bdshemu_test/basic/test_64_branch1.result create mode 100644 bdshemu_test/basic/test_64_branch2 create mode 100644 bdshemu_test/basic/test_64_branch2.asm create mode 100644 bdshemu_test/basic/test_64_branch2.result create mode 100644 bdshemu_test/basic/test_64_branch3 create mode 100644 bdshemu_test/basic/test_64_branch3.asm create mode 100644 bdshemu_test/basic/test_64_branch3.result create mode 100644 bdshemu_test/basic/test_64_branch4 create mode 100644 bdshemu_test/basic/test_64_branch4.asm create mode 100644 bdshemu_test/basic/test_64_branch4.result create mode 100644 bdshemu_test/basic/test_64_div create mode 100644 bdshemu_test/basic/test_64_div.asm create mode 100644 bdshemu_test/basic/test_64_div.result create mode 100644 bdshemu_test/basic/test_64_eicar create mode 100644 bdshemu_test/basic/test_64_eicar.asm create mode 100644 bdshemu_test/basic/test_64_eicar.result create mode 100644 bdshemu_test/basic/test_64_flags create mode 100644 bdshemu_test/basic/test_64_flags.asm create mode 100644 bdshemu_test/basic/test_64_flags.result create mode 100644 bdshemu_test/basic/test_64_loadrip01 create mode 100644 bdshemu_test/basic/test_64_loadrip01.asm create mode 100644 bdshemu_test/basic/test_64_loadrip01.result create mode 100644 bdshemu_test/basic/test_64_loadrip02 create mode 100644 bdshemu_test/basic/test_64_loadrip02.asm create mode 100644 bdshemu_test/basic/test_64_loadrip02.result create mode 100644 bdshemu_test/basic/test_64_loadrip03 create mode 100644 bdshemu_test/basic/test_64_loadrip03.asm create mode 100644 bdshemu_test/basic/test_64_loadrip03.result create mode 100644 bdshemu_test/basic/test_64_moffset create mode 100644 bdshemu_test/basic/test_64_moffset.asm create mode 100644 bdshemu_test/basic/test_64_moffset.result create mode 100644 bdshemu_test/basic/test_64_mov create mode 100644 bdshemu_test/basic/test_64_mov.asm create mode 100644 bdshemu_test/basic/test_64_mov.result create mode 100644 bdshemu_test/basic/test_64_nopsled01 create mode 100644 bdshemu_test/basic/test_64_nopsled01.asm create mode 100644 bdshemu_test/basic/test_64_nopsled01.result create mode 100644 bdshemu_test/basic/test_64_nopsled02 create mode 100644 bdshemu_test/basic/test_64_nopsled02.asm create mode 100644 bdshemu_test/basic/test_64_nopsled02.result create mode 100644 bdshemu_test/basic/test_64_nopsled03 create mode 100644 bdshemu_test/basic/test_64_nopsled03.asm create mode 100644 bdshemu_test/basic/test_64_nopsled03.result create mode 100644 bdshemu_test/basic/test_64_selfwrite01 create mode 100644 bdshemu_test/basic/test_64_selfwrite01.asm create mode 100644 bdshemu_test/basic/test_64_selfwrite01.result create mode 100644 bdshemu_test/basic/test_64_selfwrite02 create mode 100644 bdshemu_test/basic/test_64_selfwrite02.asm create mode 100644 bdshemu_test/basic/test_64_selfwrite02.result create mode 100644 bdshemu_test/basic/test_64_selfwrite03 create mode 100644 bdshemu_test/basic/test_64_selfwrite03.asm create mode 100644 bdshemu_test/basic/test_64_selfwrite03.result create mode 100644 bdshemu_test/basic/test_64_string create mode 100644 bdshemu_test/basic/test_64_string.asm create mode 100644 bdshemu_test/basic/test_64_string.result create mode 100644 bdshemu_test/basic/test_64_sys01 create mode 100644 bdshemu_test/basic/test_64_sys01.asm create mode 100644 bdshemu_test/basic/test_64_sys01.result create mode 100644 bdshemu_test/basic/test_64_sys02 create mode 100644 bdshemu_test/basic/test_64_sys02.asm create mode 100644 bdshemu_test/basic/test_64_sys02.result create mode 100644 bdshemu_test/basic/test_64_sys03 create mode 100644 bdshemu_test/basic/test_64_sys03.asm create mode 100644 bdshemu_test/basic/test_64_sys03.result create mode 100644 bdshemu_test/test_all.py create mode 100644 disasmtool/disasmtool.c create mode 100644 disasmtool/disasmtool.vcxproj create mode 100644 disasmtool/disasmtool.vcxproj.filters create mode 100644 disasmtool_lix/CMakeLists.txt create mode 100644 disasmtool_lix/Makefile create mode 100644 disasmtool_lix/disasm.hpp create mode 100644 disasmtool_lix/disasmtool.cpp create mode 100644 disasmtool_lix/dumpers.cpp create mode 100644 disasmtool_lix/external/argparse.h create mode 100644 disasmtool_lix/rapidjson.cpp create mode 100644 docs/Makefile create mode 100644 docs/make.bat create mode 100644 docs/source/conf.py create mode 100644 docs/source/index.rst create mode 100644 inc/bddisasm.h create mode 100644 inc/bdshemu/bdshemu.h create mode 100644 inc/constants.h create mode 100644 inc/cpuidflags.h create mode 100644 inc/disasmstatus.h create mode 100644 inc/disasmtypes.h create mode 100644 inc/registers.h create mode 100644 inc/version.h create mode 100644 isagenerator/Makefile create mode 100644 isagenerator/README.md create mode 100644 isagenerator/disasmlib.py create mode 100644 isagenerator/generate_tables.py create mode 100644 isagenerator/instructions/cpuid.dat create mode 100644 isagenerator/instructions/flags.dat create mode 100644 isagenerator/instructions/modes.dat create mode 100644 isagenerator/instructions/prefixes.dat create mode 100644 isagenerator/instructions/table_0F.dat create mode 100644 isagenerator/instructions/table_0F_38.dat create mode 100644 isagenerator/instructions/table_0F_3A.dat create mode 100644 isagenerator/instructions/table_3dnow.dat create mode 100644 isagenerator/instructions/table_base.dat create mode 100644 isagenerator/instructions/table_evex1.dat create mode 100644 isagenerator/instructions/table_evex2.dat create mode 100644 isagenerator/instructions/table_evex3.dat create mode 100644 isagenerator/instructions/table_fpu.dat create mode 100644 isagenerator/instructions/table_vex1.dat create mode 100644 isagenerator/instructions/table_vex2.dat create mode 100644 isagenerator/instructions/table_vex3.dat create mode 100644 isagenerator/instructions/table_xop.dat create mode 100644 isagenerator/isagenerator.vcxproj create mode 100644 isagenerator/isagenerator.vcxproj.filters create mode 100644 pydis/README.md create mode 100644 pydis/_pydis/_pydis.c create mode 100644 pydis/_pydis/pydis.c create mode 100644 pydis/_pydis/pydis.h create mode 100644 pydis/pydis/__init__.py create mode 100644 pydis/pydis/__main__.py create mode 100644 pydis/pydis/__version__.py create mode 100644 pydis/pydis/app.py create mode 100644 pydis/pydis/core.py create mode 100644 pydis/pydis/disasm.py create mode 100644 pydis/pydis/helpers.py create mode 100644 pydis/setup.py diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..587ccdd --- /dev/null +++ b/.gitignore @@ -0,0 +1,65 @@ +syntax: glob +# Object files +*.o +*.obj + +# Libraries +*.lib +*.a + +# Shared objects (inc. Windows DLLs) +*.dll +*.so +*.so.* +*.dylib + +# Executables +*.exe +*.out +*.app +*.sys + +#VS/WDK project files +*.ilk +*.pdb +*.user +*.mac +*.res +*.log +build*_*_*.xml +*.suo +*.sdf +*.opensdf +*.tlog +*.ipch +vc*.idb +/bin/ +/_intdir/ +*.aps +*.vcxprojResolveAssemblyReference.cache +*.manifest +*.unsuccessfulbuild +UpgradeLog*.XML +_UpgradeReport_Files/* +*.sbr + +#other files +*.pyc +.*.swp +*.pyd +pydis/pydis.egg-info/ +pydis/build/ +pydis/dist/ +.vs/ + +disasmtool_lix/build +.dir-locals.el +.ccls-cache/ +compile_commands.json +.gdb_history +pydis/.eggs +bdshemu_fuzz/out +bdshemu_fuzz/shfuzz +bdshemu_fuzz/out-32 +bdshemu_fuzz/out-64 +docs/build diff --git a/.vsconfig b/.vsconfig new file mode 100644 index 0000000..d5d7d24 --- /dev/null +++ b/.vsconfig @@ -0,0 +1,21 @@ +{ + "version": "1.0", + "components": [ + "Microsoft.VisualStudio.Component.CoreEditor", + "Microsoft.VisualStudio.Workload.CoreEditor", + "Microsoft.VisualStudio.Component.Roslyn.Compiler", + "Microsoft.Component.MSBuild", + "Microsoft.VisualStudio.Component.TextTemplating", + "Microsoft.VisualStudio.Component.IntelliCode", + "Microsoft.VisualStudio.Component.VC.CoreIde", + "Microsoft.VisualStudio.Component.VC.Tools.x86.x64", + "Microsoft.VisualStudio.Component.Windows10SDK.18362", + "Microsoft.VisualStudio.Component.VC.Redist.14.Latest", + "Microsoft.VisualStudio.ComponentGroup.NativeDesktop.Core", + "Microsoft.VisualStudio.ComponentGroup.WebToolsExtensions.CMake", + "Microsoft.VisualStudio.Component.VC.CMake.Project", + "Microsoft.VisualStudio.Component.VC.ATL", + "Microsoft.VisualStudio.Workload.NativeDesktop", + "Microsoft.VisualStudio.Component.VC.Runtimes.x86.x64.Spectre" + ] +} \ No newline at end of file diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..c575013 --- /dev/null +++ b/Makefile @@ -0,0 +1,22 @@ +.PHONY: all bddisasm bdshemu + +all: bddisasm bdshemu + +bddisasm: + @$(MAKE) --no-print-directory -C bddisasm + @$(MAKE) --no-print-directory RELEASE=y -C bddisasm + +bdshemu: + @$(MAKE) --no-print-directory -C bdshemu + @$(MAKE) --no-print-directory RELEASE=y -C bdshemu + +clean: + @$(MAKE) --no-print-directory -C bddisasm clean + @$(MAKE) --no-print-directory RELEASE=y -C bddisasm clean + @$(MAKE) --no-print-directory -C bdshemu clean + @$(MAKE) --no-print-directory RELEASE=y -C bdshemu clean + +install: + @$(MAKE) --no-print-directory RELEASE=y -C bddisasm install + @$(MAKE) --no-print-directory RELEASE=y -C bdshemu install + \ No newline at end of file diff --git a/README.md b/README.md index 8483244..1b3ed01 100644 --- a/README.md +++ b/README.md @@ -1,30 +1,30 @@ # The Bitdefender disassembler -The Bitdefender disassembler is a lightweight, x86/x64 only instruction decoder. It is easy to integrate, easy to work with, it has no external dependencies, it is thread-safe, it allocates no memory at all, it works in virtually any environment (we use it inside user, kernel, hypervisor, on both Windows and Linux environments), and it provides lots of info regarding the decoded instructions, such as: operands (both explicit and implicit), access mode for each operand, CPUID feature flag, flags access, etc. +The Bitdefender disassembler (bddisasm) is a lightweight, x86/x64 only instruction decoder. It is easy to integrate, easy to work with, it has no external dependencies, it is thread-safe, it allocates no memory at all, it works in virtually any environment (we use it inside user, kernel, hypervisor, on both Windows and Linux environments), and it provides lots of info regarding the decoded instructions, such as: operands (both explicit and implicit), access mode for each operand, CPUID feature flag, flags access, etc. More examples and info about the project can be found on the official documentation: [Bitdefender disassembler](http://bddisasm.readthedocs.io) ## Projects -1. disasm - this is the main disassembler project. In order to use the Bitdefender disassembler, all you have to do is build this project, and link with the output library. The only headers you need are located inside the inc folder. +1. bddisasm - this is the main disassembler project. In order to use the Bitdefender disassembler, all you have to do is build this project, and link with the output library. The only headers you need are located inside the `inc` folder. -2. shemu - this project makes use of the main disasm lib in order to build a simple, lightweight, fast, instructions emulator, designated to target shellcodes. This project is also integrated inside the disasmtool, so you can -emulate raw binary files, and see their output. Note that this simple emulator supports basic x86/x64 instructions, and does not support emulating any kind of API call. +2. bdshemu - this project makes use of the main bddisasm lib in order to build a simple, lightweight, fast, instructions emulator, designated to target shellcodes. This project is also integrated inside the disasmtool, so you can +emulate raw binary files, and see their output. Note that this simple emulator supports basic x86/x64 instructions, and does not support emulating any kind of API call. In addition, the only supported memory accesses are inside the shellcode itself, and on the emulated stack. -3. isagenerator - this project contains the instruction definitions and the scripts required to generate the disassembly tables. If you wish to add support for a new instruction, this is the place. This project will automatically generate several header files (instructions.h, mnemonics.h, constants.h, table_\*.h), so please make sure you don't manually edit any of these files. +3. isagenerator - this project contains the instruction definitions and the scripts required to generate the disassembly tables. If you wish to add support for a new instruction, this is the place. This project will automatically generate several header files (instructions.h, mnemonics.h, constants.h, table_\*.h), so please make sure you don't manually edit any of these files. You will need Python 3 to run the generation scripts. -4. disasmtool - this project is a command line disassembler tool, used mainly as an example of how to integrate the disasm lib. +4. disasmtool - this project is a command line disassembler tool, used mainly as an example of how to integrate the bddisasm and bdshemu libraries. 5. disasmtool_lix - like disasmtool, but for Linux. -6. pydis - this is the Python binding for the disasm project. +6. pydis - this is the Python binding for the bddisasm project. You will need Python 3 for this. ## Objectives The main objectives of this disassembler are: 1. Lighetweight - it's written in C, with no external dependencies, no memory allocated, and thread safe by design. -2. Fast - less than 300 CPU clocks on a Intel Core i7-8650U per decoded instruction. -3. Resilient - tested against internal fuzzers and the famous [mishegos](https://github.com/trailofbits/mishegos) tool -4. Easy to work with - just include the main header file, disasm.h, link with the disasmlib library, and call the NdDecode API! +2. Fast - less than 300 CPU clocks on an Intel Core i7-8650U per decoded instruction (more than 7M instructions per second). +3. Resilient - tested against internal fuzzers and the famous [mishegos](https://github.com/trailofbits/mishegos) tool. +4. Easy to work with - just include the main header file, bddisasm.h, link with the bddisasm library, and call the NdDecode API! 5. Complete - support every x86 instruction to date, and provide as much information as possible. ## Build @@ -35,13 +35,14 @@ In order to build the projects on Windows you need: * [Visual Studio 2019](https://visualstudio.microsoft.com/vs/) with the Desktop development with C++ workload. * [Windows SDK 10.0.18362.0](https://developer.microsoft.com/en-us/windows/downloads/windows-10-sdk/). +* [Python 3.7 or newer](https://www.python.org/downloads/release/python-373/) When you first open the solution Visual Studio should prompt you to install any missing components. -This should be enough to build disasm, disasmtool and shemu for the Debug and Release configurations. +This should be enough to build bddisasm, disasmtool and bdshemu for the Debug and Release configurations. For the DebugKernel and ReleaseKernel configurations, [WDK 1903](https://go.microsoft.com/fwlink/?linkid=2085767) is needed, alongside the Windows Driver Kit Visual Studio extension (the WDK installer should take care of this). -For isagenerator, python is needed. +For isagenerator, Python 3 is needed. Building any of the projects is done directly from Visual Studio. @@ -60,16 +61,35 @@ For disasmtool_lix you also need: * cmake 3.12 or newer * [RapidJSON](https://github.com/Tencent/rapidjson/) -In order to build disasm and shemu run `make` in the root of the repository. The results will be placed in the bin directory. +In order to build bddisasm and bdshemu run `make` in the root of the repository. The results will be placed in the bin directory. In order to build disasmtool_lix go to the disasmtool_lix directory and run `make`. The results will be in the bin directory in the disasmtool_lix/build directory. ## Example -Working with disasm is very easy. Decoding and printing the disassembly of an instruction is quick & simple: +Working with bddisasm is very easy. Decoding and printing the disassembly of an instruction is quick & simple: ```c -#include "disasm.h" +#include +#include "bddisasm/disasmtypes.h" +#include "bddisasm/bddisasm.h" + +int nd_vsnprintf_s( + char *buffer, + size_t sizeOfBuffer, + size_t count, + const char *format, + va_list argptr + ) +{ + return vsnprintf(buffer, sizeOfBuffer, format, argptr); +} + +void* nd_memset(void *s, int c, size_t n) +{ + return memset(s, c, n); +} + int main() { diff --git a/bddisasm.sln b/bddisasm.sln new file mode 100644 index 0000000..e716baa --- /dev/null +++ b/bddisasm.sln @@ -0,0 +1,87 @@ + +Microsoft Visual Studio Solution File, Format Version 12.00 +# Visual Studio Version 16 +VisualStudioVersion = 16.0.29519.87 +MinimumVisualStudioVersion = 10.0.40219.1 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "disasmtool", "disasmtool\disasmtool.vcxproj", "{94F1B65D-3305-4CCB-9DF1-50B56900D867}" + ProjectSection(ProjectDependencies) = postProject + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA} = {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "bddisasm", "bddisasm\bddisasm.vcxproj", "{3653AA19-048B-410E-B5C4-FF78E1D84C12}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "bdshemu", "bdshemu\bdshemu.vcxproj", "{3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}" + ProjectSection(ProjectDependencies) = postProject + {3653AA19-048B-410E-B5C4-FF78E1D84C12} = {3653AA19-048B-410E-B5C4-FF78E1D84C12} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "isagenerator", "isagenerator\isagenerator.vcxproj", "{0E9D2957-34FA-40EE-B4B2-0D008D2FE317}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|Win32 = Debug|Win32 + Debug|x64 = Debug|x64 + DebugKernel|Win32 = DebugKernel|Win32 + DebugKernel|x64 = DebugKernel|x64 + Release|Win32 = Release|Win32 + Release|x64 = Release|x64 + ReleaseKernel|Win32 = ReleaseKernel|Win32 + ReleaseKernel|x64 = ReleaseKernel|x64 + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {94F1B65D-3305-4CCB-9DF1-50B56900D867}.Debug|Win32.ActiveCfg = Debug|Win32 + {94F1B65D-3305-4CCB-9DF1-50B56900D867}.Debug|x64.ActiveCfg = Debug|x64 + {94F1B65D-3305-4CCB-9DF1-50B56900D867}.DebugKernel|Win32.ActiveCfg = Debug|Win32 + {94F1B65D-3305-4CCB-9DF1-50B56900D867}.DebugKernel|x64.ActiveCfg = Debug|x64 + {94F1B65D-3305-4CCB-9DF1-50B56900D867}.Release|Win32.ActiveCfg = Release|Win32 + {94F1B65D-3305-4CCB-9DF1-50B56900D867}.Release|x64.ActiveCfg = Release|x64 + {94F1B65D-3305-4CCB-9DF1-50B56900D867}.ReleaseKernel|Win32.ActiveCfg = Release|Win32 + {94F1B65D-3305-4CCB-9DF1-50B56900D867}.ReleaseKernel|x64.ActiveCfg = Release|x64 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.Debug|Win32.ActiveCfg = Debug|Win32 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.Debug|Win32.Build.0 = Debug|Win32 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.Debug|x64.ActiveCfg = Debug|x64 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.Debug|x64.Build.0 = Debug|x64 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.DebugKernel|Win32.ActiveCfg = DebugKernel|Win32 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.DebugKernel|Win32.Build.0 = DebugKernel|Win32 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.DebugKernel|x64.ActiveCfg = DebugKernel|x64 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.DebugKernel|x64.Build.0 = DebugKernel|x64 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.Release|Win32.ActiveCfg = Release|Win32 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.Release|Win32.Build.0 = Release|Win32 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.Release|x64.ActiveCfg = Release|x64 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.Release|x64.Build.0 = Release|x64 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.ReleaseKernel|Win32.ActiveCfg = ReleaseKernel|Win32 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.ReleaseKernel|Win32.Build.0 = ReleaseKernel|Win32 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.ReleaseKernel|x64.ActiveCfg = ReleaseKernel|x64 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.ReleaseKernel|x64.Build.0 = ReleaseKernel|x64 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.Debug|Win32.ActiveCfg = Debug|Win32 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.Debug|Win32.Build.0 = Debug|Win32 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.Debug|x64.ActiveCfg = Debug|x64 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.Debug|x64.Build.0 = Debug|x64 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.DebugKernel|Win32.ActiveCfg = DebugKernel|Win32 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.DebugKernel|Win32.Build.0 = DebugKernel|Win32 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.DebugKernel|x64.ActiveCfg = DebugKernel|x64 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.DebugKernel|x64.Build.0 = DebugKernel|x64 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.Release|Win32.ActiveCfg = Release|Win32 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.Release|Win32.Build.0 = Release|Win32 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.Release|x64.ActiveCfg = Release|x64 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.Release|x64.Build.0 = Release|x64 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.ReleaseKernel|Win32.ActiveCfg = ReleaseKernel|Win32 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.ReleaseKernel|Win32.Build.0 = ReleaseKernel|Win32 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.ReleaseKernel|x64.ActiveCfg = ReleaseKernel|x64 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.ReleaseKernel|x64.Build.0 = ReleaseKernel|x64 + {0E9D2957-34FA-40EE-B4B2-0D008D2FE317}.Debug|Win32.ActiveCfg = Debug|Win32 + {0E9D2957-34FA-40EE-B4B2-0D008D2FE317}.Debug|x64.ActiveCfg = Debug|x64 + {0E9D2957-34FA-40EE-B4B2-0D008D2FE317}.DebugKernel|Win32.ActiveCfg = Debug|Win32 + {0E9D2957-34FA-40EE-B4B2-0D008D2FE317}.DebugKernel|x64.ActiveCfg = Debug|x64 + {0E9D2957-34FA-40EE-B4B2-0D008D2FE317}.Release|Win32.ActiveCfg = Release|Win32 + {0E9D2957-34FA-40EE-B4B2-0D008D2FE317}.Release|x64.ActiveCfg = Release|x64 + {0E9D2957-34FA-40EE-B4B2-0D008D2FE317}.ReleaseKernel|Win32.ActiveCfg = Release|Win32 + {0E9D2957-34FA-40EE-B4B2-0D008D2FE317}.ReleaseKernel|x64.ActiveCfg = Release|x64 + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection + GlobalSection(ExtensibilityGlobals) = postSolution + SolutionGuid = {E950FA16-07C1-4613-8328-906BC10C7C02} + EndGlobalSection +EndGlobal diff --git a/bddisasm/Makefile b/bddisasm/Makefile new file mode 100644 index 0000000..cbfd9d4 --- /dev/null +++ b/bddisasm/Makefile @@ -0,0 +1,123 @@ +.PHONY: clean + +SRC_FILES := crt.c bddisasm.c + +OBJECTS := $(SRC_FILES:.c=.o) + +INCLUDES := -Iinclude -I../inc + +ifeq ($(PLATFORM),) + PLATFORM := x64 +endif + +ifeq ($(RELEASE),y) + CONFIGURATION := Release +else + CONFIGURATION := Debug +endif + +ifeq ($(PREFIX),) + PREFIX := /usr/local +endif + +DEFINES := -D_LIB -DAMD64 + +INT_DIR := ../_intdir/bddisasm/$(PLATFORM)/$(CONFIGURATION) + +DEP_DIR := $(INT_DIR)/.d + +OUT_DIR := ../bin/$(PLATFORM)/$(CONFIGURATION) + +OBJECTS_PATH := $(addprefix $(INT_DIR)/, $(OBJECTS)) + +LIB_NAME := libbddisasm.a + +WARNINGS_ENABLE := -Wall -Wextra -Wshadow -Wstrict-overflow \ + -Wframe-larger-than=3072 -Wstack-usage=3072 + +WARNINGS_DISABLE := -Wno-missing-field-initializers \ + -Wno-missing-braces \ + -Wno-unused-function \ + -Wno-unused-variable \ + -Wno-unknown-pragmas \ + -Wno-format \ + -Wno-multichar + +# Some warnings are compiler-specific, some version-specific +ifeq (,$(findstring clang,$(CC))) + CC_VERSION_MAJOR = $(shell $(CC) -dumpversion | cut -d '.' -f1) + CC_VERSION_GT_4 = $(shell [ $(CC_VERSION_MAJOR) -gt 4 ] && echo true) + CC_VERSION_GT_5 = $(shell [ $(CC_VERSION_MAJOR) -gt 5 ] && echo true) + + ifeq (true,$(CC_VERSION_GT_4)) + WARNINGS_DISABLE += -Wno-incompatible-pointer-types + endif + + ifeq (true,$(CC_VERSION_GT_5)) + WARNINGS_ENABLE += -Wshift-overflow=2 \ + -Wnull-dereference \ + -Wduplicated-cond + endif +else + WARNINGS_DISABLE += -Wno-typedef-redefinition \ + -Wno-missing-braces \ + -Wno-incompatible-pointer-types \ + -Wno-missing-field-initializers +endif + +DEPFLAGS = -MT $@ -MMD -MP -MF $(DEP_DIR)/$*.Td + +CFLAGS = -pipe -c -std=c11 -fpic -fno-strict-aliasing \ + -D_REENTRANT -fstack-protector -ffunction-sections -fdata-sections \ + $(WARNINGS_ENABLE) $(WARNINGS_DISABLE) $(DEFINES) $(INCLUDES) + +ifeq ($(RELEASE),y) + CFLAGS += -Ofast -g3 -DNDEBUG -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=1 +else + CFLAGS += -O0 -g3 -D_DEBUG -DDEBUG +endif + +all: $(LIB_NAME) + +# Here it will link the objects created below in the final .a +$(LIB_NAME): $(OBJECTS_PATH) + @mkdir -p $(OUT_DIR) + @ar rcs $(OUT_DIR)/$(LIB_NAME) $(OBJECTS_PATH) + @echo Disasm library in $(OUT_DIR)/$(LIB_NAME) + +# We need to mkdir inside the rule, so each subfolder gets created, +# and avoiding conflicts: +# ./linux/example.c => $(INT_DIR)/linux/example.o +# ./example.c => $(INT_DIR)/example.o +$(INT_DIR)/%.o: %.c $(DEP_DIR)/%.d + @mkdir -p $(dir $@) + @mkdir -p $(dir $(DEP_DIR)/$<) >/dev/null + @echo $< + @$(CC) $(DEPFLAGS) $(CFLAGS) -c $< -o $@ + @mv -f $(DEP_DIR)/$*.Td $(DEP_DIR)/$*.d + +# So 'make' won't fail if the dependecy file doesn't exist +$(DEP_DIR)/%.d: ; + +# Don't delete the dependecy files +.PRECIOUS: $(DEP_DIR)/%.d + +# Include all the dependecy files (this will trigger a rebuild if a header is changed) +-include $(patsubst %,$(DEP_DIR)/%.d,$(basename $(SRC_FILES))) + +clean_lib_file: + @rm $(OUT_DIR)/$(LIB_NAME) 2>/dev/null ||: + +clean_int_dir: + @rm -r $(INT_DIR) 2>/dev/null ||: + +clean_dep_dir: + @rm -r $(DEP_DIR) 2>/dev/null ||: + +clean: clean_lib_file clean_int_dir clean_dep_dir + +install: all + install -d $(DESTDIR)$(PREFIX)/lib/ + install -m 644 $(OUT_DIR)/$(LIB_NAME) $(DESTDIR)$(PREFIX)/lib/ + install -d $(DESTDIR)$(PREFIX)/include/bddisasm + cp -r ../inc/* $(DESTDIR)$(PREFIX)/include/bddisasm/ \ No newline at end of file diff --git a/bddisasm/bddisasm.c b/bddisasm/bddisasm.c new file mode 100644 index 0000000..34f0f31 --- /dev/null +++ b/bddisasm/bddisasm.c @@ -0,0 +1,5050 @@ +/* + * Copyright (c) 2020 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +#include "include/nd_crt.h" +#include "../inc/bddisasm.h" + +// The table definitions. +#include "include/tabledefs.h" + +// Handy macros. +#define RET_EQ(x, y, z) if ((x) == (y)) { return (z); } +#define RET_GE(x, y, z) if ((x) >= (y)) { return (z); } +#define RET_GT(x, y, z) if ((x) > (y)) { return (z); } + + +static const char *gReg8Bit[] = +{ + "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", +}; + +static const char *gReg8Bit64[] = +{ + "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", + "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b", +}; + +static const char *gReg16Bit[] = +{ + "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", + "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w", +}; + +static const char *gReg32Bit[] = +{ + "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", + "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d", +}; + +static const char *gReg64Bit[] = +{ + "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" +}; + +static const char *gRegFpu[] = +{ + "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7", +}; + +static const char *gRegMmx[] = +{ + "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", +}; + +static const char *gRegControl[] = +{ + "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", + "cr8", "cr9", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15", +}; + +static const char *gRegDebug[] = +{ + "dr0", "dr1", "dr2", "dr3", "dr4", "dr5", "dr6", "dr7", + "dr8", "dr9", "dr10", "dr11", "dr12", "dr13", "dr14", "dr15", +}; + +static const char *gRegTest[] = +{ + "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", + "tr8", "tr9", "tr10", "tr11", "tr12", "tr13", "tr14", "tr15", +}; + +static const char *gRegXmm[] = +{ + "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", + "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", + "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", + "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", +}; + +static const char *gRegYmm[] = +{ + "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", + "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", + "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", + "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31" +}; + +static const char *gRegZmm[] = +{ + "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", + "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", + "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", + "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", +}; + +static const char *gRegSeg[] = +{ + "es", "cs", "ss", "ds", "fs", "gs", "segr6", "segr7", +}; + +static const char *gRegBound[] = +{ + "bnd0", "bnd1", "bnd2", "bnd3", +}; + +static const char *gRegMask[] = +{ + "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", +}; + +static const char *gRegTile[] = +{ + "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7", +}; + +static const char *gConditionCodes[] = +{ + "EQ", "LT", "LE", "UNORD", "NEQ", "NLT", "NLE", "ORD", + "EQ_UQ", "NGE", "NGT", "false", "NEQ_OQ", "GE", "GT", "TRUE", + "EQ_OS", "LT_OQ", "LE_OQ", "UNORD_S", "NEQ_US", "NLT_UQ", "NLE_UQ", "ORD_S", + "EQ_US", "NGE_UQ", "NGT_UQ", "FALSE_OS", "NEQ_OS", "GE_OQ", "GT_OQ", "TRUE_US", +}; + +static const char *gEmbeddedRounding[] = +{ + "rn", "rd", "ru", "rz", +}; + +static const uint16_t gOperandMap[] = +{ + ND_OPE_D, // ND_OPT_A + ND_OPE_V, // ND_OPT_B + ND_OPE_R, // ND_OPT_C + ND_OPE_R, // ND_OPT_D + ND_OPE_M, // ND_OPT_E + ND_OPE_S, // ND_OPT_F + ND_OPE_R, // ND_OPT_G + ND_OPE_V, // ND_OPT_H + ND_OPE_I, // ND_OPT_I + ND_OPE_D, // ND_OPT_J + ND_OPE_S, // ND_OPT_K + ND_OPE_L, // ND_OPT_L + ND_OPE_M, // ND_OPT_M + ND_OPE_M, // ND_OPT_N + ND_OPE_D, // ND_OPT_O + ND_OPE_R, // ND_OPT_P + ND_OPE_M, // ND_OPT_Q + ND_OPE_M, // ND_OPT_R + ND_OPE_R, // ND_OPT_S + ND_OPE_R, // ND_OPT_T + ND_OPE_M, // ND_OPT_U + ND_OPE_R, // ND_OPT_V + ND_OPE_M, // ND_OPT_W + ND_OPE_S, // ND_OPT_X + ND_OPE_S, // ND_OPT_Y + ND_OPE_O, // ND_OPT_Z + ND_OPE_R, // ND_OPT_rB + ND_OPE_M, // ND_OPT_mB + ND_OPE_R, // ND_OPT_rK + ND_OPE_V, // ND_OPT_vK + ND_OPE_M, // ND_OPT_mK + ND_OPE_A, // ND_OPT_aK + ND_OPE_R, // ND_OPT_mR + ND_OPE_M, // ND_OPT_mM + ND_OPE_R, // ND_OPT_rT + ND_OPE_M, // ND_OPT_mT + ND_OPE_V, // ND_OPT_vT + ND_OPE_1, // ND_OPT_1 + + ND_OPE_S, // ND_OPT_RIP + ND_OPE_S, // ND_OPT_MXCSR + ND_OPE_S, // ND_OPT_PKRU + ND_OPE_S, // ND_OPT_SSP + + ND_OPE_S, // ND_OPT_GPR_AH + ND_OPE_S, // ND_OPT_GPR_rAX + ND_OPE_S, // ND_OPT_GPR_rCX + ND_OPE_S, // ND_OPT_GPR_rDX + ND_OPE_S, // ND_OPT_GPR_rBX + ND_OPE_S, // ND_OPT_GPR_rSP + ND_OPE_S, // ND_OPT_GPR_rBP + ND_OPE_S, // ND_OPT_GPR_rSI + ND_OPE_S, // ND_OPT_GPR_rDI + ND_OPE_S, // ND_OPT_GPR_rR11 + + ND_OPE_S, // ND_OPT_SEG_CS + ND_OPE_S, // ND_OPT_SEG_SS + ND_OPE_S, // ND_OPT_SEG_DS + ND_OPE_S, // ND_OPT_SEG_ES + ND_OPE_S, // ND_OPT_SEG_FS + ND_OPE_S, // ND_OPT_SEG_GS + + ND_OPE_S, // ND_OPT_FPU_ST0 + ND_OPE_M, // ND_OPT_FPU_STX + + ND_OPE_S, // ND_OPT_SSE_XMM0 + + ND_OPE_S, // ND_OPT_MEM_rBX_AL (as used by XLAT) + ND_OPE_S, // ND_OPT_MEM_rDI (as used by masked moves) + ND_OPE_S, // ND_OPT_MEM_SHS + + ND_OPE_S, // ND_OPT_CR_0 + ND_OPE_S, // ND_OPT_IDTR + ND_OPE_S, // ND_OPT_GDTR + ND_OPE_S, // ND_OPT_LDTR + ND_OPE_S, // ND_OPT_TR + + ND_OPE_S, // ND_OPT_X87_CONTROL + ND_OPE_S, // ND_OPT_X87_TAG + ND_OPE_S, // ND_OPT_X87_STATUS + + ND_OPE_E, // ND_OPT_MSR + ND_OPE_E, // ND_OPT_XCR + ND_OPE_S, // ND_OPT_MSR_TSC + ND_OPE_S, // ND_OPT_MSR_TSCAUX + ND_OPE_S, // ND_OPT_MSR_SEIP + ND_OPE_S, // ND_OPT_MSR_SESP + ND_OPE_S, // ND_OPT_MSR_SCS + ND_OPE_S, // ND_OPT_MSR_STAR + ND_OPE_S, // ND_OPT_MSR_LSTAR + ND_OPE_S, // ND_OPT_MSR_FMASK + ND_OPE_S, // ND_OPT_MSR_FSBASE + ND_OPE_S, // ND_OPT_MSR_GSBASE + ND_OPE_S, // ND_OPT_MSR_KGSBASE + ND_OPE_S, // ND_OPT_XCR_0 + ND_OPE_S, // ND_OPT_REG_BANK + ND_OPE_S, // Unused. +}; + + +static const uint8_t gDispsizemap16[4][8] = +{ + { 0, 0, 0, 0, 0, 0, 2, 0 }, + { 1, 1, 1, 1, 1, 1, 1, 1 }, + { 2, 2, 2, 2, 2, 2, 2, 2 }, + { 0, 0, 0, 0, 0, 0, 0, 0 }, +}; + +static const uint8_t gDispsizemap[4][8] = +{ + { 0, 0, 0, 0, 0, 4, 0, 0 }, + { 1, 1, 1, 1, 1, 1, 1, 1 }, + { 4, 4, 4, 4, 4, 4, 4, 4 }, + { 0, 0, 0, 0, 0, 0, 0, 0 }, +}; + + +// +// NdGetVersion +// +void +NdGetVersion( + uint32_t *Major, + uint32_t *Minor, + uint32_t *Revision, + char **BuildDate, + char **BuildTime + ) +{ + if (NULL != Major) + { + *Major = DISASM_VERSION_MAJOR; + } + + if (NULL != Minor) + { + *Minor = DISASM_VERSION_MINOR; + } + + if (NULL != Revision) + { + *Revision = DISASM_VERSION_REVISION; + } + + if (NULL != BuildDate) + { + *BuildDate = __DATE__; + } + + if (NULL != BuildTime) + { + *BuildTime = __TIME__; + } +} + +#ifndef KERNEL_MODE +// +// NdSprintf +// +static NDSTATUS +NdSprintf( + char *Destination, + size_t DestinationSize, + const char *Formatstring, + ... + ) +// +// Wrapper on vsnprintf. +// +{ + int res; + va_list args; + + if (NULL == Destination) + { + return ND_STATUS_INVALID_PARAMETER; + } + + if (NULL == Formatstring) + { + return ND_STATUS_INVALID_PARAMETER; + } + + nd_memzero(Destination, DestinationSize); + + va_start(args, Formatstring); + + // _vsnprintf is used instead of the more secure _vsnprintf_s because the mini-Petru supports just + // the unsecured version, and we depend on it. + res = nd_vsnprintf_s(Destination, DestinationSize, DestinationSize - 1, Formatstring, args); + + va_end(args); + + if ((res < 0) || ((size_t)res >= DestinationSize - 1)) + { + return ND_STATUS_BUFFER_OVERFLOW; + } + + return ND_STATUS_SUCCESS; +} +#else +#define NdSprintf(Destination, DestinationSize, Formatstring, ...) RtlStringCbPrintfA(Destination, \ + DestinationSize, \ + Formatstring, \ + __VA_ARGS__); +#endif + + +// +// NdFetchData +// +static uint64_t +NdFetchData( + const uint8_t *Buffer, + uint8_t Size + ) +{ + return (4 == Size) ? ND_FETCH_32(Buffer) : + (1 == Size) ? ND_FETCH_8(Buffer) : + (8 == Size) ? ND_FETCH_64(Buffer) : + (2 == Size) ? ND_FETCH_16(Buffer) : + 0; +} + + +// +// NdFetchXop +// +static NDSTATUS +NdFetchXop( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size + ) +{ + // Offset points to the 0x8F XOP prefix. + // One more byte has to follow, the modrm or the second XOP byte. + RET_GT((size_t)Offset + 2, Size, ND_STATUS_BUFFER_TOO_SMALL); + + if (((Code[Offset + 1] & 0x1F) >= 8)) + { + // XOP found, make sure the third byte is here. + RET_GT((size_t)Offset + 3, Size, ND_STATUS_BUFFER_TOO_SMALL); + + // Make sure we don't have any other prefix. + if (Instrux->HasOpSize || Instrux->HasRepnzXacquireBnd || Instrux->HasRepRepzXrelease || Instrux->HasRex) + { + return ND_STATUS_XOP_WITH_PREFIX; + } + + // Fill in XOP info. + Instrux->HasXop = true; + Instrux->EncMode = ND_ENCM_XOP; + Instrux->Xop.Xop[0] = Code[Offset]; + Instrux->Xop.Xop[1] = Code[Offset + 1]; + Instrux->Xop.Xop[2] = Code[Offset + 2]; + + Instrux->Exs.w = Instrux->Xop.w; + Instrux->Exs.r = ~Instrux->Xop.r; + Instrux->Exs.x = ~Instrux->Xop.x; + Instrux->Exs.b = ~Instrux->Xop.b; + Instrux->Exs.l = Instrux->Xop.l; + Instrux->Exs.v = ~Instrux->Xop.v; + Instrux->Exs.m = Instrux->Xop.m; + Instrux->Exs.p = Instrux->Xop.p; + + // if we are in non 64 bit mode, we must make sure that none of the extended registers are being addressed. + if (Instrux->DefCode != ND_CODE_64) + { + // Xop.R and Xop.X must be 1 (inverted). + if ((Instrux->Exs.r | Instrux->Exs.x) == 1) + { + return ND_STATUS_INVALID_ENCODING_IN_MODE; + } + + // Xop.V must be less than 8. + if ((Instrux->Exs.v & 0x8) == 0x8) + { + return ND_STATUS_INVALID_ENCODING_IN_MODE; + } + + // Xop.B is ignored, so we force it to 0. + Instrux->Exs.b = 0; + } + + // Update Instrux length & offset, and make sure we don't exceed 15 bytes. + Instrux->Length += 3; + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdFetchVex2 +// +static NDSTATUS +NdFetchVex2( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size + ) +{ + // One more byte has to follow, the modrm or the second VEX byte. + RET_GT((size_t)Offset + 2, Size, ND_STATUS_BUFFER_TOO_SMALL); + + // VEX is available only in 32 & 64 bit mode. + if ((ND_CODE_64 == Instrux->DefCode) || ((Code[Offset + 1] & 0xC0) == 0xC0)) + { + // Make sure we don't have any other prefix. + if (Instrux->HasOpSize || Instrux->HasRepnzXacquireBnd || + Instrux->HasRepRepzXrelease || Instrux->HasRex || Instrux->HasLock) + { + return ND_STATUS_VEX_WITH_PREFIX; + } + + // Fill in VEX2 info. + Instrux->VexMode = ND_VEXM_2B; + Instrux->HasVex = true; + Instrux->EncMode = ND_ENCM_VEX; + Instrux->Vex2.Vex[0] = Code[Offset]; + Instrux->Vex2.Vex[1] = Code[Offset + 1]; + + Instrux->Exs.m = 1; // For VEX2 instructions, always use the second table. + Instrux->Exs.r = ~Instrux->Vex2.r; + Instrux->Exs.v = ~Instrux->Vex2.v; + Instrux->Exs.l = Instrux->Vex2.l; + Instrux->Exs.p = Instrux->Vex2.p; + + // Update Instrux length & offset, and make sure we don't exceed 15 bytes. + Instrux->Length += 2; + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdFetchVex3 +// +static NDSTATUS +NdFetchVex3( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size + ) +{ + // One more byte has to follow, the modrm or the second VEX byte. + RET_GT((size_t)Offset + 2, Size, ND_STATUS_BUFFER_TOO_SMALL); + + // VEX is available only in 32 & 64 bit mode. + if ((ND_CODE_64 == Instrux->DefCode) || ((Code[Offset + 1] & 0xC0) == 0xC0)) + { + // VEX found, make sure the third byte is here. + RET_GT((size_t)Offset + 3, Size, ND_STATUS_BUFFER_TOO_SMALL); + + // Make sure we don't have any other prefix. + if (Instrux->HasOpSize || Instrux->HasRepnzXacquireBnd || + Instrux->HasRepRepzXrelease || Instrux->HasRex || Instrux->HasLock) + { + return ND_STATUS_VEX_WITH_PREFIX; + } + + // Fill in XOP info. + Instrux->VexMode = ND_VEXM_3B; + Instrux->HasVex = true; + Instrux->EncMode = ND_ENCM_VEX; + Instrux->Vex3.Vex[0] = Code[Offset]; + Instrux->Vex3.Vex[1] = Code[Offset + 1]; + Instrux->Vex3.Vex[2] = Code[Offset + 2]; + + Instrux->Exs.r = ~Instrux->Vex3.r; + Instrux->Exs.x = ~Instrux->Vex3.x; + Instrux->Exs.b = ~Instrux->Vex3.b; + Instrux->Exs.m = Instrux->Vex3.m; + Instrux->Exs.w = Instrux->Vex3.w; + Instrux->Exs.v = ~Instrux->Vex3.v; + Instrux->Exs.l = Instrux->Vex3.l; + Instrux->Exs.p = Instrux->Vex3.p; + + // Do validations in case of VEX outside 64 bits. + if (Instrux->DefCode != ND_CODE_64) + { + // Vex.R and Vex.X have been tested by the initial if. + + // Vex.vvvv must be less than 8. + if ((Instrux->Exs.v & 0x8) == 0x8) + { + return ND_STATUS_INVALID_ENCODING_IN_MODE; + } + + // Vex.B is ignored, so we force it to 0. + Instrux->Exs.b = 0; + } + + // Update Instrux length & offset, and make sure we don't exceed 15 bytes. + Instrux->Length += 3; + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdFetchEvex +// +static NDSTATUS +NdFetchEvex( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size + ) +{ + // One more byte has to follow, the modrm or the second VEX byte. + RET_GT((size_t)Offset + 2, Size, ND_STATUS_BUFFER_TOO_SMALL); + + if ((ND_CODE_64 != Instrux->DefCode) && ((Code[Offset + 1] & 0xC0) != 0xC0)) + { + // BOUND instruction in non-64 bit mode, not EVEX. + return ND_STATUS_SUCCESS; + } + + // EVEX found, make sure all the bytes are present. At least 4 bytes in total must be present. + RET_GT((size_t)Offset + 4, Size, ND_STATUS_BUFFER_TOO_SMALL); + + // This is EVEX. + Instrux->HasEvex = true; + Instrux->EncMode = ND_ENCM_EVEX; + Instrux->Evex.Evex[0] = Code[Offset + 0]; + Instrux->Evex.Evex[1] = Code[Offset + 1]; + Instrux->Evex.Evex[2] = Code[Offset + 2]; + Instrux->Evex.Evex[3] = Code[Offset + 3]; + + // Legacy prefixes are not accepted with EVEX. + if (Instrux->HasOpSize || Instrux->HasRepnzXacquireBnd || Instrux->HasRepRepzXrelease || Instrux->HasRex) + { + return ND_STATUS_EVEX_WITH_PREFIX; + } + + // Do the opcode independent checks. Opcode dependent checks are done when decoding each + if (Instrux->Evex.zero != 0 || Instrux->Evex.one != 1 || Instrux->Evex.m == 0) + { + return ND_STATUS_INVALID_ENCODING; + } + + // Fill in the generic extension bits + Instrux->Exs.r = ~Instrux->Evex.r; + Instrux->Exs.x = ~Instrux->Evex.x; + Instrux->Exs.b = ~Instrux->Evex.b; + Instrux->Exs.rp = ~Instrux->Evex.rp; + Instrux->Exs.m = Instrux->Evex.m; + Instrux->Exs.w = Instrux->Evex.w; + Instrux->Exs.v = ~Instrux->Evex.v; + Instrux->Exs.vp = ~Instrux->Evex.vp; + Instrux->Exs.p = Instrux->Evex.p; + Instrux->Exs.z = Instrux->Evex.z; + Instrux->Exs.l = Instrux->Evex.l; + Instrux->Exs.bm = Instrux->Evex.bm; + Instrux->Exs.k = Instrux->Evex.a; + + // Do EVEX validations outside 64 bits mode. + if (ND_CODE_64 != Instrux->DefCode) + { + // Evex.R and Evex.X must be 1. If they're not, we have BOUND instruction. This is checkked in the + // first if. Note that they are inverted inside the Evex prefix. + Instrux->Exs.r = 0; + Instrux->Exs.x = 0; + + // Evex.B is ignored, so we force it to 0. + Instrux->Exs.b = 0; + + // Evex.R' is ignored, so we force it to 0. + Instrux->Exs.rp = 0; + + // High bit inside Evex.VVVV is ignored, so we force it to 0. + Instrux->Exs.v &= 0x7; + + // Evex.V' is ignored. + Instrux->Exs.vp = 0; + } + + // Update Instrux length & offset, and make sure we don't exceed 15 bytes. + Instrux->Length += 4; + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdFetchPrefixes +// +static NDSTATUS +NdFetchPrefixes( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size + ) +{ + NDSTATUS status; + bool morePrefixes; + uint8_t prefix; + + morePrefixes = true; + + while (morePrefixes) + { + morePrefixes = false; + + RET_GT((size_t)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL); + + prefix = Code[Offset]; + + // Speedup: if the current byte is not a prefix of any kind, leave now. This will be the case most of the times. + if (ND_PREF_CODE_NONE == gPrefixesMap[prefix]) + { + status = ND_STATUS_SUCCESS; + goto done_prefixes; + } + + if (ND_PREF_CODE_STANDARD == gPrefixesMap[prefix]) + { + switch (prefix) + { + case ND_PREFIX_G0_LOCK: + Instrux->HasLock = true; + morePrefixes = true; + break; + case ND_PREFIX_G1_REPE_REPZ: + Instrux->Rep = ND_PREFIX_G1_REPE_REPZ; + Instrux->HasRepRepzXrelease = true; + morePrefixes = true; + break; + case ND_PREFIX_G1_REPNE_REPNZ: + Instrux->Rep = ND_PREFIX_G1_REPNE_REPNZ; + Instrux->HasRepnzXacquireBnd = true; + morePrefixes = true; + break; + case ND_PREFIX_G2_SEG_CS: + case ND_PREFIX_G2_SEG_SS: + case ND_PREFIX_G2_SEG_DS: + case ND_PREFIX_G2_SEG_ES: + case ND_PREFIX_G2_SEG_FS: + case ND_PREFIX_G2_SEG_GS: + if (ND_CODE_64 == Instrux->DefCode) + { + // Do not overwrite FS/GS with ES/CS/DS/SS in 64 bit mode. In 64 bit mode, only FS/GS overrides + // are considered. + if (prefix == ND_PREFIX_G2_SEG_FS || prefix == ND_PREFIX_G2_SEG_GS) + { + Instrux->Seg = prefix; + Instrux->HasSeg = true; + } + } + else + { + Instrux->Seg = prefix; + Instrux->HasSeg = true; + } + if (prefix == ND_PREFIX_G2_BR_TAKEN || prefix == ND_PREFIX_G2_BR_NOT_TAKEN) + { + Instrux->Bhint = prefix; + Instrux->HasSeg = true; + } + morePrefixes = true; + break; + case ND_PREFIX_G3_OPERAND_SIZE: + Instrux->HasOpSize = true; + morePrefixes = true; + break; + case ND_PREFIX_G4_ADDR_SIZE: + Instrux->HasAddrSize = true; + morePrefixes = true; + break; + default: + break; + } + } + + // REX must precede the opcode byte. However, if one or more other prefixes are present, the instruction + // will still decode & execute properly, but REX will be ignored. + if (morePrefixes && Instrux->HasRex) + { + Instrux->HasRex = false; + Instrux->Rex.Rex = 0; + Instrux->Exs.w = 0; + Instrux->Exs.r = 0; + Instrux->Exs.x = 0; + Instrux->Exs.b = 0; + } + + // Check for REX. + if ((ND_CODE_64 == Instrux->DefCode) && (ND_PREF_CODE_REX == gPrefixesMap[prefix])) + { + Instrux->HasRex = true; + Instrux->Rex.Rex = prefix; + Instrux->Exs.w = Instrux->Rex.w; + Instrux->Exs.r = Instrux->Rex.r; + Instrux->Exs.x = Instrux->Rex.x; + Instrux->Exs.b = Instrux->Rex.b; + morePrefixes = true; + } + + // We have found prefixes, update the instruction length and the current offset. + if (morePrefixes) + { + Instrux->Length++, Offset++; + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + } + } + + // We must have at least one more free byte after the prefixes, which will be either the opcode, either + // XOP/VEX/EVEX/MVEX prefix. + RET_GT((size_t)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL); + + // Try to match a XOP/VEX/EVEX/MVEX prefix. + if (ND_PREF_CODE_EX == gPrefixesMap[Code[Offset]]) + { + // Check for XOP + if (Code[Offset] == ND_PREFIX_XOP) + { + status = NdFetchXop(Instrux, Code, Offset, Size); + if (!ND_SUCCESS(status)) + { + return status; + } + } + else if (Code[Offset] == ND_PREFIX_VEX_2B) + { + status = NdFetchVex2(Instrux, Code, Offset, Size); + if (!ND_SUCCESS(status)) + { + return status; + } + } + else if (Code[Offset] == ND_PREFIX_VEX_3B) + { + status = NdFetchVex3(Instrux, Code, Offset, Size); + if (!ND_SUCCESS(status)) + { + return status; + } + } + else if (Code[Offset] == ND_PREFIX_EVEX) + { + status = NdFetchEvex(Instrux, Code, Offset, Size); + if (!ND_SUCCESS(status)) + { + return status; + } + } + else + { + return ND_STATUS_INVALID_INSTRUX; + } + } + else + { + Instrux->EncMode = ND_ENCM_LEGACY; + } + +done_prefixes: + // The total length of the instruction is the total length of the prefixes right now. + Instrux->PrefLength = Instrux->OpOffset = Instrux->Length; + + return ND_STATUS_SUCCESS; +} + + +// +// NdFetchOpcode +// +static NDSTATUS +NdFetchOpcode( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size + ) +{ + // At least one byte must be available, for the fetched opcode. + RET_GT((size_t)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL); + + Instrux->OpCodeBytes[Instrux->OpLength++] = Code[Offset]; + + Instrux->Length++; + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdFetchModrm +// +static NDSTATUS +NdFetchModrm( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size + ) +{ + // At least one byte must be available, for the modrm byte. + RET_GT((size_t)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL); + + // If we get called, we assume we have ModRM. + Instrux->HasModRm = true; + + // Fetch the ModRM byte & update the offset and the instruction length. + Instrux->ModRm.ModRm = Code[Offset]; + Instrux->ModRmOffset = Offset; + + Instrux->Length++, Offset++; + + // Make sure we don't exceed the maximum instruction length. + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdFetchModrmAndSib +// +static NDSTATUS +NdFetchModrmAndSib( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size + ) +{ + // At least one byte must be available, for the modrm byte. + RET_GT((size_t)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL); + + // If we get called, we assume we have ModRM. + Instrux->HasModRm = true; + + // Fetch the ModRM byte & update the offset and the instruction length. + Instrux->ModRm.ModRm = Code[Offset]; + Instrux->ModRmOffset = Offset; + + Instrux->Length++, Offset++; + + // Make sure we don't exceed the maximum instruction length. + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + + // If needed, fetch the SIB. + if ((Instrux->ModRm.rm == REG_RSP) && (Instrux->ModRm.mod != 3) && (Instrux->AddrMode != ND_ADDR_16)) + { + // At least one more byte must be available, for the sib. + RET_GT((size_t)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL); + + // SIB present. + Instrux->HasSib = true; + + Instrux->Sib.Sib = Code[Offset]; + Instrux->Length++; + + // Make sure we don't exceed the maximum instruction length. + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdFetchDisplacement +// +static NDSTATUS +NdFetchDisplacement( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size + ) +// +// Will decode the displacement from the instruction. Will fill in extracted information in Instrux, +// and will update the instruction length. +// +{ + uint8_t displSize; + + displSize = 0; + + if (ND_ADDR_16 == Instrux->AddrMode) + { + displSize = gDispsizemap16[Instrux->ModRm.mod][Instrux->ModRm.rm]; + } + else + { + displSize = gDispsizemap[Instrux->ModRm.mod][Instrux->HasSib ? Instrux->Sib.base : Instrux->ModRm.rm]; + } + + if (0 != displSize) + { + static const uint32_t signMask[4] = { 0x80, 0x8000, 0, 0x80000000 }; + + // Make sure enough buffer space is available. + RET_GT((size_t)Offset + displSize, Size, ND_STATUS_BUFFER_TOO_SMALL); + + // If we get here, we have displacement. + Instrux->HasDisp = true; + + Instrux->Displacement = (uint32_t)NdFetchData(Code + Offset, displSize); + Instrux->SignDisp = (Instrux->Displacement & signMask[displSize - 1]) ? true : false; + + // Fill in displacement info. + Instrux->DispLength = displSize; + Instrux->DispOffset = Offset; + Instrux->Length += displSize; + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdFetchAddress +// +static NDSTATUS +NdFetchAddress( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size, + uint8_t AddressSize + ) +{ + //. Make sure the + RET_GT((size_t)Offset + AddressSize, Size, ND_STATUS_BUFFER_TOO_SMALL); + + Instrux->HasAddr = true; + Instrux->AddrLength = AddressSize; + Instrux->AddrOffset = Offset; + + Instrux->Address.Ip = (uint32_t)NdFetchData(Code + Offset, Instrux->AddrLength - 2); + Instrux->Address.Cs = (uint16_t)NdFetchData(Code + Offset + Instrux->AddrLength - 2, 2); + + Instrux->Length += Instrux->AddrLength; + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdFetchImmediate +// +static NDSTATUS +NdFetchImmediate( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size, + uint8_t ImmediateSize + ) +{ + uint64_t imm; + + RET_GT((size_t)Offset + ImmediateSize, Size, ND_STATUS_BUFFER_TOO_SMALL); + + imm = NdFetchData(Code + Offset, ImmediateSize); + + if (Instrux->HasImm2) + { + Instrux->HasImm3 = true; + Instrux->Imm3Length = ImmediateSize; + Instrux->Imm3Offset = Offset; + Instrux->Immediate3 = (uint8_t)imm; + } + else if (Instrux->HasImm1) + { + Instrux->HasImm2 = true; + Instrux->Imm2Length = ImmediateSize; + Instrux->Imm2Offset = Offset; + Instrux->Immediate2 = (uint8_t)imm; + } + else + { + Instrux->HasImm1 = true; + Instrux->Imm1Length = ImmediateSize; + Instrux->Imm1Offset = Offset; + Instrux->Immediate1 = imm; + } + + Instrux->Length += ImmediateSize; + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdFetchRelativeOffset +// +static NDSTATUS +NdFetchRelativeOffset( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size, + uint8_t RelOffsetSize + ) +{ + // Make sure we don't outrun the buffer. + RET_GT((size_t)Offset + RelOffsetSize, Size, ND_STATUS_BUFFER_TOO_SMALL); + + Instrux->HasRelOffs = true; + Instrux->RelOffsLength = RelOffsetSize; + Instrux->RelOffsOffset = Offset; + + Instrux->RelativeOffset = (uint32_t)NdFetchData(Code + Offset, RelOffsetSize); + + Instrux->Length += RelOffsetSize; + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdFetchMoffset +// +static NDSTATUS +NdFetchMoffset( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size, + uint8_t MoffsetSize + ) +{ + RET_GT((size_t)Offset + MoffsetSize, Size, ND_STATUS_BUFFER_TOO_SMALL); + + Instrux->HasMoffset = true; + Instrux->MoffsetLength = MoffsetSize; + Instrux->MoffsetOffset = Offset; + + Instrux->Moffset = NdFetchData(Code + Offset, MoffsetSize); + + Instrux->Length += MoffsetSize; + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdFetchSseImmediate +// +static NDSTATUS +NdFetchSseImmediate( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size, + uint8_t SseImmSize + ) +{ + RET_GT((size_t)Offset + SseImmSize, Size, ND_STATUS_BUFFER_TOO_SMALL); + + Instrux->HasSseImm = true; + Instrux->SseImmOffset = Offset; + Instrux->SseImmediate = *(Code + Offset); + + Instrux->Length += SseImmSize; + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdGetSegOverride +// +static uint8_t +NdGetSegOverride( + INSTRUX *Instrux, + uint8_t DefaultSeg + ) +{ + // In 64 bit mode, the segment override is ignored, except for FS and GS. + if ((Instrux->DefCode == ND_CODE_64) && + (Instrux->Seg != ND_PREFIX_G2_SEG_FS) && + (Instrux->Seg != ND_PREFIX_G2_SEG_GS)) + { + return DefaultSeg; + } + + switch (Instrux->Seg) + { + case ND_PREFIX_G2_SEG_CS: + return REG_CS; + case ND_PREFIX_G2_SEG_DS: + return REG_DS; + case ND_PREFIX_G2_SEG_ES: + return REG_ES; + case ND_PREFIX_G2_SEG_SS: + return REG_SS; + case ND_PREFIX_G2_SEG_FS: + return REG_FS; + case ND_PREFIX_G2_SEG_GS: + return REG_GS; + default: + return DefaultSeg; + } +} + + +// +// NdGetCompDispSize +// +static uint8_t +NdGetCompDispSize( + const INSTRUX *Instrux, + uint32_t MemSize + ) +{ + static const uint8_t fvszLut[2][2][4] = + { + { { 16, 32, 64, 0 }, { 4, 4, 4, 0 }, }, + { { 16, 32, 64, 0 }, { 8, 8, 8, 0 }, }, + }; + + static const uint8_t hvszLut[2][4] = { { 8, 16, 32, 0 }, { 4, 4, 4, 0 }, }; + static const uint8_t dupszLut[4] = { 8, 32, 64, 0 }; + static const uint8_t fvmszLut[4] = { 16, 32, 64, 0 }; + static const uint8_t hvmszLut[4] = { 8, 16, 32, 0 }; + static const uint8_t qvmszLut[4] = { 4, 8, 16, 0 }; + static const uint8_t ovmszLut[4] = { 2, 4, 8, 0 }; + + switch (Instrux->TupleType) + { + case ND_TUPLE_FV: + return fvszLut[Instrux->Exs.w][Instrux->Exs.bm][Instrux->Exs.l]; + case ND_TUPLE_HV: + return hvszLut[Instrux->Exs.bm][Instrux->Exs.l]; + case ND_TUPLE_DUP: + return dupszLut[Instrux->Exs.l]; + case ND_TUPLE_FVM: + return fvmszLut[Instrux->Exs.l]; + case ND_TUPLE_HVM: + return hvmszLut[Instrux->Exs.l]; + case ND_TUPLE_QVM: + return qvmszLut[Instrux->Exs.l]; + case ND_TUPLE_OVM: + return ovmszLut[Instrux->Exs.l]; + case ND_TUPLE_M128: + return 16; + case ND_TUPLE_T1S8: + return 1; + case ND_TUPLE_T1S16: + return 2; + case ND_TUPLE_T1S: + return Instrux->Exs.w ? 8 : 4; + case ND_TUPLE_T1F: + return (uint8_t)MemSize; + case ND_TUPLE_T2: + return Instrux->Exs.w ? 16 : 8; + case ND_TUPLE_T4: + return Instrux->Exs.w ? 32 : 16; + case ND_TUPLE_T8: + return 32; + case ND_TUPLE_T1_4X: + return 16; + default: + // Default - we assume byte granularity for memory accesses, therefore, no scaling will be done. + return 1; + } +} + + +// +// NdParseOperand +// +static NDSTATUS +NdParseOperand( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size, + uint32_t Index, + uint64_t Specifier + ) +{ + NDSTATUS status; + PND_OPERAND operand; + uint8_t opt, ops, opf, opd, opb; + ND_REG_SIZE vsibRegSize; + uint8_t vsibIndexSize, vsibIndexCount; + ND_OPERAND_SIZE size, bcstSize; + bool width; + + // pre-init + status = ND_STATUS_SUCCESS; + vsibRegSize = 0; + vsibIndexSize = vsibIndexCount = 0; + size = bcstSize = 0; + + // Get actual width. + width = Instrux->Exs.w && !(Instrux->Attributes & ND_FLAG_WIG); + + // Get operand components. + opt = ND_OP_TYPE(Specifier); + ops = ND_OP_SIZE(Specifier); + opf = ND_OP_FLAGS(Specifier); + opd = ND_OP_DECORATORS(Specifier); + opb = ND_OP_BLOCK(Specifier); + + // Get a pointer to our op. + operand = &Instrux->Operands[Index]; + + // Fill in the flags. + operand->Flags.Flags = opf & 0xF; + + // Store operand access modes. + operand->Access.Access = opf >> 4; + + + // + // Fill in operand size. + // + switch (ops) + { + case ND_OPS_asz: + // Size given by the address mode. + size = 2 << Instrux->AddrMode; + break; + + case ND_OPS_ssz: + // Size given by the stack mode. + size = 2 << Instrux->DefStack; + break; + + case ND_OPS_0: + // No memory access. 0 operand size. + size = 0; + break; + + case ND_OPS_b: + // Byte, regardless of operand-size attribute. + size = ND_SIZE_8BIT; + break; + + case ND_OPS_w: + // Word, regardless of operand-size attribute. + size = ND_SIZE_16BIT; + break; + + case ND_OPS_d: + // Dword, regardless of operand-size attribute. + size = ND_SIZE_32BIT; + break; + + case ND_OPS_q: + // Qword, regardless of operand-size attribute. + size = ND_SIZE_64BIT; + break; + + case ND_OPS_dq: + // Double-Qword, regardless of operand-size attribute. + size = ND_SIZE_128BIT; + break; + + case ND_OPS_qq: + // Quad-Quadword (256-bits), regardless of operand-size attribute. + size = ND_SIZE_256BIT; + break; + + case ND_OPS_oq: + // Octo-Quadword (512-bits), regardless of operand-size attribute. + size = ND_SIZE_512BIT; + break; + + case ND_OPS_fa: + // 80 bits packed BCD. + size = ND_SIZE_80BIT; + break; + + case ND_OPS_fw: + // 16 bits real number. + size = ND_SIZE_16BIT; + break; + + case ND_OPS_fd: + // 32 bit real number. + size = ND_SIZE_32BIT; + break; + + case ND_OPS_fq: + // 64 bit real number. + size = ND_SIZE_64BIT; + break; + + case ND_OPS_ft: + // 80 bit real number. + size = ND_SIZE_80BIT; + break; + + case ND_OPS_fe: + // 14 bytes or 28 bytes FPU environment. + size = (Instrux->EfOpMode == ND_OPSZ_16) ? ND_SIZE_112BIT : ND_SIZE_224BIT; + break; + + case ND_OPS_fs: + // 94 bytes or 108 bytes FPU state. + size = (Instrux->EfOpMode == ND_OPSZ_16) ? ND_SIZE_752BIT : ND_SIZE_864BIT; + break; + + case ND_OPS_rx: + // 512 bytes extended state. + size = ND_SIZE_4096BIT; + break; + + case ND_OPS_cl: + // The size of one cache line. + size = ND_SIZE_CACHE_LINE; + break; + + case ND_OPS_v: + // Word, doubleword or quadword (in 64-bit mode), depending on operand-size attribute. + { + static const uint8_t szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT }; + + size = szLut[Instrux->EfOpMode]; + } + break; + + case ND_OPS_y: + // Doubleword or quadword (in 64-bit mode), depending on operand-size attribute. + { + static const uint8_t szLut[3] = { ND_SIZE_32BIT, ND_SIZE_32BIT, ND_SIZE_64BIT }; + + size = szLut[Instrux->EfOpMode]; + } + break; + + case ND_OPS_yf: + // Always uint64_t in 64 bit mode and uint32_t in 16/32 bit mode. + { + static const uint8_t szLut[3] = { ND_SIZE_32BIT, ND_SIZE_32BIT, ND_SIZE_64BIT }; + + size = szLut[Instrux->DefCode]; + } + break; + + case ND_OPS_z: + // Word for 16-bit operand-size or double word for 32 or 64-bit operand-size. + { + static const uint8_t szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_32BIT }; + + size = szLut[Instrux->EfOpMode]; + } + break; + + case ND_OPS_a: + // Two one-word operands in memory or two double-word operands in memory, + // depending on operand-size attribute (used only by the BOUND instruction). + { + static const uint8_t szLut[3] = { ND_SIZE_16BIT * 2, ND_SIZE_32BIT * 2, 0 }; + + if (Instrux->DefCode > ND_CODE_32) + { + return ND_STATUS_INVALID_INSTRUX; + } + + size = szLut[Instrux->EfOpMode]; + } + break; + + case ND_OPS_c: + // Byte or word, depending on operand-size attribute. + switch (Instrux->DefCode) + { + case ND_CODE_16: + size = Instrux->HasOpSize ? ND_SIZE_16BIT : ND_SIZE_8BIT; + break; + case ND_CODE_32: + size = Instrux->HasOpSize ? ND_SIZE_16BIT : ND_SIZE_32BIT; + break; + case ND_CODE_64: + size = ND_SIZE_64BIT; + break; + default: + return ND_STATUS_INVALID_INSTRUX; + } + break; + + case ND_OPS_p: + // 32-bit, 48-bit, or 80-bit pointer, depending on operand-size attribute. + { + static const uint8_t szLut[3] = { ND_SIZE_32BIT, ND_SIZE_48BIT, ND_SIZE_80BIT }; + + size = szLut[Instrux->EfOpMode]; + } + break; + + case ND_OPS_s: + // 6-byte or 10-byte pseudo-descriptor. + { + static const uint8_t szLut[3] = { ND_SIZE_48BIT, ND_SIZE_48BIT, ND_SIZE_80BIT }; + + size = szLut[Instrux->DefCode]; + } + break; + + case ND_OPS_l: + // 64 bit in 16 or 32 bit mode, 128 bit in long mode. Used by BNDMOV instruction. + { + static const uint8_t szLut[3] = { ND_SIZE_64BIT, ND_SIZE_64BIT, ND_SIZE_128BIT }; + + size = szLut[Instrux->DefCode]; + } + break; + + case ND_OPS_x: + // dq, qq or oq based on the operand-size attribute. + { + static const uint8_t szLut[3] = { ND_SIZE_128BIT, ND_SIZE_256BIT, ND_SIZE_512BIT }; + + size = szLut[Instrux->EfVecMode]; + } + break; + + case ND_OPS_n: + // 128, 256 or 512 bit, depending on vector length. + { + static const uint8_t szLut[3] = { ND_SIZE_128BIT, ND_SIZE_256BIT, ND_SIZE_512BIT }; + + size = szLut[Instrux->EfVecMode]; + } + break; + + case ND_OPS_u: + // 256 or 512 bit, depending on vector length. + { + static const uint8_t szLut[3] = { 0, ND_SIZE_256BIT, ND_SIZE_512BIT }; + + if (ND_VECM_128 == Instrux->EfVecMode) + { + return ND_STATUS_INVALID_INSTRUX; + } + + size = szLut[Instrux->EfVecMode]; + } + break; + + case ND_OPS_e: + // eighth = word or dword or qword + { + static const uint8_t szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT }; + + size = szLut[Instrux->EfVecMode]; + } + break; + + case ND_OPS_f: + // fourth = dword or qword or oword + { + static const uint8_t szLut[3] = { ND_SIZE_32BIT, ND_SIZE_64BIT, ND_SIZE_128BIT }; + + size = szLut[Instrux->EfVecMode]; + } + break; + + case ND_OPS_h: + // half = qword or oword or yword + { + static const uint8_t szLut[3] = { ND_SIZE_64BIT, ND_SIZE_128BIT, ND_SIZE_256BIT }; + + size = szLut[Instrux->EfVecMode]; + } + break; + + case ND_OPS_pd: + case ND_OPS_ps: + // packed double or packed single precision values. + { + static const uint8_t szLut[3] = { ND_SIZE_128BIT, ND_SIZE_256BIT, ND_SIZE_512BIT }; + + size = szLut[Instrux->EfVecMode]; + } + break; + + case ND_OPS_ss: + // Scalar single. + size = ND_SIZE_32BIT; + break; + + case ND_OPS_sd: + // Scalar double. + size = ND_SIZE_64BIT; + break; + + case ND_OPS_mib: + // MIB addressing, used by MPX instructions. + size = 0; + break; + + case ND_OPS_vm32x: + case ND_OPS_vm32y: + case ND_OPS_vm32z: + // 32 bit indexes from XMM, YMM or ZMM register. + vsibIndexSize = ND_SIZE_32BIT; + vsibIndexCount = (Instrux->Exs.l == 0) ? 4 : ((Instrux->Exs.l == 1) ? 8 : 16); + vsibRegSize = (ops == ND_OPS_vm32x) ? ND_SIZE_128BIT : + (ops == ND_OPS_vm32y) ? ND_SIZE_256BIT : + ND_SIZE_512BIT; + size = vsibIndexCount * (width ? ND_SIZE_64BIT : ND_SIZE_32BIT); + break; + + case ND_OPS_vm32h: + // 32 bit indexes from XMM or YMM. + vsibIndexSize = ND_SIZE_32BIT; + vsibIndexCount = (Instrux->Exs.l == 0) ? 2 : ((Instrux->Exs.l == 1) ? 4 : 8); + vsibRegSize = (Instrux->Exs.l == 0) ? ND_SIZE_128BIT : + (Instrux->Exs.l == 1) ? ND_SIZE_128BIT : + ND_SIZE_256BIT; + size = vsibIndexCount * (width ? ND_SIZE_64BIT : ND_SIZE_32BIT); + break; + + case ND_OPS_vm32n: + // 32 bit indexes from XMM, YMM or ZMM register. + vsibIndexSize = ND_SIZE_32BIT; + vsibIndexCount = (Instrux->Exs.l == 0) ? 4 : ((Instrux->Exs.l == 1) ? 8 : 16); + vsibRegSize = (Instrux->Exs.l == 0) ? ND_SIZE_128BIT : + (Instrux->Exs.l == 1) ? ND_SIZE_256BIT : + ND_SIZE_512BIT; + size = vsibIndexCount * (width ? ND_SIZE_64BIT : ND_SIZE_32BIT); + break; + + case ND_OPS_vm64x: + case ND_OPS_vm64y: + case ND_OPS_vm64z: + // 64 bit indexes from XMM, YMM or ZMM register. + vsibIndexSize = ND_SIZE_64BIT; + vsibIndexCount = (Instrux->Exs.l == 0) ? 2 : ((Instrux->Exs.l == 1) ? 4 : 8); + vsibRegSize = (ops == ND_OPS_vm64x) ? ND_SIZE_128BIT : + (ops == ND_OPS_vm64y) ? ND_SIZE_256BIT : + ND_SIZE_512BIT; + size = vsibIndexCount * (width ? ND_SIZE_64BIT : ND_SIZE_32BIT); + break; + + case ND_OPS_vm64h: + // 64 bit indexes from XMM or YMM. + vsibIndexSize = ND_SIZE_64BIT; + vsibIndexCount = (Instrux->Exs.l == 0) ? 1 : ((Instrux->Exs.l == 1) ? 2 : 4); + vsibRegSize = (Instrux->Exs.l == 0) ? ND_SIZE_128BIT : + (Instrux->Exs.l == 1) ? ND_SIZE_128BIT : + ND_SIZE_256BIT; + size = vsibIndexCount * (width ? ND_SIZE_64BIT : ND_SIZE_32BIT); + break; + + case ND_OPS_vm64n: + // 64 bit indexes from XMM, YMM or ZMM register. + vsibIndexSize = ND_SIZE_64BIT; + vsibIndexCount = (Instrux->Exs.l == 0) ? 2 : ((Instrux->Exs.l == 1) ? 4 : 8); + vsibRegSize = (Instrux->Exs.l == 0) ? ND_SIZE_128BIT : + (Instrux->Exs.l == 1) ? ND_SIZE_256BIT : + ND_SIZE_512BIT; + size = vsibIndexCount * (width ? ND_SIZE_64BIT : ND_SIZE_32BIT); + break; + + case ND_OPS_v2: + case ND_OPS_v3: + case ND_OPS_v4: + case ND_OPS_v8: + // Multiple words accessed. + { + static const uint8_t szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT }; + uint8_t scale = 1; + + scale = (ops == ND_OPS_v2) ? 2 : ((ops == ND_OPS_v3) ? 3 : ((ops == ND_OPS_v4) ? 4 : 8)); + + size = scale * szLut[Instrux->EfOpMode]; + } + break; + + case ND_OPS_t: + // Tile register. The actual size depends on how the TILECFG register has been programmed, but it can be + // up to 1K in size. + size = ND_SIZE_1KB; + break; + + case ND_OPS_unknown: + size = ND_SIZE_UNKNOWN; + break; + + default: + return ND_STATUS_INVALID_INSTRUX; + } + + // Store operand info. + operand->Size = operand->RawSize = bcstSize = size; + + // + // Fill in the operand type. + // + switch (opt) + { + case ND_OPT_CONST_1: + // operand is an implicit constant (used by shift/rotate instruction). + operand->Type = ND_OP_CONST; + operand->Info.Constant.Const = 1; + break; + + case ND_OPT_RIP: + // The operand is the instruction pointer. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_RIP; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = 0; + Instrux->RipAccess |= operand->Access.Access; + break; + + case ND_OPT_GPR_rAX: + // Operator is the accumulator. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_RAX; + break; + + case ND_OPT_GPR_AH: + // Operator is the accumulator. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = ND_SIZE_8BIT; + operand->Info.Register.Reg = REG_AH; + operand->Info.Register.IsHigh8 = true; + break; + + case ND_OPT_GPR_rCX: + // Operator is the counter register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_RCX; + break; + + case ND_OPT_GPR_rDX: + // Operator is rDX. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_RDX; + break; + + case ND_OPT_GPR_rBX: + // Operator is BX. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_RBX; + break; + + case ND_OPT_GPR_rBP: + // Operand is rBP. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_RBP; + break; + + case ND_OPT_GPR_rSP: + // Operand is rSP. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_RSP; + break; + + case ND_OPT_GPR_rSI: + // Operand is rSI. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_RSI; + break; + + case ND_OPT_GPR_rDI: + // Operand is rDI. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_RDI; + break; + + case ND_OPT_GPR_rR11: + // Operand is R11. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_R11; + break; + + case ND_OPT_SEG_CS: + // Operand is the CS register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SEG; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_CS; + break; + + case ND_OPT_SEG_SS: + // Operand is the SS register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SEG; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_SS; + break; + + case ND_OPT_SEG_DS: + // Operand is the DS register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SEG; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_DS; + break; + + case ND_OPT_SEG_ES: + // Operand is the ES register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SEG; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_ES; + break; + + case ND_OPT_SEG_FS: + // Operand is the FS register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SEG; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_FS; + break; + + case ND_OPT_SEG_GS: + // Operand is the GS register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SEG; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_GS; + break; + + case ND_OPT_FPU_ST0: + // Operand is the ST(0) register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_FPU; + operand->Info.Register.Size = ND_SIZE_80BIT; + operand->Info.Register.Reg = 0; + break; + + case ND_OPT_FPU_STX: + // Operand is the ST(i) register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_FPU; + operand->Info.Register.Size = ND_SIZE_80BIT; + operand->Info.Register.Reg = Instrux->ModRm.rm; + break; + + case ND_OPT_SSE_XMM0: + // Operand is the XMM0 register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SSE; + operand->Info.Register.Size = ND_SIZE_128BIT; + operand->Info.Register.Reg = 0; + break; + + // Special operands. These are always implicit, and can't be encoded inside the instruction. + case ND_OPT_CR_0: + // The operand is implicit and is control register 0. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_CR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_CR0; + break; + + case ND_OPT_SYS_GDTR: + // The operand is implicit and is the global descriptor table register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SYS; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_GDTR; + break; + + case ND_OPT_SYS_IDTR: + // The operand is implicit and is the interrupt descriptor table register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SYS; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_IDTR; + break; + + case ND_OPT_SYS_LDTR: + // The operand is implicit and is the local descriptor table register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SYS; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_LDTR; + break; + + case ND_OPT_SYS_TR: + // The operand is implicit and is the task register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SYS; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_TR; + break; + + case ND_OPT_X87_CONTROL: + // The operand is implicit and is the x87 control word. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SYS; + operand->Info.Register.Size = ND_SIZE_16BIT; + operand->Info.Register.Reg = REG_X87_CONTROL; + break; + + case ND_OPT_X87_TAG: + // The operand is implicit and is the x87 tag word. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SYS; + operand->Info.Register.Size = ND_SIZE_16BIT; + operand->Info.Register.Reg = REG_X87_TAG; + break; + + case ND_OPT_X87_STATUS: + // The operand is implicit and is the x87 status word. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SYS; + operand->Info.Register.Size = ND_SIZE_16BIT; + operand->Info.Register.Reg = REG_X87_STATUS; + break; + + case ND_OPT_MXCSR: + // The operand is implicit and is the MXCSR. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MXCSR; + operand->Info.Register.Size = ND_SIZE_32BIT; + operand->Info.Register.Reg = 0; + break; + + case ND_OPT_PKRU: + // The operand is the PKRU register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_PKRU; + operand->Info.Register.Size = ND_SIZE_32BIT; + operand->Info.Register.Reg = 0; + break; + + case ND_OPT_SSP: + // The operand is the SSP register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SSP; + operand->Info.Register.Size = (Instrux->OpMode == ND_OPSZ_64) ? ND_SIZE_64BIT : ND_SIZE_32BIT; + operand->Info.Register.Reg = 0; + break; + + case ND_OPT_MSR: + // The operand is implicit and is a MSR (usually selected by the ECX register). + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSR; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = 0xFFFFFFFF; + break; + + case ND_OPT_MSR_TSC: + // The operand is implicit and is the IA32_TSC. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSR; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = REG_IA32_TSC; + break; + + case ND_OPT_MSR_TSCAUX: + // The operand is implicit and is the IA32_TSCAUX. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSR; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = REG_IA32_TSC_AUX; + break; + + case ND_OPT_MSR_SCS: + // The operand is implicit and is the IA32_SYSENTER_CS. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSR; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = REG_IA32_SYSENTER_CS; + break; + + case ND_OPT_MSR_SESP: + // The operand is implicit and is the IA32_SYSENTER_ESP. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSR; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = REG_IA32_SYSENTER_ESP; + break; + + case ND_OPT_MSR_SEIP: + // The operand is implicit and is the IA32_SYSENTER_EIP. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSR; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = REG_IA32_SYSENTER_EIP; + break; + + case ND_OPT_MSR_STAR: + // The operand is implicit and is the IA32_STAR. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSR; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = REG_IA32_STAR; + break; + + case ND_OPT_MSR_LSTAR: + // The operand is implicit and is the IA32_STAR. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSR; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = REG_IA32_LSTAR; + break; + + case ND_OPT_MSR_FMASK: + // The operand is implicit and is the IA32_FMASK. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSR; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = REG_IA32_FMASK; + break; + + case ND_OPT_MSR_FSBASE: + // The operand is implicit and is the IA32_FS_BASE MSR. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSR; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = REG_IA32_FS_BASE; + break; + + case ND_OPT_MSR_GSBASE: + // The operand is implicit and is the IA32_GS_BASE MSR. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSR; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = REG_IA32_GS_BASE; + break; + + case ND_OPT_MSR_KGSBASE: + // The operand is implicit and is the IA32_KERNEL_GS_BASE MSR. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSR; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = REG_IA32_GS_BASE; + break; + + case ND_OPT_XCR: + // The operand is implicit and is an extended control register (usually selected by ECX register). + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_XCR; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = 0xFF; + break; + + case ND_OPT_XCR_0: + // The operand is implicit and is XCR0. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_XCR; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = 0; + break; + + case ND_OPT_REG_BANK: + // Multiple registers are accessed. + if ((Instrux->Instruction == ND_INS_PUSHA) || (Instrux->Instruction == ND_INS_POPA)) + { + operand->Type = ND_OP_REG; + operand->Size = operand->RawSize = Instrux->WordLength; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = Instrux->WordLength; + operand->Info.Register.Reg = REG_EAX; + operand->Info.Register.Count = 8; + operand->Info.Register.IsBlock = true; + } + else + { + operand->Type = ND_OP_BANK; + } + break; + + case ND_OPT_A: + // Fetch the address. NOTE: The size can't be larger than 8 bytes. + status = NdFetchAddress(Instrux, Code, Offset, Size, (uint8_t)size); + if (!ND_SUCCESS(status)) + { + return status; + } + + // Fill in operand info. + operand->Type = ND_OP_ADDR; + operand->Info.Address.BaseSeg = Instrux->Address.Cs; + operand->Info.Address.Offset = Instrux->Address.Ip; + + Offset = Instrux->Length; + break; + + case ND_OPT_B: + // General purpose register encoded in VEX.vvvv field. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + + // EVEX.V' must be 0, if a GPR is encoded using EVEX encoding. + if (Instrux->Exs.vp != 0) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + + operand->Info.Register.Reg = (uint8_t)Instrux->Exs.v; + break; + + case ND_OPT_C: + // Control register, encoded in modrm.reg. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_CR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.r << 3) | Instrux->ModRm.reg); + // On some AMD processors, the presence of the LOCK prefix before MOV to/from control registers allows accessing + // higher 8 control registers. + if ((ND_CODE_64 != Instrux->DefCode) && (Instrux->HasLock)) + { + operand->Info.Register.Reg |= 0x8; + } + + // Only CR0, CR2, CR3, CR4 & CR8 valid. + if (operand->Info.Register.Reg != 0 && + operand->Info.Register.Reg != 2 && + operand->Info.Register.Reg != 3 && + operand->Info.Register.Reg != 4 && + operand->Info.Register.Reg != 8) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + + break; + + case ND_OPT_D: + // Debug register, encoded in modrm.reg. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_DR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.r << 3) | Instrux->ModRm.reg); + + // Only DR0-DR7 valid. + if (operand->Info.Register.Reg >= 8) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + + break; + + case ND_OPT_T: + // Test register, encoded in modrm.reg. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_TR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.r << 3) | Instrux->ModRm.reg); + + // Only TR0-TR7 valid, only on 486. + if (operand->Info.Register.Reg >= 8) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + + break; + + case ND_OPT_S: + // Segment register, encoded in modrm.reg. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SEG; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = Instrux->ModRm.reg; + + // Only ES, CS, SS, DS, FS, GS valid. + if (operand->Info.Register.Reg >= 6) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + + // If CS is loaded - #UD. + if ((operand->Info.Register.Reg == REG_CS) && operand->Access.Write) + { + return ND_STATUS_CS_LOAD; + } + + break; + + case ND_OPT_E: + // General purpose register or memory, encoded in modrm.rm. + if (Instrux->ModRm.mod == 3) + { + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.b << 3) | Instrux->ModRm.rm); + operand->Info.Register.IsHigh8 = (operand->Info.Register.Size == 1) && + (operand->Info.Register.Reg >= 4) && + (ND_ENCM_LEGACY == Instrux->EncMode) && + !Instrux->HasRex; + } + else + { + goto memory; + } + break; + + case ND_OPT_F: + // The flags register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_FLG; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = 0; + Instrux->FlagsAccess.RegAccess |= operand->Access.Access; + break; + + case ND_OPT_K: + // The operand is the stack. + { + static const uint8_t szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT }; + + Instrux->MemoryAccess |= operand->Access.Access; + operand->Type = ND_OP_MEM; + operand->Info.Memory.IsStack = true; + operand->Info.Memory.HasBase = true; + operand->Info.Memory.Base = REG_RSP; + operand->Info.Memory.BaseSize = szLut[Instrux->DefStack]; + operand->Info.Memory.HasSeg = true; + operand->Info.Memory.Seg = REG_SS; + Instrux->StackWords = (uint8_t)(operand->Size / Instrux->WordLength); + Instrux->StackAccess |= operand->Access.Access; + } + break; + + case ND_OPT_G: + // General purpose register encoded in modrm.reg. + if (Instrux->Exs.rp == 1) + { + return ND_STATUS_INVALID_ENCODING; + } + + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + + // EVEX.R' must be 0 if a GPR is encoded. + if (Instrux->Exs.rp != 0) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + + operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.r << 3) | Instrux->ModRm.reg); + operand->Info.Register.IsHigh8 = (operand->Info.Register.Size == 1) && + (operand->Info.Register.Reg >= 4) && + (ND_ENCM_LEGACY == Instrux->EncMode) && + !Instrux->HasRex; + break; + + case ND_OPT_R: + // General purpose register encoded in modrm.rm. + if ((Instrux->ModRm.mod == 3) || (0 != (Instrux->Attributes & ND_FLAG_MFR))) + { + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.b << 3) | Instrux->ModRm.rm); + operand->Info.Register.IsHigh8 = (operand->Info.Register.Size == 1) && + (operand->Info.Register.Reg >= 4) && + (ND_ENCM_LEGACY == Instrux->EncMode) && + !Instrux->HasRex; + } + else + { + return ND_STATUS_INVALID_ENCODING; + } + break; + + case ND_OPT_I: + // Immediate, encoded in instructon bytes. + { + uint64_t imm; + + // Fetch the immediate. NOTE: The size won't exceed 8 bytes. + status = NdFetchImmediate(Instrux, Code, Offset, Size, (uint8_t)size); + if (!ND_SUCCESS(status)) + { + return status; + } + + // Get the last immediate. + if (Instrux->HasImm3) + { + imm = Instrux->Immediate3; + } + else if (Instrux->HasImm2) + { + imm = Instrux->Immediate2; + } + else + { + imm = Instrux->Immediate1; + } + + operand->Type = ND_OP_IMM; + + if (operand->Flags.SignExtendedDws) + { + static const uint8_t wszLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT }; + + // Get the default word size: the immediate is sign extended to the default word size. + operand->Size = wszLut[Instrux->EfOpMode]; + + operand->Info.Immediate.Imm = ND_SIGN_EX(size, imm); + } + else if (operand->Flags.SignExtendedOp1) + { + // The immediate is sign extended to the size of the first operand. + operand->Size = Instrux->Operands[0].Size; + + operand->Info.Immediate.Imm = ND_SIGN_EX(size, imm); + } + else + { + operand->Info.Immediate.Imm = imm; + } + + Offset = Instrux->Length; + } + break; + + case ND_OPT_J: + // Fetch the relative offset. NOTE: The size of the relative can't exceed 4 bytes. + status = NdFetchRelativeOffset(Instrux, Code, Offset, Size, (uint8_t)size); + if (!ND_SUCCESS(status)) + { + return status; + } + + // The instruction is RIP relative. + Instrux->IsRipRelative = true; + + operand->Type = ND_OP_OFFS; + // The relative offset is forced to the default word length. Care must be taken with the 32 bit + // branches that have 0x66 prefix (in 32 bit mode)! + operand->Size = Instrux->WordLength; + operand->Info.RelativeOffset.Rel = ND_SIGN_EX(size, Instrux->RelativeOffset); + + Offset = Instrux->Length; + + break; + + case ND_OPT_N: + // The R/M field of the ModR/M byte selects a packed-quadword, MMX technology register. + if (Instrux->ModRm.mod != 3) + { + return ND_STATUS_INVALID_ENCODING; + } + + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MMX; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = Instrux->ModRm.rm; + break; + + case ND_OPT_P: + // The reg field of the ModR/M byte selects a packed quadword MMX technology register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MMX; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = Instrux->ModRm.reg; + break; + + case ND_OPT_Q: + // A ModR/M byte follows the opcode and specifies the operand. The operand is either an MMX technology + // register or a memory address. If it is a memory address, the address is computed from a segment register + // and any of the following values: a base register, an index register, a scaling factor, and a displacement + if (Instrux->ModRm.mod == 3) + { + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MMX; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = Instrux->ModRm.rm; + } + else + { + goto memory; + } + break; + + case ND_OPT_O: + // Absolute address, encoded in instruction bytes. + { + // NOTE: The moffset len can't exceed 8 bytes. + status = NdFetchMoffset(Instrux, Code, Offset, Size, 2 << Instrux->AddrMode); + if (!ND_SUCCESS(status)) + { + return status; + } + + // operand info. + Instrux->MemoryAccess |= operand->Access.Access; + operand->Type = ND_OP_MEM; + operand->Info.Memory.HasDisp = true; + operand->Info.Memory.IsDirect = true; + operand->Info.Memory.DispSize = Instrux->MoffsetLength; + operand->Info.Memory.Disp = Instrux->Moffset; + operand->Info.Memory.HasSeg = true; + operand->Info.Memory.Seg = NdGetSegOverride(Instrux, REG_DS); + + Offset = Instrux->Length; + } + break; + + case ND_OPT_M: + // Modrm based memory addressing. + if (Instrux->ModRm.mod == 3) + { + return ND_STATUS_INVALID_ENCODING; + } + +memory: + Instrux->MemoryAccess |= operand->Access.Access; + operand->Type = ND_OP_MEM; + operand->Info.Memory.HasSeg = true; + + if (ND_ADDR_16 == Instrux->AddrMode) + { + // 16 bit addressing, make sure the instruction supports this. + if (!!(Instrux->Attributes & ND_FLAG_NOA16)) + { + return ND_STATUS_16_BIT_ADDRESSING_NOT_SUPPORTED; + } + + switch (Instrux->ModRm.rm) + { + case 0: + // [bx + si] + operand->Info.Memory.HasBase = true; + operand->Info.Memory.HasIndex = true; + operand->Info.Memory.Scale = 1; + operand->Info.Memory.Base = REG_BX; + operand->Info.Memory.Index = REG_SI; + operand->Info.Memory.BaseSize = ND_SIZE_16BIT; + operand->Info.Memory.IndexSize = ND_SIZE_16BIT; + operand->Info.Memory.Seg = REG_DS; + break; + case 1: + // [bx + di] + operand->Info.Memory.HasBase = true; + operand->Info.Memory.HasIndex = true; + operand->Info.Memory.Scale = 1; + operand->Info.Memory.Base = REG_BX; + operand->Info.Memory.Index = REG_DI; + operand->Info.Memory.BaseSize = ND_SIZE_16BIT; + operand->Info.Memory.IndexSize = ND_SIZE_16BIT; + operand->Info.Memory.Seg = REG_DS; + break; + case 2: + // [bp + si] + operand->Info.Memory.HasBase = true; + operand->Info.Memory.HasIndex = true; + operand->Info.Memory.Scale = 1; + operand->Info.Memory.Base = REG_BP; + operand->Info.Memory.Index = REG_SI; + operand->Info.Memory.BaseSize = ND_SIZE_16BIT; + operand->Info.Memory.IndexSize = ND_SIZE_16BIT; + operand->Info.Memory.Seg = REG_SS; + break; + case 3: + // [bp + di] + operand->Info.Memory.HasBase = true; + operand->Info.Memory.HasIndex = true; + operand->Info.Memory.Scale = 1; + operand->Info.Memory.Base = REG_BP; + operand->Info.Memory.Index = REG_DI; + operand->Info.Memory.BaseSize = ND_SIZE_16BIT; + operand->Info.Memory.IndexSize = ND_SIZE_16BIT; + operand->Info.Memory.Seg = REG_SS; + break; + case 4: + // [si] + operand->Info.Memory.HasBase = true; + operand->Info.Memory.Base = REG_SI; + operand->Info.Memory.BaseSize = ND_SIZE_16BIT; + operand->Info.Memory.Seg = REG_DS; + break; + case 5: + // [di] + operand->Info.Memory.HasBase = true; + operand->Info.Memory.Base = REG_DI; + operand->Info.Memory.BaseSize = ND_SIZE_16BIT; + operand->Info.Memory.Seg = REG_DS; + break; + case 6: + // [bp] + if (Instrux->ModRm.mod != 0) + { + // If mod is not zero, than we have "[bp + displacement]". + operand->Info.Memory.HasBase = true; + operand->Info.Memory.Base = REG_BP; + operand->Info.Memory.BaseSize = ND_SIZE_16BIT; + operand->Info.Memory.Seg = REG_SS; + } + else + { + // If mod is zero, than we only have a displacement that is used to directly address mem. + operand->Info.Memory.Seg = REG_DS; + } + break; + case 7: + // [bx] + operand->Info.Memory.HasBase = true; + operand->Info.Memory.Base = REG_BX; + operand->Info.Memory.BaseSize = ND_SIZE_16BIT; + operand->Info.Memory.Seg = REG_DS; + break; + } + + // Store the displacement. + operand->Info.Memory.HasDisp = !!Instrux->HasDisp; + operand->Info.Memory.DispSize = Instrux->DispLength; + operand->Info.Memory.Disp = ND_SIGN_EX(Instrux->DispLength, Instrux->Displacement); + } + else + { + uint8_t defsize = (Instrux->AddrMode == ND_ADDR_32 ? ND_SIZE_32BIT : ND_SIZE_64BIT); + + // Implicit segment is DS. + operand->Info.Memory.Seg = REG_DS; + + if (Instrux->HasSib) + { + // Check for base. + if ((Instrux->ModRm.mod == 0) && (Instrux->Sib.base == REG_RBP)) + { + // Mod is mem without displacement and base reg is RBP -> no base reg used. + // Note that this addressing mode is not RIP relative. + } + else + { + operand->Info.Memory.HasBase = true; + operand->Info.Memory.BaseSize = defsize; + operand->Info.Memory.Base = (uint8_t)((Instrux->Exs.b << 3) | Instrux->Sib.base); + + if ((operand->Info.Memory.Base == REG_RSP) || (operand->Info.Memory.Base == REG_RBP)) + { + operand->Info.Memory.Seg = REG_SS; + } + } + + // Check for index. + if ((((Instrux->Exs.x << 3) | Instrux->Sib.index) != REG_RSP) || ND_HAS_VSIB(Instrux)) + { + // Index * Scale is present. + operand->Info.Memory.HasIndex = true; + operand->Info.Memory.IndexSize = defsize; + operand->Info.Memory.Index = (uint8_t)((Instrux->Exs.x << 3) | Instrux->Sib.index); + + if (ND_HAS_VSIB(Instrux)) + { + operand->Info.Memory.IndexSize = vsibRegSize; + operand->Info.Memory.Index |= Instrux->Exs.vp << 4; + } + + operand->Info.Memory.Scale = 1 << Instrux->Sib.scale; + } + } + else + { + if ((Instrux->ModRm.mod == 0) && (Instrux->ModRm.rm == REG_RBP)) + { + // Some instructions (example: MPX) don't support RIP relative addressing. + if (!!(Instrux->Attributes & ND_FLAG_NO_RIP_REL)) + { + return ND_STATUS_RIP_REL_ADDRESSING_NOT_SUPPORTED; + } + + // + // RIP relative addressing addresses a memory region relative to the current RIP; However, + // the current RIP, when executing the current instruction, is already updated and points + // to the next instruction, therefore, we must add the instruction length also to the final + // address. Note that RIP relative addressing is used even if the instruction uses 32 bit + // addressing, as long as we're in long mode. + // + operand->Info.Memory.IsRipRel = Instrux->IsRipRelative = (Instrux->DefCode == ND_CODE_64); + } + else + { + operand->Info.Memory.HasBase = true; + operand->Info.Memory.BaseSize = defsize; + operand->Info.Memory.Base = (uint8_t)((Instrux->Exs.b << 3) | Instrux->ModRm.rm); + + if ((operand->Info.Memory.Base == REG_RSP) || (operand->Info.Memory.Base == REG_RBP)) + { + operand->Info.Memory.Seg = REG_SS; + } + } + } + + operand->Info.Memory.HasDisp = Instrux->HasDisp; + operand->Info.Memory.DispSize = Instrux->DispLength; + operand->Info.Memory.Disp = ND_SIGN_EX(Instrux->DispLength, Instrux->Displacement); + } + + // Get the segment. Note that in long mode, segment prefixes are ignored, except for FS and GS. + if (Instrux->HasSeg) + { + operand->Info.Memory.Seg = NdGetSegOverride(Instrux, operand->Info.Memory.Seg); + } + + // Handle VSIB addressing. + if (ND_HAS_VSIB(Instrux)) + { + // VSIB requires SIB. + if (!Instrux->HasSib) + { + return ND_STATUS_VSIB_WITHOUT_SIB; + } + + operand->Info.Memory.IsVsib = true; + + operand->Info.Memory.Vsib.IndexSize = vsibIndexSize; + operand->Info.Memory.Vsib.ElemCount = vsibIndexCount; + operand->Info.Memory.Vsib.ElemSize = (uint8_t)(size / vsibIndexCount); + } + + // Handle sibmem addressing, as used by Intel AMX instructions. + if (ND_HAS_SIBMEM(Instrux)) + { + // sibmem requires SIB to be present. + if (!Instrux->HasSib) + { + return ND_STATUS_INVALID_ENCODING; + } + + operand->Info.Memory.IsSibMem = true; + } + + if (Instrux->HasEvex) + { + // Handle compressed displacement, if any. Note that most EVEX instructions with 8 bit displacement + // use compressed displacement addressing. + if ((Instrux->HasDisp) && (ND_SIZE_8BIT == Instrux->DispLength)) + { + Instrux->HasCompDisp = true; + + operand->Info.Memory.HasCompDisp = true; + operand->Info.Memory.CompDispSize = NdGetCompDispSize(Instrux, operand->Size); + } + + // If we have broadcast, the operand size is fixed to either 32 bit, either 64 bit, depending on bcast size. + // Therefore, we will override the rawSize with either 32 or 64 bits. Note that bcstSize will save the total + // size of the access, and it will be used to compute the number of broadcasted elements: bcstSize / rawSize. + if ((Instrux->Exs.bm) && (opd & (ND_OPD_B32 | ND_OPD_B64))) + { + Instrux->HasBroadcast = true; + operand->Info.Memory.HasBroadcast = true; + + if (opd & ND_OPD_B32) + { + size = ND_SIZE_32BIT; + } + else if (opd & ND_OPD_B64) + { + size = ND_SIZE_64BIT; + } + else + { + size = width ? ND_SIZE_64BIT : ND_SIZE_32BIT; + } + + // Override operand size. + operand->Size = operand->RawSize = size; + } + } + + // MIB, if any. Used by some MPX instructions. + operand->Info.Memory.IsMib = ND_HAS_MIB(Instrux); + + // Bitbase, if any. Used by BT* instructions when the first op is mem and the second one reg. + operand->Info.Memory.IsBitbase = ND_HAS_BITBASE(Instrux); + + // AG, if this is the case. + if (ND_HAS_AG(Instrux)) + { + operand->Info.Memory.IsAG = true; + + // Address generation instructions ignore the segment prefixes. Examples are LEA and MPX instructions. + operand->Info.Memory.HasSeg = false; + operand->Info.Memory.Seg = 0; + } + + // Shadow Stack Access, if this is the case. + operand->Info.Memory.IsShadowStack = ND_HAS_SHS(Instrux); + + break; + + + case ND_OPT_H: + // Vector register, encoded in VEX/EVEX.vvvv. + if (ND_ENCM_LEGACY == Instrux->EncMode) + { + return ND_STATUS_HINT_OPERAND_NOT_USED; + } + else + { + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SSE; + operand->Info.Register.Size = (ND_REG_SIZE)(size < ND_SIZE_128BIT ? ND_SIZE_128BIT : size); + operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.vp << 4) | Instrux->Exs.v); + } + break; + + case ND_OPT_L: + // Vector register, encoded in immediate. + status = NdFetchSseImmediate(Instrux, Code, Offset, Size, 1); + if (!ND_SUCCESS(status)) + { + return status; + } + + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SSE; + operand->Info.Register.Size = (ND_REG_SIZE)(size < ND_SIZE_128BIT ? ND_SIZE_128BIT : size); + operand->Info.Register.Reg = ((Instrux->SseImmediate >> 4) & 0xF) | ((Instrux->SseImmediate & 8) << 1); + + Offset = Instrux->Length; + break; + + case ND_OPT_U: + // Vector register encoded in modrm.rm. + if (Instrux->ModRm.mod != 3) + { + return ND_STATUS_INVALID_ENCODING; + } + + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SSE; + operand->Info.Register.Size = (ND_REG_SIZE)(size < ND_SIZE_128BIT ? ND_SIZE_128BIT : size); + operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.b << 3) | Instrux->ModRm.rm); + if (Instrux->HasEvex || Instrux->HasMvex) + { + operand->Info.Register.Reg |= Instrux->Exs.x << 4; + } + break; + + case ND_OPT_V: + // Vector register encoded in modrm.reg. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SSE; + operand->Info.Register.Size = (ND_REG_SIZE)(size < ND_SIZE_128BIT ? ND_SIZE_128BIT : size); + operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.r << 3) | Instrux->ModRm.reg); + if (Instrux->HasEvex || Instrux->HasMvex) + { + operand->Info.Register.Reg |= Instrux->Exs.rp << 4; + } + break; + + case ND_OPT_W: + // Vector register or memory encoded in modrm.rm. + if (Instrux->ModRm.mod == 3) + { + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SSE; + operand->Info.Register.Size = (ND_REG_SIZE)(size < ND_SIZE_128BIT ? ND_SIZE_128BIT : size); + operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.b << 3) | Instrux->ModRm.rm); + if (Instrux->HasEvex || Instrux->HasMvex) + { + operand->Info.Register.Reg |= Instrux->Exs.x << 4; + } + } + else + { + goto memory; + } + break; + + case ND_OPT_X: + case ND_OPT_Y: + case ND_OPT_MEM_rDI: + // RSI/RDI based addressing, as used by string instructions. + Instrux->MemoryAccess |= operand->Access.Access; + operand->Type = ND_OP_MEM; + operand->Info.Memory.HasBase = true; + operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode; + operand->Info.Memory.HasSeg = true; + operand->Info.Memory.Base = (uint8_t)(((opt == ND_OPT_X) ? REG_RSI : REG_RDI)); + operand->Info.Memory.IsString = (ND_OPT_X == opt || ND_OPT_Y == opt); + // DS:rSI supports segment overriding. ES:rDI does not. + if (opt == ND_OPT_Y) + { + operand->Info.Memory.Seg = REG_ES; + } + else + { + operand->Info.Memory.Seg = NdGetSegOverride(Instrux, REG_DS); + } + break; + + case ND_OPT_MEM_rBX_AL: + // [rBX + AL], used by XLAT. + Instrux->MemoryAccess |= operand->Access.Access; + operand->Type = ND_OP_MEM; + operand->Info.Memory.HasBase = true; + operand->Info.Memory.HasIndex = true; + operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode; + operand->Info.Memory.IndexSize = ND_SIZE_8BIT; // Always 1 Byte. + operand->Info.Memory.Base = REG_RBX; // Always rBX. + operand->Info.Memory.Index = REG_AL; // Always AL. + operand->Info.Memory.Scale = 1; // Always 1. + operand->Info.Memory.HasSeg = true; + operand->Info.Memory.Seg = NdGetSegOverride(Instrux, REG_DS); + break; + + case ND_OPT_MEM_SHS: + // Shadow stack. + Instrux->MemoryAccess |= operand->Access.Access; + operand->Type = ND_OP_MEM; + operand->Info.Memory.IsShadowStack = true; + break; + + case ND_OPT_Z: + // A GPR Register is selected by the low 3 bits inside the opcode. REX.B can be used to extend it. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.b << 3) | (Instrux->PrimaryOpCode & 0x7)); + operand->Info.Register.IsHigh8 = (operand->Info.Register.Size == 1) && + (operand->Info.Register.Reg >= 4) && + (ND_ENCM_LEGACY == Instrux->EncMode) && + !Instrux->HasRex; + break; + + case ND_OPT_rB: + // reg inside modrm selects a BND register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_BND; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.r << 3) | Instrux->ModRm.reg); + if (operand->Info.Register.Reg >= 4) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + break; + + case ND_OPT_mB: + // rm inside modrm selects either a BND register, either memory. + if (Instrux->ModRm.mod == 3) + { + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_BND; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.b << 3) | Instrux->ModRm.rm); + if (operand->Info.Register.Reg >= 4) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + } + else + { + goto memory; + } + break; + + case ND_OPT_rK: + // reg inside modrm selects a mask register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSK; + + // Opcode dependent #UD, R and R' must be zero (1 actually, but they're inverted). + if ((Instrux->Exs.r != 0) || (Instrux->Exs.rp != 0)) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = (uint8_t)(Instrux->ModRm.reg); + + break; + + case ND_OPT_vK: + // vex.vvvv selects a mask register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSK; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = (uint8_t)Instrux->Exs.v; + if (operand->Info.Register.Reg >= 8) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + break; + + case ND_OPT_mK: + // rm inside modrm selects either a mask register, either memory. + if (Instrux->ModRm.mod == 3) + { + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSK; + operand->Info.Register.Size = ND_SIZE_64BIT; + // X and B are ignored when Msk registers are being addressed. + operand->Info.Register.Reg = Instrux->ModRm.rm; + } + else + { + goto memory; + } + break; + + case ND_OPT_aK: + // aaa inside evex selects either a mask register, which is used for masking a destination operand. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSK; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = Instrux->Exs.k; + break; + + case ND_OPT_rM: + // Sigh. reg field inside mod r/m encodes memory. This encoding is used by MOVDIR64b and ENQCMD instructions. + // When the ModR/M.reg field is used to select a memory operand, the following apply: + // - The ES segment register is used as a base + // - The ES segment register cannot be overridden + // - The size of the base register is selected by the address size, not the operand size. + operand->Type = ND_OP_MEM; + operand->Info.Memory.HasBase = true; + operand->Info.Memory.Base = (uint8_t)((Instrux->Exs.r << 3) | Instrux->ModRm.reg); + operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode; + operand->Info.Memory.HasSeg = true; + operand->Info.Memory.Seg = REG_ES; + break; + + case ND_OPT_mM: + // Sigh. rm field inside mod r/m encodes memory, even if mod is 3. + operand->Type = ND_OP_MEM; + operand->Info.Memory.HasBase = true; + operand->Info.Memory.Base = (uint8_t)((Instrux->Exs.m << 3) | Instrux->ModRm.rm); + operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode; + operand->Info.Memory.HasSeg = true; + operand->Info.Memory.Seg = NdGetSegOverride(Instrux, REG_DS); + break; + + case ND_OPT_rT: + // Tile register encoded in ModR/M.reg field. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_TILE; + operand->Info.Register.Size = size; + operand->Info.Register.Reg = Instrux->ModRm.reg; + + // #UD if a tile register > 7 is encoded. + if (Instrux->Exs.r != 0) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + + break; + + case ND_OPT_mT: + // Tile register encoded in ModR/M.rm field. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_TILE; + operand->Info.Register.Size = size; + operand->Info.Register.Reg = Instrux->ModRm.rm; + + // #UD if a tile register > 7 is encoded. + if (Instrux->Exs.b != 0) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + + break; + + case ND_OPT_vT: + // Tile register encoded in vex.vvvv field. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_TILE; + operand->Info.Register.Size = size; + operand->Info.Register.Reg = Instrux->Exs.v; + + // #UD if a tile register > 7 is encoded. + if (operand->Info.Register.Reg > 7) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + + break; + + default: + return ND_STATUS_INVALID_INSTRUX; + } + + // Handle block addressing - used by AVX512_4FMAPS and AVX512_4VNNIW instructions. Also used by VP2INTERSECTD/Q + // instructions. Also note that in block addressing, the base of the block is masked using the size of the block; + // for example, for a block size of 1, the first register must be even; For a block size of 4, the first register + // must be divisible by 4. + if (operand->Type == ND_OP_REG) + { + if (opb != 0) + { + operand->Info.Register.Count = opb; + operand->Info.Register.Reg &= ~(opb - 1); + operand->Info.Register.IsBlock = true; + } + else + { + operand->Info.Register.Count = 1; + } + } + + // Store the operand encoding inside the bitmap. + Instrux->OperandsEncodingMap |= (1 << gOperandMap[opt]); + + operand->Encoding = (ND_OPERAND_ENCODING)gOperandMap[opt]; + + // Handle decorators. + if (0 != opd) + { + // Check for mask register. Mask if present only if the operand supports masking and if the + // mask register is not k0 (which implies "no masking"). + if ((opd & ND_OPD_MASK) && (Instrux->Exs.k != 0)) + { + operand->Decorator.HasMask = true; + operand->Decorator.Mask.Msk = (uint8_t)Instrux->Exs.k; + Instrux->HasMask = true; + } + + // Check for zeroing. The operand must support zeroing and the z bit inside vex3 must be set. Note that + // zeroing is allowed only for register destinations, and NOT for memory. + if ((opd & ND_OPD_Z) && (Instrux->Exs.z) && (operand->Type != ND_OP_MEM)) + { + operand->Decorator.HasZero = true; + Instrux->HasZero = true; + } + + // Check for broadcast again. We've already filled the broadcast size before parsing the op size. + if (((opd & ND_OPD_B32) || (opd & ND_OPD_B64)) && (Instrux->Exs.bm) && (Instrux->ModRm.mod != 3)) + { + operand->Decorator.HasBroadcast = true; + operand->Decorator.Broadcast.Size = (uint8_t)operand->Size; + operand->Decorator.Broadcast.Count = (uint8_t)(bcstSize / operand->Size); + } + + if (opd & ND_OPD_SAE) + { + operand->Decorator.HasSae = Instrux->HasSae; + } + + if (opd & ND_OPD_ER) + { + operand->Decorator.HasEr = Instrux->HasEr; + } + } + + return status; +} + + +// +// NdFindInstruction +// +static NDSTATUS +NdFindInstruction( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size, + uint8_t Vendor, + ND_INSTRUCTION **InsDef + ) +{ + NDSTATUS status; + const ND_TABLE *pTable; + ND_INSTRUCTION *pIns; + bool stop, redf2, redf3; + uint32_t nextOpcode, nextIndex; + + UNREFERENCED_PARAMETER(Offset); + + // pre-init + status = ND_STATUS_SUCCESS; + pIns = NULL; + stop = false; + nextOpcode = 0; + redf2 = redf3 = false; + + switch (Instrux->EncMode) + { + case ND_ENCM_LEGACY: + pTable = (const ND_TABLE *)gRootTable; + break; + case ND_ENCM_XOP: + pTable = (const ND_TABLE *)gXopTable; + break; + case ND_ENCM_VEX: + pTable = (const ND_TABLE *)gVexTable; + break; + case ND_ENCM_EVEX: + pTable = (const ND_TABLE *)gEvexTable; + break; + default: + pTable = (const ND_TABLE *)NULL; + break; + } + + while ((!stop) && (NULL != pTable)) + { + switch (pTable->Type) + { + case ND_ILUT_INSTRUCTION: + // We've found the leaf entry, which is an instruction - we can leave. + pIns = (ND_INSTRUCTION *)(((ND_TABLE_INSTRUCTION *)pTable)->Instruction); + stop = true; + break; + + case ND_ILUT_OPCODE: + // We need an opcode to keep going. + status = NdFetchOpcode(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + stop = true; + break; + } + pTable = (const ND_TABLE *)pTable->Table[Instrux->OpCodeBytes[nextOpcode++]]; + break; + + case ND_ILUT_OPCODE_3DNOW: + // We need an opcode to select the next table, but the opcode is AFTER the modrm/sib/displacement. + if (!Instrux->HasModRm) + { + // Fetch modrm + status = NdFetchModrmAndSib(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + stop = true; + break; + } + + // Fetch displacement. + status = NdFetchDisplacement(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + stop = true; + break; + } + } + + // Fetch the opcode, which is after the modrm and displacement. + status = NdFetchOpcode(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + stop = true; + break; + } + + pTable = (const ND_TABLE *)pTable->Table[Instrux->OpCodeBytes[nextOpcode++]]; + break; + + case ND_ILUT_MODRM_MOD: + // We need modrm.mod to select the next table. + if (!Instrux->HasModRm) + { + // Fetch modrm + status = NdFetchModrmAndSib(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + stop = true; + break; + } + + // Fetch displacement. + status = NdFetchDisplacement(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + stop = true; + break; + } + } + + // Next index is either 0 (mem) or 1 (reg) + pTable = (const ND_TABLE *)pTable->Table[Instrux->ModRm.mod == 3 ? 1 : 0]; + break; + + case ND_ILUT_MODRM_REG: + // We need modrm.reg to select the next table. + if (!Instrux->HasModRm) + { + // Fetch modrm + status = NdFetchModrmAndSib(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + stop = true; + break; + } + + // Fetch displacement. + status = NdFetchDisplacement(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + stop = true; + break; + } + } + + // Next index is the reg. + pTable = (const ND_TABLE *)pTable->Table[Instrux->ModRm.reg]; + break; + + case ND_ILUT_MODRM_RM: + // We need modrm.rm to select the next table. + if (!Instrux->HasModRm) + { + // Fetch modrm + status = NdFetchModrmAndSib(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + stop = true; + break; + } + + // Fetch displacement. + status = NdFetchDisplacement(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + stop = true; + break; + } + } + + // Next index is the rm. + pTable = (const ND_TABLE *)pTable->Table[Instrux->ModRm.rm]; + break; + + case ND_ILUT_MAN_PREFIX: + // We have mandatory prefixes. + if ((Instrux->Rep == 0xF2) && !redf2) + { + // We can only redirect once through one mandatory prefix, otherwise we may + // enter an infinite loop (see CRC32 Gw Eb -> 0x66 0xF2 0x0F ...) + redf2 = true; + nextIndex = ND_ILUT_INDEX_MAN_PREF_F2; + Instrux->HasMandatoryF2 = true; + } + else if ((Instrux->Rep == 0xF3) && !redf3) + { + redf3 = true; + nextIndex = ND_ILUT_INDEX_MAN_PREF_F3; + Instrux->HasMandatoryF3 = true; + } + else if (Instrux->HasOpSize) + { + nextIndex = ND_ILUT_INDEX_MAN_PREF_66; + Instrux->HasMandatory66 = true; + } + else + { + nextIndex = ND_ILUT_INDEX_MAN_PREF_NONE; + } + pTable = (const ND_TABLE *)pTable->Table[nextIndex]; + break; + + case ND_ILUT_MODE: + { + static const uint8_t indexes[3] = + { + ND_ILUT_INDEX_MODE_16, ND_ILUT_INDEX_MODE_32, ND_ILUT_INDEX_MODE_64 + }; + + nextIndex = ND_ILUT_INDEX_MODE_NONE; + + if (NULL != pTable->Table[indexes[Instrux->DefCode]]) + { + nextIndex = indexes[Instrux->DefCode]; + } + + pTable = (const ND_TABLE *)pTable->Table[nextIndex]; + } + break; + + case ND_ILUT_DSIZE: + { + static const uint8_t indexes[3] = + { + ND_ILUT_INDEX_DSIZE_16, ND_ILUT_INDEX_DSIZE_32, ND_ILUT_INDEX_DSIZE_64 + }; + + nextIndex = ND_ILUT_INDEX_DSIZE_NONE; + + if (NULL != pTable->Table[indexes[Instrux->OpMode]]) + { + nextIndex = indexes[Instrux->OpMode]; + } + + // Handle default/forced redirections in 64 bit mode. + if (ND_CODE_64 == Instrux->DefCode) + { + if ((NULL != pTable->Table[4]) && (!Instrux->HasOpSize || Instrux->Exs.w)) + { + nextIndex = 4; + } + else if (NULL != pTable->Table[5]) + { + nextIndex = 5; + } + } + + pTable = (const ND_TABLE *)pTable->Table[nextIndex]; + } + break; + + case ND_ILUT_ASIZE: + { + static const uint8_t indexes[3] = {ND_ILUT_INDEX_ASIZE_16, ND_ILUT_INDEX_ASIZE_32, ND_ILUT_INDEX_ASIZE_64}; + + nextIndex = ND_ILUT_INDEX_ASIZE_NONE; + + if (NULL != pTable->Table[indexes[Instrux->AddrMode]]) + { + nextIndex = indexes[Instrux->AddrMode]; + } + + pTable = (const ND_TABLE *)pTable->Table[nextIndex]; + } + break; + + case ND_ILUT_AUXILIARY: + // Auxiliary redirection. Default to table[0] if nothing matches. + if (Instrux->HasRex && (NULL != pTable->Table[ND_ILUT_INDEX_AUX_REX])) + { + nextIndex = ND_ILUT_INDEX_AUX_REX; + } + else if (Instrux->HasRex && Instrux->Rex.w && (NULL != pTable->Table[ND_ILUT_INDEX_AUX_REXW])) + { + nextIndex = ND_ILUT_INDEX_AUX_REXW; + } + else if ((Instrux->DefCode == ND_CODE_64) && (NULL != pTable->Table[ND_ILUT_INDEX_AUX_O64])) + { + nextIndex = ND_ILUT_INDEX_AUX_O64; + } + else if (Instrux->Rep == ND_PREFIX_G1_REPE_REPZ && (NULL != pTable->Table[ND_ILUT_INDEX_AUX_F3])) + { + nextIndex = ND_ILUT_INDEX_AUX_F3; + } + else if ((Instrux->Rep != 0) && (NULL != pTable->Table[ND_ILUT_INDEX_AUX_REP])) + { + nextIndex = ND_ILUT_INDEX_AUX_REP; + } + else + { + nextIndex = ND_ILUT_INDEX_AUX_NONE; + } + pTable = (const ND_TABLE *)pTable->Table[nextIndex]; + break; + + case ND_ILUT_VENDOR: + // Vendor redirection. Go to the vendor specific entry. + if (NULL != pTable->Table[Vendor]) + { + pTable = (const ND_TABLE *)pTable->Table[Vendor]; + } + else + { + pTable = (const ND_TABLE *)pTable->Table[ND_VEND_ANY]; + } + break; + + case ND_ILUT_VEX_MMMMM: + pTable = (const ND_TABLE *)pTable->Table[Instrux->Exs.m]; + break; + + case ND_ILUT_VEX_PP: + pTable = (const ND_TABLE *)pTable->Table[Instrux->Exs.p]; + break; + + case ND_ILUT_VEX_L: + if (Instrux->HasEvex && Instrux->Exs.bm) + { + // We have evex; we need to fetch the modrm now, because we have to make sure we don't have SAE or ER; + // if we do have SAE or ER, we have to check the modrm byte and see if it is a reg-reg form (mod = 3), + // in which case L'L is forced to the maximum vector length of the instruction. We know for sure that + // all EVEX instructions have modrm. + if (!Instrux->HasModRm) + { + // Fetch modrm + status = NdFetchModrmAndSib(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + stop = true; + break; + } + + // Fetch displacement. + status = NdFetchDisplacement(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + stop = true; + break; + } + } + + if (3 == Instrux->ModRm.mod) + { + // We use the maximum vector length of the instruction. If the instruction does not support + // SAE or ER, a #UD would be generated. We check for this later. + if (NULL != pTable->Table[2]) + { + pTable = (const ND_TABLE *)pTable->Table[2]; + } + else if (NULL != pTable->Table[1]) + { + pTable = (const ND_TABLE *)pTable->Table[1]; + } + else + { + pTable = (const ND_TABLE *)pTable->Table[0]; + } + } + else + { + // Mod is mem, we simply use L'L for indexing, as no SAE or ER can be present. + pTable = (const ND_TABLE *)pTable->Table[Instrux->Exs.l]; + } + } + else + { + pTable = (const ND_TABLE *)pTable->Table[Instrux->Exs.l]; + } + break; + + case ND_ILUT_VEX_W: + pTable = (const ND_TABLE *)pTable->Table[Instrux->Exs.w]; + break; + + default: + status = ND_STATUS_INTERNAL_ERROR; + stop = true; + break; + } + } + + if (!ND_SUCCESS(status)) + { + goto cleanup_and_exit; + } + + if (NULL != pIns) + { + // Bingo! Valid instruction found for the encoding. If Modrm is needed and we didn't fetch it - do it now. + if ((pIns->Attributes & ND_FLAG_MODRM) && (!Instrux->HasModRm)) + { + if (0 == (pIns->Attributes & ND_FLAG_MFR)) + { + // Fetch Mod R/M and SIB. + status = NdFetchModrmAndSib(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + goto cleanup_and_exit; + } + + // Fetch displacement. + status = NdFetchDisplacement(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + goto cleanup_and_exit; + } + } + else + { + // Handle special MOV with control and debug registers - the mod is always forced to register. SIB + // and displacement is ignored. + status = NdFetchModrm(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + goto cleanup_and_exit; + } + } + } + + // Store primary opcode. + Instrux->PrimaryOpCode = Instrux->OpCodeBytes[Instrux->OpLength - 1]; + + Instrux->MainOpOffset = ND_IS_3DNOW(Instrux) ? + Instrux->Length - 1 : Instrux->OpOffset + Instrux->OpLength - 1; + + // Make sure the instruction is valid in the given mode. + if ((ND_CODE_64 == Instrux->DefCode) && (pIns->Attributes & ND_FLAG_I64)) + { + status = ND_STATUS_INVALID_ENCODING_IN_MODE; + } + + if ((ND_CODE_64 != Instrux->DefCode) && (pIns->Attributes & ND_FLAG_O64)) + { + status = ND_STATUS_INVALID_ENCODING_IN_MODE; + } + } + else + { + status = ND_STATUS_INVALID_ENCODING; + } + +cleanup_and_exit: + *InsDef = pIns; + + return status; +} + + + +// +// NdGetVectorLength +// +static __forceinline NDSTATUS +NdGetVectorLength( + INSTRUX *Instrux + ) +{ + if (Instrux->HasEvex && Instrux->Exs.bm && (Instrux->ModRm.mod == 3) && + (ND_ER_SUPPORT(Instrux) || ND_SAE_SUPPORT(Instrux))) + { + // Embedded rounding present, force the vector length to 512. + if ((Instrux->TupleType == ND_TUPLE_T1S) || (Instrux->TupleType == ND_TUPLE_T1F)) + { + Instrux->VecMode = Instrux->EfVecMode = ND_VECM_128; + } + else + { + Instrux->VecMode = Instrux->EfVecMode = ND_VECM_512; + } + + return ND_STATUS_SUCCESS; + } + + // Decode VEX vector length. Also take into consideration the "ignore L" flag. + switch (Instrux->Exs.l) + { + case 0: + Instrux->VecMode = ND_VECM_128; + Instrux->EfVecMode = ND_VECM_128; + break; + case 1: + Instrux->VecMode = ND_VECM_256; + Instrux->EfVecMode = (Instrux->Attributes & ND_FLAG_LIG) ? ND_VECM_128 : ND_VECM_256; + break; + case 2: + Instrux->VecMode = ND_VECM_512; + Instrux->EfVecMode = (Instrux->Attributes & ND_FLAG_LIG) ? ND_VECM_128 : ND_VECM_512; + break; + default: + return ND_STATUS_INVALID_INSTRUX; + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdGetAddrAndOpMode +// +static __forceinline NDSTATUS +NdGetAddrAndOpMode( + INSTRUX *Instrux + ) +{ + // Fill in addressing mode & default op size. + switch (Instrux->DefCode) + { + case ND_CODE_16: + Instrux->AddrMode = Instrux->HasAddrSize ? ND_ADDR_32 : ND_ADDR_16; + Instrux->OpMode = Instrux->HasOpSize ? ND_OPSZ_32 : ND_OPSZ_16; + break; + case ND_CODE_32: + Instrux->AddrMode = Instrux->HasAddrSize ? ND_ADDR_16 : ND_ADDR_32; + Instrux->OpMode = Instrux->HasOpSize ? ND_OPSZ_16 : ND_OPSZ_32; + break; + case ND_CODE_64: + Instrux->AddrMode = Instrux->HasAddrSize ? ND_ADDR_32 : ND_ADDR_64; + Instrux->OpMode = Instrux->Exs.w ? ND_OPSZ_64 : (Instrux->HasOpSize ? ND_OPSZ_16 : ND_OPSZ_32); + break; + default: + return ND_STATUS_INVALID_INSTRUX; + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdGetEffectiveOpMode +// +static __forceinline NDSTATUS +NdGetEffectiveOpMode( + INSTRUX *Instrux + ) +{ + static const uint8_t szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT }; + bool width, f64, d64, has66; + + // Extract the flags. + width = (0 != Instrux->Exs.w) && !(Instrux->Attributes & ND_FLAG_WIG); + // In 64 bit mode, the operand is forced to 64 bit. Size-changing prefixes are ignored. + f64 = 0 != (Instrux->Attributes & ND_FLAG_F64); + // In 64 bit mode, the operand defaults to 64 bit No 32 bit form of the instruction exists. + d64 = 0 != (Instrux->Attributes & ND_FLAG_D64); + // Check if 0x66 is indeed interpreted as a size changing prefix. Note that if 0x66 is a mandatory prefix, + // then it won't be interpreted as a size changing prefix. However, there is an exception: MOVBE and CRC32 + // have mandatory 0xF2, and 0x66 is in fact a size changing prefix. + has66 = Instrux->HasOpSize && (!Instrux->HasMandatory66 || (Instrux->Attributes & ND_FLAG_S66)); + + // Fill in the effective operand size. + switch (Instrux->DefCode) + { + case ND_CODE_16: + Instrux->EfOpMode = has66 ? ND_OPSZ_32 : ND_OPSZ_16; + break; + case ND_CODE_32: + Instrux->EfOpMode = has66 ? ND_OPSZ_16 : ND_OPSZ_32; + break; + case ND_CODE_64: + Instrux->EfOpMode = (width || f64 || (d64 && !has66)) ? ND_OPSZ_64 : (has66 ? ND_OPSZ_16 : ND_OPSZ_32); + break; + default: + return ND_STATUS_INVALID_INSTRUX; + } + + // Fill in the default word length. It can't be more than 8 bytes. + Instrux->WordLength = szLut[Instrux->EfOpMode]; + + return ND_STATUS_SUCCESS; +} + + +// +// NdValidateInstruction +// +static __forceinline NDSTATUS +NdValidateInstruction( + INSTRUX *Instrux + ) +{ + // If LOCK is present, make sure that the instruction 1. supports LOCKing and 2. the destination is memory. + // A special case are MOV to/from CRs, on AMD, in 16/32 bit mode. + if (Instrux->HasLock && (0 == (Instrux->Attributes & ND_FLAG_LOCK_SPECIAL) || (ND_CODE_64 == Instrux->DefCode)) && + (!ND_LOCK_SUPPORT(Instrux) || (Instrux->Operands[0].Type != ND_OP_MEM))) + { + return ND_STATUS_BAD_LOCK_PREFIX; + } + + // Some instructions (example: PTWRITE) do not accept the 0x66 prefix. + if (Instrux->HasOpSize && (0 != (Instrux->Attributes & ND_FLAG_NO66))) + { + return ND_STATUS_66_NOT_ACCEPTED; + } + + // 16 bit addressing is checked when decoding the memory operand (if present). + // RIP-relative addressing is checked when decoding the memory operand (if present). + // Register validity is checked when decoding the said register. + // Memory/register encoding for instructions which don't support it is checked when decoding the operand. + + // VEX/EVEX validations. + if (ND_ENCM_LEGACY != Instrux->EncMode) + { + // Instructions that don't use VEX/XOP vvvv field must set it to 1111b/0, otherwise a #UD will be generated. + if ((0 == (Instrux->OperandsEncodingMap & (1 << ND_OPE_V))) && (0 != Instrux->Exs.v)) + { + return ND_STATUS_VEX_VVVV_MUST_BE_ZERO; + } + + // Some instructions don't support 128 bit vectors. + if ((ND_VECM_128 == Instrux->EfVecMode) && (0 != (Instrux->Attributes & ND_FLAG_NOL0))) + { + return ND_STATUS_INVALID_ENCODING; + } + + // VSIB instructions have a restriction: the same vector register can't be used by more than one operand. + if (ND_HAS_VSIB(Instrux)) + { + uint8_t usedVects[32] = { 0 }; + + for (uint32_t i = 0; i < Instrux->OperandsCount; i++) + { + if (Instrux->Operands[i].Type == ND_OP_REG && Instrux->Operands[i].Info.Register.Type == ND_REG_SSE) + { + if (++usedVects[Instrux->Operands[i].Info.Register.Reg] > 1) + { + return ND_STATUS_INVALID_VSIB_REGS; + } + } + else if (Instrux->Operands[i].Type == ND_OP_MEM) + { + if (++usedVects[Instrux->Operands[i].Info.Memory.Index] > 1) + { + return ND_STATUS_INVALID_VSIB_REGS; + } + } + } + } + + // Handle AMX exception class. + if (Instrux->ExceptionClass == ND_EXC_AMX) + { + if (Instrux->ExceptionType == ND_EXT_AMX_E4) + { + // #UD if srcdest == src1, srcdest == src2 or src1 == src2. All three operands are tile regs. + if (Instrux->Operands[0].Info.Register.Reg == Instrux->Operands[1].Info.Register.Reg || + Instrux->Operands[0].Info.Register.Reg == Instrux->Operands[2].Info.Register.Reg || + Instrux->Operands[1].Info.Register.Reg == Instrux->Operands[2].Info.Register.Reg) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + } + else + { + // #UD if vex.vvvv is not 0 (0b1111 negated) for all other exception classes, as they do not use it. + if (Instrux->Exs.v != 0) + { + return ND_STATUS_VEX_VVVV_MUST_BE_ZERO; + } + } + } + + if (Instrux->HasEvex) + { + // Instructions that don't support masking must have EVEX.aaa = 0. + if (!ND_MASK_SUPPORT(Instrux) && (0 != Instrux->Exs.k)) + { + return ND_STATUS_MASK_NOT_SUPPORTED; + } + + // Some instructions have mandatory masking, and using k0 as a mask triggers #UD. + if ((Instrux->Attributes & ND_FLAG_MMASK) && (0 == Instrux->Exs.k)) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + + // EVEX.z must be 0 if: + // - zeroing is not supported by the instruction. + // - zeroing is supported, but the destination is memory. + // If zeroing is supported and the mask is 0, then zeroing is ignored. + if (0 != Instrux->Exs.z) + { + if (!ND_ZERO_SUPPORT(Instrux)) + { + return ND_STATUS_ZEROING_NOT_SUPPORTED; + } + + if (Instrux->Operands[0].Type == ND_OP_MEM) + { + return ND_STATUS_ZEROING_ON_MEMORY; + } + } + + // EVEX.b must be 0 if SAE/ER is not used. + if (Instrux->Exs.bm && (Instrux->ModRm.mod == 3) && !ND_SAE_SUPPORT(Instrux) && !ND_ER_SUPPORT(Instrux)) + { + return ND_STATUS_ER_SAE_NOT_SUPPORTED; + } + + // EVEX.b must be 0 if broadcast is not supported. + if (Instrux->Exs.bm && (Instrux->ModRm.mod != 3) && !ND_BROADCAST_SUPPORT(Instrux)) + { + return ND_STATUS_BROADCAST_NOT_SUPPORTED; + } + } + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdDecodeEx2 +// +NDSTATUS +NdDecodeEx2( + INSTRUX *Instrux, + const uint8_t *Code, + size_t Size, + uint8_t DefCode, + uint8_t DefData, + uint8_t DefStack, + uint8_t Vendor + ) +{ + NDSTATUS status; + PND_INSTRUCTION pIns; + uint32_t opIndex; + + // pre-init + status = ND_STATUS_SUCCESS; + pIns = NULL; + opIndex = 0; + + // validate + if (NULL == Instrux) + { + return ND_STATUS_INVALID_PARAMETER; + } + + if (NULL == Code) + { + return ND_STATUS_INVALID_PARAMETER; + } + + if (Size == 0) + { + return ND_STATUS_INVALID_PARAMETER; + } + + if (ND_CODE_64 < DefCode) + { + return ND_STATUS_INVALID_PARAMETER; + } + + if (ND_DATA_64 < DefData) + { + return ND_STATUS_INVALID_PARAMETER; + } + + if (ND_VEND_CYRIX < Vendor) + { + return ND_STATUS_INVALID_PARAMETER; + } + + // Initialize with zero. + nd_memzero(Instrux, sizeof(INSTRUX)); + + Instrux->DefCode = DefCode; + Instrux->DefData = DefData; + Instrux->DefStack = DefStack; + + // Fetch prefixes. We peek at the first byte, if that's not a prefix, there's no need to call the main decoder. + if (ND_PREF_CODE_NONE != gPrefixesMap[Code[0]]) + { + status = NdFetchPrefixes(Instrux, Code, 0, Size); + if (!ND_SUCCESS(status)) + { + return status; + } + } + + // Get addressing mode & operand size. + status = NdGetAddrAndOpMode(Instrux); + if (!ND_SUCCESS(status)) + { + return status; + } + + // Start iterating the tables, in order to extract the instruction entry. + status = NdFindInstruction(Instrux, Code, Instrux->Length, Size, Vendor, &pIns); + if (!ND_SUCCESS(status)) + { + return status; + } + + // Instruction found, copy information inside the Instrux. + Instrux->Attributes = pIns->Attributes; + Instrux->Instruction = Instrux->Iclass = (ND_INS_CLASS)pIns->Instruction; + Instrux->Category = (ND_INS_CATEGORY)pIns->Category; + Instrux->IsaSet = (ND_INS_SET)pIns->IsaSet; + Instrux->FlagsAccess.Undefined.Raw = pIns->SetFlags & pIns->ClearedFlags; + Instrux->FlagsAccess.Tested.Raw = pIns->TestedFlags; + Instrux->FlagsAccess.Modified.Raw = pIns->ModifiedFlags; + Instrux->FlagsAccess.Set.Raw = pIns->SetFlags ^ Instrux->FlagsAccess.Undefined.Raw; + Instrux->FlagsAccess.Cleared.Raw = pIns->ClearedFlags ^ Instrux->FlagsAccess.Undefined.Raw; + Instrux->CpuidFlag.Flag = pIns->CpuidFlag; + Instrux->ValidModes.Raw = pIns->ValidModes; + Instrux->ValidPrefixes.Raw = pIns->ValidPrefixes; + Instrux->ValidDecorators.Raw = pIns->ValidDecorators; + *((uint8_t*)&Instrux->FpuFlagsAccess) = pIns->FpuFlags; + // Valid for EVEX, VEX and SSE instructions only. A value of 0 means it's not used. + Instrux->ExceptionClass = pIns->ExcClass; + Instrux->ExceptionType = pIns->ExcType; + // Used only by EVEX instructions. + Instrux->TupleType = pIns->TupleType; + + // Copy the mnemonic, up until the NULL terminator. + for (size_t i = 0; i < sizeof(Instrux->Mnemonic); i++) + { + Instrux->Mnemonic[i] = gMnemonics[pIns->Mnemonic][i]; + if (Instrux->Mnemonic[i] == 0) + { + break; + } + } + + // Get effective operand mode. + status = NdGetEffectiveOpMode(Instrux); + if (!ND_SUCCESS(status)) + { + return status; + } + + if (ND_HAS_VECTOR(Instrux)) + { + // Get vector length. + status = NdGetVectorLength(Instrux); + if (!ND_SUCCESS(status)) + { + return status; + } + } + + // Handle condition byte, if present. + if (ND_HAS_SSE_CONDITION(Instrux)) + { + Instrux->SseCondition = Instrux->Immediate1 & 0x1F; + } + + // Handle predicate, if present. + if (ND_HAS_CONDITION(Instrux)) + { + Instrux->Condition = Instrux->Predicate = Instrux->PrimaryOpCode & 0xF; + } + + if (0 != pIns->ValidDecorators) + { + // Check for suppress all exceptions. + if ((Instrux->ValidDecorators.Sae) && (Instrux->Exs.bm) && (Instrux->ModRm.mod == 3)) + { + Instrux->HasSae = true; + } + + // Check for embedded rounding. This is available only in reg-reg encodings. Also, if embedded + // rounding is used, the vector length is forced to 512 bit, as the + if ((Instrux->ValidDecorators.Er) && (Instrux->Exs.bm) && (Instrux->ModRm.mod == 3)) + { + Instrux->HasEr = true; + Instrux->HasSae = true; + Instrux->RoundingMode = (uint8_t)Instrux->Exs.l; + } + } + + Instrux->ExpOperandsCount = ND_EXP_OPS_CNT(pIns->OpsCount); + Instrux->OperandsCount = Instrux->ExpOperandsCount + ND_IMP_OPS_CNT(pIns->OpsCount); + + // And now decode each operand. + for (opIndex = 0; opIndex < Instrux->OperandsCount; ++opIndex) + { + status = NdParseOperand(Instrux, Code, Instrux->Length, Size, opIndex, pIns->Operands[opIndex]); + if (!ND_SUCCESS(status)) + { + return status; + } + } + + // Check if the instruction is XACQUIRE or XRELEASE enabled. + if ((Instrux->Rep != 0) && (Instrux->HasLock || (!!Instrux->ValidPrefixes.HleNoLock)) && + (Instrux->Operands[0].Type == ND_OP_MEM)) + { + if ((ND_XACQUIRE_SUPPORT(Instrux) || ND_HLE_SUPPORT(Instrux)) && (Instrux->Rep == ND_PREFIX_G1_XACQUIRE)) + { + Instrux->IsXacquireEnabled = true; + } + else if ((ND_XRELEASE_SUPPORT(Instrux) || ND_HLE_SUPPORT(Instrux)) && (Instrux->Rep == ND_PREFIX_G1_XRELEASE)) + { + Instrux->IsXreleaseEnabled = true; + } + } + + // Check if the instruction is REPed. + Instrux->IsRepeated = ((Instrux->Rep != 0) && (ND_REP_SUPPORT(Instrux) || ND_REPC_SUPPORT(Instrux))); + + // Check if the instruction is CET tracked. The do not track prefix (0x3E) works only for indirect near JMP and CALL + // via register. It is always enabled for indirect far JMP and CALL or near indirect JMP and CALL via memoery. + Instrux->IsCetTracked = ND_HAS_CETT(Instrux) && ((!ND_DNT_SUPPORT(Instrux)) || + (Instrux->Seg != ND_PREFIX_G2_NO_TRACK) || + (Instrux->HasModRm && (Instrux->ModRm.mod != 3))); + + // Do instruction validations. These checks are made in order to filter out encodings that would normally + // be invalid and would generate #UD. + status = NdValidateInstruction(Instrux); + if (!ND_SUCCESS(status)) + { + return status; + } + + // Copy the instruction bytes. + for (opIndex = 0; opIndex < Instrux->Length; opIndex++) + { + Instrux->InstructionBytes[opIndex] = Code[opIndex]; + } + + // All done! Instruction successfully decoded! + return ND_STATUS_SUCCESS; +} + + +// +// NdDecodeEx +// +NDSTATUS +NdDecodeEx( + INSTRUX *Instrux, + const uint8_t *Code, + size_t Size, + uint8_t DefCode, + uint8_t DefData + ) +{ + return NdDecodeEx2(Instrux, Code, Size, DefCode, DefData, DefCode, ND_VEND_ANY); +} + + +// +// NdDecode +// +NDSTATUS +NdDecode( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t DefCode, + uint8_t DefData + ) +{ + return NdDecodeEx2(Instrux, Code, ND_MAX_INSTRUCTION_LENGTH, DefCode, DefData, DefCode, ND_VEND_ANY); +} + + +// +// NdToText +// +NDSTATUS +NdToText( + const INSTRUX *Instrux, + uint64_t Rip, + uint32_t BufferSize, + char *Buffer + ) +{ + NDSTATUS status; + char *res, temp[64]; + uint32_t opIndex, opsStored; + const ND_OPERAND *pOp; + bool alignmentStored; + + // pre-init + status = ND_STATUS_SUCCESS; + res = NULL; + opIndex = 0; + opsStored = 0; + pOp = NULL; + alignmentStored = false; + + // Validate args. + if (NULL == Instrux) + { + return ND_STATUS_INVALID_PARAMETER; + } + + if (NULL == Buffer) + { + return ND_STATUS_INVALID_PARAMETER; + } + + if (BufferSize < ND_MIN_BUF_SIZE) + { + return ND_STATUS_INVALID_PARAMETER; + } + + // init the text. + nd_memzero(Buffer, BufferSize); + nd_memzero(temp, sizeof(temp)); + + // First, store the prefixes. + if (Instrux->Rep != 0) + { + // Check for REPZ/REPNZ support, and store prefixes. + if (ND_REPC_SUPPORT(Instrux)) + { + if (Instrux->Rep == ND_PREFIX_G1_REPE_REPZ) + { + res = nd_strcat_s(Buffer, BufferSize, "REPZ "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + else if (Instrux->Rep == ND_PREFIX_G1_REPNE_REPNZ) + { + res = nd_strcat_s(Buffer, BufferSize, "REPNZ "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + } + + // Check for REP support and store prefixes. + if (ND_REP_SUPPORT(Instrux)) + { + if (Instrux->Rep == ND_PREFIX_G1_REPE_REPZ) + { + res = nd_strcat_s(Buffer, BufferSize, "REP "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + else if (Instrux->Rep == ND_PREFIX_G1_REPNE_REPNZ) + { + res = nd_strcat_s(Buffer, BufferSize, "REPNZ "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + } + + if (Instrux->IsXreleaseEnabled) + { + res = nd_strcat_s(Buffer, BufferSize, "XRELEASE "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + else if (Instrux->IsXacquireEnabled) + { + res = nd_strcat_s(Buffer, BufferSize, "XACQUIRE "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + } + + if (Instrux->HasLock) + { + if (ND_LOCK_SUPPORT(Instrux)) + { + res = nd_strcat_s(Buffer, BufferSize, "LOCK "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + } + + if (Instrux->Rep == ND_PREFIX_G1_BND) + { + if (ND_BND_SUPPORT(Instrux)) + { + res = nd_strcat_s(Buffer, BufferSize, "BND "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + } + + if (Instrux->HasSeg && ND_BHINT_SUPPORT(Instrux)) + { + switch (Instrux->Bhint) + { + case ND_PREFIX_G2_BR_TAKEN: + res = nd_strcat_s(Buffer, BufferSize, "BHT "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + + case ND_PREFIX_G2_BR_NOT_TAKEN: + res = nd_strcat_s(Buffer, BufferSize, "BHNT "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + + case ND_PREFIX_G2_BR_ALT: + res = nd_strcat_s(Buffer, BufferSize, "BHALT "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + + default: + break; + } + } + + if (Instrux->HasSeg && ND_DNT_SUPPORT(Instrux)) + { + if (!Instrux->IsCetTracked) + { + res = nd_strcat_s(Buffer, BufferSize, "DNT "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + } + + // Store the mnemonic. + res = nd_strcat_s(Buffer, BufferSize, Instrux->Mnemonic); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + + // Store condition code, if any. + if (ND_HAS_SSE_CONDITION(Instrux)) + { + res = nd_strcat_s(Buffer, BufferSize, gConditionCodes[Instrux->SseCondition]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + + // If there are no explicit operands, we can leave. + if (0 == Instrux->ExpOperandsCount) + { + return ND_STATUS_SUCCESS; + } + + // Now the operands. + for (opIndex = 0; opIndex < Instrux->OperandsCount; opIndex++) + { + status = ND_STATUS_SUCCESS; + + pOp = &Instrux->Operands[opIndex]; + + if (pOp->Type == ND_OP_NOT_PRESENT) + { + break; + } + + if (pOp->Flags.IsDefault) + { + continue; + } + + // If this is a mask operand that has been used as masking for a previous operand, than we + // can safely skip it. We check this by seeing where is the operand encoded. If it's encoded + // in the evex.aaa field, than it is a conventional mask. + if ((pOp->Encoding == ND_OPE_A) && (pOp->Type == ND_OP_REG) && + (pOp->Info.Register.Type == ND_REG_MSK) && (opIndex > 0)) + { + continue; + } + + // Store alignment. + if (!alignmentStored) + { + size_t idx = 0; + + while ((idx < BufferSize) && (Buffer[idx])) + { + idx++; + } + + while ((idx < 9) && (idx + 1 < BufferSize)) + { + Buffer[idx++] = 0x20; + } + + if (idx + 1 < BufferSize) + { + Buffer[idx++] = 0x20; + } + + Buffer[idx] = 0; + + alignmentStored = true; + } + + // Store the comma, if this isn't the first operand. + if (opsStored > 0) + { + res = nd_strcat_s(Buffer, BufferSize, ", "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + + opsStored++; + + switch (pOp->Type) + { + case ND_OP_REG: + switch (pOp->Info.Register.Type) + { + case ND_REG_GPR: + { + if (pOp->Info.Register.Reg >= ND_MAX_GPR_REGS) + { + return ND_STATUS_INVALID_INSTRUX; + } + + // General purpose register. + switch (pOp->Info.Register.Size) + { + case ND_SIZE_8BIT: + // 8 bit register. + if ((Instrux->EncMode != ND_ENCM_LEGACY) || Instrux->HasRex) + { + res = nd_strcat_s(Buffer, BufferSize, gReg8Bit64[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + else + { + res = nd_strcat_s(Buffer, BufferSize, gReg8Bit[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + case ND_SIZE_16BIT: + // 16 bit register. + res = nd_strcat_s(Buffer, BufferSize, gReg16Bit[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + + case ND_SIZE_32BIT: + // 32 bit register. + res = nd_strcat_s(Buffer, BufferSize, gReg32Bit[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + + case ND_SIZE_64BIT: + // 64 bit register. + res = nd_strcat_s(Buffer, BufferSize, gReg64Bit[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + + default: + return ND_STATUS_INVALID_INSTRUX; + } + } + break; + + case ND_REG_SEG: + { + if (pOp->Info.Register.Reg >= ND_MAX_SEG_REGS) + { + return ND_STATUS_INVALID_INSTRUX; + } + + res = nd_strcat_s(Buffer, BufferSize, gRegSeg[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + case ND_REG_FPU: + { + if (pOp->Info.Register.Reg >= ND_MAX_FPU_REGS) + { + return ND_STATUS_INVALID_INSTRUX; + } + + res = nd_strcat_s(Buffer, BufferSize, gRegFpu[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + case ND_REG_MMX: + { + if (pOp->Info.Register.Reg >= ND_MAX_MMX_REGS) + { + return ND_STATUS_INVALID_INSTRUX; + } + + res = nd_strcat_s(Buffer, BufferSize, gRegMmx[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + case ND_REG_SSE: + { + if (pOp->Info.Register.Reg >= ND_MAX_SSE_REGS) + { + return ND_STATUS_INVALID_INSTRUX; + } + + switch (pOp->Info.Register.Size) + { + case ND_SIZE_128BIT: + res = nd_strcat_s(Buffer, BufferSize, gRegXmm[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case ND_SIZE_256BIT: + res = nd_strcat_s(Buffer, BufferSize, gRegYmm[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case ND_SIZE_512BIT: + res = nd_strcat_s(Buffer, BufferSize, gRegZmm[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + default: + return ND_STATUS_INVALID_INSTRUX; + } + } + break; + + case ND_REG_CR: + { + if (pOp->Info.Register.Reg >= ND_MAX_CR_REGS) + { + return ND_STATUS_INVALID_INSTRUX; + } + + res = nd_strcat_s(Buffer, BufferSize, gRegControl[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + case ND_REG_DR: + { + if (pOp->Info.Register.Reg >= ND_MAX_DR_REGS) + { + return ND_STATUS_INVALID_INSTRUX; + } + + res = nd_strcat_s(Buffer, BufferSize, gRegDebug[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + case ND_REG_TR: + { + if (pOp->Info.Register.Reg >= ND_MAX_TR_REGS) + { + return ND_STATUS_INVALID_INSTRUX; + } + + res = nd_strcat_s(Buffer, BufferSize, gRegTest[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + case ND_REG_BND: + { + // Sanity check. + if (pOp->Info.Register.Reg >= ND_MAX_BND_REGS) + { + return ND_STATUS_INVALID_INSTRUX; + } + + res = nd_strcat_s(Buffer, BufferSize, gRegBound[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + case ND_REG_MSK: + { + // Sanity check. + if (pOp->Info.Register.Reg >= ND_MAX_MSK_REGS) + { + return ND_STATUS_INVALID_INSTRUX; + } + + res = nd_strcat_s(Buffer, BufferSize, gRegMask[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + case ND_REG_TILE: + { + // Sanity check. + if (pOp->Info.Register.Reg >= ND_MAX_TILE_REGS) + { + return ND_STATUS_INVALID_INSTRUX; + } + + res = nd_strcat_s(Buffer, BufferSize, gRegTile[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + default: + break; + } + + if (pOp->Info.Register.Count > 1) + { + status = NdSprintf(temp, sizeof(temp), "+%d", pOp->Info.Register.Count - 1); + if (!ND_SUCCESS(status)) + { + return status; + } + + res = nd_strcat_s(Buffer, BufferSize, temp); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + + break; + + case ND_OP_BANK: + // Nothing to show. + break; + + case ND_OP_CONST: + { + // Implicit constant + status = NdSprintf(temp, sizeof(temp), "%d", pOp->Info.Constant.Const); + if (!ND_SUCCESS(status)) + { + return status; + } + + res = nd_strcat_s(Buffer, BufferSize, temp); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + case ND_OP_IMM: + { + switch (pOp->RawSize) + { + case 1: + status = NdSprintf(temp, sizeof(temp), "0x%02x", (uint8_t)pOp->Info.Immediate.Imm); + break; + case 2: + status = NdSprintf(temp, sizeof(temp), "0x%04x", (uint16_t)pOp->Info.Immediate.Imm); + break; + case 4: + status = NdSprintf(temp, sizeof(temp), "0x%08x", (uint32_t)pOp->Info.Immediate.Imm); + break; + case 8: + status = NdSprintf(temp, sizeof(temp), "0x%016llx", (uint64_t)pOp->Info.Immediate.Imm); + break; + } + if (!ND_SUCCESS(status)) + { + return status; + } + + res = nd_strcat_s(Buffer, BufferSize, temp); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + case ND_OP_OFFS: + { + uint64_t dest = Rip + Instrux->Length + pOp->Info.RelativeOffset.Rel; + + // Truncate to the actual word length. + switch (Instrux->WordLength) + { + case 2: + dest &= 0xFFFF; + break; + case 4: + dest &= 0xFFFFFFFF; + break; + default: + break; + } + + status = NdSprintf(temp, sizeof(temp), "0x%llx", dest); + if (!ND_SUCCESS(status)) + { + return status; + } + + res = nd_strcat_s(Buffer, BufferSize, temp); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + case ND_OP_ADDR: + { + switch (Instrux->AddrLength) + { + case 4: + status = NdSprintf(temp, sizeof(temp), "0x%04x:0x%04x", + pOp->Info.Address.BaseSeg, (uint16_t)pOp->Info.Address.Offset); + break; + case 6: + status = NdSprintf(temp, sizeof(temp), "0x%04x:0x%08x", + pOp->Info.Address.BaseSeg, (uint32_t)pOp->Info.Address.Offset); + break; + case 10: + status = NdSprintf(temp, sizeof(temp), "0x%04x:0x%016llx", + pOp->Info.Address.BaseSeg, (uint64_t)pOp->Info.Address.Offset); + break; + default: + return ND_STATUS_INVALID_INSTRUX; + } + + res = nd_strcat_s(Buffer, BufferSize, temp); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + case ND_OP_MEM: + { + // Prepend the size. + switch (pOp->Size) + { + case 1: + res = nd_strcat_s(Buffer, BufferSize, "byte ptr "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case 2: + res = nd_strcat_s(Buffer, BufferSize, "word ptr "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case 4: + res = nd_strcat_s(Buffer, BufferSize, "dword ptr "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case 6: + res = nd_strcat_s(Buffer, BufferSize, "fword ptr "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case 8: + res = nd_strcat_s(Buffer, BufferSize, "qword ptr "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case 10: + res = nd_strcat_s(Buffer, BufferSize, "tbyte ptr "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case 16: + res = nd_strcat_s(Buffer, BufferSize, "xmmword ptr "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case 32: + res = nd_strcat_s(Buffer, BufferSize, "ymmword ptr "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case 64: + res = nd_strcat_s(Buffer, BufferSize, "zmmword ptr "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + default: + break; + } + + // Perpend the segment, only if it is overridden via a prefix. + if (pOp->Info.Memory.HasSeg && Instrux->HasSeg) + { + if (pOp->Info.Memory.Seg >= ND_MAX_SEG_REGS) + { + return ND_STATUS_INVALID_INSTRUX; + } + + if ((ND_CODE_64 != Instrux->DefCode) || (REG_FS == pOp->Info.Memory.Seg) || + (REG_GS == pOp->Info.Memory.Seg)) + { + res = nd_strcat_s(Buffer, BufferSize, gRegSeg[pOp->Info.Memory.Seg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + + res = nd_strcat_s(Buffer, BufferSize, ":"); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + } + + // Prepend the "[" + res = nd_strcat_s(Buffer, BufferSize, "["); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + + // Base, if any. + if (pOp->Info.Memory.HasBase) + { + if (pOp->Info.Memory.Base >= ND_MAX_GPR_REGS) + { + return ND_STATUS_INVALID_INSTRUX; + } + + switch (pOp->Info.Memory.BaseSize) + { + case ND_SIZE_8BIT: + res = nd_strcat_s(Buffer, BufferSize, gReg8Bit[pOp->Info.Memory.Base]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case ND_SIZE_16BIT: + res = nd_strcat_s(Buffer, BufferSize, gReg16Bit[pOp->Info.Memory.Base]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case ND_SIZE_32BIT: + res = nd_strcat_s(Buffer, BufferSize, gReg32Bit[pOp->Info.Memory.Base]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case ND_SIZE_64BIT: + res = nd_strcat_s(Buffer, BufferSize, gReg64Bit[pOp->Info.Memory.Base]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + default: + return ND_STATUS_INVALID_INSTRUX; + } + } + + // Index, if any. Special treatment for VSIB addressing. Also, perpend a "+" if base is present. + if (pOp->Info.Memory.HasIndex) + { + if (pOp->Info.Memory.Index >= (pOp->Info.Memory.IsVsib ? ND_MAX_SSE_REGS : ND_MAX_GPR_REGS)) + { + return ND_STATUS_INVALID_INSTRUX; + } + + if (pOp->Info.Memory.HasBase) + { + res = nd_strcat_s(Buffer, BufferSize, "+"); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + + switch (pOp->Info.Memory.IndexSize) + { + case ND_SIZE_8BIT: + res = nd_strcat_s(Buffer, BufferSize, gReg8Bit[pOp->Info.Memory.Index]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case ND_SIZE_16BIT: + res = nd_strcat_s(Buffer, BufferSize, gReg16Bit[pOp->Info.Memory.Index]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case ND_SIZE_32BIT: + res = nd_strcat_s(Buffer, BufferSize, gReg32Bit[pOp->Info.Memory.Index]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case ND_SIZE_64BIT: + res = nd_strcat_s(Buffer, BufferSize, gReg64Bit[pOp->Info.Memory.Index]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case ND_SIZE_128BIT: + res = nd_strcat_s(Buffer, BufferSize, gRegXmm[pOp->Info.Memory.Index]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case ND_SIZE_256BIT: + res = nd_strcat_s(Buffer, BufferSize, gRegYmm[pOp->Info.Memory.Index]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case ND_SIZE_512BIT: + res = nd_strcat_s(Buffer, BufferSize, gRegZmm[pOp->Info.Memory.Index]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + default: + return ND_STATUS_INVALID_INSTRUX; + } + + // If index is present, scale is also present. + if (pOp->Info.Memory.Scale != 1 && !pOp->Info.Memory.IsMib) + { + status = NdSprintf(temp, sizeof(temp), "*%d", pOp->Info.Memory.Scale); + if (!ND_SUCCESS(status)) + { + return status; + } + + res = nd_strcat_s(Buffer, BufferSize, temp); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + } + + // Handle displacement. + if (pOp->Info.Memory.HasDisp) + { + uint64_t normDisp, disp; + + disp = pOp->Info.Memory.Disp; + + // If this is direct addressing (O operand) or we don't have base or index, than we don't normalize + // the displacement, since it is used as a direct offset. Note that the second condition also + // includes the RIP-relative case. + if (pOp->Info.Memory.IsDirect || !(pOp->Info.Memory.HasBase || pOp->Info.Memory.HasIndex)) + { + normDisp = disp; + } + else + { + switch (pOp->Info.Memory.DispSize) + { + case 1: + normDisp = ((disp & 0x80) ? ~((uint8_t)disp) + 1UL : disp) & 0xFF; + break; + case 2: + normDisp = ((disp & 0x8000) ? ~((uint16_t)disp) + 1UL : disp) & 0xFFFF; + break; + case 4: + normDisp = ((disp & 0x80000000) ? ~((uint32_t)disp) + 1 : disp) & 0xFFFFFFFF; + break; + default: + normDisp = disp; + break; + } + + // Handle compressed displacement. It is fine to cast the normDisp to uint32_t, as the + // compressed displacement only works with uint8_t displacements. Also, in this phase, + // the normDisp is converted to a positive quantity, so no sign-extension is needed. + if (pOp->Info.Memory.HasCompDisp) + { + normDisp = (uint32_t)normDisp * pOp->Info.Memory.CompDispSize; + } + } + + + // Now displacement. + if (pOp->Info.Memory.HasBase || pOp->Info.Memory.HasIndex) + { + res = nd_strcat_s(Buffer, BufferSize, Instrux->SignDisp ? "-" : "+"); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + + if (pOp->Info.Memory.IsRipRel) + { + status = NdSprintf(temp, sizeof(temp), "rel 0x%llx", disp + Rip + Instrux->Length); + } + else + { + uint8_t trimSize; + + trimSize = (Instrux->AddrMode == ND_ADDR_16) ? 2 : ((Instrux->AddrMode == ND_ADDR_32) ? 4 : 8); + + // Truncate the displacement size to the size of the address length. + normDisp = ND_TRIM(trimSize, normDisp); + + status = NdSprintf(temp, sizeof(temp), "0x%llx", normDisp); + } + if (!ND_SUCCESS(status)) + { + return status; + } + + res = nd_strcat_s(Buffer, BufferSize, temp); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + + // And the ending "]" + res = nd_strcat_s(Buffer, BufferSize, "]"); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + default: + return ND_STATUS_INVALID_INSTRUX; + } + + // Handle memory broadcast. + if (pOp->Decorator.HasBroadcast) + { + status = NdSprintf(temp, sizeof(temp), "{1to%d}", pOp->Decorator.Broadcast.Count); + if (!ND_SUCCESS(status)) + { + return status; + } + + res = nd_strcat_s(Buffer, BufferSize, temp); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + + // Handle masking. + if (pOp->Decorator.HasMask) + { + if (pOp->Decorator.Mask.Msk >= ND_MAX_MSK_REGS) + { + return ND_STATUS_INVALID_INSTRUX; + } + + status = NdSprintf(temp, sizeof(temp), "{%s}", gRegMask[pOp->Decorator.Mask.Msk]); + if (!ND_SUCCESS(status)) + { + return status; + } + + res = nd_strcat_s(Buffer, BufferSize, temp); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + + // Handle zeroing. Note that zeroing without masking is ignored. + if (pOp->Decorator.HasZero && pOp->Decorator.HasMask) + { + res = nd_strcat_s(Buffer, BufferSize, "{z}"); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + + // Append Suppress All Exceptions decorator. + if (pOp->Decorator.HasSae && !pOp->Decorator.HasEr) + { + // ER implies SAE, so if we have ER, we will list that. + res = nd_strcat_s(Buffer, BufferSize, ", {sae}"); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + + // Append Embedded Rounding decorator. + if (pOp->Decorator.HasEr) + { + if (Instrux->RoundingMode >= 4) + { + return ND_STATUS_INVALID_INSTRUX; + } + + status = NdSprintf(temp, sizeof(temp), ", {%s-sae}", gEmbeddedRounding[Instrux->RoundingMode]); + if (!ND_SUCCESS(status)) + { + return status; + } + + res = nd_strcat_s(Buffer, BufferSize, temp); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdIsInstruxRipRelative +// +bool +NdIsInstruxRipRelative( + const INSTRUX *Instrux + ) +// +// Provided for backwards compatibility with existing code that uses disasm 1.0 +// +{ + if (NULL == Instrux) + { + return false; + } + else + { + return Instrux->IsRipRelative; + } +} + + +// +// NdGetFullAccessMap +// +NDSTATUS +NdGetFullAccessMap( + const INSTRUX *Instrux, + ND_ACCESS_MAP *AccessMap + ) +{ + uint32_t i; + const ND_OPERAND *pOp; + + // pre-init + i = 0; + pOp = NULL; + + // validate + if (NULL == Instrux) + { + return ND_STATUS_INVALID_PARAMETER; + } + + if (NULL == AccessMap) + { + return ND_STATUS_INVALID_PARAMETER; + } + + for (i = 0; i < Instrux->OperandsCount; i++) + { + pOp = &Instrux->Operands[i]; + + if (ND_OP_MEM == pOp->Type) + { + if (pOp->Info.Memory.IsStack) + { + AccessMap->StackAccess |= pOp->Access.Access; + AccessMap->GprAccess[REG_RSP] |= ND_ACCESS_READ|ND_ACCESS_WRITE; + AccessMap->SegAccess[REG_SS] |= ND_ACCESS_READ; + } + else + { + AccessMap->MemAccess |= pOp->Access.Access; + + if (pOp->Info.Memory.HasSeg) + { + AccessMap->SegAccess[pOp->Info.Memory.Seg] |= ND_ACCESS_READ; + } + + if (pOp->Info.Memory.HasBase) + { + AccessMap->GprAccess[pOp->Info.Memory.Base] |= ND_ACCESS_READ; + } + + if (pOp->Info.Memory.HasIndex) + { + if (pOp->Info.Memory.IsVsib) + { + AccessMap->SseAccess[pOp->Info.Memory.Index] |= ND_ACCESS_READ; + } + else + { + AccessMap->GprAccess[pOp->Info.Memory.Index] |= ND_ACCESS_READ; + } + } + } + } + else if (ND_OP_REG == pOp->Type) + { + switch (pOp->Info.Register.Type) + { + case ND_REG_GPR: + { + uint8_t k; + + for (k = 0; k < pOp->Info.Register.Count; k++) + { + AccessMap->GprAccess[pOp->Info.Register.Reg + k] |= pOp->Access.Access; + } + } + break; + case ND_REG_SEG: + AccessMap->SegAccess[pOp->Info.Register.Reg] |= pOp->Access.Access; + break; + case ND_REG_FPU: + AccessMap->FpuAccess[pOp->Info.Register.Reg] |= pOp->Access.Access; + break; + case ND_REG_MMX: + AccessMap->MmxAccess[pOp->Info.Register.Reg] |= pOp->Access.Access; + break; + case ND_REG_SSE: + { + uint8_t k; + + for (k = 0; k < pOp->Info.Register.Count; k++) + { + AccessMap->SseAccess[pOp->Info.Register.Reg + k] |= pOp->Access.Access; + } + } + break; + case ND_REG_CR: + AccessMap->CrAccess[pOp->Info.Register.Reg] |= pOp->Access.Access; + break; + case ND_REG_DR: + AccessMap->DrAccess[pOp->Info.Register.Reg] |= pOp->Access.Access; + break; + case ND_REG_TR: + AccessMap->TrAccess[pOp->Info.Register.Reg] |= pOp->Access.Access; + break; + case ND_REG_BND: + AccessMap->BndAccess[pOp->Info.Register.Reg] |= pOp->Access.Access; + break; + case ND_REG_MSK: + AccessMap->MskAccess[pOp->Info.Register.Reg] |= pOp->Access.Access; + break; + case ND_REG_SYS: + AccessMap->SysAccess[pOp->Info.Register.Reg] |= pOp->Access.Access; + break; + case ND_REG_X87: + AccessMap->X87Access[pOp->Info.Register.Reg] |= pOp->Access.Access; + break; + case ND_REG_FLG: + AccessMap->FlagsAccess |= pOp->Access.Access; + break; + case ND_REG_RIP: + AccessMap->RipAccess |= pOp->Access.Access; + break; + case ND_REG_MXCSR: + AccessMap->MxcsrAccess |= pOp->Access.Access; + break; + case ND_REG_PKRU: + AccessMap->PkruAccess |= pOp->Access.Access; + break; + case ND_REG_SSP: + AccessMap->SspAccess |= pOp->Access.Access; + break; + default: + break; + } + } + else if (ND_OP_BANK == Instrux->Operands[i].Type) + { + uint8_t j; + + // Bank registers access. This needs special handling. Note that LOADALL/LOADALLD is not supported, as + // it is too old and it's not valid since the good old 486. + if (ND_INS_FNSAVE == Instrux->Instruction) + { + for (j = 0; j < ND_MAX_FPU_REGS; j++) + { + AccessMap->FpuAccess[j] |= ND_ACCESS_READ; + } + } + else if (ND_INS_FRSTOR == Instrux->Instruction) + { + for (j = 0; j < ND_MAX_FPU_REGS; j++) + { + AccessMap->FpuAccess[j] |= ND_ACCESS_WRITE; + } + } + + if ((ND_INS_XSAVE == Instrux->Instruction) || (ND_INS_XSAVEOPT == Instrux->Instruction) || + (ND_INS_XSAVES == Instrux->Instruction) || (ND_INS_XSAVEC == Instrux->Instruction)) + { + for (j = 0; j < ND_MAX_SSE_REGS; j++) + { + AccessMap->SseAccess[j] |= ND_ACCESS_READ; + } + } + else if ((ND_INS_XRSTOR == Instrux->Instruction) || (ND_INS_XRSTORS == Instrux->Instruction)) + { + for (j = 0; j < ND_MAX_SSE_REGS; j++) + { + AccessMap->SseAccess[j] |= ND_ACCESS_WRITE; + } + } + } + } + + return ND_STATUS_SUCCESS; +} diff --git a/bddisasm/bddisasm.vcproj b/bddisasm/bddisasm.vcproj new file mode 100644 index 0000000..6902cd7 --- /dev/null +++ b/bddisasm/bddisasm.vcproj @@ -0,0 +1,474 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bddisasm/bddisasm.vcxproj b/bddisasm/bddisasm.vcxproj new file mode 100644 index 0000000..e625ea6 --- /dev/null +++ b/bddisasm/bddisasm.vcxproj @@ -0,0 +1,458 @@ + + + + + DebugKernel + Win32 + + + DebugKernel + x64 + + + Debug + Win32 + + + Debug + x64 + + + ReleaseKernel + Win32 + + + ReleaseKernel + x64 + + + Release + Win32 + + + Release + x64 + + + + {3653AA19-048B-410E-B5C4-FF78E1D84C12} + bddisasm + Win32Proj + 10.0.18362.0 + bddisasm + + + + StaticLibrary + v142 + Unicode + true + + + StaticLibrary + WindowsKernelModeDriver10.0 + Unicode + true + Windows7 + Desktop + false + 1 + + + StaticLibrary + v142 + Unicode + + + StaticLibrary + WindowsKernelModeDriver10.0 + Unicode + Windows7 + Desktop + false + 1 + + + StaticLibrary + v142 + Unicode + true + + + StaticLibrary + WindowsKernelModeDriver10.0 + Unicode + true + Windows7 + Desktop + false + 1 + + + StaticLibrary + v142 + Unicode + + + StaticLibrary + WindowsKernelModeDriver10.0 + Unicode + Windows7 + Desktop + false + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + <_ProjectFileVersion>14.0.23107.0 + + + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + + + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + + + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + + + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + + + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + + + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + + + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + + + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + + + + + + + + Disabled + Speed + include;..\inc;%(AdditionalIncludeDirectories) + WIN32;_DEBUG;_LIB;DEBUG;%(PreprocessorDefinitions) + false + true + Default + MultiThreadedDebugDLL + NotUsing + Level4 + true + ProgramDatabase + $(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb + + + false + + + + + + + + + Disabled + Speed + include;..\inc;%(AdditionalIncludeDirectories) + WIN32;_DEBUG;_LIB;DEBUG;%(PreprocessorDefinitions) + false + true + Default + MultiThreadedDebugDLL + NotUsing + Level4 + true + ProgramDatabase + $(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb + + /kernel /D %(AdditionalOptions) + + + false + + + + + + + + + X64 + + + /D "AMD64" %(AdditionalOptions) + Disabled + true + Speed + include;..\inc;%(AdditionalIncludeDirectories) + WIN32;_DEBUG;_LIB;DEBUG;%(PreprocessorDefinitions) + false + true + true + Default + MultiThreadedDebugDLL + false + NotUsing + Level4 + true + ProgramDatabase + $(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb + + + true + + + x:\Projects-devel\dacia-hg\bin\$(Platform)\$(Configuration);%(AdditionalLibraryDirectories) + false + + + + + + + + + X64 + + + /kernel /D "AMD64" %(AdditionalOptions) + Disabled + true + Speed + include;..\inc;%(AdditionalIncludeDirectories) + WIN32;_DEBUG;_LIB;DEBUG;%(PreprocessorDefinitions) + false + true + true + Default + MultiThreadedDebugDLL + false + NotUsing + Level4 + true + ProgramDatabase + $(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb + + + + true + + + x:\Projects-devel\dacia-hg\bin\$(Platform)\$(Configuration);%(AdditionalLibraryDirectories) + Native + false + + + + + + + + + MaxSpeed + true + Speed + include;..\inc;%(AdditionalIncludeDirectories) + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + false + MultiThreadedDLL + true + + Level4 + true + ProgramDatabase + $(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb + false + + + false + + + + + + + + + MaxSpeed + true + Speed + include;..\inc;%(AdditionalIncludeDirectories) + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + false + MultiThreadedDLL + true + NotUsing + Level4 + true + ProgramDatabase + $(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb + + /kernel /D %(AdditionalOptions) + false + + + false + + + + + + + + + X64 + + + /D "AMD64" %(AdditionalOptions) + MaxSpeed + AnySuitable + true + Speed + false + include;..\inc;%(AdditionalIncludeDirectories) + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + false + true + Default + MultiThreaded + false + true + + Level4 + true + ProgramDatabase + $(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb + + + false + + + true + false + + + + + + + + + + + + + X64 + + + /kernel /D "AMD64" %(AdditionalOptions) + MaxSpeed + AnySuitable + true + Speed + false + include;..\inc;%(AdditionalIncludeDirectories) + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + false + true + Default + MultiThreaded + false + true + NotUsing + Level4 + true + ProgramDatabase + $(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb + + + + false + + + true + Native + false + + + + + + NotUsing + NotUsing + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/bddisasm/bddisasm.vcxproj.filters b/bddisasm/bddisasm.vcxproj.filters new file mode 100644 index 0000000..5ddd5ae --- /dev/null +++ b/bddisasm/bddisasm.vcxproj.filters @@ -0,0 +1,81 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hpp;hxx;hm;inl;inc;xsd + + + {8f31fedd-353c-4b9c-9e2d-bdb129e1e02b} + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav + + + {5e26c505-e8f5-4e6c-9d54-f20e36b637b8} + + + + + Source Files + + + Source Files + + + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files\public + + + Header Files\public + + + Header Files\public + + + Header Files\public + + + Header Files\public + + + Header Files\public + + + Header Files\public + + + Header Files + + + \ No newline at end of file diff --git a/bddisasm/crt.c b/bddisasm/crt.c new file mode 100644 index 0000000..1aa5889 --- /dev/null +++ b/bddisasm/crt.c @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2020 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +#include "include/nd_crt.h" + + +// +// nd_strcat_s +// +char * +nd_strcat_s( + char *dst, + size_t dst_size, + const char *src + ) +{ + char *p; + size_t available; + + p = dst; + available = dst_size; + while (available > 0 && *p != 0) + { + p++; + available--; + } + + if (available == 0) + { + nd_memzero(dst, dst_size); + return NULL; + } + + while ((*p++ = *src++) != 0 && --available > 0); + + if (available == 0) + { + nd_memzero(dst, dst_size); + return NULL; + } + + return dst; +} diff --git a/bddisasm/include/instructions.h b/bddisasm/include/instructions.h new file mode 100644 index 0000000..460f5e0 --- /dev/null +++ b/bddisasm/include/instructions.h @@ -0,0 +1,35360 @@ +// +// This file was auto-generated by generate_tables.py from defs.dat. DO NOT MODIFY! +// + +#ifndef _INSTRUCTIONS_H_ +#define _INSTRUCTIONS_H_ + +const ND_INSTRUCTION gInstructions[2554] = +{ + // Pos:0 Instruction:"AAA" Encoding:"0x37"/"" + { + ND_INS_AAA, ND_CAT_DECIMAL, ND_SET_I86, 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_AF, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1 Instruction:"AAD Ib" Encoding:"0xD5 ib"/"I" + { + ND_INS_AAD, ND_CAT_DECIMAL, ND_SET_I86, 1, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2 Instruction:"AAM Ib" Encoding:"0xD4 ib"/"I" + { + ND_INS_AAM, ND_CAT_DECIMAL, ND_SET_I86, 2, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:3 Instruction:"AAS" Encoding:"0x3F"/"" + { + ND_INS_AAS, ND_CAT_DECIMAL, ND_SET_I86, 3, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_AF, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:4 Instruction:"ADC Eb,Gb" Encoding:"0x10 /r"/"MR" + { + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:5 Instruction:"ADC Ev,Gv" Encoding:"0x11 /r"/"MR" + { + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:6 Instruction:"ADC Gb,Eb" Encoding:"0x12 /r"/"RM" + { + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:7 Instruction:"ADC Gv,Ev" Encoding:"0x13 /r"/"RM" + { + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:8 Instruction:"ADC AL,Ib" Encoding:"0x14 ib"/"I" + { + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:9 Instruction:"ADC rAX,Iz" Encoding:"0x15 iz"/"I" + { + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:10 Instruction:"ADC Eb,Ib" Encoding:"0x80 /2 ib"/"MI" + { + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:11 Instruction:"ADC Ev,Iz" Encoding:"0x81 /2 iz"/"MI" + { + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:12 Instruction:"ADC Ev,Iz" Encoding:"0x82 /2 iz"/"MI" + { + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:13 Instruction:"ADC Ev,Ib" Encoding:"0x83 /2 ib"/"MI" + { + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:14 Instruction:"ADCX Gy,Ey" Encoding:"0x66 0x0F 0x38 0xF6 /r"/"RM" + { + ND_INS_ADCX, ND_CAT_ARITH, ND_SET_ADX, 5, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ADX, + 0, + 0|REG_RFLAG_CF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:15 Instruction:"ADD Eb,Gb" Encoding:"0x00 /r"/"MR" + { + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:16 Instruction:"ADD Ev,Gv" Encoding:"0x01 /r"/"MR" + { + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:17 Instruction:"ADD Gb,Eb" Encoding:"0x02 /r"/"RM" + { + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:18 Instruction:"ADD Gv,Ev" Encoding:"0x03 /r"/"RM" + { + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:19 Instruction:"ADD AL,Ib" Encoding:"0x04 ib"/"I" + { + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:20 Instruction:"ADD rAX,Iz" Encoding:"0x05 iz"/"I" + { + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:21 Instruction:"ADD Eb,Ib" Encoding:"0x80 /0 ib"/"MI" + { + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:22 Instruction:"ADD Ev,Iz" Encoding:"0x81 /0 iz"/"MI" + { + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:23 Instruction:"ADD Ev,Iz" Encoding:"0x82 /0 iz"/"MI" + { + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:24 Instruction:"ADD Ev,Ib" Encoding:"0x83 /0 ib"/"MI" + { + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:25 Instruction:"ADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x58 /r"/"RM" + { + ND_INS_ADDPD, ND_CAT_SSE, ND_SET_SSE2, 7, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:26 Instruction:"ADDPS Vps,Wps" Encoding:"NP 0x0F 0x58 /r"/"RM" + { + ND_INS_ADDPS, ND_CAT_SSE, ND_SET_SSE, 8, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:27 Instruction:"ADDSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x58 /r"/"RM" + { + ND_INS_ADDSD, ND_CAT_SSE, ND_SET_SSE2, 9, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:28 Instruction:"ADDSS Vss,Wss" Encoding:"0xF3 0x0F 0x58 /r"/"RM" + { + ND_INS_ADDSS, ND_CAT_SSE, ND_SET_SSE, 10, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:29 Instruction:"ADDSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0xD0 /r"/"RM" + { + ND_INS_ADDSUBPD, ND_CAT_SSE, ND_SET_SSE3, 11, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:30 Instruction:"ADDSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0xD0 /r"/"RM" + { + ND_INS_ADDSUBPS, ND_CAT_SSE, ND_SET_SSE3, 12, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:31 Instruction:"ADOX Gy,Ey" Encoding:"0xF3 0x0F 0x38 0xF6 /r"/"RM" + { + ND_INS_ADOX, ND_CAT_ARITH, ND_SET_ADX, 13, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ADX, + 0, + 0|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:32 Instruction:"AESDEC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDE /r"/"RM" + { + ND_INS_AESDEC, ND_CAT_AES, ND_SET_AES, 14, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:33 Instruction:"AESDECLAST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDF /r"/"RM" + { + ND_INS_AESDECLAST, ND_CAT_AES, ND_SET_AES, 15, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:34 Instruction:"AESENC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDC /r"/"RM" + { + ND_INS_AESENC, ND_CAT_AES, ND_SET_AES, 16, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:35 Instruction:"AESENCLAST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDD /r"/"RM" + { + ND_INS_AESENCLAST, ND_CAT_AES, ND_SET_AES, 17, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:36 Instruction:"AESIMC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDB /r"/"RM" + { + ND_INS_AESIMC, ND_CAT_AES, ND_SET_AES, 18, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:37 Instruction:"AESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xDF /r ib"/"RMI" + { + ND_INS_AESKEYGENASSIST, ND_CAT_AES, ND_SET_AES, 19, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:38 Instruction:"ALTINST" Encoding:"0x0F 0x3F"/"" + { + ND_INS_ALTINST, ND_CAT_SYSTEM, ND_SET_CYRIX, 20, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:39 Instruction:"AND Eb,Gb" Encoding:"0x20 /r"/"MR" + { + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:40 Instruction:"AND Ev,Gv" Encoding:"0x21 /r"/"MR" + { + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:41 Instruction:"AND Gb,Eb" Encoding:"0x22 /r"/"RM" + { + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_G, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:42 Instruction:"AND Gv,Ev" Encoding:"0x23 /r"/"RM" + { + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:43 Instruction:"AND AL,Ib" Encoding:"0x24 ib"/"I" + { + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:44 Instruction:"AND rAX,Iz" Encoding:"0x25 iz"/"I" + { + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:45 Instruction:"AND Eb,Ib" Encoding:"0x80 /4 ib"/"MI" + { + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:46 Instruction:"AND Ev,Iz" Encoding:"0x81 /4 iz"/"MI" + { + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:47 Instruction:"AND Ev,Iz" Encoding:"0x82 /4 iz"/"MI" + { + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:48 Instruction:"AND Ev,Ib" Encoding:"0x83 /4 ib"/"MI" + { + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:49 Instruction:"ANDN Gy,By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF2 /r"/"RVM" + { + ND_INS_ANDN, ND_CAT_BMI1, ND_SET_BMI1, 22, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, + 0, + 0|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_PF|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_PF|REG_RFLAG_AF, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_B, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:50 Instruction:"ANDNPD Vpd,Wpd" Encoding:"0x66 0x0F 0x55 /r"/"RM" + { + ND_INS_ANDNPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 23, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:51 Instruction:"ANDNPS Vps,Wps" Encoding:"NP 0x0F 0x55 /r"/"RM" + { + ND_INS_ANDNPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 24, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:52 Instruction:"ANDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x54 /r"/"RM" + { + ND_INS_ANDPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 25, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:53 Instruction:"ANDPS Vps,Wps" Encoding:"NP 0x0F 0x54 /r"/"RM" + { + ND_INS_ANDPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 26, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:54 Instruction:"ARPL Ew,Gw" Encoding:"0x63 /r"/"MR" + { + ND_INS_ARPL, ND_CAT_SYSTEM, ND_SET_I286PROT, 27, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_w, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:55 Instruction:"BEXTR Gy,Ey,By" Encoding:"vex m:2 p:0 l:0 w:x 0xF7 /r"/"RMV" + { + ND_INS_BEXTR, ND_CAT_BMI1, ND_SET_BMI1, 28, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, + 0, + 0|REG_RFLAG_ZF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_B, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:56 Instruction:"BEXTR Gy,Ey,Id" Encoding:"xop m:A 0x10 /r id"/"RMI" + { + ND_INS_BEXTR, ND_CAT_BITBYTE, ND_SET_TBM, 28, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:57 Instruction:"BLCFILL By,Ey" Encoding:"xop m:9 0x01 /1"/"VM" + { + ND_INS_BLCFILL, ND_CAT_BITBYTE, ND_SET_TBM, 29, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + 0, + 0, + 0, + 0, + OP(ND_OPT_B, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:58 Instruction:"BLCI By,Ey" Encoding:"xop m:9 0x02 /6"/"VM" + { + ND_INS_BLCI, ND_CAT_BITBYTE, ND_SET_TBM, 30, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + 0, + 0, + 0, + 0, + OP(ND_OPT_B, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:59 Instruction:"BLCIC By,Ey" Encoding:"xop m:9 0x01 /5"/"VM" + { + ND_INS_BLCIC, ND_CAT_BITBYTE, ND_SET_TBM, 31, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + 0, + 0, + 0, + 0, + OP(ND_OPT_B, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:60 Instruction:"BLCMSK By,Ey" Encoding:"xop m:9 0x02 /1"/"VM" + { + ND_INS_BLCMSK, ND_CAT_BITBYTE, ND_SET_TBM, 32, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + 0, + 0, + 0, + 0, + OP(ND_OPT_B, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:61 Instruction:"BLCS By,Ey" Encoding:"xop m:9 0x01 /3"/"VM" + { + ND_INS_BLCS, ND_CAT_BITBYTE, ND_SET_TBM, 33, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + 0, + 0, + 0, + 0, + OP(ND_OPT_B, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:62 Instruction:"BLENDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0D /r ib"/"RMI" + { + ND_INS_BLENDPD, ND_CAT_SSE, ND_SET_SSE4, 34, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:63 Instruction:"BLENDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0C /r ib"/"RMI" + { + ND_INS_BLENDPS, ND_CAT_SSE, ND_SET_SSE4, 35, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:64 Instruction:"BLENDVPD Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x15 /r"/"RM" + { + ND_INS_BLENDVPD, ND_CAT_SSE, ND_SET_SSE4, 36, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:65 Instruction:"BLENDVPS Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x14 /r"/"RM" + { + ND_INS_BLENDVPS, ND_CAT_SSE, ND_SET_SSE4, 37, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:66 Instruction:"BLSFILL By,Ey" Encoding:"xop m:9 0x01 /2"/"VM" + { + ND_INS_BLSFILL, ND_CAT_BITBYTE, ND_SET_TBM, 38, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + 0, + 0, + 0, + 0, + OP(ND_OPT_B, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:67 Instruction:"BLSI By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /3"/"VM" + { + ND_INS_BLSI, ND_CAT_BMI1, ND_SET_BMI1, 39, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_PF|REG_RFLAG_AF, + 0|REG_RFLAG_OF|REG_RFLAG_PF|REG_RFLAG_AF, + OP(ND_OPT_B, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:68 Instruction:"BLSIC By,Ey" Encoding:"xop m:9 0x01 /6"/"VM" + { + ND_INS_BLSIC, ND_CAT_BITBYTE, ND_SET_TBM, 40, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + 0, + 0, + 0, + 0, + OP(ND_OPT_B, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:69 Instruction:"BLSMSK By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /2"/"VM" + { + ND_INS_BLSMSK, ND_CAT_BMI1, ND_SET_BMI1, 41, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_SF, + 0|REG_RFLAG_PF|REG_RFLAG_AF, + 0|REG_RFLAG_ZF|REG_RFLAG_OF|REG_RFLAG_PF|REG_RFLAG_AF, + OP(ND_OPT_B, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:70 Instruction:"BLSR By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /1"/"VM" + { + ND_INS_BLSR, ND_CAT_BMI1, ND_SET_BMI1, 42, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_PF|REG_RFLAG_AF, + 0|REG_RFLAG_OF|REG_RFLAG_PF|REG_RFLAG_AF, + OP(ND_OPT_B, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:71 Instruction:"BNDCL rBl,Ey" Encoding:"0xF3 0x0F 0x1A /r"/"RM" + { + ND_INS_BNDCL, ND_CAT_MPX, ND_SET_MPX, 43, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_MPX, + 0, + 0, + 0, + 0, + OP(ND_OPT_rB, ND_OPS_l, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:72 Instruction:"BNDCN rBl,Ey" Encoding:"0xF2 0x0F 0x1B /r"/"RM" + { + ND_INS_BNDCN, ND_CAT_MPX, ND_SET_MPX, 44, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_MPX, + 0, + 0, + 0, + 0, + OP(ND_OPT_rB, ND_OPS_l, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:73 Instruction:"BNDCU rBl,Ey" Encoding:"0xF2 0x0F 0x1A /r"/"RM" + { + ND_INS_BNDCU, ND_CAT_MPX, ND_SET_MPX, 45, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_MPX, + 0, + 0, + 0, + 0, + OP(ND_OPT_rB, ND_OPS_l, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:74 Instruction:"BNDLDX rBl,Mmib" Encoding:"0x0F 0x1A /r:mem mib"/"RM" + { + ND_INS_BNDLDX, ND_CAT_MPX, ND_SET_MPX, 46, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_MODRM|ND_FLAG_MIB, ND_CFF_MPX, + 0, + 0, + 0, + 0, + OP(ND_OPT_rB, ND_OPS_l, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_mib, ND_OPF_R, 0, 0), + }, + + // Pos:75 Instruction:"BNDMK rBl,My" Encoding:"0xF3 0x0F 0x1B /r:mem"/"RM" + { + ND_INS_BNDMK, ND_CAT_MPX, ND_SET_MPX, 47, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_MODRM, ND_CFF_MPX, + 0, + 0, + 0, + 0, + OP(ND_OPT_rB, ND_OPS_l, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:76 Instruction:"BNDMOV rBl,mBl" Encoding:"0x66 0x0F 0x1A /r"/"RM" + { + ND_INS_BNDMOV, ND_CAT_MPX, ND_SET_MPX, 48, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NOA16|ND_FLAG_MODRM, ND_CFF_MPX, + 0, + 0, + 0, + 0, + OP(ND_OPT_rB, ND_OPS_l, ND_OPF_W, 0, 0), + OP(ND_OPT_mB, ND_OPS_l, ND_OPF_R, 0, 0), + }, + + // Pos:77 Instruction:"BNDMOV mBl,rBl" Encoding:"0x66 0x0F 0x1B /r"/"MR" + { + ND_INS_BNDMOV, ND_CAT_MPX, ND_SET_MPX, 48, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NOA16|ND_FLAG_MODRM, ND_CFF_MPX, + 0, + 0, + 0, + 0, + OP(ND_OPT_mB, ND_OPS_l, ND_OPF_W, 0, 0), + OP(ND_OPT_rB, ND_OPS_l, ND_OPF_R, 0, 0), + }, + + // Pos:78 Instruction:"BNDSTX Mmib,rBl" Encoding:"0x0F 0x1B /r:mem mib"/"MR" + { + ND_INS_BNDSTX, ND_CAT_MPX, ND_SET_MPX, 49, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_MODRM|ND_FLAG_MIB, ND_CFF_MPX, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_mib, ND_OPF_W, 0, 0), + OP(ND_OPT_rB, ND_OPS_l, ND_OPF_R, 0, 0), + }, + + // Pos:79 Instruction:"BOUND Gv,Ma" Encoding:"0x62 /r:mem"/"RM" + { + ND_INS_BOUND, ND_CAT_INTERRUPT, ND_SET_I186, 50, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_a, ND_OPF_R, 0, 0), + }, + + // Pos:80 Instruction:"BSF Gv,Ev" Encoding:"0x0F 0xBC /r"/"RM" + { + ND_INS_BSF, ND_CAT_I386, ND_SET_I386, 51, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_ZF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:81 Instruction:"BSR Gv,Ev" Encoding:"0x0F 0xBD /r"/"RM" + { + ND_INS_BSR, ND_CAT_BITBYTE, ND_SET_I386, 52, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_ZF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:82 Instruction:"BSWAP Zv" Encoding:"0x0F 0xC8"/"O" + { + ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + }, + + // Pos:83 Instruction:"BSWAP Zv" Encoding:"0x0F 0xC9"/"O" + { + ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + }, + + // Pos:84 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCA"/"O" + { + ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + }, + + // Pos:85 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCB"/"O" + { + ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + }, + + // Pos:86 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCC"/"O" + { + ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + }, + + // Pos:87 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCD"/"O" + { + ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + }, + + // Pos:88 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCE"/"O" + { + ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + }, + + // Pos:89 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCF"/"O" + { + ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + }, + + // Pos:90 Instruction:"BT Ev,Gv" Encoding:"0x0F 0xA3 /r bitbase"/"MR" + { + ND_INS_BT, ND_CAT_BITBYTE, ND_SET_I386, 54, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, + 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:91 Instruction:"BT Ev,Ib" Encoding:"0x0F 0xBA /4 ib"/"MI" + { + ND_INS_BT, ND_CAT_BITBYTE, ND_SET_I386, 54, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:92 Instruction:"BTC Ev,Ib" Encoding:"0x0F 0xBA /7 ib"/"MI" + { + ND_INS_BTC, ND_CAT_BITBYTE, ND_SET_I386, 55, + ND_MOD_ANY, + ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:93 Instruction:"BTC Ev,Gv" Encoding:"0x0F 0xBB /r bitbase"/"MR" + { + ND_INS_BTC, ND_CAT_I386, ND_SET_I386, 55, + ND_MOD_ANY, + ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, + 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:94 Instruction:"BTR Ev,Gv" Encoding:"0x0F 0xB3 /r bitbase"/"MR" + { + ND_INS_BTR, ND_CAT_BITBYTE, ND_SET_I386, 56, + ND_MOD_ANY, + ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, + 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:95 Instruction:"BTR Ev,Ib" Encoding:"0x0F 0xBA /6 ib"/"MI" + { + ND_INS_BTR, ND_CAT_BITBYTE, ND_SET_I386, 56, + ND_MOD_ANY, + ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:96 Instruction:"BTS Ev,Gv" Encoding:"0x0F 0xAB /r bitbase"/"MR" + { + ND_INS_BTS, ND_CAT_BITBYTE, ND_SET_I386, 57, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, + 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:97 Instruction:"BTS Ev,Ib" Encoding:"0x0F 0xBA /5 ib"/"MI" + { + ND_INS_BTS, ND_CAT_BITBYTE, ND_SET_I386, 57, + ND_MOD_ANY, + ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:98 Instruction:"BZHI Gy,Ey,By" Encoding:"vex m:2 p:0 l:0 w:x 0xF5 /r"/"RMV" + { + ND_INS_BZHI, ND_CAT_BMI2, ND_SET_BMI2, 58, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_PF|REG_RFLAG_AF, + 0|REG_RFLAG_OF|REG_RFLAG_PF|REG_RFLAG_AF, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_B, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:99 Instruction:"CALL Jz" Encoding:"0xE8 cz"/"D" + { + ND_INS_CALLNR, ND_CAT_CALL, ND_SET_I86, 59, + ND_MOD_ANY, + ND_PREF_BND, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:100 Instruction:"CALL Ev" Encoding:"0xFF /2"/"M" + { + ND_INS_CALLNI, ND_CAT_CALL, ND_SET_I86, 59, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_DNT, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_CETT|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:101 Instruction:"CALLF Ap" Encoding:"0x9A cp"/"D" + { + ND_INS_CALLFD, ND_CAT_CALL, ND_SET_I86, 60, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_A, ND_OPS_p, ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v2, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v2, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:102 Instruction:"CALLF Mp" Encoding:"0xFF /3:mem"/"M" + { + ND_INS_CALLFI, ND_CAT_CALL, ND_SET_I86, 60, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_p, ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v2, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v2, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:103 Instruction:"CBW" Encoding:"ds16 0x98"/"" + { + ND_INS_CBW, ND_CAT_CONVERT, ND_SET_I386, 61, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:104 Instruction:"CDQ" Encoding:"ds32 0x99"/"" + { + ND_INS_CDQ, ND_CAT_CONVERT, ND_SET_I386, 62, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:105 Instruction:"CDQE" Encoding:"ds64 0x98"/"" + { + ND_INS_CDQE, ND_CAT_CONVERT, ND_SET_I386, 63, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:106 Instruction:"CL1INVMB" Encoding:"0x0F 0x0A"/"" + { + ND_INS_CL1INVMB, ND_CAT_SYSTEM, ND_SET_SCC, 64, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:107 Instruction:"CLAC" Encoding:"NP 0x0F 0x01 /0xCA"/"" + { + ND_INS_CLAC, ND_CAT_SMAP, ND_SET_SMAP, 65, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SMAP, + 0, + 0, + 0, + 0|REG_RFLAG_AC, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:108 Instruction:"CLC" Encoding:"0xF8"/"" + { + ND_INS_CLC, ND_CAT_FLAGOP, ND_SET_I86, 66, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0|REG_RFLAG_CF, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:109 Instruction:"CLD" Encoding:"0xFC"/"" + { + ND_INS_CLD, ND_CAT_FLAGOP, ND_SET_I86, 67, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0|REG_RFLAG_DF, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:110 Instruction:"CLDEMOTE Mcl" Encoding:"NP 0x0F 0x1C /0:mem"/"M" + { + ND_INS_CLDEMOTE, ND_CAT_CLDEMOTE, ND_SET_CLDEMOTE, 68, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLDEMOTE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_W, 0, 0), + }, + + // Pos:111 Instruction:"CLEVICT0 M?" Encoding:"vex m:1 p:3 0xAE /7:mem"/"M" + { + ND_INS_CLEVICT0, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 69, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_unknown, ND_OPF_N, 0, 0), + }, + + // Pos:112 Instruction:"CLEVICT1 M?" Encoding:"vex m:1 p:2 0xAE /7:mem"/"M" + { + ND_INS_CLEVICT1, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 70, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_unknown, ND_OPF_N, 0, 0), + }, + + // Pos:113 Instruction:"CLFLUSH Mcl" Encoding:"NP 0x0F 0xAE /7:mem"/"M" + { + ND_INS_CLFLUSH, ND_CAT_MISC, ND_SET_CLFSH, 71, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLFSH, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0), + }, + + // Pos:114 Instruction:"CLFLUSHOPT Mcl" Encoding:"0x66 0x0F 0xAE /7:mem"/"M" + { + ND_INS_CLFLUSHOPT, ND_CAT_MISC, ND_SET_CLFSHOPT, 72, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLFSHOPT, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0), + }, + + // Pos:115 Instruction:"CLGI" Encoding:"0x0F 0x01 /0xDD"/"" + { + ND_INS_CLGI, ND_CAT_SYSTEM, ND_SET_SVM, 73, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, + 0, + 0, + 0, + 0, + }, + + // Pos:116 Instruction:"CLI" Encoding:"0xFA"/"" + { + ND_INS_CLI, ND_CAT_FLAGOP, ND_SET_I86, 74, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0|REG_RFLAG_IF, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:117 Instruction:"CLRSSBSY Mq" Encoding:"0xF3 0x0F 0xAE /6:mem"/"M" + { + ND_INS_CLRSSBSY, ND_CAT_CET, ND_SET_CET, 75, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_RW, 0, 0), + }, + + // Pos:118 Instruction:"CLTS" Encoding:"0x0F 0x06"/"" + { + ND_INS_CLTS, ND_CAT_SYSTEM, ND_SET_I286REAL, 76, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_CR_0, ND_OPS_yf, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:119 Instruction:"CLWB Mcl" Encoding:"0x66 0x0F 0xAE /6:mem"/"M" + { + ND_INS_CLWB, ND_CAT_MISC, ND_SET_CLWB, 77, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLWB, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_W, 0, 0), + }, + + // Pos:120 Instruction:"CLZERO" Encoding:"0x0F 0x01 /0xFC"/"" + { + ND_INS_CLZERO, ND_CAT_MISC, ND_SET_CLZERO, 78, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:121 Instruction:"CMC" Encoding:"0xF5"/"" + { + ND_INS_CMC, ND_CAT_FLAGOP, ND_SET_I86, 79, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_CF, + 0, + 0, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:122 Instruction:"CMOVBE Gv,Ev" Encoding:"0x0F 0x46 /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 80, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:123 Instruction:"CMOVC Gv,Ev" Encoding:"0x0F 0x42 /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 81, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_CF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:124 Instruction:"CMOVL Gv,Ev" Encoding:"0x0F 0x4C /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 82, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:125 Instruction:"CMOVLE Gv,Ev" Encoding:"0x0F 0x4E /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 83, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:126 Instruction:"CMOVNBE Gv,Ev" Encoding:"0x0F 0x47 /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 84, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:127 Instruction:"CMOVNC Gv,Ev" Encoding:"0x0F 0x43 /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 85, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_CF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:128 Instruction:"CMOVNL Gv,Ev" Encoding:"0x0F 0x4D /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 86, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:129 Instruction:"CMOVNLE Gv,Ev" Encoding:"0x0F 0x4F /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 87, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:130 Instruction:"CMOVNO Gv,Ev" Encoding:"0x0F 0x41 /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 88, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:131 Instruction:"CMOVNP Gv,Ev" Encoding:"0x0F 0x4B /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 89, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_PF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:132 Instruction:"CMOVNS Gv,Ev" Encoding:"0x0F 0x49 /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 90, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_SF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:133 Instruction:"CMOVNZ Gv,Ev" Encoding:"0x0F 0x45 /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 91, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:134 Instruction:"CMOVO Gv,Ev" Encoding:"0x0F 0x40 /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 92, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:135 Instruction:"CMOVP Gv,Ev" Encoding:"0x0F 0x4A /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 93, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_PF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:136 Instruction:"CMOVS Gv,Ev" Encoding:"0x0F 0x48 /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 94, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_SF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:137 Instruction:"CMOVZ Gv,Ev" Encoding:"0x0F 0x44 /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 95, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:138 Instruction:"CMP Eb,Gb" Encoding:"0x38 /r"/"MR" + { + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:139 Instruction:"CMP Ev,Gv" Encoding:"0x39 /r"/"MR" + { + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:140 Instruction:"CMP Gb,Eb" Encoding:"0x3A /r"/"RM" + { + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:141 Instruction:"CMP Gv,Ev" Encoding:"0x3B /r"/"RM" + { + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:142 Instruction:"CMP AL,Ib" Encoding:"0x3C ib"/"I" + { + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:143 Instruction:"CMP rAX,Iz" Encoding:"0x3D iz"/"I" + { + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:144 Instruction:"CMP Eb,Ib" Encoding:"0x80 /7 ib"/"MI" + { + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:145 Instruction:"CMP Ev,Iz" Encoding:"0x81 /7 iz"/"MI" + { + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:146 Instruction:"CMP Ev,Iz" Encoding:"0x82 /7 iz"/"MI" + { + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:147 Instruction:"CMP Ev,Ib" Encoding:"0x83 /7 ib"/"MI" + { + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:148 Instruction:"CMPPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC2 /r ib"/"RMI" + { + ND_INS_CMPPD, ND_CAT_SSE, ND_SET_SSE2, 97, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:149 Instruction:"CMPPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC2 /r ib"/"RMI" + { + ND_INS_CMPPS, ND_CAT_SSE, ND_SET_SSE, 98, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:150 Instruction:"CMPSB Xb,Yb" Encoding:"0xA6"/"" + { + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 99, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:151 Instruction:"CMPSB Xb,Yb" Encoding:"rep 0xA6"/"" + { + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 99, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_ZF|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:152 Instruction:"CMPSD Vsd,Wsd,Ib" Encoding:"0xF2 0x0F 0xC2 /r ib"/"RMI" + { + ND_INS_CMPSD, ND_CAT_SSE, ND_SET_SSE2, 100, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:153 Instruction:"CMPSD Xv,Yv" Encoding:"ds32 0xA7"/"" + { + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 100, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:154 Instruction:"CMPSD Xv,Yv" Encoding:"rep ds32 0xA7"/"" + { + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 100, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_ZF|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:155 Instruction:"CMPSQ Xv,Yv" Encoding:"ds64 0xA7"/"" + { + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 101, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:156 Instruction:"CMPSQ Xv,Yv" Encoding:"rep ds64 0xA7"/"" + { + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 101, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_ZF|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:157 Instruction:"CMPSS Vss,Wss,Ib" Encoding:"0xF3 0x0F 0xC2 /r ib"/"RMI" + { + ND_INS_CMPSS, ND_CAT_SSE, ND_SET_SSE, 102, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:158 Instruction:"CMPSW Xv,Yv" Encoding:"ds16 0xA7"/"" + { + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 103, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:159 Instruction:"CMPSW Xv,Yv" Encoding:"rep ds16 0xA7"/"" + { + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 103, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_ZF|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:160 Instruction:"CMPXCHG Eb,Gb" Encoding:"0x0F 0xB0 /r"/"MR" + { + ND_INS_CMPXCHG, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 104, + ND_MOD_ANY, + ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:161 Instruction:"CMPXCHG Ev,Gv" Encoding:"0x0F 0xB1 /r"/"MR" + { + ND_INS_CMPXCHG, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 104, + ND_MOD_ANY, + ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:162 Instruction:"CMPXCHG16B Mdq" Encoding:"rexw 0x0F 0xC7 /1:mem"/"M" + { + ND_INS_CMPXCHG16B, ND_CAT_SEMAPHORE, ND_SET_CMPXCHG16B, 105, + ND_MOD_ANY, + ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CX8, + 0, + 0|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rBX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:163 Instruction:"CMPXCHG8B Mq" Encoding:"0x0F 0xC7 /1:mem"/"M" + { + ND_INS_CMPXCHG8B, ND_CAT_SEMAPHORE, ND_SET_PENTIUMREAL, 106, + ND_MOD_ANY, + ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CX8, + 0, + 0|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rBX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:164 Instruction:"COMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2F /r"/"RM" + { + ND_INS_COMISD, ND_CAT_SSE2, ND_SET_SSE2, 107, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:165 Instruction:"COMISS Vss,Wss" Encoding:"NP 0x0F 0x2F /r"/"RM" + { + ND_INS_COMISS, ND_CAT_SSE, ND_SET_SSE, 108, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:166 Instruction:"CPUID" Encoding:"0x0F 0xA2"/"" + { + ND_INS_CPUID, ND_CAT_MISC, ND_SET_I486REAL, 109, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rBX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_CRW, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:167 Instruction:"CPU_READ" Encoding:"0x0F 0x3D"/"" + { + ND_INS_CPU_READ, ND_CAT_SYSTEM, ND_SET_CYRIX, 110, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:168 Instruction:"CPU_WRITE" Encoding:"0x0F 0x3C"/"" + { + ND_INS_CPU_WRITE, ND_CAT_SYSTEM, ND_SET_CYRIX, 111, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:169 Instruction:"CQO" Encoding:"ds64 0x99"/"" + { + ND_INS_CQO, ND_CAT_CONVERT, ND_SET_I386, 112, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:170 Instruction:"CRC32 Gy,Eb" Encoding:"0xF2 0x0F 0x38 0xF0 /r"/"RM" + { + ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 113, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE42, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:171 Instruction:"CRC32 Gy,Eb" Encoding:"0x66 0xF2 0x0F 0x38 0xF0 /r"/"RM" + { + ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 113, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_SSE42, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:172 Instruction:"CRC32 Gy,Ev" Encoding:"0xF2 0x0F 0x38 0xF1 /r"/"RM" + { + ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 113, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE42, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:173 Instruction:"CRC32 Gy,Ev" Encoding:"0x66 0xF2 0x0F 0x38 0xF1 /r"/"RM" + { + ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 113, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_SSE42, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:174 Instruction:"CVTDQ2PD Vx,Wpd" Encoding:"0xF3 0x0F 0xE6 /r"/"RM" + { + ND_INS_CVTDQ2PD, ND_CAT_CONVERT, ND_SET_SSE2, 114, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:175 Instruction:"CVTDQ2PS Vps,Wdq" Encoding:"NP 0x0F 0x5B /r"/"RM" + { + ND_INS_CVTDQ2PS, ND_CAT_CONVERT, ND_SET_SSE2, 115, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:176 Instruction:"CVTPD2DQ Vx,Wpd" Encoding:"0xF2 0x0F 0xE6 /r"/"RM" + { + ND_INS_CVTPD2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 116, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:177 Instruction:"CVTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2D /r"/"RM" + { + ND_INS_CVTPD2PI, ND_CAT_CONVERT, ND_SET_SSE2, 117, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:178 Instruction:"CVTPD2PS Vps,Wpd" Encoding:"0x66 0x0F 0x5A /r"/"RM" + { + ND_INS_CVTPD2PS, ND_CAT_CONVERT, ND_SET_SSE2, 118, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:179 Instruction:"CVTPI2PD Vpd,Qq" Encoding:"0x66 0x0F 0x2A /r"/"RM" + { + ND_INS_CVTPI2PD, ND_CAT_CONVERT, ND_SET_SSE2, 119, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:180 Instruction:"CVTPI2PS Vq,Qq" Encoding:"NP 0x0F 0x2A /r"/"RM" + { + ND_INS_CVTPI2PS, ND_CAT_CONVERT, ND_SET_SSE, 120, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:181 Instruction:"CVTPS2DQ Vdq,Wps" Encoding:"0x66 0x0F 0x5B /r"/"RM" + { + ND_INS_CVTPS2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 121, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:182 Instruction:"CVTPS2PD Vpd,Wq" Encoding:"NP 0x0F 0x5A /r"/"RM" + { + ND_INS_CVTPS2PD, ND_CAT_CONVERT, ND_SET_SSE2, 122, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:183 Instruction:"CVTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2D /r"/"RM" + { + ND_INS_CVTPS2PI, ND_CAT_CONVERT, ND_SET_SSE, 123, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:184 Instruction:"CVTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2D /r"/"RM" + { + ND_INS_CVTSD2SI, ND_CAT_CONVERT, ND_SET_SSE2, 124, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:185 Instruction:"CVTSD2SS Vss,Wsd" Encoding:"0xF2 0x0F 0x5A /r"/"RM" + { + ND_INS_CVTSD2SS, ND_CAT_CONVERT, ND_SET_SSE2, 125, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:186 Instruction:"CVTSI2SD Vsd,Ey" Encoding:"0xF2 0x0F 0x2A /r"/"RM" + { + ND_INS_CVTSI2SD, ND_CAT_CONVERT, ND_SET_SSE2, 126, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:187 Instruction:"CVTSI2SS Vss,Ey" Encoding:"0xF3 0x0F 0x2A /r"/"RM" + { + ND_INS_CVTSI2SS, ND_CAT_CONVERT, ND_SET_SSE, 127, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:188 Instruction:"CVTSS2SD Vsd,Wss" Encoding:"0xF3 0x0F 0x5A /r"/"RM" + { + ND_INS_CVTSS2SD, ND_CAT_CONVERT, ND_SET_SSE2, 128, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:189 Instruction:"CVTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2D /r"/"RM" + { + ND_INS_CVTSS2SI, ND_CAT_CONVERT, ND_SET_SSE, 129, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:190 Instruction:"CVTTPD2DQ Vx,Wpd" Encoding:"0x66 0x0F 0xE6 /r"/"RM" + { + ND_INS_CVTTPD2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 130, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:191 Instruction:"CVTTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2C /r"/"RM" + { + ND_INS_CVTTPD2PI, ND_CAT_CONVERT, ND_SET_SSE2, 131, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:192 Instruction:"CVTTPS2DQ Vdq,Wps" Encoding:"0xF3 0x0F 0x5B /r"/"RM" + { + ND_INS_CVTTPS2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 132, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:193 Instruction:"CVTTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2C /r"/"RM" + { + ND_INS_CVTTPS2PI, ND_CAT_CONVERT, ND_SET_SSE, 133, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:194 Instruction:"CVTTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2C /r"/"RM" + { + ND_INS_CVTTSD2SI, ND_CAT_CONVERT, ND_SET_SSE2, 134, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:195 Instruction:"CVTTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2C /r"/"RM" + { + ND_INS_CVTTSS2SI, ND_CAT_CONVERT, ND_SET_SSE, 135, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:196 Instruction:"CWD" Encoding:"ds16 0x99"/"" + { + ND_INS_CWD, ND_CAT_CONVERT, ND_SET_I386, 136, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:197 Instruction:"CWDE" Encoding:"ds32 0x98"/"" + { + ND_INS_CWDE, ND_CAT_CONVERT, ND_SET_I386, 137, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:198 Instruction:"DAA" Encoding:"0x27"/"" + { + ND_INS_DAA, ND_CAT_DECIMAL, ND_SET_I86, 138, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0|REG_RFLAG_CF|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF, + 0|REG_RFLAG_OF, + 0|REG_RFLAG_OF, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:199 Instruction:"DAS" Encoding:"0x2F"/"" + { + ND_INS_DAS, ND_CAT_DECIMAL, ND_SET_I86, 139, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0|REG_RFLAG_CF|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_OF, + 0|REG_RFLAG_OF, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:200 Instruction:"DEC Zv" Encoding:"0x48"/"O" + { + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:201 Instruction:"DEC Zv" Encoding:"0x49"/"O" + { + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:202 Instruction:"DEC Zv" Encoding:"0x4A"/"O" + { + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:203 Instruction:"DEC Zv" Encoding:"0x4B"/"O" + { + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:204 Instruction:"DEC Zv" Encoding:"0x4C"/"O" + { + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:205 Instruction:"DEC Zv" Encoding:"0x4D"/"O" + { + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:206 Instruction:"DEC Zv" Encoding:"0x4E"/"O" + { + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:207 Instruction:"DEC Zv" Encoding:"0x4F"/"O" + { + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:208 Instruction:"DEC Eb" Encoding:"0xFE /1"/"M" + { + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:209 Instruction:"DEC Ev" Encoding:"0xFF /1"/"M" + { + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:210 Instruction:"DELAY Ry" Encoding:"vex m:1 p:2 0xAE /6:reg"/"M" + { + ND_INS_DELAY, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 141, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:211 Instruction:"DIV Eb" Encoding:"0xF6 /6"/"M" + { + ND_INS_DIV, ND_CAT_ARITH, ND_SET_I86, 142, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:212 Instruction:"DIV Ev" Encoding:"0xF7 /6"/"M" + { + ND_INS_DIV, ND_CAT_ARITH, ND_SET_I86, 142, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:213 Instruction:"DIVPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5E /r"/"RM" + { + ND_INS_DIVPD, ND_CAT_SSE, ND_SET_SSE2, 143, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:214 Instruction:"DIVPS Vps,Wps" Encoding:"NP 0x0F 0x5E /r"/"RM" + { + ND_INS_DIVPS, ND_CAT_SSE, ND_SET_SSE, 144, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:215 Instruction:"DIVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5E /r"/"RM" + { + ND_INS_DIVSD, ND_CAT_SSE, ND_SET_SSE2, 145, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:216 Instruction:"DIVSS Vss,Wss" Encoding:"0xF3 0x0F 0x5E /r"/"RM" + { + ND_INS_DIVSS, ND_CAT_SSE, ND_SET_SSE, 146, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:217 Instruction:"DMINT" Encoding:"0x0F 0x39"/"" + { + ND_INS_DMINT, ND_CAT_SYSTEM, ND_SET_CYRIX, 147, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:218 Instruction:"DPPD Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x41 /r ib"/"RMI" + { + ND_INS_DPPD, ND_CAT_SSE, ND_SET_SSE4, 148, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:219 Instruction:"DPPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x40 /r ib"/"RMI" + { + ND_INS_DPPS, ND_CAT_SSE, ND_SET_SSE4, 149, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:220 Instruction:"EMMS" Encoding:"NP 0x0F 0x77"/"" + { + ND_INS_EMMS, ND_CAT_MMX, ND_SET_MMX, 150, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, ND_CFF_MMX, + 0, + 0, + 0, + 0, + }, + + // Pos:221 Instruction:"ENCLS" Encoding:"NP 0x0F 0x01 /0xCF"/"" + { + ND_INS_ENCLS, ND_CAT_SGX, ND_SET_SGX, 151, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SGX, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rBX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_CRW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_CRW, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_CRW, 0, 0), + }, + + // Pos:222 Instruction:"ENCLU" Encoding:"NP 0x0F 0x01 /0xD7"/"" + { + ND_INS_ENCLU, ND_CAT_SGX, ND_SET_SGX, 152, + ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SGX, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rBX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_CRW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_CRW, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_CRW, 0, 0), + }, + + // Pos:223 Instruction:"ENCLV" Encoding:"NP 0x0F 0x01 /0xC0"/"" + { + ND_INS_ENCLV, ND_CAT_SGX, ND_SET_SGX, 153, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SGX, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rBX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_CRW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_CRW, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_CRW, 0, 0), + }, + + // Pos:224 Instruction:"ENDBR32" Encoding:"a0xF3 0x0F 0x1E /0xFB"/"" + { + ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET, 154, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET, + 0, + 0, + 0, + 0, + }, + + // Pos:225 Instruction:"ENDBR64" Encoding:"a0xF3 0x0F 0x1E /0xFA"/"" + { + ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET, 155, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET, + 0, + 0, + 0, + 0, + }, + + // Pos:226 Instruction:"ENQCMD rM?,Moq" Encoding:"0xF2 0x0F 0x38 0xF8 /r:mem"/"M" + { + ND_INS_ENQCMD, ND_CAT_ENQCMD, ND_SET_ENQCMD, 156, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ENQCMD, + 0, + 0|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_rM, ND_OPS_unknown, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_oq, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:227 Instruction:"ENQCMDS rM?,Moq" Encoding:"0xF3 0x0F 0x38 0xF8 /r:mem"/"M" + { + ND_INS_ENQCMDS, ND_CAT_ENQCMD, ND_SET_ENQCMD, 157, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ENQCMD, + 0, + 0|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_rM, ND_OPS_unknown, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_oq, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:228 Instruction:"ENTER Iw,Ib" Encoding:"0xC8 iw ib"/"II" + { + ND_INS_ENTER, ND_CAT_MISC, ND_SET_I186, 158, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_I, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rBP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rSP, ND_OPS_ssz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:229 Instruction:"EXTRACTPS Ed,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x17 /r ib"/"MRI" + { + ND_INS_EXTRACTPS, ND_CAT_SSE, ND_SET_SSE4, 159, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:230 Instruction:"EXTRQ Uq,Ib,Ib" Encoding:"0x66 0x0F 0x78 /0 modrmpmp ib ib"/"MII" + { + ND_INS_EXTRQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 160, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, + 0, + 0, + 0, + 0, + OP(ND_OPT_U, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:231 Instruction:"EXTRQ Vdq,Uq" Encoding:"0x66 0x0F 0x79 /r:reg"/"RM" + { + ND_INS_EXTRQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 160, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:232 Instruction:"F2XM1" Encoding:"0xD9 /0xF0"/"" + { + ND_INS_F2XM1, ND_CAT_X87_ALU, ND_SET_X87, 161, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:233 Instruction:"FABS" Encoding:"0xD9 /0xE1"/"" + { + ND_INS_FABS, ND_CAT_X87_ALU, ND_SET_X87, 162, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:234 Instruction:"FADD ST(0),Mfd" Encoding:"0xD8 /0:mem"/"M" + { + ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 163, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fd, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:235 Instruction:"FADD ST(0),ST(i)" Encoding:"0xD8 /0:reg"/"M" + { + ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 163, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:236 Instruction:"FADD ST(0),Mfq" Encoding:"0xDC /0:mem"/"M" + { + ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 163, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fq, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:237 Instruction:"FADD ST(i),ST(0)" Encoding:"0xDC /0:reg"/"M" + { + ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 163, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:238 Instruction:"FADDP ST(i),ST(0)" Encoding:"0xDE /0:reg"/"M" + { + ND_INS_FADDP, ND_CAT_X87_ALU, ND_SET_X87, 164, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:239 Instruction:"FBLD ST(0),Mfa" Encoding:"0xDF /4:mem"/"M" + { + ND_INS_FBLD, ND_CAT_X87_ALU, ND_SET_X87, 165, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_fa, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:240 Instruction:"FBSTP Mfa,ST(0)" Encoding:"0xDF /6:mem"/"M" + { + ND_INS_FBSTP, ND_CAT_X87_ALU, ND_SET_X87, 166, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_fa, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:241 Instruction:"FCHS" Encoding:"0xD9 /0xE0"/"" + { + ND_INS_FCHS, ND_CAT_X87_ALU, ND_SET_X87, 167, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:242 Instruction:"FCMOVB ST(0),ST(i)" Encoding:"0xDA /0:reg"/"M" + { + ND_INS_FCMOVB, ND_CAT_X87_ALU, ND_SET_X87, 168, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_CW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:243 Instruction:"FCMOVBE ST(0),ST(i)" Encoding:"0xDA /2:reg"/"M" + { + ND_INS_FCMOVBE, ND_CAT_X87_ALU, ND_SET_X87, 169, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_CW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:244 Instruction:"FCMOVE ST(0),ST(i)" Encoding:"0xDA /1:reg"/"M" + { + ND_INS_FCMOVE, ND_CAT_X87_ALU, ND_SET_X87, 170, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_CW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:245 Instruction:"FCMOVNB ST(0),ST(i)" Encoding:"0xDB /0:reg"/"M" + { + ND_INS_FCMOVNB, ND_CAT_X87_ALU, ND_SET_X87, 171, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_CW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:246 Instruction:"FCMOVNBE ST(0),ST(i)" Encoding:"0xDB /2:reg"/"M" + { + ND_INS_FCMOVNBE, ND_CAT_X87_ALU, ND_SET_X87, 172, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_CW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:247 Instruction:"FCMOVNE ST(0),ST(i)" Encoding:"0xDB /1:reg"/"M" + { + ND_INS_FCMOVNE, ND_CAT_X87_ALU, ND_SET_X87, 173, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_CW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:248 Instruction:"FCMOVNU ST(0),ST(i)" Encoding:"0xDB /3:reg"/"M" + { + ND_INS_FCMOVNU, ND_CAT_X87_ALU, ND_SET_X87, 174, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_PF, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_CW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:249 Instruction:"FCMOVU ST(0),ST(i)" Encoding:"0xDA /3:reg"/"M" + { + ND_INS_FCMOVU, ND_CAT_X87_ALU, ND_SET_X87, 175, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_PF, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_CW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:250 Instruction:"FCOM ST(0),Mfd" Encoding:"0xD8 /2:mem"/"M" + { + ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 176, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_fd, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:251 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xD8 /2:reg"/"M" + { + ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 176, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:252 Instruction:"FCOM ST(0),Mfq" Encoding:"0xDC /2:mem"/"M" + { + ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 176, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_fq, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:253 Instruction:"FCOM ST(i),ST(0)" Encoding:"0xDC /2:reg"/"M" + { + ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 176, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:254 Instruction:"FCOMI ST(0),ST(i)" Encoding:"0xDB /6:reg"/"M" + { + ND_INS_FCOMI, ND_CAT_X87_ALU, ND_SET_X87, 177, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_OF, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:255 Instruction:"FCOMIP ST(0),ST(i)" Encoding:"0xDF /6:reg"/"M" + { + ND_INS_FCOMIP, ND_CAT_X87_ALU, ND_SET_X87, 178, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_OF, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:256 Instruction:"FCOMP ST(0),Mfd" Encoding:"0xD8 /3:mem"/"M" + { + ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 179, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_fd, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:257 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xD8 /3:reg"/"M" + { + ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 179, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:258 Instruction:"FCOMP ST(0),Mfq" Encoding:"0xDC /3:mem"/"M" + { + ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 179, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_fq, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:259 Instruction:"FCOMP ST(i),ST(0)" Encoding:"0xDC /3:reg"/"M" + { + ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 179, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:260 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDE /2:reg"/"M" + { + ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 179, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:261 Instruction:"FCOMPP" Encoding:"0xDE /0xD9"/"" + { + ND_INS_FCOMPP, ND_CAT_X87_ALU, ND_SET_X87, 180, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:262 Instruction:"FCOS" Encoding:"0xD9 /0xFF"/"" + { + ND_INS_FCOS, ND_CAT_X87_ALU, ND_SET_X87, 181, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:263 Instruction:"FDECSTP" Encoding:"0xD9 /0xF6"/"" + { + ND_INS_FDECSTP, ND_CAT_X87_ALU, ND_SET_X87, 182, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:264 Instruction:"FDIV ST(0),Mfd" Encoding:"0xD8 /6:mem"/"M" + { + ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 183, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fd, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:265 Instruction:"FDIV ST(0),ST(i)" Encoding:"0xD8 /6:reg"/"M" + { + ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 183, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:266 Instruction:"FDIV ST(0),Mfq" Encoding:"0xDC /6:mem"/"M" + { + ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 183, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fq, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:267 Instruction:"FDIV ST(i),ST(0)" Encoding:"0xDC /7:reg"/"M" + { + ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 183, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:268 Instruction:"FDIVP ST(i),ST(0)" Encoding:"0xDE /7:reg"/"M" + { + ND_INS_FDIVP, ND_CAT_X87_ALU, ND_SET_X87, 184, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:269 Instruction:"FDIVR ST(0),Mfd" Encoding:"0xD8 /7:mem"/"M" + { + ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 185, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fd, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:270 Instruction:"FDIVR ST(0),ST(i)" Encoding:"0xD8 /7:reg"/"M" + { + ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 185, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:271 Instruction:"FDIVR ST(0),Mfq" Encoding:"0xDC /7:mem"/"M" + { + ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 185, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fq, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:272 Instruction:"FDIVR ST(i),ST(0)" Encoding:"0xDC /6:reg"/"M" + { + ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 185, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:273 Instruction:"FDIVRP ST(i),ST(0)" Encoding:"0xDE /6:reg"/"M" + { + ND_INS_FDIVRP, ND_CAT_X87_ALU, ND_SET_X87, 186, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:274 Instruction:"FEMMS" Encoding:"0x0F 0x0E"/"" + { + ND_INS_FEMMS, ND_CAT_MMX, ND_SET_3DNOW, 187, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + }, + + // Pos:275 Instruction:"FFREE ST(i)" Encoding:"0xDD /0:reg"/"M" + { + ND_INS_FFREE, ND_CAT_X87_ALU, ND_SET_X87, 188, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_TAG, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:276 Instruction:"FFREEP ST(i)" Encoding:"0xDF /0:reg"/"M" + { + ND_INS_FFREEP, ND_CAT_X87_ALU, ND_SET_X87, 189, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_TAG, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:277 Instruction:"FIADD ST(0),Md" Encoding:"0xDA /0:mem"/"M" + { + ND_INS_FIADD, ND_CAT_X87_ALU, ND_SET_X87, 190, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:278 Instruction:"FIADD ST(0),Mw" Encoding:"0xDE /0:mem"/"M" + { + ND_INS_FIADD, ND_CAT_X87_ALU, ND_SET_X87, 190, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:279 Instruction:"FICOM ST(0),Md" Encoding:"0xDA /2:mem"/"M" + { + ND_INS_FICOM, ND_CAT_X87_ALU, ND_SET_X87, 191, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:280 Instruction:"FICOM ST(0),Mw" Encoding:"0xDE /2:mem"/"M" + { + ND_INS_FICOM, ND_CAT_X87_ALU, ND_SET_X87, 191, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:281 Instruction:"FICOMP ST(0),Md" Encoding:"0xDA /3:mem"/"M" + { + ND_INS_FICOMP, ND_CAT_X87_ALU, ND_SET_X87, 192, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:282 Instruction:"FICOMP ST(0),Mw" Encoding:"0xDE /3:mem"/"M" + { + ND_INS_FICOMP, ND_CAT_X87_ALU, ND_SET_X87, 192, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:283 Instruction:"FIDIV ST(0),Md" Encoding:"0xDA /6:mem"/"M" + { + ND_INS_FIDIV, ND_CAT_X87_ALU, ND_SET_X87, 193, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:284 Instruction:"FIDIV ST(0),Mw" Encoding:"0xDE /6:mem"/"M" + { + ND_INS_FIDIV, ND_CAT_X87_ALU, ND_SET_X87, 193, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:285 Instruction:"FIDIVR ST(0),Md" Encoding:"0xDA /7:mem"/"M" + { + ND_INS_FIDIVR, ND_CAT_X87_ALU, ND_SET_X87, 194, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:286 Instruction:"FIDIVR ST(0),Mw" Encoding:"0xDE /7:mem"/"M" + { + ND_INS_FIDIVR, ND_CAT_X87_ALU, ND_SET_X87, 194, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:287 Instruction:"FILD ST(0),Md" Encoding:"0xDB /0:mem"/"M" + { + ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 195, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:288 Instruction:"FILD ST(0),Mw" Encoding:"0xDF /0:mem"/"M" + { + ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 195, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:289 Instruction:"FILD ST(0),Mq" Encoding:"0xDF /5:mem"/"M" + { + ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 195, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:290 Instruction:"FIMUL ST(0),Md" Encoding:"0xDA /1:mem"/"M" + { + ND_INS_FIMUL, ND_CAT_X87_ALU, ND_SET_X87, 196, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:291 Instruction:"FIMUL ST(0),Mw" Encoding:"0xDE /1:mem"/"M" + { + ND_INS_FIMUL, ND_CAT_X87_ALU, ND_SET_X87, 196, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:292 Instruction:"FINCSTP" Encoding:"0xD9 /0xF7"/"" + { + ND_INS_FINCSTP, ND_CAT_X87_ALU, ND_SET_X87, 197, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:293 Instruction:"FIST Md,ST(0)" Encoding:"0xDB /2:mem"/"M" + { + ND_INS_FIST, ND_CAT_X87_ALU, ND_SET_X87, 198, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:294 Instruction:"FIST Mw,ST(0)" Encoding:"0xDF /2:mem"/"M" + { + ND_INS_FIST, ND_CAT_X87_ALU, ND_SET_X87, 198, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:295 Instruction:"FISTP Md,ST(0)" Encoding:"0xDB /3:mem"/"M" + { + ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 199, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:296 Instruction:"FISTP Mw,ST(0)" Encoding:"0xDF /3:mem"/"M" + { + ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 199, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:297 Instruction:"FISTP Mq,ST(0)" Encoding:"0xDF /7:mem"/"M" + { + ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 199, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:298 Instruction:"FISTTP Md,ST(0)" Encoding:"0xDB /1:mem"/"M" + { + ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 200, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:299 Instruction:"FISTTP Mq,ST(0)" Encoding:"0xDD /1:mem"/"M" + { + ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 200, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:300 Instruction:"FISTTP Mw,ST(0)" Encoding:"0xDF /1:mem"/"M" + { + ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 200, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:301 Instruction:"FISUB ST(0),Md" Encoding:"0xDA /4:mem"/"M" + { + ND_INS_FISUB, ND_CAT_X87_ALU, ND_SET_X87, 201, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:302 Instruction:"FISUB ST(0),Mw" Encoding:"0xDE /4:mem"/"M" + { + ND_INS_FISUB, ND_CAT_X87_ALU, ND_SET_X87, 201, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:303 Instruction:"FISUBR ST(0),Md" Encoding:"0xDA /5:mem"/"M" + { + ND_INS_FISUBR, ND_CAT_X87_ALU, ND_SET_X87, 202, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:304 Instruction:"FISUBR ST(0),Mw" Encoding:"0xDE /5:mem"/"M" + { + ND_INS_FISUBR, ND_CAT_X87_ALU, ND_SET_X87, 202, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:305 Instruction:"FLD ST(0),Mfd" Encoding:"0xD9 /0:mem"/"M" + { + ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 203, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_fd, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:306 Instruction:"FLD ST(0),ST(i)" Encoding:"0xD9 /0:reg"/"M" + { + ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 203, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:307 Instruction:"FLD ST(0),Mft" Encoding:"0xDB /5:mem"/"M" + { + ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 203, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:308 Instruction:"FLD ST(0),Mfq" Encoding:"0xDD /0:mem"/"M" + { + ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 203, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_fq, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:309 Instruction:"FLD1" Encoding:"0xD9 /0xE8"/"" + { + ND_INS_FLD1, ND_CAT_X87_ALU, ND_SET_X87, 204, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:310 Instruction:"FLDCW Mw" Encoding:"0xD9 /5:mem"/"M" + { + ND_INS_FLDCW, ND_CAT_X87_ALU, ND_SET_X87, 205, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_CONTROL, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:311 Instruction:"FLDENV Mfe" Encoding:"0xD9 /4:mem"/"M" + { + ND_INS_FLDENV, ND_CAT_X87_ALU, ND_SET_X87, 206, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_fe, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:312 Instruction:"FLDL2E" Encoding:"0xD9 /0xEA"/"" + { + ND_INS_FLDL2E, ND_CAT_X87_ALU, ND_SET_X87, 207, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:313 Instruction:"FLDL2T" Encoding:"0xD9 /0xE9"/"" + { + ND_INS_FLDL2T, ND_CAT_X87_ALU, ND_SET_X87, 208, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:314 Instruction:"FLDLG2" Encoding:"0xD9 /0xEC"/"" + { + ND_INS_FLDLG2, ND_CAT_X87_ALU, ND_SET_X87, 209, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:315 Instruction:"FLDLN2" Encoding:"0xD9 /0xED"/"" + { + ND_INS_FLDLN2, ND_CAT_X87_ALU, ND_SET_X87, 210, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:316 Instruction:"FLDPI" Encoding:"0xD9 /0xEB"/"" + { + ND_INS_FLDPI, ND_CAT_X87_ALU, ND_SET_X87, 211, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:317 Instruction:"FLDZ" Encoding:"0xD9 /0xEE"/"" + { + ND_INS_FLDZ, ND_CAT_X87_ALU, ND_SET_X87, 212, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:318 Instruction:"FMUL ST(0),Mfd" Encoding:"0xD8 /1:mem"/"M" + { + ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 213, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fd, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:319 Instruction:"FMUL ST(0),ST(i)" Encoding:"0xD8 /1:reg"/"M" + { + ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 213, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:320 Instruction:"FMUL ST(0),Mfq" Encoding:"0xDC /1:mem"/"M" + { + ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 213, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fq, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:321 Instruction:"FMUL ST(i),ST(0)" Encoding:"0xDC /1:reg"/"M" + { + ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 213, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:322 Instruction:"FMULP ST(i),ST(0)" Encoding:"0xDE /1:reg"/"M" + { + ND_INS_FMULP, ND_CAT_X87_ALU, ND_SET_X87, 214, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:323 Instruction:"FNCLEX" Encoding:"0xDB /0xE2"/"" + { + ND_INS_FNCLEX, ND_CAT_X87_ALU, ND_SET_X87, 215, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:324 Instruction:"FNDISI" Encoding:"0xDB /0xE1"/"" + { + ND_INS_FNDISI, ND_CAT_X87_ALU, ND_SET_X87, 216, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:325 Instruction:"FNINIT" Encoding:"0xDB /0xE3"/"" + { + ND_INS_FNINIT, ND_CAT_X87_ALU, ND_SET_X87, 217, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0x00, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_CONTROL, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_X87_TAG, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:326 Instruction:"FNOP" Encoding:"0xD9 /0xD0"/"" + { + ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 218, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:327 Instruction:"FNOP" Encoding:"0xDB /0xE0"/"" + { + ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 218, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:328 Instruction:"FNOP" Encoding:"0xDB /0xE4"/"" + { + ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 218, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:329 Instruction:"FNSAVE Mfs" Encoding:"0xDD /6:mem"/"M" + { + ND_INS_FNSAVE, ND_CAT_X87_ALU, ND_SET_X87, 219, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0x00, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_fs, ND_OPF_W, 0, 0), + OP(ND_OPT_X87_CONTROL, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_X87_TAG, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:330 Instruction:"FNSTCW Mw" Encoding:"0xD9 /7:mem"/"M" + { + ND_INS_FNSTCW, ND_CAT_X87_ALU, ND_SET_X87, 220, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_X87_CONTROL, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:331 Instruction:"FNSTENV Mfe" Encoding:"0xD9 /6:mem"/"M" + { + ND_INS_FNSTENV, ND_CAT_X87_ALU, ND_SET_X87, 221, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_fe, ND_OPF_W, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:332 Instruction:"FNSTSW Mw" Encoding:"0xDD /7:mem"/"M" + { + ND_INS_FNSTSW, ND_CAT_X87_ALU, ND_SET_X87, 222, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:333 Instruction:"FNSTSW AX" Encoding:"0xDF /0xE0"/"" + { + ND_INS_FNSTSW, ND_CAT_X87_ALU, ND_SET_X87, 222, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:334 Instruction:"FPATAN" Encoding:"0xD9 /0xF3"/"" + { + ND_INS_FPATAN, ND_CAT_X87_ALU, ND_SET_X87, 223, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:335 Instruction:"FPREM" Encoding:"0xD9 /0xF8"/"" + { + ND_INS_FPREM, ND_CAT_X87_ALU, ND_SET_X87, 224, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:336 Instruction:"FPREM1" Encoding:"0xD9 /0xF5"/"" + { + ND_INS_FPREM1, ND_CAT_X87_ALU, ND_SET_X87, 225, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:337 Instruction:"FPTAN" Encoding:"0xD9 /0xF2"/"" + { + ND_INS_FPTAN, ND_CAT_X87_ALU, ND_SET_X87, 226, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:338 Instruction:"FRINEAR" Encoding:"0xDF /0xFC"/"" + { + ND_INS_FRINEAR, ND_CAT_X87_ALU, ND_SET_X87, 227, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:339 Instruction:"FRNDINT" Encoding:"0xD9 /0xFC"/"" + { + ND_INS_FRNDINT, ND_CAT_X87_ALU, ND_SET_X87, 228, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:340 Instruction:"FRSTOR Mfs" Encoding:"0xDD /4:mem"/"M" + { + ND_INS_FRSTOR, ND_CAT_X87_ALU, ND_SET_X87, 229, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_fs, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_CONTROL, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:341 Instruction:"FSCALE" Encoding:"0xD9 /0xFD"/"" + { + ND_INS_FSCALE, ND_CAT_X87_ALU, ND_SET_X87, 230, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:342 Instruction:"FSIN" Encoding:"0xD9 /0xFE"/"" + { + ND_INS_FSIN, ND_CAT_X87_ALU, ND_SET_X87, 231, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:343 Instruction:"FSINCOS" Encoding:"0xD9 /0xFB"/"" + { + ND_INS_FSINCOS, ND_CAT_X87_ALU, ND_SET_X87, 232, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:344 Instruction:"FSQRT" Encoding:"0xD9 /0xFA"/"" + { + ND_INS_FSQRT, ND_CAT_X87_ALU, ND_SET_X87, 233, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:345 Instruction:"FST Mfd,ST(0)" Encoding:"0xD9 /2:mem"/"M" + { + ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 234, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_fd, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:346 Instruction:"FST Mfq,ST(0)" Encoding:"0xDD /2:mem"/"M" + { + ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 234, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_fq, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:347 Instruction:"FST ST(0),ST(i)" Encoding:"0xDD /2:reg"/"M" + { + ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 234, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:348 Instruction:"FSTDW AX" Encoding:"0xDF /0xE1"/"" + { + ND_INS_FSTDW, ND_CAT_X87_ALU, ND_SET_X87, 235, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_W, 0, 0), + }, + + // Pos:349 Instruction:"FSTP Mfd,ST(0)" Encoding:"0xD9 /3:mem"/"M" + { + ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 236, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_fd, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:350 Instruction:"FSTP Mft,ST(0)" Encoding:"0xDB /7:mem"/"M" + { + ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 236, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:351 Instruction:"FSTP Mfq,ST(0)" Encoding:"0xDD /3:mem"/"M" + { + ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 236, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_fq, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:352 Instruction:"FSTP ST(0),ST(i)" Encoding:"0xDD /3:reg"/"M" + { + ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 236, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:353 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /2:reg"/"M" + { + ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 236, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:354 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /3:reg"/"M" + { + ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 236, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:355 Instruction:"FSTPNCE ST(i),ST(0)" Encoding:"0xD9 /3:reg"/"M" + { + ND_INS_FSTPNCE, ND_CAT_X87_ALU, ND_SET_X87, 237, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:356 Instruction:"FSTSG AX" Encoding:"0xDF /0xE2"/"" + { + ND_INS_FSTSG, ND_CAT_X87_ALU, ND_SET_X87, 238, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_W, 0, 0), + }, + + // Pos:357 Instruction:"FSUB ST(0),Mfd" Encoding:"0xD8 /4:mem"/"M" + { + ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 239, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fd, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:358 Instruction:"FSUB ST(0),ST(i)" Encoding:"0xD8 /4:reg"/"M" + { + ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 239, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:359 Instruction:"FSUB ST(0),Mfq" Encoding:"0xDC /4:mem"/"M" + { + ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 239, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fq, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:360 Instruction:"FSUB ST(i),ST(0)" Encoding:"0xDC /5:reg"/"M" + { + ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 239, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:361 Instruction:"FSUBP ST(i),ST(0)" Encoding:"0xDE /5:reg"/"M" + { + ND_INS_FSUBP, ND_CAT_X87_ALU, ND_SET_X87, 240, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:362 Instruction:"FSUBR ST(0),Mfd" Encoding:"0xD8 /5:mem"/"M" + { + ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 241, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fd, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:363 Instruction:"FSUBR ST(0),ST(i)" Encoding:"0xD8 /5:reg"/"M" + { + ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 241, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:364 Instruction:"FSUBR ST(0),Mfq" Encoding:"0xDC /5:mem"/"M" + { + ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 241, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fq, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:365 Instruction:"FSUBR ST(i),ST(0)" Encoding:"0xDC /4:reg"/"M" + { + ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 241, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:366 Instruction:"FSUBRP ST(i),ST(0)" Encoding:"0xDE /4:reg"/"M" + { + ND_INS_FSUBRP, ND_CAT_X87_ALU, ND_SET_X87, 242, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:367 Instruction:"FTST" Encoding:"0xD9 /0xE4"/"" + { + ND_INS_FTST, ND_CAT_X87_ALU, ND_SET_X87, 243, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:368 Instruction:"FUCOM ST(0),ST(i)" Encoding:"0xDD /4:reg"/"M" + { + ND_INS_FUCOM, ND_CAT_X87_ALU, ND_SET_X87, 244, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:369 Instruction:"FUCOMI ST(0),ST(i)" Encoding:"0xDB /5:reg"/"M" + { + ND_INS_FUCOMI, ND_CAT_X87_ALU, ND_SET_X87, 245, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_OF, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:370 Instruction:"FUCOMIP ST(0),ST(i)" Encoding:"0xDF /5:reg"/"M" + { + ND_INS_FUCOMIP, ND_CAT_X87_ALU, ND_SET_X87, 246, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_OF, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:371 Instruction:"FUCOMP ST(0),ST(i)" Encoding:"0xDD /5:reg"/"M" + { + ND_INS_FUCOMP, ND_CAT_X87_ALU, ND_SET_X87, 247, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:372 Instruction:"FUCOMPP" Encoding:"0xDA /0xE9"/"" + { + ND_INS_FUCOMPP, ND_CAT_X87_ALU, ND_SET_X87, 248, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:373 Instruction:"FXAM" Encoding:"0xD9 /0xE5"/"" + { + ND_INS_FXAM, ND_CAT_X87_ALU, ND_SET_X87, 249, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:374 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xD9 /1:reg"/"M" + { + ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 250, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:375 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDD /1:reg"/"M" + { + ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 250, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:376 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDF /1:reg"/"M" + { + ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 250, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_X87_TAG, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:377 Instruction:"FXRSTOR Mrx" Encoding:"NP 0x0F 0xAE /1:mem"/"M" + { + ND_INS_FXRSTOR, ND_CAT_SSE, ND_SET_FXSAVE, 251, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_rx, ND_OPF_R, 0, 0), + OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:378 Instruction:"FXSAVE Mrx" Encoding:"NP 0x0F 0xAE /0:mem"/"M" + { + ND_INS_FXSAVE, ND_CAT_SSE, ND_SET_FXSAVE, 252, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_rx, ND_OPF_W, 0, 0), + OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:379 Instruction:"FXTRACT" Encoding:"0xD9 /0xF4"/"" + { + ND_INS_FXTRACT, ND_CAT_X87_ALU, ND_SET_X87, 253, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:380 Instruction:"FYL2X" Encoding:"0xD9 /0xF1"/"" + { + ND_INS_FYL2X, ND_CAT_X87_ALU, ND_SET_X87, 254, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:381 Instruction:"FYL2XP1" Encoding:"0xD9 /0xF9"/"" + { + ND_INS_FYL2XP1, ND_CAT_X87_ALU, ND_SET_X87, 255, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:382 Instruction:"GETSEC" Encoding:"NP 0x0F 0x37"/"" + { + ND_INS_GETSEC, ND_CAT_SYSTEM, ND_SET_SMX, 256, + ND_MOD_R0|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, ND_CFF_SMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rBX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:383 Instruction:"GF2P8AFFINEINVQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCF /r ib"/"RMI" + { + ND_INS_GF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 257, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:384 Instruction:"GF2P8AFFINEQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCE /r ib"/"RMI" + { + ND_INS_GF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 258, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:385 Instruction:"GF2P8MULB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xCF /r"/"RM" + { + ND_INS_GF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 259, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:386 Instruction:"HADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7C /r"/"RM" + { + ND_INS_HADDPD, ND_CAT_SSE, ND_SET_SSE3, 260, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:387 Instruction:"HADDPS Vps,Wps" Encoding:"0xF2 0x0F 0x7C /r"/"RM" + { + ND_INS_HADDPS, ND_CAT_SSE, ND_SET_SSE3, 261, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:388 Instruction:"HLT" Encoding:"0xF4"/"" + { + ND_INS_HLT, ND_CAT_SYSTEM, ND_SET_I86, 262, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:389 Instruction:"HSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7D /r"/"RM" + { + ND_INS_HSUBPD, ND_CAT_SSE, ND_SET_SSE3, 263, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:390 Instruction:"HSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0x7D /r"/"RM" + { + ND_INS_HSUBPS, ND_CAT_SSE, ND_SET_SSE3, 264, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:391 Instruction:"IDIV Eb" Encoding:"0xF6 /7"/"M" + { + ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 265, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:392 Instruction:"IDIV Ev" Encoding:"0xF7 /7"/"M" + { + ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 265, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:393 Instruction:"IMUL Gv,Ev" Encoding:"0x0F 0xAF /r"/"RM" + { + ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 266, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:394 Instruction:"IMUL Gv,Ev,Iz" Encoding:"0x69 /r iz"/"RMI" + { + ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 266, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:395 Instruction:"IMUL Gv,Ev,Ib" Encoding:"0x6B /r ib"/"RMI" + { + ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 266, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:396 Instruction:"IMUL Eb" Encoding:"0xF6 /5"/"M" + { + ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 266, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:397 Instruction:"IMUL Ev" Encoding:"0xF7 /5"/"M" + { + ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 266, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:398 Instruction:"IN AL,Ib" Encoding:"0xE4 ib"/"I" + { + ND_INS_IN, ND_CAT_IO, ND_SET_I86, 267, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:399 Instruction:"IN eAX,Ib" Encoding:"0xE5 ib"/"I" + { + ND_INS_IN, ND_CAT_IO, ND_SET_I86, 267, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_z, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:400 Instruction:"IN AL,DX" Encoding:"0xEC"/"" + { + ND_INS_IN, ND_CAT_IO, ND_SET_I86, 267, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:401 Instruction:"IN eAX,DX" Encoding:"0xED"/"" + { + ND_INS_IN, ND_CAT_IO, ND_SET_I86, 267, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_z, ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:402 Instruction:"INC Zv" Encoding:"0x40"/"O" + { + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:403 Instruction:"INC Zv" Encoding:"0x41"/"O" + { + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:404 Instruction:"INC Zv" Encoding:"0x42"/"O" + { + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:405 Instruction:"INC Zv" Encoding:"0x43"/"O" + { + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:406 Instruction:"INC Zv" Encoding:"0x44"/"O" + { + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:407 Instruction:"INC Zv" Encoding:"0x45"/"O" + { + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:408 Instruction:"INC Zv" Encoding:"0x46"/"O" + { + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:409 Instruction:"INC Zv" Encoding:"0x47"/"O" + { + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:410 Instruction:"INC Eb" Encoding:"0xFE /0"/"M" + { + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:411 Instruction:"INC Ev" Encoding:"0xFF /0"/"M" + { + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:412 Instruction:"INCSSPD Rd" Encoding:"0xF3 0x0F 0xAE /5:reg"/"M" + { + ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET, 269, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_SSP, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:413 Instruction:"INCSSPQ Rq" Encoding:"0xF3 rexw 0x0F 0xAE /5:reg"/"M" + { + ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET, 270, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_SSP, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:414 Instruction:"INSB Yb,DX" Encoding:"0x6C"/"" + { + ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 271, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:415 Instruction:"INSB Yb,DX" Encoding:"rep 0x6C"/"" + { + ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 271, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:416 Instruction:"INSD Yz,DX" Encoding:"0x6D"/"" + { + ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 272, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_z, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:417 Instruction:"INSD Yz,DX" Encoding:"rep 0x6D"/"" + { + ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 272, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_z, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:418 Instruction:"INSERTPS Vdq,Md,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:mem ib"/"RMI" + { + ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 273, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:419 Instruction:"INSERTPS Vdq,Udq,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:reg ib"/"RMI" + { + ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 273, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:420 Instruction:"INSERTQ Vdq,Udq,Ib,Ib" Encoding:"0xF2 0x0F 0x78 /r ib ib"/"RMII" + { + ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 274, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:421 Instruction:"INSERTQ Vdq,Udq" Encoding:"0xF2 0x0F 0x79 /r:reg"/"RM" + { + ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 274, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:422 Instruction:"INSW Yz,DX" Encoding:"ds16 0x6D"/"" + { + ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 275, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_z, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:423 Instruction:"INSW Yz,DX" Encoding:"rep ds16 0x6D"/"" + { + ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 275, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_z, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:424 Instruction:"INT Ib" Encoding:"0xCD ib"/"I" + { + ND_INS_INT, ND_CAT_INTERRUPT, ND_SET_I86, 276, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_VM, + 0|REG_RFLAG_VM|REG_RFLAG_IF|REG_RFLAG_NT|REG_RFLAG_AC|REG_RFLAG_RF|REG_RFLAG_TF, + 0, + 0, + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:425 Instruction:"INT1" Encoding:"0xF1"/"" + { + ND_INS_INT1, ND_CAT_INTERRUPT, ND_SET_I86, 277, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_VM, + 0|REG_RFLAG_VM|REG_RFLAG_IF|REG_RFLAG_NT|REG_RFLAG_AC|REG_RFLAG_RF|REG_RFLAG_TF, + 0, + 0, + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:426 Instruction:"INT3" Encoding:"0xCC"/"" + { + ND_INS_INT3, ND_CAT_INTERRUPT, ND_SET_I86, 278, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_VM, + 0|REG_RFLAG_VM|REG_RFLAG_IF|REG_RFLAG_NT|REG_RFLAG_AC|REG_RFLAG_RF|REG_RFLAG_TF, + 0, + 0, + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:427 Instruction:"INTO" Encoding:"0xCE"/"" + { + ND_INS_INTO, ND_CAT_INTERRUPT, ND_SET_I86, 279, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_VM, + 0|REG_RFLAG_VM|REG_RFLAG_IF|REG_RFLAG_NT|REG_RFLAG_AC|REG_RFLAG_RF|REG_RFLAG_TF, + 0, + 0, + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:428 Instruction:"INVD" Encoding:"0x0F 0x08"/"" + { + ND_INS_INVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 280, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:429 Instruction:"INVEPT Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x80 /r:mem"/"RM" + { + ND_INS_INVEPT, ND_CAT_VTX, ND_SET_VTX, 281, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_VTX, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:430 Instruction:"INVLPG Mb" Encoding:"0x0F 0x01 /7:mem"/"M" + { + ND_INS_INVLPG, ND_CAT_SYSTEM, ND_SET_I486REAL, 282, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:431 Instruction:"INVLPGA" Encoding:"0x0F 0x01 /0xDF"/"" + { + ND_INS_INVLPGA, ND_CAT_SYSTEM, ND_SET_SVM, 283, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:432 Instruction:"INVLPGB" Encoding:"0x0F 0x01 /0xFE"/"" + { + ND_INS_INVLPGB, ND_CAT_SYSTEM, ND_SET_INVLPGB, 284, + ND_MOD_R0|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_INVLPGB, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:433 Instruction:"INVPCID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x82 /r:mem"/"RM" + { + ND_INS_INVPCID, ND_CAT_MISC, ND_SET_INVPCID, 285, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_INVPCID, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:434 Instruction:"INVVPID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x81 /r:mem"/"RM" + { + ND_INS_INVVPID, ND_CAT_VTX, ND_SET_VTX, 286, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_VTX, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:435 Instruction:"IRETD" Encoding:"ds32 0xCF"/"" + { + ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 287, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:436 Instruction:"IRETQ" Encoding:"ds64 0xCF"/"" + { + ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 288, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:437 Instruction:"IRETW" Encoding:"ds16 0xCF"/"" + { + ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 289, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:438 Instruction:"JBE Jz" Encoding:"0x0F 0x86 cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 290, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:439 Instruction:"JBE Jb" Encoding:"0x76 cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 290, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:440 Instruction:"JC Jz" Encoding:"0x0F 0x82 cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 291, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_CF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:441 Instruction:"JC Jb" Encoding:"0x72 cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 291, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_CF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:442 Instruction:"JCXZ Jb" Encoding:"as16 0xE3 cb"/"D" + { + ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 292, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:443 Instruction:"JECXZ Jb" Encoding:"as32 0xE3 cb"/"D" + { + ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 293, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:444 Instruction:"JL Jz" Encoding:"0x0F 0x8C cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 294, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:445 Instruction:"JL Jb" Encoding:"0x7C cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 294, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:446 Instruction:"JLE Jz" Encoding:"0x0F 0x8E cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 295, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:447 Instruction:"JLE Jb" Encoding:"0x7E cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 295, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:448 Instruction:"JMP Jz" Encoding:"0xE9 cz"/"D" + { + ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 296, + ND_MOD_ANY, + ND_PREF_BND, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:449 Instruction:"JMP Jb" Encoding:"0xEB cb"/"D" + { + ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 296, + ND_MOD_ANY, + ND_PREF_BND, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:450 Instruction:"JMP Ev" Encoding:"0xFF /4"/"M" + { + ND_INS_JMPNI, ND_CAT_UNCOND_BR, ND_SET_I86, 296, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_DNT, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_CETT|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:451 Instruction:"JMPE Ev" Encoding:"0x0F 0x00 /6"/"M" + { + ND_INS_JMPE, ND_CAT_SYSTEM, ND_SET_I64, 297, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:452 Instruction:"JMPE Jz" Encoding:"0x0F 0xB8 cz"/"D" + { + ND_INS_JMPE, ND_CAT_UNCOND_BR, ND_SET_I64, 297, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:453 Instruction:"JMPF Ap" Encoding:"0xEA cp"/"D" + { + ND_INS_JMPFD, ND_CAT_UNCOND_BR, ND_SET_I86, 298, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_A, ND_OPS_p, ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:454 Instruction:"JMPF Mp" Encoding:"0xFF /5:mem"/"M" + { + ND_INS_JMPFI, ND_CAT_UNCOND_BR, ND_SET_I86, 298, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_p, ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:455 Instruction:"JNBE Jz" Encoding:"0x0F 0x87 cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 299, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:456 Instruction:"JNBE Jb" Encoding:"0x77 cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 299, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:457 Instruction:"JNC Jz" Encoding:"0x0F 0x83 cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 300, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_CF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:458 Instruction:"JNC Jb" Encoding:"0x73 cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 300, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_CF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:459 Instruction:"JNL Jz" Encoding:"0x0F 0x8D cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 301, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:460 Instruction:"JNL Jb" Encoding:"0x7D cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 301, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:461 Instruction:"JNLE Jz" Encoding:"0x0F 0x8F cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 302, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:462 Instruction:"JNLE Jb" Encoding:"0x7F cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 302, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:463 Instruction:"JNO Jz" Encoding:"0x0F 0x81 cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 303, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:464 Instruction:"JNO Jb" Encoding:"0x71 cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 303, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:465 Instruction:"JNP Jz" Encoding:"0x0F 0x8B cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 304, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_PF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:466 Instruction:"JNP Jb" Encoding:"0x7B cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 304, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_PF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:467 Instruction:"JNS Jz" Encoding:"0x0F 0x89 cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 305, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_SF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:468 Instruction:"JNS Jb" Encoding:"0x79 cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 305, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_SF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:469 Instruction:"JNZ Jz" Encoding:"0x0F 0x85 cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 306, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:470 Instruction:"JNZ Jb" Encoding:"0x75 cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 306, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:471 Instruction:"JO Jz" Encoding:"0x0F 0x80 cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 307, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:472 Instruction:"JO Jb" Encoding:"0x70 cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 307, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:473 Instruction:"JP Jz" Encoding:"0x0F 0x8A cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 308, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_PF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:474 Instruction:"JP Jb" Encoding:"0x7A cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 308, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_PF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:475 Instruction:"JRCXZ Jb" Encoding:"as64 0xE3 cb"/"D" + { + ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 309, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:476 Instruction:"JS Jz" Encoding:"0x0F 0x88 cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 310, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_SF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:477 Instruction:"JS Jb" Encoding:"0x78 cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 310, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_SF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:478 Instruction:"JZ Jz" Encoding:"0x0F 0x84 cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 311, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:479 Instruction:"JZ Jb" Encoding:"0x74 cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 311, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:480 Instruction:"KADDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4A /r:reg"/"RVM" + { + ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 312, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:481 Instruction:"KADDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x4A /r:reg"/"RVM" + { + ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 313, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:482 Instruction:"KADDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x4A /r:reg"/"RVM" + { + ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 314, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:483 Instruction:"KADDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4A /r:reg"/"RVM" + { + ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 315, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:484 Instruction:"KANDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x41 /r:reg"/"RVM" + { + ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512DQ, 316, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:485 Instruction:"KANDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x41 /r:reg"/"RVM" + { + ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 317, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:486 Instruction:"KANDNB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x42 /r:reg"/"RVM" + { + ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512DQ, 318, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:487 Instruction:"KANDND rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x42 /r:reg"/"RVM" + { + ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 319, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:488 Instruction:"KANDNQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x42 /r:reg"/"RVM" + { + ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 320, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:489 Instruction:"KANDNW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x42 /r:reg"/"RVM" + { + ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512F, 321, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:490 Instruction:"KANDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x41 /r:reg"/"RVM" + { + ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 322, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:491 Instruction:"KANDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x41 /r:reg"/"RVM" + { + ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512F, 323, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:492 Instruction:"KMERGE2L1H rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x48 /r:reg"/"RM" + { + ND_INS_KMERGE2L1H, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 324, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:493 Instruction:"KMERGE2L1L rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x49 /r:reg"/"RM" + { + ND_INS_KMERGE2L1L, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 325, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:494 Instruction:"KMOVB rKb,Mb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:mem"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 326, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:495 Instruction:"KMOVB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:reg"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 326, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:496 Instruction:"KMOVB Mb,rKb" Encoding:"vex m:1 p:1 l:0 w:0 0x91 /r:mem"/"MR" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 326, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:497 Instruction:"KMOVB rKb,Ry" Encoding:"vex m:1 p:1 l:0 w:0 0x92 /r:reg"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 326, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:498 Instruction:"KMOVB Gy,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x93 /r:reg"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 326, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:499 Instruction:"KMOVD rKd,Md" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:mem"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 327, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:500 Instruction:"KMOVD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:reg"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 327, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:501 Instruction:"KMOVD Md,rKd" Encoding:"vex m:1 p:1 l:0 w:1 0x91 /r:mem"/"MR" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 327, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:502 Instruction:"KMOVD rKd,Ry" Encoding:"vex m:1 p:3 l:0 w:0 0x92 /r:reg"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 327, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:503 Instruction:"KMOVD Gy,mKd" Encoding:"vex m:1 p:3 l:0 w:0 0x93 /r:reg"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 327, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:504 Instruction:"KMOVQ rKq,Mq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:mem"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 328, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:505 Instruction:"KMOVQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:reg"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 328, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:506 Instruction:"KMOVQ Mq,rKq" Encoding:"vex m:1 p:0 l:0 w:1 0x91 /r:mem"/"MR" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 328, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:507 Instruction:"KMOVQ rKq,Ry" Encoding:"vex m:1 p:3 l:0 w:1 0x92 /r:reg"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 328, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:508 Instruction:"KMOVQ Gy,mKq" Encoding:"vex m:1 p:3 l:0 w:1 0x93 /r:reg"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 328, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:509 Instruction:"KMOVW rKw,Mw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:mem"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 329, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:510 Instruction:"KMOVW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:reg"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 329, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:511 Instruction:"KMOVW Mw,rKw" Encoding:"vex m:1 p:0 l:0 w:0 0x91 /r:mem"/"MR" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 329, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:512 Instruction:"KMOVW rKw,Ry" Encoding:"vex m:1 p:0 l:0 w:0 0x92 /r:reg"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 329, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:513 Instruction:"KMOVW Gy,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x93 /r:reg"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 329, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:514 Instruction:"KNOTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x44 /r:reg"/"RM" + { + ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512DQ, 330, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:515 Instruction:"KNOTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x44 /r:reg"/"RM" + { + ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 331, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:516 Instruction:"KNOTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x44 /r:reg"/"RM" + { + ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 332, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:517 Instruction:"KNOTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x44 /r:reg"/"RM" + { + ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512F, 333, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:518 Instruction:"KORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x45 /r:reg"/"RVM" + { + ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 334, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:519 Instruction:"KORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x45 /r:reg"/"RVM" + { + ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 335, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:520 Instruction:"KORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x45 /r:reg"/"RVM" + { + ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 336, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:521 Instruction:"KORTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x98 /r:reg"/"RM" + { + ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 337, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:522 Instruction:"KORTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x98 /r:reg"/"RM" + { + ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 338, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:523 Instruction:"KORTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x98 /r:reg"/"RM" + { + ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 339, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:524 Instruction:"KORTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x98 /r:reg"/"RM" + { + ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512F, 340, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:525 Instruction:"KORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x45 /r:reg"/"RVM" + { + ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512F, 341, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:526 Instruction:"KSHIFTLB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x32 /r:reg ib"/"RMI" + { + ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512DQ, 342, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:527 Instruction:"KSHIFTLD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x33 /r:reg ib"/"RMI" + { + ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 343, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:528 Instruction:"KSHIFTLQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x33 /r:reg ib"/"RMI" + { + ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 344, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:529 Instruction:"KSHIFTLW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x32 /r:reg ib"/"RMI" + { + ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512F, 345, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:530 Instruction:"KSHIFTRB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x30 /r:reg ib"/"RMI" + { + ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512DQ, 346, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:531 Instruction:"KSHIFTRD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x31 /r:reg ib"/"RMI" + { + ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 347, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:532 Instruction:"KSHIFTRQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x31 /r:reg ib"/"RMI" + { + ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 348, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:533 Instruction:"KSHIFTRW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x30 /r:reg ib"/"RMI" + { + ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512F, 349, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:534 Instruction:"KTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x99 /r:reg"/"RM" + { + ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 350, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:535 Instruction:"KTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x99 /r:reg"/"RM" + { + ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 351, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:536 Instruction:"KTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x99 /r:reg"/"RM" + { + ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 352, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:537 Instruction:"KTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x99 /r:reg"/"RM" + { + ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 353, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:538 Instruction:"KUNPCKBW rKw,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4B /r:reg"/"RVM" + { + ND_INS_KUNPCKBW, ND_CAT_KMASK, ND_SET_AVX512F, 354, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:539 Instruction:"KUNPCKDQ rKq,vKd,mKd" Encoding:"vex m:1 p:0 l:1 w:1 0x4B /r:reg"/"RVM" + { + ND_INS_KUNPCKDQ, ND_CAT_KMASK, ND_SET_AVX512BW, 355, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:540 Instruction:"KUNPCKWD rKd,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4B /r:reg"/"RVM" + { + ND_INS_KUNPCKWD, ND_CAT_KMASK, ND_SET_AVX512BW, 356, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:541 Instruction:"KXNORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x46 /r:reg"/"RVM" + { + ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 357, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:542 Instruction:"KXNORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x46 /r:reg"/"RVM" + { + ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 358, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:543 Instruction:"KXNORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x46 /r:reg"/"RVM" + { + ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 359, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:544 Instruction:"KXNORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x46 /r:reg"/"RVM" + { + ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512F, 360, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:545 Instruction:"KXORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x47 /r:reg"/"RVM" + { + ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 361, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:546 Instruction:"KXORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x47 /r:reg"/"RVM" + { + ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 362, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:547 Instruction:"KXORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x47 /r:reg"/"RVM" + { + ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 363, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:548 Instruction:"KXORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x47 /r:reg"/"RVM" + { + ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512F, 364, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:549 Instruction:"LAHF" Encoding:"0x9F"/"" + { + ND_INS_LAHF, ND_CAT_FLAGOP, ND_SET_I86, 365, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0, + 0, + 0, + OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:550 Instruction:"LAR Gv,Mw" Encoding:"0x0F 0x02 /r:mem"/"RM" + { + ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 366, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:551 Instruction:"LAR Gv,Rz" Encoding:"0x0F 0x02 /r:reg"/"RM" + { + ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 366, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_R, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:552 Instruction:"LDDQU Vx,Mx" Encoding:"0xF2 0x0F 0xF0 /r:mem"/"RM" + { + ND_INS_LDDQU, ND_CAT_SSE, ND_SET_SSE3, 367, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:553 Instruction:"LDMXCSR Md" Encoding:"NP 0x0F 0xAE /2:mem"/"M" + { + ND_INS_LDMXCSR, ND_CAT_SSE, ND_SET_SSE, 368, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:554 Instruction:"LDS Gz,Mp" Encoding:"0xC5 /r:mem"/"RM" + { + ND_INS_LDS, ND_CAT_SEGOP, ND_SET_I86, 369, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_z, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_p, ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_DS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:555 Instruction:"LDTILECFG Moq" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0:mem"/"M" + { + ND_INS_LDTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 370, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E1, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_oq, ND_OPF_R, 0, 0), + }, + + // Pos:556 Instruction:"LEA Gv,M0" Encoding:"0x8D /r:mem"/"RM" + { + ND_INS_LEA, ND_CAT_MISC, ND_SET_I86, 371, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_0, ND_OPF_N, 0, 0), + }, + + // Pos:557 Instruction:"LEAVE" Encoding:"0xC9"/"" + { + ND_INS_LEAVE, ND_CAT_MISC, ND_SET_I186, 372, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rBP, ND_OPS_ssz, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rBP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rSP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:558 Instruction:"LES Gz,Mp" Encoding:"0xC4 /r:mem"/"RM" + { + ND_INS_LES, ND_CAT_SEGOP, ND_SET_I86, 373, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_z, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_p, ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_ES, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:559 Instruction:"LFENCE" Encoding:"NP 0x0F 0xAE /5:reg"/"" + { + ND_INS_LFENCE, ND_CAT_MISC, ND_SET_SSE2, 374, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + }, + + // Pos:560 Instruction:"LFS Gv,Mp" Encoding:"0x0F 0xB4 /r:mem"/"RM" + { + ND_INS_LFS, ND_CAT_SEGOP, ND_SET_I386, 375, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_p, ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_FS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:561 Instruction:"LGDT Ms" Encoding:"0x0F 0x01 /2:mem"/"M" + { + ND_INS_LGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 376, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_s, ND_OPF_R, 0, 0), + OP(ND_OPT_SYS_GDTR, ND_OPS_s, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:562 Instruction:"LGS Gv,Mp" Encoding:"0x0F 0xB5 /r:mem"/"RM" + { + ND_INS_LGS, ND_CAT_SEGOP, ND_SET_I386, 377, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_p, ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_GS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:563 Instruction:"LIDT Ms" Encoding:"0x0F 0x01 /3:mem"/"M" + { + ND_INS_LIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 378, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_s, ND_OPF_R, 0, 0), + OP(ND_OPT_SYS_IDTR, ND_OPS_s, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:564 Instruction:"LLDT Ew" Encoding:"0x0F 0x00 /2"/"M" + { + ND_INS_LLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 379, + ND_MOD_R0|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_SYS_LDTR, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:565 Instruction:"LLWPCB Ry" Encoding:"xop m:9 0x12 /0:reg"/"M" + { + ND_INS_LLWPCB, ND_CAT_LWP, ND_SET_LWP, 380, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:566 Instruction:"LMSW Ew" Encoding:"0x0F 0x01 /6"/"M" + { + ND_INS_LMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 381, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_CR_0, ND_OPS_yf, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:567 Instruction:"LOADALL" Encoding:"0x0F 0x05"/"" + { + ND_INS_LOADALL, ND_CAT_UNDOC, ND_SET_I486REAL, 382, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:568 Instruction:"LOADALLD" Encoding:"0x0F 0x07"/"" + { + ND_INS_LOADALLD, ND_CAT_UNDOC, ND_SET_I486REAL, 383, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:569 Instruction:"LODSB AL,Xb" Encoding:"0xAC"/"" + { + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 384, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:570 Instruction:"LODSB AL,Xb" Encoding:"rep 0xAC"/"" + { + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 384, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:571 Instruction:"LODSD EAX,Xv" Encoding:"ds32 0xAD"/"" + { + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 385, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:572 Instruction:"LODSD EAX,Xv" Encoding:"rep ds32 0xAD"/"" + { + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 385, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:573 Instruction:"LODSQ RAX,Xv" Encoding:"ds64 0xAD"/"" + { + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 386, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:574 Instruction:"LODSQ RAX,Xv" Encoding:"rep ds64 0xAD"/"" + { + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 386, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:575 Instruction:"LODSW AX,Xv" Encoding:"ds16 0xAD"/"" + { + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 387, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:576 Instruction:"LODSW AX,Xv" Encoding:"rep ds16 0xAD"/"" + { + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 387, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:577 Instruction:"LOOP Jb" Encoding:"0xE2 cb"/"D" + { + ND_INS_LOOP, ND_CAT_COND_BR, ND_SET_I86, 388, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:578 Instruction:"LOOPNZ Jb" Encoding:"0xE0 cb"/"D" + { + ND_INS_LOOPNZ, ND_CAT_COND_BR, ND_SET_I86, 389, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:579 Instruction:"LOOPZ Jb" Encoding:"0xE1 cb"/"D" + { + ND_INS_LOOPZ, ND_CAT_COND_BR, ND_SET_I86, 390, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:580 Instruction:"LSL Gv,Mw" Encoding:"0x0F 0x03 /r:mem"/"RM" + { + ND_INS_LSL, ND_CAT_SYSTEM, ND_SET_I286PROT, 391, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:581 Instruction:"LSL Gv,Rz" Encoding:"0x0F 0x03 /r:reg"/"RM" + { + ND_INS_LSL, ND_CAT_SYSTEM, ND_SET_I286PROT, 391, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_R, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:582 Instruction:"LSS Gv,Mp" Encoding:"0x0F 0xB2 /r:mem"/"RM" + { + ND_INS_LSS, ND_CAT_SEGOP, ND_SET_I386, 392, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_p, ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_SS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:583 Instruction:"LTR Ew" Encoding:"0x0F 0x00 /3"/"M" + { + ND_INS_LTR, ND_CAT_SYSTEM, ND_SET_I286PROT, 393, + ND_MOD_R0|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_SYS_TR, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:584 Instruction:"LWPINS By,Ed,Id" Encoding:"xop m:A 0x12 /0 id"/"VMI" + { + ND_INS_LWPINS, ND_CAT_LWP, ND_SET_LWP, 394, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, + 0, + 0, + 0, + 0, + OP(ND_OPT_B, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:585 Instruction:"LWPVAL By,Ed,Id" Encoding:"xop m:A 0x12 /1 id"/"VMI" + { + ND_INS_LWPVAL, ND_CAT_LWP, ND_SET_LWP, 395, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, + 0, + 0, + 0, + 0, + OP(ND_OPT_B, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:586 Instruction:"LZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBD /r"/"RM" + { + ND_INS_LZCNT, ND_CAT_LZCNT, ND_SET_LZCNT, 396, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LZCNT, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:587 Instruction:"MASKMOVDQU Vdq,Udq" Encoding:"0x66 0x0F 0xF7 /r:reg"/"RM" + { + ND_INS_MASKMOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 397, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_MEM_rDI, ND_OPS_dq, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:588 Instruction:"MASKMOVQ Pq,Nq" Encoding:"NP 0x0F 0xF7 /r:reg"/"RM" + { + ND_INS_MASKMOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 398, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_N, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_MEM_rDI, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:589 Instruction:"MAXPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5F /r"/"RM" + { + ND_INS_MAXPD, ND_CAT_SSE, ND_SET_SSE2, 399, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:590 Instruction:"MAXPS Vps,Wps" Encoding:"NP 0x0F 0x5F /r"/"RM" + { + ND_INS_MAXPS, ND_CAT_SSE, ND_SET_SSE, 400, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:591 Instruction:"MAXSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5F /r"/"RM" + { + ND_INS_MAXSD, ND_CAT_SSE, ND_SET_SSE2, 401, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:592 Instruction:"MAXSS Vss,Wss" Encoding:"0xF3 0x0F 0x5F /r"/"RM" + { + ND_INS_MAXSS, ND_CAT_SSE, ND_SET_SSE, 402, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:593 Instruction:"MCOMMIT" Encoding:"0xF3 0x0F 0x01 /0xFA"/"" + { + ND_INS_MCOMMIT, ND_CAT_MISC, ND_SET_MCOMMIT, 403, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MCOMMIT, + 0, + 0|REG_RFLAG_CF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:594 Instruction:"MFENCE" Encoding:"NP 0x0F 0xAE /6:reg"/"" + { + ND_INS_MFENCE, ND_CAT_MISC, ND_SET_SSE2, 404, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + }, + + // Pos:595 Instruction:"MINPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5D /r"/"RM" + { + ND_INS_MINPD, ND_CAT_SSE, ND_SET_SSE2, 405, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:596 Instruction:"MINPS Vps,Wps" Encoding:"NP 0x0F 0x5D /r"/"RM" + { + ND_INS_MINPS, ND_CAT_SSE, ND_SET_SSE, 406, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:597 Instruction:"MINSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5D /r"/"RM" + { + ND_INS_MINSD, ND_CAT_SSE, ND_SET_SSE2, 407, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:598 Instruction:"MINSS Vss,Wss" Encoding:"0xF3 0x0F 0x5D /r"/"RM" + { + ND_INS_MINSS, ND_CAT_SSE, ND_SET_SSE, 408, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:599 Instruction:"MONITOR" Encoding:"NP 0x0F 0x01 /0xC8"/"" + { + ND_INS_MONITOR, ND_CAT_MISC, ND_SET_SSE3, 409, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MONITOR, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:600 Instruction:"MONITORX" Encoding:"NP 0x0F 0x01 /0xFA"/"" + { + ND_INS_MONITORX, ND_CAT_SYSTEM, ND_SET_MWAITT, 410, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:601 Instruction:"MONTMUL" Encoding:"0xF3 0x0F 0xA6 /0xC0"/"" + { + ND_INS_MONTMUL, ND_CAT_PADLOCK, ND_SET_CYRIX, 411, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:602 Instruction:"MOV Ry,Cy" Encoding:"0x0F 0x20 /r"/"MR" + { + ND_INS_MOV_CR, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_LOCK_SPECIAL|ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_C, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:603 Instruction:"MOV Ry,Dy" Encoding:"0x0F 0x21 /r"/"MR" + { + ND_INS_MOV_DR, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_D, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:604 Instruction:"MOV Cy,Ry" Encoding:"0x0F 0x22 /r"/"RM" + { + ND_INS_MOV_CR, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_LOCK_SPECIAL|ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_C, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:605 Instruction:"MOV Dy,Ry" Encoding:"0x0F 0x23 /r"/"RM" + { + ND_INS_MOV_DR, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_D, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:606 Instruction:"MOV Ry,Ty" Encoding:"0x0F 0x24 /r"/"MR" + { + ND_INS_MOV_TR, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_T, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:607 Instruction:"MOV Ty,Ry" Encoding:"0x0F 0x26 /r"/"RM" + { + ND_INS_MOV_TR, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_T, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:608 Instruction:"MOV Eb,Gb" Encoding:"0x88 /r"/"MR" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_G, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:609 Instruction:"MOV Ev,Gv" Encoding:"0x89 /r"/"MR" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:610 Instruction:"MOV Gb,Eb" Encoding:"0x8A /r"/"RM" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:611 Instruction:"MOV Gv,Ev" Encoding:"0x8B /r"/"RM" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:612 Instruction:"MOV Mw,Sw" Encoding:"0x8C /r:mem"/"MR" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_S, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:613 Instruction:"MOV Rv,Sw" Encoding:"0x8C /r:reg"/"MR" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_S, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:614 Instruction:"MOV Sw,Mw" Encoding:"0x8E /r:mem"/"RM" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_S, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:615 Instruction:"MOV Sw,Rv" Encoding:"0x8E /r:reg"/"RM" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_S, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:616 Instruction:"MOV AL,Ob" Encoding:"0xA0"/"D" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_O, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:617 Instruction:"MOV rAX,Ov" Encoding:"0xA1"/"D" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_O, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:618 Instruction:"MOV Ob,AL" Encoding:"0xA2"/"D" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_O, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:619 Instruction:"MOV Ov,rAX" Encoding:"0xA3"/"D" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_O, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:620 Instruction:"MOV Zb,Ib" Encoding:"0xB0 ib"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:621 Instruction:"MOV Zb,Ib" Encoding:"0xB1 ib"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:622 Instruction:"MOV Zb,Ib" Encoding:"0xB2 ib"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:623 Instruction:"MOV Zb,Ib" Encoding:"0xB3 ib"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:624 Instruction:"MOV Zb,Ib" Encoding:"0xB4 ib"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:625 Instruction:"MOV Zb,Ib" Encoding:"0xB5 ib"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:626 Instruction:"MOV Zb,Ib" Encoding:"0xB6 ib"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:627 Instruction:"MOV Zb,Ib" Encoding:"0xB7 ib"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:628 Instruction:"MOV Zv,Iv" Encoding:"0xB8 iv"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:629 Instruction:"MOV Zv,Iv" Encoding:"0xB9 iv"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:630 Instruction:"MOV Zv,Iv" Encoding:"0xBA iv"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:631 Instruction:"MOV Zv,Iv" Encoding:"0xBB iv"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:632 Instruction:"MOV Zv,Iv" Encoding:"0xBC iv"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:633 Instruction:"MOV Zv,Iv" Encoding:"0xBD iv"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:634 Instruction:"MOV Zv,Iv" Encoding:"0xBE iv"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:635 Instruction:"MOV Zv,Iv" Encoding:"0xBF iv"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:636 Instruction:"MOV Eb,Ib" Encoding:"0xC6 /0 ib"/"MI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:637 Instruction:"MOV Ev,Iz" Encoding:"0xC7 /0 iz"/"MI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + }, + + // Pos:638 Instruction:"MOVAPD Vpd,Wpd" Encoding:"0x66 0x0F 0x28 /r"/"RM" + { + ND_INS_MOVAPD, ND_CAT_DATAXFER, ND_SET_SSE2, 413, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:639 Instruction:"MOVAPD Wpd,Vpd" Encoding:"0x66 0x0F 0x29 /r"/"MR" + { + ND_INS_MOVAPD, ND_CAT_DATAXFER, ND_SET_SSE2, 413, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:640 Instruction:"MOVAPS Vps,Wps" Encoding:"NP 0x0F 0x28 /r"/"RM" + { + ND_INS_MOVAPS, ND_CAT_DATAXFER, ND_SET_SSE, 414, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:641 Instruction:"MOVAPS Wps,Vps" Encoding:"NP 0x0F 0x29 /r"/"MR" + { + ND_INS_MOVAPS, ND_CAT_DATAXFER, ND_SET_SSE, 414, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:642 Instruction:"MOVBE Gv,Mv" Encoding:"0x0F 0x38 0xF0 /r:mem"/"RM" + { + ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 415, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVBE, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:643 Instruction:"MOVBE Gv,Mv" Encoding:"0x66 0x0F 0x38 0xF0 /r:mem"/"RM" + { + ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 415, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_MOVBE, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:644 Instruction:"MOVBE Mv,Gv" Encoding:"0x0F 0x38 0xF1 /r:mem"/"MR" + { + ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 415, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVBE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:645 Instruction:"MOVBE Mv,Gv" Encoding:"0x66 0x0F 0x38 0xF1 /r:mem"/"MR" + { + ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 415, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_MOVBE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:646 Instruction:"MOVD Pq,Ey" Encoding:"NP 0x0F 0x6E /r"/"RM" + { + ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_MMX, 416, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:647 Instruction:"MOVD Vdq,Ey" Encoding:"0x66 0x0F 0x6E /r"/"RM" + { + ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_SSE2, 416, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:648 Instruction:"MOVD Ey,Pd" Encoding:"NP 0x0F 0x7E /r"/"MR" + { + ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_MMX, 416, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_P, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:649 Instruction:"MOVD Ey,Vdq" Encoding:"0x66 0x0F 0x7E /r"/"MR" + { + ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_SSE2, 416, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:650 Instruction:"MOVDDUP Vdq,Wq" Encoding:"0xF2 0x0F 0x12 /r"/"RM" + { + ND_INS_MOVDDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 417, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:651 Instruction:"MOVDIR64B rMoq,Moq" Encoding:"0x66 0x0F 0x38 0xF8 /r:mem"/"M" + { + ND_INS_MOVDIR64B, ND_CAT_MOVDIR64B, ND_SET_MOVDIR64B, 418, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVDIR64B, + 0, + 0, + 0, + 0, + OP(ND_OPT_rM, ND_OPS_oq, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_oq, ND_OPF_R, 0, 0), + }, + + // Pos:652 Instruction:"MOVDIRI My,Gy" Encoding:"NP 0x0F 0x38 0xF9 /r:mem"/"MR" + { + ND_INS_MOVDIRI, ND_CAT_MOVDIRI, ND_SET_MOVDIRI, 419, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVDIRI, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_G, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:653 Instruction:"MOVDQ2Q Pq,Uq" Encoding:"0xF2 0x0F 0xD6 /r:reg"/"RM" + { + ND_INS_MOVDQ2Q, ND_CAT_DATAXFER, ND_SET_SSE2, 420, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:654 Instruction:"MOVDQA Vx,Wx" Encoding:"0x66 0x0F 0x6F /r"/"RM" + { + ND_INS_MOVDQA, ND_CAT_DATAXFER, ND_SET_SSE2, 421, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:655 Instruction:"MOVDQA Wx,Vx" Encoding:"0x66 0x0F 0x7F /r"/"MR" + { + ND_INS_MOVDQA, ND_CAT_DATAXFER, ND_SET_SSE2, 421, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:656 Instruction:"MOVDQU Vx,Wx" Encoding:"0xF3 0x0F 0x6F /r"/"RM" + { + ND_INS_MOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 422, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:657 Instruction:"MOVDQU Wx,Vx" Encoding:"0xF3 0x0F 0x7F /r"/"MR" + { + ND_INS_MOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 422, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:658 Instruction:"MOVHPD Vq,Mq" Encoding:"0x66 0x0F 0x16 /r:mem"/"RM" + { + ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 423, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:659 Instruction:"MOVHPD Mq,Vq" Encoding:"0x66 0x0F 0x17 /r:mem"/"MR" + { + ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 423, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:660 Instruction:"MOVHPS Vq,Mq" Encoding:"NP 0x0F 0x16 /r:mem"/"RM" + { + ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 424, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:661 Instruction:"MOVHPS Mq,Vq" Encoding:"NP 0x0F 0x17 /r:mem"/"MR" + { + ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 424, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:662 Instruction:"MOVLHPS Vq,Uq" Encoding:"NP 0x0F 0x16 /r:reg"/"RM" + { + ND_INS_MOVLHPS, ND_CAT_DATAXFER, ND_SET_SSE, 425, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:663 Instruction:"MOVLPD Vsd,Mq" Encoding:"0x66 0x0F 0x12 /r:mem"/"RM" + { + ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 426, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:664 Instruction:"MOVLPD Mq,Vpd" Encoding:"0x66 0x0F 0x13 /r:mem"/"MR" + { + ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 426, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:665 Instruction:"MOVLPS Vq,Wq" Encoding:"NP 0x0F 0x12 /r"/"RM" + { + ND_INS_MOVLPS, ND_CAT_DATAXFER, ND_SET_SSE, 427, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:666 Instruction:"MOVLPS Mq,Vps" Encoding:"NP 0x0F 0x13 /r:mem"/"MR" + { + ND_INS_MOVLPS, ND_CAT_DATAXFER, ND_SET_SSE, 427, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:667 Instruction:"MOVMSKPD Gd,Upd" Encoding:"0x66 0x0F 0x50 /r:reg"/"RM" + { + ND_INS_MOVMSKPD, ND_CAT_DATAXFER, ND_SET_SSE2, 428, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:668 Instruction:"MOVMSKPS Gd,Ups" Encoding:"NP 0x0F 0x50 /r:reg"/"RM" + { + ND_INS_MOVMSKPS, ND_CAT_DATAXFER, ND_SET_SSE, 429, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:669 Instruction:"MOVNTDQ Mx,Vx" Encoding:"0x66 0x0F 0xE7 /r:mem"/"MR" + { + ND_INS_MOVNTDQ, ND_CAT_DATAXFER, ND_SET_SSE2, 430, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:670 Instruction:"MOVNTDQA Vx,Mx" Encoding:"0x66 0x0F 0x38 0x2A /r:mem"/"RM" + { + ND_INS_MOVNTDQA, ND_CAT_SSE, ND_SET_SSE4, 431, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:671 Instruction:"MOVNTI My,Gy" Encoding:"NP 0x0F 0xC3 /r:mem"/"MR" + { + ND_INS_MOVNTI, ND_CAT_DATAXFER, ND_SET_SSE2, 432, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_G, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:672 Instruction:"MOVNTPD Mpd,Vpd" Encoding:"0x66 0x0F 0x2B /r:mem"/"MR" + { + ND_INS_MOVNTPD, ND_CAT_DATAXFER, ND_SET_SSE2, 433, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:673 Instruction:"MOVNTPS Mps,Vps" Encoding:"NP 0x0F 0x2B /r:mem"/"MR" + { + ND_INS_MOVNTPS, ND_CAT_DATAXFER, ND_SET_SSE, 434, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:674 Instruction:"MOVNTQ Mq,Pq" Encoding:"NP 0x0F 0xE7 /r:mem"/"MR" + { + ND_INS_MOVNTQ, ND_CAT_DATAXFER, ND_SET_MMX, 435, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_P, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:675 Instruction:"MOVNTSD Msd,Vsd" Encoding:"0xF2 0x0F 0x2B /r:mem"/"MR" + { + ND_INS_MOVNTSD, ND_CAT_DATAXFER, ND_SET_SSE4A, 436, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:676 Instruction:"MOVNTSS Mss,Vss" Encoding:"0xF3 0x0F 0x2B /r:mem"/"MR" + { + ND_INS_MOVNTSS, ND_CAT_DATAXFER, ND_SET_SSE4A, 437, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:677 Instruction:"MOVQ Pq,Ey" Encoding:"rexw NP 0x0F 0x6E /r"/"RM" + { + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 438, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:678 Instruction:"MOVQ Vdq,Ey" Encoding:"0x66 rexw 0x0F 0x6E /r"/"RM" + { + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 438, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:679 Instruction:"MOVQ Pq,Qq" Encoding:"NP 0x0F 0x6F /r"/"RM" + { + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 438, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:680 Instruction:"MOVQ Ey,Pq" Encoding:"rexw NP 0x0F 0x7E /r"/"MR" + { + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 438, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_P, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:681 Instruction:"MOVQ Ey,Vdq" Encoding:"0x66 rexw 0x0F 0x7E /r"/"MR" + { + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 438, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:682 Instruction:"MOVQ Vdq,Wq" Encoding:"0xF3 0x0F 0x7E /r"/"RM" + { + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 438, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:683 Instruction:"MOVQ Qq,Pq" Encoding:"NP 0x0F 0x7F /r"/"MR" + { + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 438, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_P, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:684 Instruction:"MOVQ Wq,Vq" Encoding:"0x66 0x0F 0xD6 /r"/"MR" + { + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 438, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:685 Instruction:"MOVQ2DQ Vdq,Nq" Encoding:"0xF3 0x0F 0xD6 /r:reg"/"RM" + { + ND_INS_MOVQ2DQ, ND_CAT_DATAXFER, ND_SET_SSE2, 439, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_N, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:686 Instruction:"MOVSB Yb,Xb" Encoding:"0xA4"/"" + { + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 440, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:687 Instruction:"MOVSB Yb,Xb" Encoding:"rep 0xA4"/"" + { + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 440, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:688 Instruction:"MOVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x10 /r"/"RM" + { + ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 441, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:689 Instruction:"MOVSD Wsd,Vsd" Encoding:"0xF2 0x0F 0x11 /r"/"MR" + { + ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 441, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:690 Instruction:"MOVSD Yv,Xv" Encoding:"ds32 0xA5"/"" + { + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 441, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:691 Instruction:"MOVSD Yv,Xv" Encoding:"rep ds32 0xA5"/"" + { + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 441, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:692 Instruction:"MOVSHDUP Vx,Wx" Encoding:"0xF3 0x0F 0x16 /r"/"RM" + { + ND_INS_MOVSHDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 442, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:693 Instruction:"MOVSLDUP Vx,Wx" Encoding:"0xF3 0x0F 0x12 /r"/"RM" + { + ND_INS_MOVSLDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 443, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:694 Instruction:"MOVSQ Yv,Xv" Encoding:"ds64 0xA5"/"" + { + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 444, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:695 Instruction:"MOVSQ Yv,Xv" Encoding:"rep ds64 0xA5"/"" + { + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 444, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:696 Instruction:"MOVSS Vss,Wss" Encoding:"0xF3 0x0F 0x10 /r"/"RM" + { + ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 445, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:697 Instruction:"MOVSS Wss,Vss" Encoding:"0xF3 0x0F 0x11 /r"/"MR" + { + ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 445, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:698 Instruction:"MOVSW Yv,Xv" Encoding:"ds16 0xA5"/"" + { + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 446, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:699 Instruction:"MOVSW Yv,Xv" Encoding:"rep ds16 0xA5"/"" + { + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 446, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:700 Instruction:"MOVSX Gv,Eb" Encoding:"0x0F 0xBE /r"/"RM" + { + ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 447, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:701 Instruction:"MOVSX Gv,Ew" Encoding:"0x0F 0xBF /r"/"RM" + { + ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 447, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:702 Instruction:"MOVSXD Gv,Ez" Encoding:"o64 0x63 /r"/"RM" + { + ND_INS_MOVSXD, ND_CAT_DATAXFER, ND_SET_LONGMODE, 448, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_z, ND_OPF_R, 0, 0), + }, + + // Pos:703 Instruction:"MOVUPD Vpd,Wpd" Encoding:"0x66 0x0F 0x10 /r"/"RM" + { + ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 449, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:704 Instruction:"MOVUPD Wpd,Vpd" Encoding:"0x66 0x0F 0x11 /r"/"MR" + { + ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 449, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:705 Instruction:"MOVUPS Vps,Wps" Encoding:"NP 0x0F 0x10 /r"/"RM" + { + ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 450, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:706 Instruction:"MOVUPS Wps,Vps" Encoding:"NP 0x0F 0x11 /r"/"MR" + { + ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 450, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:707 Instruction:"MOVZX Gv,Eb" Encoding:"0x0F 0xB6 /r"/"RM" + { + ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 451, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:708 Instruction:"MOVZX Gv,Ew" Encoding:"0x0F 0xB7 /r"/"RM" + { + ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 451, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:709 Instruction:"MPSADBW Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x42 /r ib"/"RMI" + { + ND_INS_MPSADBW, ND_CAT_SSE, ND_SET_SSE4, 452, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:710 Instruction:"MUL Eb" Encoding:"0xF6 /4"/"M" + { + ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 453, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:711 Instruction:"MUL Ev" Encoding:"0xF7 /4"/"M" + { + ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 453, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:712 Instruction:"MULPD Vpd,Wpd" Encoding:"0x66 0x0F 0x59 /r"/"RM" + { + ND_INS_MULPD, ND_CAT_SSE, ND_SET_SSE2, 454, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:713 Instruction:"MULPS Vps,Wps" Encoding:"NP 0x0F 0x59 /r"/"RM" + { + ND_INS_MULPS, ND_CAT_SSE, ND_SET_SSE, 455, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:714 Instruction:"MULSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x59 /r"/"RM" + { + ND_INS_MULSD, ND_CAT_SSE, ND_SET_SSE2, 456, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:715 Instruction:"MULSS Vss,Wss" Encoding:"0xF3 0x0F 0x59 /r"/"RM" + { + ND_INS_MULSS, ND_CAT_SSE, ND_SET_SSE, 457, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:716 Instruction:"MULX Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF6 /r"/"RVM" + { + ND_INS_MULX, ND_CAT_BMI2, ND_SET_BMI2, 458, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_B, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:717 Instruction:"MWAIT" Encoding:"NP 0x0F 0x01 /0xC9"/"" + { + ND_INS_MWAIT, ND_CAT_MISC, ND_SET_SSE3, 459, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MONITOR, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:718 Instruction:"MWAITX" Encoding:"NP 0x0F 0x01 /0xFB"/"" + { + ND_INS_MWAITX, ND_CAT_SYSTEM, ND_SET_MWAITT, 460, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rBX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:719 Instruction:"NEG Eb" Encoding:"0xF6 /3"/"M" + { + ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 461, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:720 Instruction:"NEG Ev" Encoding:"0xF7 /3"/"M" + { + ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 461, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:721 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /0:reg"/"MR" + { + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:722 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /1:reg"/"MR" + { + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:723 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /2:reg"/"MR" + { + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:724 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /3:reg"/"MR" + { + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:725 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /4:reg"/"MR" + { + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:726 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /5:reg"/"MR" + { + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:727 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /6:reg"/"MR" + { + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:728 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /7:reg"/"MR" + { + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:729 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /0:reg"/"M" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:730 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /1:reg"/"M" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:731 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /2:reg"/"M" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:732 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /3:reg"/"M" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:733 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /4"/"M" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:734 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /5"/"M" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:735 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /6"/"M" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:736 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /7"/"M" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:737 Instruction:"NOP Ev" Encoding:"0x0F 0x19 /r"/"M" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:738 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1A /r:reg"/"RM" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:739 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1B /r:reg"/"RM" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:740 Instruction:"NOP Gv,Ev" Encoding:"0xF3 0x0F 0x1B /r:reg"/"RM" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:741 Instruction:"NOP Ev,Gv" Encoding:"0x66 0x0F 0x1C /0:mem"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:742 Instruction:"NOP Ev,Gv" Encoding:"0xF3 0x0F 0x1C /0:mem"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:743 Instruction:"NOP Ev,Gv" Encoding:"0xF2 0x0F 0x1C /0:mem"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:744 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /0:reg"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:745 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /1"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:746 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /2"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:747 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /3"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:748 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /4"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:749 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /5"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:750 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /6"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:751 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /7"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:752 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1D /r"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:753 Instruction:"NOP Mv,Gv" Encoding:"0x0F 0x1E /r:mem"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:754 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /0:reg"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:755 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /1:reg"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:756 Instruction:"NOP Rv,Gv" Encoding:"rexw 0x0F 0x1E /1:reg"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:757 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /2:reg"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:758 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /3:reg"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:759 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /4:reg"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:760 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /5:reg"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:761 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /6:reg"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:762 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /0xF8"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:763 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /0xF9"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:764 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /0xFA"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:765 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /0xFB"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:766 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /0xFC"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:767 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /0xFD"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:768 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /0xFE"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:769 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /0xFF"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:770 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1F /r"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:771 Instruction:"NOP" Encoding:"0x90"/"" + { + ND_INS_NOP, ND_CAT_NOP, ND_SET_I86, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:772 Instruction:"NOT Eb" Encoding:"0xF6 /2"/"M" + { + ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 463, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + }, + + // Pos:773 Instruction:"NOT Ev" Encoding:"0xF7 /2"/"M" + { + ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 463, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + }, + + // Pos:774 Instruction:"OR Eb,Gb" Encoding:"0x08 /r"/"MR" + { + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:775 Instruction:"OR Ev,Gv" Encoding:"0x09 /r"/"MR" + { + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:776 Instruction:"OR Gb,Eb" Encoding:"0x0A /r"/"RM" + { + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_G, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:777 Instruction:"OR Gv,Ev" Encoding:"0x0B /r"/"RM" + { + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:778 Instruction:"OR AL,Ib" Encoding:"0x0C ib"/"I" + { + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:779 Instruction:"OR rAX,Iz" Encoding:"0x0D iz"/"I" + { + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:780 Instruction:"OR Eb,Ib" Encoding:"0x80 /1 ib"/"MI" + { + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:781 Instruction:"OR Ev,Iz" Encoding:"0x81 /1 iz"/"MI" + { + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:782 Instruction:"OR Ev,Iz" Encoding:"0x82 /1 iz"/"MI" + { + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:783 Instruction:"OR Ev,Ib" Encoding:"0x83 /1 ib"/"MI" + { + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:784 Instruction:"ORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x56 /r"/"RM" + { + ND_INS_ORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 465, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:785 Instruction:"ORPS Vps,Wps" Encoding:"NP 0x0F 0x56 /r"/"RM" + { + ND_INS_ORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 466, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:786 Instruction:"OUT Ib,AL" Encoding:"0xE6 ib"/"I" + { + ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 467, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:787 Instruction:"OUT Ib,eAX" Encoding:"0xE7 ib"/"I" + { + ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 467, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:788 Instruction:"OUT DX,AL" Encoding:"0xEE"/"" + { + ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 467, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:789 Instruction:"OUT DX,eAX" Encoding:"0xEF"/"" + { + ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 467, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:790 Instruction:"OUTSB DX,Xb" Encoding:"0x6E"/"" + { + ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 468, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:791 Instruction:"OUTSB DX,Xb" Encoding:"rep 0x6E"/"" + { + ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 468, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:792 Instruction:"OUTSD DX,Xz" Encoding:"0x6F"/"" + { + ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 469, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_X, ND_OPS_z, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:793 Instruction:"OUTSD DX,Xz" Encoding:"rep 0x6F"/"" + { + ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 469, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_X, ND_OPS_z, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:794 Instruction:"OUTSW DX,Xz" Encoding:"ds16 0x6F"/"" + { + ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 470, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_X, ND_OPS_z, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:795 Instruction:"OUTSW DX,Xz" Encoding:"rep ds16 0x6F"/"" + { + ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 470, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_X, ND_OPS_z, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:796 Instruction:"PABSB Pq,Qq" Encoding:"NP 0x0F 0x38 0x1C /r"/"RM" + { + ND_INS_PABSB, ND_CAT_MMX, ND_SET_SSSE3, 471, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:797 Instruction:"PABSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1C /r"/"RM" + { + ND_INS_PABSB, ND_CAT_SSE, ND_SET_SSSE3, 471, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:798 Instruction:"PABSD Pq,Qq" Encoding:"NP 0x0F 0x38 0x1E /r"/"RM" + { + ND_INS_PABSD, ND_CAT_MMX, ND_SET_SSSE3, 472, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:799 Instruction:"PABSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1E /r"/"RM" + { + ND_INS_PABSD, ND_CAT_SSE, ND_SET_SSSE3, 472, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:800 Instruction:"PABSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x1D /r"/"RM" + { + ND_INS_PABSW, ND_CAT_MMX, ND_SET_SSSE3, 473, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:801 Instruction:"PABSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1D /r"/"RM" + { + ND_INS_PABSW, ND_CAT_SSE, ND_SET_SSSE3, 473, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:802 Instruction:"PACKSSDW Pq,Qq" Encoding:"NP 0x0F 0x6B /r"/"RM" + { + ND_INS_PACKSSDW, ND_CAT_MMX, ND_SET_MMX, 474, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:803 Instruction:"PACKSSDW Vx,Wx" Encoding:"0x66 0x0F 0x6B /r"/"RM" + { + ND_INS_PACKSSDW, ND_CAT_SSE, ND_SET_SSE2, 474, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:804 Instruction:"PACKSSWB Pq,Qq" Encoding:"NP 0x0F 0x63 /r"/"RM" + { + ND_INS_PACKSSWB, ND_CAT_MMX, ND_SET_MMX, 475, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:805 Instruction:"PACKSSWB Vx,Wx" Encoding:"0x66 0x0F 0x63 /r"/"RM" + { + ND_INS_PACKSSWB, ND_CAT_SSE, ND_SET_SSE2, 475, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:806 Instruction:"PACKUSDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x2B /r"/"RM" + { + ND_INS_PACKUSDW, ND_CAT_SSE, ND_SET_SSE4, 476, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:807 Instruction:"PACKUSWB Pq,Qq" Encoding:"NP 0x0F 0x67 /r"/"RM" + { + ND_INS_PACKUSWB, ND_CAT_MMX, ND_SET_MMX, 477, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:808 Instruction:"PACKUSWB Vx,Wx" Encoding:"0x66 0x0F 0x67 /r"/"RM" + { + ND_INS_PACKUSWB, ND_CAT_SSE, ND_SET_SSE2, 477, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:809 Instruction:"PADDB Pq,Qq" Encoding:"NP 0x0F 0xFC /r"/"RM" + { + ND_INS_PADDB, ND_CAT_MMX, ND_SET_MMX, 478, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:810 Instruction:"PADDB Vx,Wx" Encoding:"0x66 0x0F 0xFC /r"/"RM" + { + ND_INS_PADDB, ND_CAT_SSE, ND_SET_SSE2, 478, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:811 Instruction:"PADDD Pq,Qq" Encoding:"NP 0x0F 0xFE /r"/"RM" + { + ND_INS_PADDD, ND_CAT_MMX, ND_SET_MMX, 479, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:812 Instruction:"PADDD Vx,Wx" Encoding:"0x66 0x0F 0xFE /r"/"RM" + { + ND_INS_PADDD, ND_CAT_SSE, ND_SET_SSE2, 479, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:813 Instruction:"PADDQ Pq,Qq" Encoding:"NP 0x0F 0xD4 /r"/"RM" + { + ND_INS_PADDQ, ND_CAT_MMX, ND_SET_SSE2, 480, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:814 Instruction:"PADDQ Vx,Wx" Encoding:"0x66 0x0F 0xD4 /r"/"RM" + { + ND_INS_PADDQ, ND_CAT_SSE, ND_SET_SSE2, 480, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:815 Instruction:"PADDSB Pq,Qq" Encoding:"NP 0x0F 0xEC /r"/"RM" + { + ND_INS_PADDSB, ND_CAT_MMX, ND_SET_MMX, 481, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:816 Instruction:"PADDSB Vx,Wx" Encoding:"0x66 0x0F 0xEC /r"/"RM" + { + ND_INS_PADDSB, ND_CAT_SSE, ND_SET_SSE2, 481, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:817 Instruction:"PADDSW Pq,Qq" Encoding:"NP 0x0F 0xED /r"/"RM" + { + ND_INS_PADDSW, ND_CAT_MMX, ND_SET_MMX, 482, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:818 Instruction:"PADDSW Vx,Wx" Encoding:"0x66 0x0F 0xED /r"/"RM" + { + ND_INS_PADDSW, ND_CAT_SSE, ND_SET_SSE2, 482, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:819 Instruction:"PADDUSB Pq,Qq" Encoding:"NP 0x0F 0xDC /r"/"RM" + { + ND_INS_PADDUSB, ND_CAT_MMX, ND_SET_MMX, 483, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:820 Instruction:"PADDUSB Vx,Wx" Encoding:"0x66 0x0F 0xDC /r"/"RM" + { + ND_INS_PADDUSB, ND_CAT_SSE, ND_SET_SSE2, 483, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:821 Instruction:"PADDUSW Pq,Qq" Encoding:"NP 0x0F 0xDD /r"/"RM" + { + ND_INS_PADDUSW, ND_CAT_MMX, ND_SET_MMX, 484, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:822 Instruction:"PADDUSW Vx,Wx" Encoding:"0x66 0x0F 0xDD /r"/"RM" + { + ND_INS_PADDUSW, ND_CAT_SSE, ND_SET_SSE2, 484, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:823 Instruction:"PADDW Pq,Qq" Encoding:"NP 0x0F 0xFD /r"/"RM" + { + ND_INS_PADDW, ND_CAT_MMX, ND_SET_MMX, 485, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:824 Instruction:"PADDW Vx,Wx" Encoding:"0x66 0x0F 0xFD /r"/"RM" + { + ND_INS_PADDW, ND_CAT_SSE, ND_SET_SSE2, 485, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:825 Instruction:"PALIGNR Pq,Qq,Ib" Encoding:"NP 0x0F 0x3A 0x0F /r ib"/"RMI" + { + ND_INS_PALIGNR, ND_CAT_MMX, ND_SET_SSSE3, 486, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:826 Instruction:"PALIGNR Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0F /r ib"/"RMI" + { + ND_INS_PALIGNR, ND_CAT_SSE, ND_SET_SSSE3, 486, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:827 Instruction:"PAND Pq,Qq" Encoding:"NP 0x0F 0xDB /r"/"RM" + { + ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_MMX, 487, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:828 Instruction:"PAND Vx,Wx" Encoding:"0x66 0x0F 0xDB /r"/"RM" + { + ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_SSE2, 487, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:829 Instruction:"PANDN Pq,Qq" Encoding:"NP 0x0F 0xDF /r"/"RM" + { + ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_MMX, 488, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:830 Instruction:"PANDN Vx,Wx" Encoding:"0x66 0x0F 0xDF /r"/"RM" + { + ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_SSE2, 488, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:831 Instruction:"PAUSE" Encoding:"a0xF3 0x90"/"" + { + ND_INS_PAUSE, ND_CAT_MISC, ND_SET_PAUSE, 489, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:832 Instruction:"PAVGB Pq,Qq" Encoding:"NP 0x0F 0xE0 /r"/"RM" + { + ND_INS_PAVGB, ND_CAT_MMX, ND_SET_MMX, 490, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:833 Instruction:"PAVGB Vx,Wx" Encoding:"0x66 0x0F 0xE0 /r"/"RM" + { + ND_INS_PAVGB, ND_CAT_SSE, ND_SET_SSE2, 490, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:834 Instruction:"PAVGUSB Pq,Qq" Encoding:"0x0F 0x0F /r 0xBF"/"RM" + { + ND_INS_PAVGUSB, ND_CAT_3DNOW, ND_SET_3DNOW, 491, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:835 Instruction:"PAVGW Pq,Qq" Encoding:"NP 0x0F 0xE3 /r"/"RM" + { + ND_INS_PAVGW, ND_CAT_MMX, ND_SET_MMX, 492, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:836 Instruction:"PAVGW Vx,Wx" Encoding:"0x66 0x0F 0xE3 /r"/"RM" + { + ND_INS_PAVGW, ND_CAT_SSE, ND_SET_SSE2, 492, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:837 Instruction:"PBLENDVB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x10 /r"/"RM" + { + ND_INS_PBLENDVB, ND_CAT_SSE, ND_SET_SSE4, 493, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:838 Instruction:"PBLENDW Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0E /r ib"/"RMI" + { + ND_INS_PBLENDW, ND_CAT_SSE, ND_SET_SSE4, 494, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:839 Instruction:"PCLMULQDQ Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x44 /r ib"/"RMI" + { + ND_INS_PCLMULQDQ, ND_CAT_PCLMULQDQ, ND_SET_PCLMULQDQ, 495, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_PCLMULQDQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:840 Instruction:"PCMPEQB Pq,Qq" Encoding:"NP 0x0F 0x74 /r"/"RM" + { + ND_INS_PCMPEQB, ND_CAT_MMX, ND_SET_MMX, 496, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:841 Instruction:"PCMPEQB Vx,Wx" Encoding:"0x66 0x0F 0x74 /r"/"RM" + { + ND_INS_PCMPEQB, ND_CAT_SSE, ND_SET_SSE2, 496, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:842 Instruction:"PCMPEQD Pq,Qq" Encoding:"NP 0x0F 0x76 /r"/"RM" + { + ND_INS_PCMPEQD, ND_CAT_MMX, ND_SET_MMX, 497, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:843 Instruction:"PCMPEQD Vx,Wx" Encoding:"0x66 0x0F 0x76 /r"/"RM" + { + ND_INS_PCMPEQD, ND_CAT_SSE, ND_SET_SSE2, 497, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:844 Instruction:"PCMPEQQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x29 /r"/"RM" + { + ND_INS_PCMPEQQ, ND_CAT_SSE, ND_SET_SSE4, 498, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:845 Instruction:"PCMPEQW Pq,Qq" Encoding:"NP 0x0F 0x75 /r"/"RM" + { + ND_INS_PCMPEQW, ND_CAT_MMX, ND_SET_MMX, 499, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:846 Instruction:"PCMPEQW Vx,Wx" Encoding:"0x66 0x0F 0x75 /r"/"RM" + { + ND_INS_PCMPEQW, ND_CAT_SSE, ND_SET_SSE2, 499, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:847 Instruction:"PCMPESTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x61 /r ib"/"RMI" + { + ND_INS_PCMPESTRI, ND_CAT_SSE, ND_SET_SSE42, 500, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:848 Instruction:"PCMPESTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x60 /r ib"/"RMI" + { + ND_INS_PCMPESTRM, ND_CAT_SSE, ND_SET_SSE42, 501, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:849 Instruction:"PCMPGTB Pq,Qq" Encoding:"NP 0x0F 0x64 /r"/"RM" + { + ND_INS_PCMPGTB, ND_CAT_MMX, ND_SET_MMX, 502, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:850 Instruction:"PCMPGTB Vx,Wx" Encoding:"0x66 0x0F 0x64 /r"/"RM" + { + ND_INS_PCMPGTB, ND_CAT_SSE, ND_SET_SSE2, 502, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:851 Instruction:"PCMPGTD Pq,Qq" Encoding:"NP 0x0F 0x66 /r"/"RM" + { + ND_INS_PCMPGTD, ND_CAT_MMX, ND_SET_MMX, 503, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:852 Instruction:"PCMPGTD Vx,Wx" Encoding:"0x66 0x0F 0x66 /r"/"RM" + { + ND_INS_PCMPGTD, ND_CAT_SSE, ND_SET_SSE2, 503, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:853 Instruction:"PCMPGTQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x37 /r"/"RM" + { + ND_INS_PCMPGTQ, ND_CAT_SSE, ND_SET_SSE42, 504, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:854 Instruction:"PCMPGTW Pq,Qq" Encoding:"NP 0x0F 0x65 /r"/"RM" + { + ND_INS_PCMPGTW, ND_CAT_MMX, ND_SET_MMX, 505, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:855 Instruction:"PCMPGTW Vx,Wx" Encoding:"0x66 0x0F 0x65 /r"/"RM" + { + ND_INS_PCMPGTW, ND_CAT_SSE, ND_SET_SSE2, 505, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:856 Instruction:"PCMPISTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x63 /r ib"/"RMI" + { + ND_INS_PCMPISTRI, ND_CAT_SSE, ND_SET_SSE42, 506, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:857 Instruction:"PCMPISTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x62 /r ib"/"RMI" + { + ND_INS_PCMPISTRM, ND_CAT_SSE, ND_SET_SSE42, 507, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:858 Instruction:"PCOMMIT" Encoding:"0x66 0x0F 0xAE /7:reg"/"" + { + ND_INS_PCOMMIT, ND_CAT_MISC, ND_SET_PCOMMIT, 508, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PCOMMIT, + 0, + 0, + 0, + 0, + }, + + // Pos:859 Instruction:"PCONFIG" Encoding:"NP 0x0F 0x01 /0xC5"/"" + { + ND_INS_PCONFIG, ND_CAT_PCONFIG, ND_SET_PCONFIG, 509, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PCONFIG, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rBX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:860 Instruction:"PDEP Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF5 /r"/"RVM" + { + ND_INS_PDEP, ND_CAT_BMI2, ND_SET_BMI2, 510, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_B, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:861 Instruction:"PEXT Gy,By,Ey" Encoding:"vex m:2 p:2 l:0 w:x 0xF5 /r"/"RVM" + { + ND_INS_PEXT, ND_CAT_BMI2, ND_SET_BMI2, 511, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_B, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:862 Instruction:"PEXTRB Mb,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:mem ib"/"MRI" + { + ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 512, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:863 Instruction:"PEXTRB Rd,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:reg ib"/"MRI" + { + ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 512, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:864 Instruction:"PEXTRD Ey,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r ib"/"MRI" + { + ND_INS_PEXTRD, ND_CAT_SSE, ND_SET_SSE4, 513, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:865 Instruction:"PEXTRQ Ey,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r ib"/"MRI" + { + ND_INS_PEXTRQ, ND_CAT_SSE, ND_SET_SSE4, 514, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:866 Instruction:"PEXTRW Gy,Nq,Ib" Encoding:"NP 0x0F 0xC5 /r:reg ib"/"RMI" + { + ND_INS_PEXTRW, ND_CAT_MMX, ND_SET_MMX, 515, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_N, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:867 Instruction:"PEXTRW Gy,Udq,Ib" Encoding:"0x66 0x0F 0xC5 /r:reg ib"/"RMI" + { + ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE2, 515, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:868 Instruction:"PEXTRW Mw,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:mem ib"/"MRI" + { + ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 515, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:869 Instruction:"PEXTRW Rd,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:reg ib"/"MRI" + { + ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 515, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:870 Instruction:"PF2ID Pq,Qq" Encoding:"0x0F 0x0F /r 0x1D"/"RM" + { + ND_INS_PF2ID, ND_CAT_3DNOW, ND_SET_3DNOW, 516, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:871 Instruction:"PF2IW Pq,Qq" Encoding:"0x0F 0x0F /r 0x1C"/"RM" + { + ND_INS_PF2IW, ND_CAT_3DNOW, ND_SET_3DNOW, 517, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:872 Instruction:"PFACC Pq,Qq" Encoding:"0x0F 0x0F /r 0xAE"/"RM" + { + ND_INS_PFACC, ND_CAT_3DNOW, ND_SET_3DNOW, 518, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:873 Instruction:"PFADD Pq,Qq" Encoding:"0x0F 0x0F /r 0x9E"/"RM" + { + ND_INS_PFADD, ND_CAT_3DNOW, ND_SET_3DNOW, 519, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:874 Instruction:"PFCMPEQ Pq,Qq" Encoding:"0x0F 0x0F /r 0xB0"/"RM" + { + ND_INS_PFCMPEQ, ND_CAT_3DNOW, ND_SET_3DNOW, 520, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:875 Instruction:"PFCMPGE Pq,Qq" Encoding:"0x0F 0x0F /r 0x90"/"RM" + { + ND_INS_PFCMPGE, ND_CAT_3DNOW, ND_SET_3DNOW, 521, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:876 Instruction:"PFCMPGT Pq,Qq" Encoding:"0x0F 0x0F /r 0xA0"/"RM" + { + ND_INS_PFCMPGT, ND_CAT_3DNOW, ND_SET_3DNOW, 522, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:877 Instruction:"PFMAX Pq,Qq" Encoding:"0x0F 0x0F /r 0xA4"/"RM" + { + ND_INS_PFMAX, ND_CAT_3DNOW, ND_SET_3DNOW, 523, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:878 Instruction:"PFMIN Pq,Qq" Encoding:"0x0F 0x0F /r 0x94"/"RM" + { + ND_INS_PFMIN, ND_CAT_3DNOW, ND_SET_3DNOW, 524, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:879 Instruction:"PFMIN Pq,Qq" Encoding:"0x0F 0x0F /r 0x96"/"RM" + { + ND_INS_PFMIN, ND_CAT_3DNOW, ND_SET_3DNOW, 524, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:880 Instruction:"PFMUL Pq,Qq" Encoding:"0x0F 0x0F /r 0xB4"/"RM" + { + ND_INS_PFMUL, ND_CAT_3DNOW, ND_SET_3DNOW, 525, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:881 Instruction:"PFNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8A"/"RM" + { + ND_INS_PFNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 526, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:882 Instruction:"PFPNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8E"/"RM" + { + ND_INS_PFPNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 527, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:883 Instruction:"PFRCPIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA6"/"RM" + { + ND_INS_PFRCPIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 528, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:884 Instruction:"PFRCPIT2 Pq,Qq" Encoding:"0x0F 0x0F /r 0xB6"/"RM" + { + ND_INS_PFRCPIT2, ND_CAT_3DNOW, ND_SET_3DNOW, 529, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:885 Instruction:"PFRCPV Pq,Qq" Encoding:"0x0F 0x0F /r 0x86"/"RM" + { + ND_INS_PFRCPV, ND_CAT_3DNOW, ND_SET_3DNOW, 530, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:886 Instruction:"PFRSQIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA7"/"RM" + { + ND_INS_PFRSQIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 531, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:887 Instruction:"PFRSQRT Pq,Qq" Encoding:"0x0F 0x0F /r 0x97"/"RM" + { + ND_INS_PFRSQRT, ND_CAT_3DNOW, ND_SET_3DNOW, 532, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:888 Instruction:"PFRSQRTV Pq,Qq" Encoding:"0x0F 0x0F /r 0x87"/"RM" + { + ND_INS_PFRSQRTV, ND_CAT_3DNOW, ND_SET_3DNOW, 533, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:889 Instruction:"PFSUB Pq,Qq" Encoding:"0x0F 0x0F /r 0x9A"/"RM" + { + ND_INS_PFSUB, ND_CAT_3DNOW, ND_SET_3DNOW, 534, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:890 Instruction:"PFSUBR Pq,Qq" Encoding:"0x0F 0x0F /r 0xAA"/"RM" + { + ND_INS_PFSUBR, ND_CAT_3DNOW, ND_SET_3DNOW, 535, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:891 Instruction:"PHADDD Pq,Qq" Encoding:"NP 0x0F 0x38 0x02 /r"/"RM" + { + ND_INS_PHADDD, ND_CAT_MMX, ND_SET_SSSE3, 536, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:892 Instruction:"PHADDD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x02 /r"/"RM" + { + ND_INS_PHADDD, ND_CAT_SSE, ND_SET_SSSE3, 536, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:893 Instruction:"PHADDSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x03 /r"/"RM" + { + ND_INS_PHADDSW, ND_CAT_MMX, ND_SET_SSSE3, 537, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:894 Instruction:"PHADDSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x03 /r"/"RM" + { + ND_INS_PHADDSW, ND_CAT_SSE, ND_SET_SSSE3, 537, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:895 Instruction:"PHADDW Pq,Qq" Encoding:"NP 0x0F 0x38 0x01 /r"/"RM" + { + ND_INS_PHADDW, ND_CAT_MMX, ND_SET_SSSE3, 538, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:896 Instruction:"PHADDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x01 /r"/"RM" + { + ND_INS_PHADDW, ND_CAT_SSE, ND_SET_SSSE3, 538, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:897 Instruction:"PHMINPOSUW Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x41 /r"/"RM" + { + ND_INS_PHMINPOSUW, ND_CAT_SSE, ND_SET_SSE4, 539, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:898 Instruction:"PHSUBD Pq,Qq" Encoding:"NP 0x0F 0x38 0x06 /r"/"RM" + { + ND_INS_PHSUBD, ND_CAT_MMX, ND_SET_SSSE3, 540, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:899 Instruction:"PHSUBD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x06 /r"/"RM" + { + ND_INS_PHSUBD, ND_CAT_SSE, ND_SET_SSSE3, 540, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:900 Instruction:"PHSUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x07 /r"/"RM" + { + ND_INS_PHSUBSW, ND_CAT_MMX, ND_SET_SSSE3, 541, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:901 Instruction:"PHSUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x07 /r"/"RM" + { + ND_INS_PHSUBSW, ND_CAT_SSE, ND_SET_SSSE3, 541, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:902 Instruction:"PHSUBW Pq,Qq" Encoding:"NP 0x0F 0x38 0x05 /r"/"RM" + { + ND_INS_PHSUBW, ND_CAT_MMX, ND_SET_SSSE3, 542, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:903 Instruction:"PHSUBW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x05 /r"/"RM" + { + ND_INS_PHSUBW, ND_CAT_SSE, ND_SET_SSSE3, 542, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:904 Instruction:"PI2FD Pq,Qq" Encoding:"0x0F 0x0F /r 0x0D"/"RM" + { + ND_INS_PI2FD, ND_CAT_3DNOW, ND_SET_3DNOW, 543, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:905 Instruction:"PI2FW Pq,Qq" Encoding:"0x0F 0x0F /r 0x0C"/"RM" + { + ND_INS_PI2FW, ND_CAT_3DNOW, ND_SET_3DNOW, 544, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:906 Instruction:"PINSRB Vdq,Mb,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:mem ib"/"RMI" + { + ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 545, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:907 Instruction:"PINSRB Vdq,Ry,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:reg ib"/"RMI" + { + ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 545, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:908 Instruction:"PINSRD Vdq,Ed,Ib" Encoding:"0x66 0x0F 0x3A 0x22 /r ib"/"RMI" + { + ND_INS_PINSRD, ND_CAT_SSE, ND_SET_SSE4, 546, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:909 Instruction:"PINSRQ Vdq,Eq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x22 /r ib"/"RMI" + { + ND_INS_PINSRQ, ND_CAT_SSE, ND_SET_SSE4, 547, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:910 Instruction:"PINSRW Pq,Rd,Ib" Encoding:"NP 0x0F 0xC4 /r:reg ib"/"RMI" + { + ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 548, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_R, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:911 Instruction:"PINSRW Pq,Mw,Ib" Encoding:"NP 0x0F 0xC4 /r:mem ib"/"RMI" + { + ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 548, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:912 Instruction:"PINSRW Vdq,Rd,Ib" Encoding:"0x66 0x0F 0xC4 /r:reg ib"/"RMI" + { + ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 548, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_R, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:913 Instruction:"PINSRW Vdq,Mw,Ib" Encoding:"0x66 0x0F 0xC4 /r:mem ib"/"RMI" + { + ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 548, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:914 Instruction:"PMADDUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x04 /r"/"RM" + { + ND_INS_PMADDUBSW, ND_CAT_MMX, ND_SET_SSSE3, 549, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:915 Instruction:"PMADDUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x04 /r"/"RM" + { + ND_INS_PMADDUBSW, ND_CAT_SSE, ND_SET_SSSE3, 549, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:916 Instruction:"PMADDWD Pq,Qq" Encoding:"NP 0x0F 0xF5 /r"/"RM" + { + ND_INS_PMADDWD, ND_CAT_MMX, ND_SET_MMX, 550, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:917 Instruction:"PMADDWD Vx,Wx" Encoding:"0x66 0x0F 0xF5 /r"/"RM" + { + ND_INS_PMADDWD, ND_CAT_SSE, ND_SET_SSE2, 550, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:918 Instruction:"PMAXSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3C /r"/"RM" + { + ND_INS_PMAXSB, ND_CAT_SSE, ND_SET_SSE4, 551, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:919 Instruction:"PMAXSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3D /r"/"RM" + { + ND_INS_PMAXSD, ND_CAT_SSE, ND_SET_SSE4, 552, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:920 Instruction:"PMAXSW Pq,Qq" Encoding:"NP 0x0F 0xEE /r"/"RM" + { + ND_INS_PMAXSW, ND_CAT_MMX, ND_SET_MMX, 553, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:921 Instruction:"PMAXSW Vx,Wx" Encoding:"0x66 0x0F 0xEE /r"/"RM" + { + ND_INS_PMAXSW, ND_CAT_SSE, ND_SET_SSE2, 553, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:922 Instruction:"PMAXUB Pq,Qq" Encoding:"NP 0x0F 0xDE /r"/"RM" + { + ND_INS_PMAXUB, ND_CAT_MMX, ND_SET_MMX, 554, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:923 Instruction:"PMAXUB Vx,Wx" Encoding:"0x66 0x0F 0xDE /r"/"RM" + { + ND_INS_PMAXUB, ND_CAT_SSE, ND_SET_SSE2, 554, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:924 Instruction:"PMAXUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3F /r"/"RM" + { + ND_INS_PMAXUD, ND_CAT_SSE, ND_SET_SSE4, 555, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:925 Instruction:"PMAXUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3E /r"/"RM" + { + ND_INS_PMAXUW, ND_CAT_SSE, ND_SET_SSE4, 556, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:926 Instruction:"PMINSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x38 /r"/"RM" + { + ND_INS_PMINSB, ND_CAT_SSE, ND_SET_SSE4, 557, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:927 Instruction:"PMINSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x39 /r"/"RM" + { + ND_INS_PMINSD, ND_CAT_SSE, ND_SET_SSE4, 558, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:928 Instruction:"PMINSW Pq,Qq" Encoding:"NP 0x0F 0xEA /r"/"RM" + { + ND_INS_PMINSW, ND_CAT_MMX, ND_SET_MMX, 559, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:929 Instruction:"PMINSW Vx,Wx" Encoding:"0x66 0x0F 0xEA /r"/"RM" + { + ND_INS_PMINSW, ND_CAT_SSE, ND_SET_SSE2, 559, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:930 Instruction:"PMINUB Pq,Qq" Encoding:"NP 0x0F 0xDA /r"/"RM" + { + ND_INS_PMINUB, ND_CAT_MMX, ND_SET_MMX, 560, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:931 Instruction:"PMINUB Vx,Wx" Encoding:"0x66 0x0F 0xDA /r"/"RM" + { + ND_INS_PMINUB, ND_CAT_SSE, ND_SET_SSE2, 560, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:932 Instruction:"PMINUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3B /r"/"RM" + { + ND_INS_PMINUD, ND_CAT_SSE, ND_SET_SSE4, 561, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:933 Instruction:"PMINUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3A /r"/"RM" + { + ND_INS_PMINUW, ND_CAT_SSE, ND_SET_SSE4, 562, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:934 Instruction:"PMOVMSKB Gd,Nq" Encoding:"NP 0x0F 0xD7 /r:reg"/"RM" + { + ND_INS_PMOVMSKB, ND_CAT_MMX, ND_SET_SSE, 563, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_N, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:935 Instruction:"PMOVMSKB Gd,Ux" Encoding:"0x66 0x0F 0xD7 /r:reg"/"RM" + { + ND_INS_PMOVMSKB, ND_CAT_SSE, ND_SET_SSE2, 563, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:936 Instruction:"PMOVSXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x21 /r"/"RM" + { + ND_INS_PMOVSXBD, ND_CAT_SSE, ND_SET_SSE4, 564, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:937 Instruction:"PMOVSXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x22 /r"/"RM" + { + ND_INS_PMOVSXBQ, ND_CAT_SSE, ND_SET_SSE4, 565, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:938 Instruction:"PMOVSXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x20 /r"/"RM" + { + ND_INS_PMOVSXBW, ND_CAT_SSE, ND_SET_SSE4, 566, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:939 Instruction:"PMOVSXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x25 /r"/"RM" + { + ND_INS_PMOVSXDQ, ND_CAT_SSE, ND_SET_SSE4, 567, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:940 Instruction:"PMOVSXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x23 /r"/"RM" + { + ND_INS_PMOVSXWD, ND_CAT_SSE, ND_SET_SSE4, 568, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:941 Instruction:"PMOVSXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x24 /r"/"RM" + { + ND_INS_PMOVSXWQ, ND_CAT_SSE, ND_SET_SSE4, 569, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:942 Instruction:"PMOVZXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x31 /r"/"RM" + { + ND_INS_PMOVZXBD, ND_CAT_SSE, ND_SET_SSE4, 570, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:943 Instruction:"PMOVZXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x32 /r"/"RM" + { + ND_INS_PMOVZXBQ, ND_CAT_SSE, ND_SET_SSE4, 571, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:944 Instruction:"PMOVZXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x30 /r"/"RM" + { + ND_INS_PMOVZXBW, ND_CAT_SSE, ND_SET_SSE4, 572, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:945 Instruction:"PMOVZXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x35 /r"/"RM" + { + ND_INS_PMOVZXDQ, ND_CAT_SSE, ND_SET_SSE4, 573, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:946 Instruction:"PMOVZXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x33 /r"/"RM" + { + ND_INS_PMOVZXWD, ND_CAT_SSE, ND_SET_SSE4, 574, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:947 Instruction:"PMOVZXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x34 /r"/"RM" + { + ND_INS_PMOVZXWQ, ND_CAT_SSE, ND_SET_SSE4, 575, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:948 Instruction:"PMULDQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x28 /r"/"RM" + { + ND_INS_PMULDQ, ND_CAT_SSE, ND_SET_SSE4, 576, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:949 Instruction:"PMULHRSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x0B /r"/"RM" + { + ND_INS_PMULHRSW, ND_CAT_MMX, ND_SET_SSSE3, 577, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:950 Instruction:"PMULHRSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0B /r"/"RM" + { + ND_INS_PMULHRSW, ND_CAT_SSE, ND_SET_SSSE3, 577, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:951 Instruction:"PMULHRW Pq,Qq" Encoding:"0x0F 0x0F /r 0xB7"/"RM" + { + ND_INS_PMULHRW, ND_CAT_3DNOW, ND_SET_3DNOW, 578, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:952 Instruction:"PMULHUW Pq,Qq" Encoding:"NP 0x0F 0xE4 /r"/"RM" + { + ND_INS_PMULHUW, ND_CAT_MMX, ND_SET_MMX, 579, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:953 Instruction:"PMULHUW Vx,Wx" Encoding:"0x66 0x0F 0xE4 /r"/"RM" + { + ND_INS_PMULHUW, ND_CAT_SSE, ND_SET_SSE2, 579, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:954 Instruction:"PMULHW Pq,Qq" Encoding:"NP 0x0F 0xE5 /r"/"RM" + { + ND_INS_PMULHW, ND_CAT_MMX, ND_SET_MMX, 580, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:955 Instruction:"PMULHW Vx,Wx" Encoding:"0x66 0x0F 0xE5 /r"/"RM" + { + ND_INS_PMULHW, ND_CAT_SSE, ND_SET_SSE2, 580, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:956 Instruction:"PMULLD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x40 /r"/"RM" + { + ND_INS_PMULLD, ND_CAT_SSE, ND_SET_SSE4, 581, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:957 Instruction:"PMULLW Pq,Qq" Encoding:"NP 0x0F 0xD5 /r"/"RM" + { + ND_INS_PMULLW, ND_CAT_MMX, ND_SET_MMX, 582, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:958 Instruction:"PMULLW Vx,Wx" Encoding:"0x66 0x0F 0xD5 /r"/"RM" + { + ND_INS_PMULLW, ND_CAT_SSE, ND_SET_SSE2, 582, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:959 Instruction:"PMULUDQ Pq,Qq" Encoding:"NP 0x0F 0xF4 /r"/"RM" + { + ND_INS_PMULUDQ, ND_CAT_MMX, ND_SET_SSE2, 583, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:960 Instruction:"PMULUDQ Vx,Wx" Encoding:"0x66 0x0F 0xF4 /r"/"RM" + { + ND_INS_PMULUDQ, ND_CAT_SSE, ND_SET_SSE2, 583, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:961 Instruction:"POP FS" Encoding:"0x0F 0xA1"/"" + { + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_FS, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:962 Instruction:"POP GS" Encoding:"0x0F 0xA9"/"" + { + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_GS, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:963 Instruction:"POP ES" Encoding:"0x07"/"" + { + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_ES, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:964 Instruction:"POP SS" Encoding:"0x17"/"" + { + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_SS, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:965 Instruction:"POP DS" Encoding:"0x1F"/"" + { + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_DS, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:966 Instruction:"POP Zv" Encoding:"0x58"/"O" + { + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:967 Instruction:"POP Zv" Encoding:"0x59"/"O" + { + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:968 Instruction:"POP Zv" Encoding:"0x5A"/"O" + { + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:969 Instruction:"POP Zv" Encoding:"0x5B"/"O" + { + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:970 Instruction:"POP Zv" Encoding:"0x5C"/"O" + { + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:971 Instruction:"POP Zv" Encoding:"0x5D"/"O" + { + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:972 Instruction:"POP Zv" Encoding:"0x5E"/"O" + { + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:973 Instruction:"POP Zv" Encoding:"0x5F"/"O" + { + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:974 Instruction:"POP Ev" Encoding:"0x8F /0"/"M" + { + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:975 Instruction:"POPA" Encoding:"0x61"/"" + { + ND_INS_POPA, ND_CAT_POP, ND_SET_I386, 585, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v8, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:976 Instruction:"POPCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xB8 /r"/"RM" + { + ND_INS_POPCNT, ND_CAT_SSE, ND_SET_POPCNT, 586, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_POPCNT, + 0, + 0|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:977 Instruction:"POPFD Fv" Encoding:"ds32 0x9D"/"" + { + ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 587, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:978 Instruction:"POPFQ Fv" Encoding:"dds64 0x9D"/"" + { + ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 588, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:979 Instruction:"POPFW Fv" Encoding:"ds16 0x9D"/"" + { + ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 589, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:980 Instruction:"POR Pq,Qq" Encoding:"NP 0x0F 0xEB /r"/"RM" + { + ND_INS_POR, ND_CAT_LOGICAL, ND_SET_MMX, 590, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:981 Instruction:"POR Vx,Wx" Encoding:"0x66 0x0F 0xEB /r"/"RM" + { + ND_INS_POR, ND_CAT_LOGICAL, ND_SET_SSE2, 590, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:982 Instruction:"PREFETCH Mcl" Encoding:"0x0F 0x0D /4:mem"/"M" + { + ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 591, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0), + }, + + // Pos:983 Instruction:"PREFETCH Mcl" Encoding:"0x0F 0x0D /5:mem"/"M" + { + ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 591, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0), + }, + + // Pos:984 Instruction:"PREFETCH Mcl" Encoding:"0x0F 0x0D /6:mem"/"M" + { + ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 591, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0), + }, + + // Pos:985 Instruction:"PREFETCH Mcl" Encoding:"0x0F 0x0D /7:mem"/"M" + { + ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 591, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0), + }, + + // Pos:986 Instruction:"PREFETCHE Mcl" Encoding:"0x0F 0x0D /0:mem"/"M" + { + ND_INS_PREFETCHE, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 592, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0), + }, + + // Pos:987 Instruction:"PREFETCHM Mcl" Encoding:"0x0F 0x0D /3:mem"/"M" + { + ND_INS_PREFETCHM, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 593, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0), + }, + + // Pos:988 Instruction:"PREFETCHNTA Mcl" Encoding:"0x0F 0x18 /0:mem"/"M" + { + ND_INS_PREFETCHNTA, ND_CAT_PREFETCH, ND_SET_SSE, 594, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0), + }, + + // Pos:989 Instruction:"PREFETCHT0 Mcl" Encoding:"0x0F 0x18 /1:mem"/"M" + { + ND_INS_PREFETCHT0, ND_CAT_PREFETCH, ND_SET_SSE, 595, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0), + }, + + // Pos:990 Instruction:"PREFETCHT1 Mcl" Encoding:"0x0F 0x18 /2:mem"/"M" + { + ND_INS_PREFETCHT1, ND_CAT_PREFETCH, ND_SET_SSE, 596, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0), + }, + + // Pos:991 Instruction:"PREFETCHT2 Mcl" Encoding:"0x0F 0x18 /3:mem"/"M" + { + ND_INS_PREFETCHT2, ND_CAT_PREFETCH, ND_SET_SSE, 597, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0), + }, + + // Pos:992 Instruction:"PREFETCHW Mcl" Encoding:"0x0F 0x0D /1:mem"/"M" + { + ND_INS_PREFETCHW, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 598, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0), + }, + + // Pos:993 Instruction:"PREFETCHWT1 Mcl" Encoding:"0x0F 0x0D /2:mem"/"M" + { + ND_INS_PREFETCHWT1, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 599, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0), + }, + + // Pos:994 Instruction:"PSADBW Pq,Qq" Encoding:"NP 0x0F 0xF6 /r"/"RM" + { + ND_INS_PSADBW, ND_CAT_MMX, ND_SET_MMX, 600, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:995 Instruction:"PSADBW Vx,Wx" Encoding:"0x66 0x0F 0xF6 /r"/"RM" + { + ND_INS_PSADBW, ND_CAT_SSE, ND_SET_SSE2, 600, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:996 Instruction:"PSHUFB Pq,Qq" Encoding:"NP 0x0F 0x38 0x00 /r"/"RM" + { + ND_INS_PSHUFB, ND_CAT_MMX, ND_SET_SSSE3, 601, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:997 Instruction:"PSHUFB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x00 /r"/"RM" + { + ND_INS_PSHUFB, ND_CAT_SSE, ND_SET_SSSE3, 601, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:998 Instruction:"PSHUFD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x70 /r ib"/"RMI" + { + ND_INS_PSHUFD, ND_CAT_SSE, ND_SET_SSE2, 602, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:999 Instruction:"PSHUFHW Vx,Wx,Ib" Encoding:"0xF3 0x0F 0x70 /r ib"/"RMI" + { + ND_INS_PSHUFHW, ND_CAT_SSE, ND_SET_SSE2, 603, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1000 Instruction:"PSHUFLW Vx,Wx,Ib" Encoding:"0xF2 0x0F 0x70 /r ib"/"RMI" + { + ND_INS_PSHUFLW, ND_CAT_SSE, ND_SET_SSE2, 604, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1001 Instruction:"PSHUFW Pq,Qq,Ib" Encoding:"NP 0x0F 0x70 /r ib"/"RMI" + { + ND_INS_PSHUFW, ND_CAT_MMX, ND_SET_MMX, 605, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1002 Instruction:"PSIGNB Pq,Qq" Encoding:"NP 0x0F 0x38 0x08 /r"/"RM" + { + ND_INS_PSIGNB, ND_CAT_MMX, ND_SET_SSSE3, 606, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1003 Instruction:"PSIGNB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x08 /r"/"RM" + { + ND_INS_PSIGNB, ND_CAT_SSE, ND_SET_SSSE3, 606, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1004 Instruction:"PSIGND Pq,Qq" Encoding:"NP 0x0F 0x38 0x0A /r"/"RM" + { + ND_INS_PSIGND, ND_CAT_MMX, ND_SET_SSSE3, 607, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1005 Instruction:"PSIGND Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0A /r"/"RM" + { + ND_INS_PSIGND, ND_CAT_SSE, ND_SET_SSSE3, 607, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1006 Instruction:"PSIGNW Pq,Qq" Encoding:"NP 0x0F 0x38 0x09 /r"/"RM" + { + ND_INS_PSIGNW, ND_CAT_MMX, ND_SET_SSSE3, 608, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1007 Instruction:"PSIGNW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x09 /r"/"RM" + { + ND_INS_PSIGNW, ND_CAT_SSE, ND_SET_SSSE3, 608, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1008 Instruction:"PSLLD Nq,Ib" Encoding:"NP 0x0F 0x72 /6:reg ib"/"MI" + { + ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 609, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_N, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1009 Instruction:"PSLLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /6:reg ib"/"MI" + { + ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 609, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_U, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1010 Instruction:"PSLLD Pq,Qq" Encoding:"NP 0x0F 0xF2 /r"/"RM" + { + ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 609, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1011 Instruction:"PSLLD Vx,Wx" Encoding:"0x66 0x0F 0xF2 /r"/"RM" + { + ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 609, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1012 Instruction:"PSLLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /7:reg ib"/"MI" + { + ND_INS_PSLLDQ, ND_CAT_SSE, ND_SET_SSE2, 610, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_U, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1013 Instruction:"PSLLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /6:reg ib"/"MI" + { + ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 611, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_N, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1014 Instruction:"PSLLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /6:reg ib"/"MI" + { + ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 611, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_U, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1015 Instruction:"PSLLQ Pq,Qq" Encoding:"NP 0x0F 0xF3 /r"/"RM" + { + ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 611, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1016 Instruction:"PSLLQ Vx,Wx" Encoding:"0x66 0x0F 0xF3 /r"/"RM" + { + ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 611, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1017 Instruction:"PSLLW Nq,Ib" Encoding:"NP 0x0F 0x71 /6:reg ib"/"MI" + { + ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 612, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_N, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1018 Instruction:"PSLLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /6:reg ib"/"MI" + { + ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 612, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_U, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1019 Instruction:"PSLLW Pq,Qq" Encoding:"NP 0x0F 0xF1 /r"/"RM" + { + ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 612, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1020 Instruction:"PSLLW Vx,Wx" Encoding:"0x66 0x0F 0xF1 /r"/"RM" + { + ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 612, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1021 Instruction:"PSMASH" Encoding:"0xF3 0x0F 0x01 /0xFF"/"" + { + ND_INS_PSMASH, ND_CAT_SYSTEM, ND_SET_SNP, 613, + ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, + 0, + 0|REG_RFLAG_OF|REG_RFLAG_ZF|REG_RFLAG_AF|REG_RFLAG_PF|REG_RFLAG_SF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1022 Instruction:"PSRAD Nq,Ib" Encoding:"NP 0x0F 0x72 /4:reg ib"/"MI" + { + ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 614, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_N, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1023 Instruction:"PSRAD Ux,Ib" Encoding:"0x66 0x0F 0x72 /4:reg ib"/"MI" + { + ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 614, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_U, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1024 Instruction:"PSRAD Pq,Qq" Encoding:"NP 0x0F 0xE2 /r"/"RM" + { + ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 614, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1025 Instruction:"PSRAD Vx,Wx" Encoding:"0x66 0x0F 0xE2 /r"/"RM" + { + ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 614, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1026 Instruction:"PSRAW Nq,Ib" Encoding:"NP 0x0F 0x71 /4:reg ib"/"MI" + { + ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 615, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_N, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1027 Instruction:"PSRAW Ux,Ib" Encoding:"0x66 0x0F 0x71 /4:reg ib"/"MI" + { + ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 615, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_U, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1028 Instruction:"PSRAW Pq,Qq" Encoding:"NP 0x0F 0xE1 /r"/"RM" + { + ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 615, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1029 Instruction:"PSRAW Vx,Wx" Encoding:"0x66 0x0F 0xE1 /r"/"RM" + { + ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 615, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1030 Instruction:"PSRLD Nq,Ib" Encoding:"NP 0x0F 0x72 /2:reg ib"/"MI" + { + ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 616, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_N, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1031 Instruction:"PSRLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /2:reg ib"/"MI" + { + ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 616, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_U, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1032 Instruction:"PSRLD Pq,Qq" Encoding:"NP 0x0F 0xD2 /r"/"RM" + { + ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 616, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1033 Instruction:"PSRLD Vx,Wx" Encoding:"0x66 0x0F 0xD2 /r"/"RM" + { + ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 616, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1034 Instruction:"PSRLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /3:reg ib"/"MI" + { + ND_INS_PSRLDQ, ND_CAT_SSE, ND_SET_SSE2, 617, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_U, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1035 Instruction:"PSRLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /2:reg ib"/"MI" + { + ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 618, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_N, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1036 Instruction:"PSRLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /2:reg ib"/"MI" + { + ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 618, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_U, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1037 Instruction:"PSRLQ Pq,Qq" Encoding:"NP 0x0F 0xD3 /r"/"RM" + { + ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 618, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1038 Instruction:"PSRLQ Vx,Wx" Encoding:"0x66 0x0F 0xD3 /r"/"RM" + { + ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 618, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1039 Instruction:"PSRLW Nq,Ib" Encoding:"NP 0x0F 0x71 /2:reg ib"/"MI" + { + ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 619, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_N, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1040 Instruction:"PSRLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /2:reg ib"/"MI" + { + ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 619, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_U, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1041 Instruction:"PSRLW Pq,Qq" Encoding:"NP 0x0F 0xD1 /r"/"RM" + { + ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 619, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1042 Instruction:"PSRLW Vx,Wx" Encoding:"0x66 0x0F 0xD1 /r"/"RM" + { + ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 619, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1043 Instruction:"PSUBB Pq,Qq" Encoding:"NP 0x0F 0xF8 /r"/"RM" + { + ND_INS_PSUBB, ND_CAT_MMX, ND_SET_MMX, 620, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1044 Instruction:"PSUBB Vx,Wx" Encoding:"0x66 0x0F 0xF8 /r"/"RM" + { + ND_INS_PSUBB, ND_CAT_SSE, ND_SET_SSE2, 620, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1045 Instruction:"PSUBD Pq,Qq" Encoding:"NP 0x0F 0xFA /r"/"RM" + { + ND_INS_PSUBD, ND_CAT_MMX, ND_SET_MMX, 621, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1046 Instruction:"PSUBD Vx,Wx" Encoding:"0x66 0x0F 0xFA /r"/"RM" + { + ND_INS_PSUBD, ND_CAT_SSE, ND_SET_SSE2, 621, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1047 Instruction:"PSUBQ Pq,Qq" Encoding:"NP 0x0F 0xFB /r"/"RM" + { + ND_INS_PSUBQ, ND_CAT_MMX, ND_SET_MMX, 622, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1048 Instruction:"PSUBQ Vx,Wx" Encoding:"0x66 0x0F 0xFB /r"/"RM" + { + ND_INS_PSUBQ, ND_CAT_SSE, ND_SET_SSE2, 622, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1049 Instruction:"PSUBSB Pq,Qq" Encoding:"NP 0x0F 0xE8 /r"/"RM" + { + ND_INS_PSUBSB, ND_CAT_MMX, ND_SET_MMX, 623, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1050 Instruction:"PSUBSB Vx,Wx" Encoding:"0x66 0x0F 0xE8 /r"/"RM" + { + ND_INS_PSUBSB, ND_CAT_SSE, ND_SET_SSE2, 623, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1051 Instruction:"PSUBSW Pq,Qq" Encoding:"NP 0x0F 0xE9 /r"/"RM" + { + ND_INS_PSUBSW, ND_CAT_MMX, ND_SET_MMX, 624, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1052 Instruction:"PSUBSW Vx,Wx" Encoding:"0x66 0x0F 0xE9 /r"/"RM" + { + ND_INS_PSUBSW, ND_CAT_SSE, ND_SET_SSE2, 624, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1053 Instruction:"PSUBUSB Pq,Qq" Encoding:"NP 0x0F 0xD8 /r"/"RM" + { + ND_INS_PSUBUSB, ND_CAT_MMX, ND_SET_MMX, 625, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1054 Instruction:"PSUBUSB Vx,Wx" Encoding:"0x66 0x0F 0xD8 /r"/"RM" + { + ND_INS_PSUBUSB, ND_CAT_SSE, ND_SET_SSE2, 625, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1055 Instruction:"PSUBUSW Pq,Qq" Encoding:"NP 0x0F 0xD9 /r"/"RM" + { + ND_INS_PSUBUSW, ND_CAT_MMX, ND_SET_MMX, 626, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1056 Instruction:"PSUBUSW Vx,Wx" Encoding:"0x66 0x0F 0xD9 /r"/"RM" + { + ND_INS_PSUBUSW, ND_CAT_SSE, ND_SET_SSE2, 626, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1057 Instruction:"PSUBW Pq,Qq" Encoding:"NP 0x0F 0xF9 /r"/"RM" + { + ND_INS_PSUBW, ND_CAT_MMX, ND_SET_MMX, 627, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1058 Instruction:"PSUBW Vx,Wx" Encoding:"0x66 0x0F 0xF9 /r"/"RM" + { + ND_INS_PSUBW, ND_CAT_SSE, ND_SET_SSE2, 627, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1059 Instruction:"PSWAPD Pq,Qq" Encoding:"0x0F 0x0F /r 0xBB"/"RM" + { + ND_INS_PSWAPD, ND_CAT_3DNOW, ND_SET_3DNOW, 628, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1060 Instruction:"PTEST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x17 /r"/"RM" + { + ND_INS_PTEST, ND_CAT_SSE, ND_SET_SSE4, 629, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1061 Instruction:"PTWRITE Ey" Encoding:"0xF3 0x0F 0xAE /4"/"M" + { + ND_INS_PTWRITE, ND_CAT_PTWRITE, ND_SET_PTWRITE, 630, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NO66|ND_FLAG_MODRM, ND_CFF_PTWRITE, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1062 Instruction:"PUNPCKHBW Pq,Qq" Encoding:"NP 0x0F 0x68 /r"/"RM" + { + ND_INS_PUNPCKHBW, ND_CAT_MMX, ND_SET_MMX, 631, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1063 Instruction:"PUNPCKHBW Vx,Wx" Encoding:"0x66 0x0F 0x68 /r"/"RM" + { + ND_INS_PUNPCKHBW, ND_CAT_SSE, ND_SET_SSE2, 631, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1064 Instruction:"PUNPCKHDQ Pq,Qq" Encoding:"NP 0x0F 0x6A /r"/"RM" + { + ND_INS_PUNPCKHDQ, ND_CAT_MMX, ND_SET_MMX, 632, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1065 Instruction:"PUNPCKHDQ Vx,Wx" Encoding:"0x66 0x0F 0x6A /r"/"RM" + { + ND_INS_PUNPCKHDQ, ND_CAT_SSE, ND_SET_SSE2, 632, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1066 Instruction:"PUNPCKHQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6D /r"/"RM" + { + ND_INS_PUNPCKHQDQ, ND_CAT_SSE, ND_SET_SSE2, 633, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1067 Instruction:"PUNPCKHWD Pq,Qq" Encoding:"NP 0x0F 0x69 /r"/"RM" + { + ND_INS_PUNPCKHWD, ND_CAT_MMX, ND_SET_MMX, 634, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1068 Instruction:"PUNPCKHWD Vx,Wx" Encoding:"0x66 0x0F 0x69 /r"/"RM" + { + ND_INS_PUNPCKHWD, ND_CAT_SSE, ND_SET_SSE2, 634, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1069 Instruction:"PUNPCKLBW Pq,Qd" Encoding:"NP 0x0F 0x60 /r"/"RM" + { + ND_INS_PUNPCKLBW, ND_CAT_MMX, ND_SET_MMX, 635, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:1070 Instruction:"PUNPCKLBW Vx,Wx" Encoding:"0x66 0x0F 0x60 /r"/"RM" + { + ND_INS_PUNPCKLBW, ND_CAT_SSE, ND_SET_SSE2, 635, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1071 Instruction:"PUNPCKLDQ Pq,Qd" Encoding:"NP 0x0F 0x62 /r"/"RM" + { + ND_INS_PUNPCKLDQ, ND_CAT_MMX, ND_SET_MMX, 636, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:1072 Instruction:"PUNPCKLDQ Vx,Wx" Encoding:"0x66 0x0F 0x62 /r"/"RM" + { + ND_INS_PUNPCKLDQ, ND_CAT_SSE, ND_SET_SSE2, 636, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1073 Instruction:"PUNPCKLQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6C /r"/"RM" + { + ND_INS_PUNPCKLQDQ, ND_CAT_SSE, ND_SET_SSE2, 637, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1074 Instruction:"PUNPCKLWD Pq,Qd" Encoding:"NP 0x0F 0x61 /r"/"RM" + { + ND_INS_PUNPCKLWD, ND_CAT_MMX, ND_SET_MMX, 638, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:1075 Instruction:"PUNPCKLWD Vx,Wx" Encoding:"0x66 0x0F 0x61 /r"/"RM" + { + ND_INS_PUNPCKLWD, ND_CAT_SSE, ND_SET_SSE2, 638, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1076 Instruction:"PUSH FS" Encoding:"0x0F 0xA0"/"" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_FS, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1077 Instruction:"PUSH GS" Encoding:"0x0F 0xA8"/"" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_GS, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1078 Instruction:"PUSH ES" Encoding:"0x06"/"" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_ES, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1079 Instruction:"PUSH CS" Encoding:"0x0E"/"" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1080 Instruction:"PUSH SS" Encoding:"0x16"/"" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_SS, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1081 Instruction:"PUSH DS" Encoding:"0x1E"/"" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_DS, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1082 Instruction:"PUSH Zv" Encoding:"0x50"/"O" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1083 Instruction:"PUSH Zv" Encoding:"0x51"/"O" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1084 Instruction:"PUSH Zv" Encoding:"0x52"/"O" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1085 Instruction:"PUSH Zv" Encoding:"0x53"/"O" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1086 Instruction:"PUSH Zv" Encoding:"0x54"/"O" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1087 Instruction:"PUSH Zv" Encoding:"0x55"/"O" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1088 Instruction:"PUSH Zv" Encoding:"0x56"/"O" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1089 Instruction:"PUSH Zv" Encoding:"0x57"/"O" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1090 Instruction:"PUSH Iz" Encoding:"0x68 iz"/"I" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_DWS|ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1091 Instruction:"PUSH Ib" Encoding:"0x6A ib"/"I" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_DWS|ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1092 Instruction:"PUSH Ev" Encoding:"0xFF /6"/"M" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1093 Instruction:"PUSHA" Encoding:"0x60"/"" + { + ND_INS_PUSHA, ND_CAT_PUSH, ND_SET_I386, 640, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v8, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1094 Instruction:"PUSHFD Fv" Encoding:"ds32 0x9C"/"" + { + ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 641, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1095 Instruction:"PUSHFQ Fv" Encoding:"dds64 0x9C"/"" + { + ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 642, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1096 Instruction:"PUSHFW Fv" Encoding:"ds16 0x9C"/"" + { + ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 643, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1097 Instruction:"PVALIDATE" Encoding:"0xF2 0x0F 0x01 /0xFF"/"" + { + ND_INS_PVALIDATE, ND_CAT_SYSTEM, ND_SET_SNP, 644, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SNP, + 0, + 0|REG_RFLAG_OF|REG_RFLAG_ZF|REG_RFLAG_AF|REG_RFLAG_PF|REG_RFLAG_SF|REG_RFLAG_CF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1098 Instruction:"PXOR Pq,Qq" Encoding:"NP 0x0F 0xEF /r"/"RM" + { + ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_MMX, 645, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1099 Instruction:"PXOR Vx,Wx" Encoding:"0x66 0x0F 0xEF /r"/"RM" + { + ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_SSE2, 645, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1100 Instruction:"RCL Eb,Ib" Encoding:"0xC0 /2 ib"/"MI" + { + ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 646, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1101 Instruction:"RCL Ev,Ib" Encoding:"0xC1 /2 ib"/"MI" + { + ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 646, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1102 Instruction:"RCL Eb,1" Encoding:"0xD0 /2"/"M1" + { + ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 646, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1103 Instruction:"RCL Ev,1" Encoding:"0xD1 /2"/"M1" + { + ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 646, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1104 Instruction:"RCL Eb,CL" Encoding:"0xD2 /2"/"MC" + { + ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 646, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1105 Instruction:"RCL Ev,CL" Encoding:"0xD3 /2"/"MC" + { + ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 646, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1106 Instruction:"RCPPS Vps,Wps" Encoding:"NP 0x0F 0x53 /r"/"RM" + { + ND_INS_RCPPS, ND_CAT_SSE, ND_SET_SSE, 647, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1107 Instruction:"RCPSS Vss,Wss" Encoding:"0xF3 0x0F 0x53 /r"/"RM" + { + ND_INS_RCPSS, ND_CAT_SSE, ND_SET_SSE, 648, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1108 Instruction:"RCR Eb,Ib" Encoding:"0xC0 /3 ib"/"MI" + { + ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 649, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1109 Instruction:"RCR Ev,Ib" Encoding:"0xC1 /3 ib"/"MI" + { + ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 649, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1110 Instruction:"RCR Eb,1" Encoding:"0xD0 /3"/"M1" + { + ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 649, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1111 Instruction:"RCR Ev,1" Encoding:"0xD1 /3"/"M1" + { + ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 649, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1112 Instruction:"RCR Eb,CL" Encoding:"0xD2 /3"/"MC" + { + ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 649, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1113 Instruction:"RCR Ev,CL" Encoding:"0xD3 /3"/"MC" + { + ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 649, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1114 Instruction:"RDFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /0:reg"/"M" + { + ND_INS_RDFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 650, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_MSR_FSBASE, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1115 Instruction:"RDGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /1:reg"/"M" + { + ND_INS_RDGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 651, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_MSR_GSBASE, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1116 Instruction:"RDMSR" Encoding:"0x0F 0x32"/"" + { + ND_INS_RDMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 652, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, ND_CFF_MSR, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1117 Instruction:"RDPID Rv" Encoding:"0xF3 0x0F 0xC7 /7:reg"/"M" + { + ND_INS_RDPID, ND_CAT_RDPID, ND_SET_RDPID, 653, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDPID, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_MSR_TSCAUX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1118 Instruction:"RDPKRU" Encoding:"NP 0x0F 0x01 /0xEE"/"" + { + ND_INS_RDPKRU, ND_CAT_MISC, ND_SET_PKU, 654, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PKU, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_PKRU, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1119 Instruction:"RDPMC" Encoding:"0x0F 0x33"/"" + { + ND_INS_RDPMC, ND_CAT_SYSTEM, ND_SET_RDPMC, 655, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1120 Instruction:"RDPRU" Encoding:"0x0F 0x01 /0xFD"/"" + { + ND_INS_RDPRU, ND_CAT_MISC, ND_SET_RDPRU, 656, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDPRU, + 0, + 0|REG_RFLAG_CF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1121 Instruction:"RDRAND Rv" Encoding:"0x0F 0xC7 /6:reg"/"M" + { + ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 657, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDRAND, + 0, + 0|REG_RFLAG_CF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1122 Instruction:"RDRAND Rv" Encoding:"0x66 0x0F 0xC7 /6:reg"/"M" + { + ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 657, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_RDRAND, + 0, + 0|REG_RFLAG_CF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1123 Instruction:"RDSEED Rv" Encoding:"0x0F 0xC7 /7:reg"/"M" + { + ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 658, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDSEED, + 0, + 0|REG_RFLAG_CF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1124 Instruction:"RDSEED Rv" Encoding:"0x66 0x0F 0xC7 /7:reg"/"M" + { + ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 658, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_RDSEED, + 0, + 0|REG_RFLAG_CF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1125 Instruction:"RDSHR Ed" Encoding:"cyrix 0x0F 0x36 /r"/"M" + { + ND_INS_RDSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 659, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:1126 Instruction:"RDSSPD Rd" Encoding:"a0xF3 0x0F 0x1E /1:reg"/"M" + { + ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET, 660, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_SSP, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1127 Instruction:"RDSSPQ Rq" Encoding:"a0xF3 rexw 0x0F 0x1E /1:reg"/"M" + { + ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET, 661, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_SSP, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1128 Instruction:"RDTSC" Encoding:"0x0F 0x31"/"" + { + ND_INS_RDTSC, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 662, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_MSR_TSC, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1129 Instruction:"RDTSCP" Encoding:"0x0F 0x01 /0xF9"/"" + { + ND_INS_RDTSCP, ND_CAT_SYSTEM, ND_SET_RDTSCP, 663, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDTSCP, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_MSR_TSC, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_MSR_TSCAUX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1130 Instruction:"RETF Iw" Encoding:"0xCA iw"/"I" + { + ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 664, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_I, ND_OPS_w, ND_OPF_SEX_DWS|ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v2, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v2, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1131 Instruction:"RETF" Encoding:"0xCB"/"" + { + ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 664, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v2, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v2, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1132 Instruction:"RETN Iw" Encoding:"0xC2 iw"/"I" + { + ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 665, + ND_MOD_ANY, + ND_PREF_BND, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_I, ND_OPS_w, ND_OPF_SEX_DWS|ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rSP, ND_OPS_ssz, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1133 Instruction:"RETN" Encoding:"0xC3"/"" + { + ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 665, + ND_MOD_ANY, + ND_PREF_BND, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1134 Instruction:"RMPADJUST" Encoding:"0xF3 0x0F 0x01 /0xFE"/"" + { + ND_INS_RMPADJUST, ND_CAT_SYSTEM, ND_SET_SNP, 666, + ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, + 0, + 0|REG_RFLAG_OF|REG_RFLAG_ZF|REG_RFLAG_AF|REG_RFLAG_PF|REG_RFLAG_SF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1135 Instruction:"RMPUPDATE" Encoding:"0xF2 0x0F 0x01 /0xFE"/"" + { + ND_INS_RMPUPDATE, ND_CAT_SYSTEM, ND_SET_SNP, 667, + ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, + 0, + 0|REG_RFLAG_OF|REG_RFLAG_ZF|REG_RFLAG_AF|REG_RFLAG_PF|REG_RFLAG_SF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1136 Instruction:"ROL Eb,Ib" Encoding:"0xC0 /0 ib"/"MI" + { + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 668, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1137 Instruction:"ROL Ev,Ib" Encoding:"0xC1 /0 ib"/"MI" + { + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 668, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1138 Instruction:"ROL Eb,1" Encoding:"0xD0 /0"/"M1" + { + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 668, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1139 Instruction:"ROL Ev,1" Encoding:"0xD1 /0"/"M1" + { + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 668, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1140 Instruction:"ROL Eb,CL" Encoding:"0xD2 /0"/"MC" + { + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 668, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1141 Instruction:"ROL Ev,CL" Encoding:"0xD3 /0"/"MC" + { + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 668, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1142 Instruction:"ROR Eb,Ib" Encoding:"0xC0 /1 ib"/"MI" + { + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 669, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1143 Instruction:"ROR Ev,Ib" Encoding:"0xC1 /1 ib"/"MI" + { + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 669, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1144 Instruction:"ROR Eb,1" Encoding:"0xD0 /1"/"M1" + { + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 669, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1145 Instruction:"ROR Ev,1" Encoding:"0xD1 /1"/"M1" + { + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 669, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1146 Instruction:"ROR Eb,CL" Encoding:"0xD2 /1"/"MC" + { + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 669, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1147 Instruction:"ROR Ev,CL" Encoding:"0xD3 /1"/"MC" + { + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 669, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1148 Instruction:"RORX Gy,Ey,Ib" Encoding:"vex m:3 p:3 l:0 w:x 0xF0 /r ib"/"RMI" + { + ND_INS_RORX, ND_CAT_BMI2, ND_SET_BMI2, 670, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1149 Instruction:"ROUNDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x09 /r ib"/"RMI" + { + ND_INS_ROUNDPD, ND_CAT_SSE, ND_SET_SSE4, 671, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1150 Instruction:"ROUNDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x08 /r ib"/"RMI" + { + ND_INS_ROUNDPS, ND_CAT_SSE, ND_SET_SSE4, 672, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1151 Instruction:"ROUNDSD Vsd,Wsd,Ib" Encoding:"0x66 0x0F 0x3A 0x0B /r ib"/"RMI" + { + ND_INS_ROUNDSD, ND_CAT_SSE, ND_SET_SSE4, 673, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1152 Instruction:"ROUNDSS Vss,Wss,Ib" Encoding:"0x66 0x0F 0x3A 0x0A /r ib"/"RMI" + { + ND_INS_ROUNDSS, ND_CAT_SSE, ND_SET_SSE4, 674, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1153 Instruction:"RSDC Sw,Ms" Encoding:"cyrix 0x0F 0x79 /r:mem"/"RM" + { + ND_INS_RSDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 675, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_S, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_s, ND_OPF_R, 0, 0), + }, + + // Pos:1154 Instruction:"RSLDT Ms" Encoding:"cyrix 0x0F 0x7B /r:mem"/"M" + { + ND_INS_RSLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 676, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_s, ND_OPF_R, 0, 0), + }, + + // Pos:1155 Instruction:"RSM" Encoding:"0x0F 0xAA"/"" + { + ND_INS_RSM, ND_CAT_SYSRET, ND_SET_I486, 677, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1156 Instruction:"RSQRTPS Vps,Wps" Encoding:"NP 0x0F 0x52 /r"/"RM" + { + ND_INS_RSQRTPS, ND_CAT_SSE, ND_SET_SSE, 678, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1157 Instruction:"RSQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x52 /r"/"RM" + { + ND_INS_RSQRTSS, ND_CAT_SSE, ND_SET_SSE, 679, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1158 Instruction:"RSTORSSP Mq" Encoding:"0xF3 0x0F 0x01 /5:mem"/"M" + { + ND_INS_RSTORSSP, ND_CAT_CET, ND_SET_CET, 680, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_RW, 0, 0), + }, + + // Pos:1159 Instruction:"RSTS Ms" Encoding:"cyrix 0x0F 0x7D /r:mem"/"M" + { + ND_INS_RSTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 681, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_s, ND_OPF_R, 0, 0), + }, + + // Pos:1160 Instruction:"SAHF" Encoding:"0x9E"/"" + { + ND_INS_SAHF, ND_CAT_FLAGOP, ND_SET_I86, 682, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0, + 0, + OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1161 Instruction:"SAL Eb,Ib" Encoding:"0xC0 /6 ib"/"MI" + { + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 683, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1162 Instruction:"SAL Ev,Ib" Encoding:"0xC1 /6 ib"/"MI" + { + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 683, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1163 Instruction:"SAL Eb,1" Encoding:"0xD0 /6"/"M1" + { + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 683, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1164 Instruction:"SAL Ev,1" Encoding:"0xD1 /6"/"M1" + { + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 683, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1165 Instruction:"SAL Eb,CL" Encoding:"0xD2 /6"/"MC" + { + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 683, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1166 Instruction:"SAL Ev,CL" Encoding:"0xD3 /6"/"MC" + { + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 683, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1167 Instruction:"SALC" Encoding:"0xD6"/"" + { + ND_INS_SALC, ND_CAT_FLAGOP, ND_SET_I86, 684, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_CF, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1168 Instruction:"SAR Eb,Ib" Encoding:"0xC0 /7 ib"/"MI" + { + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 685, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1169 Instruction:"SAR Ev,Ib" Encoding:"0xC1 /7 ib"/"MI" + { + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 685, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1170 Instruction:"SAR Eb,1" Encoding:"0xD0 /7"/"M1" + { + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 685, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1171 Instruction:"SAR Ev,1" Encoding:"0xD1 /7"/"M1" + { + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 685, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1172 Instruction:"SAR Eb,CL" Encoding:"0xD2 /7"/"MC" + { + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 685, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1173 Instruction:"SAR Ev,CL" Encoding:"0xD3 /7"/"MC" + { + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 685, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1174 Instruction:"SARX Gy,Ey,By" Encoding:"vex m:2 p:2 l:0 w:x 0xF7 /r"/"RMV" + { + ND_INS_SARX, ND_CAT_BMI2, ND_SET_BMI2, 686, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_B, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1175 Instruction:"SAVEPREVSSP" Encoding:"0xF3 0x0F 0x01 /0xEA"/"" + { + ND_INS_SAVEPREVSSP, ND_CAT_CET, ND_SET_CET, 687, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET, + 0, + 0, + 0, + 0, + OP(ND_OPT_MEM_SHS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_SSP, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1176 Instruction:"SBB Eb,Gb" Encoding:"0x18 /r"/"MR" + { + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1177 Instruction:"SBB Ev,Gv" Encoding:"0x19 /r"/"MR" + { + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1178 Instruction:"SBB Gb,Eb" Encoding:"0x1A /r"/"RM" + { + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1179 Instruction:"SBB Gv,Ev" Encoding:"0x1B /r"/"RM" + { + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1180 Instruction:"SBB AL,Ib" Encoding:"0x1C ib"/"I" + { + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1181 Instruction:"SBB rAX,Iz" Encoding:"0x1D iz"/"I" + { + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1182 Instruction:"SBB Eb,Ib" Encoding:"0x80 /3 ib"/"MI" + { + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1183 Instruction:"SBB Ev,Iz" Encoding:"0x81 /3 iz"/"MI" + { + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1184 Instruction:"SBB Ev,Iz" Encoding:"0x82 /3 iz"/"MI" + { + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1185 Instruction:"SBB Ev,Ib" Encoding:"0x83 /3 ib"/"MI" + { + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1186 Instruction:"SCASB AL,Yb" Encoding:"0xAE"/"" + { + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 689, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1187 Instruction:"SCASB AL,Yb" Encoding:"rep 0xAE"/"" + { + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 689, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_ZF|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1188 Instruction:"SCASD EAX,Yv" Encoding:"ds32 0xAF"/"" + { + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 690, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1189 Instruction:"SCASD EAX,Yv" Encoding:"rep ds32 0xAF"/"" + { + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 690, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_ZF|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1190 Instruction:"SCASQ RAX,Yv" Encoding:"ds64 0xAF"/"" + { + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 691, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1191 Instruction:"SCASQ RAX,Yv" Encoding:"rep ds64 0xAF"/"" + { + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 691, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_ZF|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1192 Instruction:"SCASW AX,Yv" Encoding:"ds16 0xAF"/"" + { + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 692, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1193 Instruction:"SCASW AX,Yv" Encoding:"rep ds16 0xAF"/"" + { + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 692, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_ZF|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1194 Instruction:"SERIALIZE" Encoding:"NP 0x0F 0x01 /0xE8"/"" + { + ND_INS_SERIALIZE, ND_CAT_MISC, ND_SET_SERIALIZE, 693, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SERIALIZE, + 0, + 0, + 0, + 0, + }, + + // Pos:1195 Instruction:"SETBE Eb" Encoding:"0x0F 0x96 /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 694, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1196 Instruction:"SETC Eb" Encoding:"0x0F 0x92 /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 695, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1197 Instruction:"SETL Eb" Encoding:"0x0F 0x9C /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 696, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1198 Instruction:"SETLE Eb" Encoding:"0x0F 0x9E /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 697, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1199 Instruction:"SETNB Eb" Encoding:"0x0F 0x97 /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 698, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1200 Instruction:"SETNC Eb" Encoding:"0x0F 0x93 /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 699, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1201 Instruction:"SETNL Eb" Encoding:"0x0F 0x9D /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 700, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1202 Instruction:"SETNLE Eb" Encoding:"0x0F 0x9F /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 701, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1203 Instruction:"SETNO Eb" Encoding:"0x0F 0x91 /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 702, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1204 Instruction:"SETNP Eb" Encoding:"0x0F 0x9B /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 703, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_PF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1205 Instruction:"SETNS Eb" Encoding:"0x0F 0x99 /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 704, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_SF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1206 Instruction:"SETNZ Eb" Encoding:"0x0F 0x95 /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 705, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1207 Instruction:"SETO Eb" Encoding:"0x0F 0x90 /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 706, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1208 Instruction:"SETP Eb" Encoding:"0x0F 0x9A /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 707, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_PF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1209 Instruction:"SETS Eb" Encoding:"0x0F 0x98 /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 708, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_SF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1210 Instruction:"SETSSBSY" Encoding:"0xF3 0x0F 0x01 /0xE8"/"" + { + ND_INS_SETSSBSY, ND_CAT_CET, ND_SET_CET, 709, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET, + 0, + 0, + 0, + 0, + }, + + // Pos:1211 Instruction:"SETZ Eb" Encoding:"0x0F 0x94 /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 710, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1212 Instruction:"SFENCE" Encoding:"NP 0x0F 0xAE /7:reg"/"" + { + ND_INS_SFENCE, ND_CAT_MISC, ND_SET_SSE2, 711, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + }, + + // Pos:1213 Instruction:"SGDT Ms" Encoding:"0x0F 0x01 /0:mem"/"M" + { + ND_INS_SGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 712, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_s, ND_OPF_W, 0, 0), + OP(ND_OPT_SYS_GDTR, ND_OPS_s, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1214 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC9 /r"/"RM" + { + ND_INS_SHA1MSG1, ND_CAT_SHA, ND_SET_SHA, 713, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1215 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCA /r"/"RM" + { + ND_INS_SHA1MSG2, ND_CAT_SHA, ND_SET_SHA, 714, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1216 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC8 /r"/"RM" + { + ND_INS_SHA1NEXTE, ND_CAT_SHA, ND_SET_SHA, 715, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1217 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"NP 0x0F 0x3A 0xCC /r ib"/"RMI" + { + ND_INS_SHA1RNDS4, ND_CAT_SHA, ND_SET_SHA, 716, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1218 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCC /r"/"RM" + { + ND_INS_SHA256MSG1, ND_CAT_SHA, ND_SET_SHA, 717, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1219 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCD /r"/"RM" + { + ND_INS_SHA256MSG2, ND_CAT_SHA, ND_SET_SHA, 718, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1220 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCB /r"/"RM" + { + ND_INS_SHA256RNDS2, ND_CAT_SHA, ND_SET_SHA, 719, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1221 Instruction:"SHL Eb,Ib" Encoding:"0xC0 /4 ib"/"MI" + { + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 720, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1222 Instruction:"SHL Ev,Ib" Encoding:"0xC1 /4 ib"/"MI" + { + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 720, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1223 Instruction:"SHL Eb,1" Encoding:"0xD0 /4"/"M1" + { + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 720, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1224 Instruction:"SHL Ev,1" Encoding:"0xD1 /4"/"M1" + { + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 720, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1225 Instruction:"SHL Eb,CL" Encoding:"0xD2 /4"/"MC" + { + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 720, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1226 Instruction:"SHL Ev,CL" Encoding:"0xD3 /4"/"MC" + { + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 720, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1227 Instruction:"SHLD Ev,Gv,Ib" Encoding:"0x0F 0xA4 /r ib"/"MRI" + { + ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 721, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1228 Instruction:"SHLD Ev,Gv,CL" Encoding:"0x0F 0xA5 /r"/"MRC" + { + ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 721, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1229 Instruction:"SHLX Gy,Ey,By" Encoding:"vex m:2 p:1 l:0 w:x 0xF7 /r"/"RMV" + { + ND_INS_SHLX, ND_CAT_BMI2, ND_SET_BMI2, 722, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_B, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1230 Instruction:"SHR Eb,Ib" Encoding:"0xC0 /5 ib"/"MI" + { + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 723, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1231 Instruction:"SHR Ev,Ib" Encoding:"0xC1 /5 ib"/"MI" + { + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 723, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1232 Instruction:"SHR Eb,1" Encoding:"0xD0 /5"/"M1" + { + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 723, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1233 Instruction:"SHR Ev,1" Encoding:"0xD1 /5"/"M1" + { + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 723, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1234 Instruction:"SHR Eb,CL" Encoding:"0xD2 /5"/"MC" + { + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 723, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1235 Instruction:"SHR Ev,CL" Encoding:"0xD3 /5"/"MC" + { + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 723, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1236 Instruction:"SHRD Ev,Gv,Ib" Encoding:"0x0F 0xAC /r ib"/"MRI" + { + ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 724, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1237 Instruction:"SHRD Ev,Gv,CL" Encoding:"0x0F 0xAD /r"/"MRC" + { + ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 724, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1238 Instruction:"SHRX Gy,Ey,By" Encoding:"vex m:2 p:3 l:0 w:x 0xF7 /r"/"RMV" + { + ND_INS_SHRX, ND_CAT_BMI2, ND_SET_BMI2, 725, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_B, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1239 Instruction:"SHUFPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC6 /r ib"/"RMI" + { + ND_INS_SHUFPD, ND_CAT_SSE, ND_SET_SSE2, 726, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1240 Instruction:"SHUFPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC6 /r ib"/"RMI" + { + ND_INS_SHUFPS, ND_CAT_SSE, ND_SET_SSE, 727, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1241 Instruction:"SIDT Ms" Encoding:"0x0F 0x01 /1:mem"/"M" + { + ND_INS_SIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 728, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_s, ND_OPF_W, 0, 0), + OP(ND_OPT_SYS_IDTR, ND_OPS_s, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1242 Instruction:"SKINIT" Encoding:"0x0F 0x01 /0xDE"/"" + { + ND_INS_SKINIT, ND_CAT_SYSTEM, ND_SET_SVM, 729, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1243 Instruction:"SLDT Mw" Encoding:"0x0F 0x00 /0:mem"/"M" + { + ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 730, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_SYS_LDTR, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1244 Instruction:"SLDT Rv" Encoding:"0x0F 0x00 /0:reg"/"M" + { + ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 730, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_SYS_LDTR, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1245 Instruction:"SLWPCB Ry" Encoding:"xop m:9 0x12 /1:reg"/"M" + { + ND_INS_SLWPCB, ND_CAT_LWP, ND_SET_LWP, 731, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1246 Instruction:"SMINT" Encoding:"cyrix 0x0F 0x7E"/"" + { + ND_INS_SMINT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 732, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:1247 Instruction:"SMSW Mw" Encoding:"0x0F 0x01 /4:mem"/"M" + { + ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 733, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_CR_0, ND_OPS_yf, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1248 Instruction:"SMSW Rv" Encoding:"0x0F 0x01 /4:reg"/"M" + { + ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 733, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_CR_0, ND_OPS_yf, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1249 Instruction:"SPFLT Ry" Encoding:"vex m:1 p:3 0xAE /6:reg"/"M" + { + ND_INS_SPFLT, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 734, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1250 Instruction:"SQRTPD Vpd,Wpd" Encoding:"0x66 0x0F 0x51 /r"/"RM" + { + ND_INS_SQRTPD, ND_CAT_SSE, ND_SET_SSE2, 735, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:1251 Instruction:"SQRTPS Vps,Wps" Encoding:"NP 0x0F 0x51 /r"/"RM" + { + ND_INS_SQRTPS, ND_CAT_SSE, ND_SET_SSE, 736, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1252 Instruction:"SQRTSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x51 /r"/"RM" + { + ND_INS_SQRTSD, ND_CAT_SSE, ND_SET_SSE2, 737, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1253 Instruction:"SQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x51 /r"/"RM" + { + ND_INS_SQRTSS, ND_CAT_SSE, ND_SET_SSE, 738, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1254 Instruction:"STAC" Encoding:"NP 0x0F 0x01 /0xCB"/"" + { + ND_INS_STAC, ND_CAT_SMAP, ND_SET_SMAP, 739, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SMAP, + 0, + 0, + 0|REG_RFLAG_AC, + 0, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1255 Instruction:"STC" Encoding:"0xF9"/"" + { + ND_INS_STC, ND_CAT_FLAGOP, ND_SET_I86, 740, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0|REG_RFLAG_CF, + 0, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1256 Instruction:"STD" Encoding:"0xFD"/"" + { + ND_INS_STD, ND_CAT_FLAGOP, ND_SET_I86, 741, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0|REG_RFLAG_DF, + 0, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1257 Instruction:"STGI" Encoding:"0x0F 0x01 /0xDC"/"" + { + ND_INS_STGI, ND_CAT_SYSTEM, ND_SET_SVM, 742, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, + 0, + 0, + 0, + 0, + }, + + // Pos:1258 Instruction:"STI" Encoding:"0xFB"/"" + { + ND_INS_STI, ND_CAT_FLAGOP, ND_SET_I86, 743, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0|REG_RFLAG_IF, + 0, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1259 Instruction:"STMXCSR Md" Encoding:"NP 0x0F 0xAE /3:mem"/"M" + { + ND_INS_STMXCSR, ND_CAT_SSE, ND_SET_SSE, 744, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1260 Instruction:"STOSB Yb,AL" Encoding:"0xAA"/"" + { + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 745, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1261 Instruction:"STOSB Yb,AL" Encoding:"rep 0xAA"/"" + { + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 745, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1262 Instruction:"STOSD Yv,EAX" Encoding:"ds32 0xAB"/"" + { + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 746, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1263 Instruction:"STOSD Yv,EAX" Encoding:"rep ds32 0xAB"/"" + { + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 746, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1264 Instruction:"STOSQ Yv,RAX" Encoding:"ds64 0xAB"/"" + { + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 747, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1265 Instruction:"STOSQ Yv,RAX" Encoding:"rep ds64 0xAB"/"" + { + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 747, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1266 Instruction:"STOSW Yv,AX" Encoding:"ds16 0xAB"/"" + { + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 748, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1267 Instruction:"STOSW Yv,AX" Encoding:"rep ds16 0xAB"/"" + { + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 748, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1268 Instruction:"STR Mw" Encoding:"0x0F 0x00 /1:mem"/"M" + { + ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 749, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_SYS_TR, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1269 Instruction:"STR Rv" Encoding:"0x0F 0x00 /1:reg"/"M" + { + ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 749, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_SYS_TR, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1270 Instruction:"STTILECFG Moq" Encoding:"vex m:2 p:1 l:0 w:0 0x49 /0:mem"/"M" + { + ND_INS_STTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 750, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E2, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_oq, ND_OPF_W, 0, 0), + }, + + // Pos:1271 Instruction:"SUB Eb,Gb" Encoding:"0x28 /r"/"MR" + { + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1272 Instruction:"SUB Ev,Gv" Encoding:"0x29 /r"/"MR" + { + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1273 Instruction:"SUB Gb,Eb" Encoding:"0x2A /r"/"RM" + { + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1274 Instruction:"SUB Gv,Ev" Encoding:"0x2B /r"/"RM" + { + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1275 Instruction:"SUB AL,Ib" Encoding:"0x2C ib"/"I" + { + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1276 Instruction:"SUB rAX,Iz" Encoding:"0x2D iz"/"I" + { + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1277 Instruction:"SUB Eb,Ib" Encoding:"0x80 /5 ib"/"MI" + { + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1278 Instruction:"SUB Ev,Iz" Encoding:"0x81 /5 iz"/"MI" + { + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1279 Instruction:"SUB Ev,Iz" Encoding:"0x82 /5 iz"/"MI" + { + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1280 Instruction:"SUB Ev,Ib" Encoding:"0x83 /5 ib"/"MI" + { + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1281 Instruction:"SUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5C /r"/"RM" + { + ND_INS_SUBPD, ND_CAT_SSE, ND_SET_SSE2, 752, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:1282 Instruction:"SUBPS Vps,Wps" Encoding:"NP 0x0F 0x5C /r"/"RM" + { + ND_INS_SUBPS, ND_CAT_SSE, ND_SET_SSE, 753, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1283 Instruction:"SUBSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5C /r"/"RM" + { + ND_INS_SUBSD, ND_CAT_SSE, ND_SET_SSE2, 754, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1284 Instruction:"SUBSS Vss,Wss" Encoding:"0xF3 0x0F 0x5C /r"/"RM" + { + ND_INS_SUBSS, ND_CAT_SSE, ND_SET_SSE, 755, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1285 Instruction:"SVDC Ms,Sw" Encoding:"cyrix 0x0F 0x78 /r:mem"/"MR" + { + ND_INS_SVDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 756, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_s, ND_OPF_W, 0, 0), + OP(ND_OPT_S, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:1286 Instruction:"SVLDT Ms" Encoding:"cyrix 0x0F 0x7A /r:mem"/"M" + { + ND_INS_SVLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 757, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_s, ND_OPF_W, 0, 0), + }, + + // Pos:1287 Instruction:"SVTS Ms" Encoding:"cyrix 0x0F 0x7C /r:mem"/"M" + { + ND_INS_SVTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 758, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_s, ND_OPF_W, 0, 0), + }, + + // Pos:1288 Instruction:"SWAPGS" Encoding:"0x0F 0x01 /0xF8"/"" + { + ND_INS_SWAPGS, ND_CAT_SYSTEM, ND_SET_LONGMODE, 759, + ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_MSR_GSBASE, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_MSR_KGSBASE, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1289 Instruction:"SYSCALL" Encoding:"o64 0x0F 0x05"/"" + { + ND_INS_SYSCALL, ND_CAT_SYSCALL, ND_SET_AMD, 760, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 9), 0, 0, 0, 0, 0, 0, ND_FLAG_O64, ND_CFF_FSC, + 0, + 0, + 0, + 0, + OP(ND_OPT_MSR_STAR, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_MSR_LSTAR, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_MSR_FMASK, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_SS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rR11, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1290 Instruction:"SYSENTER" Encoding:"0x0F 0x34"/"" + { + ND_INS_SYSENTER, ND_CAT_SYSCALL, ND_SET_PPRO, 761, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 8), 0, 0, 0, 0, 0, 0, 0, ND_CFF_SEP, + 0, + 0, + 0, + 0|REG_RFLAG_IF, + OP(ND_OPT_MSR_SCS, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_MSR_SESP, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_MSR_SEIP, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_SS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rSP, ND_OPS_ssz, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1291 Instruction:"SYSEXIT" Encoding:"0x0F 0x35"/"" + { + ND_INS_SYSEXIT, ND_CAT_SYSRET, ND_SET_PPRO, 762, + ND_MOD_R0|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, ND_CFF_SEP, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_SS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rSP, ND_OPS_ssz, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1292 Instruction:"SYSRET" Encoding:"o64 0x0F 0x07"/"" + { + ND_INS_SYSRET, ND_CAT_SYSRET, ND_SET_AMD, 763, + ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 7), 0, 0, 0, 0, 0, 0, ND_FLAG_O64, ND_CFF_FSC, + 0, + 0, + 0, + 0, + OP(ND_OPT_MSR_STAR, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_SS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rR11, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1293 Instruction:"T1MSKC By,Ey" Encoding:"xop m:9 0x01 /7"/"VM" + { + ND_INS_T1MSKC, ND_CAT_BITBYTE, ND_SET_TBM, 764, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + 0, + 0, + 0, + 0, + OP(ND_OPT_B, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1294 Instruction:"TDPBF16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5C /r:reg"/"" + { + ND_INS_TDPBF16PS, ND_CAT_AMX, ND_SET_AMXBF16, 765, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXBF16, + 0, + 0, + 0, + 0, + OP(ND_OPT_rT, ND_OPS_t, ND_OPF_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, ND_OPF_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, ND_OPF_R, 0, 0), + }, + + // Pos:1295 Instruction:"TDPBSSD rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5E /r:reg"/"" + { + ND_INS_TDPBSSD, ND_CAT_AMX, ND_SET_AMXINT8, 766, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, + 0, + 0, + 0, + 0, + OP(ND_OPT_rT, ND_OPS_t, ND_OPF_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, ND_OPF_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, ND_OPF_R, 0, 0), + }, + + // Pos:1296 Instruction:"TDPBSUD rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5E /r:reg"/"" + { + ND_INS_TDPBSUD, ND_CAT_AMX, ND_SET_AMXINT8, 767, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, + 0, + 0, + 0, + 0, + OP(ND_OPT_rT, ND_OPS_t, ND_OPF_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, ND_OPF_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, ND_OPF_R, 0, 0), + }, + + // Pos:1297 Instruction:"TDPBUSD rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x5E /r:reg"/"" + { + ND_INS_TDPBUSD, ND_CAT_AMX, ND_SET_AMXINT8, 768, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, + 0, + 0, + 0, + 0, + OP(ND_OPT_rT, ND_OPS_t, ND_OPF_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, ND_OPF_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, ND_OPF_R, 0, 0), + }, + + // Pos:1298 Instruction:"TDPBUUD rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x5E /r:reg"/"" + { + ND_INS_TDPBUUD, ND_CAT_AMX, ND_SET_AMXINT8, 769, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, + 0, + 0, + 0, + 0, + OP(ND_OPT_rT, ND_OPS_t, ND_OPF_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, ND_OPF_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, ND_OPF_R, 0, 0), + }, + + // Pos:1299 Instruction:"TEST Eb,Gb" Encoding:"0x84 /r"/"MR" + { + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 770, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1300 Instruction:"TEST Ev,Gv" Encoding:"0x85 /r"/"MR" + { + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 770, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1301 Instruction:"TEST AL,Ib" Encoding:"0xA8 ib"/"I" + { + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 770, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1302 Instruction:"TEST rAX,Iz" Encoding:"0xA9 iz"/"I" + { + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 770, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1303 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /0 ib"/"MI" + { + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 770, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1304 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /1 ib"/"MI" + { + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 770, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1305 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /0 iz"/"MI" + { + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 770, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1306 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /1 iz"/"MI" + { + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 770, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1307 Instruction:"TILELOADD rTt,Mt" Encoding:"vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem"/"M" + { + ND_INS_TILELOADD, ND_CAT_AMX, ND_SET_AMXTILE, 771, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, + 0, + 0, + 0, + 0, + OP(ND_OPT_rT, ND_OPS_t, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_t, ND_OPF_R, 0, 0), + }, + + // Pos:1308 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem"/"M" + { + ND_INS_TILELOADDT1, ND_CAT_AMX, ND_SET_AMXTILE, 772, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, + 0, + 0, + 0, + 0, + OP(ND_OPT_rT, ND_OPS_t, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_t, ND_OPF_R, 0, 0), + }, + + // Pos:1309 Instruction:"TILERELEASE" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0xC0"/"" + { + ND_INS_TILERELEASE, ND_CAT_AMX, ND_SET_AMXTILE, 773, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(0, 0), 0, ND_EXT_AMX_E6, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, + 0, + 0, + 0, + 0, + }, + + // Pos:1310 Instruction:"TILESTORED Mt,rTt" Encoding:"vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem"/"M" + { + ND_INS_TILESTORED, ND_CAT_AMX, ND_SET_AMXTILE, 774, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_t, ND_OPF_W, 0, 0), + OP(ND_OPT_rT, ND_OPS_t, ND_OPF_R, 0, 0), + }, + + // Pos:1311 Instruction:"TILEZERO rTt" Encoding:"vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0"/"" + { + ND_INS_TILEZERO, ND_CAT_AMX, ND_SET_AMXTILE, 775, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E5, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, + 0, + 0, + 0, + 0, + OP(ND_OPT_rT, ND_OPS_t, ND_OPF_W, 0, 0), + }, + + // Pos:1312 Instruction:"TLBSYNC" Encoding:"0x0F 0x01 /0xFF"/"" + { + ND_INS_TLBSYNC, ND_CAT_SYSTEM, ND_SET_INVLPGB, 776, + ND_MOD_R0|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_INVLPGB, + 0, + 0, + 0, + 0, + }, + + // Pos:1313 Instruction:"TPAUSE Ry" Encoding:"0x66 0x0F 0xAE /6:reg"/"M" + { + ND_INS_TPAUSE, ND_CAT_WAITPKG, ND_SET_WAITPKG, 777, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, + 0, + 0|REG_RFLAG_CF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1314 Instruction:"TZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBC /r"/"RM" + { + ND_INS_TZCNT, ND_CAT_BMI1, ND_SET_BMI1, 778, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1315 Instruction:"TZMSK By,Ey" Encoding:"xop m:9 0x01 /4"/"VM" + { + ND_INS_TZMSK, ND_CAT_BITBYTE, ND_SET_TBM, 779, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + 0, + 0, + 0, + 0, + OP(ND_OPT_B, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1316 Instruction:"UCOMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2E /r"/"RM" + { + ND_INS_UCOMISD, ND_CAT_SSE2, ND_SET_SSE2, 780, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1317 Instruction:"UCOMISS Vss,Wss" Encoding:"NP 0x0F 0x2E /r"/"RM" + { + ND_INS_UCOMISS, ND_CAT_SSE, ND_SET_SSE, 781, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1318 Instruction:"UD0 Gd,Ed" Encoding:"0x0F 0xFF /r"/"RM" + { + ND_INS_UD0, ND_CAT_UD, ND_SET_UD, 782, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:1319 Instruction:"UD1 Gd,Ed" Encoding:"0x0F 0xB9 /r"/"RM" + { + ND_INS_UD1, ND_CAT_UD, ND_SET_UD, 783, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:1320 Instruction:"UD2" Encoding:"0x0F 0x0B"/"" + { + ND_INS_UD2, ND_CAT_MISC, ND_SET_PPRO, 784, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:1321 Instruction:"UMONITOR mMb" Encoding:"0xF3 0x0F 0xAE /6:reg"/"M" + { + ND_INS_UMONITOR, ND_CAT_WAITPKG, ND_SET_WAITPKG, 785, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, + 0, + 0|REG_RFLAG_CF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_mM, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1322 Instruction:"UMWAIT Ry" Encoding:"0xF2 0x0F 0xAE /6:reg"/"M" + { + ND_INS_UMWAIT, ND_CAT_WAITPKG, ND_SET_WAITPKG, 786, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1323 Instruction:"UNPCKHPD Vx,Wx" Encoding:"0x66 0x0F 0x15 /r"/"RM" + { + ND_INS_UNPCKHPD, ND_CAT_SSE, ND_SET_SSE2, 787, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1324 Instruction:"UNPCKHPS Vx,Wx" Encoding:"NP 0x0F 0x15 /r"/"RM" + { + ND_INS_UNPCKHPS, ND_CAT_SSE, ND_SET_SSE, 788, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1325 Instruction:"UNPCKLPD Vx,Wx" Encoding:"0x66 0x0F 0x14 /r"/"RM" + { + ND_INS_UNPCKLPD, ND_CAT_SSE, ND_SET_SSE2, 789, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1326 Instruction:"UNPCKLPS Vx,Wx" Encoding:"NP 0x0F 0x14 /r"/"RM" + { + ND_INS_UNPCKLPS, ND_CAT_SSE, ND_SET_SSE, 790, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1327 Instruction:"V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x9A /r:mem"/"RAVM" + { + ND_INS_V4FMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 791, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_oq, ND_OPF_R, 0, 4), + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1328 Instruction:"V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0x9B /r:mem"/"RAVM" + { + ND_INS_V4FMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 792, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 4), + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1329 Instruction:"V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0xAA /r:mem"/"RAVM" + { + ND_INS_V4FNMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 793, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_oq, ND_OPF_R, 0, 4), + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1330 Instruction:"V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0xAB /r:mem"/"RAVM" + { + ND_INS_V4FNMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 794, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 4), + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1331 Instruction:"VADDPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x58 /r"/"RAVM" + { + ND_INS_VADDPD, ND_CAT_AVX512, ND_SET_AVX512F, 795, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1332 Instruction:"VADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x58 /r"/"RVM" + { + ND_INS_VADDPD, ND_CAT_AVX, ND_SET_AVX, 795, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:1333 Instruction:"VADDPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x58 /r"/"RAVM" + { + ND_INS_VADDPS, ND_CAT_AVX512, ND_SET_AVX512F, 796, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1334 Instruction:"VADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x58 /r"/"RVM" + { + ND_INS_VADDPS, ND_CAT_AVX, ND_SET_AVX, 796, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1335 Instruction:"VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x58 /r"/"RAVM" + { + ND_INS_VADDSD, ND_CAT_AVX512, ND_SET_AVX512F, 797, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1336 Instruction:"VADDSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x58 /r"/"RVM" + { + ND_INS_VADDSD, ND_CAT_AVX, ND_SET_AVX, 797, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1337 Instruction:"VADDSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x58 /r"/"RAVM" + { + ND_INS_VADDSS, ND_CAT_AVX512, ND_SET_AVX512F, 798, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1338 Instruction:"VADDSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x58 /r"/"RVM" + { + ND_INS_VADDSS, ND_CAT_AVX, ND_SET_AVX, 798, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1339 Instruction:"VADDSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0xD0 /r"/"RVM" + { + ND_INS_VADDSUBPD, ND_CAT_AVX, ND_SET_AVX, 799, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:1340 Instruction:"VADDSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0xD0 /r"/"RVM" + { + ND_INS_VADDSUBPS, ND_CAT_AVX, ND_SET_AVX, 800, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1341 Instruction:"VAESDEC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDE /r"/"RVM" + { + ND_INS_VAESDEC, ND_CAT_VAES, ND_SET_VAES, 801, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1342 Instruction:"VAESDEC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDE /r"/"RVM" + { + ND_INS_VAESDEC, ND_CAT_AES, ND_SET_AES, 801, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1343 Instruction:"VAESDECLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDF /r"/"RVM" + { + ND_INS_VAESDECLAST, ND_CAT_VAES, ND_SET_VAES, 802, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1344 Instruction:"VAESDECLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDF /r"/"RVM" + { + ND_INS_VAESDECLAST, ND_CAT_AES, ND_SET_AES, 802, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1345 Instruction:"VAESENC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDC /r"/"RVM" + { + ND_INS_VAESENC, ND_CAT_VAES, ND_SET_VAES, 803, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1346 Instruction:"VAESENC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDC /r"/"RVM" + { + ND_INS_VAESENC, ND_CAT_AES, ND_SET_AES, 803, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1347 Instruction:"VAESENCLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDD /r"/"RVM" + { + ND_INS_VAESENCLAST, ND_CAT_VAES, ND_SET_VAES, 804, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1348 Instruction:"VAESENCLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDD /r"/"RVM" + { + ND_INS_VAESENCLAST, ND_CAT_AES, ND_SET_AES, 804, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1349 Instruction:"VAESIMC Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0xDB /r"/"RM" + { + ND_INS_VAESIMC, ND_CAT_AES, ND_SET_AES, 805, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1350 Instruction:"VAESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0xDF /r ib"/"RMI" + { + ND_INS_VAESKEYGENASSIST, ND_CAT_AES, ND_SET_AES, 806, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1351 Instruction:"VALIGND Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x03 /r ib"/"RAVMI" + { + ND_INS_VALIGND, ND_CAT_AVX512, ND_SET_AVX512F, 807, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1352 Instruction:"VALIGNQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x03 /r ib"/"RAVMI" + { + ND_INS_VALIGNQ, ND_CAT_AVX512, ND_SET_AVX512F, 808, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1353 Instruction:"VANDNPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x55 /r"/"RAVM" + { + ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 809, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:1354 Instruction:"VANDNPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x55 /r"/"RVM" + { + ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 809, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:1355 Instruction:"VANDNPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x55 /r"/"RAVM" + { + ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 810, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1356 Instruction:"VANDNPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x55 /r"/"RVM" + { + ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 810, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1357 Instruction:"VANDPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x54 /r"/"RAVM" + { + ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 811, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:1358 Instruction:"VANDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x54 /r"/"RVM" + { + ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 811, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:1359 Instruction:"VANDPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x54 /r"/"RAVM" + { + ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 812, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1360 Instruction:"VANDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x54 /r"/"RVM" + { + ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 812, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1361 Instruction:"VBLENDMPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x65 /r"/"RAVM" + { + ND_INS_VBLENDMPD, ND_CAT_BLEND, ND_SET_AVX512F, 813, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:1362 Instruction:"VBLENDMPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x65 /r"/"RAVM" + { + ND_INS_VBLENDMPS, ND_CAT_BLEND, ND_SET_AVX512F, 814, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1363 Instruction:"VBLENDPD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0D /r ib"/"RVMI" + { + ND_INS_VBLENDPD, ND_CAT_AVX, ND_SET_AVX, 815, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1364 Instruction:"VBLENDPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0C /r ib"/"RVMI" + { + ND_INS_VBLENDPS, ND_CAT_AVX, ND_SET_AVX, 816, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1365 Instruction:"VBLENDVPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4B /r is4"/"RVML" + { + ND_INS_VBLENDVPD, ND_CAT_AVX, ND_SET_AVX, 817, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1366 Instruction:"VBLENDVPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4A /r is4"/"RVML" + { + ND_INS_VBLENDVPS, ND_CAT_AVX, ND_SET_AVX, 818, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1367 Instruction:"VBROADCASTF128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x1A /r:mem"/"RM" + { + ND_INS_VBROADCASTF128, ND_CAT_BROADCAST, ND_SET_AVX, 819, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1368 Instruction:"VBROADCASTF32X2 Vu{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x19 /r"/"RAM" + { + ND_INS_VBROADCASTF32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 820, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_u, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1369 Instruction:"VBROADCASTF32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x1A /r:mem"/"RAM" + { + ND_INS_VBROADCASTF32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 821, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_u, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1370 Instruction:"VBROADCASTF32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x1B /r:mem"/"RAM" + { + ND_INS_VBROADCASTF32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 822, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_qq, ND_OPF_R, 0, 0), + }, + + // Pos:1371 Instruction:"VBROADCASTF64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x1A /r:mem"/"RAM" + { + ND_INS_VBROADCASTF64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 823, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_u, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1372 Instruction:"VBROADCASTF64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x1B /r:mem"/"RAM" + { + ND_INS_VBROADCASTF64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 824, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_qq, ND_OPF_R, 0, 0), + }, + + // Pos:1373 Instruction:"VBROADCASTI128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x5A /r:mem"/"RM" + { + ND_INS_VBROADCASTI128, ND_CAT_BROADCAST, ND_SET_AVX2, 825, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1374 Instruction:"VBROADCASTI32X2 Vn{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x59 /r"/"RAM" + { + ND_INS_VBROADCASTI32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 826, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1375 Instruction:"VBROADCASTI32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x5A /r:mem"/"RAM" + { + ND_INS_VBROADCASTI32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 827, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_u, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1376 Instruction:"VBROADCASTI32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x5B /r:mem"/"RAM" + { + ND_INS_VBROADCASTI32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 828, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_qq, ND_OPF_R, 0, 0), + }, + + // Pos:1377 Instruction:"VBROADCASTI64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x5A /r:mem"/"RAM" + { + ND_INS_VBROADCASTI64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 829, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_u, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1378 Instruction:"VBROADCASTI64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x5B /r:mem"/"RAM" + { + ND_INS_VBROADCASTI64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 830, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_qq, ND_OPF_R, 0, 0), + }, + + // Pos:1379 Instruction:"VBROADCASTSD Vu{K}{z},aKq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x19 /r"/"RAM" + { + ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX512F, 831, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_u, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1380 Instruction:"VBROADCASTSD Vqq,Wsd" Encoding:"vex m:2 p:1 l:x w:0 0x19 /r"/"RM" + { + ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX, 831, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1381 Instruction:"VBROADCASTSS Vn{K}{z},aKq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x18 /r"/"RAM" + { + ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX512F, 832, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1382 Instruction:"VBROADCASTSS Vx,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x18 /r"/"RM" + { + ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX, 832, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1383 Instruction:"VCMPPD rKq{K},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC2 /r ib"/"RAVMI" + { + ND_INS_VCMPPD, ND_CAT_AVX512, ND_SET_AVX512F, 833, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1384 Instruction:"VCMPPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC2 /r ib"/"RVMI" + { + ND_INS_VCMPPD, ND_CAT_AVX, ND_SET_AVX, 833, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1385 Instruction:"VCMPPS rKq{K},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC2 /r ib"/"RAVMI" + { + ND_INS_VCMPPS, ND_CAT_AVX512, ND_SET_AVX512F, 834, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1386 Instruction:"VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:1 p:3 l:x w:1 0xC2 /r ib"/"RAVMI" + { + ND_INS_VCMPSD, ND_CAT_AVX512, ND_SET_AVX512F, 835, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1387 Instruction:"VCMPSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:1 p:3 l:i w:i 0xC2 /r ib"/"RVMI" + { + ND_INS_VCMPSD, ND_CAT_AVX, ND_SET_AVX, 835, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1388 Instruction:"VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:1 p:2 l:x w:0 0xC2 /r ib"/"RAVMI" + { + ND_INS_VCMPSS, ND_CAT_AVX512, ND_SET_AVX512F, 836, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1389 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:0 l:i w:i 0xC2 /r ib"/"RVMI" + { + ND_INS_VCMPSS, ND_CAT_AVX, ND_SET_AVX, 836, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1390 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:2 l:i w:i 0xC2 /r ib"/"RVMI" + { + ND_INS_VCMPSS, ND_CAT_AVX, ND_SET_AVX, 836, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1391 Instruction:"VCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2F /r"/"RM" + { + ND_INS_VCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 837, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_SAE, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1392 Instruction:"VCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2F /r"/"RM" + { + ND_INS_VCOMISD, ND_CAT_AVX, ND_SET_AVX, 837, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1393 Instruction:"VCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2F /r"/"RM" + { + ND_INS_VCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 838, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_SAE, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1394 Instruction:"VCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2F /r"/"RM" + { + ND_INS_VCOMISS, ND_CAT_AVX, ND_SET_AVX, 838, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1395 Instruction:"VCOMPRESSPD Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x8A /r"/"MAR" + { + ND_INS_VCOMPRESSPD, ND_CAT_COMPRESS, ND_SET_AVX512F, 839, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1396 Instruction:"VCOMPRESSPS Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x8A /r"/"MAR" + { + ND_INS_VCOMPRESSPS, ND_CAT_COMPRESS, ND_SET_AVX512F, 840, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1397 Instruction:"VCVTDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0xE6 /r"/"RAM" + { + ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 841, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1398 Instruction:"VCVTDQ2PD Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0xE6 /r"/"RM" + { + ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 841, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1399 Instruction:"VCVTDQ2PD Vqq,Wdq" Encoding:"vex m:1 p:2 l:1 w:i 0xE6 /r"/"RM" + { + ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 841, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1400 Instruction:"VCVTDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5B /r"/"RAM" + { + ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 842, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1401 Instruction:"VCVTDQ2PS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5B /r"/"RM" + { + ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX, 842, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1402 Instruction:"VCVTNE2PS2BF16 Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:3 l:x w:0 0x72 /r"/"RAVM" + { + ND_INS_VCVTNE2PS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 843, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1403 Instruction:"VCVTNEPS2BF16 Vh{K}{z},aKq,Wn" Encoding:"evex m:2 p:2 l:x w:0 0x72 /r"/"RAM" + { + ND_INS_VCVTNEPS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 844, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_h, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1404 Instruction:"VCVTPD2DQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0xE6 /r"/"RAM" + { + ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 845, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_h, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1405 Instruction:"VCVTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:3 l:x w:i 0xE6 /r"/"RM" + { + ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 845, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1406 Instruction:"VCVTPD2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5A /r"/"RAM" + { + ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 846, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_h, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1407 Instruction:"VCVTPD2PS Vdq,Wdq" Encoding:"vex m:1 p:1 l:0 w:i 0x5A /r"/"RM" + { + ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 846, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1408 Instruction:"VCVTPD2PS Vdq,Wqq" Encoding:"vex m:1 p:1 l:1 w:i 0x5A /r"/"RM" + { + ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 846, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_qq, ND_OPF_R, 0, 0), + }, + + // Pos:1409 Instruction:"VCVTPD2QQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x7B /r"/"RAM" + { + ND_INS_VCVTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 847, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1410 Instruction:"VCVTPD2UDQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x79 /r"/"RAM" + { + ND_INS_VCVTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 848, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_h, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1411 Instruction:"VCVTPD2UQQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x79 /r"/"RAM" + { + ND_INS_VCVTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 849, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1412 Instruction:"VCVTPH2PS Vn{K}{z},aKq,Wh{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x13 /r"/"RAM" + { + ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 850, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E11, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, ND_OPD_SAE, 0), + }, + + // Pos:1413 Instruction:"VCVTPH2PS Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:0 0x13 /r"/"RM" + { + ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 850, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1414 Instruction:"VCVTPH2PS Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:0 0x13 /r"/"RM" + { + ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 850, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1415 Instruction:"VCVTPS2DQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x5B /r"/"RAM" + { + ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 851, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1416 Instruction:"VCVTPS2DQ Vps,Wps" Encoding:"vex m:1 p:1 l:x w:i 0x5B /r"/"RM" + { + ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 851, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1417 Instruction:"VCVTPS2PD Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5A /r"/"RAM" + { + ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 852, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + + // Pos:1418 Instruction:"VCVTPS2PD Vpd,Wq" Encoding:"vex m:1 p:0 l:0 w:i 0x5A /r"/"RM" + { + ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 852, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1419 Instruction:"VCVTPS2PD Vqq,Wdq" Encoding:"vex m:1 p:0 l:1 w:i 0x5A /r"/"RM" + { + ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 852, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1420 Instruction:"VCVTPS2PH Wh{K}{z},aKq,Vn{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1D /r ib"/"MARI" + { + ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_AVX512F, 853, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_HVM, ND_EXT_E11, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_h, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1421 Instruction:"VCVTPS2PH Wq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x1D /r ib"/"MRI" + { + ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 853, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1422 Instruction:"VCVTPS2PH Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x1D /r ib"/"MRI" + { + ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 853, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1423 Instruction:"VCVTPS2QQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x7B /r"/"RAM" + { + ND_INS_VCVTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 854, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1424 Instruction:"VCVTPS2UDQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x79 /r"/"RAM" + { + ND_INS_VCVTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 855, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1425 Instruction:"VCVTPS2UQQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x79 /r"/"RAM" + { + ND_INS_VCVTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 856, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1426 Instruction:"VCVTQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0xE6 /r"/"RAM" + { + ND_INS_VCVTQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 857, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1427 Instruction:"VCVTQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x5B /r"/"RAM" + { + ND_INS_VCVTQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 858, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_h, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1428 Instruction:"VCVTSD2SI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x2D /r"/"RM" + { + ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 859, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1429 Instruction:"VCVTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2D /r"/"RM" + { + ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 859, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1430 Instruction:"VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5A /r"/"RAVM" + { + ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 860, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1431 Instruction:"VCVTSD2SS Vss,Hx,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5A /r"/"RVM" + { + ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX, 860, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1432 Instruction:"VCVTSD2USI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x79 /r"/"RM" + { + ND_INS_VCVTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 861, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1433 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:0 0x2A /r"/"RVM" + { + ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 862, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, ND_OPD_ER, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1434 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x2A /r"/"RVM" + { + ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 862, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, ND_OPD_ER, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1435 Instruction:"VCVTSI2SD Vsd,Hsd,Ey" Encoding:"vex m:1 p:3 l:i w:x 0x2A /r"/"RVM" + { + ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX, 862, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1436 Instruction:"VCVTSI2SS Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x2A /r"/"RVM" + { + ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 863, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, ND_OPD_ER, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1437 Instruction:"VCVTSI2SS Vss,Hss,Ey" Encoding:"vex m:1 p:2 l:i w:x 0x2A /r"/"RVM" + { + ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX, 863, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1438 Instruction:"VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5A /r"/"RAVM" + { + ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 864, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_SAE, 0), + }, + + // Pos:1439 Instruction:"VCVTSS2SD Vsd,Hx,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5A /r"/"RVM" + { + ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX, 864, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1440 Instruction:"VCVTSS2SI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x2D /r"/"RM" + { + ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 865, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1441 Instruction:"VCVTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2D /r"/"RM" + { + ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 865, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1442 Instruction:"VCVTSS2USI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x79 /r"/"RM" + { + ND_INS_VCVTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 866, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1443 Instruction:"VCVTTPD2DQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0xE6 /r"/"RAM" + { + ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 867, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_h, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), + }, + + // Pos:1444 Instruction:"VCVTTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE6 /r"/"RM" + { + ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 867, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1445 Instruction:"VCVTTPD2QQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x7A /r"/"RAM" + { + ND_INS_VCVTTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 868, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), + }, + + // Pos:1446 Instruction:"VCVTTPD2UDQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:0 l:x w:1 0x78 /r"/"RAM" + { + ND_INS_VCVTTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 869, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_h, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), + }, + + // Pos:1447 Instruction:"VCVTTPD2UQQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x78 /r"/"RAM" + { + ND_INS_VCVTTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 870, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), + }, + + // Pos:1448 Instruction:"VCVTTPS2DQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:2 l:x w:0 0x5B /r"/"RAM" + { + ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 871, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + + // Pos:1449 Instruction:"VCVTTPS2DQ Vps,Wps" Encoding:"vex m:1 p:2 l:x w:i 0x5B /r"/"RM" + { + ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 871, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1450 Instruction:"VCVTTPS2QQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x7A /r"/"RAM" + { + ND_INS_VCVTTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 872, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + + // Pos:1451 Instruction:"VCVTTPS2UDQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x78 /r"/"RAM" + { + ND_INS_VCVTTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 873, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + + // Pos:1452 Instruction:"VCVTTPS2UQQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x78 /r"/"RAM" + { + ND_INS_VCVTTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 874, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + + // Pos:1453 Instruction:"VCVTTSD2SI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x2C /r"/"RM" + { + ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 875, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_SAE, 0), + }, + + // Pos:1454 Instruction:"VCVTTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2C /r"/"RM" + { + ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 875, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1455 Instruction:"VCVTTSD2USI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x78 /r"/"RM" + { + ND_INS_VCVTTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 876, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_SAE, 0), + }, + + // Pos:1456 Instruction:"VCVTTSS2SI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x2C /r"/"RM" + { + ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 877, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_SAE, 0), + }, + + // Pos:1457 Instruction:"VCVTTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2C /r"/"RM" + { + ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 877, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1458 Instruction:"VCVTTSS2USI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x78 /r"/"RM" + { + ND_INS_VCVTTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 878, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_SAE, 0), + }, + + // Pos:1459 Instruction:"VCVTUDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0x7A /r"/"RAM" + { + ND_INS_VCVTUDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 879, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1460 Instruction:"VCVTUDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:3 l:x w:0 0x7A /r"/"RAM" + { + ND_INS_VCVTUDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 880, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1461 Instruction:"VCVTUQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0x7A /r"/"RAM" + { + ND_INS_VCVTUQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 881, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1462 Instruction:"VCVTUQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0x7A /r"/"RAM" + { + ND_INS_VCVTUQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 882, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_h, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1463 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:0 0x7B /r"/"RVM" + { + ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 883, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, ND_OPD_ER, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1464 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x7B /r"/"RVM" + { + ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 883, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, ND_OPD_ER, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1465 Instruction:"VCVTUSI2SS Vss,Hss{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x7B /r"/"RVM" + { + ND_INS_VCVTUSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 884, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1466 Instruction:"VDBPSADBW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x42 /r ib"/"RAVMI" + { + ND_INS_VDBPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 885, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1467 Instruction:"VDIVPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5E /r"/"RAVM" + { + ND_INS_VDIVPD, ND_CAT_AVX512, ND_SET_AVX512F, 886, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1468 Instruction:"VDIVPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5E /r"/"RVM" + { + ND_INS_VDIVPD, ND_CAT_AVX, ND_SET_AVX, 886, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:1469 Instruction:"VDIVPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5E /r"/"RAVM" + { + ND_INS_VDIVPS, ND_CAT_AVX512, ND_SET_AVX512F, 887, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1470 Instruction:"VDIVPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5E /r"/"RVM" + { + ND_INS_VDIVPS, ND_CAT_AVX, ND_SET_AVX, 887, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1471 Instruction:"VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5E /r"/"RAVM" + { + ND_INS_VDIVSD, ND_CAT_AVX512, ND_SET_AVX512F, 888, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1472 Instruction:"VDIVSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5E /r"/"RVM" + { + ND_INS_VDIVSD, ND_CAT_AVX, ND_SET_AVX, 888, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1473 Instruction:"VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5E /r"/"RAVM" + { + ND_INS_VDIVSS, ND_CAT_AVX512, ND_SET_AVX512F, 889, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1474 Instruction:"VDIVSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5E /r"/"RVM" + { + ND_INS_VDIVSS, ND_CAT_AVX, ND_SET_AVX, 889, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1475 Instruction:"VDPBF16PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x52 /r"/"RAVM" + { + ND_INS_VDPBF16PS, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 890, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1476 Instruction:"VDPPD Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x41 /r ib"/"RVMI" + { + ND_INS_VDPPD, ND_CAT_AVX, ND_SET_AVX, 891, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1477 Instruction:"VDPPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x40 /r ib"/"RVMI" + { + ND_INS_VDPPS, ND_CAT_AVX, ND_SET_AVX, 892, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1478 Instruction:"VERR Ew" Encoding:"0x0F 0x00 /4"/"M" + { + ND_INS_VERR, ND_CAT_SYSTEM, ND_SET_I286PROT, 893, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1479 Instruction:"VERW Ew" Encoding:"0x0F 0x00 /5"/"M" + { + ND_INS_VERW, ND_CAT_SYSTEM, ND_SET_I286PROT, 894, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1480 Instruction:"VEXP2PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xC8 /r"/"RAM" + { + ND_INS_VEXP2PD, ND_CAT_KNL, ND_SET_AVX512ER, 895, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_oq, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), + }, + + // Pos:1481 Instruction:"VEXP2PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xC8 /r"/"RAM" + { + ND_INS_VEXP2PS, ND_CAT_KNL, ND_SET_AVX512ER, 896, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_oq, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + + // Pos:1482 Instruction:"VEXPANDPD Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x88 /r"/"RAM" + { + ND_INS_VEXPANDPD, ND_CAT_EXPAND, ND_SET_AVX512F, 897, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1483 Instruction:"VEXPANDPS Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x88 /r"/"RAM" + { + ND_INS_VEXPANDPS, ND_CAT_EXPAND, ND_SET_AVX512F, 898, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1484 Instruction:"VEXTRACTF128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x19 /r ib"/"MRI" + { + ND_INS_VEXTRACTF128, ND_CAT_AVX, ND_SET_AVX, 899, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1485 Instruction:"VEXTRACTF32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x19 /r ib"/"MARI" + { + ND_INS_VEXTRACTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 900, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_u, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1486 Instruction:"VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1B /r ib"/"MARI" + { + ND_INS_VEXTRACTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 901, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_qq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1487 Instruction:"VEXTRACTF64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x19 /r ib"/"MARI" + { + ND_INS_VEXTRACTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 902, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_u, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1488 Instruction:"VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1B /r ib"/"MARI" + { + ND_INS_VEXTRACTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 903, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_qq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1489 Instruction:"VEXTRACTI128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x39 /r ib"/"MRI" + { + ND_INS_VEXTRACTI128, ND_CAT_AVX2, ND_SET_AVX2, 904, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1490 Instruction:"VEXTRACTI32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x39 /r ib"/"MARI" + { + ND_INS_VEXTRACTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 905, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_u, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1491 Instruction:"VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3B /r ib"/"MARI" + { + ND_INS_VEXTRACTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 906, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_qq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1492 Instruction:"VEXTRACTI64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x39 /r ib"/"MARI" + { + ND_INS_VEXTRACTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 907, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_u, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1493 Instruction:"VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3B /r ib"/"MARI" + { + ND_INS_VEXTRACTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 908, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_qq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1494 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" + { + ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 909, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1495 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" + { + ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 909, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1496 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" + { + ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 909, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1497 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" + { + ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 909, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1498 Instruction:"VFIXUPIMMPD Vn{K}{z},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x54 /r ib"/"RAVMI" + { + ND_INS_VFIXUPIMMPD, ND_CAT_AVX512, ND_SET_AVX512F, 910, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1499 Instruction:"VFIXUPIMMPS Vn{K}{z},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x54 /r ib"/"RAVMI" + { + ND_INS_VFIXUPIMMPS, ND_CAT_AVX512, ND_SET_AVX512F, 911, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1500 Instruction:"VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x55 /r ib"/"RAVMI" + { + ND_INS_VFIXUPIMMSD, ND_CAT_AVX512, ND_SET_AVX512F, 912, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1501 Instruction:"VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x55 /r ib"/"RAVMI" + { + ND_INS_VFIXUPIMMSS, ND_CAT_AVX512, ND_SET_AVX512F, 913, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1502 Instruction:"VFMADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x98 /r"/"RAVM" + { + ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 914, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1503 Instruction:"VFMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x98 /r"/"RVM" + { + ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 914, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1504 Instruction:"VFMADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x98 /r"/"RAVM" + { + ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 915, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1505 Instruction:"VFMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x98 /r"/"RVM" + { + ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 915, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1506 Instruction:"VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x99 /r"/"RAVM" + { + ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 916, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1507 Instruction:"VFMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:x w:1 0x99 /r"/"RVM" + { + ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 916, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1508 Instruction:"VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x99 /r"/"RAVM" + { + ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 917, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1509 Instruction:"VFMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x99 /r"/"RVM" + { + ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 917, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1510 Instruction:"VFMADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA8 /r"/"RAVM" + { + ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 918, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1511 Instruction:"VFMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA8 /r"/"RVM" + { + ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 918, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1512 Instruction:"VFMADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA8 /r"/"RAVM" + { + ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 919, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1513 Instruction:"VFMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA8 /r"/"RVM" + { + ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 919, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1514 Instruction:"VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xA9 /r"/"RAVM" + { + ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 920, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1515 Instruction:"VFMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:0 w:1 0xA9 /r"/"RVM" + { + ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 920, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1516 Instruction:"VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xA9 /r"/"RAVM" + { + ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 921, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1517 Instruction:"VFMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:0 w:0 0xA9 /r"/"RVM" + { + ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 921, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1518 Instruction:"VFMADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB8 /r"/"RAVM" + { + ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 922, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1519 Instruction:"VFMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB8 /r"/"RVM" + { + ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 922, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1520 Instruction:"VFMADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB8 /r"/"RAVM" + { + ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 923, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1521 Instruction:"VFMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB8 /r"/"RVM" + { + ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 923, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1522 Instruction:"VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xB9 /r"/"RAVM" + { + ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 924, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1523 Instruction:"VFMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:0 w:1 0xB9 /r"/"RVM" + { + ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 924, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1524 Instruction:"VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xB9 /r"/"RAVM" + { + ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 925, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1525 Instruction:"VFMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:0 w:0 0xB9 /r"/"RVM" + { + ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 925, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1526 Instruction:"VFMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x69 /r is4"/"RVML" + { + ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 926, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1527 Instruction:"VFMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x69 /r is4"/"RVLM" + { + ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 926, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1528 Instruction:"VFMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x68 /r is4"/"RVML" + { + ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 927, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1529 Instruction:"VFMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x68 /r is4"/"RVLM" + { + ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 927, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1530 Instruction:"VFMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6B /r is4"/"RVML" + { + ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 928, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1531 Instruction:"VFMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6B /r is4"/"RVLM" + { + ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 928, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1532 Instruction:"VFMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6A /r is4"/"RVML" + { + ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 929, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1533 Instruction:"VFMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6A /r is4"/"RVLM" + { + ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 929, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1534 Instruction:"VFMADDSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x96 /r"/"RAVM" + { + ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 930, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1535 Instruction:"VFMADDSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x96 /r"/"RVM" + { + ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 930, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1536 Instruction:"VFMADDSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x96 /r"/"RAVM" + { + ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 931, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1537 Instruction:"VFMADDSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x96 /r"/"RVM" + { + ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 931, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1538 Instruction:"VFMADDSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA6 /r"/"RAVM" + { + ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 932, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1539 Instruction:"VFMADDSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA6 /r"/"RVM" + { + ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 932, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1540 Instruction:"VFMADDSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA6 /r"/"RAVM" + { + ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 933, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1541 Instruction:"VFMADDSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA6 /r"/"RVM" + { + ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 933, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1542 Instruction:"VFMADDSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB6 /r"/"RAVM" + { + ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 934, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1543 Instruction:"VFMADDSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB6 /r"/"RVM" + { + ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 934, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1544 Instruction:"VFMADDSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB6 /r"/"RAVM" + { + ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 935, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1545 Instruction:"VFMADDSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB6 /r"/"RVM" + { + ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 935, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1546 Instruction:"VFMADDSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5D /r is4"/"RVML" + { + ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 936, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1547 Instruction:"VFMADDSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5D /r is4"/"RVLM" + { + ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 936, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1548 Instruction:"VFMADDSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5C /r is4"/"RVML" + { + ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 937, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1549 Instruction:"VFMADDSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5C /r is4"/"RVLM" + { + ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 937, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1550 Instruction:"VFMSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9A /r"/"RAVM" + { + ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 938, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1551 Instruction:"VFMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9A /r"/"RVM" + { + ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 938, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1552 Instruction:"VFMSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9A /r"/"RAVM" + { + ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 939, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1553 Instruction:"VFMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9A /r"/"RVM" + { + ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 939, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1554 Instruction:"VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9B /r"/"RAVM" + { + ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 940, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1555 Instruction:"VFMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:x w:1 0x9B /r"/"RVM" + { + ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 940, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1556 Instruction:"VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9B /r"/"RAVM" + { + ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 941, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1557 Instruction:"VFMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x9B /r"/"RVM" + { + ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 941, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1558 Instruction:"VFMSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAA /r"/"RAVM" + { + ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 942, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1559 Instruction:"VFMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAA /r"/"RVM" + { + ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 942, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1560 Instruction:"VFMSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAA /r"/"RAVM" + { + ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 943, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1561 Instruction:"VFMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAA /r"/"RVM" + { + ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 943, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1562 Instruction:"VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAB /r"/"RAVM" + { + ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 944, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1563 Instruction:"VFMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:0 w:1 0xAB /r"/"RVM" + { + ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 944, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1564 Instruction:"VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAB /r"/"RAVM" + { + ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 945, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1565 Instruction:"VFMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:0 w:0 0xAB /r"/"RVM" + { + ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 945, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1566 Instruction:"VFMSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBA /r"/"RAVM" + { + ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 946, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1567 Instruction:"VFMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBA /r"/"RVM" + { + ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 946, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1568 Instruction:"VFMSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBA /r"/"RAVM" + { + ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 947, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1569 Instruction:"VFMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBA /r"/"RVM" + { + ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 947, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1570 Instruction:"VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBB /r"/"RAVM" + { + ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 948, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1571 Instruction:"VFMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:0 w:1 0xBB /r"/"RVM" + { + ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 948, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1572 Instruction:"VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBB /r"/"RAVM" + { + ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 949, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1573 Instruction:"VFMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:0 w:0 0xBB /r"/"RVM" + { + ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 949, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1574 Instruction:"VFMSUBADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x97 /r"/"RAVM" + { + ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 950, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1575 Instruction:"VFMSUBADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x97 /r"/"RVM" + { + ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_FMA, 950, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1576 Instruction:"VFMSUBADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x97 /r"/"RAVM" + { + ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 951, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1577 Instruction:"VFMSUBADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x97 /r"/"RVM" + { + ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_FMA, 951, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1578 Instruction:"VFMSUBADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA7 /r"/"RAVM" + { + ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 952, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1579 Instruction:"VFMSUBADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA7 /r"/"RVM" + { + ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_FMA, 952, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1580 Instruction:"VFMSUBADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA7 /r"/"RAVM" + { + ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 953, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1581 Instruction:"VFMSUBADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA7 /r"/"RVM" + { + ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_FMA, 953, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1582 Instruction:"VFMSUBADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB7 /r"/"RAVM" + { + ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 954, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1583 Instruction:"VFMSUBADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB7 /r"/"RVM" + { + ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_FMA, 954, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1584 Instruction:"VFMSUBADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB7 /r"/"RAVM" + { + ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 955, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1585 Instruction:"VFMSUBADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB7 /r"/"RVM" + { + ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_FMA, 955, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1586 Instruction:"VFMSUBADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5F /r is4"/"RVML" + { + ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 956, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1587 Instruction:"VFMSUBADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5F /r is4"/"RVLM" + { + ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 956, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1588 Instruction:"VFMSUBADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5E /r is4"/"RVML" + { + ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 957, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1589 Instruction:"VFMSUBADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5E /r is4"/"RVLM" + { + ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 957, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1590 Instruction:"VFMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6D /r is4"/"RVML" + { + ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 958, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1591 Instruction:"VFMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6D /r is4"/"RVLM" + { + ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 958, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1592 Instruction:"VFMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6C /r is4"/"RVML" + { + ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 959, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1593 Instruction:"VFMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6C /r is4"/"RVLM" + { + ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 959, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1594 Instruction:"VFMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6F /r is4"/"RVML" + { + ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 960, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1595 Instruction:"VFMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6F /r is4"/"RVLM" + { + ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 960, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1596 Instruction:"VFMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6E /r is4"/"RVML" + { + ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 961, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1597 Instruction:"VFMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6E /r is4"/"RVLM" + { + ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 961, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1598 Instruction:"VFNMADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9C /r"/"RAVM" + { + ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 962, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1599 Instruction:"VFNMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9C /r"/"RVM" + { + ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 962, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1600 Instruction:"VFNMADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9C /r"/"RAVM" + { + ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 963, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1601 Instruction:"VFNMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9C /r"/"RVM" + { + ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 963, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1602 Instruction:"VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9D /r"/"RAVM" + { + ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 964, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1603 Instruction:"VFNMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9D /r"/"RVM" + { + ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 964, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1604 Instruction:"VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9D /r"/"RAVM" + { + ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 965, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1605 Instruction:"VFNMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9D /r"/"RVM" + { + ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 965, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1606 Instruction:"VFNMADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAC /r"/"RAVM" + { + ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 966, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1607 Instruction:"VFNMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAC /r"/"RVM" + { + ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 966, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1608 Instruction:"VFNMADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAC /r"/"RAVM" + { + ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 967, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1609 Instruction:"VFNMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAC /r"/"RVM" + { + ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 967, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1610 Instruction:"VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAD /r"/"RAVM" + { + ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 968, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1611 Instruction:"VFNMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:0 w:1 0xAD /r"/"RVM" + { + ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 968, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1612 Instruction:"VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAD /r"/"RAVM" + { + ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 969, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1613 Instruction:"VFNMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:0 w:0 0xAD /r"/"RVM" + { + ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 969, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1614 Instruction:"VFNMADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBC /r"/"RAVM" + { + ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 970, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1615 Instruction:"VFNMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBC /r"/"RVM" + { + ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 970, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1616 Instruction:"VFNMADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBC /r"/"RAVM" + { + ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 971, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1617 Instruction:"VFNMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBC /r"/"RVM" + { + ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 971, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1618 Instruction:"VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBD /r"/"RAVM" + { + ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 972, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1619 Instruction:"VFNMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:0 w:1 0xBD /r"/"RVM" + { + ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 972, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1620 Instruction:"VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBD /r"/"RAVM" + { + ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 973, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1621 Instruction:"VFNMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:0 w:0 0xBD /r"/"RVM" + { + ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 973, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1622 Instruction:"VFNMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x79 /r is4"/"RVML" + { + ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 974, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1623 Instruction:"VFNMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x79 /r is4"/"RVLM" + { + ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 974, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1624 Instruction:"VFNMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x78 /r is4"/"RVML" + { + ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 975, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1625 Instruction:"VFNMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x78 /r is4"/"RVLM" + { + ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 975, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1626 Instruction:"VFNMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7B /r is4"/"RVML" + { + ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 976, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1627 Instruction:"VFNMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7B /r is4"/"RVLM" + { + ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 976, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1628 Instruction:"VFNMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7A /r is4"/"RVML" + { + ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 977, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1629 Instruction:"VFNMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7A /r is4"/"RVLM" + { + ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 977, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1630 Instruction:"VFNMSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9E /r"/"RAVM" + { + ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 978, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1631 Instruction:"VFNMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9E /r"/"RVM" + { + ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 978, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1632 Instruction:"VFNMSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9E /r"/"RAVM" + { + ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 979, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1633 Instruction:"VFNMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9E /r"/"RVM" + { + ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 979, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1634 Instruction:"VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9F /r"/"RAVM" + { + ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 980, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1635 Instruction:"VFNMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:0 w:1 0x9F /r"/"RVM" + { + ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 980, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1636 Instruction:"VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9F /r"/"RAVM" + { + ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 981, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1637 Instruction:"VFNMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:0 w:0 0x9F /r"/"RVM" + { + ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 981, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1638 Instruction:"VFNMSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAE /r"/"RAVM" + { + ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 982, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1639 Instruction:"VFNMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAE /r"/"RVM" + { + ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 982, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1640 Instruction:"VFNMSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAE /r"/"RAVM" + { + ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 983, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1641 Instruction:"VFNMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAE /r"/"RVM" + { + ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 983, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1642 Instruction:"VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAF /r"/"RAVM" + { + ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 984, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1643 Instruction:"VFNMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:0 w:1 0xAF /r"/"RVM" + { + ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 984, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1644 Instruction:"VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAF /r"/"RAVM" + { + ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 985, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1645 Instruction:"VFNMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:0 w:0 0xAF /r"/"RVM" + { + ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 985, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1646 Instruction:"VFNMSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBE /r"/"RAVM" + { + ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 986, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1647 Instruction:"VFNMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBE /r"/"RVM" + { + ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 986, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1648 Instruction:"VFNMSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBE /r"/"RAVM" + { + ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 987, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1649 Instruction:"VFNMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBE /r"/"RVM" + { + ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 987, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1650 Instruction:"VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBF /r"/"RAVM" + { + ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 988, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1651 Instruction:"VFNMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:0 w:1 0xBF /r"/"RVM" + { + ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 988, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1652 Instruction:"VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBF /r"/"RAVM" + { + ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 989, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1653 Instruction:"VFNMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:0 w:0 0xBF /r"/"RVM" + { + ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 989, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1654 Instruction:"VFNMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7D /r is4"/"RVML" + { + ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 990, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1655 Instruction:"VFNMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7D /r is4"/"RVLM" + { + ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 990, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1656 Instruction:"VFNMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7C /r is4"/"RVML" + { + ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 991, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1657 Instruction:"VFNMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7C /r is4"/"RVLM" + { + ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 991, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1658 Instruction:"VFNMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7F /r is4"/"RVML" + { + ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 992, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1659 Instruction:"VFNMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7F /r is4"/"RVLM" + { + ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 992, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1660 Instruction:"VFNMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7E /r is4"/"RVML" + { + ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 993, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1661 Instruction:"VFNMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7E /r is4"/"RVLM" + { + ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 993, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1662 Instruction:"VFPCLASSPD rKq{K},aKq,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x66 /r ib"/"RAMI" + { + ND_INS_VFPCLASSPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 994, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1663 Instruction:"VFPCLASSPS rKq{K},aKq,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x66 /r ib"/"RAMI" + { + ND_INS_VFPCLASSPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 995, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1664 Instruction:"VFPCLASSSD rKq{K},aKq,Wsd,Ib" Encoding:"evex m:3 p:1 l:i w:1 0x67 /r ib"/"RAMI" + { + ND_INS_VFPCLASSSD, ND_CAT_AVX512, ND_SET_AVX512DQ, 996, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1665 Instruction:"VFPCLASSSS rKq{K},aKq,Wss,Ib" Encoding:"evex m:3 p:1 l:i w:0 0x67 /r ib"/"RAMI" + { + ND_INS_VFPCLASSSS, ND_CAT_AVX512, ND_SET_AVX512DQ, 997, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1666 Instruction:"VFRCZPD Vx,Wx" Encoding:"xop m:9 0x81 /r"/"RM" + { + ND_INS_VFRCZPD, ND_CAT_XOP, ND_SET_XOP, 998, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1667 Instruction:"VFRCZPS Vx,Wx" Encoding:"xop m:9 0x80 /r"/"RM" + { + ND_INS_VFRCZPS, ND_CAT_XOP, ND_SET_XOP, 999, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1668 Instruction:"VFRCZSD Vdq,Wsd" Encoding:"xop m:9 0x83 /r"/"RM" + { + ND_INS_VFRCZSD, ND_CAT_XOP, ND_SET_XOP, 1000, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1669 Instruction:"VFRCZSS Vdq,Wss" Encoding:"xop m:9 0x82 /r"/"RM" + { + ND_INS_VFRCZSS, ND_CAT_XOP, ND_SET_XOP, 1001, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1670 Instruction:"VGATHERDPD Vn{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RAM" + { + ND_INS_VGATHERDPD, ND_CAT_GATHER, ND_SET_AVX512F, 1002, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_vm32h, ND_OPF_RW, 0, 0), + }, + + // Pos:1671 Instruction:"VGATHERDPD Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RMV" + { + ND_INS_VGATHERDPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1002, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_CRW, 0, 0), + OP(ND_OPT_M, ND_OPS_vm32h, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_RW, 0, 0), + }, + + // Pos:1672 Instruction:"VGATHERDPS Vn{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RAM" + { + ND_INS_VGATHERDPS, ND_CAT_GATHER, ND_SET_AVX512F, 1003, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_vm32n, ND_OPF_RW, 0, 0), + }, + + // Pos:1673 Instruction:"VGATHERDPS Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RMV" + { + ND_INS_VGATHERDPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1003, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_CRW, 0, 0), + OP(ND_OPT_M, ND_OPS_vm32n, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_RW, 0, 0), + }, + + // Pos:1674 Instruction:"VGATHERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /1:mem vsib"/"MA" + { + ND_INS_VGATHERPF0DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1004, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_vm32h, ND_OPF_R, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1675 Instruction:"VGATHERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /1:mem vsib"/"MA" + { + ND_INS_VGATHERPF0DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1005, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_vm32n, ND_OPF_R, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1676 Instruction:"VGATHERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /1:mem vsib"/"MA" + { + ND_INS_VGATHERPF0QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1006, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_vm64n, ND_OPF_R, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1677 Instruction:"VGATHERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /1:mem vsib"/"MA" + { + ND_INS_VGATHERPF0QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1007, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_vm64n, ND_OPF_R, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1678 Instruction:"VGATHERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /2:mem vsib"/"MA" + { + ND_INS_VGATHERPF1DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1008, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_vm32h, ND_OPF_R, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1679 Instruction:"VGATHERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /2:mem vsib"/"MA" + { + ND_INS_VGATHERPF1DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1009, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_vm32n, ND_OPF_R, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1680 Instruction:"VGATHERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /2:mem vsib"/"MA" + { + ND_INS_VGATHERPF1QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1010, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_vm64n, ND_OPF_R, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1681 Instruction:"VGATHERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /2:mem vsib"/"MA" + { + ND_INS_VGATHERPF1QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1011, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_vm64n, ND_OPF_R, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1682 Instruction:"VGATHERQPD Vn{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RAM" + { + ND_INS_VGATHERQPD, ND_CAT_GATHER, ND_SET_AVX512F, 1012, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_vm64n, ND_OPF_RW, 0, 0), + }, + + // Pos:1683 Instruction:"VGATHERQPD Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RMV" + { + ND_INS_VGATHERQPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1012, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_CRW, 0, 0), + OP(ND_OPT_M, ND_OPS_vm64n, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_RW, 0, 0), + }, + + // Pos:1684 Instruction:"VGATHERQPS Vh{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RAM" + { + ND_INS_VGATHERQPS, ND_CAT_GATHER, ND_SET_AVX512F, 1013, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_h, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_vm64n, ND_OPF_RW, 0, 0), + }, + + // Pos:1685 Instruction:"VGATHERQPS Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RMV" + { + ND_INS_VGATHERQPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1013, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_CRW, 0, 0), + OP(ND_OPT_M, ND_OPS_vm64n, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_RW, 0, 0), + }, + + // Pos:1686 Instruction:"VGETEXPPD Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x42 /r"/"RAM" + { + ND_INS_VGETEXPPD, ND_CAT_AVX512, ND_SET_AVX512F, 1014, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), + }, + + // Pos:1687 Instruction:"VGETEXPPS Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x42 /r"/"RAM" + { + ND_INS_VGETEXPPS, ND_CAT_AVX512, ND_SET_AVX512F, 1015, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + + // Pos:1688 Instruction:"VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x43 /r"/"RAVM" + { + ND_INS_VGETEXPSD, ND_CAT_AVX512, ND_SET_AVX512F, 1016, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_SAE, 0), + }, + + // Pos:1689 Instruction:"VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x43 /r"/"RAVM" + { + ND_INS_VGETEXPSS, ND_CAT_AVX512, ND_SET_AVX512F, 1017, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_SAE, 0), + }, + + // Pos:1690 Instruction:"VGETMANTPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x26 /r ib"/"RAMI" + { + ND_INS_VGETMANTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1018, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1691 Instruction:"VGETMANTPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x26 /r ib"/"RAMI" + { + ND_INS_VGETMANTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1019, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1692 Instruction:"VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x27 /r ib"/"RAVMI" + { + ND_INS_VGETMANTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1020, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1693 Instruction:"VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x27 /r ib"/"RAVMI" + { + ND_INS_VGETMANTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1021, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1694 Instruction:"VGF2P8AFFINEINVQB Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCF /r ib"/"RAVMI" + { + ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1022, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1695 Instruction:"VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCF /r ib"/"RVMI" + { + ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1022, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1696 Instruction:"VGF2P8AFFINEQB Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCE /r ib"/"RAVMI" + { + ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1023, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1697 Instruction:"VGF2P8AFFINEQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCE /r ib"/"RVMI" + { + ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1023, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1698 Instruction:"VGF2P8MULB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0xCF /r"/"RAVM" + { + ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1024, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1699 Instruction:"VGF2P8MULB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xCF /r"/"RVM" + { + ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1024, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1700 Instruction:"VHADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7C /r"/"RVM" + { + ND_INS_VHADDPD, ND_CAT_AVX, ND_SET_AVX, 1025, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:1701 Instruction:"VHADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7C /r"/"RVM" + { + ND_INS_VHADDPS, ND_CAT_AVX, ND_SET_AVX, 1026, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1702 Instruction:"VHSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7D /r"/"RVM" + { + ND_INS_VHSUBPD, ND_CAT_AVX, ND_SET_AVX, 1027, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:1703 Instruction:"VHSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7D /r"/"RVM" + { + ND_INS_VHSUBPS, ND_CAT_AVX, ND_SET_AVX, 1028, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1704 Instruction:"VINSERTF128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x18 /r ib"/"RVMI" + { + ND_INS_VINSERTF128, ND_CAT_AVX, ND_SET_AVX, 1029, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_qq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1705 Instruction:"VINSERTF32X4 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x18 /r ib"/"RAVMI" + { + ND_INS_VINSERTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1030, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_u, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_u, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1706 Instruction:"VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1A /r ib"/"RAVMI" + { + ND_INS_VINSERTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1031, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_oq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1707 Instruction:"VINSERTF64X2 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x18 /r ib"/"RAVMI" + { + ND_INS_VINSERTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1032, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_u, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_u, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1708 Instruction:"VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1A /r ib"/"RAVMI" + { + ND_INS_VINSERTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1033, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_oq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1709 Instruction:"VINSERTI128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x38 /r ib"/"RVMI" + { + ND_INS_VINSERTI128, ND_CAT_AVX2, ND_SET_AVX2, 1034, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_qq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1710 Instruction:"VINSERTI32X4 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x38 /r ib"/"RAVMI" + { + ND_INS_VINSERTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1035, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_u, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_u, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1711 Instruction:"VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3A /r ib"/"RAVMI" + { + ND_INS_VINSERTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1036, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_oq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1712 Instruction:"VINSERTI64X2 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x38 /r ib"/"RAVMI" + { + ND_INS_VINSERTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1037, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_u, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_u, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1713 Instruction:"VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3A /r ib"/"RAVMI" + { + ND_INS_VINSERTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1038, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_oq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1714 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI" + { + ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1039, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1715 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI" + { + ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1039, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1716 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI" + { + ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1039, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1717 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI" + { + ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1039, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1718 Instruction:"VLDDQU Vx,Mx" Encoding:"vex m:1 p:3 l:x w:i 0xF0 /r:mem"/"RM" + { + ND_INS_VLDDQU, ND_CAT_AVX, ND_SET_AVX, 1040, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1719 Instruction:"VLDMXCSR Md" Encoding:"vex m:1 p:0 0xAE /2:mem"/"M" + { + ND_INS_VLDMXCSR, ND_CAT_AVX, ND_SET_AVX, 1041, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(1, 1), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1720 Instruction:"VMASKMOVDQU Vdq,Udq" Encoding:"vex m:1 p:1 l:0 w:i 0xF7 /r:reg"/"RM" + { + ND_INS_VMASKMOVDQU, ND_CAT_AVX, ND_SET_AVX, 1042, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_MEM_rDI, ND_OPS_dq, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1721 Instruction:"VMASKMOVPD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2D /r:mem"/"RVM" + { + ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1043, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1722 Instruction:"VMASKMOVPD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2F /r:mem"/"MVR" + { + ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1043, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1723 Instruction:"VMASKMOVPS Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2C /r:mem"/"RVM" + { + ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1044, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1724 Instruction:"VMASKMOVPS Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2E /r:mem"/"MVR" + { + ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1044, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1725 Instruction:"VMAXPD Vn{K}{z},aKq,Hn,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5F /r"/"RAVM" + { + ND_INS_VMAXPD, ND_CAT_AVX512, ND_SET_AVX512F, 1045, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), + }, + + // Pos:1726 Instruction:"VMAXPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5F /r"/"RVM" + { + ND_INS_VMAXPD, ND_CAT_AVX, ND_SET_AVX, 1045, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:1727 Instruction:"VMAXPS Vn{K}{z},aKq,Hn,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5F /r"/"RAVM" + { + ND_INS_VMAXPS, ND_CAT_AVX512, ND_SET_AVX512F, 1046, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + + // Pos:1728 Instruction:"VMAXPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5F /r"/"RVM" + { + ND_INS_VMAXPS, ND_CAT_AVX, ND_SET_AVX, 1046, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1729 Instruction:"VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5F /r"/"RAVM" + { + ND_INS_VMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1047, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_SAE, 0), + }, + + // Pos:1730 Instruction:"VMAXSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5F /r"/"RVM" + { + ND_INS_VMAXSD, ND_CAT_AVX, ND_SET_AVX, 1047, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1731 Instruction:"VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5F /r"/"RAVM" + { + ND_INS_VMAXSS, ND_CAT_AVX512, ND_SET_AVX512F, 1048, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_SAE, 0), + }, + + // Pos:1732 Instruction:"VMAXSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5F /r"/"RVM" + { + ND_INS_VMAXSS, ND_CAT_AVX, ND_SET_AVX, 1048, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1733 Instruction:"VMCALL" Encoding:"0x0F 0x01 /0xC1"/"" + { + ND_INS_VMCALL, ND_CAT_VTX, ND_SET_VTX, 1049, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, + 0, + 0, + 0, + 0, + }, + + // Pos:1734 Instruction:"VMCLEAR Mq" Encoding:"0x66 0x0F 0xC7 /6:mem"/"M" + { + ND_INS_VMCLEAR, ND_CAT_VTX, ND_SET_VTX, 1050, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1735 Instruction:"VMFUNC" Encoding:"NP 0x0F 0x01 /0xD4"/"" + { + ND_INS_VMFUNC, ND_CAT_VTX, ND_SET_VTX, 1051, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, + 0, + 0, + 0, + 0, + }, + + // Pos:1736 Instruction:"VMGEXIT" Encoding:"0xF3 0x0F 0x01 /0xD9"/"" + { + ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1052, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, + 0, + 0, + 0, + 0, + }, + + // Pos:1737 Instruction:"VMGEXIT" Encoding:"0xF2 0x0F 0x01 /0xD9"/"" + { + ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1052, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, + 0, + 0, + 0, + 0, + }, + + // Pos:1738 Instruction:"VMINPD Vn{K}{z},aKq,Hn,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5D /r"/"RAVM" + { + ND_INS_VMINPD, ND_CAT_AVX512, ND_SET_AVX512F, 1053, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), + }, + + // Pos:1739 Instruction:"VMINPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5D /r"/"RVM" + { + ND_INS_VMINPD, ND_CAT_AVX, ND_SET_AVX, 1053, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:1740 Instruction:"VMINPS Vn{K}{z},aKq,Hn,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5D /r"/"RAVM" + { + ND_INS_VMINPS, ND_CAT_AVX512, ND_SET_AVX512F, 1054, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + + // Pos:1741 Instruction:"VMINPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5D /r"/"RVM" + { + ND_INS_VMINPS, ND_CAT_AVX, ND_SET_AVX, 1054, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1742 Instruction:"VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5D /r"/"RAVM" + { + ND_INS_VMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1055, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_SAE, 0), + }, + + // Pos:1743 Instruction:"VMINSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5D /r"/"RVM" + { + ND_INS_VMINSD, ND_CAT_AVX, ND_SET_AVX, 1055, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1744 Instruction:"VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5D /r"/"RAVM" + { + ND_INS_VMINSS, ND_CAT_AVX512, ND_SET_AVX512F, 1056, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_SAE, 0), + }, + + // Pos:1745 Instruction:"VMINSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5D /r"/"RVM" + { + ND_INS_VMINSS, ND_CAT_AVX, ND_SET_AVX, 1056, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1746 Instruction:"VMLAUNCH" Encoding:"0x0F 0x01 /0xC2"/"" + { + ND_INS_VMLAUNCH, ND_CAT_VTX, ND_SET_VTX, 1057, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1747 Instruction:"VMLOAD" Encoding:"0x0F 0x01 /0xDA"/"" + { + ND_INS_VMLOAD, ND_CAT_SYSTEM, ND_SET_SVM, 1058, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1748 Instruction:"VMMCALL" Encoding:"0x0F 0x01 /0xD9"/"" + { + ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1059, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, + 0, + 0, + 0, + 0, + }, + + // Pos:1749 Instruction:"VMOVAPD Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x28 /r"/"RAM" + { + ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1060, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1750 Instruction:"VMOVAPD Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x29 /r"/"MAR" + { + ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1060, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1751 Instruction:"VMOVAPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x28 /r"/"RM" + { + ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1060, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1752 Instruction:"VMOVAPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x29 /r"/"MR" + { + ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1060, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1753 Instruction:"VMOVAPS Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:0 l:x w:0 0x28 /r"/"RAM" + { + ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1061, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1754 Instruction:"VMOVAPS Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x29 /r"/"MAR" + { + ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1061, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1755 Instruction:"VMOVAPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x28 /r"/"RM" + { + ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1061, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1756 Instruction:"VMOVAPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x29 /r"/"MR" + { + ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1061, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1757 Instruction:"VMOVD Vdq,Ed" Encoding:"evex m:1 p:1 l:0 w:0 0x6E /r"/"RM" + { + ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1062, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:1758 Instruction:"VMOVD Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:0 0x7E /r"/"MR" + { + ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1062, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1759 Instruction:"VMOVD Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:0 0x6E /r"/"RM" + { + ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1062, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1760 Instruction:"VMOVD Ey,Vd" Encoding:"vex m:1 p:1 l:0 w:0 0x7E /r"/"MR" + { + ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1062, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:1761 Instruction:"VMOVDDUP Vdq{K}{z},aKq,Wq" Encoding:"evex m:1 p:3 l:0 w:1 0x12 /r"/"RAM" + { + ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1063, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1762 Instruction:"VMOVDDUP Vqq{K}{z},aKq,Wqq" Encoding:"evex m:1 p:3 l:1 w:1 0x12 /r"/"RAM" + { + ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1063, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qq, ND_OPF_R, 0, 0), + }, + + // Pos:1763 Instruction:"VMOVDDUP Voq{K}{z},aKq,Woq" Encoding:"evex m:1 p:3 l:2 w:1 0x12 /r"/"RAM" + { + ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1063, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_oq, ND_OPF_R, 0, 0), + }, + + // Pos:1764 Instruction:"VMOVDDUP Vdq,Wq" Encoding:"vex m:1 p:3 l:0 w:i 0x12 /r"/"RM" + { + ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1063, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1765 Instruction:"VMOVDDUP Vqq,Wqq" Encoding:"vex m:1 p:3 l:1 w:i 0x12 /r"/"RM" + { + ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1063, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_qq, ND_OPF_R, 0, 0), + }, + + // Pos:1766 Instruction:"VMOVDQA Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6F /r"/"RM" + { + ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1064, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1767 Instruction:"VMOVDQA Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x7F /r"/"MR" + { + ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1064, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1768 Instruction:"VMOVDQA32 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:0 0x6F /r"/"RAM" + { + ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1065, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1769 Instruction:"VMOVDQA32 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:0 0x7F /r"/"MAR" + { + ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1065, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1770 Instruction:"VMOVDQA64 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x6F /r"/"RAM" + { + ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1066, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1771 Instruction:"VMOVDQA64 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x7F /r"/"MAR" + { + ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1066, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1772 Instruction:"VMOVDQU Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x6F /r"/"RM" + { + ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1067, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1773 Instruction:"VMOVDQU Wx,Vx" Encoding:"vex m:1 p:2 l:x w:i 0x7F /r"/"MR" + { + ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1067, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1774 Instruction:"VMOVDQU16 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:3 l:x w:1 0x6F /r"/"RAM" + { + ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1068, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1775 Instruction:"VMOVDQU16 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:3 l:x w:1 0x7F /r"/"MAR" + { + ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1068, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1776 Instruction:"VMOVDQU32 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x6F /r"/"RAM" + { + ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1069, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1777 Instruction:"VMOVDQU32 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:2 l:x w:0 0x7F /r"/"MAR" + { + ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1069, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1778 Instruction:"VMOVDQU64 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:1 0x6F /r"/"RAM" + { + ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1070, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1779 Instruction:"VMOVDQU64 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:2 l:x w:1 0x7F /r"/"MAR" + { + ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1070, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1780 Instruction:"VMOVDQU8 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:3 l:x w:0 0x6F /r"/"RAM" + { + ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1071, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1781 Instruction:"VMOVDQU8 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:3 l:x w:0 0x7F /r"/"MAR" + { + ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1071, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1782 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:reg"/"RVM" + { + ND_INS_VMOVHLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1072, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1783 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:reg"/"RVM" + { + ND_INS_VMOVHLPS, ND_CAT_AVX, ND_SET_AVX, 1072, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1784 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x16 /r:mem"/"RVM" + { + ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1073, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1785 Instruction:"VMOVHPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x17 /r:mem"/"MR" + { + ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1073, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1786 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x16 /r:mem"/"RVM" + { + ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1073, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1787 Instruction:"VMOVHPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x17 /r:mem"/"MR" + { + ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1073, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1788 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:mem"/"RVM" + { + ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1074, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1789 Instruction:"VMOVHPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x17 /r:mem"/"MR" + { + ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1074, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1790 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:mem"/"RVM" + { + ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1074, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1791 Instruction:"VMOVHPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x17 /r:mem"/"MR" + { + ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1074, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1792 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:reg"/"RVM" + { + ND_INS_VMOVLHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1075, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1793 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:reg"/"RVM" + { + ND_INS_VMOVLHPS, ND_CAT_AVX, ND_SET_AVX, 1075, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1794 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x12 /r:mem"/"RVM" + { + ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1076, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1795 Instruction:"VMOVLPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x13 /r:mem"/"MR" + { + ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1076, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1796 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x12 /r:mem"/"RVM" + { + ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1076, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1797 Instruction:"VMOVLPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x13 /r:mem"/"MR" + { + ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1076, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1798 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:mem"/"RVM" + { + ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1077, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1799 Instruction:"VMOVLPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x13 /r:mem"/"MR" + { + ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1077, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1800 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:mem"/"RVM" + { + ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1077, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1801 Instruction:"VMOVLPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x13 /r:mem"/"MR" + { + ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1077, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1802 Instruction:"VMOVMSKPD Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0x50 /r:reg"/"RM" + { + ND_INS_VMOVMSKPD, ND_CAT_DATAXFER, ND_SET_AVX, 1078, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1803 Instruction:"VMOVMSKPS Gy,Ux" Encoding:"vex m:1 p:0 l:x w:i 0x50 /r:reg"/"RM" + { + ND_INS_VMOVMSKPS, ND_CAT_DATAXFER, ND_SET_AVX, 1079, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1804 Instruction:"VMOVNTDQ Mn,Vn" Encoding:"evex m:1 p:1 l:x w:0 0xE7 /r:mem"/"MR" + { + ND_INS_VMOVNTDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1080, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_n, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1805 Instruction:"VMOVNTDQ Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0xE7 /r:mem"/"MR" + { + ND_INS_VMOVNTDQ, ND_CAT_AVX, ND_SET_AVX, 1080, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1806 Instruction:"VMOVNTDQA Vn,Mn" Encoding:"evex m:2 p:1 l:x w:0 0x2A /r:mem"/"RM" + { + ND_INS_VMOVNTDQA, ND_CAT_DATAXFER, ND_SET_AVX512F, 1081, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1807 Instruction:"VMOVNTDQA Vx,Mx" Encoding:"vex m:2 p:1 l:x w:i 0x2A /r:mem"/"RM" + { + ND_INS_VMOVNTDQA, ND_CAT_AVX, ND_SET_AVX, 1081, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1808 Instruction:"VMOVNTPD Mn,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x2B /r:mem"/"MR" + { + ND_INS_VMOVNTPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1082, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_n, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1809 Instruction:"VMOVNTPD Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x2B /r:mem"/"MR" + { + ND_INS_VMOVNTPD, ND_CAT_AVX, ND_SET_AVX, 1082, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1810 Instruction:"VMOVNTPS Mn,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x2B /r:mem"/"MR" + { + ND_INS_VMOVNTPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1083, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_n, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1811 Instruction:"VMOVNTPS Mx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x2B /r:mem"/"MR" + { + ND_INS_VMOVNTPS, ND_CAT_AVX, ND_SET_AVX, 1083, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1812 Instruction:"VMOVQ Vdq,Eq" Encoding:"evex m:1 p:1 l:0 w:1 0x6E /r"/"RM" + { + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1084, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1813 Instruction:"VMOVQ Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x7E /r"/"MR" + { + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1084, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1814 Instruction:"VMOVQ Vdq,Wq" Encoding:"evex m:1 p:2 l:0 w:1 0x7E /r"/"RM" + { + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1084, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1815 Instruction:"VMOVQ Wq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0xD6 /r"/"MR" + { + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1084, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1816 Instruction:"VMOVQ Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:1 0x6E /r"/"RM" + { + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1084, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1817 Instruction:"VMOVQ Ey,Vq" Encoding:"vex m:1 p:1 l:0 w:1 0x7E /r"/"MR" + { + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1084, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1818 Instruction:"VMOVQ Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0x7E /r"/"RM" + { + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1084, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1819 Instruction:"VMOVQ Wq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0xD6 /r"/"MR" + { + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1084, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1820 Instruction:"VMOVSD Vdq{K}{z},aKq,Msd" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:mem"/"RAM" + { + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1085, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1821 Instruction:"VMOVSD Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:reg"/"RAVM" + { + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1085, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1822 Instruction:"VMOVSD Msd{K},aKq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:mem"/"MAR" + { + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1085, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_sd, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1823 Instruction:"VMOVSD Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:reg"/"MAVR" + { + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1085, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_U, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1824 Instruction:"VMOVSD Vdq,Hdq,Usd" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:reg"/"RVM" + { + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1085, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_U, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1825 Instruction:"VMOVSD Vdq,Mq" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:mem"/"RM" + { + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1085, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1826 Instruction:"VMOVSD Usd,Hsd,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:reg"/"MVR" + { + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1085, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_U, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1827 Instruction:"VMOVSD Mq,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:mem"/"MR" + { + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1085, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1828 Instruction:"VMOVSHDUP Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x16 /r"/"RAM" + { + ND_INS_VMOVSHDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1086, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1829 Instruction:"VMOVSHDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x16 /r"/"RM" + { + ND_INS_VMOVSHDUP, ND_CAT_AVX, ND_SET_AVX, 1086, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1830 Instruction:"VMOVSLDUP Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x12 /r"/"RAM" + { + ND_INS_VMOVSLDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1087, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1831 Instruction:"VMOVSLDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x12 /r"/"RM" + { + ND_INS_VMOVSLDUP, ND_CAT_AVX, ND_SET_AVX, 1087, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1832 Instruction:"VMOVSS Vdq{K}{z},aKq,Mss" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:mem"/"RAM" + { + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1088, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1833 Instruction:"VMOVSS Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:reg"/"RAVM" + { + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1088, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1834 Instruction:"VMOVSS Mss{K},aKq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:mem"/"MAR" + { + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1088, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_ss, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1835 Instruction:"VMOVSS Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:reg"/"MAVR" + { + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1088, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_U, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1836 Instruction:"VMOVSS Vdq,Hdq,Uss" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:reg"/"RVM" + { + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1088, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_U, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1837 Instruction:"VMOVSS Vdq,Md" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:mem"/"RM" + { + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1088, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:1838 Instruction:"VMOVSS Uss,Hss,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:reg"/"MVR" + { + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1088, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_U, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1839 Instruction:"VMOVSS Md,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:mem"/"MR" + { + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1088, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1840 Instruction:"VMOVUPD Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x10 /r"/"RAM" + { + ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1089, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1841 Instruction:"VMOVUPD Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x11 /r"/"MAR" + { + ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1089, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1842 Instruction:"VMOVUPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x10 /r"/"RM" + { + ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1089, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1843 Instruction:"VMOVUPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x11 /r"/"MR" + { + ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1089, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1844 Instruction:"VMOVUPS Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:0 l:x w:0 0x10 /r"/"RAM" + { + ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1090, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1845 Instruction:"VMOVUPS Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x11 /r"/"MAR" + { + ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1090, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1846 Instruction:"VMOVUPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x10 /r"/"RM" + { + ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1090, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1847 Instruction:"VMOVUPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x11 /r"/"MR" + { + ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1090, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1848 Instruction:"VMPSADBW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x42 /r ib"/"RVMI" + { + ND_INS_VMPSADBW, ND_CAT_AVX, ND_SET_AVX, 1091, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1849 Instruction:"VMPTRLD Mq" Encoding:"NP 0x0F 0xC7 /6:mem"/"M" + { + ND_INS_VMPTRLD, ND_CAT_VTX, ND_SET_VTX, 1092, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1850 Instruction:"VMPTRST Mq" Encoding:"NP 0x0F 0xC7 /7:mem"/"M" + { + ND_INS_VMPTRST, ND_CAT_VTX, ND_SET_VTX, 1093, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1851 Instruction:"VMREAD Ey,Gy" Encoding:"NP 0x0F 0x78 /r"/"MR" + { + ND_INS_VMREAD, ND_CAT_VTX, ND_SET_VTX, 1094, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_VTX, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1852 Instruction:"VMRESUME" Encoding:"0x0F 0x01 /0xC3"/"" + { + ND_INS_VMRESUME, ND_CAT_VTX, ND_SET_VTX, 1095, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1853 Instruction:"VMRUN" Encoding:"0x0F 0x01 /0xD8"/"" + { + ND_INS_VMRUN, ND_CAT_SYSTEM, ND_SET_SVM, 1096, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1854 Instruction:"VMSAVE" Encoding:"0x0F 0x01 /0xDB"/"" + { + ND_INS_VMSAVE, ND_CAT_SYSTEM, ND_SET_SVM, 1097, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, + 0, + 0, + 0, + 0, + }, + + // Pos:1855 Instruction:"VMULPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x59 /r"/"RAVM" + { + ND_INS_VMULPD, ND_CAT_AVX512, ND_SET_AVX512F, 1098, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1856 Instruction:"VMULPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x59 /r"/"RVM" + { + ND_INS_VMULPD, ND_CAT_AVX, ND_SET_AVX, 1098, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:1857 Instruction:"VMULPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x59 /r"/"RAVM" + { + ND_INS_VMULPS, ND_CAT_AVX512, ND_SET_AVX512F, 1099, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1858 Instruction:"VMULPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x59 /r"/"RVM" + { + ND_INS_VMULPS, ND_CAT_AVX, ND_SET_AVX, 1099, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1859 Instruction:"VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x59 /r"/"RAVM" + { + ND_INS_VMULSD, ND_CAT_AVX512, ND_SET_AVX512F, 1100, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1860 Instruction:"VMULSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x59 /r"/"RVM" + { + ND_INS_VMULSD, ND_CAT_AVX, ND_SET_AVX, 1100, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1861 Instruction:"VMULSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x59 /r"/"RAVM" + { + ND_INS_VMULSS, ND_CAT_AVX512, ND_SET_AVX512F, 1101, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1862 Instruction:"VMULSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x59 /r"/"RVM" + { + ND_INS_VMULSS, ND_CAT_AVX, ND_SET_AVX, 1101, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1863 Instruction:"VMWRITE Gy,Ey" Encoding:"NP 0x0F 0x79 /r"/"RM" + { + ND_INS_VMWRITE, ND_CAT_VTX, ND_SET_VTX, 1102, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_VTX, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1864 Instruction:"VMXOFF" Encoding:"0x0F 0x01 /0xC4"/"" + { + ND_INS_VMXOFF, ND_CAT_VTX, ND_SET_VTX, 1103, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1865 Instruction:"VMXON Mq" Encoding:"0xF3 0x0F 0xC7 /6:mem"/"M" + { + ND_INS_VMXON, ND_CAT_VTX, ND_SET_VTX, 1104, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1866 Instruction:"VORPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x56 /r"/"RAVM" + { + ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1105, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:1867 Instruction:"VORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x56 /r"/"RVM" + { + ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1105, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:1868 Instruction:"VORPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x56 /r"/"RAVM" + { + ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1106, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1869 Instruction:"VORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x56 /r"/"RVM" + { + ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1106, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1870 Instruction:"VP2INTERSECTD rKq+1,Hn,Wn|B32" Encoding:"evex m:2 p:3 l:x w:0 0x68 /r"/"RVM" + { + ND_INS_VP2INTERSECTD, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1107, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VP2INTERSECT, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 2), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1871 Instruction:"VP2INTERSECTQ rKq+1,Hn,Wn|B64" Encoding:"evex m:2 p:3 l:x w:1 0x68 /r"/"RVM" + { + ND_INS_VP2INTERSECTQ, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1108, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VP2INTERSECT, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 2), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:1872 Instruction:"VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x52 /r:mem"/"RAVM" + { + ND_INS_VP4DPWSSD, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1109, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124VNNIW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_oq, ND_OPF_R, 0, 4), + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1873 Instruction:"VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x53 /r:mem"/"RAVM" + { + ND_INS_VP4DPWSSDS, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1110, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124VNNIW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_oq, ND_OPF_R, 0, 4), + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1874 Instruction:"VPABSB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:x 0x1C /r"/"RAM" + { + ND_INS_VPABSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1111, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1875 Instruction:"VPABSB Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1C /r"/"RM" + { + ND_INS_VPABSB, ND_CAT_AVX, ND_SET_AVX, 1111, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1876 Instruction:"VPABSD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x1E /r"/"RAM" + { + ND_INS_VPABSD, ND_CAT_AVX512, ND_SET_AVX512F, 1112, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1877 Instruction:"VPABSD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1E /r"/"RM" + { + ND_INS_VPABSD, ND_CAT_AVX, ND_SET_AVX, 1112, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1878 Instruction:"VPABSQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x1F /r"/"RAM" + { + ND_INS_VPABSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1113, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:1879 Instruction:"VPABSW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:x 0x1D /r"/"RAM" + { + ND_INS_VPABSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1114, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1880 Instruction:"VPABSW Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1D /r"/"RM" + { + ND_INS_VPABSW, ND_CAT_AVX, ND_SET_AVX, 1114, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1881 Instruction:"VPACKSSDW Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6B /r"/"RAVM" + { + ND_INS_VPACKSSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1115, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1882 Instruction:"VPACKSSDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6B /r"/"RVM" + { + ND_INS_VPACKSSDW, ND_CAT_AVX, ND_SET_AVX, 1115, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1883 Instruction:"VPACKSSWB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x63 /r"/"RAVM" + { + ND_INS_VPACKSSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1116, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1884 Instruction:"VPACKSSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x63 /r"/"RVM" + { + ND_INS_VPACKSSWB, ND_CAT_AVX, ND_SET_AVX, 1116, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1885 Instruction:"VPACKUSDW Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x2B /r"/"RAVM" + { + ND_INS_VPACKUSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1117, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1886 Instruction:"VPACKUSDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x2B /r"/"RVM" + { + ND_INS_VPACKUSDW, ND_CAT_AVX, ND_SET_AVX, 1117, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1887 Instruction:"VPACKUSWB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x67 /r"/"RAVM" + { + ND_INS_VPACKUSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1118, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1888 Instruction:"VPACKUSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x67 /r"/"RVM" + { + ND_INS_VPACKUSWB, ND_CAT_AVX, ND_SET_AVX, 1118, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1889 Instruction:"VPADDB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xFC /r"/"RAVM" + { + ND_INS_VPADDB, ND_CAT_AVX512, ND_SET_AVX512BW, 1119, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1890 Instruction:"VPADDB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFC /r"/"RVM" + { + ND_INS_VPADDB, ND_CAT_AVX, ND_SET_AVX, 1119, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1891 Instruction:"VPADDD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFE /r"/"RAVM" + { + ND_INS_VPADDD, ND_CAT_AVX512, ND_SET_AVX512F, 1120, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1892 Instruction:"VPADDD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFE /r"/"RVM" + { + ND_INS_VPADDD, ND_CAT_AVX, ND_SET_AVX, 1120, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1893 Instruction:"VPADDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xD4 /r"/"RAVM" + { + ND_INS_VPADDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1121, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:1894 Instruction:"VPADDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD4 /r"/"RVM" + { + ND_INS_VPADDQ, ND_CAT_AVX, ND_SET_AVX, 1121, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1895 Instruction:"VPADDSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEC /r"/"RAVM" + { + ND_INS_VPADDSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1122, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1896 Instruction:"VPADDSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEC /r"/"RVM" + { + ND_INS_VPADDSB, ND_CAT_AVX, ND_SET_AVX, 1122, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1897 Instruction:"VPADDSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xED /r"/"RAVM" + { + ND_INS_VPADDSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1123, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1898 Instruction:"VPADDSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xED /r"/"RVM" + { + ND_INS_VPADDSW, ND_CAT_AVX, ND_SET_AVX, 1123, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1899 Instruction:"VPADDUSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDC /r"/"RAVM" + { + ND_INS_VPADDUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1124, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1900 Instruction:"VPADDUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDC /r"/"RVM" + { + ND_INS_VPADDUSB, ND_CAT_AVX, ND_SET_AVX, 1124, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1901 Instruction:"VPADDUSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDD /r"/"RAVM" + { + ND_INS_VPADDUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1125, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1902 Instruction:"VPADDUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDD /r"/"RVM" + { + ND_INS_VPADDUSW, ND_CAT_AVX, ND_SET_AVX, 1125, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1903 Instruction:"VPADDW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xFD /r"/"RAVM" + { + ND_INS_VPADDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1126, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1904 Instruction:"VPADDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFD /r"/"RVM" + { + ND_INS_VPADDW, ND_CAT_AVX, ND_SET_AVX, 1126, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1905 Instruction:"VPALIGNR Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x0F /r ib"/"RAVMI" + { + ND_INS_VPALIGNR, ND_CAT_AVX512, ND_SET_AVX512BW, 1127, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1906 Instruction:"VPALIGNR Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0F /r ib"/"RVMI" + { + ND_INS_VPALIGNR, ND_CAT_AVX, ND_SET_AVX, 1127, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1907 Instruction:"VPAND Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDB /r"/"RVM" + { + ND_INS_VPAND, ND_CAT_LOGICAL, ND_SET_AVX, 1128, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1908 Instruction:"VPANDD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDB /r"/"RAVM" + { + ND_INS_VPANDD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1129, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1909 Instruction:"VPANDN Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDF /r"/"RVM" + { + ND_INS_VPANDN, ND_CAT_LOGICAL, ND_SET_AVX, 1130, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1910 Instruction:"VPANDND Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDF /r"/"RAVM" + { + ND_INS_VPANDND, ND_CAT_LOGICAL, ND_SET_AVX512F, 1131, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1911 Instruction:"VPANDNQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDF /r"/"RAVM" + { + ND_INS_VPANDNQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1132, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:1912 Instruction:"VPANDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDB /r"/"RAVM" + { + ND_INS_VPANDQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1133, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:1913 Instruction:"VPAVGB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE0 /r"/"RAVM" + { + ND_INS_VPAVGB, ND_CAT_AVX512, ND_SET_AVX512BW, 1134, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1914 Instruction:"VPAVGB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE0 /r"/"RVM" + { + ND_INS_VPAVGB, ND_CAT_AVX, ND_SET_AVX, 1134, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1915 Instruction:"VPAVGW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE3 /r"/"RAVM" + { + ND_INS_VPAVGW, ND_CAT_AVX512, ND_SET_AVX512BW, 1135, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1916 Instruction:"VPAVGW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE3 /r"/"RVM" + { + ND_INS_VPAVGW, ND_CAT_AVX, ND_SET_AVX, 1135, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1917 Instruction:"VPBLENDD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x02 /r ib"/"RVMI" + { + ND_INS_VPBLENDD, ND_CAT_AVX2, ND_SET_AVX2, 1136, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1918 Instruction:"VPBLENDMB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x66 /r"/"RAVM" + { + ND_INS_VPBLENDMB, ND_CAT_BLEND, ND_SET_AVX512BW, 1137, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1919 Instruction:"VPBLENDMD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x64 /r"/"RAVM" + { + ND_INS_VPBLENDMD, ND_CAT_BLEND, ND_SET_AVX512F, 1138, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1920 Instruction:"VPBLENDMQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x64 /r"/"RAVM" + { + ND_INS_VPBLENDMQ, ND_CAT_BLEND, ND_SET_AVX512F, 1139, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:1921 Instruction:"VPBLENDMW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x66 /r"/"RAVM" + { + ND_INS_VPBLENDMW, ND_CAT_BLEND, ND_SET_AVX512BW, 1140, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1922 Instruction:"VPBLENDVB Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4C /r is4"/"RVML" + { + ND_INS_VPBLENDVB, ND_CAT_AVX, ND_SET_AVX, 1141, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1923 Instruction:"VPBLENDW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0E /r ib"/"RVMI" + { + ND_INS_VPBLENDW, ND_CAT_AVX, ND_SET_AVX, 1142, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1924 Instruction:"VPBROADCASTB Vn{K}{z},aKq,Wb" Encoding:"evex m:2 p:1 l:x w:0 0x78 /r"/"RAM" + { + ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1143, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1925 Instruction:"VPBROADCASTB Vn{K}{z},aKq,Rb" Encoding:"evex m:2 p:1 l:x w:0 0x7A /r:reg"/"RAM" + { + ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1143, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_R, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1926 Instruction:"VPBROADCASTB Vx,Wb" Encoding:"vex m:2 p:1 l:x w:0 0x78 /r"/"RM" + { + ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX2, 1143, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1927 Instruction:"VPBROADCASTD Vn{K}{z},aKq,Wd" Encoding:"evex m:2 p:1 l:x w:0 0x58 /r"/"RAM" + { + ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1144, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:1928 Instruction:"VPBROADCASTD Vn{K}{z},aKq,Rd" Encoding:"evex m:2 p:1 l:x w:0 0x7C /r:reg"/"RAM" + { + ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1144, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_R, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:1929 Instruction:"VPBROADCASTD Vx,Wd" Encoding:"vex m:2 p:1 l:x w:0 0x58 /r"/"RM" + { + ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX2, 1144, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:1930 Instruction:"VPBROADCASTMB2Q Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x2A /r:reg"/"RM" + { + ND_INS_VPBROADCASTMB2Q, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1145, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1931 Instruction:"VPBROADCASTMW2D Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x3A /r:reg"/"RM" + { + ND_INS_VPBROADCASTMW2D, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1146, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1932 Instruction:"VPBROADCASTQ Vn{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:1 0x59 /r"/"RAM" + { + ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1147, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1933 Instruction:"VPBROADCASTQ Vn{K}{z},aKq,Rq" Encoding:"evex m:2 p:1 l:x w:1 0x7C /r:reg"/"RAM" + { + ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1147, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_R, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1934 Instruction:"VPBROADCASTQ Vx,Wq" Encoding:"vex m:2 p:1 l:x w:0 0x59 /r"/"RM" + { + ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX2, 1147, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1935 Instruction:"VPBROADCASTW Vn{K}{z},aKq,Ww" Encoding:"evex m:2 p:1 l:x w:0 0x79 /r"/"RAM" + { + ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1148, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:1936 Instruction:"VPBROADCASTW Vn{K}{z},aKq,Rw" Encoding:"evex m:2 p:1 l:x w:0 0x7B /r:reg"/"RAM" + { + ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1148, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_R, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:1937 Instruction:"VPBROADCASTW Vx,Ww" Encoding:"vex m:2 p:1 l:x w:0 0x79 /r"/"RM" + { + ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX2, 1148, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:1938 Instruction:"VPCLMULQDQ Vn,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI" + { + ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1149, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VPCLMULQDQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1939 Instruction:"VPCLMULQDQ Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x44 /r ib"/"RVMI" + { + ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1149, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VPCLMULQDQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1940 Instruction:"VPCMOV Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA2 /r is4"/"RVML" + { + ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1150, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1941 Instruction:"VPCMOV Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA2 /r is4"/"RVLM" + { + ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1150, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1942 Instruction:"VPCMPB rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3F /r ib"/"RAVMI" + { + ND_INS_VPCMPB, ND_CAT_AVX512, ND_SET_AVX512BW, 1151, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1943 Instruction:"VPCMPD rKq{K},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1F /r ib"/"RAVMI" + { + ND_INS_VPCMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1152, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1944 Instruction:"VPCMPEQB rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x74 /r"/"RAVM" + { + ND_INS_VPCMPEQB, ND_CAT_AVX512, ND_SET_AVX512BW, 1153, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1945 Instruction:"VPCMPEQB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x74 /r"/"RVM" + { + ND_INS_VPCMPEQB, ND_CAT_AVX, ND_SET_AVX, 1153, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1946 Instruction:"VPCMPEQD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:i 0x76 /r"/"RAVM" + { + ND_INS_VPCMPEQD, ND_CAT_AVX512, ND_SET_AVX512F, 1154, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1947 Instruction:"VPCMPEQD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x76 /r"/"RVM" + { + ND_INS_VPCMPEQD, ND_CAT_AVX, ND_SET_AVX, 1154, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1948 Instruction:"VPCMPEQQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x29 /r"/"RAVM" + { + ND_INS_VPCMPEQQ, ND_CAT_AVX512, ND_SET_AVX512F, 1155, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:1949 Instruction:"VPCMPEQQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x29 /r"/"RVM" + { + ND_INS_VPCMPEQQ, ND_CAT_AVX, ND_SET_AVX, 1155, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1950 Instruction:"VPCMPEQW rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x75 /r"/"RAVM" + { + ND_INS_VPCMPEQW, ND_CAT_AVX512, ND_SET_AVX512BW, 1156, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1951 Instruction:"VPCMPEQW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x75 /r"/"RVM" + { + ND_INS_VPCMPEQW, ND_CAT_AVX, ND_SET_AVX, 1156, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1952 Instruction:"VPCMPESTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x61 /r ib"/"RMI" + { + ND_INS_VPCMPESTRI, ND_CAT_STTNI, ND_SET_AVX, 1157, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1953 Instruction:"VPCMPESTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x60 /r ib"/"RMI" + { + ND_INS_VPCMPESTRM, ND_CAT_STTNI, ND_SET_AVX, 1158, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1954 Instruction:"VPCMPGTB rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x64 /r"/"RAVM" + { + ND_INS_VPCMPGTB, ND_CAT_AVX512, ND_SET_AVX512BW, 1159, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1955 Instruction:"VPCMPGTB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x64 /r"/"RVM" + { + ND_INS_VPCMPGTB, ND_CAT_AVX, ND_SET_AVX, 1159, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1956 Instruction:"VPCMPGTD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x66 /r"/"RAVM" + { + ND_INS_VPCMPGTD, ND_CAT_AVX512, ND_SET_AVX512F, 1160, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1957 Instruction:"VPCMPGTD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x66 /r"/"RVM" + { + ND_INS_VPCMPGTD, ND_CAT_AVX, ND_SET_AVX, 1160, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1958 Instruction:"VPCMPGTQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x37 /r"/"RAVM" + { + ND_INS_VPCMPGTQ, ND_CAT_AVX512, ND_SET_AVX512F, 1161, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:1959 Instruction:"VPCMPGTQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x37 /r"/"RVM" + { + ND_INS_VPCMPGTQ, ND_CAT_AVX, ND_SET_AVX, 1161, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1960 Instruction:"VPCMPGTW rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x65 /r"/"RAVM" + { + ND_INS_VPCMPGTW, ND_CAT_AVX512, ND_SET_AVX512BW, 1162, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1961 Instruction:"VPCMPGTW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x65 /r"/"RVM" + { + ND_INS_VPCMPGTW, ND_CAT_AVX, ND_SET_AVX, 1162, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1962 Instruction:"VPCMPISTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x63 /r ib"/"RMI" + { + ND_INS_VPCMPISTRI, ND_CAT_STTNI, ND_SET_AVX, 1163, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1963 Instruction:"VPCMPISTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x62 /r ib"/"RMI" + { + ND_INS_VPCMPISTRM, ND_CAT_STTNI, ND_SET_AVX, 1164, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1964 Instruction:"VPCMPQ rKq{K},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1F /r ib"/"RAVMI" + { + ND_INS_VPCMPQ, ND_CAT_AVX512, ND_SET_AVX512F, 1165, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1965 Instruction:"VPCMPUB rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3E /r ib"/"RAVMI" + { + ND_INS_VPCMPUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1166, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1966 Instruction:"VPCMPUD rKq{K},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1E /r ib"/"RAVMI" + { + ND_INS_VPCMPUD, ND_CAT_AVX512, ND_SET_AVX512F, 1167, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1967 Instruction:"VPCMPUQ rKq{K},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1E /r ib"/"RAVMI" + { + ND_INS_VPCMPUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1168, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1968 Instruction:"VPCMPUW rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3E /r ib"/"RAVMI" + { + ND_INS_VPCMPUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1169, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1969 Instruction:"VPCMPW rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3F /r ib"/"RAVMI" + { + ND_INS_VPCMPW, ND_CAT_AVX512, ND_SET_AVX512BW, 1170, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1970 Instruction:"VPCOMB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCC /r ib"/"RVMI" + { + ND_INS_VPCOMB, ND_CAT_XOP, ND_SET_XOP, 1171, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1971 Instruction:"VPCOMD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCE /r ib"/"RVMI" + { + ND_INS_VPCOMD, ND_CAT_XOP, ND_SET_XOP, 1172, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1972 Instruction:"VPCOMPRESSB Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x63 /r"/"MAR" + { + ND_INS_VPCOMPRESSB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1173, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1973 Instruction:"VPCOMPRESSD Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x8B /r"/"MAR" + { + ND_INS_VPCOMPRESSD, ND_CAT_COMPRESS, ND_SET_AVX512F, 1174, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1974 Instruction:"VPCOMPRESSQ Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x8B /r"/"MAR" + { + ND_INS_VPCOMPRESSQ, ND_CAT_COMPRESS, ND_SET_AVX512F, 1175, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1975 Instruction:"VPCOMPRESSW Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x63 /r"/"MAR" + { + ND_INS_VPCOMPRESSW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1176, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1976 Instruction:"VPCOMQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCF /r ib"/"RVMI" + { + ND_INS_VPCOMQ, ND_CAT_XOP, ND_SET_XOP, 1177, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1977 Instruction:"VPCOMUB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEC /r ib"/"RVMI" + { + ND_INS_VPCOMUB, ND_CAT_XOP, ND_SET_XOP, 1178, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1978 Instruction:"VPCOMUD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEE /r ib"/"RVMI" + { + ND_INS_VPCOMUD, ND_CAT_XOP, ND_SET_XOP, 1179, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1979 Instruction:"VPCOMUQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEF /r ib"/"RVMI" + { + ND_INS_VPCOMUQ, ND_CAT_XOP, ND_SET_XOP, 1180, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1980 Instruction:"VPCOMUW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xED /r ib"/"RVMI" + { + ND_INS_VPCOMUW, ND_CAT_XOP, ND_SET_XOP, 1181, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1981 Instruction:"VPCOMW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCD /r ib"/"RVMI" + { + ND_INS_VPCOMW, ND_CAT_XOP, ND_SET_XOP, 1182, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1982 Instruction:"VPCONFLICTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0xC4 /r"/"RAM" + { + ND_INS_VPCONFLICTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1183, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1983 Instruction:"VPCONFLICTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xC4 /r"/"RAM" + { + ND_INS_VPCONFLICTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1184, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:1984 Instruction:"VPDPBUSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x50 /r"/"RAVM" + { + ND_INS_VPDPBUSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1185, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1985 Instruction:"VPDPBUSDS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x51 /r"/"RAVM" + { + ND_INS_VPDPBUSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1186, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1986 Instruction:"VPDPWSSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x52 /r"/"RAVM" + { + ND_INS_VPDPWSSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1187, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1987 Instruction:"VPDPWSSDS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x53 /r"/"RAVM" + { + ND_INS_VPDPWSSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1188, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1988 Instruction:"VPERM2F128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x06 /r ib"/"RVMI" + { + ND_INS_VPERM2F128, ND_CAT_AVX, ND_SET_AVX, 1189, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_qq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1989 Instruction:"VPERM2I128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x46 /r ib"/"RVMI" + { + ND_INS_VPERM2I128, ND_CAT_AVX2, ND_SET_AVX2, 1190, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_qq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1990 Instruction:"VPERMB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x8D /r"/"RAVM" + { + ND_INS_VPERMB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1191, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1991 Instruction:"VPERMD Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:x w:0 0x36 /r"/"RAVM" + { + ND_INS_VPERMD, ND_CAT_AVX512, ND_SET_AVX512F, 1192, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_u, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_u, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_u, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1992 Instruction:"VPERMD Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x36 /r"/"RVM" + { + ND_INS_VPERMD, ND_CAT_AVX2, ND_SET_AVX2, 1192, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_qq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qq, ND_OPF_R, 0, 0), + }, + + // Pos:1993 Instruction:"VPERMI2B Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x75 /r"/"RAVM" + { + ND_INS_VPERMI2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1193, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1994 Instruction:"VPERMI2D Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x76 /r"/"RAVM" + { + ND_INS_VPERMI2D, ND_CAT_AVX512, ND_SET_AVX512F, 1194, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1995 Instruction:"VPERMI2PD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x77 /r"/"RAVM" + { + ND_INS_VPERMI2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1195, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:1996 Instruction:"VPERMI2PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x77 /r"/"RAVM" + { + ND_INS_VPERMI2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1196, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1997 Instruction:"VPERMI2Q Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x76 /r"/"RAVM" + { + ND_INS_VPERMI2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1197, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:1998 Instruction:"VPERMI2W Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x75 /r"/"RAVM" + { + ND_INS_VPERMI2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1198, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1999 Instruction:"VPERMILPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x0D /r"/"RAVM" + { + ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1199, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2000 Instruction:"VPERMILPD Vn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x05 /r ib"/"RAMI" + { + ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1199, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2001 Instruction:"VPERMILPD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0D /r"/"RVM" + { + ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1199, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2002 Instruction:"VPERMILPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x05 /r ib"/"RMI" + { + ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1199, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2003 Instruction:"VPERMILPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x0C /r"/"RAVM" + { + ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1200, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2004 Instruction:"VPERMILPS Vn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x04 /r ib"/"RAMI" + { + ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1200, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2005 Instruction:"VPERMILPS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0C /r"/"RVM" + { + ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1200, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2006 Instruction:"VPERMILPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x04 /r ib"/"RMI" + { + ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1200, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2007 Instruction:"VPERMILzz2PD Vx,Hx,Wx,Lx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x49 /r ib"/"RVMLI" + { + ND_INS_VPERMILzz2PD, ND_CAT_XOP, ND_SET_XOP, 1201, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2008 Instruction:"VPERMILzz2PD Vx,Hx,Lx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0x49 /r ib"/"RVLMI" + { + ND_INS_VPERMILzz2PD, ND_CAT_XOP, ND_SET_XOP, 1201, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2009 Instruction:"VPERMILzz2PS Vx,Hx,Wx,Lx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x48 /r ib"/"RVMLI" + { + ND_INS_VPERMILzz2PS, ND_CAT_XOP, ND_SET_XOP, 1202, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2010 Instruction:"VPERMILzz2PS Vx,Hx,Lx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0x48 /r ib"/"RVLMI" + { + ND_INS_VPERMILzz2PS, ND_CAT_XOP, ND_SET_XOP, 1202, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2011 Instruction:"VPERMPD Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:1 w:1 0x16 /r"/"RAVM" + { + ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1203, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_u, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_u, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_u, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2012 Instruction:"VPERMPD Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:2 w:1 0x16 /r"/"RAVM" + { + ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1203, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_u, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_u, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_u, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2013 Instruction:"VPERMPD Vu{K}{z},aKq,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x01 /r ib"/"RAMI" + { + ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1203, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_u, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_u, ND_OPF_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2014 Instruction:"VPERMPD Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x01 /r ib"/"RMI" + { + ND_INS_VPERMPD, ND_CAT_AVX2, ND_SET_AVX2, 1203, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_qq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2015 Instruction:"VPERMPS Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:1 w:0 0x16 /r"/"RAVM" + { + ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1204, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_u, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_u, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_u, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2016 Instruction:"VPERMPS Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:2 w:0 0x16 /r"/"RAVM" + { + ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1204, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_u, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_u, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_u, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2017 Instruction:"VPERMPS Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x16 /r"/"RVM" + { + ND_INS_VPERMPS, ND_CAT_AVX2, ND_SET_AVX2, 1204, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_qq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qq, ND_OPF_R, 0, 0), + }, + + // Pos:2018 Instruction:"VPERMQ Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:x w:1 0x36 /r"/"RAVM" + { + ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1205, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_u, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_u, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_u, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2019 Instruction:"VPERMQ Vu{K}{z},aKq,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x00 /r ib"/"RAMI" + { + ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1205, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_u, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_u, ND_OPF_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2020 Instruction:"VPERMQ Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x00 /r ib"/"RMI" + { + ND_INS_VPERMQ, ND_CAT_AVX2, ND_SET_AVX2, 1205, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_qq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2021 Instruction:"VPERMT2B Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x7D /r"/"RAVM" + { + ND_INS_VPERMT2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1206, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2022 Instruction:"VPERMT2D Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7E /r"/"RAVM" + { + ND_INS_VPERMT2D, ND_CAT_AVX512, ND_SET_AVX512F, 1207, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2023 Instruction:"VPERMT2PD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7F /r"/"RAVM" + { + ND_INS_VPERMT2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1208, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2024 Instruction:"VPERMT2PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7F /r"/"RAVM" + { + ND_INS_VPERMT2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1209, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2025 Instruction:"VPERMT2Q Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7E /r"/"RAVM" + { + ND_INS_VPERMT2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1210, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2026 Instruction:"VPERMT2W Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x7D /r"/"RAVM" + { + ND_INS_VPERMT2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1211, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2027 Instruction:"VPERMW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x8D /r"/"RAVM" + { + ND_INS_VPERMW, ND_CAT_AVX512, ND_SET_AVX512BW, 1212, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2028 Instruction:"VPEXPANDB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x62 /r"/"RAM" + { + ND_INS_VPEXPANDB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1213, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2029 Instruction:"VPEXPANDD Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x89 /r"/"RAM" + { + ND_INS_VPEXPANDD, ND_CAT_EXPAND, ND_SET_AVX512F, 1214, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2030 Instruction:"VPEXPANDQ Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x89 /r"/"RAM" + { + ND_INS_VPEXPANDQ, ND_CAT_EXPAND, ND_SET_AVX512F, 1215, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2031 Instruction:"VPEXPANDW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x62 /r"/"RAM" + { + ND_INS_VPEXPANDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1216, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2032 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI" + { + ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1217, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2033 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI" + { + ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1217, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2034 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x14 /r:mem ib"/"MRI" + { + ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1217, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2035 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x14 /r:reg ib"/"MRI" + { + ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1217, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2036 Instruction:"VPEXTRD Ed,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r ib"/"MRI" + { + ND_INS_VPEXTRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1218, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2037 Instruction:"VPEXTRD Ey,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r ib"/"MRI" + { + ND_INS_VPEXTRD, ND_CAT_AVX, ND_SET_AVX, 1218, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2038 Instruction:"VPEXTRQ Eq,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r ib"/"MRI" + { + ND_INS_VPEXTRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1219, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2039 Instruction:"VPEXTRQ Ey,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r ib"/"MRI" + { + ND_INS_VPEXTRQ, ND_CAT_AVX, ND_SET_AVX, 1219, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2040 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI" + { + ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1220, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2041 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI" + { + ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1220, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2042 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI" + { + ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1220, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2043 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"vex m:1 p:1 l:0 w:0 0xC5 /r:reg ib"/"RMI" + { + ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1220, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2044 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x15 /r:mem ib"/"MRI" + { + ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1220, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2045 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x15 /r:reg ib"/"MRI" + { + ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1220, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2046 Instruction:"VPGATHERDD Vn{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RAM" + { + ND_INS_VPGATHERDD, ND_CAT_GATHER, ND_SET_AVX512F, 1221, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_vm32n, ND_OPF_RW, 0, 0), + }, + + // Pos:2047 Instruction:"VPGATHERDD Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RMV" + { + ND_INS_VPGATHERDD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1221, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_CRW, 0, 0), + OP(ND_OPT_M, ND_OPS_vm32n, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_RW, 0, 0), + }, + + // Pos:2048 Instruction:"VPGATHERDQ Vn{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RAM" + { + ND_INS_VPGATHERDQ, ND_CAT_GATHER, ND_SET_AVX512F, 1222, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_vm32h, ND_OPF_RW, 0, 0), + }, + + // Pos:2049 Instruction:"VPGATHERDQ Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RMV" + { + ND_INS_VPGATHERDQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1222, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_CRW, 0, 0), + OP(ND_OPT_M, ND_OPS_vm32h, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_RW, 0, 0), + }, + + // Pos:2050 Instruction:"VPGATHERQD Vh{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RAM" + { + ND_INS_VPGATHERQD, ND_CAT_GATHER, ND_SET_AVX512F, 1223, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_h, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_vm64n, ND_OPF_RW, 0, 0), + }, + + // Pos:2051 Instruction:"VPGATHERQD Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RMV" + { + ND_INS_VPGATHERQD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1223, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_CRW, 0, 0), + OP(ND_OPT_M, ND_OPS_vm64n, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_RW, 0, 0), + }, + + // Pos:2052 Instruction:"VPGATHERQQ Vn{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RAM" + { + ND_INS_VPGATHERQQ, ND_CAT_GATHER, ND_SET_AVX512F, 1224, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_vm64n, ND_OPF_RW, 0, 0), + }, + + // Pos:2053 Instruction:"VPGATHERQQ Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RMV" + { + ND_INS_VPGATHERQQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1224, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_CRW, 0, 0), + OP(ND_OPT_M, ND_OPS_vm64n, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_RW, 0, 0), + }, + + // Pos:2054 Instruction:"VPHADDBD Vdq,Wdq" Encoding:"xop m:9 0xC2 /r"/"RM" + { + ND_INS_VPHADDBD, ND_CAT_XOP, ND_SET_XOP, 1225, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2055 Instruction:"VPHADDBQ Vdq,Wdq" Encoding:"xop m:9 0xC3 /r"/"RM" + { + ND_INS_VPHADDBQ, ND_CAT_XOP, ND_SET_XOP, 1226, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2056 Instruction:"VPHADDBW Vdq,Wdq" Encoding:"xop m:9 0xC1 /r"/"RM" + { + ND_INS_VPHADDBW, ND_CAT_XOP, ND_SET_XOP, 1227, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2057 Instruction:"VPHADDD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x02 /r"/"RVM" + { + ND_INS_VPHADDD, ND_CAT_AVX, ND_SET_AVX, 1228, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2058 Instruction:"VPHADDDQ Vdq,Wdq" Encoding:"xop m:9 0xCB /r"/"RM" + { + ND_INS_VPHADDDQ, ND_CAT_XOP, ND_SET_XOP, 1229, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2059 Instruction:"VPHADDSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x03 /r"/"RVM" + { + ND_INS_VPHADDSW, ND_CAT_AVX, ND_SET_AVX, 1230, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2060 Instruction:"VPHADDUBD Vdq,Wdq" Encoding:"xop m:9 0xD2 /r"/"RM" + { + ND_INS_VPHADDUBD, ND_CAT_XOP, ND_SET_XOP, 1231, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2061 Instruction:"VPHADDUBQ Vdq,Wdq" Encoding:"xop m:9 0xD3 /r"/"RM" + { + ND_INS_VPHADDUBQ, ND_CAT_XOP, ND_SET_XOP, 1232, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2062 Instruction:"VPHADDUBW Vdq,Wdq" Encoding:"xop m:9 0xD1 /r"/"RM" + { + ND_INS_VPHADDUBW, ND_CAT_XOP, ND_SET_XOP, 1233, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2063 Instruction:"VPHADDUDQ Vdq,Wdq" Encoding:"xop m:9 0xDB /r"/"RM" + { + ND_INS_VPHADDUDQ, ND_CAT_XOP, ND_SET_XOP, 1234, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2064 Instruction:"VPHADDUWD Vdq,Wdq" Encoding:"xop m:9 0xD6 /r"/"RM" + { + ND_INS_VPHADDUWD, ND_CAT_XOP, ND_SET_XOP, 1235, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2065 Instruction:"VPHADDUWQ Vdq,Wdq" Encoding:"xop m:9 0xD7 /r"/"RM" + { + ND_INS_VPHADDUWQ, ND_CAT_XOP, ND_SET_XOP, 1236, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2066 Instruction:"VPHADDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x01 /r"/"RVM" + { + ND_INS_VPHADDW, ND_CAT_AVX, ND_SET_AVX, 1237, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2067 Instruction:"VPHADDWD Vdq,Wdq" Encoding:"xop m:9 0xC6 /r"/"RM" + { + ND_INS_VPHADDWD, ND_CAT_XOP, ND_SET_XOP, 1238, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2068 Instruction:"VPHADDWQ Vdq,Wdq" Encoding:"xop m:9 0xC7 /r"/"RM" + { + ND_INS_VPHADDWQ, ND_CAT_XOP, ND_SET_XOP, 1239, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2069 Instruction:"VPHMINPOSUW Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0x41 /r"/"RM" + { + ND_INS_VPHMINPOSUW, ND_CAT_AVX, ND_SET_AVX, 1240, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2070 Instruction:"VPHSUBBW Vdq,Wdq" Encoding:"xop m:9 0xE1 /r"/"RM" + { + ND_INS_VPHSUBBW, ND_CAT_XOP, ND_SET_XOP, 1241, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2071 Instruction:"VPHSUBD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x06 /r"/"RVM" + { + ND_INS_VPHSUBD, ND_CAT_AVX, ND_SET_AVX, 1242, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2072 Instruction:"VPHSUBDQ Vdq,Wdq" Encoding:"xop m:9 0xE3 /r"/"RM" + { + ND_INS_VPHSUBDQ, ND_CAT_XOP, ND_SET_XOP, 1243, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2073 Instruction:"VPHSUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x07 /r"/"RVM" + { + ND_INS_VPHSUBSW, ND_CAT_AVX, ND_SET_AVX, 1244, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2074 Instruction:"VPHSUBW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x05 /r"/"RVM" + { + ND_INS_VPHSUBW, ND_CAT_AVX, ND_SET_AVX, 1245, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2075 Instruction:"VPHSUBWD Vdq,Wdq" Encoding:"xop m:9 0xE2 /r"/"RM" + { + ND_INS_VPHSUBWD, ND_CAT_XOP, ND_SET_XOP, 1246, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2076 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI" + { + ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1247, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2077 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI" + { + ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1247, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_R, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2078 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI" + { + ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1247, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2079 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI" + { + ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1247, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_R, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2080 Instruction:"VPINSRD Vdq,Hdq,Ed,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI" + { + ND_INS_VPINSRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1248, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2081 Instruction:"VPINSRD Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI" + { + ND_INS_VPINSRD, ND_CAT_AVX, ND_SET_AVX, 1248, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2082 Instruction:"VPINSRQ Vdq,Hdq,Eq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI" + { + ND_INS_VPINSRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1249, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2083 Instruction:"VPINSRQ Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI" + { + ND_INS_VPINSRQ, ND_CAT_AVX, ND_SET_AVX, 1249, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2084 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI" + { + ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1250, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2085 Instruction:"VPINSRW Vdq,Hdq,Rv,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI" + { + ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1250, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2086 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"vex m:1 p:1 l:0 w:0 0xC4 /r:mem ib"/"RVMI" + { + ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1250, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2087 Instruction:"VPINSRW Vdq,Hdq,Ry,Ib" Encoding:"vex m:1 p:1 l:0 w:0 0xC4 /r:reg ib"/"RVMI" + { + ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1250, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2088 Instruction:"VPLZCNTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x44 /r"/"RAM" + { + ND_INS_VPLZCNTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1251, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2089 Instruction:"VPLZCNTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x44 /r"/"RAM" + { + ND_INS_VPLZCNTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1252, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2090 Instruction:"VPMACSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9E /r is4"/"RVML" + { + ND_INS_VPMACSDD, ND_CAT_XOP, ND_SET_XOP, 1253, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2091 Instruction:"VPMACSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9F /r is4"/"RVML" + { + ND_INS_VPMACSDQH, ND_CAT_XOP, ND_SET_XOP, 1254, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2092 Instruction:"VPMACSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x97 /r is4"/"RVML" + { + ND_INS_VPMACSDQL, ND_CAT_XOP, ND_SET_XOP, 1255, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2093 Instruction:"VPMACSSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8E /r is4"/"RVML" + { + ND_INS_VPMACSSDD, ND_CAT_XOP, ND_SET_XOP, 1256, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2094 Instruction:"VPMACSSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8F /r is4"/"RVML" + { + ND_INS_VPMACSSDQH, ND_CAT_XOP, ND_SET_XOP, 1257, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2095 Instruction:"VPMACSSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x87 /r is4"/"RVML" + { + ND_INS_VPMACSSDQL, ND_CAT_XOP, ND_SET_XOP, 1258, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2096 Instruction:"VPMACSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x86 /r is4"/"RVML" + { + ND_INS_VPMACSSWD, ND_CAT_XOP, ND_SET_XOP, 1259, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2097 Instruction:"VPMACSSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x85 /r is4"/"RVML" + { + ND_INS_VPMACSSWW, ND_CAT_XOP, ND_SET_XOP, 1260, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2098 Instruction:"VPMACSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x96 /r is4"/"RVML" + { + ND_INS_VPMACSWD, ND_CAT_XOP, ND_SET_XOP, 1261, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2099 Instruction:"VPMACSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x95 /r is4"/"RVML" + { + ND_INS_VPMACSWW, ND_CAT_XOP, ND_SET_XOP, 1262, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2100 Instruction:"VPMADCSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xA6 /r is4"/"RVML" + { + ND_INS_VPMADCSSWD, ND_CAT_XOP, ND_SET_XOP, 1263, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2101 Instruction:"VPMADCSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xB6 /r is4"/"RVML" + { + ND_INS_VPMADCSWD, ND_CAT_XOP, ND_SET_XOP, 1264, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2102 Instruction:"VPMADD52HUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB5 /r"/"RAVM" + { + ND_INS_VPMADD52HUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1265, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512IFMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2103 Instruction:"VPMADD52LUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB4 /r"/"RAVM" + { + ND_INS_VPMADD52LUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1266, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512IFMA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2104 Instruction:"VPMADDUBSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x04 /r"/"RAVM" + { + ND_INS_VPMADDUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1267, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2105 Instruction:"VPMADDUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x04 /r"/"RVM" + { + ND_INS_VPMADDUBSW, ND_CAT_AVX, ND_SET_AVX, 1267, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2106 Instruction:"VPMADDWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF5 /r"/"RAVM" + { + ND_INS_VPMADDWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1268, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2107 Instruction:"VPMADDWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF5 /r"/"RVM" + { + ND_INS_VPMADDWD, ND_CAT_AVX, ND_SET_AVX, 1268, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2108 Instruction:"VPMASKMOVD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x8C /r:mem"/"RVM" + { + ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1269, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2109 Instruction:"VPMASKMOVD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x8E /r:mem"/"MVR" + { + ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1269, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2110 Instruction:"VPMASKMOVQ Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:1 0x8C /r:mem"/"RVM" + { + ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1270, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2111 Instruction:"VPMASKMOVQ Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:1 0x8E /r:mem"/"MVR" + { + ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1270, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2112 Instruction:"VPMAXSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3C /r"/"RAVM" + { + ND_INS_VPMAXSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1271, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2113 Instruction:"VPMAXSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3C /r"/"RVM" + { + ND_INS_VPMAXSB, ND_CAT_AVX, ND_SET_AVX, 1271, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2114 Instruction:"VPMAXSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3D /r"/"RAVM" + { + ND_INS_VPMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1272, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2115 Instruction:"VPMAXSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3D /r"/"RVM" + { + ND_INS_VPMAXSD, ND_CAT_AVX, ND_SET_AVX, 1272, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2116 Instruction:"VPMAXSQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3D /r"/"RAVM" + { + ND_INS_VPMAXSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1273, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2117 Instruction:"VPMAXSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEE /r"/"RAVM" + { + ND_INS_VPMAXSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1274, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2118 Instruction:"VPMAXSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEE /r"/"RVM" + { + ND_INS_VPMAXSW, ND_CAT_AVX, ND_SET_AVX, 1274, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2119 Instruction:"VPMAXUB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDE /r"/"RAVM" + { + ND_INS_VPMAXUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1275, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2120 Instruction:"VPMAXUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDE /r"/"RVM" + { + ND_INS_VPMAXUB, ND_CAT_AVX, ND_SET_AVX, 1275, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2121 Instruction:"VPMAXUD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3F /r"/"RAVM" + { + ND_INS_VPMAXUD, ND_CAT_AVX512, ND_SET_AVX512F, 1276, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2122 Instruction:"VPMAXUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3F /r"/"RVM" + { + ND_INS_VPMAXUD, ND_CAT_AVX, ND_SET_AVX, 1276, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2123 Instruction:"VPMAXUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3F /r"/"RAVM" + { + ND_INS_VPMAXUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1277, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2124 Instruction:"VPMAXUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3E /r"/"RAVM" + { + ND_INS_VPMAXUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1278, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2125 Instruction:"VPMAXUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3E /r"/"RVM" + { + ND_INS_VPMAXUW, ND_CAT_AVX, ND_SET_AVX, 1278, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2126 Instruction:"VPMINSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x38 /r"/"RAVM" + { + ND_INS_VPMINSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1279, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2127 Instruction:"VPMINSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x38 /r"/"RVM" + { + ND_INS_VPMINSB, ND_CAT_AVX, ND_SET_AVX, 1279, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2128 Instruction:"VPMINSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x39 /r"/"RAVM" + { + ND_INS_VPMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1280, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2129 Instruction:"VPMINSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x39 /r"/"RVM" + { + ND_INS_VPMINSD, ND_CAT_AVX, ND_SET_AVX, 1280, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2130 Instruction:"VPMINSQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x39 /r"/"RAVM" + { + ND_INS_VPMINSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1281, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2131 Instruction:"VPMINSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEA /r"/"RAVM" + { + ND_INS_VPMINSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1282, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2132 Instruction:"VPMINSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEA /r"/"RVM" + { + ND_INS_VPMINSW, ND_CAT_AVX, ND_SET_AVX, 1282, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2133 Instruction:"VPMINUB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDA /r"/"RAVM" + { + ND_INS_VPMINUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1283, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2134 Instruction:"VPMINUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDA /r"/"RVM" + { + ND_INS_VPMINUB, ND_CAT_AVX, ND_SET_AVX, 1283, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2135 Instruction:"VPMINUD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3B /r"/"RAVM" + { + ND_INS_VPMINUD, ND_CAT_AVX512, ND_SET_AVX512F, 1284, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2136 Instruction:"VPMINUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3B /r"/"RVM" + { + ND_INS_VPMINUD, ND_CAT_AVX, ND_SET_AVX, 1284, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2137 Instruction:"VPMINUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3B /r"/"RAVM" + { + ND_INS_VPMINUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1285, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2138 Instruction:"VPMINUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3A /r"/"RAVM" + { + ND_INS_VPMINUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1286, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2139 Instruction:"VPMINUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3A /r"/"RVM" + { + ND_INS_VPMINUW, ND_CAT_AVX, ND_SET_AVX, 1286, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2140 Instruction:"VPMOVB2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:0 0x29 /r:reg"/"RM" + { + ND_INS_VPMOVB2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1287, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2141 Instruction:"VPMOVD2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:0 0x39 /r:reg"/"RM" + { + ND_INS_VPMOVD2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1288, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2142 Instruction:"VPMOVDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x31 /r"/"MAR" + { + ND_INS_VPMOVDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1289, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_f, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2143 Instruction:"VPMOVDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x33 /r"/"MAR" + { + ND_INS_VPMOVDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1290, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_h, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2144 Instruction:"VPMOVM2B Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x28 /r:reg"/"RM" + { + ND_INS_VPMOVM2B, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1291, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:2145 Instruction:"VPMOVM2D Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x38 /r:reg"/"RM" + { + ND_INS_VPMOVM2D, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1292, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:2146 Instruction:"VPMOVM2Q Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x38 /r:reg"/"RM" + { + ND_INS_VPMOVM2Q, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1293, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:2147 Instruction:"VPMOVM2W Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x28 /r:reg"/"RM" + { + ND_INS_VPMOVM2W, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1294, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:2148 Instruction:"VPMOVMSKB Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0xD7 /r:reg"/"RM" + { + ND_INS_VPMOVMSKB, ND_CAT_DATAXFER, ND_SET_AVX, 1295, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2149 Instruction:"VPMOVQ2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:1 0x39 /r:reg"/"RM" + { + ND_INS_VPMOVQ2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1296, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2150 Instruction:"VPMOVQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x32 /r"/"MAR" + { + ND_INS_VPMOVQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1297, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_e, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2151 Instruction:"VPMOVQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x35 /r"/"MAR" + { + ND_INS_VPMOVQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1298, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_h, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2152 Instruction:"VPMOVQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x34 /r"/"MAR" + { + ND_INS_VPMOVQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1299, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_f, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2153 Instruction:"VPMOVSDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x21 /r"/"MAR" + { + ND_INS_VPMOVSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1300, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_f, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2154 Instruction:"VPMOVSDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x23 /r"/"MAR" + { + ND_INS_VPMOVSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1301, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_h, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2155 Instruction:"VPMOVSQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x22 /r"/"MAR" + { + ND_INS_VPMOVSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1302, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_e, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2156 Instruction:"VPMOVSQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x25 /r"/"MAR" + { + ND_INS_VPMOVSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1303, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_h, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2157 Instruction:"VPMOVSQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x24 /r"/"MAR" + { + ND_INS_VPMOVSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1304, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_f, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2158 Instruction:"VPMOVSWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x20 /r"/"MAR" + { + ND_INS_VPMOVSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1305, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_h, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2159 Instruction:"VPMOVSXBD Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x21 /r"/"RAM" + { + ND_INS_VPMOVSXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1306, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_f, ND_OPF_R, 0, 0), + }, + + // Pos:2160 Instruction:"VPMOVSXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x21 /r"/"RM" + { + ND_INS_VPMOVSXBD, ND_CAT_AVX, ND_SET_AVX, 1306, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:2161 Instruction:"VPMOVSXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x21 /r"/"RM" + { + ND_INS_VPMOVSXBD, ND_CAT_AVX2, ND_SET_AVX2, 1306, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:2162 Instruction:"VPMOVSXBQ Vn{K}{z},aKq,We" Encoding:"evex m:2 p:1 l:x w:i 0x22 /r"/"RAM" + { + ND_INS_VPMOVSXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1307, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_e, ND_OPF_R, 0, 0), + }, + + // Pos:2163 Instruction:"VPMOVSXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x22 /r"/"RM" + { + ND_INS_VPMOVSXBQ, ND_CAT_AVX, ND_SET_AVX, 1307, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:2164 Instruction:"VPMOVSXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x22 /r"/"RM" + { + ND_INS_VPMOVSXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1307, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:2165 Instruction:"VPMOVSXBW Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x20 /r"/"RAM" + { + ND_INS_VPMOVSXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1308, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, 0, 0), + }, + + // Pos:2166 Instruction:"VPMOVSXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x20 /r"/"RM" + { + ND_INS_VPMOVSXBW, ND_CAT_AVX, ND_SET_AVX, 1308, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:2167 Instruction:"VPMOVSXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x20 /r"/"RM" + { + ND_INS_VPMOVSXBW, ND_CAT_AVX2, ND_SET_AVX2, 1308, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2168 Instruction:"VPMOVSXDQ Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:0 0x25 /r"/"RAM" + { + ND_INS_VPMOVSXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1309, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, 0, 0), + }, + + // Pos:2169 Instruction:"VPMOVSXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x25 /r"/"RM" + { + ND_INS_VPMOVSXDQ, ND_CAT_AVX, ND_SET_AVX, 1309, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:2170 Instruction:"VPMOVSXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x25 /r"/"RM" + { + ND_INS_VPMOVSXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1309, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2171 Instruction:"VPMOVSXWD Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x23 /r"/"RAM" + { + ND_INS_VPMOVSXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1310, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, 0, 0), + }, + + // Pos:2172 Instruction:"VPMOVSXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x23 /r"/"RM" + { + ND_INS_VPMOVSXWD, ND_CAT_AVX, ND_SET_AVX, 1310, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:2173 Instruction:"VPMOVSXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x23 /r"/"RM" + { + ND_INS_VPMOVSXWD, ND_CAT_AVX2, ND_SET_AVX2, 1310, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2174 Instruction:"VPMOVSXWQ Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x24 /r"/"RAM" + { + ND_INS_VPMOVSXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1311, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_f, ND_OPF_R, 0, 0), + }, + + // Pos:2175 Instruction:"VPMOVSXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x24 /r"/"RM" + { + ND_INS_VPMOVSXWQ, ND_CAT_AVX, ND_SET_AVX, 1311, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:2176 Instruction:"VPMOVSXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x24 /r"/"RM" + { + ND_INS_VPMOVSXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1311, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:2177 Instruction:"VPMOVUSDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x11 /r"/"MAR" + { + ND_INS_VPMOVUSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1312, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_f, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2178 Instruction:"VPMOVUSDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x13 /r"/"MAR" + { + ND_INS_VPMOVUSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1313, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_h, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2179 Instruction:"VPMOVUSQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x12 /r"/"MAR" + { + ND_INS_VPMOVUSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1314, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_e, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2180 Instruction:"VPMOVUSQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x15 /r"/"MAR" + { + ND_INS_VPMOVUSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1315, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_h, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2181 Instruction:"VPMOVUSQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x14 /r"/"MAR" + { + ND_INS_VPMOVUSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1316, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_f, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2182 Instruction:"VPMOVUSWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x10 /r"/"MAR" + { + ND_INS_VPMOVUSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1317, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_h, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2183 Instruction:"VPMOVW2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:1 0x29 /r:reg"/"RM" + { + ND_INS_VPMOVW2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1318, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2184 Instruction:"VPMOVWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x30 /r"/"MAR" + { + ND_INS_VPMOVWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1319, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_h, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2185 Instruction:"VPMOVZXBD Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x31 /r"/"RAM" + { + ND_INS_VPMOVZXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1320, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_f, ND_OPF_R, 0, 0), + }, + + // Pos:2186 Instruction:"VPMOVZXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x31 /r"/"RM" + { + ND_INS_VPMOVZXBD, ND_CAT_AVX, ND_SET_AVX, 1320, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:2187 Instruction:"VPMOVZXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x31 /r"/"RM" + { + ND_INS_VPMOVZXBD, ND_CAT_AVX2, ND_SET_AVX2, 1320, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:2188 Instruction:"VPMOVZXBQ Vn{K}{z},aKq,We" Encoding:"evex m:2 p:1 l:x w:i 0x32 /r"/"RAM" + { + ND_INS_VPMOVZXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1321, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_e, ND_OPF_R, 0, 0), + }, + + // Pos:2189 Instruction:"VPMOVZXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x32 /r"/"RM" + { + ND_INS_VPMOVZXBQ, ND_CAT_AVX, ND_SET_AVX, 1321, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:2190 Instruction:"VPMOVZXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x32 /r"/"RM" + { + ND_INS_VPMOVZXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1321, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:2191 Instruction:"VPMOVZXBW Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x30 /r"/"RAM" + { + ND_INS_VPMOVZXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1322, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, 0, 0), + }, + + // Pos:2192 Instruction:"VPMOVZXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x30 /r"/"RM" + { + ND_INS_VPMOVZXBW, ND_CAT_AVX, ND_SET_AVX, 1322, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:2193 Instruction:"VPMOVZXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x30 /r"/"RM" + { + ND_INS_VPMOVZXBW, ND_CAT_AVX2, ND_SET_AVX2, 1322, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2194 Instruction:"VPMOVZXDQ Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:0 0x35 /r"/"RAM" + { + ND_INS_VPMOVZXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1323, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, 0, 0), + }, + + // Pos:2195 Instruction:"VPMOVZXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x35 /r"/"RM" + { + ND_INS_VPMOVZXDQ, ND_CAT_AVX, ND_SET_AVX, 1323, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:2196 Instruction:"VPMOVZXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x35 /r"/"RM" + { + ND_INS_VPMOVZXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1323, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2197 Instruction:"VPMOVZXWD Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x33 /r"/"RAM" + { + ND_INS_VPMOVZXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1324, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, 0, 0), + }, + + // Pos:2198 Instruction:"VPMOVZXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x33 /r"/"RM" + { + ND_INS_VPMOVZXWD, ND_CAT_AVX, ND_SET_AVX, 1324, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:2199 Instruction:"VPMOVZXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x33 /r"/"RM" + { + ND_INS_VPMOVZXWD, ND_CAT_AVX2, ND_SET_AVX2, 1324, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2200 Instruction:"VPMOVZXWQ Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x34 /r"/"RAM" + { + ND_INS_VPMOVZXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1325, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_f, ND_OPF_R, 0, 0), + }, + + // Pos:2201 Instruction:"VPMOVZXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x34 /r"/"RM" + { + ND_INS_VPMOVZXWQ, ND_CAT_AVX, ND_SET_AVX, 1325, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:2202 Instruction:"VPMOVZXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x34 /r"/"RM" + { + ND_INS_VPMOVZXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1325, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:2203 Instruction:"VPMULDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x28 /r"/"RAVM" + { + ND_INS_VPMULDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1326, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2204 Instruction:"VPMULDQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x28 /r"/"RVM" + { + ND_INS_VPMULDQ, ND_CAT_AVX, ND_SET_AVX, 1326, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2205 Instruction:"VPMULHRSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x0B /r"/"RAVM" + { + ND_INS_VPMULHRSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1327, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2206 Instruction:"VPMULHRSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0B /r"/"RVM" + { + ND_INS_VPMULHRSW, ND_CAT_AVX, ND_SET_AVX, 1327, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2207 Instruction:"VPMULHUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE4 /r"/"RAVM" + { + ND_INS_VPMULHUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1328, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2208 Instruction:"VPMULHUW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE4 /r"/"RVM" + { + ND_INS_VPMULHUW, ND_CAT_AVX, ND_SET_AVX, 1328, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2209 Instruction:"VPMULHW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE5 /r"/"RAVM" + { + ND_INS_VPMULHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1329, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2210 Instruction:"VPMULHW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE5 /r"/"RVM" + { + ND_INS_VPMULHW, ND_CAT_AVX, ND_SET_AVX, 1329, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2211 Instruction:"VPMULLD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x40 /r"/"RAVM" + { + ND_INS_VPMULLD, ND_CAT_AVX512, ND_SET_AVX512F, 1330, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2212 Instruction:"VPMULLD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x40 /r"/"RVM" + { + ND_INS_VPMULLD, ND_CAT_AVX, ND_SET_AVX, 1330, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2213 Instruction:"VPMULLQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x40 /r"/"RAVM" + { + ND_INS_VPMULLQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1331, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2214 Instruction:"VPMULLW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD5 /r"/"RAVM" + { + ND_INS_VPMULLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1332, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2215 Instruction:"VPMULLW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD5 /r"/"RVM" + { + ND_INS_VPMULLW, ND_CAT_AVX, ND_SET_AVX, 1332, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2216 Instruction:"VPMULTISHIFTQB Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x83 /r"/"RAVM" + { + ND_INS_VPMULTISHIFTQB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1333, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2217 Instruction:"VPMULUDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xF4 /r"/"RAVM" + { + ND_INS_VPMULUDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1334, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2218 Instruction:"VPMULUDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF4 /r"/"RVM" + { + ND_INS_VPMULUDQ, ND_CAT_AVX, ND_SET_AVX, 1334, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2219 Instruction:"VPOPCNTB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x54 /r"/"RAM" + { + ND_INS_VPOPCNTB, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1335, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2220 Instruction:"VPOPCNTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x55 /r"/"RAM" + { + ND_INS_VPOPCNTD, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1336, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VPOPCNTDQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2221 Instruction:"VPOPCNTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x55 /r"/"RAM" + { + ND_INS_VPOPCNTQ, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1337, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VPOPCNTDQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2222 Instruction:"VPOPCNTW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x54 /r"/"RAM" + { + ND_INS_VPOPCNTW, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1338, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2223 Instruction:"VPOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEB /r"/"RVM" + { + ND_INS_VPOR, ND_CAT_LOGICAL, ND_SET_AVX, 1339, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2224 Instruction:"VPORD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEB /r"/"RAVM" + { + ND_INS_VPORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1340, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2225 Instruction:"VPORQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEB /r"/"RAVM" + { + ND_INS_VPORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1341, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2226 Instruction:"VPPERM Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA3 /r is4"/"RVML" + { + ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1342, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2227 Instruction:"VPPERM Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA3 /r is4"/"RVLM" + { + ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1342, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2228 Instruction:"VPROLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /1 ib"/"VAMI" + { + ND_INS_VPROLD, ND_CAT_AVX512, ND_SET_AVX512F, 1343, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_H, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2229 Instruction:"VPROLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /1 ib"/"VAMI" + { + ND_INS_VPROLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1344, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_H, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2230 Instruction:"VPROLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x15 /r"/"RAVM" + { + ND_INS_VPROLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1345, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2231 Instruction:"VPROLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x15 /r"/"RAVM" + { + ND_INS_VPROLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1346, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2232 Instruction:"VPRORD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /0 ib"/"VAMI" + { + ND_INS_VPRORD, ND_CAT_AVX512, ND_SET_AVX512F, 1347, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_H, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2233 Instruction:"VPRORQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /0 ib"/"VAMI" + { + ND_INS_VPRORQ, ND_CAT_AVX512, ND_SET_AVX512F, 1348, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_H, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2234 Instruction:"VPRORVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x14 /r"/"RAVM" + { + ND_INS_VPRORVD, ND_CAT_AVX512, ND_SET_AVX512F, 1349, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2235 Instruction:"VPRORVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x14 /r"/"RAVM" + { + ND_INS_VPRORVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1350, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2236 Instruction:"VPROTB Vdq,Wdq,Ib" Encoding:"xop m:8 0xC0 /r ib"/"RMI" + { + ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1351, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2237 Instruction:"VPROTB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x90 /r"/"RMV" + { + ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1351, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2238 Instruction:"VPROTB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x90 /r"/"RVM" + { + ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1351, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2239 Instruction:"VPROTD Vdq,Wdq,Ib" Encoding:"xop m:8 0xC2 /r ib"/"RMI" + { + ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1352, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2240 Instruction:"VPROTD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x92 /r"/"RMV" + { + ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1352, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2241 Instruction:"VPROTD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x92 /r"/"RVM" + { + ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1352, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2242 Instruction:"VPROTQ Vdq,Wdq,Ib" Encoding:"xop m:8 0xC3 /r ib"/"RMI" + { + ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1353, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2243 Instruction:"VPROTQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x93 /r"/"RMV" + { + ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1353, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2244 Instruction:"VPROTQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x93 /r"/"RVM" + { + ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1353, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2245 Instruction:"VPROTW Vdq,Wdq,Ib" Encoding:"xop m:8 0xC1 /r ib"/"RMI" + { + ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1354, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2246 Instruction:"VPROTW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x91 /r"/"RMV" + { + ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1354, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2247 Instruction:"VPROTW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x91 /r"/"RVM" + { + ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1354, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2248 Instruction:"VPSADBW Vn,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF6 /r"/"RVM" + { + ND_INS_VPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1355, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2249 Instruction:"VPSADBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF6 /r"/"RVM" + { + ND_INS_VPSADBW, ND_CAT_AVX, ND_SET_AVX, 1355, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2250 Instruction:"VPSCATTERDD Mvm32n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0xA0 /r:mem vsib"/"MAR" + { + ND_INS_VPSCATTERDD, ND_CAT_SCATTER, ND_SET_AVX512F, 1356, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_vm32n, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, 0, 0), + }, + + // Pos:2251 Instruction:"VPSCATTERDQ Mvm32h{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA0 /r:mem vsib"/"MAR" + { + ND_INS_VPSCATTERDQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1357, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_vm32h, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, 0, 0), + }, + + // Pos:2252 Instruction:"VPSCATTERQD Mvm64n{K},aKq,Vh" Encoding:"evex m:2 p:1 l:x w:0 0xA1 /r:mem vsib"/"MAR" + { + ND_INS_VPSCATTERQD, ND_CAT_SCATTER, ND_SET_AVX512F, 1358, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_vm64n, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_h, ND_OPF_RW, 0, 0), + }, + + // Pos:2253 Instruction:"VPSCATTERQQ Mvm64n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA1 /r:mem vsib"/"MAR" + { + ND_INS_VPSCATTERQQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1359, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_vm64n, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, 0, 0), + }, + + // Pos:2254 Instruction:"VPSHAB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x98 /r"/"RMV" + { + ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1360, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2255 Instruction:"VPSHAB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x98 /r"/"RVM" + { + ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1360, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2256 Instruction:"VPSHAD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9A /r"/"RMV" + { + ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1361, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2257 Instruction:"VPSHAD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9A /r"/"RVM" + { + ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1361, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2258 Instruction:"VPSHAQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9B /r"/"RMV" + { + ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1362, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2259 Instruction:"VPSHAQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9B /r"/"RVM" + { + ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1362, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2260 Instruction:"VPSHAW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x99 /r"/"RMV" + { + ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1363, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2261 Instruction:"VPSHAW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x99 /r"/"RVM" + { + ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1363, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2262 Instruction:"VPSHLB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x94 /r"/"RMV" + { + ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1364, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2263 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x94 /r"/"RVM" + { + ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1364, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2264 Instruction:"VPSHLB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x95 /r"/"RMV" + { + ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1364, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2265 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x95 /r"/"RVM" + { + ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1364, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2266 Instruction:"VPSHLB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x96 /r"/"RMV" + { + ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1364, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2267 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x96 /r"/"RVM" + { + ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1364, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2268 Instruction:"VPSHLDD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x71 /r ib"/"RAVMI" + { + ND_INS_VPSHLDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1365, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2269 Instruction:"VPSHLDQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x71 /r ib"/"RAVMI" + { + ND_INS_VPSHLDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1366, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2270 Instruction:"VPSHLDVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x71 /r"/"RAVM" + { + ND_INS_VPSHLDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1367, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2271 Instruction:"VPSHLDVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x71 /r"/"RAVM" + { + ND_INS_VPSHLDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1368, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2272 Instruction:"VPSHLDVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x70 /r"/"RAVM" + { + ND_INS_VPSHLDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1369, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2273 Instruction:"VPSHLDW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x70 /r ib"/"RAVMI" + { + ND_INS_VPSHLDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1370, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2274 Instruction:"VPSHLQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x97 /r"/"RMV" + { + ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1371, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2275 Instruction:"VPSHLQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x97 /r"/"RVM" + { + ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1371, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2276 Instruction:"VPSHRDD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x73 /r ib"/"RAVMI" + { + ND_INS_VPSHRDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1372, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2277 Instruction:"VPSHRDQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x73 /r ib"/"RAVMI" + { + ND_INS_VPSHRDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1373, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2278 Instruction:"VPSHRDVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x73 /r"/"RAVM" + { + ND_INS_VPSHRDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1374, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2279 Instruction:"VPSHRDVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x73 /r"/"RAVM" + { + ND_INS_VPSHRDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1375, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2280 Instruction:"VPSHRDVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x72 /r"/"RAVM" + { + ND_INS_VPSHRDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1376, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2281 Instruction:"VPSHRDW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x72 /r ib"/"RAVMI" + { + ND_INS_VPSHRDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1377, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2282 Instruction:"VPSHUFB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x00 /r"/"RAVM" + { + ND_INS_VPSHUFB, ND_CAT_AVX512, ND_SET_AVX512BW, 1378, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2283 Instruction:"VPSHUFB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x00 /r"/"RVM" + { + ND_INS_VPSHUFB, ND_CAT_AVX, ND_SET_AVX, 1378, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2284 Instruction:"VPSHUFBITQMB rK{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x8F /r"/"RAVM" + { + ND_INS_VPSHUFBITQMB, ND_CAT_AVX512VBMI, ND_SET_AVX512BITALG, 1379, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2285 Instruction:"VPSHUFD Vn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x70 /r ib"/"RAMI" + { + ND_INS_VPSHUFD, ND_CAT_AVX512, ND_SET_AVX512F, 1380, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2286 Instruction:"VPSHUFD Vx,Wx,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x70 /r ib"/"RMI" + { + ND_INS_VPSHUFD, ND_CAT_AVX, ND_SET_AVX, 1380, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2287 Instruction:"VPSHUFHW Vn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:2 l:x w:i 0x70 /r ib"/"RAMI" + { + ND_INS_VPSHUFHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1381, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2288 Instruction:"VPSHUFHW Vx,Wx,Ib" Encoding:"vex m:1 p:2 l:x w:i 0x70 /r ib"/"RMI" + { + ND_INS_VPSHUFHW, ND_CAT_AVX, ND_SET_AVX, 1381, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2289 Instruction:"VPSHUFLW Vn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:3 l:x w:i 0x70 /r ib"/"RAMI" + { + ND_INS_VPSHUFLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1382, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2290 Instruction:"VPSHUFLW Vx,Wx,Ib" Encoding:"vex m:1 p:3 l:x w:i 0x70 /r ib"/"RMI" + { + ND_INS_VPSHUFLW, ND_CAT_AVX, ND_SET_AVX, 1382, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2291 Instruction:"VPSIGNB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x08 /r"/"RVM" + { + ND_INS_VPSIGNB, ND_CAT_AVX, ND_SET_AVX, 1383, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2292 Instruction:"VPSIGND Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0A /r"/"RVM" + { + ND_INS_VPSIGND, ND_CAT_AVX, ND_SET_AVX, 1384, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2293 Instruction:"VPSIGNW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x09 /r"/"RVM" + { + ND_INS_VPSIGNW, ND_CAT_AVX, ND_SET_AVX, 1385, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2294 Instruction:"VPSLLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /6 ib"/"VAMI" + { + ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1386, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_H, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2295 Instruction:"VPSLLD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xF2 /r"/"RAVM" + { + ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1386, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2296 Instruction:"VPSLLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /6:reg ib"/"VMI" + { + ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1386, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_H, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2297 Instruction:"VPSLLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF2 /r"/"RVM" + { + ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1386, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2298 Instruction:"VPSLLDQ Hn,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /7 ib"/"VMI" + { + ND_INS_VPSLLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1387, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_H, ND_OPS_n, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2299 Instruction:"VPSLLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /7:reg ib"/"VMI" + { + ND_INS_VPSLLDQ, ND_CAT_AVX, ND_SET_AVX, 1387, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_H, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2300 Instruction:"VPSLLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /6 ib"/"VAMI" + { + ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1388, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_H, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2301 Instruction:"VPSLLQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xF3 /r"/"RAVM" + { + ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1388, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2302 Instruction:"VPSLLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /6:reg ib"/"VMI" + { + ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1388, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_H, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2303 Instruction:"VPSLLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF3 /r"/"RVM" + { + ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1388, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2304 Instruction:"VPSLLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x47 /r"/"RAVM" + { + ND_INS_VPSLLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1389, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2305 Instruction:"VPSLLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x47 /r"/"RVM" + { + ND_INS_VPSLLVD, ND_CAT_AVX2, ND_SET_AVX2, 1389, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2306 Instruction:"VPSLLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x47 /r"/"RAVM" + { + ND_INS_VPSLLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1390, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2307 Instruction:"VPSLLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x47 /r"/"RVM" + { + ND_INS_VPSLLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1390, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2308 Instruction:"VPSLLVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x12 /r"/"RAVM" + { + ND_INS_VPSLLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1391, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2309 Instruction:"VPSLLW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /6 ib"/"VAMI" + { + ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1392, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_H, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2310 Instruction:"VPSLLW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xF1 /r"/"RAVM" + { + ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1392, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2311 Instruction:"VPSLLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /6:reg ib"/"VMI" + { + ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1392, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_H, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2312 Instruction:"VPSLLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF1 /r"/"RVM" + { + ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1392, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2313 Instruction:"VPSRAD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /4 ib"/"VAMI" + { + ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1393, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_H, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2314 Instruction:"VPSRAD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xE2 /r"/"RAVM" + { + ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1393, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2315 Instruction:"VPSRAD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /4:reg ib"/"VMI" + { + ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1393, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_H, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2316 Instruction:"VPSRAD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE2 /r"/"RVM" + { + ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1393, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2317 Instruction:"VPSRAQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /4 ib"/"VAMI" + { + ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1394, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_H, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2318 Instruction:"VPSRAQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xE2 /r"/"RAVM" + { + ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1394, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2319 Instruction:"VPSRAVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x46 /r"/"RAVM" + { + ND_INS_VPSRAVD, ND_CAT_AVX512, ND_SET_AVX512F, 1395, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2320 Instruction:"VPSRAVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x46 /r"/"RVM" + { + ND_INS_VPSRAVD, ND_CAT_AVX2, ND_SET_AVX2, 1395, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2321 Instruction:"VPSRAVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x46 /r"/"RAVM" + { + ND_INS_VPSRAVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1396, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2322 Instruction:"VPSRAVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x11 /r"/"RAVM" + { + ND_INS_VPSRAVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1397, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2323 Instruction:"VPSRAW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /4 ib"/"VAMI" + { + ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1398, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_H, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2324 Instruction:"VPSRAW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xE1 /r"/"RAVM" + { + ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1398, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2325 Instruction:"VPSRAW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /4:reg ib"/"VMI" + { + ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1398, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_H, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2326 Instruction:"VPSRAW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE1 /r"/"RVM" + { + ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1398, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2327 Instruction:"VPSRLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /2 ib"/"VAMI" + { + ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1399, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_H, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2328 Instruction:"VPSRLD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xD2 /r"/"RAVM" + { + ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1399, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2329 Instruction:"VPSRLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /2:reg ib"/"VMI" + { + ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1399, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_H, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2330 Instruction:"VPSRLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD2 /r"/"RVM" + { + ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1399, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2331 Instruction:"VPSRLDQ Hn,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /3 ib"/"VMI" + { + ND_INS_VPSRLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1400, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_H, ND_OPS_n, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2332 Instruction:"VPSRLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /3:reg ib"/"VMI" + { + ND_INS_VPSRLDQ, ND_CAT_AVX, ND_SET_AVX, 1400, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_H, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2333 Instruction:"VPSRLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /2 ib"/"VAMI" + { + ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1401, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_H, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2334 Instruction:"VPSRLQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xD3 /r"/"RAVM" + { + ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1401, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2335 Instruction:"VPSRLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /2:reg ib"/"VMI" + { + ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1401, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_H, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2336 Instruction:"VPSRLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD3 /r"/"RVM" + { + ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1401, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2337 Instruction:"VPSRLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x45 /r"/"RAVM" + { + ND_INS_VPSRLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1402, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2338 Instruction:"VPSRLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x45 /r"/"RVM" + { + ND_INS_VPSRLVD, ND_CAT_AVX2, ND_SET_AVX2, 1402, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2339 Instruction:"VPSRLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x45 /r"/"RAVM" + { + ND_INS_VPSRLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1403, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2340 Instruction:"VPSRLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x45 /r"/"RVM" + { + ND_INS_VPSRLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1403, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2341 Instruction:"VPSRLVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x10 /r"/"RAVM" + { + ND_INS_VPSRLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1404, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2342 Instruction:"VPSRLW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /2 ib"/"VAMI" + { + ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1405, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_H, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2343 Instruction:"VPSRLW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xD1 /r"/"RAVM" + { + ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1405, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2344 Instruction:"VPSRLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /2:reg ib"/"VMI" + { + ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1405, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_H, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2345 Instruction:"VPSRLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD1 /r"/"RVM" + { + ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1405, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:2346 Instruction:"VPSUBB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF8 /r"/"RAVM" + { + ND_INS_VPSUBB, ND_CAT_AVX512, ND_SET_AVX512BW, 1406, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2347 Instruction:"VPSUBB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF8 /r"/"RVM" + { + ND_INS_VPSUBB, ND_CAT_AVX, ND_SET_AVX, 1406, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2348 Instruction:"VPSUBD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFA /r"/"RAVM" + { + ND_INS_VPSUBD, ND_CAT_AVX512, ND_SET_AVX512F, 1407, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2349 Instruction:"VPSUBD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFA /r"/"RVM" + { + ND_INS_VPSUBD, ND_CAT_AVX, ND_SET_AVX, 1407, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2350 Instruction:"VPSUBQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xFB /r"/"RAVM" + { + ND_INS_VPSUBQ, ND_CAT_AVX512, ND_SET_AVX512F, 1408, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2351 Instruction:"VPSUBQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFB /r"/"RVM" + { + ND_INS_VPSUBQ, ND_CAT_AVX, ND_SET_AVX, 1408, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2352 Instruction:"VPSUBSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE8 /r"/"RAVM" + { + ND_INS_VPSUBSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1409, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2353 Instruction:"VPSUBSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE8 /r"/"RVM" + { + ND_INS_VPSUBSB, ND_CAT_AVX, ND_SET_AVX, 1409, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2354 Instruction:"VPSUBSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE9 /r"/"RAVM" + { + ND_INS_VPSUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1410, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2355 Instruction:"VPSUBSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE9 /r"/"RVM" + { + ND_INS_VPSUBSW, ND_CAT_AVX, ND_SET_AVX, 1410, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2356 Instruction:"VPSUBUSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD8 /r"/"RAVM" + { + ND_INS_VPSUBUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1411, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2357 Instruction:"VPSUBUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD8 /r"/"RVM" + { + ND_INS_VPSUBUSB, ND_CAT_AVX, ND_SET_AVX, 1411, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2358 Instruction:"VPSUBUSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD9 /r"/"RAVM" + { + ND_INS_VPSUBUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1412, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2359 Instruction:"VPSUBUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD9 /r"/"RVM" + { + ND_INS_VPSUBUSW, ND_CAT_AVX, ND_SET_AVX, 1412, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2360 Instruction:"VPSUBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF9 /r"/"RAVM" + { + ND_INS_VPSUBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1413, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2361 Instruction:"VPSUBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF9 /r"/"RVM" + { + ND_INS_VPSUBW, ND_CAT_AVX, ND_SET_AVX, 1413, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2362 Instruction:"VPTERNLOGD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x25 /r ib"/"RAVMI" + { + ND_INS_VPTERNLOGD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1414, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2363 Instruction:"VPTERNLOGQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x25 /r ib"/"RAVMI" + { + ND_INS_VPTERNLOGQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1415, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2364 Instruction:"VPTEST Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x17 /r"/"RM" + { + ND_INS_VPTEST, ND_CAT_LOGICAL, ND_SET_AVX, 1416, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2365 Instruction:"VPTESTMB rKq{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x26 /r"/"RAVM" + { + ND_INS_VPTESTMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1417, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2366 Instruction:"VPTESTMD rKq{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x27 /r"/"RAVM" + { + ND_INS_VPTESTMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1418, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2367 Instruction:"VPTESTMQ rKq{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x27 /r"/"RAVM" + { + ND_INS_VPTESTMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1419, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2368 Instruction:"VPTESTMW rKq{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x26 /r"/"RAVM" + { + ND_INS_VPTESTMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1420, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2369 Instruction:"VPTESTNMB rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:2 l:x w:0 0x26 /r"/"RAVM" + { + ND_INS_VPTESTNMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1421, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2370 Instruction:"VPTESTNMD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x27 /r"/"RAVM" + { + ND_INS_VPTESTNMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1422, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2371 Instruction:"VPTESTNMQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:2 l:x w:1 0x27 /r"/"RAVM" + { + ND_INS_VPTESTNMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1423, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2372 Instruction:"VPTESTNMW rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:2 l:x w:1 0x26 /r"/"RAVM" + { + ND_INS_VPTESTNMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1424, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2373 Instruction:"VPUNPCKHBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x68 /r"/"RAVM" + { + ND_INS_VPUNPCKHBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1425, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2374 Instruction:"VPUNPCKHBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x68 /r"/"RVM" + { + ND_INS_VPUNPCKHBW, ND_CAT_AVX, ND_SET_AVX, 1425, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2375 Instruction:"VPUNPCKHDQ Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6A /r"/"RAVM" + { + ND_INS_VPUNPCKHDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1426, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2376 Instruction:"VPUNPCKHDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6A /r"/"RVM" + { + ND_INS_VPUNPCKHDQ, ND_CAT_AVX, ND_SET_AVX, 1426, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2377 Instruction:"VPUNPCKHQDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6D /r"/"RAVM" + { + ND_INS_VPUNPCKHQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1427, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2378 Instruction:"VPUNPCKHQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6D /r"/"RVM" + { + ND_INS_VPUNPCKHQDQ, ND_CAT_AVX, ND_SET_AVX, 1427, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2379 Instruction:"VPUNPCKHWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x69 /r"/"RAVM" + { + ND_INS_VPUNPCKHWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1428, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2380 Instruction:"VPUNPCKHWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x69 /r"/"RVM" + { + ND_INS_VPUNPCKHWD, ND_CAT_AVX, ND_SET_AVX, 1428, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2381 Instruction:"VPUNPCKLBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:x 0x60 /r"/"RAVM" + { + ND_INS_VPUNPCKLBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1429, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2382 Instruction:"VPUNPCKLBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x60 /r"/"RVM" + { + ND_INS_VPUNPCKLBW, ND_CAT_AVX, ND_SET_AVX, 1429, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2383 Instruction:"VPUNPCKLDQ Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x62 /r"/"RAVM" + { + ND_INS_VPUNPCKLDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1430, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2384 Instruction:"VPUNPCKLDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x62 /r"/"RVM" + { + ND_INS_VPUNPCKLDQ, ND_CAT_AVX, ND_SET_AVX, 1430, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2385 Instruction:"VPUNPCKLQDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6C /r"/"RAVM" + { + ND_INS_VPUNPCKLQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1431, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2386 Instruction:"VPUNPCKLQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6C /r"/"RVM" + { + ND_INS_VPUNPCKLQDQ, ND_CAT_AVX, ND_SET_AVX, 1431, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2387 Instruction:"VPUNPCKLWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:x 0x61 /r"/"RAVM" + { + ND_INS_VPUNPCKLWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1432, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:2388 Instruction:"VPUNPCKLWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x61 /r"/"RVM" + { + ND_INS_VPUNPCKLWD, ND_CAT_AVX, ND_SET_AVX, 1432, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2389 Instruction:"VPXOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEF /r"/"RVM" + { + ND_INS_VPXOR, ND_CAT_LOGICAL, ND_SET_AVX, 1433, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2390 Instruction:"VPXORD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEF /r"/"RAVM" + { + ND_INS_VPXORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1434, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2391 Instruction:"VPXORQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEF /r"/"RAVM" + { + ND_INS_VPXORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1435, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2392 Instruction:"VRANGEPD Vn{K}{z},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x50 /r ib"/"RAVMI" + { + ND_INS_VRANGEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1436, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2393 Instruction:"VRANGEPS Vn{K}{z},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x50 /r ib"/"RAVMI" + { + ND_INS_VRANGEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1437, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2394 Instruction:"VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x51 /r ib"/"RAVMI" + { + ND_INS_VRANGESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1438, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2395 Instruction:"VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x51 /r ib"/"RAVMI" + { + ND_INS_VRANGESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1439, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2396 Instruction:"VRCP14PD Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4C /r"/"RAM" + { + ND_INS_VRCP14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1440, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2397 Instruction:"VRCP14PS Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4C /r"/"RAM" + { + ND_INS_VRCP14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1441, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2398 Instruction:"VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4D /r"/"RAVM" + { + ND_INS_VRCP14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1442, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:2399 Instruction:"VRCP14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4D /r"/"RAVM" + { + ND_INS_VRCP14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1443, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:2400 Instruction:"VRCP28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCA /r"/"RAM" + { + ND_INS_VRCP28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1444, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_oq, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), + }, + + // Pos:2401 Instruction:"VRCP28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCA /r"/"RAM" + { + ND_INS_VRCP28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1445, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_oq, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + + // Pos:2402 Instruction:"VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCB /r"/"RAVM" + { + ND_INS_VRCP28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1446, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_SAE, 0), + }, + + // Pos:2403 Instruction:"VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCB /r"/"RAVM" + { + ND_INS_VRCP28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1447, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_SAE, 0), + }, + + // Pos:2404 Instruction:"VRCPPS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x53 /r"/"RM" + { + ND_INS_VRCPPS, ND_CAT_AVX, ND_SET_AVX, 1448, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:2405 Instruction:"VRCPSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x53 /r"/"RVM" + { + ND_INS_VRCPSS, ND_CAT_AVX, ND_SET_AVX, 1449, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:2406 Instruction:"VREDUCEPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x56 /r ib"/"RAMI" + { + ND_INS_VREDUCEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1450, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2407 Instruction:"VREDUCEPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x56 /r ib"/"RAMI" + { + ND_INS_VREDUCEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1451, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2408 Instruction:"VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x57 /r ib"/"RAVMI" + { + ND_INS_VREDUCESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1452, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2409 Instruction:"VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x57 /r ib"/"RAVMI" + { + ND_INS_VREDUCESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1453, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2410 Instruction:"VRNDSCALEPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x09 /r ib"/"RAMI" + { + ND_INS_VRNDSCALEPD, ND_CAT_AVX512, ND_SET_AVX512F, 1454, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2411 Instruction:"VRNDSCALEPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x08 /r ib"/"RAMI" + { + ND_INS_VRNDSCALEPS, ND_CAT_AVX512, ND_SET_AVX512F, 1455, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2412 Instruction:"VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x0B /r ib"/"RAVMI" + { + ND_INS_VRNDSCALESD, ND_CAT_AVX512, ND_SET_AVX512F, 1456, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2413 Instruction:"VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x0A /r ib"/"RAVMI" + { + ND_INS_VRNDSCALESS, ND_CAT_AVX512, ND_SET_AVX512F, 1457, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2414 Instruction:"VROUNDPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x09 /r ib"/"RMI" + { + ND_INS_VROUNDPD, ND_CAT_AVX, ND_SET_AVX, 1458, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2415 Instruction:"VROUNDPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x08 /r ib"/"RMI" + { + ND_INS_VROUNDPS, ND_CAT_AVX, ND_SET_AVX, 1459, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2416 Instruction:"VROUNDSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0B /r ib"/"RVMI" + { + ND_INS_VROUNDSD, ND_CAT_AVX, ND_SET_AVX, 1460, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2417 Instruction:"VROUNDSS Vss,Hss,Wss,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0A /r ib"/"RVMI" + { + ND_INS_VROUNDSS, ND_CAT_AVX, ND_SET_AVX, 1461, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2418 Instruction:"VRSQRT14PD Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4E /r"/"RAM" + { + ND_INS_VRSQRT14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1462, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2419 Instruction:"VRSQRT14PS Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4E /r"/"RAM" + { + ND_INS_VRSQRT14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1463, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2420 Instruction:"VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4F /r"/"RAVM" + { + ND_INS_VRSQRT14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1464, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:2421 Instruction:"VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4F /r"/"RAVM" + { + ND_INS_VRSQRT14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1465, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:2422 Instruction:"VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCC /r"/"RAM" + { + ND_INS_VRSQRT28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1466, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_oq, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), + }, + + // Pos:2423 Instruction:"VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCC /r"/"RAM" + { + ND_INS_VRSQRT28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1467, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_oq, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + + // Pos:2424 Instruction:"VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCD /r"/"RAVM" + { + ND_INS_VRSQRT28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1468, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_SAE, 0), + }, + + // Pos:2425 Instruction:"VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCD /r"/"RAVM" + { + ND_INS_VRSQRT28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1469, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_SAE, 0), + }, + + // Pos:2426 Instruction:"VRSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x52 /r"/"RM" + { + ND_INS_VRSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1470, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2427 Instruction:"VRSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x52 /r"/"RVM" + { + ND_INS_VRSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1471, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:2428 Instruction:"VSCALEFPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x2C /r"/"RAVM" + { + ND_INS_VSCALEFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1472, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:2429 Instruction:"VSCALEFPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x2C /r"/"RAVM" + { + ND_INS_VSCALEFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1473, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:2430 Instruction:"VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x2D /r"/"RAVM" + { + ND_INS_VSCALEFSD, ND_CAT_AVX512, ND_SET_AVX512F, 1474, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:2431 Instruction:"VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x2D /r"/"RAVM" + { + ND_INS_VSCALEFSS, ND_CAT_AVX512, ND_SET_AVX512F, 1475, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:2432 Instruction:"VSCATTERDPD Mvm32h{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib"/"MAR" + { + ND_INS_VSCATTERDPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1476, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_vm32h, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, 0, 0), + }, + + // Pos:2433 Instruction:"VSCATTERDPS Mvm32n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib"/"MAR" + { + ND_INS_VSCATTERDPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1477, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_vm32n, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, 0, 0), + }, + + // Pos:2434 Instruction:"VSCATTERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /5:mem vsib"/"MA" + { + ND_INS_VSCATTERPF0DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1478, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_vm32h, ND_OPF_R, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:2435 Instruction:"VSCATTERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /5:mem vsib"/"MA" + { + ND_INS_VSCATTERPF0DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1479, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_vm32n, ND_OPF_R, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:2436 Instruction:"VSCATTERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /5:mem vsib"/"MA" + { + ND_INS_VSCATTERPF0QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1480, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_vm64n, ND_OPF_R, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:2437 Instruction:"VSCATTERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /5:mem vsib"/"MA" + { + ND_INS_VSCATTERPF0QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1481, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_vm64n, ND_OPF_R, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:2438 Instruction:"VSCATTERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /6:mem vsib"/"MA" + { + ND_INS_VSCATTERPF1DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1482, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_vm32h, ND_OPF_R, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:2439 Instruction:"VSCATTERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /6:mem vsib"/"MA" + { + ND_INS_VSCATTERPF1DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1483, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_vm32n, ND_OPF_R, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:2440 Instruction:"VSCATTERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /6:mem vsib"/"MA" + { + ND_INS_VSCATTERPF1QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1484, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_vm64n, ND_OPF_R, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:2441 Instruction:"VSCATTERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /6:mem vsib"/"MA" + { + ND_INS_VSCATTERPF1QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1485, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_vm64n, ND_OPF_R, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:2442 Instruction:"VSCATTERQPD Mvm64n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib"/"MAR" + { + ND_INS_VSCATTERQPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1486, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_vm64n, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, 0, 0), + }, + + // Pos:2443 Instruction:"VSCATTERQPS Mvm64n{K},aKq,Vh" Encoding:"evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib"/"MAR" + { + ND_INS_VSCATTERQPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1487, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_vm64n, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_h, ND_OPF_RW, 0, 0), + }, + + // Pos:2444 Instruction:"VSHUFF32X4 Vu{K}{z},aKq,Hu,Wu|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x23 /r ib"/"RAVMI" + { + ND_INS_VSHUFF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1488, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_u, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_u, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_u, ND_OPF_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2445 Instruction:"VSHUFF64X2 Vu{K}{z},aKq,Hu,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x23 /r ib"/"RAVMI" + { + ND_INS_VSHUFF64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1489, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_u, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_u, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_u, ND_OPF_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2446 Instruction:"VSHUFI32X4 Vu{K}{z},aKq,Hu,Wu|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x43 /r ib"/"RAVMI" + { + ND_INS_VSHUFI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1490, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_u, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_u, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_u, ND_OPF_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2447 Instruction:"VSHUFI64X2 Vu{K}{z},aKq,Hu,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x43 /r ib"/"RAVMI" + { + ND_INS_VSHUFI64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1491, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_u, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_u, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_u, ND_OPF_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2448 Instruction:"VSHUFPD Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC6 /r ib"/"RAVMI" + { + ND_INS_VSHUFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1492, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2449 Instruction:"VSHUFPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC6 /r ib"/"RVMI" + { + ND_INS_VSHUFPD, ND_CAT_AVX, ND_SET_AVX, 1492, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2450 Instruction:"VSHUFPS Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC6 /r ib"/"RAVMI" + { + ND_INS_VSHUFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1493, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2451 Instruction:"VSHUFPS Vps,Hps,Wps,Ib" Encoding:"vex m:1 p:0 l:x w:i 0xC6 /r ib"/"RVMI" + { + ND_INS_VSHUFPS, ND_CAT_AVX, ND_SET_AVX, 1493, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:2452 Instruction:"VSQRTPD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x51 /r"/"RAM" + { + ND_INS_VSQRTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1494, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:2453 Instruction:"VSQRTPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x51 /r"/"RM" + { + ND_INS_VSQRTPD, ND_CAT_AVX, ND_SET_AVX, 1494, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2454 Instruction:"VSQRTPS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x51 /r"/"RAM" + { + ND_INS_VSQRTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1495, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:2455 Instruction:"VSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x51 /r"/"RM" + { + ND_INS_VSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1495, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2456 Instruction:"VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x51 /r"/"RAVM" + { + ND_INS_VSQRTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1496, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:2457 Instruction:"VSQRTSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x51 /r"/"RVM" + { + ND_INS_VSQRTSD, ND_CAT_AVX, ND_SET_AVX, 1496, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:2458 Instruction:"VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x51 /r"/"RAVM" + { + ND_INS_VSQRTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1497, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:2459 Instruction:"VSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x51 /r"/"RVM" + { + ND_INS_VSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1497, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:2460 Instruction:"VSTMXCSR Md" Encoding:"vex m:1 p:0 0xAE /3:mem"/"M" + { + ND_INS_VSTMXCSR, ND_CAT_AVX, ND_SET_AVX, 1498, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(1, 1), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:2461 Instruction:"VSUBPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5C /r"/"RAVM" + { + ND_INS_VSUBPD, ND_CAT_AVX512, ND_SET_AVX512F, 1499, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:2462 Instruction:"VSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5C /r"/"RVM" + { + ND_INS_VSUBPD, ND_CAT_AVX, ND_SET_AVX, 1499, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:2463 Instruction:"VSUBPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5C /r"/"RAVM" + { + ND_INS_VSUBPS, ND_CAT_AVX512, ND_SET_AVX512F, 1500, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:2464 Instruction:"VSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5C /r"/"RVM" + { + ND_INS_VSUBPS, ND_CAT_AVX, ND_SET_AVX, 1500, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:2465 Instruction:"VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5C /r"/"RAVM" + { + ND_INS_VSUBSD, ND_CAT_AVX512, ND_SET_AVX512F, 1501, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:2466 Instruction:"VSUBSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5C /r"/"RVM" + { + ND_INS_VSUBSD, ND_CAT_AVX, ND_SET_AVX, 1501, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:2467 Instruction:"VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5C /r"/"RAVM" + { + ND_INS_VSUBSS, ND_CAT_AVX512, ND_SET_AVX512F, 1502, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:2468 Instruction:"VSUBSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5C /r"/"RVM" + { + ND_INS_VSUBSS, ND_CAT_AVX, ND_SET_AVX, 1502, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:2469 Instruction:"VTESTPD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0F /r"/"RM" + { + ND_INS_VTESTPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1503, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2470 Instruction:"VTESTPS Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0E /r"/"RM" + { + ND_INS_VTESTPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1504, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2471 Instruction:"VUCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2E /r"/"RM" + { + ND_INS_VUCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 1505, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_SAE, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2472 Instruction:"VUCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2E /r"/"RM" + { + ND_INS_VUCOMISD, ND_CAT_AVX, ND_SET_AVX, 1505, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2473 Instruction:"VUCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2E /r"/"RM" + { + ND_INS_VUCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 1506, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_SAE, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2474 Instruction:"VUCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2E /r"/"RM" + { + ND_INS_VUCOMISS, ND_CAT_AVX, ND_SET_AVX, 1506, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2475 Instruction:"VUNPCKHPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x15 /r"/"RAVM" + { + ND_INS_VUNPCKHPD, ND_CAT_AVX512, ND_SET_AVX512F, 1507, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2476 Instruction:"VUNPCKHPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x15 /r"/"RVM" + { + ND_INS_VUNPCKHPD, ND_CAT_AVX, ND_SET_AVX, 1507, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2477 Instruction:"VUNPCKHPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x15 /r"/"RAVM" + { + ND_INS_VUNPCKHPS, ND_CAT_AVX512, ND_SET_AVX512F, 1508, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2478 Instruction:"VUNPCKHPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x15 /r"/"RVM" + { + ND_INS_VUNPCKHPS, ND_CAT_AVX, ND_SET_AVX, 1508, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2479 Instruction:"VUNPCKLPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x14 /r"/"RAVM" + { + ND_INS_VUNPCKLPD, ND_CAT_AVX512, ND_SET_AVX512F, 1509, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2480 Instruction:"VUNPCKLPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x14 /r"/"RVM" + { + ND_INS_VUNPCKLPD, ND_CAT_AVX, ND_SET_AVX, 1509, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2481 Instruction:"VUNPCKLPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x14 /r"/"RAVM" + { + ND_INS_VUNPCKLPS, ND_CAT_AVX512, ND_SET_AVX512F, 1510, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2482 Instruction:"VUNPCKLPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x14 /r"/"RVM" + { + ND_INS_VUNPCKLPS, ND_CAT_AVX, ND_SET_AVX, 1510, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:2483 Instruction:"VXORPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x57 /r"/"RAVM" + { + ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1511, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:2484 Instruction:"VXORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x57 /r"/"RVM" + { + ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1511, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:2485 Instruction:"VXORPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x57 /r"/"RAVM" + { + ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1512, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:2486 Instruction:"VXORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x57 /r"/"RVM" + { + ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1512, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:2487 Instruction:"VZEROALL" Encoding:"vex m:1 p:0 l:1 0x77"/"" + { + ND_INS_VZEROALL, ND_CAT_AVX, ND_SET_AVX, 1513, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(0, 1), 0, ND_EXT_8, ND_EXC_SSE_AVX, 0, 0, 0, 0, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2488 Instruction:"VZEROUPPER" Encoding:"vex m:1 p:0 l:0 0x77"/"" + { + ND_INS_VZEROUPPER, ND_CAT_AVX, ND_SET_AVX, 1514, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(0, 1), 0, ND_EXT_8, ND_EXC_SSE_AVX, 0, 0, 0, 0, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2489 Instruction:"WAIT" Encoding:"0x9B"/"" + { + ND_INS_WAIT, ND_CAT_X87_ALU, ND_SET_X87, 1515, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:2490 Instruction:"WBINVD" Encoding:"NP 0x0F 0x09"/"" + { + ND_INS_WBINVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 1516, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:2491 Instruction:"WBNOINVD" Encoding:"0xF3 0x0F 0x09"/"" + { + ND_INS_WBNOINVD, ND_CAT_WBNOINVD, ND_SET_WBNOINVD, 1517, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, ND_CFF_WBNOINVD, + 0, + 0, + 0, + 0, + }, + + // Pos:2492 Instruction:"WRFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /2:reg"/"M" + { + ND_INS_WRFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1518, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_MSR_FSBASE, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2493 Instruction:"WRGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /3:reg"/"M" + { + ND_INS_WRGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1519, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_MSR_GSBASE, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2494 Instruction:"WRMSR" Encoding:"0x0F 0x30"/"" + { + ND_INS_WRMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 1520, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, ND_CFF_MSR, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2495 Instruction:"WRPKRU" Encoding:"NP 0x0F 0x01 /0xEF"/"" + { + ND_INS_WRPKRU, ND_CAT_MISC, ND_SET_PKU, 1521, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PKU, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_PKRU, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2496 Instruction:"WRSHR Ed" Encoding:"cyrix 0x0F 0x37 /r"/"M" + { + ND_INS_WRSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 1522, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_d, ND_OPF_W, 0, 0), + }, + + // Pos:2497 Instruction:"WRSSD My,Gy" Encoding:"NP 0x0F 0x38 0xF6 /r:mem"/"MR" + { + ND_INS_WRSS, ND_CAT_CET, ND_SET_CET, 1523, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_G, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:2498 Instruction:"WRSSQ My,Gy" Encoding:"rexw NP 0x0F 0x38 0xF6 /r:mem"/"MR" + { + ND_INS_WRSS, ND_CAT_CET, ND_SET_CET, 1524, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_G, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:2499 Instruction:"WRUSSD My,Gy" Encoding:"0x66 0x0F 0x38 0xF5 /r:mem"/"MR" + { + ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET, 1525, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_G, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:2500 Instruction:"WRUSSQ My,Gy" Encoding:"rexw 0x66 0x0F 0x38 0xF5 /r:mem"/"MR" + { + ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET, 1526, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_G, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:2501 Instruction:"XABORT Ib" Encoding:"0xC6 /0xF8 ib"/"I" + { + ND_INS_XABORT, ND_CAT_UNCOND_BR, ND_SET_TSX, 1527, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, + 0, + 0, + 0, + 0, + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + }, + + // Pos:2502 Instruction:"XADD Eb,Gb" Encoding:"0x0F 0xC0 /r"/"MR" + { + ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1528, + ND_MOD_ANY, + ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2503 Instruction:"XADD Ev,Gv" Encoding:"0x0F 0xC1 /r"/"MR" + { + ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1528, + ND_MOD_ANY, + ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2504 Instruction:"XBEGIN Jz" Encoding:"0xC7 /0xF8 cz"/"D" + { + ND_INS_XBEGIN, ND_CAT_COND_BR, ND_SET_TSX, 1529, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, + 0, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + }, + + // Pos:2505 Instruction:"XCHG Eb,Gb" Encoding:"0x86 /r"/"MR" + { + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1530, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLE_WO_LOCK, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, ND_OPF_RW, 0, 0), + }, + + // Pos:2506 Instruction:"XCHG Ev,Gv" Encoding:"0x87 /r"/"MR" + { + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1530, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLE_WO_LOCK, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_RW, 0, 0), + }, + + // Pos:2507 Instruction:"XCHG rAX,Zv" Encoding:"rex 0x90"/"O" + { + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1530, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + }, + + // Pos:2508 Instruction:"XCHG rAX,Zv" Encoding:"0x91"/"O" + { + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1530, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + }, + + // Pos:2509 Instruction:"XCHG rAX,Zv" Encoding:"0x92"/"O" + { + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1530, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + }, + + // Pos:2510 Instruction:"XCHG rAX,Zv" Encoding:"0x93"/"O" + { + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1530, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + }, + + // Pos:2511 Instruction:"XCHG rAX,Zv" Encoding:"0x94"/"O" + { + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1530, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + }, + + // Pos:2512 Instruction:"XCHG rAX,Zv" Encoding:"0x95"/"O" + { + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1530, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + }, + + // Pos:2513 Instruction:"XCHG rAX,Zv" Encoding:"0x96"/"O" + { + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1530, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + }, + + // Pos:2514 Instruction:"XCHG rAX,Zv" Encoding:"0x97"/"O" + { + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1530, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + }, + + // Pos:2515 Instruction:"XCRYPTCBC" Encoding:"0xF3 0x0F 0xA7 /0xD0"/"" + { + ND_INS_XCRYPTCBC, ND_CAT_PADLOCK, ND_SET_CYRIX, 1531, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:2516 Instruction:"XCRYPTCFB" Encoding:"0xF3 0x0F 0xA7 /0xE0"/"" + { + ND_INS_XCRYPTCFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1532, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:2517 Instruction:"XCRYPTCTR" Encoding:"0xF3 0x0F 0xA7 /0xD8"/"" + { + ND_INS_XCRYPTCTR, ND_CAT_PADLOCK, ND_SET_CYRIX, 1533, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:2518 Instruction:"XCRYPTECB" Encoding:"0xF3 0x0F 0xA7 /0xC8"/"" + { + ND_INS_XCRYPTECB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1534, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:2519 Instruction:"XCRYPTOFB" Encoding:"0xF3 0x0F 0xA7 /0xE8"/"" + { + ND_INS_XCRYPTOFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1535, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:2520 Instruction:"XEND" Encoding:"NP 0x0F 0x01 /0xD5"/"" + { + ND_INS_XEND, ND_CAT_COND_BR, ND_SET_TSX, 1536, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, + 0, + 0, + 0, + 0, + }, + + // Pos:2521 Instruction:"XGETBV" Encoding:"NP 0x0F 0x01 /0xD0"/"" + { + ND_INS_XGETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1537, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_XCR, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:2522 Instruction:"XLATB" Encoding:"0xD7"/"" + { + ND_INS_XLATB, ND_CAT_MISC, ND_SET_I86, 1538, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_MEM_rBX_AL, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:2523 Instruction:"XOR Eb,Gb" Encoding:"0x30 /r"/"MR" + { + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1539, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2524 Instruction:"XOR Ev,Gv" Encoding:"0x31 /r"/"MR" + { + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1539, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2525 Instruction:"XOR Gb,Eb" Encoding:"0x32 /r"/"RM" + { + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1539, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_G, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2526 Instruction:"XOR Gv,Ev" Encoding:"0x33 /r"/"RM" + { + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1539, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2527 Instruction:"XOR AL,Ib" Encoding:"0x34 ib"/"I" + { + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1539, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2528 Instruction:"XOR rAX,Iz" Encoding:"0x35 iz"/"I" + { + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1539, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2529 Instruction:"XOR Eb,Ib" Encoding:"0x80 /6 ib"/"MI" + { + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1539, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2530 Instruction:"XOR Ev,Iz" Encoding:"0x81 /6 iz"/"MI" + { + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1539, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2531 Instruction:"XOR Ev,Iz" Encoding:"0x82 /6 iz"/"MI" + { + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1539, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2532 Instruction:"XOR Ev,Ib" Encoding:"0x83 /6 ib"/"MI" + { + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1539, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2533 Instruction:"XORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x57 /r"/"RM" + { + ND_INS_XORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 1540, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:2534 Instruction:"XORPS Vps,Wps" Encoding:"NP 0x0F 0x57 /r"/"RM" + { + ND_INS_XORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 1541, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:2535 Instruction:"XRESLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE9"/"" + { + ND_INS_XRESLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1542, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TSXLDTRK, + 0, + 0, + 0, + 0, + }, + + // Pos:2536 Instruction:"XRSTOR M?" Encoding:"NP 0x0F 0xAE /5:mem"/"M" + { + ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1543, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_unknown, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2537 Instruction:"XRSTOR64 M?" Encoding:"rexw NP 0x0F 0xAE /5:mem"/"M" + { + ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1544, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_unknown, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2538 Instruction:"XRSTORS M?" Encoding:"NP 0x0F 0xC7 /3:mem"/"M" + { + ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1545, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_unknown, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2539 Instruction:"XRSTORS64 M?" Encoding:"rexw NP 0x0F 0xC7 /3:mem"/"M" + { + ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1546, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_unknown, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2540 Instruction:"XSAVE M?" Encoding:"NP 0x0F 0xAE /4:mem"/"M" + { + ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1547, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_unknown, ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:2541 Instruction:"XSAVE64 M?" Encoding:"rexw NP 0x0F 0xAE /4:mem"/"M" + { + ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1548, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_unknown, ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:2542 Instruction:"XSAVEC M?" Encoding:"NP 0x0F 0xC7 /4:mem"/"M" + { + ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1549, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVEC, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_unknown, ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:2543 Instruction:"XSAVEC64 M?" Encoding:"rexw NP 0x0F 0xC7 /4:mem"/"M" + { + ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1550, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVEC, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_unknown, ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:2544 Instruction:"XSAVEOPT M?" Encoding:"NP 0x0F 0xAE /6:mem"/"M" + { + ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1551, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_unknown, ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:2545 Instruction:"XSAVEOPT64 M?" Encoding:"rexw NP 0x0F 0xAE /6:mem"/"M" + { + ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1552, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_unknown, ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:2546 Instruction:"XSAVES M?" Encoding:"NP 0x0F 0xC7 /5:mem"/"M" + { + ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1553, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_unknown, ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:2547 Instruction:"XSAVES64 M?" Encoding:"rexw NP 0x0F 0xC7 /5:mem"/"M" + { + ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1554, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_unknown, ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:2548 Instruction:"XSETBV" Encoding:"NP 0x0F 0x01 /0xD1"/"" + { + ND_INS_XSETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1555, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_XCR, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2549 Instruction:"XSHA1" Encoding:"0xF3 0x0F 0xA6 /0xC8"/"" + { + ND_INS_XSHA1, ND_CAT_PADLOCK, ND_SET_CYRIX, 1556, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:2550 Instruction:"XSHA256" Encoding:"0xF3 0x0F 0xA6 /0xD0"/"" + { + ND_INS_XSHA256, ND_CAT_PADLOCK, ND_SET_CYRIX, 1557, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:2551 Instruction:"XSTORE" Encoding:"0x0F 0xA7 /0xC0"/"" + { + ND_INS_XSTORE, ND_CAT_PADLOCK, ND_SET_CYRIX, 1558, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:2552 Instruction:"XSUSLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE8"/"" + { + ND_INS_XSUSLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1559, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TSXLDTRK, + 0, + 0, + 0, + 0, + }, + + // Pos:2553 Instruction:"XTEST" Encoding:"NP 0x0F 0x01 /0xD6"/"" + { + ND_INS_XTEST, ND_CAT_LOGIC, ND_SET_TSX, 1560, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, + 0, + 0|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + +}; + +#endif diff --git a/bddisasm/include/mnemonics.h b/bddisasm/include/mnemonics.h new file mode 100644 index 0000000..b227082 --- /dev/null +++ b/bddisasm/include/mnemonics.h @@ -0,0 +1,282 @@ +#ifndef _MNEMONICS_H_ +#define _MNEMONICS_H_ + +const char *gMnemonics[1561] = +{ + "AAA", "AAD", "AAM", "AAS", "ADC", "ADCX", "ADD", "ADDPD", "ADDPS", + "ADDSD", "ADDSS", "ADDSUBPD", "ADDSUBPS", "ADOX", "AESDEC", "AESDECLAST", + "AESENC", "AESENCLAST", "AESIMC", "AESKEYGENASSIST", "ALTINST", + "AND", "ANDN", "ANDNPD", "ANDNPS", "ANDPD", "ANDPS", "ARPL", + "BEXTR", "BLCFILL", "BLCI", "BLCIC", "BLCMSK", "BLCS", "BLENDPD", + "BLENDPS", "BLENDVPD", "BLENDVPS", "BLSFILL", "BLSI", "BLSIC", + "BLSMSK", "BLSR", "BNDCL", "BNDCN", "BNDCU", "BNDLDX", "BNDMK", + "BNDMOV", "BNDSTX", "BOUND", "BSF", "BSR", "BSWAP", "BT", "BTC", + "BTR", "BTS", "BZHI", "CALL", "CALLF", "CBW", "CDQ", "CDQE", + "CL1INVMB", "CLAC", "CLC", "CLD", "CLDEMOTE", "CLEVICT0", "CLEVICT1", + "CLFLUSH", "CLFLUSHOPT", "CLGI", "CLI", "CLRSSBSY", "CLTS", "CLWB", + "CLZERO", "CMC", "CMOVBE", "CMOVC", "CMOVL", "CMOVLE", "CMOVNBE", + "CMOVNC", "CMOVNL", "CMOVNLE", "CMOVNO", "CMOVNP", "CMOVNS", + "CMOVNZ", "CMOVO", "CMOVP", "CMOVS", "CMOVZ", "CMP", "CMPPD", + "CMPPS", "CMPSB", "CMPSD", "CMPSQ", "CMPSS", "CMPSW", "CMPXCHG", + "CMPXCHG16B", "CMPXCHG8B", "COMISD", "COMISS", "CPUID", "CPU_READ", + "CPU_WRITE", "CQO", "CRC32", "CVTDQ2PD", "CVTDQ2PS", "CVTPD2DQ", + "CVTPD2PI", "CVTPD2PS", "CVTPI2PD", "CVTPI2PS", "CVTPS2DQ", "CVTPS2PD", + "CVTPS2PI", "CVTSD2SI", "CVTSD2SS", "CVTSI2SD", "CVTSI2SS", "CVTSS2SD", + "CVTSS2SI", "CVTTPD2DQ", "CVTTPD2PI", "CVTTPS2DQ", "CVTTPS2PI", + "CVTTSD2SI", "CVTTSS2SI", "CWD", "CWDE", "DAA", "DAS", "DEC", + "DELAY", "DIV", "DIVPD", "DIVPS", "DIVSD", "DIVSS", "DMINT", + "DPPD", "DPPS", "EMMS", "ENCLS", "ENCLU", "ENCLV", "ENDBR32", + "ENDBR64", "ENQCMD", "ENQCMDS", "ENTER", "EXTRACTPS", "EXTRQ", + "F2XM1", "FABS", "FADD", "FADDP", "FBLD", "FBSTP", "FCHS", "FCMOVB", + "FCMOVBE", "FCMOVE", "FCMOVNB", "FCMOVNBE", "FCMOVNE", "FCMOVNU", + "FCMOVU", "FCOM", "FCOMI", "FCOMIP", "FCOMP", "FCOMPP", "FCOS", + "FDECSTP", "FDIV", "FDIVP", "FDIVR", "FDIVRP", "FEMMS", "FFREE", + "FFREEP", "FIADD", "FICOM", "FICOMP", "FIDIV", "FIDIVR", "FILD", + "FIMUL", "FINCSTP", "FIST", "FISTP", "FISTTP", "FISUB", "FISUBR", + "FLD", "FLD1", "FLDCW", "FLDENV", "FLDL2E", "FLDL2T", "FLDLG2", + "FLDLN2", "FLDPI", "FLDZ", "FMUL", "FMULP", "FNCLEX", "FNDISI", + "FNINIT", "FNOP", "FNSAVE", "FNSTCW", "FNSTENV", "FNSTSW", "FPATAN", + "FPREM", "FPREM1", "FPTAN", "FRINEAR", "FRNDINT", "FRSTOR", "FSCALE", + "FSIN", "FSINCOS", "FSQRT", "FST", "FSTDW", "FSTP", "FSTPNCE", + "FSTSG", "FSUB", "FSUBP", "FSUBR", "FSUBRP", "FTST", "FUCOM", + "FUCOMI", "FUCOMIP", "FUCOMP", "FUCOMPP", "FXAM", "FXCH", "FXRSTOR", + "FXSAVE", "FXTRACT", "FYL2X", "FYL2XP1", "GETSEC", "GF2P8AFFINEINVQB", + "GF2P8AFFINEQB", "GF2P8MULB", "HADDPD", "HADDPS", "HLT", "HSUBPD", + "HSUBPS", "IDIV", "IMUL", "IN", "INC", "INCSSPD", "INCSSPQ", + "INSB", "INSD", "INSERTPS", "INSERTQ", "INSW", "INT", "INT1", + "INT3", "INTO", "INVD", "INVEPT", "INVLPG", "INVLPGA", "INVLPGB", + "INVPCID", "INVVPID", "IRETD", "IRETQ", "IRETW", "JBE", "JC", + "JCXZ", "JECXZ", "JL", "JLE", "JMP", "JMPE", "JMPF", "JNBE", + "JNC", "JNL", "JNLE", "JNO", "JNP", "JNS", "JNZ", "JO", "JP", + "JRCXZ", "JS", "JZ", "KADDB", "KADDD", "KADDQ", "KADDW", "KANDB", + "KANDD", "KANDNB", "KANDND", "KANDNQ", "KANDNW", "KANDQ", "KANDW", + "KMERGE2L1H", "KMERGE2L1L", "KMOVB", "KMOVD", "KMOVQ", "KMOVW", + "KNOTB", "KNOTD", "KNOTQ", "KNOTW", "KORB", "KORD", "KORQ", "KORTESTB", + "KORTESTD", "KORTESTQ", "KORTESTW", "KORW", "KSHIFTLB", "KSHIFTLD", + "KSHIFTLQ", "KSHIFTLW", "KSHIFTRB", "KSHIFTRD", "KSHIFTRQ", "KSHIFTRW", + "KTESTB", "KTESTD", "KTESTQ", "KTESTW", "KUNPCKBW", "KUNPCKDQ", + "KUNPCKWD", "KXNORB", "KXNORD", "KXNORQ", "KXNORW", "KXORB", + "KXORD", "KXORQ", "KXORW", "LAHF", "LAR", "LDDQU", "LDMXCSR", + "LDS", "LDTILECFG", "LEA", "LEAVE", "LES", "LFENCE", "LFS", "LGDT", + "LGS", "LIDT", "LLDT", "LLWPCB", "LMSW", "LOADALL", "LOADALLD", + "LODSB", "LODSD", "LODSQ", "LODSW", "LOOP", "LOOPNZ", "LOOPZ", + "LSL", "LSS", "LTR", "LWPINS", "LWPVAL", "LZCNT", "MASKMOVDQU", + "MASKMOVQ", "MAXPD", "MAXPS", "MAXSD", "MAXSS", "MCOMMIT", "MFENCE", + "MINPD", "MINPS", "MINSD", "MINSS", "MONITOR", "MONITORX", "MONTMUL", + "MOV", "MOVAPD", "MOVAPS", "MOVBE", "MOVD", "MOVDDUP", "MOVDIR64B", + "MOVDIRI", "MOVDQ2Q", "MOVDQA", "MOVDQU", "MOVHPD", "MOVHPS", + "MOVLHPS", "MOVLPD", "MOVLPS", "MOVMSKPD", "MOVMSKPS", "MOVNTDQ", + "MOVNTDQA", "MOVNTI", "MOVNTPD", "MOVNTPS", "MOVNTQ", "MOVNTSD", + "MOVNTSS", "MOVQ", "MOVQ2DQ", "MOVSB", "MOVSD", "MOVSHDUP", "MOVSLDUP", + "MOVSQ", "MOVSS", "MOVSW", "MOVSX", "MOVSXD", "MOVUPD", "MOVUPS", + "MOVZX", "MPSADBW", "MUL", "MULPD", "MULPS", "MULSD", "MULSS", + "MULX", "MWAIT", "MWAITX", "NEG", "NOP", "NOT", "OR", "ORPD", + "ORPS", "OUT", "OUTSB", "OUTSD", "OUTSW", "PABSB", "PABSD", "PABSW", + "PACKSSDW", "PACKSSWB", "PACKUSDW", "PACKUSWB", "PADDB", "PADDD", + "PADDQ", "PADDSB", "PADDSW", "PADDUSB", "PADDUSW", "PADDW", "PALIGNR", + "PAND", "PANDN", "PAUSE", "PAVGB", "PAVGUSB", "PAVGW", "PBLENDVB", + "PBLENDW", "PCLMULQDQ", "PCMPEQB", "PCMPEQD", "PCMPEQQ", "PCMPEQW", + "PCMPESTRI", "PCMPESTRM", "PCMPGTB", "PCMPGTD", "PCMPGTQ", "PCMPGTW", + "PCMPISTRI", "PCMPISTRM", "PCOMMIT", "PCONFIG", "PDEP", "PEXT", + "PEXTRB", "PEXTRD", "PEXTRQ", "PEXTRW", "PF2ID", "PF2IW", "PFACC", + "PFADD", "PFCMPEQ", "PFCMPGE", "PFCMPGT", "PFMAX", "PFMIN", "PFMUL", + "PFNACC", "PFPNACC", "PFRCPIT1", "PFRCPIT2", "PFRCPV", "PFRSQIT1", + "PFRSQRT", "PFRSQRTV", "PFSUB", "PFSUBR", "PHADDD", "PHADDSW", + "PHADDW", "PHMINPOSUW", "PHSUBD", "PHSUBSW", "PHSUBW", "PI2FD", + "PI2FW", "PINSRB", "PINSRD", "PINSRQ", "PINSRW", "PMADDUBSW", + "PMADDWD", "PMAXSB", "PMAXSD", "PMAXSW", "PMAXUB", "PMAXUD", + "PMAXUW", "PMINSB", "PMINSD", "PMINSW", "PMINUB", "PMINUD", "PMINUW", + "PMOVMSKB", "PMOVSXBD", "PMOVSXBQ", "PMOVSXBW", "PMOVSXDQ", "PMOVSXWD", + "PMOVSXWQ", "PMOVZXBD", "PMOVZXBQ", "PMOVZXBW", "PMOVZXDQ", "PMOVZXWD", + "PMOVZXWQ", "PMULDQ", "PMULHRSW", "PMULHRW", "PMULHUW", "PMULHW", + "PMULLD", "PMULLW", "PMULUDQ", "POP", "POPA", "POPCNT", "POPFD", + "POPFQ", "POPFW", "POR", "PREFETCH", "PREFETCHE", "PREFETCHM", + "PREFETCHNTA", "PREFETCHT0", "PREFETCHT1", "PREFETCHT2", "PREFETCHW", + "PREFETCHWT1", "PSADBW", "PSHUFB", "PSHUFD", "PSHUFHW", "PSHUFLW", + "PSHUFW", "PSIGNB", "PSIGND", "PSIGNW", "PSLLD", "PSLLDQ", "PSLLQ", + "PSLLW", "PSMASH", "PSRAD", "PSRAW", "PSRLD", "PSRLDQ", "PSRLQ", + "PSRLW", "PSUBB", "PSUBD", "PSUBQ", "PSUBSB", "PSUBSW", "PSUBUSB", + "PSUBUSW", "PSUBW", "PSWAPD", "PTEST", "PTWRITE", "PUNPCKHBW", + "PUNPCKHDQ", "PUNPCKHQDQ", "PUNPCKHWD", "PUNPCKLBW", "PUNPCKLDQ", + "PUNPCKLQDQ", "PUNPCKLWD", "PUSH", "PUSHA", "PUSHFD", "PUSHFQ", + "PUSHFW", "PVALIDATE", "PXOR", "RCL", "RCPPS", "RCPSS", "RCR", + "RDFSBASE", "RDGSBASE", "RDMSR", "RDPID", "RDPKRU", "RDPMC", + "RDPRU", "RDRAND", "RDSEED", "RDSHR", "RDSSPD", "RDSSPQ", "RDTSC", + "RDTSCP", "RETF", "RETN", "RMPADJUST", "RMPUPDATE", "ROL", "ROR", + "RORX", "ROUNDPD", "ROUNDPS", "ROUNDSD", "ROUNDSS", "RSDC", "RSLDT", + "RSM", "RSQRTPS", "RSQRTSS", "RSTORSSP", "RSTS", "SAHF", "SAL", + "SALC", "SAR", "SARX", "SAVEPREVSSP", "SBB", "SCASB", "SCASD", + "SCASQ", "SCASW", "SERIALIZE", "SETBE", "SETC", "SETL", "SETLE", + "SETNB", "SETNC", "SETNL", "SETNLE", "SETNO", "SETNP", "SETNS", + "SETNZ", "SETO", "SETP", "SETS", "SETSSBSY", "SETZ", "SFENCE", + "SGDT", "SHA1MSG1", "SHA1MSG2", "SHA1NEXTE", "SHA1RNDS4", "SHA256MSG1", + "SHA256MSG2", "SHA256RNDS2", "SHL", "SHLD", "SHLX", "SHR", "SHRD", + "SHRX", "SHUFPD", "SHUFPS", "SIDT", "SKINIT", "SLDT", "SLWPCB", + "SMINT", "SMSW", "SPFLT", "SQRTPD", "SQRTPS", "SQRTSD", "SQRTSS", + "STAC", "STC", "STD", "STGI", "STI", "STMXCSR", "STOSB", "STOSD", + "STOSQ", "STOSW", "STR", "STTILECFG", "SUB", "SUBPD", "SUBPS", + "SUBSD", "SUBSS", "SVDC", "SVLDT", "SVTS", "SWAPGS", "SYSCALL", + "SYSENTER", "SYSEXIT", "SYSRET", "T1MSKC", "TDPBF16PS", "TDPBSSD", + "TDPBSUD", "TDPBUSD", "TDPBUUD", "TEST", "TILELOADD", "TILELOADDT1", + "TILERELEASE", "TILESTORED", "TILEZERO", "TLBSYNC", "TPAUSE", + "TZCNT", "TZMSK", "UCOMISD", "UCOMISS", "UD0", "UD1", "UD2", + "UMONITOR", "UMWAIT", "UNPCKHPD", "UNPCKHPS", "UNPCKLPD", "UNPCKLPS", + "V4FMADDPS", "V4FMADDSS", "V4FNMADDPS", "V4FNMADDSS", "VADDPD", + "VADDPS", "VADDSD", "VADDSS", "VADDSUBPD", "VADDSUBPS", "VAESDEC", + "VAESDECLAST", "VAESENC", "VAESENCLAST", "VAESIMC", "VAESKEYGENASSIST", + "VALIGND", "VALIGNQ", "VANDNPD", "VANDNPS", "VANDPD", "VANDPS", + "VBLENDMPD", "VBLENDMPS", "VBLENDPD", "VBLENDPS", "VBLENDVPD", + "VBLENDVPS", "VBROADCASTF128", "VBROADCASTF32X2", "VBROADCASTF32X4", + "VBROADCASTF32X8", "VBROADCASTF64X2", "VBROADCASTF64X4", "VBROADCASTI128", + "VBROADCASTI32X2", "VBROADCASTI32X4", "VBROADCASTI32X8", "VBROADCASTI64X2", + "VBROADCASTI64X4", "VBROADCASTSD", "VBROADCASTSS", "VCMPPD", + "VCMPPS", "VCMPSD", "VCMPSS", "VCOMISD", "VCOMISS", "VCOMPRESSPD", + "VCOMPRESSPS", "VCVTDQ2PD", "VCVTDQ2PS", "VCVTNE2PS2BF16", "VCVTNEPS2BF16", + "VCVTPD2DQ", "VCVTPD2PS", "VCVTPD2QQ", "VCVTPD2UDQ", "VCVTPD2UQQ", + "VCVTPH2PS", "VCVTPS2DQ", "VCVTPS2PD", "VCVTPS2PH", "VCVTPS2QQ", + "VCVTPS2UDQ", "VCVTPS2UQQ", "VCVTQQ2PD", "VCVTQQ2PS", "VCVTSD2SI", + "VCVTSD2SS", "VCVTSD2USI", "VCVTSI2SD", "VCVTSI2SS", "VCVTSS2SD", + "VCVTSS2SI", "VCVTSS2USI", "VCVTTPD2DQ", "VCVTTPD2QQ", "VCVTTPD2UDQ", + "VCVTTPD2UQQ", "VCVTTPS2DQ", "VCVTTPS2QQ", "VCVTTPS2UDQ", "VCVTTPS2UQQ", + "VCVTTSD2SI", "VCVTTSD2USI", "VCVTTSS2SI", "VCVTTSS2USI", "VCVTUDQ2PD", + "VCVTUDQ2PS", "VCVTUQQ2PD", "VCVTUQQ2PS", "VCVTUSI2SD", "VCVTUSI2SS", + "VDBPSADBW", "VDIVPD", "VDIVPS", "VDIVSD", "VDIVSS", "VDPBF16PS", + "VDPPD", "VDPPS", "VERR", "VERW", "VEXP2PD", "VEXP2PS", "VEXPANDPD", + "VEXPANDPS", "VEXTRACTF128", "VEXTRACTF32X4", "VEXTRACTF32X8", + "VEXTRACTF64X2", "VEXTRACTF64X4", "VEXTRACTI128", "VEXTRACTI32X4", + "VEXTRACTI32X8", "VEXTRACTI64X2", "VEXTRACTI64X4", "VEXTRACTPS", + "VFIXUPIMMPD", "VFIXUPIMMPS", "VFIXUPIMMSD", "VFIXUPIMMSS", "VFMADD132PD", + "VFMADD132PS", "VFMADD132SD", "VFMADD132SS", "VFMADD213PD", "VFMADD213PS", + "VFMADD213SD", "VFMADD213SS", "VFMADD231PD", "VFMADD231PS", "VFMADD231SD", + "VFMADD231SS", "VFMADDPD", "VFMADDPS", "VFMADDSD", "VFMADDSS", + "VFMADDSUB132PD", "VFMADDSUB132PS", "VFMADDSUB213PD", "VFMADDSUB213PS", + "VFMADDSUB231PD", "VFMADDSUB231PS", "VFMADDSUBPD", "VFMADDSUBPS", + "VFMSUB132PD", "VFMSUB132PS", "VFMSUB132SD", "VFMSUB132SS", "VFMSUB213PD", + "VFMSUB213PS", "VFMSUB213SD", "VFMSUB213SS", "VFMSUB231PD", "VFMSUB231PS", + "VFMSUB231SD", "VFMSUB231SS", "VFMSUBADD132PD", "VFMSUBADD132PS", + "VFMSUBADD213PD", "VFMSUBADD213PS", "VFMSUBADD231PD", "VFMSUBADD231PS", + "VFMSUBADDPD", "VFMSUBADDPS", "VFMSUBPD", "VFMSUBPS", "VFMSUBSD", + "VFMSUBSS", "VFNMADD132PD", "VFNMADD132PS", "VFNMADD132SD", "VFNMADD132SS", + "VFNMADD213PD", "VFNMADD213PS", "VFNMADD213SD", "VFNMADD213SS", + "VFNMADD231PD", "VFNMADD231PS", "VFNMADD231SD", "VFNMADD231SS", + "VFNMADDPD", "VFNMADDPS", "VFNMADDSD", "VFNMADDSS", "VFNMSUB132PD", + "VFNMSUB132PS", "VFNMSUB132SD", "VFNMSUB132SS", "VFNMSUB213PD", + "VFNMSUB213PS", "VFNMSUB213SD", "VFNMSUB213SS", "VFNMSUB231PD", + "VFNMSUB231PS", "VFNMSUB231SD", "VFNMSUB231SS", "VFNMSUBPD", + "VFNMSUBPS", "VFNMSUBSD", "VFNMSUBSS", "VFPCLASSPD", "VFPCLASSPS", + "VFPCLASSSD", "VFPCLASSSS", "VFRCZPD", "VFRCZPS", "VFRCZSD", + "VFRCZSS", "VGATHERDPD", "VGATHERDPS", "VGATHERPF0DPD", "VGATHERPF0DPS", + "VGATHERPF0QPD", "VGATHERPF0QPS", "VGATHERPF1DPD", "VGATHERPF1DPS", + "VGATHERPF1QPD", "VGATHERPF1QPS", "VGATHERQPD", "VGATHERQPS", + "VGETEXPPD", "VGETEXPPS", "VGETEXPSD", "VGETEXPSS", "VGETMANTPD", + "VGETMANTPS", "VGETMANTSD", "VGETMANTSS", "VGF2P8AFFINEINVQB", + "VGF2P8AFFINEQB", "VGF2P8MULB", "VHADDPD", "VHADDPS", "VHSUBPD", + "VHSUBPS", "VINSERTF128", "VINSERTF32X4", "VINSERTF32X8", "VINSERTF64X2", + "VINSERTF64X4", "VINSERTI128", "VINSERTI32X4", "VINSERTI32X8", + "VINSERTI64X2", "VINSERTI64X4", "VINSERTPS", "VLDDQU", "VLDMXCSR", + "VMASKMOVDQU", "VMASKMOVPD", "VMASKMOVPS", "VMAXPD", "VMAXPS", + "VMAXSD", "VMAXSS", "VMCALL", "VMCLEAR", "VMFUNC", "VMGEXIT", + "VMINPD", "VMINPS", "VMINSD", "VMINSS", "VMLAUNCH", "VMLOAD", + "VMMCALL", "VMOVAPD", "VMOVAPS", "VMOVD", "VMOVDDUP", "VMOVDQA", + "VMOVDQA32", "VMOVDQA64", "VMOVDQU", "VMOVDQU16", "VMOVDQU32", + "VMOVDQU64", "VMOVDQU8", "VMOVHLPS", "VMOVHPD", "VMOVHPS", "VMOVLHPS", + "VMOVLPD", "VMOVLPS", "VMOVMSKPD", "VMOVMSKPS", "VMOVNTDQ", "VMOVNTDQA", + "VMOVNTPD", "VMOVNTPS", "VMOVQ", "VMOVSD", "VMOVSHDUP", "VMOVSLDUP", + "VMOVSS", "VMOVUPD", "VMOVUPS", "VMPSADBW", "VMPTRLD", "VMPTRST", + "VMREAD", "VMRESUME", "VMRUN", "VMSAVE", "VMULPD", "VMULPS", + "VMULSD", "VMULSS", "VMWRITE", "VMXOFF", "VMXON", "VORPD", "VORPS", + "VP2INTERSECTD", "VP2INTERSECTQ", "VP4DPWSSD", "VP4DPWSSDS", + "VPABSB", "VPABSD", "VPABSQ", "VPABSW", "VPACKSSDW", "VPACKSSWB", + "VPACKUSDW", "VPACKUSWB", "VPADDB", "VPADDD", "VPADDQ", "VPADDSB", + "VPADDSW", "VPADDUSB", "VPADDUSW", "VPADDW", "VPALIGNR", "VPAND", + "VPANDD", "VPANDN", "VPANDND", "VPANDNQ", "VPANDQ", "VPAVGB", + "VPAVGW", "VPBLENDD", "VPBLENDMB", "VPBLENDMD", "VPBLENDMQ", + "VPBLENDMW", "VPBLENDVB", "VPBLENDW", "VPBROADCASTB", "VPBROADCASTD", + "VPBROADCASTMB2Q", "VPBROADCASTMW2D", "VPBROADCASTQ", "VPBROADCASTW", + "VPCLMULQDQ", "VPCMOV", "VPCMPB", "VPCMPD", "VPCMPEQB", "VPCMPEQD", + "VPCMPEQQ", "VPCMPEQW", "VPCMPESTRI", "VPCMPESTRM", "VPCMPGTB", + "VPCMPGTD", "VPCMPGTQ", "VPCMPGTW", "VPCMPISTRI", "VPCMPISTRM", + "VPCMPQ", "VPCMPUB", "VPCMPUD", "VPCMPUQ", "VPCMPUW", "VPCMPW", + "VPCOMB", "VPCOMD", "VPCOMPRESSB", "VPCOMPRESSD", "VPCOMPRESSQ", + "VPCOMPRESSW", "VPCOMQ", "VPCOMUB", "VPCOMUD", "VPCOMUQ", "VPCOMUW", + "VPCOMW", "VPCONFLICTD", "VPCONFLICTQ", "VPDPBUSD", "VPDPBUSDS", + "VPDPWSSD", "VPDPWSSDS", "VPERM2F128", "VPERM2I128", "VPERMB", + "VPERMD", "VPERMI2B", "VPERMI2D", "VPERMI2PD", "VPERMI2PS", "VPERMI2Q", + "VPERMI2W", "VPERMILPD", "VPERMILPS", "VPERMILzz2PD", "VPERMILzz2PS", + "VPERMPD", "VPERMPS", "VPERMQ", "VPERMT2B", "VPERMT2D", "VPERMT2PD", + "VPERMT2PS", "VPERMT2Q", "VPERMT2W", "VPERMW", "VPEXPANDB", "VPEXPANDD", + "VPEXPANDQ", "VPEXPANDW", "VPEXTRB", "VPEXTRD", "VPEXTRQ", "VPEXTRW", + "VPGATHERDD", "VPGATHERDQ", "VPGATHERQD", "VPGATHERQQ", "VPHADDBD", + "VPHADDBQ", "VPHADDBW", "VPHADDD", "VPHADDDQ", "VPHADDSW", "VPHADDUBD", + "VPHADDUBQ", "VPHADDUBW", "VPHADDUDQ", "VPHADDUWD", "VPHADDUWQ", + "VPHADDW", "VPHADDWD", "VPHADDWQ", "VPHMINPOSUW", "VPHSUBBW", + "VPHSUBD", "VPHSUBDQ", "VPHSUBSW", "VPHSUBW", "VPHSUBWD", "VPINSRB", + "VPINSRD", "VPINSRQ", "VPINSRW", "VPLZCNTD", "VPLZCNTQ", "VPMACSDD", + "VPMACSDQH", "VPMACSDQL", "VPMACSSDD", "VPMACSSDQH", "VPMACSSDQL", + "VPMACSSWD", "VPMACSSWW", "VPMACSWD", "VPMACSWW", "VPMADCSSWD", + "VPMADCSWD", "VPMADD52HUQ", "VPMADD52LUQ", "VPMADDUBSW", "VPMADDWD", + "VPMASKMOVD", "VPMASKMOVQ", "VPMAXSB", "VPMAXSD", "VPMAXSQ", + "VPMAXSW", "VPMAXUB", "VPMAXUD", "VPMAXUQ", "VPMAXUW", "VPMINSB", + "VPMINSD", "VPMINSQ", "VPMINSW", "VPMINUB", "VPMINUD", "VPMINUQ", + "VPMINUW", "VPMOVB2M", "VPMOVD2M", "VPMOVDB", "VPMOVDW", "VPMOVM2B", + "VPMOVM2D", "VPMOVM2Q", "VPMOVM2W", "VPMOVMSKB", "VPMOVQ2M", + "VPMOVQB", "VPMOVQD", "VPMOVQW", "VPMOVSDB", "VPMOVSDW", "VPMOVSQB", + "VPMOVSQD", "VPMOVSQW", "VPMOVSWB", "VPMOVSXBD", "VPMOVSXBQ", + "VPMOVSXBW", "VPMOVSXDQ", "VPMOVSXWD", "VPMOVSXWQ", "VPMOVUSDB", + "VPMOVUSDW", "VPMOVUSQB", "VPMOVUSQD", "VPMOVUSQW", "VPMOVUSWB", + "VPMOVW2M", "VPMOVWB", "VPMOVZXBD", "VPMOVZXBQ", "VPMOVZXBW", + "VPMOVZXDQ", "VPMOVZXWD", "VPMOVZXWQ", "VPMULDQ", "VPMULHRSW", + "VPMULHUW", "VPMULHW", "VPMULLD", "VPMULLQ", "VPMULLW", "VPMULTISHIFTQB", + "VPMULUDQ", "VPOPCNTB", "VPOPCNTD", "VPOPCNTQ", "VPOPCNTW", "VPOR", + "VPORD", "VPORQ", "VPPERM", "VPROLD", "VPROLQ", "VPROLVD", "VPROLVQ", + "VPRORD", "VPRORQ", "VPRORVD", "VPRORVQ", "VPROTB", "VPROTD", + "VPROTQ", "VPROTW", "VPSADBW", "VPSCATTERDD", "VPSCATTERDQ", + "VPSCATTERQD", "VPSCATTERQQ", "VPSHAB", "VPSHAD", "VPSHAQ", "VPSHAW", + "VPSHLB", "VPSHLDD", "VPSHLDQ", "VPSHLDVD", "VPSHLDVQ", "VPSHLDVW", + "VPSHLDW", "VPSHLQ", "VPSHRDD", "VPSHRDQ", "VPSHRDVD", "VPSHRDVQ", + "VPSHRDVW", "VPSHRDW", "VPSHUFB", "VPSHUFBITQMB", "VPSHUFD", + "VPSHUFHW", "VPSHUFLW", "VPSIGNB", "VPSIGND", "VPSIGNW", "VPSLLD", + "VPSLLDQ", "VPSLLQ", "VPSLLVD", "VPSLLVQ", "VPSLLVW", "VPSLLW", + "VPSRAD", "VPSRAQ", "VPSRAVD", "VPSRAVQ", "VPSRAVW", "VPSRAW", + "VPSRLD", "VPSRLDQ", "VPSRLQ", "VPSRLVD", "VPSRLVQ", "VPSRLVW", + "VPSRLW", "VPSUBB", "VPSUBD", "VPSUBQ", "VPSUBSB", "VPSUBSW", + "VPSUBUSB", "VPSUBUSW", "VPSUBW", "VPTERNLOGD", "VPTERNLOGQ", + "VPTEST", "VPTESTMB", "VPTESTMD", "VPTESTMQ", "VPTESTMW", "VPTESTNMB", + "VPTESTNMD", "VPTESTNMQ", "VPTESTNMW", "VPUNPCKHBW", "VPUNPCKHDQ", + "VPUNPCKHQDQ", "VPUNPCKHWD", "VPUNPCKLBW", "VPUNPCKLDQ", "VPUNPCKLQDQ", + "VPUNPCKLWD", "VPXOR", "VPXORD", "VPXORQ", "VRANGEPD", "VRANGEPS", + "VRANGESD", "VRANGESS", "VRCP14PD", "VRCP14PS", "VRCP14SD", "VRCP14SS", + "VRCP28PD", "VRCP28PS", "VRCP28SD", "VRCP28SS", "VRCPPS", "VRCPSS", + "VREDUCEPD", "VREDUCEPS", "VREDUCESD", "VREDUCESS", "VRNDSCALEPD", + "VRNDSCALEPS", "VRNDSCALESD", "VRNDSCALESS", "VROUNDPD", "VROUNDPS", + "VROUNDSD", "VROUNDSS", "VRSQRT14PD", "VRSQRT14PS", "VRSQRT14SD", + "VRSQRT14SS", "VRSQRT28PD", "VRSQRT28PS", "VRSQRT28SD", "VRSQRT28SS", + "VRSQRTPS", "VRSQRTSS", "VSCALEFPD", "VSCALEFPS", "VSCALEFSD", + "VSCALEFSS", "VSCATTERDPD", "VSCATTERDPS", "VSCATTERPF0DPD", + "VSCATTERPF0DPS", "VSCATTERPF0QPD", "VSCATTERPF0QPS", "VSCATTERPF1DPD", + "VSCATTERPF1DPS", "VSCATTERPF1QPD", "VSCATTERPF1QPS", "VSCATTERQPD", + "VSCATTERQPS", "VSHUFF32X4", "VSHUFF64X2", "VSHUFI32X4", "VSHUFI64X2", + "VSHUFPD", "VSHUFPS", "VSQRTPD", "VSQRTPS", "VSQRTSD", "VSQRTSS", + "VSTMXCSR", "VSUBPD", "VSUBPS", "VSUBSD", "VSUBSS", "VTESTPD", + "VTESTPS", "VUCOMISD", "VUCOMISS", "VUNPCKHPD", "VUNPCKHPS", + "VUNPCKLPD", "VUNPCKLPS", "VXORPD", "VXORPS", "VZEROALL", "VZEROUPPER", + "WAIT", "WBINVD", "WBNOINVD", "WRFSBASE", "WRGSBASE", "WRMSR", + "WRPKRU", "WRSHR", "WRSSD", "WRSSQ", "WRUSSD", "WRUSSQ", "XABORT", + "XADD", "XBEGIN", "XCHG", "XCRYPTCBC", "XCRYPTCFB", "XCRYPTCTR", + "XCRYPTECB", "XCRYPTOFB", "XEND", "XGETBV", "XLATB", "XOR", "XORPD", + "XORPS", "XRESLDTRK", "XRSTOR", "XRSTOR64", "XRSTORS", "XRSTORS64", + "XSAVE", "XSAVE64", "XSAVEC", "XSAVEC64", "XSAVEOPT", "XSAVEOPT64", + "XSAVES", "XSAVES64", "XSETBV", "XSHA1", "XSHA256", "XSTORE", + "XSUSLDTRK", "XTEST", +}; + + +const char *gPrefixes[18] = +{ + "BHALT", "BHNT", "BHT", "BND", "DNT", "LOCK", "REPNZ", "REPZ", + "XACQUIRE", "XRELEASE", "addr", "cs", "ds", "es", "fs", "gs", + "size", "ss", +}; + +#endif + diff --git a/bddisasm/include/nd_crt.h b/bddisasm/include/nd_crt.h new file mode 100644 index 0000000..a0e1c1b --- /dev/null +++ b/bddisasm/include/nd_crt.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2020 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _ND_CRT_H_ +#define _ND_CRT_H_ + +#include "../../inc/disasmtypes.h" + +#ifndef UNREFERENCED_PARAMETER +#define UNREFERENCED_PARAMETER(P) ((void)(P)) +#endif + +#if defined(_MSC_VER) + +typedef char * va_list; + +# ifndef _ADDRESSOF +# ifdef __cplusplus +# define _ADDRESSOF(v) ( &reinterpret_cast(v) ) +# else +# define _ADDRESSOF(v) ( &(v) ) +# endif // __cplusplus +# endif // !_ADDRESSOF + +# ifndef KERNEL_MODE + +# if defined(AMD64) || defined(WIN64) + +extern void __cdecl __va_start(__out va_list *, ...); // is this exported by VC compiler? + +# define _crt_va_start(ap, x) ( __va_start(&ap, x) ) +# define _crt_va_arg(ap, t) ( ( sizeof(t) > sizeof(QWORD) || ( sizeof(t) & (sizeof(t) - 1) ) != 0 ) \ + ? **(t **)( ( ap += sizeof(QWORD) ) - sizeof(QWORD) ) \ + : *(t *)( ( ap += sizeof(QWORD) ) - sizeof(QWORD) ) ) +# define _crt_va_end(ap) ( ap = (va_list)0 ) + +# else + +// a guess at the proper definitions for other platforms + +# ifndef _INTSIZEOF +# define _INTSIZEOF(n) ( (sizeof(n) + sizeof(int) - 1) & ~(sizeof(int) - 1) ) +# endif // !_INTSIZEOF + + +# define _crt_va_start(ap,v) ( ap = (va_list)_ADDRESSOF(v) + _INTSIZEOF(v) ) +# define _crt_va_arg(ap,t) ( *(t *)((ap += _INTSIZEOF(t)) - _INTSIZEOF(t)) ) +# define _crt_va_end(ap) ( ap = (va_list)0 ) + +# endif // AMD64 || WIN64 + +# define va_start _crt_va_start +# define va_arg _crt_va_arg +# define va_end _crt_va_end + +#endif // KERNEL_MODE + +#else + +# include + +# define __forceinline inline __attribute__((always_inline)) + +#endif // _MSC_VER + +#ifndef KERNEL_MODE +// Declared here only. Expecting it to be defined in the integrator. +extern int nd_vsnprintf_s( + char *buffer, + size_t sizeOfBuffer, + size_t count, + const char *format, + va_list argptr + ); +#endif // KERNEL_MODE + +// Declared here only. Expecting it to be defined in the integrator. +extern void *nd_memset(void *s, int c, size_t n); + +#define nd_memzero(Dest, Size) nd_memset((Dest), 0, (Size)) + +char * +nd_strcat_s( + char *dst, + size_t dst_size, + const char *src + ); + +#endif // _ND_CRT_H_ diff --git a/bddisasm/include/prefixes.h b/bddisasm/include/prefixes.h new file mode 100644 index 0000000..240366b --- /dev/null +++ b/bddisasm/include/prefixes.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2020 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _PREFIXES_H_ +#define _PREFIXES_H_ + +#define ND_PREF_CODE_NONE 0 +#define ND_PREF_CODE_STANDARD 1 +#define ND_PREF_CODE_EX 2 +#define ND_PREF_CODE_REX 3 + +static const uint8_t gPrefixesMap[256] = +{ +// 0 1 2 3 4 5 6 7 8 9 A B C D E F + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 0 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 1 + 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, // 2 + 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, // 3 + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, // 4 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 5 + 0, 0, 2, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, // 6 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 7 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, // 8 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 9 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // A + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // B + 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // C + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // E + 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // F +}; + +#endif // _PREFIXES_H_ diff --git a/bddisasm/include/table_evex.h b/bddisasm/include/table_evex.h new file mode 100644 index 0000000..4f81d61 --- /dev/null +++ b/bddisasm/include/table_evex.h @@ -0,0 +1,12254 @@ +#ifndef _TABLE_EVEX_H_ +#define _TABLE_EVEX_H_ + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_9a_03_mem_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1327] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_9a_03_mem_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_9a_03_mem_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_02_9a_03_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gEvexTable_root_02_9a_03_mem_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_9a_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_02_9a_03_mem_l, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_9a_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1550] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_9a_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1552] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_9a_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_9a_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_9a_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_9a_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_9a_01_w, + /* 02 */ NULL, + /* 03 */ (const void *)&gEvexTable_root_02_9a_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_9b_03_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1328] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_9b_03_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_9b_03_mem_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_9b_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_02_9b_03_mem_w, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_9b_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1554] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_9b_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1556] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_9b_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_9b_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_9b_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_9b_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_9b_01_w, + /* 02 */ NULL, + /* 03 */ (const void *)&gEvexTable_root_02_9b_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_aa_03_mem_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1329] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_aa_03_mem_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_aa_03_mem_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_02_aa_03_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gEvexTable_root_02_aa_03_mem_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_aa_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_02_aa_03_mem_l, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_aa_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1558] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_aa_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1560] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_aa_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_aa_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_aa_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_aa_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_aa_01_w, + /* 02 */ NULL, + /* 03 */ (const void *)&gEvexTable_root_02_aa_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_ab_03_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1330] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_ab_03_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_ab_03_mem_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_ab_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_02_ab_03_mem_w, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_ab_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1562] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_ab_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1564] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_ab_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_ab_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_ab_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_ab_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_ab_01_w, + /* 02 */ NULL, + /* 03 */ (const void *)&gEvexTable_root_02_ab_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_de_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1341] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_de_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_de_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_df_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1343] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_df_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_df_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_dc_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1345] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_dc_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_dc_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_dd_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1347] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_dd_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_dd_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_65_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1361] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_65_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1362] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_65_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_65_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_65_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_65_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_65_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_19_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1368] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_19_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1379] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_19_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_19_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_19_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_19_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_19_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_1a_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1369] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_1a_01_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1371] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_1a_01_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_1a_01_mem_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_1a_01_mem_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_1a_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_02_1a_01_mem_w, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_1a_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_1a_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_1b_01_mem_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1370] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_1b_01_mem_02_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1372] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_1b_01_mem_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_1b_01_mem_02_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_1b_01_mem_02_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_02_1b_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gEvexTable_root_02_1b_01_mem_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_1b_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_02_1b_01_mem_l, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_1b_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_1b_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_59_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1374] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_59_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1932] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_59_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_59_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_59_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_59_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_59_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_5a_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1375] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_5a_01_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1377] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_5a_01_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_5a_01_mem_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_5a_01_mem_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_5a_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_02_5a_01_mem_w, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_5a_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_5a_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_5b_01_mem_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1376] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_5b_01_mem_02_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1378] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_5b_01_mem_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_5b_01_mem_02_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_5b_01_mem_02_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_02_5b_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gEvexTable_root_02_5b_01_mem_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_5b_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_02_5b_01_mem_l, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_5b_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_5b_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_18_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1381] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_18_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_18_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_18_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_18_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_8a_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1395] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_8a_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1396] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_8a_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_8a_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_8a_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_8a_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_8a_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_72_03_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1402] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_72_03_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_72_03_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_72_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1403] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_72_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_72_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_72_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2280] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_72_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_72_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_72_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_72_01_w, + /* 02 */ (const void *)&gEvexTable_root_02_72_02_w, + /* 03 */ (const void *)&gEvexTable_root_02_72_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_13_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1412] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_13_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_13_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_13_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2178] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_13_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_13_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_13_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_13_01_w, + /* 02 */ (const void *)&gEvexTable_root_02_13_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_52_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1475] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_52_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_52_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_52_03_mem_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1872] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_52_03_mem_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_52_03_mem_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_02_52_03_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gEvexTable_root_02_52_03_mem_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_52_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_02_52_03_mem_l, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_52_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1986] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_52_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_52_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_52_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_52_01_w, + /* 02 */ (const void *)&gEvexTable_root_02_52_02_w, + /* 03 */ (const void *)&gEvexTable_root_02_52_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_c8_01_02_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1480] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_c8_01_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1481] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_c8_01_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_c8_01_02_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_c8_01_02_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_02_c8_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gEvexTable_root_02_c8_01_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_c8_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_c8_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_88_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1482] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_88_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1483] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_88_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_88_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_88_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_88_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_88_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_98_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1502] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_98_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1504] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_98_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_98_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_98_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_98_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_98_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_99_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1506] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_99_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1508] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_99_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_99_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_99_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_99_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_99_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_a8_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1510] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_a8_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1512] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_a8_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_a8_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_a8_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_a8_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_a8_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_a9_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1514] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_a9_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1516] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_a9_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_a9_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_a9_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_a9_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_a9_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_b8_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1518] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_b8_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1520] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_b8_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_b8_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_b8_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_b8_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_b8_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_b9_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1522] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_b9_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1524] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_b9_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_b9_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_b9_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_b9_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_b9_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_96_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1534] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_96_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1536] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_96_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_96_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_96_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_96_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_96_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_a6_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1538] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_a6_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1540] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_a6_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_a6_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_a6_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_a6_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_a6_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_b6_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1542] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_b6_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1544] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_b6_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_b6_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_b6_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_b6_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_b6_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_ba_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1566] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_ba_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1568] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_ba_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_ba_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_ba_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_ba_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_ba_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_bb_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1570] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_bb_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1572] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_bb_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_bb_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_bb_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_bb_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_bb_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_97_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1574] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_97_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1576] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_97_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_97_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_97_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_97_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_97_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_a7_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1578] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_a7_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1580] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_a7_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_a7_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_a7_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_a7_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_a7_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_b7_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1582] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_b7_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1584] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_b7_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_b7_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_b7_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_b7_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_b7_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_9c_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1598] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_9c_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1600] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_9c_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_9c_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_9c_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_9c_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_9c_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_9d_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1602] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_9d_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1604] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_9d_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_9d_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_9d_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_9d_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_9d_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_ac_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1606] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_ac_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1608] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_ac_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_ac_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_ac_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_ac_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_ac_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_ad_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1610] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_ad_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1612] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_ad_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_ad_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_ad_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_ad_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_ad_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_bc_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1614] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_bc_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1616] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_bc_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_bc_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_bc_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_bc_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_bc_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_bd_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1618] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_bd_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1620] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_bd_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_bd_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_bd_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_bd_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_bd_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_9e_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1630] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_9e_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1632] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_9e_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_9e_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_9e_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_9e_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_9e_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_9f_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1634] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_9f_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1636] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_9f_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_9f_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_9f_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_9f_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_9f_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_ae_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1638] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_ae_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1640] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_ae_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_ae_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_ae_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_ae_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_ae_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_af_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1642] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_af_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1644] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_af_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_af_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_af_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_af_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_af_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_be_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1646] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_be_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1648] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_be_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_be_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_be_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_be_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_be_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_bf_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1650] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_bf_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1652] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_bf_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_bf_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_bf_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_bf_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_bf_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_92_01_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1670] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_92_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1672] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_92_01_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_92_01_mem_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_92_01_mem_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_92_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_02_92_01_mem_w, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_92_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_92_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_01_02_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1674] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_01_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1675] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_01_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_c6_01_mem_01_02_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_c6_01_mem_01_02_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gEvexTable_root_02_c6_01_mem_01_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_02_02_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1678] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_02_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1679] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_02_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_c6_01_mem_02_02_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_c6_01_mem_02_02_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_02_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gEvexTable_root_02_c6_01_mem_02_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_05_02_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2434] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_05_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2435] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_05_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_c6_01_mem_05_02_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_c6_01_mem_05_02_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_05_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gEvexTable_root_02_c6_01_mem_05_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_06_02_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2438] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_06_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2439] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_06_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_c6_01_mem_06_02_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_c6_01_mem_06_02_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_06_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gEvexTable_root_02_c6_01_mem_06_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_REG gEvexTable_root_02_c6_01_mem_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_c6_01_mem_01_l, + /* 02 */ (const void *)&gEvexTable_root_02_c6_01_mem_02_l, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ (const void *)&gEvexTable_root_02_c6_01_mem_05_l, + /* 06 */ (const void *)&gEvexTable_root_02_c6_01_mem_06_l, + /* 07 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_c6_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_02_c6_01_mem_modrmreg, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_c6_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_c6_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_01_02_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1676] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_01_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1677] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_01_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_c7_01_mem_01_02_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_c7_01_mem_01_02_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gEvexTable_root_02_c7_01_mem_01_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_02_02_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1680] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_02_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1681] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_02_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_c7_01_mem_02_02_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_c7_01_mem_02_02_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_02_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gEvexTable_root_02_c7_01_mem_02_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_05_02_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2436] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_05_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2437] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_05_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_c7_01_mem_05_02_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_c7_01_mem_05_02_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_05_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gEvexTable_root_02_c7_01_mem_05_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_06_02_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2440] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_06_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2441] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_06_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_c7_01_mem_06_02_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_c7_01_mem_06_02_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_06_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gEvexTable_root_02_c7_01_mem_06_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_REG gEvexTable_root_02_c7_01_mem_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_c7_01_mem_01_l, + /* 02 */ (const void *)&gEvexTable_root_02_c7_01_mem_02_l, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ (const void *)&gEvexTable_root_02_c7_01_mem_05_l, + /* 06 */ (const void *)&gEvexTable_root_02_c7_01_mem_06_l, + /* 07 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_c7_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_02_c7_01_mem_modrmreg, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_c7_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_c7_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_93_01_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1682] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_93_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1684] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_93_01_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_93_01_mem_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_93_01_mem_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_93_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_02_93_01_mem_w, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_93_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_93_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_42_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1686] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_42_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1687] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_42_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_42_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_42_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_42_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_42_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_43_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1688] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_43_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1689] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_43_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_43_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_43_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_43_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_43_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_cf_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1698] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_cf_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_cf_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_cf_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_cf_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_2a_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1806] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_2a_01_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_2a_01_mem_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_2a_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_02_2a_01_mem_w, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_2a_02_reg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1930] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_2a_02_reg_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_2a_02_reg_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_2a_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_2a_02_reg_w, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_2a_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_2a_01_modrmmod, + /* 02 */ (const void *)&gEvexTable_root_02_2a_02_modrmmod, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_68_03_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1870] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_68_03_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1871] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_68_03_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_68_03_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_68_03_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_68_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ (const void *)&gEvexTable_root_02_68_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_53_03_mem_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1873] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_53_03_mem_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_53_03_mem_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_02_53_03_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gEvexTable_root_02_53_03_mem_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_53_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_02_53_03_mem_l, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_53_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1987] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_53_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_53_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_53_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_53_01_w, + /* 02 */ NULL, + /* 03 */ (const void *)&gEvexTable_root_02_53_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_1c_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1874] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_1c_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_1c_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_1e_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1876] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_1e_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_1e_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_1e_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_1e_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_1f_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1878] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_1f_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_1f_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_1f_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_1f_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_1d_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1879] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_1d_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_1d_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_2b_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1885] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_2b_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_2b_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_2b_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_2b_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_66_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1918] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_66_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1921] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_66_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_66_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_66_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_66_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_66_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_64_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1919] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_64_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1920] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_64_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_64_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_64_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_64_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_64_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_78_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1924] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_78_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_78_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_78_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_78_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_7a_01_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1925] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_7a_01_reg_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_7a_01_reg_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_7a_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_7a_01_reg_w, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_7a_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_7a_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_58_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1927] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_58_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_58_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_58_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_58_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_7c_01_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1928] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_7c_01_reg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1933] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_7c_01_reg_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_7c_01_reg_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_7c_01_reg_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_7c_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_7c_01_reg_w, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_7c_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_7c_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_3a_02_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1931] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_3a_02_reg_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_3a_02_reg_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_3a_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_3a_02_reg_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_3a_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2138] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_3a_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_3a_01_leaf, + /* 02 */ (const void *)&gEvexTable_root_02_3a_02_modrmmod, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_79_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1935] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_79_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_79_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_79_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_79_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_7b_01_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1936] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_7b_01_reg_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_7b_01_reg_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_7b_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_7b_01_reg_w, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_7b_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_7b_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_29_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1948] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_29_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_29_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_29_02_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2140] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_29_02_reg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2183] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_29_02_reg_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_29_02_reg_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_29_02_reg_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_29_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_29_02_reg_w, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_29_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_29_01_w, + /* 02 */ (const void *)&gEvexTable_root_02_29_02_modrmmod, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_37_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1958] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_37_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_37_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_37_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_37_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_63_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1972] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_63_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1975] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_63_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_63_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_63_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_63_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_63_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_8b_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1973] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_8b_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1974] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_8b_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_8b_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_8b_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_8b_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_8b_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_c4_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1982] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_c4_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1983] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_c4_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_c4_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_c4_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_c4_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_c4_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_50_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1984] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_50_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_50_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_50_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_50_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_51_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1985] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_51_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_51_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_51_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_51_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_8d_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1990] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_8d_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2027] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_8d_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_8d_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_8d_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_8d_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_8d_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_36_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1991] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_36_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2018] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_36_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_36_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_36_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_36_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_36_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_75_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1993] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_75_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1998] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_75_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_75_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_75_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_75_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_75_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_76_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1994] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_76_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1997] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_76_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_76_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_76_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_76_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_76_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_77_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1995] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_77_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1996] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_77_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_77_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_77_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_77_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_77_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_0d_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1999] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_0d_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_0d_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_0d_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_0d_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_0c_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2003] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_0c_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_0c_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_0c_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_0c_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2011] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2015] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_16_01_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_16_01_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_16_01_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_02_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2012] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2016] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_16_01_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_16_01_02_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_16_01_02_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_02_16_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_16_01_01_w, + /* 02 */ (const void *)&gEvexTable_root_02_16_01_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_16_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_16_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_7d_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2021] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_7d_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2026] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_7d_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_7d_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_7d_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_7d_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_7d_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_7e_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2022] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_7e_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2025] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_7e_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_7e_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_7e_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_7e_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_7e_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_7f_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2023] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_7f_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2024] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_7f_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_7f_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_7f_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_7f_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_7f_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_62_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2028] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_62_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2031] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_62_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_62_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_62_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_62_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_62_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_89_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2029] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_89_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2030] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_89_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_89_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_89_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_89_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_89_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_90_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2046] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_90_01_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2048] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_90_01_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_90_01_mem_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_90_01_mem_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_90_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_02_90_01_mem_w, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_90_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_90_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_91_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2050] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_91_01_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2052] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_91_01_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_91_01_mem_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_91_01_mem_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_91_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_02_91_01_mem_w, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_91_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_91_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_44_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2088] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_44_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2089] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_44_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_44_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_44_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_44_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_44_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_b5_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2102] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_b5_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_b5_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_b5_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_b5_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_b4_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2103] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_b4_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_b4_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_b4_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_b4_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_04_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2104] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_04_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_04_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_3c_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2112] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_3c_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_3c_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_3d_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2114] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_3d_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2116] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_3d_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_3d_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_3d_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_3d_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_3d_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_3f_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2121] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_3f_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2123] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_3f_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_3f_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_3f_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_3f_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_3f_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_3e_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2124] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_3e_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_3e_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_38_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2126] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_38_02_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2145] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_38_02_reg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2146] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_38_02_reg_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_38_02_reg_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_38_02_reg_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_38_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_38_02_reg_w, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_38_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_38_01_leaf, + /* 02 */ (const void *)&gEvexTable_root_02_38_02_modrmmod, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2128] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2130] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_39_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_39_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_39_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_02_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2141] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_02_reg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2149] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_39_02_reg_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_39_02_reg_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_39_02_reg_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_39_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_39_02_reg_w, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_39_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_39_01_w, + /* 02 */ (const void *)&gEvexTable_root_02_39_02_modrmmod, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_3b_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2135] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_3b_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2137] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_3b_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_3b_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_3b_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_3b_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_3b_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_31_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2142] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_31_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_31_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_31_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2185] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_31_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_31_01_leaf, + /* 02 */ (const void *)&gEvexTable_root_02_31_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_33_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2143] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_33_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_33_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_33_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2197] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_33_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_33_01_leaf, + /* 02 */ (const void *)&gEvexTable_root_02_33_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_28_02_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2144] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_28_02_reg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2147] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_28_02_reg_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_28_02_reg_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_28_02_reg_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_28_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_28_02_reg_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_28_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2203] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_28_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_28_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_28_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_28_01_w, + /* 02 */ (const void *)&gEvexTable_root_02_28_02_modrmmod, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_32_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2150] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_32_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_32_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_32_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2188] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_32_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_32_01_leaf, + /* 02 */ (const void *)&gEvexTable_root_02_32_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_35_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2151] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_35_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_35_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_35_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2194] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_35_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_35_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_35_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_35_01_w, + /* 02 */ (const void *)&gEvexTable_root_02_35_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_34_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2152] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_34_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_34_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_34_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2200] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_34_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_34_01_leaf, + /* 02 */ (const void *)&gEvexTable_root_02_34_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_21_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2153] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_21_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_21_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_21_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2159] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_21_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_21_01_leaf, + /* 02 */ (const void *)&gEvexTable_root_02_21_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_23_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2154] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_23_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_23_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_23_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2171] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_23_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_23_01_leaf, + /* 02 */ (const void *)&gEvexTable_root_02_23_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_22_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2155] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_22_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_22_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_22_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2162] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_22_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_22_01_leaf, + /* 02 */ (const void *)&gEvexTable_root_02_22_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_25_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2156] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_25_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_25_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_25_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2168] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_25_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_25_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_25_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_25_01_w, + /* 02 */ (const void *)&gEvexTable_root_02_25_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_24_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2157] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_24_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_24_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_24_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2174] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_24_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_24_01_leaf, + /* 02 */ (const void *)&gEvexTable_root_02_24_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_20_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2158] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_20_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_20_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_20_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2165] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_20_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_20_01_leaf, + /* 02 */ (const void *)&gEvexTable_root_02_20_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_11_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2177] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_11_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_11_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_11_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2322] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_11_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_11_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_11_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_11_01_w, + /* 02 */ (const void *)&gEvexTable_root_02_11_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_12_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2179] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_12_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_12_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_12_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2308] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_12_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_12_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_12_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_12_01_w, + /* 02 */ (const void *)&gEvexTable_root_02_12_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_15_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2180] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_15_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_15_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_15_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2230] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_15_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2231] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_15_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_15_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_15_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_15_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_15_01_w, + /* 02 */ (const void *)&gEvexTable_root_02_15_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_14_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2181] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_14_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_14_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_14_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2234] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_14_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2235] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_14_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_14_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_14_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_14_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_14_01_w, + /* 02 */ (const void *)&gEvexTable_root_02_14_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_10_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2182] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_10_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_10_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_10_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2341] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_10_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_10_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_10_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_10_01_w, + /* 02 */ (const void *)&gEvexTable_root_02_10_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_30_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2184] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_30_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_30_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_30_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2191] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_30_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_30_01_leaf, + /* 02 */ (const void *)&gEvexTable_root_02_30_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_0b_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2205] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_0b_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_0b_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_40_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2211] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_40_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2213] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_40_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_40_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_40_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_40_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_40_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_83_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2216] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_83_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_83_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_83_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_83_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_54_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2219] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_54_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2222] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_54_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_54_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_54_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_54_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_54_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_55_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2220] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_55_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2221] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_55_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_55_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_55_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_55_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_55_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_a0_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2250] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_a0_01_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2251] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_a0_01_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_a0_01_mem_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_a0_01_mem_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_a0_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_02_a0_01_mem_w, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_a0_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_a0_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_a1_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2252] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_a1_01_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2253] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_a1_01_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_a1_01_mem_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_a1_01_mem_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_a1_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_02_a1_01_mem_w, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_a1_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_a1_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_71_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2270] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_71_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2271] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_71_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_71_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_71_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_71_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_71_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_70_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2272] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_70_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_70_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_70_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_70_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_73_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2278] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_73_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2279] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_73_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_73_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_73_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_73_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_73_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2282] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_00_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_00_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_8f_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2284] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_8f_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_8f_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_8f_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_8f_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_47_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2304] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_47_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2306] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_47_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_47_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_47_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_47_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_47_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_46_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2319] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_46_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2321] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_46_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_46_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_46_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_46_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_46_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_45_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2337] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_45_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2339] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_45_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_45_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_45_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_45_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_45_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2365] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2368] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_26_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_26_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_26_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2369] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_02_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2372] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_26_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_26_02_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_26_02_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_26_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_26_01_w, + /* 02 */ (const void *)&gEvexTable_root_02_26_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2366] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2367] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_27_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_27_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_27_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2370] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_02_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2371] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_27_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_27_02_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_27_02_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_27_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_27_01_w, + /* 02 */ (const void *)&gEvexTable_root_02_27_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_4c_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2396] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_4c_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2397] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_4c_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_4c_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_4c_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_4c_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_4c_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_4d_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2398] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_4d_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2399] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_4d_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_4d_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_4d_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_4d_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_4d_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_ca_01_02_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2400] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_ca_01_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2401] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_ca_01_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_ca_01_02_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_ca_01_02_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_02_ca_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gEvexTable_root_02_ca_01_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_ca_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_ca_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_cb_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2402] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_cb_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2403] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_cb_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_cb_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_cb_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_cb_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_cb_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_4e_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2418] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_4e_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2419] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_4e_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_4e_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_4e_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_4e_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_4e_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_4f_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2420] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_4f_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2421] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_4f_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_4f_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_4f_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_4f_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_4f_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_cc_01_02_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2422] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_cc_01_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2423] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_cc_01_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_cc_01_02_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_cc_01_02_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_02_cc_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gEvexTable_root_02_cc_01_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_cc_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_cc_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_cd_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2424] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_cd_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2425] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_cd_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_cd_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_cd_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_cd_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_cd_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_2c_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2428] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_2c_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2429] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_2c_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_2c_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_2c_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_2c_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_2c_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_2d_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2430] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_2d_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2431] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_2d_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_2d_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_2d_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_2d_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_2d_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_a2_01_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2432] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_a2_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2433] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_a2_01_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_a2_01_mem_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_a2_01_mem_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_a2_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_02_a2_01_mem_w, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_a2_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_a2_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_a3_01_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2442] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_02_a3_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2443] +}; + +const ND_TABLE_VEX_W gEvexTable_root_02_a3_01_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_02_a3_01_mem_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_02_a3_01_mem_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_02_a3_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_02_a3_01_mem_w, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_02_a3_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_02_a3_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_OPCODE gEvexTable_root_02_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ (const void *)&gEvexTable_root_02_00_pp, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ (const void *)&gEvexTable_root_02_04_pp, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + /* 08 */ NULL, + /* 09 */ NULL, + /* 0a */ NULL, + /* 0b */ (const void *)&gEvexTable_root_02_0b_pp, + /* 0c */ (const void *)&gEvexTable_root_02_0c_pp, + /* 0d */ (const void *)&gEvexTable_root_02_0d_pp, + /* 0e */ NULL, + /* 0f */ NULL, + /* 10 */ (const void *)&gEvexTable_root_02_10_pp, + /* 11 */ (const void *)&gEvexTable_root_02_11_pp, + /* 12 */ (const void *)&gEvexTable_root_02_12_pp, + /* 13 */ (const void *)&gEvexTable_root_02_13_pp, + /* 14 */ (const void *)&gEvexTable_root_02_14_pp, + /* 15 */ (const void *)&gEvexTable_root_02_15_pp, + /* 16 */ (const void *)&gEvexTable_root_02_16_pp, + /* 17 */ NULL, + /* 18 */ (const void *)&gEvexTable_root_02_18_pp, + /* 19 */ (const void *)&gEvexTable_root_02_19_pp, + /* 1a */ (const void *)&gEvexTable_root_02_1a_pp, + /* 1b */ (const void *)&gEvexTable_root_02_1b_pp, + /* 1c */ (const void *)&gEvexTable_root_02_1c_pp, + /* 1d */ (const void *)&gEvexTable_root_02_1d_pp, + /* 1e */ (const void *)&gEvexTable_root_02_1e_pp, + /* 1f */ (const void *)&gEvexTable_root_02_1f_pp, + /* 20 */ (const void *)&gEvexTable_root_02_20_pp, + /* 21 */ (const void *)&gEvexTable_root_02_21_pp, + /* 22 */ (const void *)&gEvexTable_root_02_22_pp, + /* 23 */ (const void *)&gEvexTable_root_02_23_pp, + /* 24 */ (const void *)&gEvexTable_root_02_24_pp, + /* 25 */ (const void *)&gEvexTable_root_02_25_pp, + /* 26 */ (const void *)&gEvexTable_root_02_26_pp, + /* 27 */ (const void *)&gEvexTable_root_02_27_pp, + /* 28 */ (const void *)&gEvexTable_root_02_28_pp, + /* 29 */ (const void *)&gEvexTable_root_02_29_pp, + /* 2a */ (const void *)&gEvexTable_root_02_2a_pp, + /* 2b */ (const void *)&gEvexTable_root_02_2b_pp, + /* 2c */ (const void *)&gEvexTable_root_02_2c_pp, + /* 2d */ (const void *)&gEvexTable_root_02_2d_pp, + /* 2e */ NULL, + /* 2f */ NULL, + /* 30 */ (const void *)&gEvexTable_root_02_30_pp, + /* 31 */ (const void *)&gEvexTable_root_02_31_pp, + /* 32 */ (const void *)&gEvexTable_root_02_32_pp, + /* 33 */ (const void *)&gEvexTable_root_02_33_pp, + /* 34 */ (const void *)&gEvexTable_root_02_34_pp, + /* 35 */ (const void *)&gEvexTable_root_02_35_pp, + /* 36 */ (const void *)&gEvexTable_root_02_36_pp, + /* 37 */ (const void *)&gEvexTable_root_02_37_pp, + /* 38 */ (const void *)&gEvexTable_root_02_38_pp, + /* 39 */ (const void *)&gEvexTable_root_02_39_pp, + /* 3a */ (const void *)&gEvexTable_root_02_3a_pp, + /* 3b */ (const void *)&gEvexTable_root_02_3b_pp, + /* 3c */ (const void *)&gEvexTable_root_02_3c_pp, + /* 3d */ (const void *)&gEvexTable_root_02_3d_pp, + /* 3e */ (const void *)&gEvexTable_root_02_3e_pp, + /* 3f */ (const void *)&gEvexTable_root_02_3f_pp, + /* 40 */ (const void *)&gEvexTable_root_02_40_pp, + /* 41 */ NULL, + /* 42 */ (const void *)&gEvexTable_root_02_42_pp, + /* 43 */ (const void *)&gEvexTable_root_02_43_pp, + /* 44 */ (const void *)&gEvexTable_root_02_44_pp, + /* 45 */ (const void *)&gEvexTable_root_02_45_pp, + /* 46 */ (const void *)&gEvexTable_root_02_46_pp, + /* 47 */ (const void *)&gEvexTable_root_02_47_pp, + /* 48 */ NULL, + /* 49 */ NULL, + /* 4a */ NULL, + /* 4b */ NULL, + /* 4c */ (const void *)&gEvexTable_root_02_4c_pp, + /* 4d */ (const void *)&gEvexTable_root_02_4d_pp, + /* 4e */ (const void *)&gEvexTable_root_02_4e_pp, + /* 4f */ (const void *)&gEvexTable_root_02_4f_pp, + /* 50 */ (const void *)&gEvexTable_root_02_50_pp, + /* 51 */ (const void *)&gEvexTable_root_02_51_pp, + /* 52 */ (const void *)&gEvexTable_root_02_52_pp, + /* 53 */ (const void *)&gEvexTable_root_02_53_pp, + /* 54 */ (const void *)&gEvexTable_root_02_54_pp, + /* 55 */ (const void *)&gEvexTable_root_02_55_pp, + /* 56 */ NULL, + /* 57 */ NULL, + /* 58 */ (const void *)&gEvexTable_root_02_58_pp, + /* 59 */ (const void *)&gEvexTable_root_02_59_pp, + /* 5a */ (const void *)&gEvexTable_root_02_5a_pp, + /* 5b */ (const void *)&gEvexTable_root_02_5b_pp, + /* 5c */ NULL, + /* 5d */ NULL, + /* 5e */ NULL, + /* 5f */ NULL, + /* 60 */ NULL, + /* 61 */ NULL, + /* 62 */ (const void *)&gEvexTable_root_02_62_pp, + /* 63 */ (const void *)&gEvexTable_root_02_63_pp, + /* 64 */ (const void *)&gEvexTable_root_02_64_pp, + /* 65 */ (const void *)&gEvexTable_root_02_65_pp, + /* 66 */ (const void *)&gEvexTable_root_02_66_pp, + /* 67 */ NULL, + /* 68 */ (const void *)&gEvexTable_root_02_68_pp, + /* 69 */ NULL, + /* 6a */ NULL, + /* 6b */ NULL, + /* 6c */ NULL, + /* 6d */ NULL, + /* 6e */ NULL, + /* 6f */ NULL, + /* 70 */ (const void *)&gEvexTable_root_02_70_pp, + /* 71 */ (const void *)&gEvexTable_root_02_71_pp, + /* 72 */ (const void *)&gEvexTable_root_02_72_pp, + /* 73 */ (const void *)&gEvexTable_root_02_73_pp, + /* 74 */ NULL, + /* 75 */ (const void *)&gEvexTable_root_02_75_pp, + /* 76 */ (const void *)&gEvexTable_root_02_76_pp, + /* 77 */ (const void *)&gEvexTable_root_02_77_pp, + /* 78 */ (const void *)&gEvexTable_root_02_78_pp, + /* 79 */ (const void *)&gEvexTable_root_02_79_pp, + /* 7a */ (const void *)&gEvexTable_root_02_7a_pp, + /* 7b */ (const void *)&gEvexTable_root_02_7b_pp, + /* 7c */ (const void *)&gEvexTable_root_02_7c_pp, + /* 7d */ (const void *)&gEvexTable_root_02_7d_pp, + /* 7e */ (const void *)&gEvexTable_root_02_7e_pp, + /* 7f */ (const void *)&gEvexTable_root_02_7f_pp, + /* 80 */ NULL, + /* 81 */ NULL, + /* 82 */ NULL, + /* 83 */ (const void *)&gEvexTable_root_02_83_pp, + /* 84 */ NULL, + /* 85 */ NULL, + /* 86 */ NULL, + /* 87 */ NULL, + /* 88 */ (const void *)&gEvexTable_root_02_88_pp, + /* 89 */ (const void *)&gEvexTable_root_02_89_pp, + /* 8a */ (const void *)&gEvexTable_root_02_8a_pp, + /* 8b */ (const void *)&gEvexTable_root_02_8b_pp, + /* 8c */ NULL, + /* 8d */ (const void *)&gEvexTable_root_02_8d_pp, + /* 8e */ NULL, + /* 8f */ (const void *)&gEvexTable_root_02_8f_pp, + /* 90 */ (const void *)&gEvexTable_root_02_90_pp, + /* 91 */ (const void *)&gEvexTable_root_02_91_pp, + /* 92 */ (const void *)&gEvexTable_root_02_92_pp, + /* 93 */ (const void *)&gEvexTable_root_02_93_pp, + /* 94 */ NULL, + /* 95 */ NULL, + /* 96 */ (const void *)&gEvexTable_root_02_96_pp, + /* 97 */ (const void *)&gEvexTable_root_02_97_pp, + /* 98 */ (const void *)&gEvexTable_root_02_98_pp, + /* 99 */ (const void *)&gEvexTable_root_02_99_pp, + /* 9a */ (const void *)&gEvexTable_root_02_9a_pp, + /* 9b */ (const void *)&gEvexTable_root_02_9b_pp, + /* 9c */ (const void *)&gEvexTable_root_02_9c_pp, + /* 9d */ (const void *)&gEvexTable_root_02_9d_pp, + /* 9e */ (const void *)&gEvexTable_root_02_9e_pp, + /* 9f */ (const void *)&gEvexTable_root_02_9f_pp, + /* a0 */ (const void *)&gEvexTable_root_02_a0_pp, + /* a1 */ (const void *)&gEvexTable_root_02_a1_pp, + /* a2 */ (const void *)&gEvexTable_root_02_a2_pp, + /* a3 */ (const void *)&gEvexTable_root_02_a3_pp, + /* a4 */ NULL, + /* a5 */ NULL, + /* a6 */ (const void *)&gEvexTable_root_02_a6_pp, + /* a7 */ (const void *)&gEvexTable_root_02_a7_pp, + /* a8 */ (const void *)&gEvexTable_root_02_a8_pp, + /* a9 */ (const void *)&gEvexTable_root_02_a9_pp, + /* aa */ (const void *)&gEvexTable_root_02_aa_pp, + /* ab */ (const void *)&gEvexTable_root_02_ab_pp, + /* ac */ (const void *)&gEvexTable_root_02_ac_pp, + /* ad */ (const void *)&gEvexTable_root_02_ad_pp, + /* ae */ (const void *)&gEvexTable_root_02_ae_pp, + /* af */ (const void *)&gEvexTable_root_02_af_pp, + /* b0 */ NULL, + /* b1 */ NULL, + /* b2 */ NULL, + /* b3 */ NULL, + /* b4 */ (const void *)&gEvexTable_root_02_b4_pp, + /* b5 */ (const void *)&gEvexTable_root_02_b5_pp, + /* b6 */ (const void *)&gEvexTable_root_02_b6_pp, + /* b7 */ (const void *)&gEvexTable_root_02_b7_pp, + /* b8 */ (const void *)&gEvexTable_root_02_b8_pp, + /* b9 */ (const void *)&gEvexTable_root_02_b9_pp, + /* ba */ (const void *)&gEvexTable_root_02_ba_pp, + /* bb */ (const void *)&gEvexTable_root_02_bb_pp, + /* bc */ (const void *)&gEvexTable_root_02_bc_pp, + /* bd */ (const void *)&gEvexTable_root_02_bd_pp, + /* be */ (const void *)&gEvexTable_root_02_be_pp, + /* bf */ (const void *)&gEvexTable_root_02_bf_pp, + /* c0 */ NULL, + /* c1 */ NULL, + /* c2 */ NULL, + /* c3 */ NULL, + /* c4 */ (const void *)&gEvexTable_root_02_c4_pp, + /* c5 */ NULL, + /* c6 */ (const void *)&gEvexTable_root_02_c6_pp, + /* c7 */ (const void *)&gEvexTable_root_02_c7_pp, + /* c8 */ (const void *)&gEvexTable_root_02_c8_pp, + /* c9 */ NULL, + /* ca */ (const void *)&gEvexTable_root_02_ca_pp, + /* cb */ (const void *)&gEvexTable_root_02_cb_pp, + /* cc */ (const void *)&gEvexTable_root_02_cc_pp, + /* cd */ (const void *)&gEvexTable_root_02_cd_pp, + /* ce */ NULL, + /* cf */ (const void *)&gEvexTable_root_02_cf_pp, + /* d0 */ NULL, + /* d1 */ NULL, + /* d2 */ NULL, + /* d3 */ NULL, + /* d4 */ NULL, + /* d5 */ NULL, + /* d6 */ NULL, + /* d7 */ NULL, + /* d8 */ NULL, + /* d9 */ NULL, + /* da */ NULL, + /* db */ NULL, + /* dc */ (const void *)&gEvexTable_root_02_dc_pp, + /* dd */ (const void *)&gEvexTable_root_02_dd_pp, + /* de */ (const void *)&gEvexTable_root_02_de_pp, + /* df */ (const void *)&gEvexTable_root_02_df_pp, + /* e0 */ NULL, + /* e1 */ NULL, + /* e2 */ NULL, + /* e3 */ NULL, + /* e4 */ NULL, + /* e5 */ NULL, + /* e6 */ NULL, + /* e7 */ NULL, + /* e8 */ NULL, + /* e9 */ NULL, + /* ea */ NULL, + /* eb */ NULL, + /* ec */ NULL, + /* ed */ NULL, + /* ee */ NULL, + /* ef */ NULL, + /* f0 */ NULL, + /* f1 */ NULL, + /* f2 */ NULL, + /* f3 */ NULL, + /* f4 */ NULL, + /* f5 */ NULL, + /* f6 */ NULL, + /* f7 */ NULL, + /* f8 */ NULL, + /* f9 */ NULL, + /* fa */ NULL, + /* fb */ NULL, + /* fc */ NULL, + /* fd */ NULL, + /* fe */ NULL, + /* ff */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1331] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_58_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_58_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1333] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_58_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_58_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_03_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1335] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_58_03_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_58_03_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1337] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_58_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_58_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_58_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_58_00_w, + /* 01 */ (const void *)&gEvexTable_root_01_58_01_w, + /* 02 */ (const void *)&gEvexTable_root_01_58_02_w, + /* 03 */ (const void *)&gEvexTable_root_01_58_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_55_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1353] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_55_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_55_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_55_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1355] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_55_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_55_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_55_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_55_00_w, + /* 01 */ (const void *)&gEvexTable_root_01_55_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_54_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1357] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_54_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_54_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_54_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1359] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_54_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_54_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_54_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_54_00_w, + /* 01 */ (const void *)&gEvexTable_root_01_54_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1383] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_c2_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_c2_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1385] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_c2_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_c2_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_03_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1386] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_c2_03_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_c2_03_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1388] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_c2_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_c2_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_c2_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_c2_00_w, + /* 01 */ (const void *)&gEvexTable_root_01_c2_01_w, + /* 02 */ (const void *)&gEvexTable_root_01_c2_02_w, + /* 03 */ (const void *)&gEvexTable_root_01_c2_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_2f_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1391] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_2f_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_2f_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_2f_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1393] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_2f_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_2f_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_2f_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_2f_00_w, + /* 01 */ (const void *)&gEvexTable_root_01_2f_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1397] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_02_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1426] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_e6_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_e6_02_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_01_e6_02_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_03_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1404] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_e6_03_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_e6_03_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1443] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_e6_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_e6_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_e6_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_e6_01_w, + /* 02 */ (const void *)&gEvexTable_root_01_e6_02_w, + /* 03 */ (const void *)&gEvexTable_root_01_e6_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1400] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1427] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_5b_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_5b_00_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_01_5b_00_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1415] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_5b_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_5b_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1448] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_5b_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_5b_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_5b_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_5b_00_w, + /* 01 */ (const void *)&gEvexTable_root_01_5b_01_w, + /* 02 */ (const void *)&gEvexTable_root_01_5b_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1406] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_5a_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_5a_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1417] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_5a_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_5a_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_03_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1430] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_5a_03_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_5a_03_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1438] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_5a_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_5a_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_5a_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_5a_00_w, + /* 01 */ (const void *)&gEvexTable_root_01_5a_01_w, + /* 02 */ (const void *)&gEvexTable_root_01_5a_02_w, + /* 03 */ (const void *)&gEvexTable_root_01_5a_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1409] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1423] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_7b_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_7b_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_01_7b_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_03_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1463] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_03_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1464] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_7b_03_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_7b_03_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_01_7b_03_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1465] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_7b_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_7b_01_w, + /* 02 */ (const void *)&gEvexTable_root_01_7b_02_leaf, + /* 03 */ (const void *)&gEvexTable_root_01_7b_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1410] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1424] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_79_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_79_00_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_01_79_00_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1411] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1425] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_79_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_79_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_01_79_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1432] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1442] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_79_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_79_00_w, + /* 01 */ (const void *)&gEvexTable_root_01_79_01_w, + /* 02 */ (const void *)&gEvexTable_root_01_79_02_leaf, + /* 03 */ (const void *)&gEvexTable_root_01_79_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_2d_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1428] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_2d_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1440] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_2d_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gEvexTable_root_01_2d_02_leaf, + /* 03 */ (const void *)&gEvexTable_root_01_2d_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_2a_03_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1433] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_2a_03_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1434] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_2a_03_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_2a_03_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_01_2a_03_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_2a_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1436] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_2a_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gEvexTable_root_01_2a_02_leaf, + /* 03 */ (const void *)&gEvexTable_root_01_2a_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1445] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1450] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_7a_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_7a_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_01_7a_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1459] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_02_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1461] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_7a_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_7a_02_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_01_7a_02_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_03_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1460] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_03_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1462] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_7a_03_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_7a_03_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_01_7a_03_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_7a_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_7a_01_w, + /* 02 */ (const void *)&gEvexTable_root_01_7a_02_w, + /* 03 */ (const void *)&gEvexTable_root_01_7a_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1446] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1451] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_78_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_78_00_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_01_78_00_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1447] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1452] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_78_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_78_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_01_78_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1455] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1458] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_78_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_78_00_w, + /* 01 */ (const void *)&gEvexTable_root_01_78_01_w, + /* 02 */ (const void *)&gEvexTable_root_01_78_02_leaf, + /* 03 */ (const void *)&gEvexTable_root_01_78_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_2c_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1453] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_2c_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1456] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_2c_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gEvexTable_root_01_2c_02_leaf, + /* 03 */ (const void *)&gEvexTable_root_01_2c_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1467] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_5e_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_5e_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1469] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_5e_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_5e_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_03_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1471] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_5e_03_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_5e_03_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1473] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_5e_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_5e_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_5e_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_5e_00_w, + /* 01 */ (const void *)&gEvexTable_root_01_5e_01_w, + /* 02 */ (const void *)&gEvexTable_root_01_5e_02_w, + /* 03 */ (const void *)&gEvexTable_root_01_5e_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1725] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_5f_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_5f_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1727] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_5f_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_5f_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_03_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1729] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_5f_03_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_5f_03_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1731] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_5f_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_5f_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_5f_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_5f_00_w, + /* 01 */ (const void *)&gEvexTable_root_01_5f_01_w, + /* 02 */ (const void *)&gEvexTable_root_01_5f_02_w, + /* 03 */ (const void *)&gEvexTable_root_01_5f_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1738] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_5d_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_5d_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1740] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_5d_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_5d_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_03_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1742] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_5d_03_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_5d_03_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1744] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_5d_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_5d_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_5d_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_5d_00_w, + /* 01 */ (const void *)&gEvexTable_root_01_5d_01_w, + /* 02 */ (const void *)&gEvexTable_root_01_5d_02_w, + /* 03 */ (const void *)&gEvexTable_root_01_5d_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_28_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1749] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_28_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_28_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_28_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1753] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_28_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_28_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_28_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_28_00_w, + /* 01 */ (const void *)&gEvexTable_root_01_28_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_29_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1750] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_29_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_29_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_29_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1754] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_29_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_29_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_29_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_29_00_w, + /* 01 */ (const void *)&gEvexTable_root_01_29_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_6e_01_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1757] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_6e_01_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1812] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_6e_01_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_6e_01_00_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_01_6e_01_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_01_6e_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_01_6e_01_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_6e_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_6e_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_7e_01_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1758] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_7e_01_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1813] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_7e_01_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_7e_01_00_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_01_7e_01_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_01_7e_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_01_7e_01_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_7e_02_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1814] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_7e_02_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_7e_02_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_01_7e_02_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_01_7e_02_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_7e_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_7e_01_l, + /* 02 */ (const void *)&gEvexTable_root_01_7e_02_l, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_03_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1761] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_12_03_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_12_03_00_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_03_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1762] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_12_03_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_12_03_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_03_02_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1763] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_12_03_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_12_03_02_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_01_12_03_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_01_12_03_00_w, + /* 01 */ (const void *)&gEvexTable_root_01_12_03_01_w, + /* 02 */ (const void *)&gEvexTable_root_01_12_03_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_00_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1782] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_12_00_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_12_00_reg_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_01_12_00_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_01_12_00_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_00_mem_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1798] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_12_00_mem_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_12_00_mem_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_01_12_00_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_01_12_00_mem_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_01_12_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_01_12_00_mem_l, + /* 01 */ (const void *)&gEvexTable_root_01_12_00_reg_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_01_mem_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1794] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_12_01_mem_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_12_01_mem_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_01_12_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_01_12_01_mem_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_01_12_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_01_12_01_mem_l, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1830] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_12_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_12_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_12_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_12_00_modrmmod, + /* 01 */ (const void *)&gEvexTable_root_01_12_01_modrmmod, + /* 02 */ (const void *)&gEvexTable_root_01_12_02_w, + /* 03 */ (const void *)&gEvexTable_root_01_12_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1768] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1770] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_6f_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_6f_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_01_6f_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_03_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1774] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_03_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1780] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_6f_03_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_6f_03_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_01_6f_03_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1776] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_02_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1778] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_6f_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_6f_02_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_01_6f_02_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_6f_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_6f_01_w, + /* 02 */ (const void *)&gEvexTable_root_01_6f_02_w, + /* 03 */ (const void *)&gEvexTable_root_01_6f_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1769] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1771] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_7f_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_7f_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_01_7f_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_03_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1775] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_03_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1781] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_7f_03_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_7f_03_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_01_7f_03_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1777] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_02_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1779] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_7f_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_7f_02_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_01_7f_02_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_7f_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_7f_01_w, + /* 02 */ (const void *)&gEvexTable_root_01_7f_02_w, + /* 03 */ (const void *)&gEvexTable_root_01_7f_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_01_mem_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1784] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_16_01_mem_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_16_01_mem_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_01_16_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_01_16_01_mem_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_01_16_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_01_16_01_mem_l, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_00_mem_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1788] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_16_00_mem_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_16_00_mem_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_01_16_00_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_01_16_00_mem_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_00_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1792] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_16_00_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_16_00_reg_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_01_16_00_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_01_16_00_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_01_16_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_01_16_00_mem_l, + /* 01 */ (const void *)&gEvexTable_root_01_16_00_reg_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1828] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_16_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_16_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_16_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_16_00_modrmmod, + /* 01 */ (const void *)&gEvexTable_root_01_16_01_modrmmod, + /* 02 */ (const void *)&gEvexTable_root_01_16_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_17_01_mem_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1785] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_17_01_mem_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_17_01_mem_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_01_17_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_01_17_01_mem_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_01_17_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_01_17_01_mem_l, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_17_00_mem_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1789] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_17_00_mem_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_17_00_mem_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_01_17_00_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_01_17_00_mem_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_01_17_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_01_17_00_mem_l, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_17_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_17_00_modrmmod, + /* 01 */ (const void *)&gEvexTable_root_01_17_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_13_01_mem_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1795] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_13_01_mem_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_13_01_mem_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_01_13_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_01_13_01_mem_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_01_13_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_01_13_01_mem_l, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_13_00_mem_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1799] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_13_00_mem_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_13_00_mem_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_01_13_00_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_01_13_00_mem_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_01_13_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_01_13_00_mem_l, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_13_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_13_00_modrmmod, + /* 01 */ (const void *)&gEvexTable_root_01_13_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_e7_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1804] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_e7_01_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_e7_01_mem_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_01_e7_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_01_e7_01_mem_w, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_e7_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_e7_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_2b_01_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1808] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_2b_01_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_2b_01_mem_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_01_2b_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_01_2b_01_mem_w, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_2b_00_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1810] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_2b_00_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_2b_00_mem_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_01_2b_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_01_2b_00_mem_w, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_2b_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_2b_00_modrmmod, + /* 01 */ (const void *)&gEvexTable_root_01_2b_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_d6_01_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1815] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_d6_01_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_d6_01_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_01_d6_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_01_d6_01_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_d6_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_d6_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_03_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1820] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_10_03_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_10_03_mem_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_03_reg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1821] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_10_03_reg_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_10_03_reg_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_01_10_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_01_10_03_mem_w, + /* 01 */ (const void *)&gEvexTable_root_01_10_03_reg_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_02_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1832] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_10_02_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_10_02_mem_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_02_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1833] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_10_02_reg_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_10_02_reg_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_01_10_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_01_10_02_mem_w, + /* 01 */ (const void *)&gEvexTable_root_01_10_02_reg_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1840] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_10_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_10_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1844] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_10_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_10_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_10_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_10_00_w, + /* 01 */ (const void *)&gEvexTable_root_01_10_01_w, + /* 02 */ (const void *)&gEvexTable_root_01_10_02_modrmmod, + /* 03 */ (const void *)&gEvexTable_root_01_10_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_03_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1822] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_11_03_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_11_03_mem_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_03_reg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1823] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_11_03_reg_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_11_03_reg_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_01_11_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_01_11_03_mem_w, + /* 01 */ (const void *)&gEvexTable_root_01_11_03_reg_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_02_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1834] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_11_02_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_11_02_mem_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_02_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1835] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_11_02_reg_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_11_02_reg_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_01_11_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_01_11_02_mem_w, + /* 01 */ (const void *)&gEvexTable_root_01_11_02_reg_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1841] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_11_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_11_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1845] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_11_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_11_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_11_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_11_00_w, + /* 01 */ (const void *)&gEvexTable_root_01_11_01_w, + /* 02 */ (const void *)&gEvexTable_root_01_11_02_modrmmod, + /* 03 */ (const void *)&gEvexTable_root_01_11_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1855] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_59_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_59_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1857] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_59_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_59_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_03_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1859] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_59_03_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_59_03_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1861] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_59_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_59_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_59_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_59_00_w, + /* 01 */ (const void *)&gEvexTable_root_01_59_01_w, + /* 02 */ (const void *)&gEvexTable_root_01_59_02_w, + /* 03 */ (const void *)&gEvexTable_root_01_59_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_56_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1866] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_56_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_56_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_56_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1868] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_56_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_56_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_56_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_56_00_w, + /* 01 */ (const void *)&gEvexTable_root_01_56_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_6b_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1881] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_6b_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_6b_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_6b_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_6b_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_63_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1883] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_63_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_63_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_67_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1887] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_67_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_67_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_fc_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1889] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_fc_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_fc_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_fe_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1891] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_fe_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_fe_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_fe_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_fe_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_d4_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1893] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_d4_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_d4_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_d4_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_d4_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_ec_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1895] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_ec_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_ec_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_ed_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1897] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_ed_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_ed_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_dc_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1899] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_dc_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_dc_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_dd_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1901] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_dd_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_dd_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_fd_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1903] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_fd_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_fd_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_db_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1908] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_db_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1912] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_db_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_db_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_01_db_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_db_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_db_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_df_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1910] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_df_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1911] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_df_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_df_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_01_df_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_df_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_df_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_e0_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1913] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_e0_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_e0_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_e3_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1915] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_e3_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_e3_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_74_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1944] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_74_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_74_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_76_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1946] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_76_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_76_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_75_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1950] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_75_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_75_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_64_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1954] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_64_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_64_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_66_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1956] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_66_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_66_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_66_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_66_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_65_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1960] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_65_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_65_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_c5_01_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2040] +}; + +const ND_TABLE_VEX_L gEvexTable_root_01_c5_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_01_c5_01_reg_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_01_c5_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_c5_01_reg_l, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_c5_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_c5_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_c4_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2084] +}; + +const ND_TABLE_VEX_L gEvexTable_root_01_c4_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_01_c4_01_mem_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_c4_01_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2085] +}; + +const ND_TABLE_VEX_L gEvexTable_root_01_c4_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_01_c4_01_reg_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_01_c4_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_01_c4_01_mem_l, + /* 01 */ (const void *)&gEvexTable_root_01_c4_01_reg_l, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_c4_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_c4_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_f5_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2106] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_f5_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_f5_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_ee_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2117] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_ee_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_ee_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_de_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2119] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_de_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_de_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_ea_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2131] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_ea_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_ea_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_da_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2133] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_da_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_da_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_e4_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2207] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_e4_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_e4_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_e5_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2209] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_e5_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_e5_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_d5_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2214] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_d5_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_d5_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_f4_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2217] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_f4_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_f4_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_f4_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_f4_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_eb_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2224] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_eb_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2225] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_eb_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_eb_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_01_eb_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_eb_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_eb_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2228] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2229] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_72_01_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_72_01_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_01_72_01_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2232] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2233] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_72_01_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_72_01_00_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_01_72_01_00_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_06_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2294] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_72_01_06_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_72_01_06_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_04_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2313] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_04_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2317] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_72_01_04_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_72_01_04_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_01_72_01_04_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2327] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_72_01_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_72_01_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_MODRM_REG gEvexTable_root_01_72_01_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexTable_root_01_72_01_00_w, + /* 01 */ (const void *)&gEvexTable_root_01_72_01_01_w, + /* 02 */ (const void *)&gEvexTable_root_01_72_01_02_w, + /* 03 */ NULL, + /* 04 */ (const void *)&gEvexTable_root_01_72_01_04_w, + /* 05 */ NULL, + /* 06 */ (const void *)&gEvexTable_root_01_72_01_06_w, + /* 07 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_72_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_72_01_modrmreg, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_f6_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2248] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_f6_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_f6_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_70_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2285] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_70_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_70_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_70_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2287] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_70_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2289] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_70_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_70_01_w, + /* 02 */ (const void *)&gEvexTable_root_01_70_02_leaf, + /* 03 */ (const void *)&gEvexTable_root_01_70_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_f2_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2295] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_f2_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_f2_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_f2_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_f2_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2298] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_06_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2300] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_73_01_06_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_73_01_06_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2331] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_02_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2333] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_73_01_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_73_01_02_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gEvexTable_root_01_73_01_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gEvexTable_root_01_73_01_02_w, + /* 03 */ (const void *)&gEvexTable_root_01_73_01_03_leaf, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ (const void *)&gEvexTable_root_01_73_01_06_w, + /* 07 */ (const void *)&gEvexTable_root_01_73_01_07_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_73_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_73_01_modrmreg, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_f3_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2301] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_f3_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_f3_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_f3_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_f3_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_71_01_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2309] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_71_01_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2323] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_71_01_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2342] +}; + +const ND_TABLE_MODRM_REG gEvexTable_root_01_71_01_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gEvexTable_root_01_71_01_02_leaf, + /* 03 */ NULL, + /* 04 */ (const void *)&gEvexTable_root_01_71_01_04_leaf, + /* 05 */ NULL, + /* 06 */ (const void *)&gEvexTable_root_01_71_01_06_leaf, + /* 07 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_71_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_71_01_modrmreg, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_f1_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2310] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_f1_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_f1_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_e2_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2314] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_e2_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2318] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_e2_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_e2_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_01_e2_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_e2_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_e2_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_e1_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2324] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_e1_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_e1_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_d2_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2328] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_d2_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_d2_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_d2_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_d2_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_d3_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2334] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_d3_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_d3_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_d3_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_d3_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_d1_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2343] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_d1_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_d1_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_f8_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2346] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_f8_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_f8_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_fa_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2348] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_fa_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_fa_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_fa_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_fa_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_fb_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2350] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_fb_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_fb_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_fb_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_fb_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_e8_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2352] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_e8_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_e8_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_e9_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2354] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_e9_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_e9_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_d8_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2356] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_d8_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_d8_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_d9_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2358] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_d9_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_d9_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_f9_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2360] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_f9_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_f9_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_68_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2373] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_68_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_68_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_6a_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2375] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_6a_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_6a_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_6a_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_6a_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_6d_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2377] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_6d_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_6d_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_6d_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_6d_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_69_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2379] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_69_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_69_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_60_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2381] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_60_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_60_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_62_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2383] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_62_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_62_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_62_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_62_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_6c_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2385] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_6c_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_6c_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_6c_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_6c_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_61_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2387] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_61_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_61_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_ef_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2390] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_ef_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2391] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_ef_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_ef_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_01_ef_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_ef_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_ef_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_c6_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2448] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_c6_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_c6_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_c6_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2450] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_c6_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_c6_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_c6_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_c6_00_w, + /* 01 */ (const void *)&gEvexTable_root_01_c6_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2452] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_51_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_51_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2454] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_51_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_51_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_03_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2456] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_51_03_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_51_03_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2458] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_51_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_51_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_51_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_51_00_w, + /* 01 */ (const void *)&gEvexTable_root_01_51_01_w, + /* 02 */ (const void *)&gEvexTable_root_01_51_02_w, + /* 03 */ (const void *)&gEvexTable_root_01_51_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2461] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_5c_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_5c_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2463] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_5c_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_5c_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_03_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2465] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_5c_03_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_5c_03_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2467] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_5c_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_5c_02_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_5c_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_5c_00_w, + /* 01 */ (const void *)&gEvexTable_root_01_5c_01_w, + /* 02 */ (const void *)&gEvexTable_root_01_5c_02_w, + /* 03 */ (const void *)&gEvexTable_root_01_5c_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_2e_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2471] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_2e_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_2e_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_2e_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2473] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_2e_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_2e_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_2e_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_2e_00_w, + /* 01 */ (const void *)&gEvexTable_root_01_2e_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_15_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2475] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_15_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_15_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_15_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2477] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_15_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_15_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_15_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_15_00_w, + /* 01 */ (const void *)&gEvexTable_root_01_15_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_14_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2479] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_14_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_14_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_14_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2481] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_14_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_14_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_14_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_14_00_w, + /* 01 */ (const void *)&gEvexTable_root_01_14_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_57_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2483] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_57_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_57_01_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_01_57_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2485] +}; + +const ND_TABLE_VEX_W gEvexTable_root_01_57_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_01_57_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_01_57_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gEvexTable_root_01_57_00_w, + /* 01 */ (const void *)&gEvexTable_root_01_57_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_OPCODE gEvexTable_root_01_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + /* 08 */ NULL, + /* 09 */ NULL, + /* 0a */ NULL, + /* 0b */ NULL, + /* 0c */ NULL, + /* 0d */ NULL, + /* 0e */ NULL, + /* 0f */ NULL, + /* 10 */ (const void *)&gEvexTable_root_01_10_pp, + /* 11 */ (const void *)&gEvexTable_root_01_11_pp, + /* 12 */ (const void *)&gEvexTable_root_01_12_pp, + /* 13 */ (const void *)&gEvexTable_root_01_13_pp, + /* 14 */ (const void *)&gEvexTable_root_01_14_pp, + /* 15 */ (const void *)&gEvexTable_root_01_15_pp, + /* 16 */ (const void *)&gEvexTable_root_01_16_pp, + /* 17 */ (const void *)&gEvexTable_root_01_17_pp, + /* 18 */ NULL, + /* 19 */ NULL, + /* 1a */ NULL, + /* 1b */ NULL, + /* 1c */ NULL, + /* 1d */ NULL, + /* 1e */ NULL, + /* 1f */ NULL, + /* 20 */ NULL, + /* 21 */ NULL, + /* 22 */ NULL, + /* 23 */ NULL, + /* 24 */ NULL, + /* 25 */ NULL, + /* 26 */ NULL, + /* 27 */ NULL, + /* 28 */ (const void *)&gEvexTable_root_01_28_pp, + /* 29 */ (const void *)&gEvexTable_root_01_29_pp, + /* 2a */ (const void *)&gEvexTable_root_01_2a_pp, + /* 2b */ (const void *)&gEvexTable_root_01_2b_pp, + /* 2c */ (const void *)&gEvexTable_root_01_2c_pp, + /* 2d */ (const void *)&gEvexTable_root_01_2d_pp, + /* 2e */ (const void *)&gEvexTable_root_01_2e_pp, + /* 2f */ (const void *)&gEvexTable_root_01_2f_pp, + /* 30 */ NULL, + /* 31 */ NULL, + /* 32 */ NULL, + /* 33 */ NULL, + /* 34 */ NULL, + /* 35 */ NULL, + /* 36 */ NULL, + /* 37 */ NULL, + /* 38 */ NULL, + /* 39 */ NULL, + /* 3a */ NULL, + /* 3b */ NULL, + /* 3c */ NULL, + /* 3d */ NULL, + /* 3e */ NULL, + /* 3f */ NULL, + /* 40 */ NULL, + /* 41 */ NULL, + /* 42 */ NULL, + /* 43 */ NULL, + /* 44 */ NULL, + /* 45 */ NULL, + /* 46 */ NULL, + /* 47 */ NULL, + /* 48 */ NULL, + /* 49 */ NULL, + /* 4a */ NULL, + /* 4b */ NULL, + /* 4c */ NULL, + /* 4d */ NULL, + /* 4e */ NULL, + /* 4f */ NULL, + /* 50 */ NULL, + /* 51 */ (const void *)&gEvexTable_root_01_51_pp, + /* 52 */ NULL, + /* 53 */ NULL, + /* 54 */ (const void *)&gEvexTable_root_01_54_pp, + /* 55 */ (const void *)&gEvexTable_root_01_55_pp, + /* 56 */ (const void *)&gEvexTable_root_01_56_pp, + /* 57 */ (const void *)&gEvexTable_root_01_57_pp, + /* 58 */ (const void *)&gEvexTable_root_01_58_pp, + /* 59 */ (const void *)&gEvexTable_root_01_59_pp, + /* 5a */ (const void *)&gEvexTable_root_01_5a_pp, + /* 5b */ (const void *)&gEvexTable_root_01_5b_pp, + /* 5c */ (const void *)&gEvexTable_root_01_5c_pp, + /* 5d */ (const void *)&gEvexTable_root_01_5d_pp, + /* 5e */ (const void *)&gEvexTable_root_01_5e_pp, + /* 5f */ (const void *)&gEvexTable_root_01_5f_pp, + /* 60 */ (const void *)&gEvexTable_root_01_60_pp, + /* 61 */ (const void *)&gEvexTable_root_01_61_pp, + /* 62 */ (const void *)&gEvexTable_root_01_62_pp, + /* 63 */ (const void *)&gEvexTable_root_01_63_pp, + /* 64 */ (const void *)&gEvexTable_root_01_64_pp, + /* 65 */ (const void *)&gEvexTable_root_01_65_pp, + /* 66 */ (const void *)&gEvexTable_root_01_66_pp, + /* 67 */ (const void *)&gEvexTable_root_01_67_pp, + /* 68 */ (const void *)&gEvexTable_root_01_68_pp, + /* 69 */ (const void *)&gEvexTable_root_01_69_pp, + /* 6a */ (const void *)&gEvexTable_root_01_6a_pp, + /* 6b */ (const void *)&gEvexTable_root_01_6b_pp, + /* 6c */ (const void *)&gEvexTable_root_01_6c_pp, + /* 6d */ (const void *)&gEvexTable_root_01_6d_pp, + /* 6e */ (const void *)&gEvexTable_root_01_6e_pp, + /* 6f */ (const void *)&gEvexTable_root_01_6f_pp, + /* 70 */ (const void *)&gEvexTable_root_01_70_pp, + /* 71 */ (const void *)&gEvexTable_root_01_71_pp, + /* 72 */ (const void *)&gEvexTable_root_01_72_pp, + /* 73 */ (const void *)&gEvexTable_root_01_73_pp, + /* 74 */ (const void *)&gEvexTable_root_01_74_pp, + /* 75 */ (const void *)&gEvexTable_root_01_75_pp, + /* 76 */ (const void *)&gEvexTable_root_01_76_pp, + /* 77 */ NULL, + /* 78 */ (const void *)&gEvexTable_root_01_78_pp, + /* 79 */ (const void *)&gEvexTable_root_01_79_pp, + /* 7a */ (const void *)&gEvexTable_root_01_7a_pp, + /* 7b */ (const void *)&gEvexTable_root_01_7b_pp, + /* 7c */ NULL, + /* 7d */ NULL, + /* 7e */ (const void *)&gEvexTable_root_01_7e_pp, + /* 7f */ (const void *)&gEvexTable_root_01_7f_pp, + /* 80 */ NULL, + /* 81 */ NULL, + /* 82 */ NULL, + /* 83 */ NULL, + /* 84 */ NULL, + /* 85 */ NULL, + /* 86 */ NULL, + /* 87 */ NULL, + /* 88 */ NULL, + /* 89 */ NULL, + /* 8a */ NULL, + /* 8b */ NULL, + /* 8c */ NULL, + /* 8d */ NULL, + /* 8e */ NULL, + /* 8f */ NULL, + /* 90 */ NULL, + /* 91 */ NULL, + /* 92 */ NULL, + /* 93 */ NULL, + /* 94 */ NULL, + /* 95 */ NULL, + /* 96 */ NULL, + /* 97 */ NULL, + /* 98 */ NULL, + /* 99 */ NULL, + /* 9a */ NULL, + /* 9b */ NULL, + /* 9c */ NULL, + /* 9d */ NULL, + /* 9e */ NULL, + /* 9f */ NULL, + /* a0 */ NULL, + /* a1 */ NULL, + /* a2 */ NULL, + /* a3 */ NULL, + /* a4 */ NULL, + /* a5 */ NULL, + /* a6 */ NULL, + /* a7 */ NULL, + /* a8 */ NULL, + /* a9 */ NULL, + /* aa */ NULL, + /* ab */ NULL, + /* ac */ NULL, + /* ad */ NULL, + /* ae */ NULL, + /* af */ NULL, + /* b0 */ NULL, + /* b1 */ NULL, + /* b2 */ NULL, + /* b3 */ NULL, + /* b4 */ NULL, + /* b5 */ NULL, + /* b6 */ NULL, + /* b7 */ NULL, + /* b8 */ NULL, + /* b9 */ NULL, + /* ba */ NULL, + /* bb */ NULL, + /* bc */ NULL, + /* bd */ NULL, + /* be */ NULL, + /* bf */ NULL, + /* c0 */ NULL, + /* c1 */ NULL, + /* c2 */ (const void *)&gEvexTable_root_01_c2_pp, + /* c3 */ NULL, + /* c4 */ (const void *)&gEvexTable_root_01_c4_pp, + /* c5 */ (const void *)&gEvexTable_root_01_c5_pp, + /* c6 */ (const void *)&gEvexTable_root_01_c6_pp, + /* c7 */ NULL, + /* c8 */ NULL, + /* c9 */ NULL, + /* ca */ NULL, + /* cb */ NULL, + /* cc */ NULL, + /* cd */ NULL, + /* ce */ NULL, + /* cf */ NULL, + /* d0 */ NULL, + /* d1 */ (const void *)&gEvexTable_root_01_d1_pp, + /* d2 */ (const void *)&gEvexTable_root_01_d2_pp, + /* d3 */ (const void *)&gEvexTable_root_01_d3_pp, + /* d4 */ (const void *)&gEvexTable_root_01_d4_pp, + /* d5 */ (const void *)&gEvexTable_root_01_d5_pp, + /* d6 */ (const void *)&gEvexTable_root_01_d6_pp, + /* d7 */ NULL, + /* d8 */ (const void *)&gEvexTable_root_01_d8_pp, + /* d9 */ (const void *)&gEvexTable_root_01_d9_pp, + /* da */ (const void *)&gEvexTable_root_01_da_pp, + /* db */ (const void *)&gEvexTable_root_01_db_pp, + /* dc */ (const void *)&gEvexTable_root_01_dc_pp, + /* dd */ (const void *)&gEvexTable_root_01_dd_pp, + /* de */ (const void *)&gEvexTable_root_01_de_pp, + /* df */ (const void *)&gEvexTable_root_01_df_pp, + /* e0 */ (const void *)&gEvexTable_root_01_e0_pp, + /* e1 */ (const void *)&gEvexTable_root_01_e1_pp, + /* e2 */ (const void *)&gEvexTable_root_01_e2_pp, + /* e3 */ (const void *)&gEvexTable_root_01_e3_pp, + /* e4 */ (const void *)&gEvexTable_root_01_e4_pp, + /* e5 */ (const void *)&gEvexTable_root_01_e5_pp, + /* e6 */ (const void *)&gEvexTable_root_01_e6_pp, + /* e7 */ (const void *)&gEvexTable_root_01_e7_pp, + /* e8 */ (const void *)&gEvexTable_root_01_e8_pp, + /* e9 */ (const void *)&gEvexTable_root_01_e9_pp, + /* ea */ (const void *)&gEvexTable_root_01_ea_pp, + /* eb */ (const void *)&gEvexTable_root_01_eb_pp, + /* ec */ (const void *)&gEvexTable_root_01_ec_pp, + /* ed */ (const void *)&gEvexTable_root_01_ed_pp, + /* ee */ (const void *)&gEvexTable_root_01_ee_pp, + /* ef */ (const void *)&gEvexTable_root_01_ef_pp, + /* f0 */ NULL, + /* f1 */ (const void *)&gEvexTable_root_01_f1_pp, + /* f2 */ (const void *)&gEvexTable_root_01_f2_pp, + /* f3 */ (const void *)&gEvexTable_root_01_f3_pp, + /* f4 */ (const void *)&gEvexTable_root_01_f4_pp, + /* f5 */ (const void *)&gEvexTable_root_01_f5_pp, + /* f6 */ (const void *)&gEvexTable_root_01_f6_pp, + /* f7 */ NULL, + /* f8 */ (const void *)&gEvexTable_root_01_f8_pp, + /* f9 */ (const void *)&gEvexTable_root_01_f9_pp, + /* fa */ (const void *)&gEvexTable_root_01_fa_pp, + /* fb */ (const void *)&gEvexTable_root_01_fb_pp, + /* fc */ (const void *)&gEvexTable_root_01_fc_pp, + /* fd */ (const void *)&gEvexTable_root_01_fd_pp, + /* fe */ (const void *)&gEvexTable_root_01_fe_pp, + /* ff */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_03_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1351] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_03_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1352] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_03_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_03_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_03_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_03_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_03_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_1d_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1420] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_1d_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_1d_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_1d_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_1d_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_42_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1466] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_42_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_42_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_42_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_42_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_19_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1485] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_19_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1487] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_19_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_19_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_19_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_19_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_19_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_1b_01_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1486] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_1b_01_02_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1488] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_1b_01_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_1b_01_02_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_1b_01_02_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_03_1b_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gEvexTable_root_03_1b_01_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_1b_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_1b_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_39_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1490] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_39_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1492] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_39_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_39_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_39_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_39_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_39_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_3b_01_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1491] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_3b_01_02_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1493] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_3b_01_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_3b_01_02_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_3b_01_02_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_03_3b_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gEvexTable_root_03_3b_01_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_3b_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_3b_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_17_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1494] +}; + +const ND_TABLE_VEX_L gEvexTable_root_03_17_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_03_17_01_mem_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_17_01_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1495] +}; + +const ND_TABLE_VEX_L gEvexTable_root_03_17_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_03_17_01_reg_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_03_17_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_03_17_01_mem_l, + /* 01 */ (const void *)&gEvexTable_root_03_17_01_reg_l, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_17_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_17_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_54_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1498] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_54_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1499] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_54_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_54_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_54_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_54_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_54_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_55_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1500] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_55_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1501] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_55_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_55_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_55_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_55_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_55_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_66_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1662] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_66_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1663] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_66_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_66_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_66_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_66_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_66_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_67_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1664] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_67_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1665] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_67_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_67_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_67_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_67_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_67_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_26_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1690] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_26_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1691] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_26_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_26_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_26_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_26_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_26_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_27_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1692] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_27_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1693] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_27_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_27_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_27_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_27_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_27_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_cf_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1694] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_cf_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_cf_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_cf_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_cf_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_ce_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1696] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_ce_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_ce_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_ce_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_ce_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_18_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1705] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_18_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1707] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_18_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_18_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_18_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_18_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_18_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_1a_01_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1706] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_1a_01_02_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1708] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_1a_01_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_1a_01_02_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_1a_01_02_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_03_1a_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gEvexTable_root_03_1a_01_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_1a_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_1a_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_38_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1710] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_38_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1712] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_38_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_38_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_38_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_38_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_38_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_3a_01_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1711] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_3a_01_02_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1713] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_3a_01_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_3a_01_02_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_3a_01_02_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_03_3a_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gEvexTable_root_03_3a_01_02_w, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_3a_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_3a_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_21_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1714] +}; + +const ND_TABLE_VEX_L gEvexTable_root_03_21_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_03_21_01_mem_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_21_01_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1715] +}; + +const ND_TABLE_VEX_L gEvexTable_root_03_21_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_03_21_01_reg_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_03_21_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_03_21_01_mem_l, + /* 01 */ (const void *)&gEvexTable_root_03_21_01_reg_l, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_21_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_21_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_0f_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1905] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_0f_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_0f_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_44_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1938] +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_44_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_44_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_3f_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1942] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_3f_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1969] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_3f_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_3f_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_3f_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_3f_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_3f_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_1f_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1943] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_1f_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1964] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_1f_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_1f_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_1f_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_1f_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_1f_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_3e_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1965] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_3e_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1968] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_3e_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_3e_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_3e_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_3e_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_3e_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_1e_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1966] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_1e_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1967] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_1e_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_1e_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_1e_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_1e_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_1e_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_05_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2000] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_05_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_05_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_05_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_05_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_04_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2004] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_04_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_04_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_04_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_04_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_01_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2013] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_01_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_01_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_01_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_01_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_00_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2019] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_00_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_00_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_00_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_00_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_14_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2032] +}; + +const ND_TABLE_VEX_L gEvexTable_root_03_14_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_03_14_01_mem_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_14_01_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2033] +}; + +const ND_TABLE_VEX_L gEvexTable_root_03_14_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_03_14_01_reg_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_03_14_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_03_14_01_mem_l, + /* 01 */ (const void *)&gEvexTable_root_03_14_01_reg_l, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_14_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_14_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_16_01_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2036] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_16_01_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2038] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_16_01_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_16_01_00_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_16_01_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_03_16_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_03_16_01_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_16_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_16_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_15_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2041] +}; + +const ND_TABLE_VEX_L gEvexTable_root_03_15_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_03_15_01_mem_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_15_01_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2042] +}; + +const ND_TABLE_VEX_L gEvexTable_root_03_15_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_03_15_01_reg_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_03_15_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_03_15_01_mem_l, + /* 01 */ (const void *)&gEvexTable_root_03_15_01_reg_l, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_15_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_15_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_20_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2076] +}; + +const ND_TABLE_VEX_L gEvexTable_root_03_20_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_03_20_01_mem_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_20_01_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2077] +}; + +const ND_TABLE_VEX_L gEvexTable_root_03_20_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_03_20_01_reg_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexTable_root_03_20_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_03_20_01_mem_l, + /* 01 */ (const void *)&gEvexTable_root_03_20_01_reg_l, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_20_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_20_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_22_01_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2080] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_22_01_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2082] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_22_01_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_22_01_00_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_22_01_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_03_22_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_03_22_01_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_22_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_22_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_71_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2268] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_71_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2269] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_71_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_71_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_71_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_71_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_71_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_70_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2273] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_70_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_70_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_70_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_70_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_73_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2276] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_73_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2277] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_73_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_73_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_73_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_73_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_73_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_72_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2281] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_72_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_72_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_72_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_72_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_25_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2362] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_25_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2363] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_25_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_25_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_25_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_25_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_25_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_50_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2392] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_50_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2393] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_50_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_50_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_50_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_50_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_50_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_51_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2394] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_51_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2395] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_51_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_51_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_51_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_51_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_51_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_56_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2406] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_56_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2407] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_56_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_56_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_56_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_56_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_56_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_57_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2408] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_57_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2409] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_57_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_57_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_57_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_57_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_57_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_09_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2410] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_09_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_09_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_09_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_09_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_08_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2411] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_08_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_08_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_08_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_08_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_0b_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2412] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_0b_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_0b_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_0b_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_0b_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_0a_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2413] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_0a_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_0a_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_0a_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_0a_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_23_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2444] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_23_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2445] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_23_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_23_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_23_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_23_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_23_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_43_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2446] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_43_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2447] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_43_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gEvexTable_root_03_43_01_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_43_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gEvexTable_root_03_43_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_03_43_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_OPCODE gEvexTable_root_03_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ (const void *)&gEvexTable_root_03_00_pp, + /* 01 */ (const void *)&gEvexTable_root_03_01_pp, + /* 02 */ NULL, + /* 03 */ (const void *)&gEvexTable_root_03_03_pp, + /* 04 */ (const void *)&gEvexTable_root_03_04_pp, + /* 05 */ (const void *)&gEvexTable_root_03_05_pp, + /* 06 */ NULL, + /* 07 */ NULL, + /* 08 */ (const void *)&gEvexTable_root_03_08_pp, + /* 09 */ (const void *)&gEvexTable_root_03_09_pp, + /* 0a */ (const void *)&gEvexTable_root_03_0a_pp, + /* 0b */ (const void *)&gEvexTable_root_03_0b_pp, + /* 0c */ NULL, + /* 0d */ NULL, + /* 0e */ NULL, + /* 0f */ (const void *)&gEvexTable_root_03_0f_pp, + /* 10 */ NULL, + /* 11 */ NULL, + /* 12 */ NULL, + /* 13 */ NULL, + /* 14 */ (const void *)&gEvexTable_root_03_14_pp, + /* 15 */ (const void *)&gEvexTable_root_03_15_pp, + /* 16 */ (const void *)&gEvexTable_root_03_16_pp, + /* 17 */ (const void *)&gEvexTable_root_03_17_pp, + /* 18 */ (const void *)&gEvexTable_root_03_18_pp, + /* 19 */ (const void *)&gEvexTable_root_03_19_pp, + /* 1a */ (const void *)&gEvexTable_root_03_1a_pp, + /* 1b */ (const void *)&gEvexTable_root_03_1b_pp, + /* 1c */ NULL, + /* 1d */ (const void *)&gEvexTable_root_03_1d_pp, + /* 1e */ (const void *)&gEvexTable_root_03_1e_pp, + /* 1f */ (const void *)&gEvexTable_root_03_1f_pp, + /* 20 */ (const void *)&gEvexTable_root_03_20_pp, + /* 21 */ (const void *)&gEvexTable_root_03_21_pp, + /* 22 */ (const void *)&gEvexTable_root_03_22_pp, + /* 23 */ (const void *)&gEvexTable_root_03_23_pp, + /* 24 */ NULL, + /* 25 */ (const void *)&gEvexTable_root_03_25_pp, + /* 26 */ (const void *)&gEvexTable_root_03_26_pp, + /* 27 */ (const void *)&gEvexTable_root_03_27_pp, + /* 28 */ NULL, + /* 29 */ NULL, + /* 2a */ NULL, + /* 2b */ NULL, + /* 2c */ NULL, + /* 2d */ NULL, + /* 2e */ NULL, + /* 2f */ NULL, + /* 30 */ NULL, + /* 31 */ NULL, + /* 32 */ NULL, + /* 33 */ NULL, + /* 34 */ NULL, + /* 35 */ NULL, + /* 36 */ NULL, + /* 37 */ NULL, + /* 38 */ (const void *)&gEvexTable_root_03_38_pp, + /* 39 */ (const void *)&gEvexTable_root_03_39_pp, + /* 3a */ (const void *)&gEvexTable_root_03_3a_pp, + /* 3b */ (const void *)&gEvexTable_root_03_3b_pp, + /* 3c */ NULL, + /* 3d */ NULL, + /* 3e */ (const void *)&gEvexTable_root_03_3e_pp, + /* 3f */ (const void *)&gEvexTable_root_03_3f_pp, + /* 40 */ NULL, + /* 41 */ NULL, + /* 42 */ (const void *)&gEvexTable_root_03_42_pp, + /* 43 */ (const void *)&gEvexTable_root_03_43_pp, + /* 44 */ (const void *)&gEvexTable_root_03_44_pp, + /* 45 */ NULL, + /* 46 */ NULL, + /* 47 */ NULL, + /* 48 */ NULL, + /* 49 */ NULL, + /* 4a */ NULL, + /* 4b */ NULL, + /* 4c */ NULL, + /* 4d */ NULL, + /* 4e */ NULL, + /* 4f */ NULL, + /* 50 */ (const void *)&gEvexTable_root_03_50_pp, + /* 51 */ (const void *)&gEvexTable_root_03_51_pp, + /* 52 */ NULL, + /* 53 */ NULL, + /* 54 */ (const void *)&gEvexTable_root_03_54_pp, + /* 55 */ (const void *)&gEvexTable_root_03_55_pp, + /* 56 */ (const void *)&gEvexTable_root_03_56_pp, + /* 57 */ (const void *)&gEvexTable_root_03_57_pp, + /* 58 */ NULL, + /* 59 */ NULL, + /* 5a */ NULL, + /* 5b */ NULL, + /* 5c */ NULL, + /* 5d */ NULL, + /* 5e */ NULL, + /* 5f */ NULL, + /* 60 */ NULL, + /* 61 */ NULL, + /* 62 */ NULL, + /* 63 */ NULL, + /* 64 */ NULL, + /* 65 */ NULL, + /* 66 */ (const void *)&gEvexTable_root_03_66_pp, + /* 67 */ (const void *)&gEvexTable_root_03_67_pp, + /* 68 */ NULL, + /* 69 */ NULL, + /* 6a */ NULL, + /* 6b */ NULL, + /* 6c */ NULL, + /* 6d */ NULL, + /* 6e */ NULL, + /* 6f */ NULL, + /* 70 */ (const void *)&gEvexTable_root_03_70_pp, + /* 71 */ (const void *)&gEvexTable_root_03_71_pp, + /* 72 */ (const void *)&gEvexTable_root_03_72_pp, + /* 73 */ (const void *)&gEvexTable_root_03_73_pp, + /* 74 */ NULL, + /* 75 */ NULL, + /* 76 */ NULL, + /* 77 */ NULL, + /* 78 */ NULL, + /* 79 */ NULL, + /* 7a */ NULL, + /* 7b */ NULL, + /* 7c */ NULL, + /* 7d */ NULL, + /* 7e */ NULL, + /* 7f */ NULL, + /* 80 */ NULL, + /* 81 */ NULL, + /* 82 */ NULL, + /* 83 */ NULL, + /* 84 */ NULL, + /* 85 */ NULL, + /* 86 */ NULL, + /* 87 */ NULL, + /* 88 */ NULL, + /* 89 */ NULL, + /* 8a */ NULL, + /* 8b */ NULL, + /* 8c */ NULL, + /* 8d */ NULL, + /* 8e */ NULL, + /* 8f */ NULL, + /* 90 */ NULL, + /* 91 */ NULL, + /* 92 */ NULL, + /* 93 */ NULL, + /* 94 */ NULL, + /* 95 */ NULL, + /* 96 */ NULL, + /* 97 */ NULL, + /* 98 */ NULL, + /* 99 */ NULL, + /* 9a */ NULL, + /* 9b */ NULL, + /* 9c */ NULL, + /* 9d */ NULL, + /* 9e */ NULL, + /* 9f */ NULL, + /* a0 */ NULL, + /* a1 */ NULL, + /* a2 */ NULL, + /* a3 */ NULL, + /* a4 */ NULL, + /* a5 */ NULL, + /* a6 */ NULL, + /* a7 */ NULL, + /* a8 */ NULL, + /* a9 */ NULL, + /* aa */ NULL, + /* ab */ NULL, + /* ac */ NULL, + /* ad */ NULL, + /* ae */ NULL, + /* af */ NULL, + /* b0 */ NULL, + /* b1 */ NULL, + /* b2 */ NULL, + /* b3 */ NULL, + /* b4 */ NULL, + /* b5 */ NULL, + /* b6 */ NULL, + /* b7 */ NULL, + /* b8 */ NULL, + /* b9 */ NULL, + /* ba */ NULL, + /* bb */ NULL, + /* bc */ NULL, + /* bd */ NULL, + /* be */ NULL, + /* bf */ NULL, + /* c0 */ NULL, + /* c1 */ NULL, + /* c2 */ NULL, + /* c3 */ NULL, + /* c4 */ NULL, + /* c5 */ NULL, + /* c6 */ NULL, + /* c7 */ NULL, + /* c8 */ NULL, + /* c9 */ NULL, + /* ca */ NULL, + /* cb */ NULL, + /* cc */ NULL, + /* cd */ NULL, + /* ce */ (const void *)&gEvexTable_root_03_ce_pp, + /* cf */ (const void *)&gEvexTable_root_03_cf_pp, + /* d0 */ NULL, + /* d1 */ NULL, + /* d2 */ NULL, + /* d3 */ NULL, + /* d4 */ NULL, + /* d5 */ NULL, + /* d6 */ NULL, + /* d7 */ NULL, + /* d8 */ NULL, + /* d9 */ NULL, + /* da */ NULL, + /* db */ NULL, + /* dc */ NULL, + /* dd */ NULL, + /* de */ NULL, + /* df */ NULL, + /* e0 */ NULL, + /* e1 */ NULL, + /* e2 */ NULL, + /* e3 */ NULL, + /* e4 */ NULL, + /* e5 */ NULL, + /* e6 */ NULL, + /* e7 */ NULL, + /* e8 */ NULL, + /* e9 */ NULL, + /* ea */ NULL, + /* eb */ NULL, + /* ec */ NULL, + /* ed */ NULL, + /* ee */ NULL, + /* ef */ NULL, + /* f0 */ NULL, + /* f1 */ NULL, + /* f2 */ NULL, + /* f3 */ NULL, + /* f4 */ NULL, + /* f5 */ NULL, + /* f6 */ NULL, + /* f7 */ NULL, + /* f8 */ NULL, + /* f9 */ NULL, + /* fa */ NULL, + /* fb */ NULL, + /* fc */ NULL, + /* fd */ NULL, + /* fe */ NULL, + /* ff */ NULL, + } +}; + +const ND_TABLE_VEX_MMMMM gEvexTable_root_mmmmm = +{ + ND_ILUT_VEX_MMMMM, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gEvexTable_root_01_opcode, + /* 02 */ (const void *)&gEvexTable_root_02_opcode, + /* 03 */ (const void *)&gEvexTable_root_03_opcode, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + /* 08 */ NULL, + /* 09 */ NULL, + /* 0a */ NULL, + /* 0b */ NULL, + /* 0c */ NULL, + /* 0d */ NULL, + /* 0e */ NULL, + /* 0f */ NULL, + /* 10 */ NULL, + /* 11 */ NULL, + /* 12 */ NULL, + /* 13 */ NULL, + /* 14 */ NULL, + /* 15 */ NULL, + /* 16 */ NULL, + /* 17 */ NULL, + /* 18 */ NULL, + /* 19 */ NULL, + /* 1a */ NULL, + /* 1b */ NULL, + /* 1c */ NULL, + /* 1d */ NULL, + /* 1e */ NULL, + /* 1f */ NULL, + } +}; + +const PND_TABLE gEvexTable = (const PND_TABLE)&gEvexTable_root_mmmmm; + + +#endif + diff --git a/bddisasm/include/table_root.h b/bddisasm/include/table_root.h new file mode 100644 index 0000000..c22784d --- /dev/null +++ b/bddisasm/include/table_root.h @@ -0,0 +1,15555 @@ +#ifndef _TABLE_ROOT_H_ +#define _TABLE_ROOT_H_ + +const ND_TABLE_INSTRUCTION gRootTable_root_37_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[0] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d5_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d4_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_3f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[3] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_10_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[4] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_11_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[5] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_12_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[6] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_13_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[7] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_14_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[8] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_15_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[9] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_80_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[10] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_80_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[21] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_80_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[45] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_80_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[144] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_80_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[780] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_80_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1182] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_80_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1277] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_80_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2529] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_80_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_80_00_leaf, + /* 01 */ (const void *)&gRootTable_root_80_01_leaf, + /* 02 */ (const void *)&gRootTable_root_80_02_leaf, + /* 03 */ (const void *)&gRootTable_root_80_03_leaf, + /* 04 */ (const void *)&gRootTable_root_80_04_leaf, + /* 05 */ (const void *)&gRootTable_root_80_05_leaf, + /* 06 */ (const void *)&gRootTable_root_80_06_leaf, + /* 07 */ (const void *)&gRootTable_root_80_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_81_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[11] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_81_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[22] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_81_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[46] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_81_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[145] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_81_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[781] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_81_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1183] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_81_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1278] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_81_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2530] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_81_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_81_00_leaf, + /* 01 */ (const void *)&gRootTable_root_81_01_leaf, + /* 02 */ (const void *)&gRootTable_root_81_02_leaf, + /* 03 */ (const void *)&gRootTable_root_81_03_leaf, + /* 04 */ (const void *)&gRootTable_root_81_04_leaf, + /* 05 */ (const void *)&gRootTable_root_81_05_leaf, + /* 06 */ (const void *)&gRootTable_root_81_06_leaf, + /* 07 */ (const void *)&gRootTable_root_81_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_82_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[12] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_82_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[23] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_82_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[47] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_82_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[146] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_82_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[782] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_82_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1184] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_82_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1279] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_82_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2531] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_82_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_82_00_leaf, + /* 01 */ (const void *)&gRootTable_root_82_01_leaf, + /* 02 */ (const void *)&gRootTable_root_82_02_leaf, + /* 03 */ (const void *)&gRootTable_root_82_03_leaf, + /* 04 */ (const void *)&gRootTable_root_82_04_leaf, + /* 05 */ (const void *)&gRootTable_root_82_05_leaf, + /* 06 */ (const void *)&gRootTable_root_82_06_leaf, + /* 07 */ (const void *)&gRootTable_root_82_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_83_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[13] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_83_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[24] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_83_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[48] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_83_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[147] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_83_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[783] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_83_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1185] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_83_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1280] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_83_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2532] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_83_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_83_00_leaf, + /* 01 */ (const void *)&gRootTable_root_83_01_leaf, + /* 02 */ (const void *)&gRootTable_root_83_02_leaf, + /* 03 */ (const void *)&gRootTable_root_83_03_leaf, + /* 04 */ (const void *)&gRootTable_root_83_04_leaf, + /* 05 */ (const void *)&gRootTable_root_83_05_leaf, + /* 06 */ (const void *)&gRootTable_root_83_06_leaf, + /* 07 */ (const void *)&gRootTable_root_83_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[14] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[31] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_NP_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2497] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_NP_rexw_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2498] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_38_f6_mem_NP_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_f6_mem_NP_None_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_38_f6_mem_NP_rexw_leaf, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_f6_mem_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_f6_mem_NP_auxiliary, + /* 01 */ (const void *)&gRootTable_root_0f_38_f6_mem_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_38_f6_mem_F3_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_reg_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[14] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_reg_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[31] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_f6_reg_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_f6_reg_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_38_f6_reg_F3_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f6_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_f6_mem_mprefix, + /* 01 */ (const void *)&gRootTable_root_0f_38_f6_reg_mprefix, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_de_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[32] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_de_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_de_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_df_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[33] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_df_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_df_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_dc_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[34] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_dc_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_dc_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_dd_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[35] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_dd_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_dd_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_db_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[36] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_db_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_db_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_15_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[64] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_15_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_15_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_14_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[65] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_14_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_14_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_mem_F2_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[170] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_mem_F2_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[171] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_f0_mem_F2_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_f0_mem_F2_None_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_38_f0_mem_F2_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_mem_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[642] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_mem_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[643] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_f0_mem_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_f0_mem_None_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_38_f0_mem_66_leaf, + /* 02 */ NULL, + /* 03 */ (const void *)&gRootTable_root_0f_38_f0_mem_F2_mprefix, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_reg_F2_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[170] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_reg_F2_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[171] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_f0_reg_F2_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_f0_reg_F2_None_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_38_f0_reg_F2_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_f0_reg_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ (const void *)&gRootTable_root_0f_38_f0_reg_F2_mprefix, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f0_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_f0_mem_mprefix, + /* 01 */ (const void *)&gRootTable_root_0f_38_f0_reg_mprefix, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_mem_F2_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[172] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_mem_F2_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[173] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_f1_mem_F2_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_f1_mem_F2_None_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_38_f1_mem_F2_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_mem_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[644] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_mem_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[645] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_f1_mem_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_f1_mem_None_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_38_f1_mem_66_leaf, + /* 02 */ NULL, + /* 03 */ (const void *)&gRootTable_root_0f_38_f1_mem_F2_mprefix, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_reg_F2_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[172] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_reg_F2_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[173] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_f1_reg_F2_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_f1_reg_F2_None_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_38_f1_reg_F2_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_f1_reg_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ (const void *)&gRootTable_root_0f_38_f1_reg_F2_mprefix, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f1_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_f1_mem_mprefix, + /* 01 */ (const void *)&gRootTable_root_0f_38_f1_reg_mprefix, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f8_mem_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[226] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f8_mem_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[227] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f8_mem_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[651] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_f8_mem_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_f8_mem_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_38_f8_mem_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_38_f8_mem_F2_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f8_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_f8_mem_mprefix, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cf_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[385] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_cf_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_cf_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_80_mem_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[429] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_80_mem_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_80_mem_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_80_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_80_mem_mprefix, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_82_mem_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[433] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_82_mem_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_82_mem_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_82_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_82_mem_mprefix, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_81_mem_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[434] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_81_mem_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_81_mem_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_81_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_81_mem_mprefix, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f9_mem_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[652] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_f9_mem_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_f9_mem_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f9_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_f9_mem_mprefix, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_2a_mem_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[670] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_2a_mem_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_2a_mem_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_2a_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_2a_mem_mprefix, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1c_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[796] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1c_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[797] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_1c_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_1c_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_38_1c_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1e_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[798] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1e_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[799] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_1e_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_1e_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_38_1e_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1d_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[800] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1d_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[801] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_1d_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_1d_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_38_1d_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_2b_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[806] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_2b_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_2b_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_10_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[837] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_10_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_10_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_29_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[844] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_29_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_29_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_37_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[853] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_37_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_37_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_02_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[891] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_02_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[892] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_02_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_02_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_38_02_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_03_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[893] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_03_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[894] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_03_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_03_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_38_03_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_01_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[895] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_01_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[896] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_01_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_01_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_38_01_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_41_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[897] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_41_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_41_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_06_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[898] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_06_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[899] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_06_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_06_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_38_06_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_07_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[900] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_07_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[901] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_07_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_07_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_38_07_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_05_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[902] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_05_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[903] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_05_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_05_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_38_05_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_04_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[914] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_04_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[915] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_04_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_04_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_38_04_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3c_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[918] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_3c_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_3c_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3d_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[919] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_3d_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_3d_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3f_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[924] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_3f_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_3f_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3e_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[925] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_3e_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_3e_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_38_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[926] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_38_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_38_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_39_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[927] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_39_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_39_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3b_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[932] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_3b_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_3b_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3a_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[933] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_3a_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_3a_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_21_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[936] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_21_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_21_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_22_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[937] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_22_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_22_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_20_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[938] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_20_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_20_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_25_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[939] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_25_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_25_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_23_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[940] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_23_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_23_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_24_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[941] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_24_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_24_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_31_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[942] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_31_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_31_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_32_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[943] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_32_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_32_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_30_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[944] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_30_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_30_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_35_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[945] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_35_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_35_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_33_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[946] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_33_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_33_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_34_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[947] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_34_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_34_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_28_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[948] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_28_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_28_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0b_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[949] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0b_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[950] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_0b_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_0b_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_38_0b_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_40_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[956] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_40_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_40_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_00_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[996] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_00_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[997] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_00_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_00_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_38_00_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_08_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1002] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_08_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1003] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_08_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_08_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_38_08_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0a_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1004] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0a_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1005] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_0a_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_0a_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_38_0a_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_09_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1006] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_09_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1007] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_09_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_09_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_38_09_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_17_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1060] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_17_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_17_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_c9_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1214] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_c9_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_c9_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_ca_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1215] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_ca_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_ca_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_c8_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1216] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_c8_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_c8_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cc_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1218] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_cc_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_cc_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cd_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1219] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_cd_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_cd_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cb_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1220] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_cb_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_cb_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f5_mem_66_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2499] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f5_mem_66_rexw_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2500] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_38_f5_mem_66_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_f5_mem_66_None_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_38_f5_mem_66_rexw_leaf, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_38_f5_mem_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_38_f5_mem_66_auxiliary, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f5_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_f5_mem_mprefix, + /* 01 */ NULL, + } +}; + +const ND_TABLE_OPCODE gRootTable_root_0f_38_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ (const void *)&gRootTable_root_0f_38_00_mprefix, + /* 01 */ (const void *)&gRootTable_root_0f_38_01_mprefix, + /* 02 */ (const void *)&gRootTable_root_0f_38_02_mprefix, + /* 03 */ (const void *)&gRootTable_root_0f_38_03_mprefix, + /* 04 */ (const void *)&gRootTable_root_0f_38_04_mprefix, + /* 05 */ (const void *)&gRootTable_root_0f_38_05_mprefix, + /* 06 */ (const void *)&gRootTable_root_0f_38_06_mprefix, + /* 07 */ (const void *)&gRootTable_root_0f_38_07_mprefix, + /* 08 */ (const void *)&gRootTable_root_0f_38_08_mprefix, + /* 09 */ (const void *)&gRootTable_root_0f_38_09_mprefix, + /* 0a */ (const void *)&gRootTable_root_0f_38_0a_mprefix, + /* 0b */ (const void *)&gRootTable_root_0f_38_0b_mprefix, + /* 0c */ NULL, + /* 0d */ NULL, + /* 0e */ NULL, + /* 0f */ NULL, + /* 10 */ (const void *)&gRootTable_root_0f_38_10_mprefix, + /* 11 */ NULL, + /* 12 */ NULL, + /* 13 */ NULL, + /* 14 */ (const void *)&gRootTable_root_0f_38_14_mprefix, + /* 15 */ (const void *)&gRootTable_root_0f_38_15_mprefix, + /* 16 */ NULL, + /* 17 */ (const void *)&gRootTable_root_0f_38_17_mprefix, + /* 18 */ NULL, + /* 19 */ NULL, + /* 1a */ NULL, + /* 1b */ NULL, + /* 1c */ (const void *)&gRootTable_root_0f_38_1c_mprefix, + /* 1d */ (const void *)&gRootTable_root_0f_38_1d_mprefix, + /* 1e */ (const void *)&gRootTable_root_0f_38_1e_mprefix, + /* 1f */ NULL, + /* 20 */ (const void *)&gRootTable_root_0f_38_20_mprefix, + /* 21 */ (const void *)&gRootTable_root_0f_38_21_mprefix, + /* 22 */ (const void *)&gRootTable_root_0f_38_22_mprefix, + /* 23 */ (const void *)&gRootTable_root_0f_38_23_mprefix, + /* 24 */ (const void *)&gRootTable_root_0f_38_24_mprefix, + /* 25 */ (const void *)&gRootTable_root_0f_38_25_mprefix, + /* 26 */ NULL, + /* 27 */ NULL, + /* 28 */ (const void *)&gRootTable_root_0f_38_28_mprefix, + /* 29 */ (const void *)&gRootTable_root_0f_38_29_mprefix, + /* 2a */ (const void *)&gRootTable_root_0f_38_2a_modrmmod, + /* 2b */ (const void *)&gRootTable_root_0f_38_2b_mprefix, + /* 2c */ NULL, + /* 2d */ NULL, + /* 2e */ NULL, + /* 2f */ NULL, + /* 30 */ (const void *)&gRootTable_root_0f_38_30_mprefix, + /* 31 */ (const void *)&gRootTable_root_0f_38_31_mprefix, + /* 32 */ (const void *)&gRootTable_root_0f_38_32_mprefix, + /* 33 */ (const void *)&gRootTable_root_0f_38_33_mprefix, + /* 34 */ (const void *)&gRootTable_root_0f_38_34_mprefix, + /* 35 */ (const void *)&gRootTable_root_0f_38_35_mprefix, + /* 36 */ NULL, + /* 37 */ (const void *)&gRootTable_root_0f_38_37_mprefix, + /* 38 */ (const void *)&gRootTable_root_0f_38_38_mprefix, + /* 39 */ (const void *)&gRootTable_root_0f_38_39_mprefix, + /* 3a */ (const void *)&gRootTable_root_0f_38_3a_mprefix, + /* 3b */ (const void *)&gRootTable_root_0f_38_3b_mprefix, + /* 3c */ (const void *)&gRootTable_root_0f_38_3c_mprefix, + /* 3d */ (const void *)&gRootTable_root_0f_38_3d_mprefix, + /* 3e */ (const void *)&gRootTable_root_0f_38_3e_mprefix, + /* 3f */ (const void *)&gRootTable_root_0f_38_3f_mprefix, + /* 40 */ (const void *)&gRootTable_root_0f_38_40_mprefix, + /* 41 */ (const void *)&gRootTable_root_0f_38_41_mprefix, + /* 42 */ NULL, + /* 43 */ NULL, + /* 44 */ NULL, + /* 45 */ NULL, + /* 46 */ NULL, + /* 47 */ NULL, + /* 48 */ NULL, + /* 49 */ NULL, + /* 4a */ NULL, + /* 4b */ NULL, + /* 4c */ NULL, + /* 4d */ NULL, + /* 4e */ NULL, + /* 4f */ NULL, + /* 50 */ NULL, + /* 51 */ NULL, + /* 52 */ NULL, + /* 53 */ NULL, + /* 54 */ NULL, + /* 55 */ NULL, + /* 56 */ NULL, + /* 57 */ NULL, + /* 58 */ NULL, + /* 59 */ NULL, + /* 5a */ NULL, + /* 5b */ NULL, + /* 5c */ NULL, + /* 5d */ NULL, + /* 5e */ NULL, + /* 5f */ NULL, + /* 60 */ NULL, + /* 61 */ NULL, + /* 62 */ NULL, + /* 63 */ NULL, + /* 64 */ NULL, + /* 65 */ NULL, + /* 66 */ NULL, + /* 67 */ NULL, + /* 68 */ NULL, + /* 69 */ NULL, + /* 6a */ NULL, + /* 6b */ NULL, + /* 6c */ NULL, + /* 6d */ NULL, + /* 6e */ NULL, + /* 6f */ NULL, + /* 70 */ NULL, + /* 71 */ NULL, + /* 72 */ NULL, + /* 73 */ NULL, + /* 74 */ NULL, + /* 75 */ NULL, + /* 76 */ NULL, + /* 77 */ NULL, + /* 78 */ NULL, + /* 79 */ NULL, + /* 7a */ NULL, + /* 7b */ NULL, + /* 7c */ NULL, + /* 7d */ NULL, + /* 7e */ NULL, + /* 7f */ NULL, + /* 80 */ (const void *)&gRootTable_root_0f_38_80_modrmmod, + /* 81 */ (const void *)&gRootTable_root_0f_38_81_modrmmod, + /* 82 */ (const void *)&gRootTable_root_0f_38_82_modrmmod, + /* 83 */ NULL, + /* 84 */ NULL, + /* 85 */ NULL, + /* 86 */ NULL, + /* 87 */ NULL, + /* 88 */ NULL, + /* 89 */ NULL, + /* 8a */ NULL, + /* 8b */ NULL, + /* 8c */ NULL, + /* 8d */ NULL, + /* 8e */ NULL, + /* 8f */ NULL, + /* 90 */ NULL, + /* 91 */ NULL, + /* 92 */ NULL, + /* 93 */ NULL, + /* 94 */ NULL, + /* 95 */ NULL, + /* 96 */ NULL, + /* 97 */ NULL, + /* 98 */ NULL, + /* 99 */ NULL, + /* 9a */ NULL, + /* 9b */ NULL, + /* 9c */ NULL, + /* 9d */ NULL, + /* 9e */ NULL, + /* 9f */ NULL, + /* a0 */ NULL, + /* a1 */ NULL, + /* a2 */ NULL, + /* a3 */ NULL, + /* a4 */ NULL, + /* a5 */ NULL, + /* a6 */ NULL, + /* a7 */ NULL, + /* a8 */ NULL, + /* a9 */ NULL, + /* aa */ NULL, + /* ab */ NULL, + /* ac */ NULL, + /* ad */ NULL, + /* ae */ NULL, + /* af */ NULL, + /* b0 */ NULL, + /* b1 */ NULL, + /* b2 */ NULL, + /* b3 */ NULL, + /* b4 */ NULL, + /* b5 */ NULL, + /* b6 */ NULL, + /* b7 */ NULL, + /* b8 */ NULL, + /* b9 */ NULL, + /* ba */ NULL, + /* bb */ NULL, + /* bc */ NULL, + /* bd */ NULL, + /* be */ NULL, + /* bf */ NULL, + /* c0 */ NULL, + /* c1 */ NULL, + /* c2 */ NULL, + /* c3 */ NULL, + /* c4 */ NULL, + /* c5 */ NULL, + /* c6 */ NULL, + /* c7 */ NULL, + /* c8 */ (const void *)&gRootTable_root_0f_38_c8_mprefix, + /* c9 */ (const void *)&gRootTable_root_0f_38_c9_mprefix, + /* ca */ (const void *)&gRootTable_root_0f_38_ca_mprefix, + /* cb */ (const void *)&gRootTable_root_0f_38_cb_mprefix, + /* cc */ (const void *)&gRootTable_root_0f_38_cc_mprefix, + /* cd */ (const void *)&gRootTable_root_0f_38_cd_mprefix, + /* ce */ NULL, + /* cf */ (const void *)&gRootTable_root_0f_38_cf_mprefix, + /* d0 */ NULL, + /* d1 */ NULL, + /* d2 */ NULL, + /* d3 */ NULL, + /* d4 */ NULL, + /* d5 */ NULL, + /* d6 */ NULL, + /* d7 */ NULL, + /* d8 */ NULL, + /* d9 */ NULL, + /* da */ NULL, + /* db */ (const void *)&gRootTable_root_0f_38_db_mprefix, + /* dc */ (const void *)&gRootTable_root_0f_38_dc_mprefix, + /* dd */ (const void *)&gRootTable_root_0f_38_dd_mprefix, + /* de */ (const void *)&gRootTable_root_0f_38_de_mprefix, + /* df */ (const void *)&gRootTable_root_0f_38_df_mprefix, + /* e0 */ NULL, + /* e1 */ NULL, + /* e2 */ NULL, + /* e3 */ NULL, + /* e4 */ NULL, + /* e5 */ NULL, + /* e6 */ NULL, + /* e7 */ NULL, + /* e8 */ NULL, + /* e9 */ NULL, + /* ea */ NULL, + /* eb */ NULL, + /* ec */ NULL, + /* ed */ NULL, + /* ee */ NULL, + /* ef */ NULL, + /* f0 */ (const void *)&gRootTable_root_0f_38_f0_modrmmod, + /* f1 */ (const void *)&gRootTable_root_0f_38_f1_modrmmod, + /* f2 */ NULL, + /* f3 */ NULL, + /* f4 */ NULL, + /* f5 */ (const void *)&gRootTable_root_0f_38_f5_modrmmod, + /* f6 */ (const void *)&gRootTable_root_0f_38_f6_modrmmod, + /* f7 */ NULL, + /* f8 */ (const void *)&gRootTable_root_0f_38_f8_modrmmod, + /* f9 */ (const void *)&gRootTable_root_0f_38_f9_modrmmod, + /* fa */ NULL, + /* fb */ NULL, + /* fc */ NULL, + /* fd */ NULL, + /* fe */ NULL, + /* ff */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_58_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[25] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_58_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[26] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_58_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[27] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_58_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[28] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_58_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_58_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_58_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_58_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_58_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_d0_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[29] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_d0_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[30] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_d0_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_d0_66_leaf, + /* 02 */ NULL, + /* 03 */ (const void *)&gRootTable_root_0f_d0_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_df_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[37] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_df_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_df_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0d_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[62] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0d_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_0d_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0c_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[63] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0c_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_0c_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_41_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[218] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_41_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_41_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_40_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[219] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_40_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_40_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_17_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[229] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_17_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_17_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_cf_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[383] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_cf_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_cf_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_ce_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[384] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_ce_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_ce_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_21_mem_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[418] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_21_mem_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_21_mem_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_21_reg_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[419] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_21_reg_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_21_reg_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_21_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_3a_21_mem_mprefix, + /* 01 */ (const void *)&gRootTable_root_0f_3a_21_reg_mprefix, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_42_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[709] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_42_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_42_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0f_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[825] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0f_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[826] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0f_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_3a_0f_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_3a_0f_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0e_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[838] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0e_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_0e_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_44_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[839] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_44_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_44_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_61_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[847] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_61_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_61_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_60_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[848] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_60_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_60_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_63_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[856] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_63_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_63_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_62_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[857] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_62_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_62_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_14_mem_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[862] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_14_mem_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_14_mem_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_14_reg_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[863] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_14_reg_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_14_reg_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_14_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_3a_14_mem_mprefix, + /* 01 */ (const void *)&gRootTable_root_0f_3a_14_reg_mprefix, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_16_66_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[864] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_16_66_rexw_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[865] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_3a_16_66_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_0f_3a_16_66_None_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_3a_16_66_rexw_leaf, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_16_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_16_66_auxiliary, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_15_mem_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[868] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_15_mem_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_15_mem_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_15_reg_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[869] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_15_reg_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_15_reg_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_15_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_3a_15_mem_mprefix, + /* 01 */ (const void *)&gRootTable_root_0f_3a_15_reg_mprefix, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_20_mem_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[906] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_20_mem_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_20_mem_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_20_reg_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[907] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_20_reg_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_20_reg_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_20_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_3a_20_mem_mprefix, + /* 01 */ (const void *)&gRootTable_root_0f_3a_20_reg_mprefix, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_22_66_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[908] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_22_66_rexw_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[909] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_3a_22_66_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_0f_3a_22_66_None_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_3a_22_66_rexw_leaf, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_22_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_22_66_auxiliary, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_09_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1149] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_09_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_09_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_08_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1150] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_08_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_08_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0b_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1151] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0b_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_0b_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0a_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1152] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0a_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_0a_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_cc_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1217] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_cc_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_3a_cc_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_OPCODE gRootTable_root_0f_3a_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + /* 08 */ (const void *)&gRootTable_root_0f_3a_08_mprefix, + /* 09 */ (const void *)&gRootTable_root_0f_3a_09_mprefix, + /* 0a */ (const void *)&gRootTable_root_0f_3a_0a_mprefix, + /* 0b */ (const void *)&gRootTable_root_0f_3a_0b_mprefix, + /* 0c */ (const void *)&gRootTable_root_0f_3a_0c_mprefix, + /* 0d */ (const void *)&gRootTable_root_0f_3a_0d_mprefix, + /* 0e */ (const void *)&gRootTable_root_0f_3a_0e_mprefix, + /* 0f */ (const void *)&gRootTable_root_0f_3a_0f_mprefix, + /* 10 */ NULL, + /* 11 */ NULL, + /* 12 */ NULL, + /* 13 */ NULL, + /* 14 */ (const void *)&gRootTable_root_0f_3a_14_modrmmod, + /* 15 */ (const void *)&gRootTable_root_0f_3a_15_modrmmod, + /* 16 */ (const void *)&gRootTable_root_0f_3a_16_mprefix, + /* 17 */ (const void *)&gRootTable_root_0f_3a_17_mprefix, + /* 18 */ NULL, + /* 19 */ NULL, + /* 1a */ NULL, + /* 1b */ NULL, + /* 1c */ NULL, + /* 1d */ NULL, + /* 1e */ NULL, + /* 1f */ NULL, + /* 20 */ (const void *)&gRootTable_root_0f_3a_20_modrmmod, + /* 21 */ (const void *)&gRootTable_root_0f_3a_21_modrmmod, + /* 22 */ (const void *)&gRootTable_root_0f_3a_22_mprefix, + /* 23 */ NULL, + /* 24 */ NULL, + /* 25 */ NULL, + /* 26 */ NULL, + /* 27 */ NULL, + /* 28 */ NULL, + /* 29 */ NULL, + /* 2a */ NULL, + /* 2b */ NULL, + /* 2c */ NULL, + /* 2d */ NULL, + /* 2e */ NULL, + /* 2f */ NULL, + /* 30 */ NULL, + /* 31 */ NULL, + /* 32 */ NULL, + /* 33 */ NULL, + /* 34 */ NULL, + /* 35 */ NULL, + /* 36 */ NULL, + /* 37 */ NULL, + /* 38 */ NULL, + /* 39 */ NULL, + /* 3a */ NULL, + /* 3b */ NULL, + /* 3c */ NULL, + /* 3d */ NULL, + /* 3e */ NULL, + /* 3f */ NULL, + /* 40 */ (const void *)&gRootTable_root_0f_3a_40_mprefix, + /* 41 */ (const void *)&gRootTable_root_0f_3a_41_mprefix, + /* 42 */ (const void *)&gRootTable_root_0f_3a_42_mprefix, + /* 43 */ NULL, + /* 44 */ (const void *)&gRootTable_root_0f_3a_44_mprefix, + /* 45 */ NULL, + /* 46 */ NULL, + /* 47 */ NULL, + /* 48 */ NULL, + /* 49 */ NULL, + /* 4a */ NULL, + /* 4b */ NULL, + /* 4c */ NULL, + /* 4d */ NULL, + /* 4e */ NULL, + /* 4f */ NULL, + /* 50 */ NULL, + /* 51 */ NULL, + /* 52 */ NULL, + /* 53 */ NULL, + /* 54 */ NULL, + /* 55 */ NULL, + /* 56 */ NULL, + /* 57 */ NULL, + /* 58 */ NULL, + /* 59 */ NULL, + /* 5a */ NULL, + /* 5b */ NULL, + /* 5c */ NULL, + /* 5d */ NULL, + /* 5e */ NULL, + /* 5f */ NULL, + /* 60 */ (const void *)&gRootTable_root_0f_3a_60_mprefix, + /* 61 */ (const void *)&gRootTable_root_0f_3a_61_mprefix, + /* 62 */ (const void *)&gRootTable_root_0f_3a_62_mprefix, + /* 63 */ (const void *)&gRootTable_root_0f_3a_63_mprefix, + /* 64 */ NULL, + /* 65 */ NULL, + /* 66 */ NULL, + /* 67 */ NULL, + /* 68 */ NULL, + /* 69 */ NULL, + /* 6a */ NULL, + /* 6b */ NULL, + /* 6c */ NULL, + /* 6d */ NULL, + /* 6e */ NULL, + /* 6f */ NULL, + /* 70 */ NULL, + /* 71 */ NULL, + /* 72 */ NULL, + /* 73 */ NULL, + /* 74 */ NULL, + /* 75 */ NULL, + /* 76 */ NULL, + /* 77 */ NULL, + /* 78 */ NULL, + /* 79 */ NULL, + /* 7a */ NULL, + /* 7b */ NULL, + /* 7c */ NULL, + /* 7d */ NULL, + /* 7e */ NULL, + /* 7f */ NULL, + /* 80 */ NULL, + /* 81 */ NULL, + /* 82 */ NULL, + /* 83 */ NULL, + /* 84 */ NULL, + /* 85 */ NULL, + /* 86 */ NULL, + /* 87 */ NULL, + /* 88 */ NULL, + /* 89 */ NULL, + /* 8a */ NULL, + /* 8b */ NULL, + /* 8c */ NULL, + /* 8d */ NULL, + /* 8e */ NULL, + /* 8f */ NULL, + /* 90 */ NULL, + /* 91 */ NULL, + /* 92 */ NULL, + /* 93 */ NULL, + /* 94 */ NULL, + /* 95 */ NULL, + /* 96 */ NULL, + /* 97 */ NULL, + /* 98 */ NULL, + /* 99 */ NULL, + /* 9a */ NULL, + /* 9b */ NULL, + /* 9c */ NULL, + /* 9d */ NULL, + /* 9e */ NULL, + /* 9f */ NULL, + /* a0 */ NULL, + /* a1 */ NULL, + /* a2 */ NULL, + /* a3 */ NULL, + /* a4 */ NULL, + /* a5 */ NULL, + /* a6 */ NULL, + /* a7 */ NULL, + /* a8 */ NULL, + /* a9 */ NULL, + /* aa */ NULL, + /* ab */ NULL, + /* ac */ NULL, + /* ad */ NULL, + /* ae */ NULL, + /* af */ NULL, + /* b0 */ NULL, + /* b1 */ NULL, + /* b2 */ NULL, + /* b3 */ NULL, + /* b4 */ NULL, + /* b5 */ NULL, + /* b6 */ NULL, + /* b7 */ NULL, + /* b8 */ NULL, + /* b9 */ NULL, + /* ba */ NULL, + /* bb */ NULL, + /* bc */ NULL, + /* bd */ NULL, + /* be */ NULL, + /* bf */ NULL, + /* c0 */ NULL, + /* c1 */ NULL, + /* c2 */ NULL, + /* c3 */ NULL, + /* c4 */ NULL, + /* c5 */ NULL, + /* c6 */ NULL, + /* c7 */ NULL, + /* c8 */ NULL, + /* c9 */ NULL, + /* ca */ NULL, + /* cb */ NULL, + /* cc */ (const void *)&gRootTable_root_0f_3a_cc_mprefix, + /* cd */ NULL, + /* ce */ (const void *)&gRootTable_root_0f_3a_ce_mprefix, + /* cf */ (const void *)&gRootTable_root_0f_3a_cf_mprefix, + /* d0 */ NULL, + /* d1 */ NULL, + /* d2 */ NULL, + /* d3 */ NULL, + /* d4 */ NULL, + /* d5 */ NULL, + /* d6 */ NULL, + /* d7 */ NULL, + /* d8 */ NULL, + /* d9 */ NULL, + /* da */ NULL, + /* db */ NULL, + /* dc */ NULL, + /* dd */ NULL, + /* de */ NULL, + /* df */ (const void *)&gRootTable_root_0f_3a_df_mprefix, + /* e0 */ NULL, + /* e1 */ NULL, + /* e2 */ NULL, + /* e3 */ NULL, + /* e4 */ NULL, + /* e5 */ NULL, + /* e6 */ NULL, + /* e7 */ NULL, + /* e8 */ NULL, + /* e9 */ NULL, + /* ea */ NULL, + /* eb */ NULL, + /* ec */ NULL, + /* ed */ NULL, + /* ee */ NULL, + /* ef */ NULL, + /* f0 */ NULL, + /* f1 */ NULL, + /* f2 */ NULL, + /* f3 */ NULL, + /* f4 */ NULL, + /* f5 */ NULL, + /* f6 */ NULL, + /* f7 */ NULL, + /* f8 */ NULL, + /* f9 */ NULL, + /* fa */ NULL, + /* fb */ NULL, + /* fc */ NULL, + /* fd */ NULL, + /* fe */ NULL, + /* ff */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[38] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_55_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[50] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_55_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[51] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_55_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_55_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_55_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_54_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[52] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_54_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[53] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_54_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_54_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_54_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mem_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[71] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mem_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[73] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mem_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[74] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mem_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[76] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_1a_mem_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_1a_mem_None_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_1a_mem_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_1a_mem_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_1a_mem_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_reg_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[71] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_reg_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[73] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_reg_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[76] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_reg_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[738] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_1a_reg_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_1a_reg_None_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_1a_reg_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_1a_reg_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_1a_reg_F2_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_1a_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_1a_mem_mprefix, + /* 01 */ (const void *)&gRootTable_root_0f_1a_reg_mprefix, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mem_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[72] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mem_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[75] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mem_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[77] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mem_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[78] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_1b_mem_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_1b_mem_None_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_1b_mem_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_1b_mem_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_1b_mem_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_reg_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[72] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_reg_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[77] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_reg_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[739] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_reg_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[740] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_1b_reg_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_1b_reg_None_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_1b_reg_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_1b_reg_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_1b_reg_F2_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_1b_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_1b_mem_mprefix, + /* 01 */ (const void *)&gRootTable_root_0f_1b_reg_mprefix, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_bc_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[80] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_bc_aF3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1314] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_bc_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_0f_bc_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ (const void *)&gRootTable_root_0f_bc_aF3_leaf, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_bd_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[81] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_bd_aF3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[586] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_bd_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_0f_bd_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ (const void *)&gRootTable_root_0f_bd_aF3_leaf, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c8_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[82] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c9_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[83] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ca_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[84] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_cb_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[85] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_cc_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[86] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_cd_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[87] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ce_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[88] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_cf_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[89] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_a3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[90] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ba_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[91] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ba_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[92] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ba_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[95] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ba_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[97] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_0f_ba_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ (const void *)&gRootTable_root_0f_ba_04_leaf, + /* 05 */ (const void *)&gRootTable_root_0f_ba_05_leaf, + /* 06 */ (const void *)&gRootTable_root_0f_ba_06_leaf, + /* 07 */ (const void *)&gRootTable_root_0f_ba_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_bb_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[93] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_b3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[94] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ab_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[96] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[106] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_02_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[107] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_02_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_01_02_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_07_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[221] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_07_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_01_07_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_00_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[599] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_00_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_01_00_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_01_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[717] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_01_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_01_01_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_03_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1254] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_03_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_01_03_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_01_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_01_00_mprefix, + /* 01 */ (const void *)&gRootTable_root_0f_01_reg_01_01_mprefix, + /* 02 */ (const void *)&gRootTable_root_0f_01_reg_01_02_mprefix, + /* 03 */ (const void *)&gRootTable_root_0f_01_reg_01_03_mprefix, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ (const void *)&gRootTable_root_0f_01_reg_01_07_mprefix, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[115] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[431] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1242] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1257] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1736] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1737] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1748] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_03_01_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_03_01_None_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_01_reg_03_01_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_01_reg_03_01_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1747] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1853] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1854] +}; + +const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_03_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_03_00_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_01_reg_03_01_mprefix, + /* 02 */ (const void *)&gRootTable_root_0f_01_reg_03_02_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_01_reg_03_03_leaf, + /* 04 */ (const void *)&gRootTable_root_0f_01_reg_03_04_leaf, + /* 05 */ (const void *)&gRootTable_root_0f_01_reg_03_05_leaf, + /* 06 */ (const void *)&gRootTable_root_0f_01_reg_03_06_leaf, + /* 07 */ (const void *)&gRootTable_root_0f_01_reg_03_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[120] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_06_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[432] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_06_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1134] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_06_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1135] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_06_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_07_06_None_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_01_reg_07_06_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_01_reg_07_06_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_02_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[593] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_02_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[600] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_02_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_07_02_NP_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_01_reg_07_02_F3_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_03_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[718] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_03_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_07_03_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1021] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1097] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1312] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_07_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_07_07_None_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_01_reg_07_07_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_01_reg_07_07_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1120] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1129] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1288] +}; + +const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_07_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_07_00_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_01_reg_07_01_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_01_reg_07_02_mprefix, + /* 03 */ (const void *)&gRootTable_root_0f_01_reg_07_03_mprefix, + /* 04 */ (const void *)&gRootTable_root_0f_01_reg_07_04_leaf, + /* 05 */ (const void *)&gRootTable_root_0f_01_reg_07_05_leaf, + /* 06 */ (const void *)&gRootTable_root_0f_01_reg_07_06_mprefix, + /* 07 */ (const void *)&gRootTable_root_0f_01_reg_07_07_mprefix, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_07_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[222] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_07_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_07_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_04_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1735] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_04_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_04_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_05_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2520] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_05_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_05_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_00_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2521] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_00_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_00_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_01_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2548] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_01_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_01_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_06_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2553] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_06_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_06_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_02_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_00_mprefix, + /* 01 */ (const void *)&gRootTable_root_0f_01_reg_02_01_mprefix, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ (const void *)&gRootTable_root_0f_01_reg_02_04_mprefix, + /* 05 */ (const void *)&gRootTable_root_0f_01_reg_02_05_mprefix, + /* 06 */ (const void *)&gRootTable_root_0f_01_reg_02_06_mprefix, + /* 07 */ (const void *)&gRootTable_root_0f_01_reg_02_07_mprefix, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_00_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[223] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_00_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_00_00_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_05_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[859] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_05_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_00_05_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1733] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1746] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1852] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1864] +}; + +const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_00_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_00_00_mprefix, + /* 01 */ (const void *)&gRootTable_root_0f_01_reg_00_01_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_01_reg_00_02_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_01_reg_00_03_leaf, + /* 04 */ (const void *)&gRootTable_root_0f_01_reg_00_04_leaf, + /* 05 */ (const void *)&gRootTable_root_0f_01_reg_00_05_mprefix, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[566] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_06_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1118] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_06_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_05_06_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_02_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1175] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_02_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_01_reg_05_02_F3_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1194] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1210] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2552] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_00_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_05_00_NP_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_01_reg_05_00_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_01_reg_05_00_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_07_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2495] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_07_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_05_07_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_01_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2535] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_01_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ (const void *)&gRootTable_root_0f_01_reg_05_01_F2_leaf, + } +}; + +const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_05_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_05_00_mprefix, + /* 01 */ (const void *)&gRootTable_root_0f_01_reg_05_01_mprefix, + /* 02 */ (const void *)&gRootTable_root_0f_01_reg_05_02_mprefix, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ (const void *)&gRootTable_root_0f_01_reg_05_06_mprefix, + /* 07 */ (const void *)&gRootTable_root_0f_01_reg_05_07_mprefix, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1248] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_0f_01_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_00_modrmrm, + /* 01 */ (const void *)&gRootTable_root_0f_01_reg_01_modrmrm, + /* 02 */ (const void *)&gRootTable_root_0f_01_reg_02_modrmrm, + /* 03 */ (const void *)&gRootTable_root_0f_01_reg_03_modrmrm, + /* 04 */ (const void *)&gRootTable_root_0f_01_reg_04_leaf, + /* 05 */ (const void *)&gRootTable_root_0f_01_reg_05_modrmrm, + /* 06 */ (const void *)&gRootTable_root_0f_01_reg_06_leaf, + /* 07 */ (const void *)&gRootTable_root_0f_01_reg_07_modrmrm, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[430] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[561] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[563] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[566] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_05_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1158] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_01_mem_05_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_01_mem_05_F3_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1213] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1241] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1247] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_0f_01_mem_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_mem_00_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_01_mem_01_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_01_mem_02_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_01_mem_03_leaf, + /* 04 */ (const void *)&gRootTable_root_0f_01_mem_04_leaf, + /* 05 */ (const void *)&gRootTable_root_0f_01_mem_05_mprefix, + /* 06 */ (const void *)&gRootTable_root_0f_01_mem_06_leaf, + /* 07 */ (const void *)&gRootTable_root_0f_01_mem_07_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_mem_modrmreg, + /* 01 */ (const void *)&gRootTable_root_0f_01_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_mem_00_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[110] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_mem_00_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[741] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_mem_00_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[742] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_mem_00_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[743] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_1c_mem_00_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_1c_mem_00_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_1c_mem_00_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_1c_mem_00_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_1c_mem_00_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[745] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_mem_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[746] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_mem_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[747] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_mem_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[748] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_mem_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[749] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_mem_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[750] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_mem_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[751] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_0f_1c_mem_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_0f_1c_mem_00_mprefix, + /* 01 */ (const void *)&gRootTable_root_0f_1c_mem_01_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_1c_mem_02_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_1c_mem_03_leaf, + /* 04 */ (const void *)&gRootTable_root_0f_1c_mem_04_leaf, + /* 05 */ (const void *)&gRootTable_root_0f_1c_mem_05_leaf, + /* 06 */ (const void *)&gRootTable_root_0f_1c_mem_06_leaf, + /* 07 */ (const void *)&gRootTable_root_0f_1c_mem_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[744] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_reg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[745] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_reg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[746] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_reg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[747] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_reg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[748] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_reg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[749] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_reg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[750] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_reg_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[751] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_0f_1c_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_0f_1c_reg_00_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_1c_reg_01_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_1c_reg_02_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_1c_reg_03_leaf, + /* 04 */ (const void *)&gRootTable_root_0f_1c_reg_04_leaf, + /* 05 */ (const void *)&gRootTable_root_0f_1c_reg_05_leaf, + /* 06 */ (const void *)&gRootTable_root_0f_1c_reg_06_leaf, + /* 07 */ (const void *)&gRootTable_root_0f_1c_reg_07_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_1c_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_1c_mem_modrmreg, + /* 01 */ (const void *)&gRootTable_root_0f_1c_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_07_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[113] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_07_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[114] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_07_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_07_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_ae_mem_07_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[117] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[119] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_NP_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2544] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_NP_rexw_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2545] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_06_NP_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_06_NP_None_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_ae_mem_06_NP_rexw_leaf, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_06_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_06_NP_auxiliary, + /* 01 */ (const void *)&gRootTable_root_0f_ae_mem_06_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_ae_mem_06_F3_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_01_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[377] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_01_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_01_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_00_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[378] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_00_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_00_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_02_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[553] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_02_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_02_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1061] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_NP_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2540] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_NP_rexw_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2541] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_04_NP_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_04_NP_None_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_ae_mem_04_NP_rexw_leaf, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_04_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_04_NP_auxiliary, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_ae_mem_04_F3_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_03_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1259] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_03_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_03_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_05_NP_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2536] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_05_NP_rexw_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2537] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_05_NP_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_05_NP_None_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_ae_mem_05_NP_rexw_leaf, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_05_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_05_NP_auxiliary, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_REG gRootTable_root_0f_ae_mem_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_00_mprefix, + /* 01 */ (const void *)&gRootTable_root_0f_ae_mem_01_mprefix, + /* 02 */ (const void *)&gRootTable_root_0f_ae_mem_02_mprefix, + /* 03 */ (const void *)&gRootTable_root_0f_ae_mem_03_mprefix, + /* 04 */ (const void *)&gRootTable_root_0f_ae_mem_04_mprefix, + /* 05 */ (const void *)&gRootTable_root_0f_ae_mem_05_mprefix, + /* 06 */ (const void *)&gRootTable_root_0f_ae_mem_06_mprefix, + /* 07 */ (const void *)&gRootTable_root_0f_ae_mem_07_mprefix, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_05_F3_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[412] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_05_F3_rexw_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[413] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_05_F3_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_0f_ae_reg_05_F3_None_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_ae_reg_05_F3_rexw_leaf, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_05_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[559] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_05_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_ae_reg_05_NP_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_ae_reg_05_F3_auxiliary, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[594] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1313] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1321] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1322] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_06_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_ae_reg_06_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_ae_reg_06_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_ae_reg_06_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_ae_reg_06_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_07_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[858] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_07_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1212] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_07_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_ae_reg_07_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_ae_reg_07_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_04_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1061] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_04_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_ae_reg_04_F3_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_00_F3_64_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1114] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_00_F3_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ (const void *)&gRootTable_root_0f_ae_reg_00_F3_64_leaf, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_00_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_ae_reg_00_F3_auxiliary, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_01_F3_64_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1115] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_01_F3_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ (const void *)&gRootTable_root_0f_ae_reg_01_F3_64_leaf, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_01_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_ae_reg_01_F3_auxiliary, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_02_F3_64_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2492] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_02_F3_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ (const void *)&gRootTable_root_0f_ae_reg_02_F3_64_leaf, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_02_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_ae_reg_02_F3_auxiliary, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_03_F3_64_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2493] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_03_F3_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ (const void *)&gRootTable_root_0f_ae_reg_03_F3_64_leaf, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_03_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_ae_reg_03_F3_auxiliary, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_REG gRootTable_root_0f_ae_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_0f_ae_reg_00_mprefix, + /* 01 */ (const void *)&gRootTable_root_0f_ae_reg_01_mprefix, + /* 02 */ (const void *)&gRootTable_root_0f_ae_reg_02_mprefix, + /* 03 */ (const void *)&gRootTable_root_0f_ae_reg_03_mprefix, + /* 04 */ (const void *)&gRootTable_root_0f_ae_reg_04_mprefix, + /* 05 */ (const void *)&gRootTable_root_0f_ae_reg_05_mprefix, + /* 06 */ (const void *)&gRootTable_root_0f_ae_reg_06_mprefix, + /* 07 */ (const void *)&gRootTable_root_0f_ae_reg_07_mprefix, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_ae_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_modrmreg, + /* 01 */ (const void *)&gRootTable_root_0f_ae_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[118] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_46_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[122] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_42_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[123] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_4c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[124] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_4e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[125] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_47_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[126] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_43_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[127] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_4d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[128] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_4f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[129] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_41_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[130] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_4b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[131] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_49_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[132] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_45_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[133] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_40_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[134] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_4a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[135] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_48_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[136] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_44_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[137] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c2_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[148] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c2_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[149] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c2_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[152] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c2_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[157] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_c2_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_c2_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_c2_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_c2_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_c2_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_b0_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[160] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_b1_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[161] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_01_rexw_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[162] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_01_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[163] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_01_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_0f_c7_mem_01_None_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_c7_mem_01_rexw_leaf, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1734] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1849] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1865] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_06_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_c7_mem_06_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_c7_mem_06_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_c7_mem_06_F3_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_07_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1850] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_07_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_c7_mem_07_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_03_NP_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2538] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_03_NP_rexw_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2539] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_03_NP_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_0f_c7_mem_03_NP_None_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_c7_mem_03_NP_rexw_leaf, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_03_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_c7_mem_03_NP_auxiliary, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_04_NP_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2542] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_04_NP_rexw_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2543] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_04_NP_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_0f_c7_mem_04_NP_None_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_c7_mem_04_NP_rexw_leaf, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_04_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_c7_mem_04_NP_auxiliary, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_05_NP_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2546] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_05_NP_rexw_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2547] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_05_NP_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_0f_c7_mem_05_NP_None_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_c7_mem_05_NP_rexw_leaf, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_05_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_c7_mem_05_NP_auxiliary, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_REG gRootTable_root_0f_c7_mem_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_c7_mem_01_auxiliary, + /* 02 */ NULL, + /* 03 */ (const void *)&gRootTable_root_0f_c7_mem_03_mprefix, + /* 04 */ (const void *)&gRootTable_root_0f_c7_mem_04_mprefix, + /* 05 */ (const void *)&gRootTable_root_0f_c7_mem_05_mprefix, + /* 06 */ (const void *)&gRootTable_root_0f_c7_mem_06_mprefix, + /* 07 */ (const void *)&gRootTable_root_0f_c7_mem_07_mprefix, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_07_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1117] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_07_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1123] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_07_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1124] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_c7_reg_07_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_c7_reg_07_None_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_c7_reg_07_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_c7_reg_07_F3_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_06_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1121] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_06_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1122] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_c7_reg_06_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_c7_reg_06_None_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_c7_reg_06_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_REG gRootTable_root_0f_c7_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ (const void *)&gRootTable_root_0f_c7_reg_06_mprefix, + /* 07 */ (const void *)&gRootTable_root_0f_c7_reg_07_mprefix, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_c7_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_c7_mem_modrmreg, + /* 01 */ (const void *)&gRootTable_root_0f_c7_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_2f_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[164] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_2f_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[165] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_2f_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_2f_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_2f_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_a2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[166] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[167] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[168] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_e6_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[174] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_e6_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[176] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_e6_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[190] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_e6_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_e6_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_e6_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_e6_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_5b_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[175] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_5b_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[181] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_5b_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[192] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_5b_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_5b_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_5b_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_5b_F3_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_2d_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[177] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_2d_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[183] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_2d_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[184] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_2d_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[189] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_2d_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_2d_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_2d_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_2d_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_2d_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_5a_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[178] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_5a_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[182] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_5a_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[185] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_5a_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[188] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_5a_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_5a_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_5a_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_5a_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_5a_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_2a_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[179] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_2a_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[180] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_2a_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[186] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_2a_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[187] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_2a_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_2a_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_2a_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_2a_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_2a_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_2c_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[191] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_2c_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[193] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_2c_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[194] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_2c_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[195] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_2c_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_2c_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_2c_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_2c_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_2c_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_5e_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[213] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_5e_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[214] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_5e_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[215] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_5e_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[216] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_5e_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_5e_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_5e_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_5e_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_5e_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_39_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[217] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_77_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[220] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_77_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_77_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_reg_07_03_aF3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[224] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_reg_07_03_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[765] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_reg_07_03_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_0f_1e_reg_07_03_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ (const void *)&gRootTable_root_0f_1e_reg_07_03_aF3_leaf, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_reg_07_02_aF3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[225] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_reg_07_02_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[764] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_reg_07_02_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_0f_1e_reg_07_02_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ (const void *)&gRootTable_root_0f_1e_reg_07_02_aF3_leaf, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_reg_07_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[762] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_reg_07_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[763] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_reg_07_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[766] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_reg_07_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[767] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_reg_07_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[768] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_reg_07_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[769] +}; + +const ND_TABLE_MODRM_RM gRootTable_root_0f_1e_reg_07_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gRootTable_root_0f_1e_reg_07_00_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_1e_reg_07_01_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_1e_reg_07_02_auxiliary, + /* 03 */ (const void *)&gRootTable_root_0f_1e_reg_07_03_auxiliary, + /* 04 */ (const void *)&gRootTable_root_0f_1e_reg_07_04_leaf, + /* 05 */ (const void *)&gRootTable_root_0f_1e_reg_07_05_leaf, + /* 06 */ (const void *)&gRootTable_root_0f_1e_reg_07_06_leaf, + /* 07 */ (const void *)&gRootTable_root_0f_1e_reg_07_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[754] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_reg_01_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[755] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_reg_01_rexw_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[756] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_reg_01_rexw_aF3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1127] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_reg_01_rexw_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_0f_1e_reg_01_rexw_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ (const void *)&gRootTable_root_0f_1e_reg_01_rexw_aF3_leaf, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_reg_01_aF3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1126] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_reg_01_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_0f_1e_reg_01_None_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_1e_reg_01_rexw_auxiliary, + /* 03 */ NULL, + /* 04 */ (const void *)&gRootTable_root_0f_1e_reg_01_aF3_leaf, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_reg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[757] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_reg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[758] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_reg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[759] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_reg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[760] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_reg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[761] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_0f_1e_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_0f_1e_reg_00_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_1e_reg_01_auxiliary, + /* 02 */ (const void *)&gRootTable_root_0f_1e_reg_02_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_1e_reg_03_leaf, + /* 04 */ (const void *)&gRootTable_root_0f_1e_reg_04_leaf, + /* 05 */ (const void *)&gRootTable_root_0f_1e_reg_05_leaf, + /* 06 */ (const void *)&gRootTable_root_0f_1e_reg_06_leaf, + /* 07 */ (const void *)&gRootTable_root_0f_1e_reg_07_modrmrm, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_mem_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[753] +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_1e_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_1e_mem_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_1e_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_None_66_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[230] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_0f_78_None_66_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_0f_78_None_66_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_None_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[420] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_None_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1851] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_78_None_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_78_None_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_78_None_66_modrmreg, + /* 02 */ NULL, + /* 03 */ (const void *)&gRootTable_root_0f_78_None_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_cyrix_mem_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1285] +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_78_cyrix_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_78_cyrix_mem_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VENDOR gRootTable_root_0f_78_vendor = +{ + ND_ILUT_VENDOR, + { + /* 00 */ (const void *)&gRootTable_root_0f_78_None_mprefix, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ (const void *)&gRootTable_root_0f_78_cyrix_modrmmod, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_reg_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[231] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_reg_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[421] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_reg_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1863] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_reg_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_79_None_reg_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_79_None_reg_66_leaf, + /* 02 */ NULL, + /* 03 */ (const void *)&gRootTable_root_0f_79_None_reg_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_mem_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1863] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_mem_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_79_None_mem_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_79_None_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_79_None_mem_mprefix, + /* 01 */ (const void *)&gRootTable_root_0f_79_None_reg_mprefix, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_cyrix_mem_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1153] +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_79_cyrix_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_79_cyrix_mem_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VENDOR gRootTable_root_0f_79_vendor = +{ + ND_ILUT_VENDOR, + { + /* 00 */ (const void *)&gRootTable_root_0f_79_None_modrmmod, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ (const void *)&gRootTable_root_0f_79_cyrix_modrmmod, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[274] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_37_None_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[382] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_37_None_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_37_None_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_37_cyrix_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2496] +}; + +const ND_TABLE_VENDOR gRootTable_root_0f_37_vendor = +{ + ND_ILUT_VENDOR, + { + /* 00 */ (const void *)&gRootTable_root_0f_37_None_mprefix, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ (const void *)&gRootTable_root_0f_37_cyrix_leaf, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_7c_None_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[386] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_7c_None_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[387] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_7c_None_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_7c_None_66_leaf, + /* 02 */ NULL, + /* 03 */ (const void *)&gRootTable_root_0f_7c_None_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_7c_cyrix_mem_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1287] +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_7c_cyrix_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_7c_cyrix_mem_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VENDOR gRootTable_root_0f_7c_vendor = +{ + ND_ILUT_VENDOR, + { + /* 00 */ (const void *)&gRootTable_root_0f_7c_None_mprefix, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ (const void *)&gRootTable_root_0f_7c_cyrix_modrmmod, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_7d_None_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[389] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_7d_None_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[390] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_7d_None_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_7d_None_66_leaf, + /* 02 */ NULL, + /* 03 */ (const void *)&gRootTable_root_0f_7d_None_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_7d_cyrix_mem_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1159] +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_7d_cyrix_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_7d_cyrix_mem_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VENDOR gRootTable_root_0f_7d_vendor = +{ + ND_ILUT_VENDOR, + { + /* 00 */ (const void *)&gRootTable_root_0f_7d_None_mprefix, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ (const void *)&gRootTable_root_0f_7d_cyrix_modrmmod, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_af_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[393] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[428] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_86_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[438] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_82_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[440] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_8c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[444] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_8e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[446] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[451] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[564] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[583] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1243] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1268] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1478] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1479] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_0f_00_mem_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_0f_00_mem_00_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_00_mem_01_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_00_mem_02_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_00_mem_03_leaf, + /* 04 */ (const void *)&gRootTable_root_0f_00_mem_04_leaf, + /* 05 */ (const void *)&gRootTable_root_0f_00_mem_05_leaf, + /* 06 */ (const void *)&gRootTable_root_0f_00_mem_06_leaf, + /* 07 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[451] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[564] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[583] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1244] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1269] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1478] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1479] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_0f_00_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_0f_00_reg_00_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_00_reg_01_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_00_reg_02_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_00_reg_03_leaf, + /* 04 */ (const void *)&gRootTable_root_0f_00_reg_04_leaf, + /* 05 */ (const void *)&gRootTable_root_0f_00_reg_05_leaf, + /* 06 */ (const void *)&gRootTable_root_0f_00_reg_06_leaf, + /* 07 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_00_mem_modrmreg, + /* 01 */ (const void *)&gRootTable_root_0f_00_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_b8_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[452] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_b8_aF3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[976] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_b8_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_0f_b8_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ (const void *)&gRootTable_root_0f_b8_aF3_leaf, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_87_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[455] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_83_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[457] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_8d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[459] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_8f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[461] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_81_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[463] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_8b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[465] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_89_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[467] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_85_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[469] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_80_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[471] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_8a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[473] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_88_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[476] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_84_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[478] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_02_mem_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[550] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_02_reg_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[551] +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_02_mem_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_02_reg_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_f0_mem_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[552] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_f0_mem_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ (const void *)&gRootTable_root_0f_f0_mem_F2_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_f0_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_f0_mem_mprefix, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_b4_mem_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[560] +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_b4_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_b4_mem_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_b5_mem_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[562] +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_b5_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_b5_mem_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_05_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[567] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_05_64_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1289] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_05_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_0f_05_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ (const void *)&gRootTable_root_0f_05_64_leaf, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_07_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[568] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_07_64_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1292] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_07_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_0f_07_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ (const void *)&gRootTable_root_0f_07_64_leaf, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_03_mem_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[580] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_03_reg_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[581] +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_03_mem_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_03_reg_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_b2_mem_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[582] +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_b2_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_b2_mem_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_f7_reg_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[587] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_f7_reg_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[588] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_f7_reg_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_f7_reg_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_f7_reg_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_f7_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_f7_reg_mprefix, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_5f_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[589] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_5f_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[590] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_5f_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[591] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_5f_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[592] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_5f_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_5f_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_5f_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_5f_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_5f_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_5d_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[595] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_5d_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[596] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_5d_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[597] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_5d_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[598] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_5d_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_5d_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_5d_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_5d_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_5d_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_a6_reg_00_00_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[601] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_00_00_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_a6_reg_00_00_F3_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_RM gRootTable_root_0f_a6_reg_00_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gRootTable_root_0f_a6_reg_00_00_mprefix, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_a6_reg_01_00_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2549] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_01_00_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_a6_reg_01_00_F3_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_RM gRootTable_root_0f_a6_reg_01_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gRootTable_root_0f_a6_reg_01_00_mprefix, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_a6_reg_02_00_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2550] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_02_00_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_a6_reg_02_00_F3_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_RM gRootTable_root_0f_a6_reg_02_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gRootTable_root_0f_a6_reg_02_00_mprefix, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_MODRM_REG gRootTable_root_0f_a6_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_0f_a6_reg_00_modrmrm, + /* 01 */ (const void *)&gRootTable_root_0f_a6_reg_01_modrmrm, + /* 02 */ (const void *)&gRootTable_root_0f_a6_reg_02_modrmrm, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_a6_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_a6_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_20_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[602] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_21_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[603] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_22_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[604] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_23_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[605] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_24_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[606] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_26_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[607] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_28_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[638] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_28_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[640] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_28_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_28_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_28_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_29_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[639] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_29_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[641] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_29_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_29_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_29_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_6e_NP_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[646] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_6e_NP_rexw_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[677] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_6e_NP_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_0f_6e_NP_None_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_6e_NP_rexw_leaf, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_6e_66_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[647] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_6e_66_rexw_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[678] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_6e_66_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_0f_6e_66_None_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_6e_66_rexw_leaf, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_6e_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_6e_NP_auxiliary, + /* 01 */ (const void *)&gRootTable_root_0f_6e_66_auxiliary, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_NP_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[648] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_NP_rexw_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[680] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_7e_None_NP_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_0f_7e_None_NP_None_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_7e_None_NP_rexw_leaf, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_66_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[649] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_66_rexw_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[681] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_7e_None_66_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_0f_7e_None_66_None_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_7e_None_66_rexw_leaf, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[682] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_7e_None_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_7e_None_NP_auxiliary, + /* 01 */ (const void *)&gRootTable_root_0f_7e_None_66_auxiliary, + /* 02 */ (const void *)&gRootTable_root_0f_7e_None_F3_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_cyrix_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1246] +}; + +const ND_TABLE_VENDOR gRootTable_root_0f_7e_vendor = +{ + ND_ILUT_VENDOR, + { + /* 00 */ (const void *)&gRootTable_root_0f_7e_None_mprefix, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ (const void *)&gRootTable_root_0f_7e_cyrix_leaf, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[650] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[663] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[665] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[693] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_12_mem_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_12_mem_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_12_mem_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_12_mem_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_12_mem_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_reg_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[650] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_reg_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[665] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_reg_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[693] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_12_reg_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_12_reg_NP_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_12_reg_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_12_reg_F2_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_12_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_12_mem_mprefix, + /* 01 */ (const void *)&gRootTable_root_0f_12_reg_mprefix, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_d6_reg_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[653] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_d6_reg_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[684] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_d6_reg_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[685] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_d6_reg_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_d6_reg_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_d6_reg_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_d6_reg_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_d6_mem_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[684] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_d6_mem_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_d6_mem_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_d6_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_d6_mem_mprefix, + /* 01 */ (const void *)&gRootTable_root_0f_d6_reg_mprefix, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_6f_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[654] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_6f_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[656] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_6f_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[679] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_6f_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_6f_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_6f_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_6f_F3_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_7f_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[655] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_7f_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[657] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_7f_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[683] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_7f_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_7f_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_7f_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_7f_F3_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_mem_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[658] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_mem_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[660] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_mem_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[692] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_16_mem_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_16_mem_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_16_mem_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_16_mem_F3_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_reg_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[662] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_reg_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[692] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_16_reg_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_16_reg_NP_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_16_reg_F3_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_16_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_16_mem_mprefix, + /* 01 */ (const void *)&gRootTable_root_0f_16_reg_mprefix, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_17_mem_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[659] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_17_mem_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[661] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_17_mem_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_17_mem_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_17_mem_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_17_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_17_mem_mprefix, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_13_mem_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[664] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_13_mem_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[666] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_13_mem_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_13_mem_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_13_mem_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_13_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_13_mem_mprefix, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_50_reg_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[667] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_50_reg_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[668] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_50_reg_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_50_reg_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_50_reg_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_50_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_50_reg_mprefix, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_e7_mem_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[669] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_e7_mem_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[674] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_e7_mem_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_e7_mem_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_e7_mem_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_e7_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_e7_mem_mprefix, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c3_mem_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[671] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_c3_mem_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_c3_mem_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_c3_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_c3_mem_mprefix, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_2b_mem_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[672] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_2b_mem_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[673] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_2b_mem_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[675] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_2b_mem_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[676] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_2b_mem_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_2b_mem_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_2b_mem_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_2b_mem_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_2b_mem_F2_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_2b_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_2b_mem_mprefix, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_10_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[688] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_10_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[696] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_10_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[703] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_10_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[705] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_10_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_10_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_10_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_10_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_10_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_11_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[689] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_11_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[697] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_11_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[704] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_11_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[706] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_11_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_11_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_11_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_11_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_11_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_be_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[700] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_bf_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[701] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_b6_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[707] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_b7_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[708] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_59_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[712] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_59_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[713] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_59_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[714] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_59_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[715] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_59_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_59_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_59_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_59_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_59_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[721] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[722] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[723] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[724] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[725] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[726] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[727] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[728] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_0f_0d_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_0f_0d_reg_00_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_0d_reg_01_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_0d_reg_02_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_0d_reg_03_leaf, + /* 04 */ (const void *)&gRootTable_root_0f_0d_reg_04_leaf, + /* 05 */ (const void *)&gRootTable_root_0f_0d_reg_05_leaf, + /* 06 */ (const void *)&gRootTable_root_0f_0d_reg_06_leaf, + /* 07 */ (const void *)&gRootTable_root_0f_0d_reg_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[982] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[983] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[984] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[985] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[986] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[987] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[992] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[993] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_0f_0d_mem_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_0f_0d_mem_00_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_0d_mem_01_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_0d_mem_02_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_0d_mem_03_leaf, + /* 04 */ (const void *)&gRootTable_root_0f_0d_mem_04_leaf, + /* 05 */ (const void *)&gRootTable_root_0f_0d_mem_05_leaf, + /* 06 */ (const void *)&gRootTable_root_0f_0d_mem_06_leaf, + /* 07 */ (const void *)&gRootTable_root_0f_0d_mem_07_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_0d_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_0d_mem_modrmreg, + /* 01 */ (const void *)&gRootTable_root_0f_0d_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[729] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[730] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[731] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[732] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[733] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[734] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[735] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[736] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_0f_18_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_0f_18_reg_00_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_18_reg_01_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_18_reg_02_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_18_reg_03_leaf, + /* 04 */ (const void *)&gRootTable_root_0f_18_reg_04_leaf, + /* 05 */ (const void *)&gRootTable_root_0f_18_reg_05_leaf, + /* 06 */ (const void *)&gRootTable_root_0f_18_reg_06_leaf, + /* 07 */ (const void *)&gRootTable_root_0f_18_reg_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[733] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[734] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[735] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[736] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[988] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[989] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[990] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[991] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_0f_18_mem_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_0f_18_mem_00_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_18_mem_01_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_18_mem_02_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_18_mem_03_leaf, + /* 04 */ (const void *)&gRootTable_root_0f_18_mem_04_leaf, + /* 05 */ (const void *)&gRootTable_root_0f_18_mem_05_leaf, + /* 06 */ (const void *)&gRootTable_root_0f_18_mem_06_leaf, + /* 07 */ (const void *)&gRootTable_root_0f_18_mem_07_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_18_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_18_mem_modrmreg, + /* 01 */ (const void *)&gRootTable_root_0f_18_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_19_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[737] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[752] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_1f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[770] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_56_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[784] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_56_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[785] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_56_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_56_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_56_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_6b_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[802] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_6b_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[803] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_6b_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_6b_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_6b_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_63_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[804] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_63_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[805] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_63_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_63_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_63_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_67_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[807] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_67_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[808] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_67_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_67_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_67_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_fc_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[809] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_fc_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[810] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_fc_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_fc_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_fc_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_fe_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[811] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_fe_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[812] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_fe_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_fe_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_fe_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_d4_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[813] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_d4_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[814] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_d4_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_d4_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_d4_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ec_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[815] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ec_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[816] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_ec_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_ec_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_ec_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ed_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[817] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ed_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[818] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_ed_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_ed_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_ed_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_dc_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[819] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_dc_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[820] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_dc_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_dc_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_dc_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_dd_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[821] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_dd_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[822] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_dd_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_dd_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_dd_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_fd_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[823] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_fd_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[824] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_fd_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_fd_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_fd_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_db_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[827] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_db_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[828] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_db_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_db_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_db_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_df_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[829] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_df_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[830] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_df_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_df_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_df_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_e0_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[832] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_e0_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[833] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_e0_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_e0_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_e0_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_bf_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[834] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_1d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[870] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_1c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[871] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_ae_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[872] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_9e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[873] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b0_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[874] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_90_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[875] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_a0_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[876] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_a4_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[877] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_94_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[878] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_96_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[879] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b4_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[880] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_8a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[881] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_8e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[882] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_a6_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[883] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b6_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[884] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_86_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[885] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_a7_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[886] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_97_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[887] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_87_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[888] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_9a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[889] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_aa_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[890] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_0d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[904] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_0c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[905] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b7_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[951] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_bb_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1059] +}; + +const ND_TABLE_OPCODE gRootTable_root_0f_0f_opcode_3dnow = +{ + ND_ILUT_OPCODE_3DNOW, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + /* 08 */ NULL, + /* 09 */ NULL, + /* 0a */ NULL, + /* 0b */ NULL, + /* 0c */ (const void *)&gRootTable_root_0f_0f_0c_leaf, + /* 0d */ (const void *)&gRootTable_root_0f_0f_0d_leaf, + /* 0e */ NULL, + /* 0f */ NULL, + /* 10 */ NULL, + /* 11 */ NULL, + /* 12 */ NULL, + /* 13 */ NULL, + /* 14 */ NULL, + /* 15 */ NULL, + /* 16 */ NULL, + /* 17 */ NULL, + /* 18 */ NULL, + /* 19 */ NULL, + /* 1a */ NULL, + /* 1b */ NULL, + /* 1c */ (const void *)&gRootTable_root_0f_0f_1c_leaf, + /* 1d */ (const void *)&gRootTable_root_0f_0f_1d_leaf, + /* 1e */ NULL, + /* 1f */ NULL, + /* 20 */ NULL, + /* 21 */ NULL, + /* 22 */ NULL, + /* 23 */ NULL, + /* 24 */ NULL, + /* 25 */ NULL, + /* 26 */ NULL, + /* 27 */ NULL, + /* 28 */ NULL, + /* 29 */ NULL, + /* 2a */ NULL, + /* 2b */ NULL, + /* 2c */ NULL, + /* 2d */ NULL, + /* 2e */ NULL, + /* 2f */ NULL, + /* 30 */ NULL, + /* 31 */ NULL, + /* 32 */ NULL, + /* 33 */ NULL, + /* 34 */ NULL, + /* 35 */ NULL, + /* 36 */ NULL, + /* 37 */ NULL, + /* 38 */ NULL, + /* 39 */ NULL, + /* 3a */ NULL, + /* 3b */ NULL, + /* 3c */ NULL, + /* 3d */ NULL, + /* 3e */ NULL, + /* 3f */ NULL, + /* 40 */ NULL, + /* 41 */ NULL, + /* 42 */ NULL, + /* 43 */ NULL, + /* 44 */ NULL, + /* 45 */ NULL, + /* 46 */ NULL, + /* 47 */ NULL, + /* 48 */ NULL, + /* 49 */ NULL, + /* 4a */ NULL, + /* 4b */ NULL, + /* 4c */ NULL, + /* 4d */ NULL, + /* 4e */ NULL, + /* 4f */ NULL, + /* 50 */ NULL, + /* 51 */ NULL, + /* 52 */ NULL, + /* 53 */ NULL, + /* 54 */ NULL, + /* 55 */ NULL, + /* 56 */ NULL, + /* 57 */ NULL, + /* 58 */ NULL, + /* 59 */ NULL, + /* 5a */ NULL, + /* 5b */ NULL, + /* 5c */ NULL, + /* 5d */ NULL, + /* 5e */ NULL, + /* 5f */ NULL, + /* 60 */ NULL, + /* 61 */ NULL, + /* 62 */ NULL, + /* 63 */ NULL, + /* 64 */ NULL, + /* 65 */ NULL, + /* 66 */ NULL, + /* 67 */ NULL, + /* 68 */ NULL, + /* 69 */ NULL, + /* 6a */ NULL, + /* 6b */ NULL, + /* 6c */ NULL, + /* 6d */ NULL, + /* 6e */ NULL, + /* 6f */ NULL, + /* 70 */ NULL, + /* 71 */ NULL, + /* 72 */ NULL, + /* 73 */ NULL, + /* 74 */ NULL, + /* 75 */ NULL, + /* 76 */ NULL, + /* 77 */ NULL, + /* 78 */ NULL, + /* 79 */ NULL, + /* 7a */ NULL, + /* 7b */ NULL, + /* 7c */ NULL, + /* 7d */ NULL, + /* 7e */ NULL, + /* 7f */ NULL, + /* 80 */ NULL, + /* 81 */ NULL, + /* 82 */ NULL, + /* 83 */ NULL, + /* 84 */ NULL, + /* 85 */ NULL, + /* 86 */ (const void *)&gRootTable_root_0f_0f_86_leaf, + /* 87 */ (const void *)&gRootTable_root_0f_0f_87_leaf, + /* 88 */ NULL, + /* 89 */ NULL, + /* 8a */ (const void *)&gRootTable_root_0f_0f_8a_leaf, + /* 8b */ NULL, + /* 8c */ NULL, + /* 8d */ NULL, + /* 8e */ (const void *)&gRootTable_root_0f_0f_8e_leaf, + /* 8f */ NULL, + /* 90 */ (const void *)&gRootTable_root_0f_0f_90_leaf, + /* 91 */ NULL, + /* 92 */ NULL, + /* 93 */ NULL, + /* 94 */ (const void *)&gRootTable_root_0f_0f_94_leaf, + /* 95 */ NULL, + /* 96 */ (const void *)&gRootTable_root_0f_0f_96_leaf, + /* 97 */ (const void *)&gRootTable_root_0f_0f_97_leaf, + /* 98 */ NULL, + /* 99 */ NULL, + /* 9a */ (const void *)&gRootTable_root_0f_0f_9a_leaf, + /* 9b */ NULL, + /* 9c */ NULL, + /* 9d */ NULL, + /* 9e */ (const void *)&gRootTable_root_0f_0f_9e_leaf, + /* 9f */ NULL, + /* a0 */ (const void *)&gRootTable_root_0f_0f_a0_leaf, + /* a1 */ NULL, + /* a2 */ NULL, + /* a3 */ NULL, + /* a4 */ (const void *)&gRootTable_root_0f_0f_a4_leaf, + /* a5 */ NULL, + /* a6 */ (const void *)&gRootTable_root_0f_0f_a6_leaf, + /* a7 */ (const void *)&gRootTable_root_0f_0f_a7_leaf, + /* a8 */ NULL, + /* a9 */ NULL, + /* aa */ (const void *)&gRootTable_root_0f_0f_aa_leaf, + /* ab */ NULL, + /* ac */ NULL, + /* ad */ NULL, + /* ae */ (const void *)&gRootTable_root_0f_0f_ae_leaf, + /* af */ NULL, + /* b0 */ (const void *)&gRootTable_root_0f_0f_b0_leaf, + /* b1 */ NULL, + /* b2 */ NULL, + /* b3 */ NULL, + /* b4 */ (const void *)&gRootTable_root_0f_0f_b4_leaf, + /* b5 */ NULL, + /* b6 */ (const void *)&gRootTable_root_0f_0f_b6_leaf, + /* b7 */ (const void *)&gRootTable_root_0f_0f_b7_leaf, + /* b8 */ NULL, + /* b9 */ NULL, + /* ba */ NULL, + /* bb */ (const void *)&gRootTable_root_0f_0f_bb_leaf, + /* bc */ NULL, + /* bd */ NULL, + /* be */ NULL, + /* bf */ (const void *)&gRootTable_root_0f_0f_bf_leaf, + /* c0 */ NULL, + /* c1 */ NULL, + /* c2 */ NULL, + /* c3 */ NULL, + /* c4 */ NULL, + /* c5 */ NULL, + /* c6 */ NULL, + /* c7 */ NULL, + /* c8 */ NULL, + /* c9 */ NULL, + /* ca */ NULL, + /* cb */ NULL, + /* cc */ NULL, + /* cd */ NULL, + /* ce */ NULL, + /* cf */ NULL, + /* d0 */ NULL, + /* d1 */ NULL, + /* d2 */ NULL, + /* d3 */ NULL, + /* d4 */ NULL, + /* d5 */ NULL, + /* d6 */ NULL, + /* d7 */ NULL, + /* d8 */ NULL, + /* d9 */ NULL, + /* da */ NULL, + /* db */ NULL, + /* dc */ NULL, + /* dd */ NULL, + /* de */ NULL, + /* df */ NULL, + /* e0 */ NULL, + /* e1 */ NULL, + /* e2 */ NULL, + /* e3 */ NULL, + /* e4 */ NULL, + /* e5 */ NULL, + /* e6 */ NULL, + /* e7 */ NULL, + /* e8 */ NULL, + /* e9 */ NULL, + /* ea */ NULL, + /* eb */ NULL, + /* ec */ NULL, + /* ed */ NULL, + /* ee */ NULL, + /* ef */ NULL, + /* f0 */ NULL, + /* f1 */ NULL, + /* f2 */ NULL, + /* f3 */ NULL, + /* f4 */ NULL, + /* f5 */ NULL, + /* f6 */ NULL, + /* f7 */ NULL, + /* f8 */ NULL, + /* f9 */ NULL, + /* fa */ NULL, + /* fb */ NULL, + /* fc */ NULL, + /* fd */ NULL, + /* fe */ NULL, + /* ff */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_e3_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[835] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_e3_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[836] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_e3_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_e3_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_e3_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_74_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[840] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_74_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[841] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_74_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_74_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_74_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_76_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[842] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_76_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[843] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_76_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_76_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_76_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_75_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[845] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_75_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[846] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_75_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_75_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_75_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_64_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[849] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_64_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[850] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_64_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_64_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_64_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_66_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[851] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_66_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[852] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_66_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_66_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_66_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_65_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[854] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_65_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[855] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_65_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_65_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_65_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c5_reg_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[866] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c5_reg_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[867] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_c5_reg_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_c5_reg_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_c5_reg_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_c5_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_c5_reg_mprefix, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c4_reg_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[910] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c4_reg_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[912] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_c4_reg_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_c4_reg_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_c4_reg_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c4_mem_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[911] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c4_mem_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[913] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_c4_mem_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_c4_mem_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_c4_mem_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_c4_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_c4_mem_mprefix, + /* 01 */ (const void *)&gRootTable_root_0f_c4_reg_mprefix, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_f5_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[916] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_f5_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[917] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_f5_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_f5_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_f5_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ee_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[920] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ee_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[921] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_ee_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_ee_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_ee_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_de_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[922] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_de_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[923] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_de_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_de_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_de_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ea_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[928] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ea_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[929] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_ea_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_ea_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_ea_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_da_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[930] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_da_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[931] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_da_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_da_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_da_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_d7_reg_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[934] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_d7_reg_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[935] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_d7_reg_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_d7_reg_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_d7_reg_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_d7_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_d7_reg_mprefix, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_e4_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[952] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_e4_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[953] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_e4_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_e4_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_e4_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_e5_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[954] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_e5_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[955] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_e5_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_e5_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_e5_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_d5_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[957] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_d5_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[958] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_d5_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_d5_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_d5_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_f4_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[959] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_f4_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[960] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_f4_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_f4_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_f4_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_a1_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[961] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_a9_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[962] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_eb_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[980] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_eb_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[981] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_eb_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_eb_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_eb_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_f6_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[994] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_f6_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[995] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_f6_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_f6_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_f6_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[998] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[999] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1000] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1001] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_70_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_70_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_70_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_70_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_70_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_06_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1008] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_06_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1009] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_06_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_72_reg_06_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_72_reg_06_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_04_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1022] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_04_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1023] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_04_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_72_reg_04_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_72_reg_04_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_02_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1030] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_02_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1031] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_02_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_72_reg_02_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_72_reg_02_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_REG gRootTable_root_0f_72_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_72_reg_02_mprefix, + /* 03 */ NULL, + /* 04 */ (const void *)&gRootTable_root_0f_72_reg_04_mprefix, + /* 05 */ NULL, + /* 06 */ (const void *)&gRootTable_root_0f_72_reg_06_mprefix, + /* 07 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_72_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_72_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_f2_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1010] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_f2_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1011] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_f2_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_f2_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_f2_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_07_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1012] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_07_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_73_reg_07_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_06_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1013] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_06_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1014] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_06_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_73_reg_06_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_73_reg_06_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_03_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1034] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_03_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_73_reg_03_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_02_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1035] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_02_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1036] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_02_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_73_reg_02_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_73_reg_02_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_REG gRootTable_root_0f_73_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_73_reg_02_mprefix, + /* 03 */ (const void *)&gRootTable_root_0f_73_reg_03_mprefix, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ (const void *)&gRootTable_root_0f_73_reg_06_mprefix, + /* 07 */ (const void *)&gRootTable_root_0f_73_reg_07_mprefix, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_73_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_73_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_f3_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1015] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_f3_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1016] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_f3_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_f3_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_f3_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_06_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1017] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_06_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1018] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_06_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_71_reg_06_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_71_reg_06_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_04_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1026] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_04_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1027] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_04_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_71_reg_04_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_71_reg_04_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_02_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1039] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_02_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1040] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_02_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_71_reg_02_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_71_reg_02_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_REG gRootTable_root_0f_71_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_71_reg_02_mprefix, + /* 03 */ NULL, + /* 04 */ (const void *)&gRootTable_root_0f_71_reg_04_mprefix, + /* 05 */ NULL, + /* 06 */ (const void *)&gRootTable_root_0f_71_reg_06_mprefix, + /* 07 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_71_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_71_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_f1_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1019] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_f1_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1020] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_f1_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_f1_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_f1_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_e2_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1024] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_e2_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1025] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_e2_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_e2_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_e2_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_e1_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1028] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_e1_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1029] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_e1_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_e1_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_e1_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_d2_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1032] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_d2_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1033] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_d2_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_d2_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_d2_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_d3_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1037] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_d3_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1038] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_d3_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_d3_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_d3_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_d1_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1041] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_d1_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1042] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_d1_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_d1_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_d1_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_f8_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1043] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_f8_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1044] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_f8_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_f8_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_f8_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_fa_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1045] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_fa_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1046] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_fa_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_fa_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_fa_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_fb_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1047] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_fb_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1048] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_fb_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_fb_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_fb_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_e8_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1049] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_e8_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1050] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_e8_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_e8_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_e8_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_e9_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1051] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_e9_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1052] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_e9_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_e9_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_e9_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_d8_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1053] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_d8_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1054] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_d8_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_d8_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_d8_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_d9_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1055] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_d9_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1056] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_d9_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_d9_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_d9_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_f9_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1057] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_f9_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1058] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_f9_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_f9_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_f9_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_68_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1062] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_68_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1063] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_68_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_68_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_68_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_6a_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1064] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_6a_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1065] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_6a_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_6a_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_6a_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_6d_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1066] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_6d_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_6d_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_69_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1067] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_69_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1068] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_69_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_69_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_69_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_60_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1069] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_60_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1070] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_60_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_60_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_60_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_62_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1071] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_62_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1072] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_62_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_62_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_62_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_6c_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1073] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_6c_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_6c_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_61_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1074] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_61_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1075] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_61_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_61_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_61_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_a0_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1076] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_a8_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1077] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ef_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1098] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ef_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1099] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_ef_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_ef_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_ef_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_53_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1106] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_53_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1107] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_53_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_53_NP_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_53_F3_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_32_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1116] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_33_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1119] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_36_cyrix_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1125] +}; + +const ND_TABLE_VENDOR gRootTable_root_0f_36_vendor = +{ + ND_ILUT_VENDOR, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ (const void *)&gRootTable_root_0f_36_cyrix_leaf, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_31_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1128] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_7b_cyrix_mem_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1154] +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_7b_cyrix_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_7b_cyrix_mem_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VENDOR gRootTable_root_0f_7b_vendor = +{ + ND_ILUT_VENDOR, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ (const void *)&gRootTable_root_0f_7b_cyrix_modrmmod, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_aa_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1155] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_52_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1156] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_52_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1157] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_52_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_52_NP_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_52_F3_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_96_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1195] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_92_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1196] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_9c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1197] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_9e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1198] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_97_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1199] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_93_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1200] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_9d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1201] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_9f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1202] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_91_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1203] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_9b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1204] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_99_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1205] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_95_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1206] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_90_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1207] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_9a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1208] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_98_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1209] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_94_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1211] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_a4_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1227] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_a5_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1228] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ac_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1236] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ad_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1237] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c6_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1239] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c6_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1240] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_c6_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_c6_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_c6_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1250] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1251] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1252] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1253] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_51_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_51_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_51_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_51_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_51_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1281] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1282] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1283] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1284] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_5c_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_5c_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_5c_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_5c_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_5c_F2_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_7a_cyrix_mem_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1286] +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_7a_cyrix_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_7a_cyrix_mem_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VENDOR gRootTable_root_0f_7a_vendor = +{ + ND_ILUT_VENDOR, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ (const void *)&gRootTable_root_0f_7a_cyrix_modrmmod, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_34_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1290] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_35_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1291] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_2e_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1316] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_2e_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1317] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_2e_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_2e_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_2e_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_ff_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1318] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_b9_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1319] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_0b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1320] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_15_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1323] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_15_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1324] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_15_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_15_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_15_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_14_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1325] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_14_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1326] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_14_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_14_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_14_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_09_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2490] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_09_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2491] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_09_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_09_NP_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_09_F3_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_30_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2494] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c0_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2502] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c1_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2503] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_02_00_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2515] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_02_00_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_a7_reg_02_00_F3_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_02_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gRootTable_root_0f_a7_reg_02_00_mprefix, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_04_00_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2516] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_04_00_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_a7_reg_04_00_F3_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_04_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gRootTable_root_0f_a7_reg_04_00_mprefix, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_03_00_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2517] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_03_00_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_a7_reg_03_00_F3_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_03_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gRootTable_root_0f_a7_reg_03_00_mprefix, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_01_00_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2518] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_01_00_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_a7_reg_01_00_F3_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_01_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gRootTable_root_0f_a7_reg_01_00_mprefix, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_05_00_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2519] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_05_00_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_a7_reg_05_00_F3_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_05_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gRootTable_root_0f_a7_reg_05_00_mprefix, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2551] +}; + +const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_00_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gRootTable_root_0f_a7_reg_00_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_MODRM_REG gRootTable_root_0f_a7_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_0f_a7_reg_00_modrmrm, + /* 01 */ (const void *)&gRootTable_root_0f_a7_reg_01_modrmrm, + /* 02 */ (const void *)&gRootTable_root_0f_a7_reg_02_modrmrm, + /* 03 */ (const void *)&gRootTable_root_0f_a7_reg_03_modrmrm, + /* 04 */ (const void *)&gRootTable_root_0f_a7_reg_04_modrmrm, + /* 05 */ (const void *)&gRootTable_root_0f_a7_reg_05_modrmrm, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_a7_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_a7_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_57_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2533] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_57_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2534] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_57_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_57_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_57_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_OPCODE gRootTable_root_0f_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ (const void *)&gRootTable_root_0f_00_modrmmod, + /* 01 */ (const void *)&gRootTable_root_0f_01_modrmmod, + /* 02 */ (const void *)&gRootTable_root_0f_02_modrmmod, + /* 03 */ (const void *)&gRootTable_root_0f_03_modrmmod, + /* 04 */ NULL, + /* 05 */ (const void *)&gRootTable_root_0f_05_auxiliary, + /* 06 */ (const void *)&gRootTable_root_0f_06_leaf, + /* 07 */ (const void *)&gRootTable_root_0f_07_auxiliary, + /* 08 */ (const void *)&gRootTable_root_0f_08_leaf, + /* 09 */ (const void *)&gRootTable_root_0f_09_mprefix, + /* 0a */ (const void *)&gRootTable_root_0f_0a_leaf, + /* 0b */ (const void *)&gRootTable_root_0f_0b_leaf, + /* 0c */ NULL, + /* 0d */ (const void *)&gRootTable_root_0f_0d_modrmmod, + /* 0e */ (const void *)&gRootTable_root_0f_0e_leaf, + /* 0f */ (const void *)&gRootTable_root_0f_0f_opcode_3dnow, + /* 10 */ (const void *)&gRootTable_root_0f_10_mprefix, + /* 11 */ (const void *)&gRootTable_root_0f_11_mprefix, + /* 12 */ (const void *)&gRootTable_root_0f_12_modrmmod, + /* 13 */ (const void *)&gRootTable_root_0f_13_modrmmod, + /* 14 */ (const void *)&gRootTable_root_0f_14_mprefix, + /* 15 */ (const void *)&gRootTable_root_0f_15_mprefix, + /* 16 */ (const void *)&gRootTable_root_0f_16_modrmmod, + /* 17 */ (const void *)&gRootTable_root_0f_17_modrmmod, + /* 18 */ (const void *)&gRootTable_root_0f_18_modrmmod, + /* 19 */ (const void *)&gRootTable_root_0f_19_leaf, + /* 1a */ (const void *)&gRootTable_root_0f_1a_modrmmod, + /* 1b */ (const void *)&gRootTable_root_0f_1b_modrmmod, + /* 1c */ (const void *)&gRootTable_root_0f_1c_modrmmod, + /* 1d */ (const void *)&gRootTable_root_0f_1d_leaf, + /* 1e */ (const void *)&gRootTable_root_0f_1e_modrmmod, + /* 1f */ (const void *)&gRootTable_root_0f_1f_leaf, + /* 20 */ (const void *)&gRootTable_root_0f_20_leaf, + /* 21 */ (const void *)&gRootTable_root_0f_21_leaf, + /* 22 */ (const void *)&gRootTable_root_0f_22_leaf, + /* 23 */ (const void *)&gRootTable_root_0f_23_leaf, + /* 24 */ (const void *)&gRootTable_root_0f_24_leaf, + /* 25 */ NULL, + /* 26 */ (const void *)&gRootTable_root_0f_26_leaf, + /* 27 */ NULL, + /* 28 */ (const void *)&gRootTable_root_0f_28_mprefix, + /* 29 */ (const void *)&gRootTable_root_0f_29_mprefix, + /* 2a */ (const void *)&gRootTable_root_0f_2a_mprefix, + /* 2b */ (const void *)&gRootTable_root_0f_2b_modrmmod, + /* 2c */ (const void *)&gRootTable_root_0f_2c_mprefix, + /* 2d */ (const void *)&gRootTable_root_0f_2d_mprefix, + /* 2e */ (const void *)&gRootTable_root_0f_2e_mprefix, + /* 2f */ (const void *)&gRootTable_root_0f_2f_mprefix, + /* 30 */ (const void *)&gRootTable_root_0f_30_leaf, + /* 31 */ (const void *)&gRootTable_root_0f_31_leaf, + /* 32 */ (const void *)&gRootTable_root_0f_32_leaf, + /* 33 */ (const void *)&gRootTable_root_0f_33_leaf, + /* 34 */ (const void *)&gRootTable_root_0f_34_leaf, + /* 35 */ (const void *)&gRootTable_root_0f_35_leaf, + /* 36 */ (const void *)&gRootTable_root_0f_36_vendor, + /* 37 */ (const void *)&gRootTable_root_0f_37_vendor, + /* 38 */ (const void *)&gRootTable_root_0f_38_opcode, + /* 39 */ (const void *)&gRootTable_root_0f_39_leaf, + /* 3a */ (const void *)&gRootTable_root_0f_3a_opcode, + /* 3b */ NULL, + /* 3c */ (const void *)&gRootTable_root_0f_3c_leaf, + /* 3d */ (const void *)&gRootTable_root_0f_3d_leaf, + /* 3e */ NULL, + /* 3f */ (const void *)&gRootTable_root_0f_3f_leaf, + /* 40 */ (const void *)&gRootTable_root_0f_40_leaf, + /* 41 */ (const void *)&gRootTable_root_0f_41_leaf, + /* 42 */ (const void *)&gRootTable_root_0f_42_leaf, + /* 43 */ (const void *)&gRootTable_root_0f_43_leaf, + /* 44 */ (const void *)&gRootTable_root_0f_44_leaf, + /* 45 */ (const void *)&gRootTable_root_0f_45_leaf, + /* 46 */ (const void *)&gRootTable_root_0f_46_leaf, + /* 47 */ (const void *)&gRootTable_root_0f_47_leaf, + /* 48 */ (const void *)&gRootTable_root_0f_48_leaf, + /* 49 */ (const void *)&gRootTable_root_0f_49_leaf, + /* 4a */ (const void *)&gRootTable_root_0f_4a_leaf, + /* 4b */ (const void *)&gRootTable_root_0f_4b_leaf, + /* 4c */ (const void *)&gRootTable_root_0f_4c_leaf, + /* 4d */ (const void *)&gRootTable_root_0f_4d_leaf, + /* 4e */ (const void *)&gRootTable_root_0f_4e_leaf, + /* 4f */ (const void *)&gRootTable_root_0f_4f_leaf, + /* 50 */ (const void *)&gRootTable_root_0f_50_modrmmod, + /* 51 */ (const void *)&gRootTable_root_0f_51_mprefix, + /* 52 */ (const void *)&gRootTable_root_0f_52_mprefix, + /* 53 */ (const void *)&gRootTable_root_0f_53_mprefix, + /* 54 */ (const void *)&gRootTable_root_0f_54_mprefix, + /* 55 */ (const void *)&gRootTable_root_0f_55_mprefix, + /* 56 */ (const void *)&gRootTable_root_0f_56_mprefix, + /* 57 */ (const void *)&gRootTable_root_0f_57_mprefix, + /* 58 */ (const void *)&gRootTable_root_0f_58_mprefix, + /* 59 */ (const void *)&gRootTable_root_0f_59_mprefix, + /* 5a */ (const void *)&gRootTable_root_0f_5a_mprefix, + /* 5b */ (const void *)&gRootTable_root_0f_5b_mprefix, + /* 5c */ (const void *)&gRootTable_root_0f_5c_mprefix, + /* 5d */ (const void *)&gRootTable_root_0f_5d_mprefix, + /* 5e */ (const void *)&gRootTable_root_0f_5e_mprefix, + /* 5f */ (const void *)&gRootTable_root_0f_5f_mprefix, + /* 60 */ (const void *)&gRootTable_root_0f_60_mprefix, + /* 61 */ (const void *)&gRootTable_root_0f_61_mprefix, + /* 62 */ (const void *)&gRootTable_root_0f_62_mprefix, + /* 63 */ (const void *)&gRootTable_root_0f_63_mprefix, + /* 64 */ (const void *)&gRootTable_root_0f_64_mprefix, + /* 65 */ (const void *)&gRootTable_root_0f_65_mprefix, + /* 66 */ (const void *)&gRootTable_root_0f_66_mprefix, + /* 67 */ (const void *)&gRootTable_root_0f_67_mprefix, + /* 68 */ (const void *)&gRootTable_root_0f_68_mprefix, + /* 69 */ (const void *)&gRootTable_root_0f_69_mprefix, + /* 6a */ (const void *)&gRootTable_root_0f_6a_mprefix, + /* 6b */ (const void *)&gRootTable_root_0f_6b_mprefix, + /* 6c */ (const void *)&gRootTable_root_0f_6c_mprefix, + /* 6d */ (const void *)&gRootTable_root_0f_6d_mprefix, + /* 6e */ (const void *)&gRootTable_root_0f_6e_mprefix, + /* 6f */ (const void *)&gRootTable_root_0f_6f_mprefix, + /* 70 */ (const void *)&gRootTable_root_0f_70_mprefix, + /* 71 */ (const void *)&gRootTable_root_0f_71_modrmmod, + /* 72 */ (const void *)&gRootTable_root_0f_72_modrmmod, + /* 73 */ (const void *)&gRootTable_root_0f_73_modrmmod, + /* 74 */ (const void *)&gRootTable_root_0f_74_mprefix, + /* 75 */ (const void *)&gRootTable_root_0f_75_mprefix, + /* 76 */ (const void *)&gRootTable_root_0f_76_mprefix, + /* 77 */ (const void *)&gRootTable_root_0f_77_mprefix, + /* 78 */ (const void *)&gRootTable_root_0f_78_vendor, + /* 79 */ (const void *)&gRootTable_root_0f_79_vendor, + /* 7a */ (const void *)&gRootTable_root_0f_7a_vendor, + /* 7b */ (const void *)&gRootTable_root_0f_7b_vendor, + /* 7c */ (const void *)&gRootTable_root_0f_7c_vendor, + /* 7d */ (const void *)&gRootTable_root_0f_7d_vendor, + /* 7e */ (const void *)&gRootTable_root_0f_7e_vendor, + /* 7f */ (const void *)&gRootTable_root_0f_7f_mprefix, + /* 80 */ (const void *)&gRootTable_root_0f_80_leaf, + /* 81 */ (const void *)&gRootTable_root_0f_81_leaf, + /* 82 */ (const void *)&gRootTable_root_0f_82_leaf, + /* 83 */ (const void *)&gRootTable_root_0f_83_leaf, + /* 84 */ (const void *)&gRootTable_root_0f_84_leaf, + /* 85 */ (const void *)&gRootTable_root_0f_85_leaf, + /* 86 */ (const void *)&gRootTable_root_0f_86_leaf, + /* 87 */ (const void *)&gRootTable_root_0f_87_leaf, + /* 88 */ (const void *)&gRootTable_root_0f_88_leaf, + /* 89 */ (const void *)&gRootTable_root_0f_89_leaf, + /* 8a */ (const void *)&gRootTable_root_0f_8a_leaf, + /* 8b */ (const void *)&gRootTable_root_0f_8b_leaf, + /* 8c */ (const void *)&gRootTable_root_0f_8c_leaf, + /* 8d */ (const void *)&gRootTable_root_0f_8d_leaf, + /* 8e */ (const void *)&gRootTable_root_0f_8e_leaf, + /* 8f */ (const void *)&gRootTable_root_0f_8f_leaf, + /* 90 */ (const void *)&gRootTable_root_0f_90_leaf, + /* 91 */ (const void *)&gRootTable_root_0f_91_leaf, + /* 92 */ (const void *)&gRootTable_root_0f_92_leaf, + /* 93 */ (const void *)&gRootTable_root_0f_93_leaf, + /* 94 */ (const void *)&gRootTable_root_0f_94_leaf, + /* 95 */ (const void *)&gRootTable_root_0f_95_leaf, + /* 96 */ (const void *)&gRootTable_root_0f_96_leaf, + /* 97 */ (const void *)&gRootTable_root_0f_97_leaf, + /* 98 */ (const void *)&gRootTable_root_0f_98_leaf, + /* 99 */ (const void *)&gRootTable_root_0f_99_leaf, + /* 9a */ (const void *)&gRootTable_root_0f_9a_leaf, + /* 9b */ (const void *)&gRootTable_root_0f_9b_leaf, + /* 9c */ (const void *)&gRootTable_root_0f_9c_leaf, + /* 9d */ (const void *)&gRootTable_root_0f_9d_leaf, + /* 9e */ (const void *)&gRootTable_root_0f_9e_leaf, + /* 9f */ (const void *)&gRootTable_root_0f_9f_leaf, + /* a0 */ (const void *)&gRootTable_root_0f_a0_leaf, + /* a1 */ (const void *)&gRootTable_root_0f_a1_leaf, + /* a2 */ (const void *)&gRootTable_root_0f_a2_leaf, + /* a3 */ (const void *)&gRootTable_root_0f_a3_leaf, + /* a4 */ (const void *)&gRootTable_root_0f_a4_leaf, + /* a5 */ (const void *)&gRootTable_root_0f_a5_leaf, + /* a6 */ (const void *)&gRootTable_root_0f_a6_modrmmod, + /* a7 */ (const void *)&gRootTable_root_0f_a7_modrmmod, + /* a8 */ (const void *)&gRootTable_root_0f_a8_leaf, + /* a9 */ (const void *)&gRootTable_root_0f_a9_leaf, + /* aa */ (const void *)&gRootTable_root_0f_aa_leaf, + /* ab */ (const void *)&gRootTable_root_0f_ab_leaf, + /* ac */ (const void *)&gRootTable_root_0f_ac_leaf, + /* ad */ (const void *)&gRootTable_root_0f_ad_leaf, + /* ae */ (const void *)&gRootTable_root_0f_ae_modrmmod, + /* af */ (const void *)&gRootTable_root_0f_af_leaf, + /* b0 */ (const void *)&gRootTable_root_0f_b0_leaf, + /* b1 */ (const void *)&gRootTable_root_0f_b1_leaf, + /* b2 */ (const void *)&gRootTable_root_0f_b2_modrmmod, + /* b3 */ (const void *)&gRootTable_root_0f_b3_leaf, + /* b4 */ (const void *)&gRootTable_root_0f_b4_modrmmod, + /* b5 */ (const void *)&gRootTable_root_0f_b5_modrmmod, + /* b6 */ (const void *)&gRootTable_root_0f_b6_leaf, + /* b7 */ (const void *)&gRootTable_root_0f_b7_leaf, + /* b8 */ (const void *)&gRootTable_root_0f_b8_auxiliary, + /* b9 */ (const void *)&gRootTable_root_0f_b9_leaf, + /* ba */ (const void *)&gRootTable_root_0f_ba_modrmreg, + /* bb */ (const void *)&gRootTable_root_0f_bb_leaf, + /* bc */ (const void *)&gRootTable_root_0f_bc_auxiliary, + /* bd */ (const void *)&gRootTable_root_0f_bd_auxiliary, + /* be */ (const void *)&gRootTable_root_0f_be_leaf, + /* bf */ (const void *)&gRootTable_root_0f_bf_leaf, + /* c0 */ (const void *)&gRootTable_root_0f_c0_leaf, + /* c1 */ (const void *)&gRootTable_root_0f_c1_leaf, + /* c2 */ (const void *)&gRootTable_root_0f_c2_mprefix, + /* c3 */ (const void *)&gRootTable_root_0f_c3_modrmmod, + /* c4 */ (const void *)&gRootTable_root_0f_c4_modrmmod, + /* c5 */ (const void *)&gRootTable_root_0f_c5_modrmmod, + /* c6 */ (const void *)&gRootTable_root_0f_c6_mprefix, + /* c7 */ (const void *)&gRootTable_root_0f_c7_modrmmod, + /* c8 */ (const void *)&gRootTable_root_0f_c8_leaf, + /* c9 */ (const void *)&gRootTable_root_0f_c9_leaf, + /* ca */ (const void *)&gRootTable_root_0f_ca_leaf, + /* cb */ (const void *)&gRootTable_root_0f_cb_leaf, + /* cc */ (const void *)&gRootTable_root_0f_cc_leaf, + /* cd */ (const void *)&gRootTable_root_0f_cd_leaf, + /* ce */ (const void *)&gRootTable_root_0f_ce_leaf, + /* cf */ (const void *)&gRootTable_root_0f_cf_leaf, + /* d0 */ (const void *)&gRootTable_root_0f_d0_mprefix, + /* d1 */ (const void *)&gRootTable_root_0f_d1_mprefix, + /* d2 */ (const void *)&gRootTable_root_0f_d2_mprefix, + /* d3 */ (const void *)&gRootTable_root_0f_d3_mprefix, + /* d4 */ (const void *)&gRootTable_root_0f_d4_mprefix, + /* d5 */ (const void *)&gRootTable_root_0f_d5_mprefix, + /* d6 */ (const void *)&gRootTable_root_0f_d6_modrmmod, + /* d7 */ (const void *)&gRootTable_root_0f_d7_modrmmod, + /* d8 */ (const void *)&gRootTable_root_0f_d8_mprefix, + /* d9 */ (const void *)&gRootTable_root_0f_d9_mprefix, + /* da */ (const void *)&gRootTable_root_0f_da_mprefix, + /* db */ (const void *)&gRootTable_root_0f_db_mprefix, + /* dc */ (const void *)&gRootTable_root_0f_dc_mprefix, + /* dd */ (const void *)&gRootTable_root_0f_dd_mprefix, + /* de */ (const void *)&gRootTable_root_0f_de_mprefix, + /* df */ (const void *)&gRootTable_root_0f_df_mprefix, + /* e0 */ (const void *)&gRootTable_root_0f_e0_mprefix, + /* e1 */ (const void *)&gRootTable_root_0f_e1_mprefix, + /* e2 */ (const void *)&gRootTable_root_0f_e2_mprefix, + /* e3 */ (const void *)&gRootTable_root_0f_e3_mprefix, + /* e4 */ (const void *)&gRootTable_root_0f_e4_mprefix, + /* e5 */ (const void *)&gRootTable_root_0f_e5_mprefix, + /* e6 */ (const void *)&gRootTable_root_0f_e6_mprefix, + /* e7 */ (const void *)&gRootTable_root_0f_e7_modrmmod, + /* e8 */ (const void *)&gRootTable_root_0f_e8_mprefix, + /* e9 */ (const void *)&gRootTable_root_0f_e9_mprefix, + /* ea */ (const void *)&gRootTable_root_0f_ea_mprefix, + /* eb */ (const void *)&gRootTable_root_0f_eb_mprefix, + /* ec */ (const void *)&gRootTable_root_0f_ec_mprefix, + /* ed */ (const void *)&gRootTable_root_0f_ed_mprefix, + /* ee */ (const void *)&gRootTable_root_0f_ee_mprefix, + /* ef */ (const void *)&gRootTable_root_0f_ef_mprefix, + /* f0 */ (const void *)&gRootTable_root_0f_f0_modrmmod, + /* f1 */ (const void *)&gRootTable_root_0f_f1_mprefix, + /* f2 */ (const void *)&gRootTable_root_0f_f2_mprefix, + /* f3 */ (const void *)&gRootTable_root_0f_f3_mprefix, + /* f4 */ (const void *)&gRootTable_root_0f_f4_mprefix, + /* f5 */ (const void *)&gRootTable_root_0f_f5_mprefix, + /* f6 */ (const void *)&gRootTable_root_0f_f6_mprefix, + /* f7 */ (const void *)&gRootTable_root_0f_f7_modrmmod, + /* f8 */ (const void *)&gRootTable_root_0f_f8_mprefix, + /* f9 */ (const void *)&gRootTable_root_0f_f9_mprefix, + /* fa */ (const void *)&gRootTable_root_0f_fa_mprefix, + /* fb */ (const void *)&gRootTable_root_0f_fb_mprefix, + /* fc */ (const void *)&gRootTable_root_0f_fc_mprefix, + /* fd */ (const void *)&gRootTable_root_0f_fd_mprefix, + /* fe */ (const void *)&gRootTable_root_0f_fe_mprefix, + /* ff */ (const void *)&gRootTable_root_0f_ff_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[15] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[16] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[17] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[18] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[19] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[20] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_20_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[39] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_21_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[40] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_22_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[41] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_23_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[42] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_24_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[43] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_25_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[44] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_63_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[54] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_63_64_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[702] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_63_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_63_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ (const void *)&gRootTable_root_63_64_leaf, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_62_mem_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[79] +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_62_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_62_mem_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_e8_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[99] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[100] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[102] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[209] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[411] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[450] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[454] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1092] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_ff_mem_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_ff_mem_00_leaf, + /* 01 */ (const void *)&gRootTable_root_ff_mem_01_leaf, + /* 02 */ (const void *)&gRootTable_root_ff_mem_02_leaf, + /* 03 */ (const void *)&gRootTable_root_ff_mem_03_leaf, + /* 04 */ (const void *)&gRootTable_root_ff_mem_04_leaf, + /* 05 */ (const void *)&gRootTable_root_ff_mem_05_leaf, + /* 06 */ (const void *)&gRootTable_root_ff_mem_06_leaf, + /* 07 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[100] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[209] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[411] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[450] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1092] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_ff_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_ff_reg_00_leaf, + /* 01 */ (const void *)&gRootTable_root_ff_reg_01_leaf, + /* 02 */ (const void *)&gRootTable_root_ff_reg_02_leaf, + /* 03 */ NULL, + /* 04 */ (const void *)&gRootTable_root_ff_reg_04_leaf, + /* 05 */ NULL, + /* 06 */ (const void *)&gRootTable_root_ff_reg_06_leaf, + /* 07 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_ff_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_ff_mem_modrmreg, + /* 01 */ (const void *)&gRootTable_root_ff_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_9a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[101] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_98_ds16_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[103] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_98_ds64_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[105] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_98_ds32_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[197] +}; + +const ND_TABLE_DSIZE gRootTable_root_98_dsize = +{ + ND_ILUT_DSIZE, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_98_ds16_leaf, + /* 02 */ (const void *)&gRootTable_root_98_ds32_leaf, + /* 03 */ (const void *)&gRootTable_root_98_ds64_leaf, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_99_ds32_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[104] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_99_ds64_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[169] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_99_ds16_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[196] +}; + +const ND_TABLE_DSIZE gRootTable_root_99_dsize = +{ + ND_ILUT_DSIZE, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_99_ds16_leaf, + /* 02 */ (const void *)&gRootTable_root_99_ds32_leaf, + /* 03 */ (const void *)&gRootTable_root_99_ds64_leaf, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_f8_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[108] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_fc_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[109] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_fa_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[116] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_f5_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[121] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_38_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[138] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_39_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[139] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_3a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[140] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_3b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[141] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_3c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[142] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_3d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[143] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_a6_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[150] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_a6_rep_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[151] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_a6_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_a6_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ (const void *)&gRootTable_root_a6_rep_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds32_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[153] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds32_rep_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[154] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_a7_ds32_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_a7_ds32_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ (const void *)&gRootTable_root_a7_ds32_rep_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds64_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[155] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds64_rep_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[156] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_a7_ds64_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_a7_ds64_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ (const void *)&gRootTable_root_a7_ds64_rep_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds16_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[158] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds16_rep_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[159] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_a7_ds16_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_a7_ds16_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ (const void *)&gRootTable_root_a7_ds16_rep_leaf, + } +}; + +const ND_TABLE_DSIZE gRootTable_root_a7_dsize = +{ + ND_ILUT_DSIZE, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_a7_ds16_auxiliary, + /* 02 */ (const void *)&gRootTable_root_a7_ds32_auxiliary, + /* 03 */ (const void *)&gRootTable_root_a7_ds64_auxiliary, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_27_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[198] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_2f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[199] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_48_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[200] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_49_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[201] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_4a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[202] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_4b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[203] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_4c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[204] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_4d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[205] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_4e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[206] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_4f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[207] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_fe_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[208] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_fe_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[410] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_fe_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_fe_00_leaf, + /* 01 */ (const void *)&gRootTable_root_fe_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_f6_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[211] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_f6_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[391] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_f6_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[396] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_f6_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[710] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_f6_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[719] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_f6_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[772] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_f6_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1303] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_f6_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1304] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_f6_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_f6_00_leaf, + /* 01 */ (const void *)&gRootTable_root_f6_01_leaf, + /* 02 */ (const void *)&gRootTable_root_f6_02_leaf, + /* 03 */ (const void *)&gRootTable_root_f6_03_leaf, + /* 04 */ (const void *)&gRootTable_root_f6_04_leaf, + /* 05 */ (const void *)&gRootTable_root_f6_05_leaf, + /* 06 */ (const void *)&gRootTable_root_f6_06_leaf, + /* 07 */ (const void *)&gRootTable_root_f6_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_f7_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[212] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_f7_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[392] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_f7_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[397] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_f7_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[711] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_f7_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[720] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_f7_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[773] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_f7_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1305] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_f7_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1306] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_f7_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_f7_00_leaf, + /* 01 */ (const void *)&gRootTable_root_f7_01_leaf, + /* 02 */ (const void *)&gRootTable_root_f7_02_leaf, + /* 03 */ (const void *)&gRootTable_root_f7_03_leaf, + /* 04 */ (const void *)&gRootTable_root_f7_04_leaf, + /* 05 */ (const void *)&gRootTable_root_f7_05_leaf, + /* 06 */ (const void *)&gRootTable_root_f7_06_leaf, + /* 07 */ (const void *)&gRootTable_root_f7_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_c8_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[228] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[232] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[263] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[292] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[334] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[336] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[337] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[379] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[380] +}; + +const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_06_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gRootTable_root_d9_reg_06_00_leaf, + /* 01 */ (const void *)&gRootTable_root_d9_reg_06_01_leaf, + /* 02 */ (const void *)&gRootTable_root_d9_reg_06_02_leaf, + /* 03 */ (const void *)&gRootTable_root_d9_reg_06_03_leaf, + /* 04 */ (const void *)&gRootTable_root_d9_reg_06_04_leaf, + /* 05 */ (const void *)&gRootTable_root_d9_reg_06_05_leaf, + /* 06 */ (const void *)&gRootTable_root_d9_reg_06_06_leaf, + /* 07 */ (const void *)&gRootTable_root_d9_reg_06_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_04_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[233] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_04_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[241] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_04_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[367] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_04_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[373] +}; + +const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_04_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gRootTable_root_d9_reg_04_00_leaf, + /* 01 */ (const void *)&gRootTable_root_d9_reg_04_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ (const void *)&gRootTable_root_d9_reg_04_04_leaf, + /* 05 */ (const void *)&gRootTable_root_d9_reg_04_05_leaf, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[262] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[335] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[339] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[341] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[342] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[343] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[344] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[381] +}; + +const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_07_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gRootTable_root_d9_reg_07_00_leaf, + /* 01 */ (const void *)&gRootTable_root_d9_reg_07_01_leaf, + /* 02 */ (const void *)&gRootTable_root_d9_reg_07_02_leaf, + /* 03 */ (const void *)&gRootTable_root_d9_reg_07_03_leaf, + /* 04 */ (const void *)&gRootTable_root_d9_reg_07_04_leaf, + /* 05 */ (const void *)&gRootTable_root_d9_reg_07_05_leaf, + /* 06 */ (const void *)&gRootTable_root_d9_reg_07_06_leaf, + /* 07 */ (const void *)&gRootTable_root_d9_reg_07_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[306] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[309] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[312] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[313] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[314] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[315] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[316] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[317] +}; + +const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_05_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gRootTable_root_d9_reg_05_00_leaf, + /* 01 */ (const void *)&gRootTable_root_d9_reg_05_01_leaf, + /* 02 */ (const void *)&gRootTable_root_d9_reg_05_02_leaf, + /* 03 */ (const void *)&gRootTable_root_d9_reg_05_03_leaf, + /* 04 */ (const void *)&gRootTable_root_d9_reg_05_04_leaf, + /* 05 */ (const void *)&gRootTable_root_d9_reg_05_05_leaf, + /* 06 */ (const void *)&gRootTable_root_d9_reg_05_06_leaf, + /* 07 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[326] +}; + +const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_02_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gRootTable_root_d9_reg_02_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[355] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[374] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_d9_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_d9_reg_00_leaf, + /* 01 */ (const void *)&gRootTable_root_d9_reg_01_leaf, + /* 02 */ (const void *)&gRootTable_root_d9_reg_02_modrmrm, + /* 03 */ (const void *)&gRootTable_root_d9_reg_03_leaf, + /* 04 */ (const void *)&gRootTable_root_d9_reg_04_modrmrm, + /* 05 */ (const void *)&gRootTable_root_d9_reg_05_modrmrm, + /* 06 */ (const void *)&gRootTable_root_d9_reg_06_modrmrm, + /* 07 */ (const void *)&gRootTable_root_d9_reg_07_modrmrm, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[305] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[310] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[311] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[330] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[331] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[345] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[349] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_d9_mem_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_d9_mem_00_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_d9_mem_02_leaf, + /* 03 */ (const void *)&gRootTable_root_d9_mem_03_leaf, + /* 04 */ (const void *)&gRootTable_root_d9_mem_04_leaf, + /* 05 */ (const void *)&gRootTable_root_d9_mem_05_leaf, + /* 06 */ (const void *)&gRootTable_root_d9_mem_06_leaf, + /* 07 */ (const void *)&gRootTable_root_d9_mem_07_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_d9_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_d9_mem_modrmreg, + /* 01 */ (const void *)&gRootTable_root_d9_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[234] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[250] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[256] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[264] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[269] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[318] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[357] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[362] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_d8_mem_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_d8_mem_00_leaf, + /* 01 */ (const void *)&gRootTable_root_d8_mem_01_leaf, + /* 02 */ (const void *)&gRootTable_root_d8_mem_02_leaf, + /* 03 */ (const void *)&gRootTable_root_d8_mem_03_leaf, + /* 04 */ (const void *)&gRootTable_root_d8_mem_04_leaf, + /* 05 */ (const void *)&gRootTable_root_d8_mem_05_leaf, + /* 06 */ (const void *)&gRootTable_root_d8_mem_06_leaf, + /* 07 */ (const void *)&gRootTable_root_d8_mem_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[235] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[251] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[257] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[265] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[270] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[319] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[358] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[363] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_d8_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_d8_reg_00_leaf, + /* 01 */ (const void *)&gRootTable_root_d8_reg_01_leaf, + /* 02 */ (const void *)&gRootTable_root_d8_reg_02_leaf, + /* 03 */ (const void *)&gRootTable_root_d8_reg_03_leaf, + /* 04 */ (const void *)&gRootTable_root_d8_reg_04_leaf, + /* 05 */ (const void *)&gRootTable_root_d8_reg_05_leaf, + /* 06 */ (const void *)&gRootTable_root_d8_reg_06_leaf, + /* 07 */ (const void *)&gRootTable_root_d8_reg_07_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_d8_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_d8_mem_modrmreg, + /* 01 */ (const void *)&gRootTable_root_d8_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[236] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[252] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[258] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[266] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[271] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[320] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[359] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[364] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_dc_mem_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_dc_mem_00_leaf, + /* 01 */ (const void *)&gRootTable_root_dc_mem_01_leaf, + /* 02 */ (const void *)&gRootTable_root_dc_mem_02_leaf, + /* 03 */ (const void *)&gRootTable_root_dc_mem_03_leaf, + /* 04 */ (const void *)&gRootTable_root_dc_mem_04_leaf, + /* 05 */ (const void *)&gRootTable_root_dc_mem_05_leaf, + /* 06 */ (const void *)&gRootTable_root_dc_mem_06_leaf, + /* 07 */ (const void *)&gRootTable_root_dc_mem_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[237] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[253] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[259] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[267] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[272] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[321] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[360] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[365] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_dc_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_dc_reg_00_leaf, + /* 01 */ (const void *)&gRootTable_root_dc_reg_01_leaf, + /* 02 */ (const void *)&gRootTable_root_dc_reg_02_leaf, + /* 03 */ (const void *)&gRootTable_root_dc_reg_03_leaf, + /* 04 */ (const void *)&gRootTable_root_dc_reg_04_leaf, + /* 05 */ (const void *)&gRootTable_root_dc_reg_05_leaf, + /* 06 */ (const void *)&gRootTable_root_dc_reg_06_leaf, + /* 07 */ (const void *)&gRootTable_root_dc_reg_07_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_dc_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_dc_mem_modrmreg, + /* 01 */ (const void *)&gRootTable_root_dc_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[238] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[260] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_03_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[261] +}; + +const ND_TABLE_MODRM_RM gRootTable_root_de_reg_03_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_de_reg_03_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[268] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[273] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[322] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[361] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[366] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_de_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_de_reg_00_leaf, + /* 01 */ (const void *)&gRootTable_root_de_reg_01_leaf, + /* 02 */ (const void *)&gRootTable_root_de_reg_02_leaf, + /* 03 */ (const void *)&gRootTable_root_de_reg_03_modrmrm, + /* 04 */ (const void *)&gRootTable_root_de_reg_04_leaf, + /* 05 */ (const void *)&gRootTable_root_de_reg_05_leaf, + /* 06 */ (const void *)&gRootTable_root_de_reg_06_leaf, + /* 07 */ (const void *)&gRootTable_root_de_reg_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[278] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[280] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[282] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[284] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[286] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[291] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[302] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[304] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_de_mem_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_de_mem_00_leaf, + /* 01 */ (const void *)&gRootTable_root_de_mem_01_leaf, + /* 02 */ (const void *)&gRootTable_root_de_mem_02_leaf, + /* 03 */ (const void *)&gRootTable_root_de_mem_03_leaf, + /* 04 */ (const void *)&gRootTable_root_de_mem_04_leaf, + /* 05 */ (const void *)&gRootTable_root_de_mem_05_leaf, + /* 06 */ (const void *)&gRootTable_root_de_mem_06_leaf, + /* 07 */ (const void *)&gRootTable_root_de_mem_07_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_de_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_de_mem_modrmreg, + /* 01 */ (const void *)&gRootTable_root_de_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[239] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[240] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[288] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[289] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[294] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[296] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[297] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[300] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_df_mem_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_df_mem_00_leaf, + /* 01 */ (const void *)&gRootTable_root_df_mem_01_leaf, + /* 02 */ (const void *)&gRootTable_root_df_mem_02_leaf, + /* 03 */ (const void *)&gRootTable_root_df_mem_03_leaf, + /* 04 */ (const void *)&gRootTable_root_df_mem_04_leaf, + /* 05 */ (const void *)&gRootTable_root_df_mem_05_leaf, + /* 06 */ (const void *)&gRootTable_root_df_mem_06_leaf, + /* 07 */ (const void *)&gRootTable_root_df_mem_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[255] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[276] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_04_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[333] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_04_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[348] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_04_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[356] +}; + +const ND_TABLE_MODRM_RM gRootTable_root_df_reg_04_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gRootTable_root_df_reg_04_00_leaf, + /* 01 */ (const void *)&gRootTable_root_df_reg_04_01_leaf, + /* 02 */ (const void *)&gRootTable_root_df_reg_04_02_leaf, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_07_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[338] +}; + +const ND_TABLE_MODRM_RM gRootTable_root_df_reg_07_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ (const void *)&gRootTable_root_df_reg_07_04_leaf, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[353] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[354] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[370] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[376] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_df_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_df_reg_00_leaf, + /* 01 */ (const void *)&gRootTable_root_df_reg_01_leaf, + /* 02 */ (const void *)&gRootTable_root_df_reg_02_leaf, + /* 03 */ (const void *)&gRootTable_root_df_reg_03_leaf, + /* 04 */ (const void *)&gRootTable_root_df_reg_04_modrmrm, + /* 05 */ (const void *)&gRootTable_root_df_reg_05_leaf, + /* 06 */ (const void *)&gRootTable_root_df_reg_06_leaf, + /* 07 */ (const void *)&gRootTable_root_df_reg_07_modrmrm, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_df_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_df_mem_modrmreg, + /* 01 */ (const void *)&gRootTable_root_df_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[242] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[243] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[244] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[249] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_05_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[372] +}; + +const ND_TABLE_MODRM_RM gRootTable_root_da_reg_05_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_da_reg_05_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_MODRM_REG gRootTable_root_da_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_da_reg_00_leaf, + /* 01 */ (const void *)&gRootTable_root_da_reg_01_leaf, + /* 02 */ (const void *)&gRootTable_root_da_reg_02_leaf, + /* 03 */ (const void *)&gRootTable_root_da_reg_03_leaf, + /* 04 */ NULL, + /* 05 */ (const void *)&gRootTable_root_da_reg_05_modrmrm, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[277] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[279] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[281] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[283] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[285] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[290] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[301] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[303] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_da_mem_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_da_mem_00_leaf, + /* 01 */ (const void *)&gRootTable_root_da_mem_01_leaf, + /* 02 */ (const void *)&gRootTable_root_da_mem_02_leaf, + /* 03 */ (const void *)&gRootTable_root_da_mem_03_leaf, + /* 04 */ (const void *)&gRootTable_root_da_mem_04_leaf, + /* 05 */ (const void *)&gRootTable_root_da_mem_05_leaf, + /* 06 */ (const void *)&gRootTable_root_da_mem_06_leaf, + /* 07 */ (const void *)&gRootTable_root_da_mem_07_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_da_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_da_mem_modrmreg, + /* 01 */ (const void *)&gRootTable_root_da_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[245] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[246] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[247] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[248] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[254] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[323] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[324] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[325] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[327] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[328] +}; + +const ND_TABLE_MODRM_RM gRootTable_root_db_reg_04_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gRootTable_root_db_reg_04_00_leaf, + /* 01 */ (const void *)&gRootTable_root_db_reg_04_01_leaf, + /* 02 */ (const void *)&gRootTable_root_db_reg_04_02_leaf, + /* 03 */ (const void *)&gRootTable_root_db_reg_04_03_leaf, + /* 04 */ (const void *)&gRootTable_root_db_reg_04_04_leaf, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[369] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_db_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_db_reg_00_leaf, + /* 01 */ (const void *)&gRootTable_root_db_reg_01_leaf, + /* 02 */ (const void *)&gRootTable_root_db_reg_02_leaf, + /* 03 */ (const void *)&gRootTable_root_db_reg_03_leaf, + /* 04 */ (const void *)&gRootTable_root_db_reg_04_modrmrm, + /* 05 */ (const void *)&gRootTable_root_db_reg_05_leaf, + /* 06 */ (const void *)&gRootTable_root_db_reg_06_leaf, + /* 07 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[287] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[293] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[295] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[298] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[307] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[350] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_db_mem_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_db_mem_00_leaf, + /* 01 */ (const void *)&gRootTable_root_db_mem_01_leaf, + /* 02 */ (const void *)&gRootTable_root_db_mem_02_leaf, + /* 03 */ (const void *)&gRootTable_root_db_mem_03_leaf, + /* 04 */ NULL, + /* 05 */ (const void *)&gRootTable_root_db_mem_05_leaf, + /* 06 */ NULL, + /* 07 */ (const void *)&gRootTable_root_db_mem_07_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_db_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_db_mem_modrmreg, + /* 01 */ (const void *)&gRootTable_root_db_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[275] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[347] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[352] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[368] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[371] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[375] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_dd_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_dd_reg_00_leaf, + /* 01 */ (const void *)&gRootTable_root_dd_reg_01_leaf, + /* 02 */ (const void *)&gRootTable_root_dd_reg_02_leaf, + /* 03 */ (const void *)&gRootTable_root_dd_reg_03_leaf, + /* 04 */ (const void *)&gRootTable_root_dd_reg_04_leaf, + /* 05 */ (const void *)&gRootTable_root_dd_reg_05_leaf, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[299] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[308] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[329] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[332] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[340] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[346] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[351] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_dd_mem_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_dd_mem_00_leaf, + /* 01 */ (const void *)&gRootTable_root_dd_mem_01_leaf, + /* 02 */ (const void *)&gRootTable_root_dd_mem_02_leaf, + /* 03 */ (const void *)&gRootTable_root_dd_mem_03_leaf, + /* 04 */ (const void *)&gRootTable_root_dd_mem_04_leaf, + /* 05 */ NULL, + /* 06 */ (const void *)&gRootTable_root_dd_mem_06_leaf, + /* 07 */ (const void *)&gRootTable_root_dd_mem_07_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_dd_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_dd_mem_modrmreg, + /* 01 */ (const void *)&gRootTable_root_dd_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_f4_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[388] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_69_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[394] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_6b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[395] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_e4_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[398] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_e5_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[399] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ec_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[400] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ed_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[401] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_40_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[402] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_41_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[403] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_42_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[404] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_43_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[405] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_44_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[406] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_45_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[407] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_46_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[408] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_47_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[409] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_6c_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[414] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_6c_rep_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[415] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_6c_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_6c_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ (const void *)&gRootTable_root_6c_rep_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_6d_None_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[416] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_6d_None_rep_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[417] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_6d_None_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_6d_None_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ (const void *)&gRootTable_root_6d_None_rep_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_6d_ds16_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[422] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_6d_ds16_rep_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[423] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_6d_ds16_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_6d_ds16_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ (const void *)&gRootTable_root_6d_ds16_rep_leaf, + } +}; + +const ND_TABLE_DSIZE gRootTable_root_6d_dsize = +{ + ND_ILUT_DSIZE, + { + /* 00 */ (const void *)&gRootTable_root_6d_None_auxiliary, + /* 01 */ (const void *)&gRootTable_root_6d_ds16_auxiliary, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_cd_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[424] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_f1_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[425] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_cc_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[426] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ce_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[427] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_cf_ds32_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[435] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_cf_ds64_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[436] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_cf_ds16_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[437] +}; + +const ND_TABLE_DSIZE gRootTable_root_cf_dsize = +{ + ND_ILUT_DSIZE, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_cf_ds16_leaf, + /* 02 */ (const void *)&gRootTable_root_cf_ds32_leaf, + /* 03 */ (const void *)&gRootTable_root_cf_ds64_leaf, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_76_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[439] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_72_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[441] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_e3_as16_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[442] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_e3_as32_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[443] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_e3_as64_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[475] +}; + +const ND_TABLE_ASIZE gRootTable_root_e3_asize = +{ + ND_ILUT_ASIZE, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_e3_as16_leaf, + /* 02 */ (const void *)&gRootTable_root_e3_as32_leaf, + /* 03 */ (const void *)&gRootTable_root_e3_as64_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_7c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[445] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_7e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[447] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_e9_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[448] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_eb_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[449] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ea_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[453] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_77_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[456] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_73_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[458] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_7d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[460] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_7f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[462] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_71_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[464] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_7b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[466] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_79_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[468] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_75_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[470] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_70_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[472] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_7a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[474] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_78_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[477] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_74_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[479] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_9f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[549] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_c5_mem_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[554] +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_c5_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_c5_mem_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_8d_mem_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[556] +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_8d_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_8d_mem_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_c9_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[557] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_c4_mem_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[558] +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_c4_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_c4_mem_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ac_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[569] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ac_rep_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[570] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_ac_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_ac_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ (const void *)&gRootTable_root_ac_rep_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds32_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[571] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds32_rep_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[572] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_ad_ds32_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_ad_ds32_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ (const void *)&gRootTable_root_ad_ds32_rep_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds64_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[573] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds64_rep_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[574] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_ad_ds64_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_ad_ds64_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ (const void *)&gRootTable_root_ad_ds64_rep_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds16_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[575] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds16_rep_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[576] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_ad_ds16_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_ad_ds16_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ (const void *)&gRootTable_root_ad_ds16_rep_leaf, + } +}; + +const ND_TABLE_DSIZE gRootTable_root_ad_dsize = +{ + ND_ILUT_DSIZE, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_ad_ds16_auxiliary, + /* 02 */ (const void *)&gRootTable_root_ad_ds32_auxiliary, + /* 03 */ (const void *)&gRootTable_root_ad_ds64_auxiliary, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_e2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[577] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_e0_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[578] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_e1_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[579] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_88_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[608] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_89_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[609] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_8a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[610] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_8b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[611] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_8c_mem_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[612] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_8c_reg_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[613] +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_8c_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_8c_mem_leaf, + /* 01 */ (const void *)&gRootTable_root_8c_reg_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_8e_mem_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[614] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_8e_reg_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[615] +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_8e_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_8e_mem_leaf, + /* 01 */ (const void *)&gRootTable_root_8e_reg_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_a0_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[616] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_a1_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[617] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_a2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[618] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_a3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[619] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_b0_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[620] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_b1_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[621] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_b2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[622] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_b3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[623] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_b4_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[624] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_b5_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[625] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_b6_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[626] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_b7_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[627] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_b8_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[628] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_b9_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[629] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ba_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[630] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_bb_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[631] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_bc_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[632] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_bd_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[633] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_be_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[634] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_bf_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[635] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_c6_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[636] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_c6_mem_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_c6_mem_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_c6_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[636] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_c6_reg_07_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2501] +}; + +const ND_TABLE_MODRM_RM gRootTable_root_c6_reg_07_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gRootTable_root_c6_reg_07_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_MODRM_REG gRootTable_root_c6_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_c6_reg_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ (const void *)&gRootTable_root_c6_reg_07_modrmrm, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_c6_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_c6_mem_modrmreg, + /* 01 */ (const void *)&gRootTable_root_c6_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_c7_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[637] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_c7_mem_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_c7_mem_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_c7_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[637] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_c7_reg_07_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2504] +}; + +const ND_TABLE_MODRM_RM gRootTable_root_c7_reg_07_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gRootTable_root_c7_reg_07_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_MODRM_REG gRootTable_root_c7_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_c7_reg_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ (const void *)&gRootTable_root_c7_reg_07_modrmrm, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_c7_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_c7_mem_modrmreg, + /* 01 */ (const void *)&gRootTable_root_c7_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_a4_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[686] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_a4_rep_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[687] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_a4_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_a4_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ (const void *)&gRootTable_root_a4_rep_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds32_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[690] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds32_rep_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[691] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_a5_ds32_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_a5_ds32_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ (const void *)&gRootTable_root_a5_ds32_rep_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds64_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[694] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds64_rep_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[695] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_a5_ds64_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_a5_ds64_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ (const void *)&gRootTable_root_a5_ds64_rep_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds16_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[698] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds16_rep_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[699] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_a5_ds16_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_a5_ds16_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ (const void *)&gRootTable_root_a5_ds16_rep_leaf, + } +}; + +const ND_TABLE_DSIZE gRootTable_root_a5_dsize = +{ + ND_ILUT_DSIZE, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_a5_ds16_auxiliary, + /* 02 */ (const void *)&gRootTable_root_a5_ds32_auxiliary, + /* 03 */ (const void *)&gRootTable_root_a5_ds64_auxiliary, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_90_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[771] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_90_aF3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[831] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_90_rex_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2507] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_90_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_90_None_leaf, + /* 01 */ (const void *)&gRootTable_root_90_rex_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ (const void *)&gRootTable_root_90_aF3_leaf, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[774] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_09_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[775] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[776] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[777] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[778] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[779] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_e6_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[786] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_e7_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[787] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ee_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[788] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ef_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[789] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_6e_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[790] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_6e_rep_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[791] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_6e_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_6e_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ (const void *)&gRootTable_root_6e_rep_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_6f_None_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[792] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_6f_None_rep_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[793] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_6f_None_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_6f_None_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ (const void *)&gRootTable_root_6f_None_rep_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_6f_ds16_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[794] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_6f_ds16_rep_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[795] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_6f_ds16_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_6f_ds16_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ (const void *)&gRootTable_root_6f_ds16_rep_leaf, + } +}; + +const ND_TABLE_DSIZE gRootTable_root_6f_dsize = +{ + ND_ILUT_DSIZE, + { + /* 00 */ (const void *)&gRootTable_root_6f_None_auxiliary, + /* 01 */ (const void *)&gRootTable_root_6f_ds16_auxiliary, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[963] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_17_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[964] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_1f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[965] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_58_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[966] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_59_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[967] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_5a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[968] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_5b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[969] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_5c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[970] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_5d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[971] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_5e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[972] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_5f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[973] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_8f_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[974] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_8f_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_8f_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_61_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[975] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_9d_ds32_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[977] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_9d_dds64_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[978] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_9d_ds16_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[979] +}; + +const ND_TABLE_DSIZE gRootTable_root_9d_dsize = +{ + ND_ILUT_DSIZE, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_9d_ds16_leaf, + /* 02 */ (const void *)&gRootTable_root_9d_ds32_leaf, + /* 03 */ NULL, + /* 04 */ (const void *)&gRootTable_root_9d_dds64_leaf, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1078] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1079] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_16_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1080] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_1e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1081] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_50_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1082] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_51_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1083] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_52_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1084] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_53_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1085] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_54_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1086] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_55_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1087] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_56_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1088] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_57_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1089] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_68_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1090] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_6a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1091] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_60_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1093] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_9c_ds32_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1094] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_9c_dds64_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1095] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_9c_ds16_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1096] +}; + +const ND_TABLE_DSIZE gRootTable_root_9c_dsize = +{ + ND_ILUT_DSIZE, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_9c_ds16_leaf, + /* 02 */ (const void *)&gRootTable_root_9c_ds32_leaf, + /* 03 */ NULL, + /* 04 */ (const void *)&gRootTable_root_9c_dds64_leaf, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_c0_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1100] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_c0_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1108] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_c0_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1136] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_c0_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1142] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_c0_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1161] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_c0_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1168] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_c0_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1221] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_c0_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1230] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_c0_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_c0_00_leaf, + /* 01 */ (const void *)&gRootTable_root_c0_01_leaf, + /* 02 */ (const void *)&gRootTable_root_c0_02_leaf, + /* 03 */ (const void *)&gRootTable_root_c0_03_leaf, + /* 04 */ (const void *)&gRootTable_root_c0_04_leaf, + /* 05 */ (const void *)&gRootTable_root_c0_05_leaf, + /* 06 */ (const void *)&gRootTable_root_c0_06_leaf, + /* 07 */ (const void *)&gRootTable_root_c0_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_c1_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1101] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_c1_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1109] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_c1_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1137] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_c1_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1143] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_c1_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1162] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_c1_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1169] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_c1_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1222] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_c1_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1231] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_c1_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_c1_00_leaf, + /* 01 */ (const void *)&gRootTable_root_c1_01_leaf, + /* 02 */ (const void *)&gRootTable_root_c1_02_leaf, + /* 03 */ (const void *)&gRootTable_root_c1_03_leaf, + /* 04 */ (const void *)&gRootTable_root_c1_04_leaf, + /* 05 */ (const void *)&gRootTable_root_c1_05_leaf, + /* 06 */ (const void *)&gRootTable_root_c1_06_leaf, + /* 07 */ (const void *)&gRootTable_root_c1_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d0_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1102] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d0_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1110] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d0_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1138] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d0_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1144] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d0_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1163] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d0_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1170] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d0_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1223] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d0_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1232] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_d0_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_d0_00_leaf, + /* 01 */ (const void *)&gRootTable_root_d0_01_leaf, + /* 02 */ (const void *)&gRootTable_root_d0_02_leaf, + /* 03 */ (const void *)&gRootTable_root_d0_03_leaf, + /* 04 */ (const void *)&gRootTable_root_d0_04_leaf, + /* 05 */ (const void *)&gRootTable_root_d0_05_leaf, + /* 06 */ (const void *)&gRootTable_root_d0_06_leaf, + /* 07 */ (const void *)&gRootTable_root_d0_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d1_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1103] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d1_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1111] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d1_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1139] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d1_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1145] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d1_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1164] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d1_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1171] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d1_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1224] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d1_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1233] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_d1_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_d1_00_leaf, + /* 01 */ (const void *)&gRootTable_root_d1_01_leaf, + /* 02 */ (const void *)&gRootTable_root_d1_02_leaf, + /* 03 */ (const void *)&gRootTable_root_d1_03_leaf, + /* 04 */ (const void *)&gRootTable_root_d1_04_leaf, + /* 05 */ (const void *)&gRootTable_root_d1_05_leaf, + /* 06 */ (const void *)&gRootTable_root_d1_06_leaf, + /* 07 */ (const void *)&gRootTable_root_d1_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d2_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1104] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d2_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1112] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d2_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1140] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d2_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1146] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d2_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1165] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d2_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1172] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d2_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1225] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d2_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1234] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_d2_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_d2_00_leaf, + /* 01 */ (const void *)&gRootTable_root_d2_01_leaf, + /* 02 */ (const void *)&gRootTable_root_d2_02_leaf, + /* 03 */ (const void *)&gRootTable_root_d2_03_leaf, + /* 04 */ (const void *)&gRootTable_root_d2_04_leaf, + /* 05 */ (const void *)&gRootTable_root_d2_05_leaf, + /* 06 */ (const void *)&gRootTable_root_d2_06_leaf, + /* 07 */ (const void *)&gRootTable_root_d2_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d3_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1105] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d3_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1113] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d3_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1141] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d3_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1147] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d3_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1166] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d3_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1173] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d3_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1226] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d3_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1235] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_d3_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_d3_00_leaf, + /* 01 */ (const void *)&gRootTable_root_d3_01_leaf, + /* 02 */ (const void *)&gRootTable_root_d3_02_leaf, + /* 03 */ (const void *)&gRootTable_root_d3_03_leaf, + /* 04 */ (const void *)&gRootTable_root_d3_04_leaf, + /* 05 */ (const void *)&gRootTable_root_d3_05_leaf, + /* 06 */ (const void *)&gRootTable_root_d3_06_leaf, + /* 07 */ (const void *)&gRootTable_root_d3_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ca_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1130] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_cb_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1131] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_c2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1132] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_c3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1133] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_9e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1160] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d6_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1167] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_18_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1176] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_19_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1177] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_1a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1178] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_1b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1179] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_1c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1180] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_1d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1181] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ae_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1186] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ae_rep_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1187] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_ae_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_ae_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ (const void *)&gRootTable_root_ae_rep_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_af_ds32_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1188] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_af_ds32_rep_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1189] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_af_ds32_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_af_ds32_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ (const void *)&gRootTable_root_af_ds32_rep_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_af_ds64_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1190] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_af_ds64_rep_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1191] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_af_ds64_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_af_ds64_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ (const void *)&gRootTable_root_af_ds64_rep_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_af_ds16_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1192] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_af_ds16_rep_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1193] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_af_ds16_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_af_ds16_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ (const void *)&gRootTable_root_af_ds16_rep_leaf, + } +}; + +const ND_TABLE_DSIZE gRootTable_root_af_dsize = +{ + ND_ILUT_DSIZE, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_af_ds16_auxiliary, + /* 02 */ (const void *)&gRootTable_root_af_ds32_auxiliary, + /* 03 */ (const void *)&gRootTable_root_af_ds64_auxiliary, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_f9_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1255] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_fd_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1256] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_fb_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1258] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_aa_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1260] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_aa_rep_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1261] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_aa_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_aa_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ (const void *)&gRootTable_root_aa_rep_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds32_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1262] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds32_rep_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1263] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_ab_ds32_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_ab_ds32_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ (const void *)&gRootTable_root_ab_ds32_rep_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds64_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1264] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds64_rep_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1265] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_ab_ds64_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_ab_ds64_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ (const void *)&gRootTable_root_ab_ds64_rep_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds16_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1266] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds16_rep_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1267] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_ab_ds16_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_ab_ds16_None_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ (const void *)&gRootTable_root_ab_ds16_rep_leaf, + } +}; + +const ND_TABLE_DSIZE gRootTable_root_ab_dsize = +{ + ND_ILUT_DSIZE, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_ab_ds16_auxiliary, + /* 02 */ (const void *)&gRootTable_root_ab_ds32_auxiliary, + /* 03 */ (const void *)&gRootTable_root_ab_ds64_auxiliary, + /* 04 */ NULL, + /* 05 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_28_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1271] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_29_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1272] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_2a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1273] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_2b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1274] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_2c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1275] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_2d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1276] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_84_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1299] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_85_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1300] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_a8_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1301] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_a9_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1302] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_9b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2489] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_86_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2505] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_87_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2506] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_91_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2508] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_92_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2509] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_93_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2510] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_94_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2511] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_95_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2512] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_96_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2513] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_97_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2514] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_d7_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2522] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_30_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2523] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_31_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2524] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_32_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2525] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_33_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2526] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_34_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2527] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_35_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2528] +}; + +const ND_TABLE_OPCODE gRootTable_root_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ (const void *)&gRootTable_root_00_leaf, + /* 01 */ (const void *)&gRootTable_root_01_leaf, + /* 02 */ (const void *)&gRootTable_root_02_leaf, + /* 03 */ (const void *)&gRootTable_root_03_leaf, + /* 04 */ (const void *)&gRootTable_root_04_leaf, + /* 05 */ (const void *)&gRootTable_root_05_leaf, + /* 06 */ (const void *)&gRootTable_root_06_leaf, + /* 07 */ (const void *)&gRootTable_root_07_leaf, + /* 08 */ (const void *)&gRootTable_root_08_leaf, + /* 09 */ (const void *)&gRootTable_root_09_leaf, + /* 0a */ (const void *)&gRootTable_root_0a_leaf, + /* 0b */ (const void *)&gRootTable_root_0b_leaf, + /* 0c */ (const void *)&gRootTable_root_0c_leaf, + /* 0d */ (const void *)&gRootTable_root_0d_leaf, + /* 0e */ (const void *)&gRootTable_root_0e_leaf, + /* 0f */ (const void *)&gRootTable_root_0f_opcode, + /* 10 */ (const void *)&gRootTable_root_10_leaf, + /* 11 */ (const void *)&gRootTable_root_11_leaf, + /* 12 */ (const void *)&gRootTable_root_12_leaf, + /* 13 */ (const void *)&gRootTable_root_13_leaf, + /* 14 */ (const void *)&gRootTable_root_14_leaf, + /* 15 */ (const void *)&gRootTable_root_15_leaf, + /* 16 */ (const void *)&gRootTable_root_16_leaf, + /* 17 */ (const void *)&gRootTable_root_17_leaf, + /* 18 */ (const void *)&gRootTable_root_18_leaf, + /* 19 */ (const void *)&gRootTable_root_19_leaf, + /* 1a */ (const void *)&gRootTable_root_1a_leaf, + /* 1b */ (const void *)&gRootTable_root_1b_leaf, + /* 1c */ (const void *)&gRootTable_root_1c_leaf, + /* 1d */ (const void *)&gRootTable_root_1d_leaf, + /* 1e */ (const void *)&gRootTable_root_1e_leaf, + /* 1f */ (const void *)&gRootTable_root_1f_leaf, + /* 20 */ (const void *)&gRootTable_root_20_leaf, + /* 21 */ (const void *)&gRootTable_root_21_leaf, + /* 22 */ (const void *)&gRootTable_root_22_leaf, + /* 23 */ (const void *)&gRootTable_root_23_leaf, + /* 24 */ (const void *)&gRootTable_root_24_leaf, + /* 25 */ (const void *)&gRootTable_root_25_leaf, + /* 26 */ NULL, + /* 27 */ (const void *)&gRootTable_root_27_leaf, + /* 28 */ (const void *)&gRootTable_root_28_leaf, + /* 29 */ (const void *)&gRootTable_root_29_leaf, + /* 2a */ (const void *)&gRootTable_root_2a_leaf, + /* 2b */ (const void *)&gRootTable_root_2b_leaf, + /* 2c */ (const void *)&gRootTable_root_2c_leaf, + /* 2d */ (const void *)&gRootTable_root_2d_leaf, + /* 2e */ NULL, + /* 2f */ (const void *)&gRootTable_root_2f_leaf, + /* 30 */ (const void *)&gRootTable_root_30_leaf, + /* 31 */ (const void *)&gRootTable_root_31_leaf, + /* 32 */ (const void *)&gRootTable_root_32_leaf, + /* 33 */ (const void *)&gRootTable_root_33_leaf, + /* 34 */ (const void *)&gRootTable_root_34_leaf, + /* 35 */ (const void *)&gRootTable_root_35_leaf, + /* 36 */ NULL, + /* 37 */ (const void *)&gRootTable_root_37_leaf, + /* 38 */ (const void *)&gRootTable_root_38_leaf, + /* 39 */ (const void *)&gRootTable_root_39_leaf, + /* 3a */ (const void *)&gRootTable_root_3a_leaf, + /* 3b */ (const void *)&gRootTable_root_3b_leaf, + /* 3c */ (const void *)&gRootTable_root_3c_leaf, + /* 3d */ (const void *)&gRootTable_root_3d_leaf, + /* 3e */ NULL, + /* 3f */ (const void *)&gRootTable_root_3f_leaf, + /* 40 */ (const void *)&gRootTable_root_40_leaf, + /* 41 */ (const void *)&gRootTable_root_41_leaf, + /* 42 */ (const void *)&gRootTable_root_42_leaf, + /* 43 */ (const void *)&gRootTable_root_43_leaf, + /* 44 */ (const void *)&gRootTable_root_44_leaf, + /* 45 */ (const void *)&gRootTable_root_45_leaf, + /* 46 */ (const void *)&gRootTable_root_46_leaf, + /* 47 */ (const void *)&gRootTable_root_47_leaf, + /* 48 */ (const void *)&gRootTable_root_48_leaf, + /* 49 */ (const void *)&gRootTable_root_49_leaf, + /* 4a */ (const void *)&gRootTable_root_4a_leaf, + /* 4b */ (const void *)&gRootTable_root_4b_leaf, + /* 4c */ (const void *)&gRootTable_root_4c_leaf, + /* 4d */ (const void *)&gRootTable_root_4d_leaf, + /* 4e */ (const void *)&gRootTable_root_4e_leaf, + /* 4f */ (const void *)&gRootTable_root_4f_leaf, + /* 50 */ (const void *)&gRootTable_root_50_leaf, + /* 51 */ (const void *)&gRootTable_root_51_leaf, + /* 52 */ (const void *)&gRootTable_root_52_leaf, + /* 53 */ (const void *)&gRootTable_root_53_leaf, + /* 54 */ (const void *)&gRootTable_root_54_leaf, + /* 55 */ (const void *)&gRootTable_root_55_leaf, + /* 56 */ (const void *)&gRootTable_root_56_leaf, + /* 57 */ (const void *)&gRootTable_root_57_leaf, + /* 58 */ (const void *)&gRootTable_root_58_leaf, + /* 59 */ (const void *)&gRootTable_root_59_leaf, + /* 5a */ (const void *)&gRootTable_root_5a_leaf, + /* 5b */ (const void *)&gRootTable_root_5b_leaf, + /* 5c */ (const void *)&gRootTable_root_5c_leaf, + /* 5d */ (const void *)&gRootTable_root_5d_leaf, + /* 5e */ (const void *)&gRootTable_root_5e_leaf, + /* 5f */ (const void *)&gRootTable_root_5f_leaf, + /* 60 */ (const void *)&gRootTable_root_60_leaf, + /* 61 */ (const void *)&gRootTable_root_61_leaf, + /* 62 */ (const void *)&gRootTable_root_62_modrmmod, + /* 63 */ (const void *)&gRootTable_root_63_auxiliary, + /* 64 */ NULL, + /* 65 */ NULL, + /* 66 */ NULL, + /* 67 */ NULL, + /* 68 */ (const void *)&gRootTable_root_68_leaf, + /* 69 */ (const void *)&gRootTable_root_69_leaf, + /* 6a */ (const void *)&gRootTable_root_6a_leaf, + /* 6b */ (const void *)&gRootTable_root_6b_leaf, + /* 6c */ (const void *)&gRootTable_root_6c_auxiliary, + /* 6d */ (const void *)&gRootTable_root_6d_dsize, + /* 6e */ (const void *)&gRootTable_root_6e_auxiliary, + /* 6f */ (const void *)&gRootTable_root_6f_dsize, + /* 70 */ (const void *)&gRootTable_root_70_leaf, + /* 71 */ (const void *)&gRootTable_root_71_leaf, + /* 72 */ (const void *)&gRootTable_root_72_leaf, + /* 73 */ (const void *)&gRootTable_root_73_leaf, + /* 74 */ (const void *)&gRootTable_root_74_leaf, + /* 75 */ (const void *)&gRootTable_root_75_leaf, + /* 76 */ (const void *)&gRootTable_root_76_leaf, + /* 77 */ (const void *)&gRootTable_root_77_leaf, + /* 78 */ (const void *)&gRootTable_root_78_leaf, + /* 79 */ (const void *)&gRootTable_root_79_leaf, + /* 7a */ (const void *)&gRootTable_root_7a_leaf, + /* 7b */ (const void *)&gRootTable_root_7b_leaf, + /* 7c */ (const void *)&gRootTable_root_7c_leaf, + /* 7d */ (const void *)&gRootTable_root_7d_leaf, + /* 7e */ (const void *)&gRootTable_root_7e_leaf, + /* 7f */ (const void *)&gRootTable_root_7f_leaf, + /* 80 */ (const void *)&gRootTable_root_80_modrmreg, + /* 81 */ (const void *)&gRootTable_root_81_modrmreg, + /* 82 */ (const void *)&gRootTable_root_82_modrmreg, + /* 83 */ (const void *)&gRootTable_root_83_modrmreg, + /* 84 */ (const void *)&gRootTable_root_84_leaf, + /* 85 */ (const void *)&gRootTable_root_85_leaf, + /* 86 */ (const void *)&gRootTable_root_86_leaf, + /* 87 */ (const void *)&gRootTable_root_87_leaf, + /* 88 */ (const void *)&gRootTable_root_88_leaf, + /* 89 */ (const void *)&gRootTable_root_89_leaf, + /* 8a */ (const void *)&gRootTable_root_8a_leaf, + /* 8b */ (const void *)&gRootTable_root_8b_leaf, + /* 8c */ (const void *)&gRootTable_root_8c_modrmmod, + /* 8d */ (const void *)&gRootTable_root_8d_modrmmod, + /* 8e */ (const void *)&gRootTable_root_8e_modrmmod, + /* 8f */ (const void *)&gRootTable_root_8f_modrmreg, + /* 90 */ (const void *)&gRootTable_root_90_auxiliary, + /* 91 */ (const void *)&gRootTable_root_91_leaf, + /* 92 */ (const void *)&gRootTable_root_92_leaf, + /* 93 */ (const void *)&gRootTable_root_93_leaf, + /* 94 */ (const void *)&gRootTable_root_94_leaf, + /* 95 */ (const void *)&gRootTable_root_95_leaf, + /* 96 */ (const void *)&gRootTable_root_96_leaf, + /* 97 */ (const void *)&gRootTable_root_97_leaf, + /* 98 */ (const void *)&gRootTable_root_98_dsize, + /* 99 */ (const void *)&gRootTable_root_99_dsize, + /* 9a */ (const void *)&gRootTable_root_9a_leaf, + /* 9b */ (const void *)&gRootTable_root_9b_leaf, + /* 9c */ (const void *)&gRootTable_root_9c_dsize, + /* 9d */ (const void *)&gRootTable_root_9d_dsize, + /* 9e */ (const void *)&gRootTable_root_9e_leaf, + /* 9f */ (const void *)&gRootTable_root_9f_leaf, + /* a0 */ (const void *)&gRootTable_root_a0_leaf, + /* a1 */ (const void *)&gRootTable_root_a1_leaf, + /* a2 */ (const void *)&gRootTable_root_a2_leaf, + /* a3 */ (const void *)&gRootTable_root_a3_leaf, + /* a4 */ (const void *)&gRootTable_root_a4_auxiliary, + /* a5 */ (const void *)&gRootTable_root_a5_dsize, + /* a6 */ (const void *)&gRootTable_root_a6_auxiliary, + /* a7 */ (const void *)&gRootTable_root_a7_dsize, + /* a8 */ (const void *)&gRootTable_root_a8_leaf, + /* a9 */ (const void *)&gRootTable_root_a9_leaf, + /* aa */ (const void *)&gRootTable_root_aa_auxiliary, + /* ab */ (const void *)&gRootTable_root_ab_dsize, + /* ac */ (const void *)&gRootTable_root_ac_auxiliary, + /* ad */ (const void *)&gRootTable_root_ad_dsize, + /* ae */ (const void *)&gRootTable_root_ae_auxiliary, + /* af */ (const void *)&gRootTable_root_af_dsize, + /* b0 */ (const void *)&gRootTable_root_b0_leaf, + /* b1 */ (const void *)&gRootTable_root_b1_leaf, + /* b2 */ (const void *)&gRootTable_root_b2_leaf, + /* b3 */ (const void *)&gRootTable_root_b3_leaf, + /* b4 */ (const void *)&gRootTable_root_b4_leaf, + /* b5 */ (const void *)&gRootTable_root_b5_leaf, + /* b6 */ (const void *)&gRootTable_root_b6_leaf, + /* b7 */ (const void *)&gRootTable_root_b7_leaf, + /* b8 */ (const void *)&gRootTable_root_b8_leaf, + /* b9 */ (const void *)&gRootTable_root_b9_leaf, + /* ba */ (const void *)&gRootTable_root_ba_leaf, + /* bb */ (const void *)&gRootTable_root_bb_leaf, + /* bc */ (const void *)&gRootTable_root_bc_leaf, + /* bd */ (const void *)&gRootTable_root_bd_leaf, + /* be */ (const void *)&gRootTable_root_be_leaf, + /* bf */ (const void *)&gRootTable_root_bf_leaf, + /* c0 */ (const void *)&gRootTable_root_c0_modrmreg, + /* c1 */ (const void *)&gRootTable_root_c1_modrmreg, + /* c2 */ (const void *)&gRootTable_root_c2_leaf, + /* c3 */ (const void *)&gRootTable_root_c3_leaf, + /* c4 */ (const void *)&gRootTable_root_c4_modrmmod, + /* c5 */ (const void *)&gRootTable_root_c5_modrmmod, + /* c6 */ (const void *)&gRootTable_root_c6_modrmmod, + /* c7 */ (const void *)&gRootTable_root_c7_modrmmod, + /* c8 */ (const void *)&gRootTable_root_c8_leaf, + /* c9 */ (const void *)&gRootTable_root_c9_leaf, + /* ca */ (const void *)&gRootTable_root_ca_leaf, + /* cb */ (const void *)&gRootTable_root_cb_leaf, + /* cc */ (const void *)&gRootTable_root_cc_leaf, + /* cd */ (const void *)&gRootTable_root_cd_leaf, + /* ce */ (const void *)&gRootTable_root_ce_leaf, + /* cf */ (const void *)&gRootTable_root_cf_dsize, + /* d0 */ (const void *)&gRootTable_root_d0_modrmreg, + /* d1 */ (const void *)&gRootTable_root_d1_modrmreg, + /* d2 */ (const void *)&gRootTable_root_d2_modrmreg, + /* d3 */ (const void *)&gRootTable_root_d3_modrmreg, + /* d4 */ (const void *)&gRootTable_root_d4_leaf, + /* d5 */ (const void *)&gRootTable_root_d5_leaf, + /* d6 */ (const void *)&gRootTable_root_d6_leaf, + /* d7 */ (const void *)&gRootTable_root_d7_leaf, + /* d8 */ (const void *)&gRootTable_root_d8_modrmmod, + /* d9 */ (const void *)&gRootTable_root_d9_modrmmod, + /* da */ (const void *)&gRootTable_root_da_modrmmod, + /* db */ (const void *)&gRootTable_root_db_modrmmod, + /* dc */ (const void *)&gRootTable_root_dc_modrmmod, + /* dd */ (const void *)&gRootTable_root_dd_modrmmod, + /* de */ (const void *)&gRootTable_root_de_modrmmod, + /* df */ (const void *)&gRootTable_root_df_modrmmod, + /* e0 */ (const void *)&gRootTable_root_e0_leaf, + /* e1 */ (const void *)&gRootTable_root_e1_leaf, + /* e2 */ (const void *)&gRootTable_root_e2_leaf, + /* e3 */ (const void *)&gRootTable_root_e3_asize, + /* e4 */ (const void *)&gRootTable_root_e4_leaf, + /* e5 */ (const void *)&gRootTable_root_e5_leaf, + /* e6 */ (const void *)&gRootTable_root_e6_leaf, + /* e7 */ (const void *)&gRootTable_root_e7_leaf, + /* e8 */ (const void *)&gRootTable_root_e8_leaf, + /* e9 */ (const void *)&gRootTable_root_e9_leaf, + /* ea */ (const void *)&gRootTable_root_ea_leaf, + /* eb */ (const void *)&gRootTable_root_eb_leaf, + /* ec */ (const void *)&gRootTable_root_ec_leaf, + /* ed */ (const void *)&gRootTable_root_ed_leaf, + /* ee */ (const void *)&gRootTable_root_ee_leaf, + /* ef */ (const void *)&gRootTable_root_ef_leaf, + /* f0 */ NULL, + /* f1 */ (const void *)&gRootTable_root_f1_leaf, + /* f2 */ NULL, + /* f3 */ NULL, + /* f4 */ (const void *)&gRootTable_root_f4_leaf, + /* f5 */ (const void *)&gRootTable_root_f5_leaf, + /* f6 */ (const void *)&gRootTable_root_f6_modrmreg, + /* f7 */ (const void *)&gRootTable_root_f7_modrmreg, + /* f8 */ (const void *)&gRootTable_root_f8_leaf, + /* f9 */ (const void *)&gRootTable_root_f9_leaf, + /* fa */ (const void *)&gRootTable_root_fa_leaf, + /* fb */ (const void *)&gRootTable_root_fb_leaf, + /* fc */ (const void *)&gRootTable_root_fc_leaf, + /* fd */ (const void *)&gRootTable_root_fd_leaf, + /* fe */ (const void *)&gRootTable_root_fe_modrmreg, + /* ff */ (const void *)&gRootTable_root_ff_modrmmod, + } +}; + +const PND_TABLE gRootTable = (const PND_TABLE)&gRootTable_root_opcode; + + +#endif + diff --git a/bddisasm/include/table_vex.h b/bddisasm/include/table_vex.h new file mode 100644 index 0000000..0fd4377 --- /dev/null +++ b/bddisasm/include/table_vex.h @@ -0,0 +1,11644 @@ +#ifndef _TABLE_VEX_H_ +#define _TABLE_VEX_H_ + +const ND_TABLE_INSTRUCTION gVexTable_root_02_f2_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[49] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_f2_00_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_f2_00_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_f2_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_02_f2_00_l, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[55] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_f7_00_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_f7_00_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1174] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_f7_02_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_f7_02_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1229] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_f7_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_f7_01_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_03_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1238] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_f7_03_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_f7_03_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_f7_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_02_f7_00_l, + /* 01 */ (const void *)&gVexTable_root_02_f7_01_l, + /* 02 */ (const void *)&gVexTable_root_02_f7_02_l, + /* 03 */ (const void *)&gVexTable_root_02_f7_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_f3_00_03_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[67] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_f3_00_03_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_f3_00_03_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_f3_00_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[69] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_f3_00_02_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_f3_00_02_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_f3_00_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[70] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_f3_00_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_f3_00_01_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_REG gVexTable_root_02_f3_00_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_f3_00_01_l, + /* 02 */ (const void *)&gVexTable_root_02_f3_00_02_l, + /* 03 */ (const void *)&gVexTable_root_02_f3_00_03_l, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_f3_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_02_f3_00_modrmreg, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_f5_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[98] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_f5_00_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_f5_00_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_f5_03_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[860] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_f5_03_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_f5_03_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_f5_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[861] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_f5_02_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_f5_02_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_f5_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_02_f5_00_l, + /* 01 */ NULL, + /* 02 */ (const void *)&gVexTable_root_02_f5_02_l, + /* 03 */ (const void *)&gVexTable_root_02_f5_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_49_00_mem_00_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[555] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_49_00_mem_00_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_49_00_mem_00_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_02_49_00_mem_00_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_49_00_mem_00_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_REG gVexTable_root_02_49_00_mem_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gVexTable_root_02_49_00_mem_00_l, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_49_00_reg_00_00_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1309] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_49_00_reg_00_00_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_49_00_reg_00_00_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_02_49_00_reg_00_00_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_49_00_reg_00_00_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_RM gVexTable_root_02_49_00_reg_00_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gVexTable_root_02_49_00_reg_00_00_l, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_MODRM_REG gVexTable_root_02_49_00_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gVexTable_root_02_49_00_reg_00_modrmrm, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_49_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_49_00_mem_modrmreg, + /* 01 */ (const void *)&gVexTable_root_02_49_00_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_49_01_mem_00_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1270] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_49_01_mem_00_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_49_01_mem_00_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_02_49_01_mem_00_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_49_01_mem_00_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_REG gVexTable_root_02_49_01_mem_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gVexTable_root_02_49_01_mem_00_l, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_49_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_49_01_mem_modrmreg, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_49_03_reg_00_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1311] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_49_03_reg_00_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_49_03_reg_00_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_02_49_03_reg_00_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_49_03_reg_00_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_RM gVexTable_root_02_49_03_reg_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gVexTable_root_02_49_03_reg_00_l, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_49_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_49_03_reg_modrmrm, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_49_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_02_49_00_modrmmod, + /* 01 */ (const void *)&gVexTable_root_02_49_01_modrmmod, + /* 02 */ NULL, + /* 03 */ (const void *)&gVexTable_root_02_49_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_f6_03_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[716] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_f6_03_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_f6_03_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_f6_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ (const void *)&gVexTable_root_02_f6_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_5c_02_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1294] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_5c_02_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_5c_02_reg_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_02_5c_02_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_5c_02_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_5c_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_5c_02_reg_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_5c_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gVexTable_root_02_5c_02_modrmmod, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_03_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1295] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_5e_03_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_5e_03_reg_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_02_5e_03_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_5e_03_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_5e_03_reg_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_02_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1296] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_5e_02_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_5e_02_reg_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_02_5e_02_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_5e_02_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_5e_02_reg_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_01_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1297] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_5e_01_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_5e_01_reg_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_02_5e_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_5e_01_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_5e_01_reg_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_00_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1298] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_5e_00_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_5e_00_reg_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_02_5e_00_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_5e_00_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_5e_00_reg_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_5e_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_02_5e_00_modrmmod, + /* 01 */ (const void *)&gVexTable_root_02_5e_01_modrmmod, + /* 02 */ (const void *)&gVexTable_root_02_5e_02_modrmmod, + /* 03 */ (const void *)&gVexTable_root_02_5e_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_4b_03_mem_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1307] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_4b_03_mem_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_4b_03_mem_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_02_4b_03_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_4b_03_mem_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_4b_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_4b_03_mem_l, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_4b_01_mem_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1308] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_4b_01_mem_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_4b_01_mem_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_02_4b_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_4b_01_mem_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_4b_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_4b_01_mem_l, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_4b_02_mem_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1310] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_4b_02_mem_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_4b_02_mem_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_02_4b_02_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_4b_02_mem_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_4b_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_4b_02_mem_l, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_4b_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_4b_01_modrmmod, + /* 02 */ (const void *)&gVexTable_root_02_4b_02_modrmmod, + /* 03 */ (const void *)&gVexTable_root_02_4b_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_de_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1342] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_de_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_de_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_df_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1344] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_df_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_df_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_dc_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1346] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_dc_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_dc_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_dd_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1348] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_dd_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_dd_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_db_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1349] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_db_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_db_01_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_db_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_db_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_1a_01_mem_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1367] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_1a_01_mem_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_1a_01_mem_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_02_1a_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_1a_01_mem_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_1a_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_1a_01_mem_l, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_1a_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_1a_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_5a_01_mem_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1373] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_5a_01_mem_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_5a_01_mem_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_02_5a_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_5a_01_mem_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_5a_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_5a_01_mem_l, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_5a_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_5a_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_19_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1380] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_19_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_19_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_19_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_19_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_18_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1382] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_18_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_18_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_18_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_18_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_13_01_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1413] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_13_01_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_13_01_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_13_01_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1414] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_13_01_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_13_01_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_02_13_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_13_01_00_w, + /* 01 */ (const void *)&gVexTable_root_02_13_01_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_13_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_13_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_98_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1503] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_98_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1505] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_98_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_98_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_98_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_98_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_98_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_99_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1507] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_99_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1509] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_99_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_99_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_99_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_99_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_99_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_a8_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1511] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_a8_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1513] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_a8_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_a8_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_a8_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_a8_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_a8_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_a9_01_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1515] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_a9_01_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1517] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_a9_01_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_a9_01_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_a9_01_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_02_a9_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_a9_01_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_a9_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_a9_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_b8_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1519] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_b8_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1521] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_b8_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_b8_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_b8_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_b8_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_b8_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_b9_01_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1523] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_b9_01_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1525] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_b9_01_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_b9_01_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_b9_01_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_02_b9_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_b9_01_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_b9_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_b9_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_96_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1535] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_96_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1537] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_96_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_96_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_96_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_96_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_96_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_a6_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1539] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_a6_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1541] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_a6_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_a6_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_a6_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_a6_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_a6_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_b6_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1543] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_b6_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1545] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_b6_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_b6_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_b6_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_b6_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_b6_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_9a_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1551] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_9a_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1553] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_9a_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_9a_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_9a_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_9a_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_9a_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_9b_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1555] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_9b_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1557] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_9b_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_9b_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_9b_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_9b_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_9b_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_aa_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1559] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_aa_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1561] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_aa_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_aa_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_aa_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_aa_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_aa_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_ab_01_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1563] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_ab_01_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1565] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_ab_01_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_ab_01_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_ab_01_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_02_ab_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_ab_01_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_ab_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_ab_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_ba_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1567] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_ba_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1569] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_ba_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_ba_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_ba_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_ba_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_ba_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_bb_01_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1571] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_bb_01_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1573] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_bb_01_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_bb_01_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_bb_01_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_02_bb_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_bb_01_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_bb_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_bb_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_97_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1575] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_97_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1577] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_97_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_97_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_97_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_97_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_97_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_a7_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1579] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_a7_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1581] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_a7_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_a7_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_a7_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_a7_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_a7_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_b7_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1583] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_b7_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1585] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_b7_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_b7_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_b7_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_b7_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_b7_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_9c_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1599] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_9c_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1601] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_9c_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_9c_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_9c_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_9c_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_9c_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_9d_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1603] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_9d_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1605] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_9d_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_9d_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_9d_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_9d_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_9d_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_ac_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1607] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_ac_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1609] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_ac_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_ac_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_ac_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_ac_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_ac_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_ad_01_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1611] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_ad_01_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1613] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_ad_01_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_ad_01_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_ad_01_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_02_ad_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_ad_01_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_ad_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_ad_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_bc_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1615] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_bc_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1617] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_bc_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_bc_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_bc_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_bc_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_bc_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_bd_01_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1619] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_bd_01_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1621] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_bd_01_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_bd_01_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_bd_01_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_02_bd_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_bd_01_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_bd_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_bd_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_9e_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1631] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_9e_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1633] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_9e_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_9e_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_9e_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_9e_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_9e_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_9f_01_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1635] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_9f_01_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1637] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_9f_01_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_9f_01_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_9f_01_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_02_9f_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_9f_01_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_9f_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_9f_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_ae_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1639] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_ae_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1641] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_ae_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_ae_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_ae_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_ae_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_ae_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_af_01_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1643] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_af_01_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1645] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_af_01_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_af_01_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_af_01_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_02_af_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_af_01_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_af_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_af_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_be_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1647] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_be_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1649] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_be_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_be_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_be_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_be_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_be_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_bf_01_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1651] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_bf_01_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1653] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_bf_01_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_bf_01_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_bf_01_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_02_bf_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_bf_01_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_bf_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_bf_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_92_01_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1671] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_92_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1673] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_92_01_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_92_01_mem_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_92_01_mem_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_92_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_92_01_mem_w, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_92_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_92_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_93_01_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1683] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_93_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1685] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_93_01_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_93_01_mem_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_93_01_mem_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_93_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_93_01_mem_w, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_93_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_93_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_cf_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1699] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_cf_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_cf_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_cf_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_cf_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_2d_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1721] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_2d_01_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_2d_01_mem_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_2d_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_2d_01_mem_w, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_2d_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_2d_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_2f_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1722] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_2f_01_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_2f_01_mem_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_2f_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_2f_01_mem_w, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_2f_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_2f_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_2c_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1723] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_2c_01_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_2c_01_mem_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_2c_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_2c_01_mem_w, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_2c_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_2c_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_2e_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1724] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_2e_01_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_2e_01_mem_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_2e_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_2e_01_mem_w, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_2e_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_2e_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_2a_01_mem_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1807] +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_2a_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_2a_01_mem_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_2a_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_2a_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_1c_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1875] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_1c_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_1c_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_1e_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1877] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_1e_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_1e_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_1d_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1880] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_1d_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_1d_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_2b_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1886] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_2b_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_2b_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_78_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1926] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_78_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_78_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_78_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_78_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_58_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1929] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_58_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_58_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_58_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_58_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_59_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1934] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_59_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_59_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_59_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_59_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_79_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1937] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_79_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_79_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_79_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_79_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_29_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1949] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_29_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_29_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_37_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1959] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_37_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_37_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_36_01_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1992] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_36_01_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_36_01_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_02_36_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_36_01_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_36_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_36_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_0d_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2001] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_0d_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_0d_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_0d_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_0d_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_0c_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2005] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_0c_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_0c_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_0c_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_0c_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_16_01_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2017] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_16_01_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_16_01_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_02_16_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_16_01_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_16_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_16_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_90_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2047] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_90_01_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2049] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_90_01_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_90_01_mem_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_90_01_mem_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_90_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_90_01_mem_w, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_90_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_90_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_91_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2051] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_91_01_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2053] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_91_01_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_91_01_mem_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_91_01_mem_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_91_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_91_01_mem_w, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_91_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_91_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_02_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2057] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_02_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_02_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_03_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2059] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_03_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_03_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2066] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_01_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_01_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_41_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2069] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_41_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_41_01_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_41_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_41_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_06_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2071] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_06_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_06_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_07_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2073] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_07_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_07_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_05_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2074] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_05_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_05_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_04_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2105] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_04_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_04_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_8c_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2108] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_8c_01_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2110] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_8c_01_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_8c_01_mem_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_8c_01_mem_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_8c_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_8c_01_mem_w, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_8c_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_8c_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_8e_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2109] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_8e_01_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2111] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_8e_01_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_8e_01_mem_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_8e_01_mem_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_8e_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_8e_01_mem_w, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_8e_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_8e_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_3c_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2113] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_3c_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_3c_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_3d_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2115] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_3d_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_3d_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_3f_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2122] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_3f_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_3f_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_3e_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2125] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_3e_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_3e_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_38_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2127] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_38_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_38_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_39_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2129] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_39_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_39_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_3b_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2136] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_3b_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_3b_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_3a_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2139] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_3a_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_3a_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_21_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2160] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_21_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2161] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_21_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_21_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_21_01_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_21_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_21_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_22_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2163] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_22_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2164] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_22_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_22_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_22_01_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_22_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_22_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_20_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2166] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_20_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2167] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_20_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_20_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_20_01_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_20_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_20_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_25_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2169] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_25_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2170] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_25_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_25_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_25_01_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_25_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_25_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_23_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2172] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_23_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2173] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_23_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_23_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_23_01_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_23_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_23_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_24_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2175] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_24_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2176] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_24_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_24_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_24_01_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_24_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_24_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_31_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2186] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_31_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2187] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_31_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_31_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_31_01_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_31_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_31_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_32_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2189] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_32_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2190] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_32_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_32_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_32_01_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_32_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_32_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_30_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2192] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_30_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2193] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_30_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_30_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_30_01_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_30_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_30_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_35_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2195] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_35_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2196] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_35_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_35_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_35_01_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_35_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_35_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_33_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2198] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_33_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2199] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_33_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_33_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_33_01_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_33_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_33_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_34_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2201] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_34_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2202] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_34_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_34_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_34_01_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_34_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_34_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_28_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2204] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_28_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_28_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_0b_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2206] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_0b_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_0b_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_40_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2212] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_40_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_40_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2283] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_00_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_00_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_08_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2291] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_08_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_08_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_0a_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2292] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_0a_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_0a_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_09_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2293] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_09_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_09_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_47_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2305] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_47_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2307] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_47_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_47_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_47_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_47_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_47_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_46_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2320] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_46_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_46_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_46_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_46_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_45_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2338] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_45_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2340] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_45_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_45_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_02_45_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_45_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_45_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_17_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2364] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_17_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_17_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_0f_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2469] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_0f_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_0f_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_0f_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_0f_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_0e_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2470] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_0e_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_0e_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_0e_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_0e_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_OPCODE gVexTable_root_02_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ (const void *)&gVexTable_root_02_00_pp, + /* 01 */ (const void *)&gVexTable_root_02_01_pp, + /* 02 */ (const void *)&gVexTable_root_02_02_pp, + /* 03 */ (const void *)&gVexTable_root_02_03_pp, + /* 04 */ (const void *)&gVexTable_root_02_04_pp, + /* 05 */ (const void *)&gVexTable_root_02_05_pp, + /* 06 */ (const void *)&gVexTable_root_02_06_pp, + /* 07 */ (const void *)&gVexTable_root_02_07_pp, + /* 08 */ (const void *)&gVexTable_root_02_08_pp, + /* 09 */ (const void *)&gVexTable_root_02_09_pp, + /* 0a */ (const void *)&gVexTable_root_02_0a_pp, + /* 0b */ (const void *)&gVexTable_root_02_0b_pp, + /* 0c */ (const void *)&gVexTable_root_02_0c_pp, + /* 0d */ (const void *)&gVexTable_root_02_0d_pp, + /* 0e */ (const void *)&gVexTable_root_02_0e_pp, + /* 0f */ (const void *)&gVexTable_root_02_0f_pp, + /* 10 */ NULL, + /* 11 */ NULL, + /* 12 */ NULL, + /* 13 */ (const void *)&gVexTable_root_02_13_pp, + /* 14 */ NULL, + /* 15 */ NULL, + /* 16 */ (const void *)&gVexTable_root_02_16_pp, + /* 17 */ (const void *)&gVexTable_root_02_17_pp, + /* 18 */ (const void *)&gVexTable_root_02_18_pp, + /* 19 */ (const void *)&gVexTable_root_02_19_pp, + /* 1a */ (const void *)&gVexTable_root_02_1a_pp, + /* 1b */ NULL, + /* 1c */ (const void *)&gVexTable_root_02_1c_pp, + /* 1d */ (const void *)&gVexTable_root_02_1d_pp, + /* 1e */ (const void *)&gVexTable_root_02_1e_pp, + /* 1f */ NULL, + /* 20 */ (const void *)&gVexTable_root_02_20_pp, + /* 21 */ (const void *)&gVexTable_root_02_21_pp, + /* 22 */ (const void *)&gVexTable_root_02_22_pp, + /* 23 */ (const void *)&gVexTable_root_02_23_pp, + /* 24 */ (const void *)&gVexTable_root_02_24_pp, + /* 25 */ (const void *)&gVexTable_root_02_25_pp, + /* 26 */ NULL, + /* 27 */ NULL, + /* 28 */ (const void *)&gVexTable_root_02_28_pp, + /* 29 */ (const void *)&gVexTable_root_02_29_pp, + /* 2a */ (const void *)&gVexTable_root_02_2a_pp, + /* 2b */ (const void *)&gVexTable_root_02_2b_pp, + /* 2c */ (const void *)&gVexTable_root_02_2c_pp, + /* 2d */ (const void *)&gVexTable_root_02_2d_pp, + /* 2e */ (const void *)&gVexTable_root_02_2e_pp, + /* 2f */ (const void *)&gVexTable_root_02_2f_pp, + /* 30 */ (const void *)&gVexTable_root_02_30_pp, + /* 31 */ (const void *)&gVexTable_root_02_31_pp, + /* 32 */ (const void *)&gVexTable_root_02_32_pp, + /* 33 */ (const void *)&gVexTable_root_02_33_pp, + /* 34 */ (const void *)&gVexTable_root_02_34_pp, + /* 35 */ (const void *)&gVexTable_root_02_35_pp, + /* 36 */ (const void *)&gVexTable_root_02_36_pp, + /* 37 */ (const void *)&gVexTable_root_02_37_pp, + /* 38 */ (const void *)&gVexTable_root_02_38_pp, + /* 39 */ (const void *)&gVexTable_root_02_39_pp, + /* 3a */ (const void *)&gVexTable_root_02_3a_pp, + /* 3b */ (const void *)&gVexTable_root_02_3b_pp, + /* 3c */ (const void *)&gVexTable_root_02_3c_pp, + /* 3d */ (const void *)&gVexTable_root_02_3d_pp, + /* 3e */ (const void *)&gVexTable_root_02_3e_pp, + /* 3f */ (const void *)&gVexTable_root_02_3f_pp, + /* 40 */ (const void *)&gVexTable_root_02_40_pp, + /* 41 */ (const void *)&gVexTable_root_02_41_pp, + /* 42 */ NULL, + /* 43 */ NULL, + /* 44 */ NULL, + /* 45 */ (const void *)&gVexTable_root_02_45_pp, + /* 46 */ (const void *)&gVexTable_root_02_46_pp, + /* 47 */ (const void *)&gVexTable_root_02_47_pp, + /* 48 */ NULL, + /* 49 */ (const void *)&gVexTable_root_02_49_pp, + /* 4a */ NULL, + /* 4b */ (const void *)&gVexTable_root_02_4b_pp, + /* 4c */ NULL, + /* 4d */ NULL, + /* 4e */ NULL, + /* 4f */ NULL, + /* 50 */ NULL, + /* 51 */ NULL, + /* 52 */ NULL, + /* 53 */ NULL, + /* 54 */ NULL, + /* 55 */ NULL, + /* 56 */ NULL, + /* 57 */ NULL, + /* 58 */ (const void *)&gVexTable_root_02_58_pp, + /* 59 */ (const void *)&gVexTable_root_02_59_pp, + /* 5a */ (const void *)&gVexTable_root_02_5a_pp, + /* 5b */ NULL, + /* 5c */ (const void *)&gVexTable_root_02_5c_pp, + /* 5d */ NULL, + /* 5e */ (const void *)&gVexTable_root_02_5e_pp, + /* 5f */ NULL, + /* 60 */ NULL, + /* 61 */ NULL, + /* 62 */ NULL, + /* 63 */ NULL, + /* 64 */ NULL, + /* 65 */ NULL, + /* 66 */ NULL, + /* 67 */ NULL, + /* 68 */ NULL, + /* 69 */ NULL, + /* 6a */ NULL, + /* 6b */ NULL, + /* 6c */ NULL, + /* 6d */ NULL, + /* 6e */ NULL, + /* 6f */ NULL, + /* 70 */ NULL, + /* 71 */ NULL, + /* 72 */ NULL, + /* 73 */ NULL, + /* 74 */ NULL, + /* 75 */ NULL, + /* 76 */ NULL, + /* 77 */ NULL, + /* 78 */ (const void *)&gVexTable_root_02_78_pp, + /* 79 */ (const void *)&gVexTable_root_02_79_pp, + /* 7a */ NULL, + /* 7b */ NULL, + /* 7c */ NULL, + /* 7d */ NULL, + /* 7e */ NULL, + /* 7f */ NULL, + /* 80 */ NULL, + /* 81 */ NULL, + /* 82 */ NULL, + /* 83 */ NULL, + /* 84 */ NULL, + /* 85 */ NULL, + /* 86 */ NULL, + /* 87 */ NULL, + /* 88 */ NULL, + /* 89 */ NULL, + /* 8a */ NULL, + /* 8b */ NULL, + /* 8c */ (const void *)&gVexTable_root_02_8c_pp, + /* 8d */ NULL, + /* 8e */ (const void *)&gVexTable_root_02_8e_pp, + /* 8f */ NULL, + /* 90 */ (const void *)&gVexTable_root_02_90_pp, + /* 91 */ (const void *)&gVexTable_root_02_91_pp, + /* 92 */ (const void *)&gVexTable_root_02_92_pp, + /* 93 */ (const void *)&gVexTable_root_02_93_pp, + /* 94 */ NULL, + /* 95 */ NULL, + /* 96 */ (const void *)&gVexTable_root_02_96_pp, + /* 97 */ (const void *)&gVexTable_root_02_97_pp, + /* 98 */ (const void *)&gVexTable_root_02_98_pp, + /* 99 */ (const void *)&gVexTable_root_02_99_pp, + /* 9a */ (const void *)&gVexTable_root_02_9a_pp, + /* 9b */ (const void *)&gVexTable_root_02_9b_pp, + /* 9c */ (const void *)&gVexTable_root_02_9c_pp, + /* 9d */ (const void *)&gVexTable_root_02_9d_pp, + /* 9e */ (const void *)&gVexTable_root_02_9e_pp, + /* 9f */ (const void *)&gVexTable_root_02_9f_pp, + /* a0 */ NULL, + /* a1 */ NULL, + /* a2 */ NULL, + /* a3 */ NULL, + /* a4 */ NULL, + /* a5 */ NULL, + /* a6 */ (const void *)&gVexTable_root_02_a6_pp, + /* a7 */ (const void *)&gVexTable_root_02_a7_pp, + /* a8 */ (const void *)&gVexTable_root_02_a8_pp, + /* a9 */ (const void *)&gVexTable_root_02_a9_pp, + /* aa */ (const void *)&gVexTable_root_02_aa_pp, + /* ab */ (const void *)&gVexTable_root_02_ab_pp, + /* ac */ (const void *)&gVexTable_root_02_ac_pp, + /* ad */ (const void *)&gVexTable_root_02_ad_pp, + /* ae */ (const void *)&gVexTable_root_02_ae_pp, + /* af */ (const void *)&gVexTable_root_02_af_pp, + /* b0 */ NULL, + /* b1 */ NULL, + /* b2 */ NULL, + /* b3 */ NULL, + /* b4 */ NULL, + /* b5 */ NULL, + /* b6 */ (const void *)&gVexTable_root_02_b6_pp, + /* b7 */ (const void *)&gVexTable_root_02_b7_pp, + /* b8 */ (const void *)&gVexTable_root_02_b8_pp, + /* b9 */ (const void *)&gVexTable_root_02_b9_pp, + /* ba */ (const void *)&gVexTable_root_02_ba_pp, + /* bb */ (const void *)&gVexTable_root_02_bb_pp, + /* bc */ (const void *)&gVexTable_root_02_bc_pp, + /* bd */ (const void *)&gVexTable_root_02_bd_pp, + /* be */ (const void *)&gVexTable_root_02_be_pp, + /* bf */ (const void *)&gVexTable_root_02_bf_pp, + /* c0 */ NULL, + /* c1 */ NULL, + /* c2 */ NULL, + /* c3 */ NULL, + /* c4 */ NULL, + /* c5 */ NULL, + /* c6 */ NULL, + /* c7 */ NULL, + /* c8 */ NULL, + /* c9 */ NULL, + /* ca */ NULL, + /* cb */ NULL, + /* cc */ NULL, + /* cd */ NULL, + /* ce */ NULL, + /* cf */ (const void *)&gVexTable_root_02_cf_pp, + /* d0 */ NULL, + /* d1 */ NULL, + /* d2 */ NULL, + /* d3 */ NULL, + /* d4 */ NULL, + /* d5 */ NULL, + /* d6 */ NULL, + /* d7 */ NULL, + /* d8 */ NULL, + /* d9 */ NULL, + /* da */ NULL, + /* db */ (const void *)&gVexTable_root_02_db_pp, + /* dc */ (const void *)&gVexTable_root_02_dc_pp, + /* dd */ (const void *)&gVexTable_root_02_dd_pp, + /* de */ (const void *)&gVexTable_root_02_de_pp, + /* df */ (const void *)&gVexTable_root_02_df_pp, + /* e0 */ NULL, + /* e1 */ NULL, + /* e2 */ NULL, + /* e3 */ NULL, + /* e4 */ NULL, + /* e5 */ NULL, + /* e6 */ NULL, + /* e7 */ NULL, + /* e8 */ NULL, + /* e9 */ NULL, + /* ea */ NULL, + /* eb */ NULL, + /* ec */ NULL, + /* ed */ NULL, + /* ee */ NULL, + /* ef */ NULL, + /* f0 */ NULL, + /* f1 */ NULL, + /* f2 */ (const void *)&gVexTable_root_02_f2_pp, + /* f3 */ (const void *)&gVexTable_root_02_f3_pp, + /* f4 */ NULL, + /* f5 */ (const void *)&gVexTable_root_02_f5_pp, + /* f6 */ (const void *)&gVexTable_root_02_f6_pp, + /* f7 */ (const void *)&gVexTable_root_02_f7_pp, + /* f8 */ NULL, + /* f9 */ NULL, + /* fa */ NULL, + /* fb */ NULL, + /* fc */ NULL, + /* fd */ NULL, + /* fe */ NULL, + /* ff */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_03_mem_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[111] +}; + +const ND_TABLE_MODRM_REG gVexTable_root_01_ae_03_mem_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ (const void *)&gVexTable_root_01_ae_03_mem_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_03_reg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1249] +}; + +const ND_TABLE_MODRM_REG gVexTable_root_01_ae_03_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ (const void *)&gVexTable_root_01_ae_03_reg_06_leaf, + /* 07 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_ae_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_01_ae_03_mem_modrmreg, + /* 01 */ (const void *)&gVexTable_root_01_ae_03_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_02_mem_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[112] +}; + +const ND_TABLE_MODRM_REG gVexTable_root_01_ae_02_mem_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ (const void *)&gVexTable_root_01_ae_02_mem_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_02_reg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[210] +}; + +const ND_TABLE_MODRM_REG gVexTable_root_01_ae_02_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ (const void *)&gVexTable_root_01_ae_02_reg_06_leaf, + /* 07 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_ae_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_01_ae_02_mem_modrmreg, + /* 01 */ (const void *)&gVexTable_root_01_ae_02_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_00_mem_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1719] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_00_mem_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2460] +}; + +const ND_TABLE_MODRM_REG gVexTable_root_01_ae_00_mem_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gVexTable_root_01_ae_00_mem_02_leaf, + /* 03 */ (const void *)&gVexTable_root_01_ae_00_mem_03_leaf, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_ae_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_01_ae_00_mem_modrmreg, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_ae_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_ae_00_modrmmod, + /* 01 */ NULL, + /* 02 */ (const void *)&gVexTable_root_01_ae_02_modrmmod, + /* 03 */ (const void *)&gVexTable_root_01_ae_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_4a_01_reg_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[480] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_4a_01_reg_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[481] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_4a_01_reg_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_4a_01_reg_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_4a_01_reg_01_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_4a_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_4a_01_reg_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_4a_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_4a_01_reg_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_4a_00_reg_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[482] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_4a_00_reg_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[483] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_4a_00_reg_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_4a_00_reg_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_4a_00_reg_01_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_4a_00_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_4a_00_reg_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_4a_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_4a_00_reg_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_4a_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_4a_00_modrmmod, + /* 01 */ (const void *)&gVexTable_root_01_4a_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_41_01_reg_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[484] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_41_01_reg_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[485] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_41_01_reg_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_41_01_reg_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_41_01_reg_01_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_41_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_41_01_reg_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_41_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_41_01_reg_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_41_00_reg_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[490] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_41_00_reg_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[491] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_41_00_reg_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_41_00_reg_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_41_00_reg_01_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_41_00_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_41_00_reg_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_41_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_41_00_reg_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_41_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_41_00_modrmmod, + /* 01 */ (const void *)&gVexTable_root_01_41_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_42_01_reg_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[486] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_42_01_reg_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[487] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_42_01_reg_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_42_01_reg_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_42_01_reg_01_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_42_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_42_01_reg_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_42_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_42_01_reg_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_42_00_reg_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[488] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_42_00_reg_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[489] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_42_00_reg_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_42_00_reg_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_42_00_reg_01_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_42_00_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_42_00_reg_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_42_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_42_00_reg_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_42_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_42_00_modrmmod, + /* 01 */ (const void *)&gVexTable_root_01_42_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_48_00_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[492] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_48_00_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_48_00_reg_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_48_00_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_48_00_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_48_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_48_00_reg_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_48_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_48_00_modrmmod, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_49_00_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[493] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_49_00_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_49_00_reg_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_49_00_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_49_00_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_49_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_49_00_reg_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_49_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_49_00_modrmmod, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_90_01_mem_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[494] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_90_01_mem_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[499] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_90_01_mem_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_90_01_mem_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_90_01_mem_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_90_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_90_01_mem_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_90_01_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[495] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_90_01_reg_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[500] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_90_01_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_90_01_reg_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_90_01_reg_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_90_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_90_01_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_90_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_01_90_01_mem_l, + /* 01 */ (const void *)&gVexTable_root_01_90_01_reg_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_90_00_mem_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[504] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_90_00_mem_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[509] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_90_00_mem_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_90_00_mem_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_90_00_mem_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_90_00_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_90_00_mem_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_90_00_reg_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[505] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_90_00_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[510] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_90_00_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_90_00_reg_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_90_00_reg_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_90_00_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_90_00_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_90_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_01_90_00_mem_l, + /* 01 */ (const void *)&gVexTable_root_01_90_00_reg_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_90_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_90_00_modrmmod, + /* 01 */ (const void *)&gVexTable_root_01_90_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_91_01_mem_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[496] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_91_01_mem_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[501] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_91_01_mem_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_91_01_mem_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_91_01_mem_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_91_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_91_01_mem_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_91_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_01_91_01_mem_l, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_91_00_mem_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[506] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_91_00_mem_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[511] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_91_00_mem_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_91_00_mem_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_91_00_mem_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_91_00_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_91_00_mem_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_91_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_01_91_00_mem_l, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_91_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_91_00_modrmmod, + /* 01 */ (const void *)&gVexTable_root_01_91_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_92_01_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[497] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_92_01_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_92_01_reg_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_92_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_92_01_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_92_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_92_01_reg_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_92_03_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[502] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_92_03_reg_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[507] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_92_03_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_92_03_reg_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_92_03_reg_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_92_03_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_92_03_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_92_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_92_03_reg_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_92_00_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[512] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_92_00_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_92_00_reg_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_92_00_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_92_00_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_92_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_92_00_reg_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_92_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_92_00_modrmmod, + /* 01 */ (const void *)&gVexTable_root_01_92_01_modrmmod, + /* 02 */ NULL, + /* 03 */ (const void *)&gVexTable_root_01_92_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_93_01_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[498] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_93_01_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_93_01_reg_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_93_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_93_01_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_93_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_93_01_reg_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_93_03_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[503] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_93_03_reg_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[508] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_93_03_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_93_03_reg_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_93_03_reg_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_93_03_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_93_03_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_93_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_93_03_reg_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_93_00_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[513] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_93_00_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_93_00_reg_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_93_00_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_93_00_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_93_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_93_00_reg_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_93_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_93_00_modrmmod, + /* 01 */ (const void *)&gVexTable_root_01_93_01_modrmmod, + /* 02 */ NULL, + /* 03 */ (const void *)&gVexTable_root_01_93_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_44_01_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[514] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_44_01_reg_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[515] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_44_01_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_44_01_reg_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_44_01_reg_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_44_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_44_01_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_44_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_44_01_reg_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_44_00_reg_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[516] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_44_00_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[517] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_44_00_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_44_00_reg_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_44_00_reg_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_44_00_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_44_00_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_44_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_44_00_reg_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_44_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_44_00_modrmmod, + /* 01 */ (const void *)&gVexTable_root_01_44_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_45_01_reg_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[518] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_45_01_reg_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[519] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_45_01_reg_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_45_01_reg_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_45_01_reg_01_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_45_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_45_01_reg_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_45_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_45_01_reg_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_45_00_reg_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[520] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_45_00_reg_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[525] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_45_00_reg_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_45_00_reg_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_45_00_reg_01_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_45_00_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_45_00_reg_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_45_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_45_00_reg_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_45_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_45_00_modrmmod, + /* 01 */ (const void *)&gVexTable_root_01_45_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_98_01_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[521] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_98_01_reg_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[522] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_98_01_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_98_01_reg_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_98_01_reg_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_98_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_98_01_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_98_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_98_01_reg_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_98_00_reg_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[523] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_98_00_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[524] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_98_00_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_98_00_reg_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_98_00_reg_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_98_00_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_98_00_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_98_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_98_00_reg_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_98_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_98_00_modrmmod, + /* 01 */ (const void *)&gVexTable_root_01_98_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_99_01_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[534] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_99_01_reg_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[535] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_99_01_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_99_01_reg_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_99_01_reg_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_99_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_99_01_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_99_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_99_01_reg_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_99_00_reg_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[536] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_99_00_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[537] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_99_00_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_99_00_reg_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_99_00_reg_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_99_00_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_99_00_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_99_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_99_00_reg_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_99_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_99_00_modrmmod, + /* 01 */ (const void *)&gVexTable_root_01_99_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_4b_01_reg_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[538] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_4b_01_reg_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_4b_01_reg_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_4b_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_4b_01_reg_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_4b_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_4b_01_reg_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_4b_00_reg_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[539] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_4b_00_reg_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[540] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_4b_00_reg_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_4b_00_reg_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_4b_00_reg_01_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_4b_00_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_4b_00_reg_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_4b_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_4b_00_reg_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_4b_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_4b_00_modrmmod, + /* 01 */ (const void *)&gVexTable_root_01_4b_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_46_01_reg_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[541] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_46_01_reg_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[542] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_46_01_reg_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_46_01_reg_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_46_01_reg_01_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_46_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_46_01_reg_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_46_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_46_01_reg_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_46_00_reg_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[543] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_46_00_reg_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[544] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_46_00_reg_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_46_00_reg_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_46_00_reg_01_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_46_00_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_46_00_reg_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_46_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_46_00_reg_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_46_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_46_00_modrmmod, + /* 01 */ (const void *)&gVexTable_root_01_46_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_47_01_reg_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[545] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_47_01_reg_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[546] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_47_01_reg_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_47_01_reg_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_47_01_reg_01_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_47_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_47_01_reg_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_47_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_47_01_reg_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_47_00_reg_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[547] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_47_00_reg_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[548] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_47_00_reg_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_47_00_reg_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_47_00_reg_01_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_47_00_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_47_00_reg_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_47_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_47_00_reg_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_47_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_47_00_modrmmod, + /* 01 */ (const void *)&gVexTable_root_01_47_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_58_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1332] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_58_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1334] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_58_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1336] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_58_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1338] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_58_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_58_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_58_01_leaf, + /* 02 */ (const void *)&gVexTable_root_01_58_02_leaf, + /* 03 */ (const void *)&gVexTable_root_01_58_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_d0_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1339] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_d0_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1340] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_d0_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_d0_01_leaf, + /* 02 */ NULL, + /* 03 */ (const void *)&gVexTable_root_01_d0_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_55_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1354] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_55_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1356] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_55_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_55_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_55_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_54_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1358] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_54_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1360] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_54_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_54_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_54_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1384] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1387] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1389] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1390] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_c2_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_c2_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_c2_01_leaf, + /* 02 */ (const void *)&gVexTable_root_01_c2_02_leaf, + /* 03 */ (const void *)&gVexTable_root_01_c2_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_2f_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1392] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_2f_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1394] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_2f_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_2f_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_2f_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1398] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_02_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1399] +}; + +const ND_TABLE_VEX_L gVexTable_root_01_e6_02_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_e6_02_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_e6_02_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1405] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1444] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_e6_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_e6_01_leaf, + /* 02 */ (const void *)&gVexTable_root_01_e6_02_l, + /* 03 */ (const void *)&gVexTable_root_01_e6_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_5b_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1401] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_5b_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1416] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_5b_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1449] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_5b_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_5b_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_5b_01_leaf, + /* 02 */ (const void *)&gVexTable_root_01_5b_02_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1407] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1408] +}; + +const ND_TABLE_VEX_L gVexTable_root_01_5a_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_5a_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_5a_01_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1418] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1419] +}; + +const ND_TABLE_VEX_L gVexTable_root_01_5a_00_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_5a_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_5a_00_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1431] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1439] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_5a_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_5a_00_l, + /* 01 */ (const void *)&gVexTable_root_01_5a_01_l, + /* 02 */ (const void *)&gVexTable_root_01_5a_02_leaf, + /* 03 */ (const void *)&gVexTable_root_01_5a_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_2d_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1429] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_2d_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1441] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_2d_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gVexTable_root_01_2d_02_leaf, + /* 03 */ (const void *)&gVexTable_root_01_2d_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_2a_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1435] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_2a_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1437] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_2a_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gVexTable_root_01_2a_02_leaf, + /* 03 */ (const void *)&gVexTable_root_01_2a_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_2c_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1454] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_2c_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1457] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_2c_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gVexTable_root_01_2c_02_leaf, + /* 03 */ (const void *)&gVexTable_root_01_2c_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1468] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1470] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1472] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1474] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_5e_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_5e_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_5e_01_leaf, + /* 02 */ (const void *)&gVexTable_root_01_5e_02_leaf, + /* 03 */ (const void *)&gVexTable_root_01_5e_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_7c_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1700] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_7c_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1701] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_7c_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_7c_01_leaf, + /* 02 */ NULL, + /* 03 */ (const void *)&gVexTable_root_01_7c_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_7d_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1702] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_7d_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1703] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_7d_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_7d_01_leaf, + /* 02 */ NULL, + /* 03 */ (const void *)&gVexTable_root_01_7d_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_f0_03_mem_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1718] +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_f0_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_01_f0_03_mem_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_f0_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ (const void *)&gVexTable_root_01_f0_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_f7_01_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1720] +}; + +const ND_TABLE_VEX_L gVexTable_root_01_f7_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_f7_01_reg_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_f7_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_f7_01_reg_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_f7_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_f7_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1726] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1728] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1730] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1732] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_5f_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_5f_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_5f_01_leaf, + /* 02 */ (const void *)&gVexTable_root_01_5f_02_leaf, + /* 03 */ (const void *)&gVexTable_root_01_5f_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1739] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1741] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1743] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1745] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_5d_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_5d_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_5d_01_leaf, + /* 02 */ (const void *)&gVexTable_root_01_5d_02_leaf, + /* 03 */ (const void *)&gVexTable_root_01_5d_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_28_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1751] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_28_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1755] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_28_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_28_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_28_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_29_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1752] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_29_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1756] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_29_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_29_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_29_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_6e_01_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1759] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_6e_01_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1816] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_6e_01_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_6e_01_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_6e_01_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_6e_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_6e_01_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_6e_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_6e_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_7e_01_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1760] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_7e_01_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1817] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_7e_01_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_7e_01_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_7e_01_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_7e_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_7e_01_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_7e_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1818] +}; + +const ND_TABLE_VEX_L gVexTable_root_01_7e_02_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_7e_02_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_7e_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_7e_01_l, + /* 02 */ (const void *)&gVexTable_root_01_7e_02_l, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_12_03_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1764] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_12_03_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1765] +}; + +const ND_TABLE_VEX_L gVexTable_root_01_12_03_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_12_03_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_12_03_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_12_00_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1783] +}; + +const ND_TABLE_VEX_L gVexTable_root_01_12_00_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_12_00_reg_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_12_00_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1800] +}; + +const ND_TABLE_VEX_L gVexTable_root_01_12_00_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_12_00_mem_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_12_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_01_12_00_mem_l, + /* 01 */ (const void *)&gVexTable_root_01_12_00_reg_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_12_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1796] +}; + +const ND_TABLE_VEX_L gVexTable_root_01_12_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_12_01_mem_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_12_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_01_12_01_mem_l, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_12_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1831] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_12_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_12_00_modrmmod, + /* 01 */ (const void *)&gVexTable_root_01_12_01_modrmmod, + /* 02 */ (const void *)&gVexTable_root_01_12_02_leaf, + /* 03 */ (const void *)&gVexTable_root_01_12_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_6f_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1766] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_6f_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1772] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_6f_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_6f_01_leaf, + /* 02 */ (const void *)&gVexTable_root_01_6f_02_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_7f_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1767] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_7f_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1773] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_7f_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_7f_01_leaf, + /* 02 */ (const void *)&gVexTable_root_01_7f_02_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_16_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1786] +}; + +const ND_TABLE_VEX_L gVexTable_root_01_16_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_16_01_mem_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_16_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_01_16_01_mem_l, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_16_00_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1790] +}; + +const ND_TABLE_VEX_L gVexTable_root_01_16_00_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_16_00_mem_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_16_00_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1793] +}; + +const ND_TABLE_VEX_L gVexTable_root_01_16_00_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_16_00_reg_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_16_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_01_16_00_mem_l, + /* 01 */ (const void *)&gVexTable_root_01_16_00_reg_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_16_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1829] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_16_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_16_00_modrmmod, + /* 01 */ (const void *)&gVexTable_root_01_16_01_modrmmod, + /* 02 */ (const void *)&gVexTable_root_01_16_02_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_17_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1787] +}; + +const ND_TABLE_VEX_L gVexTable_root_01_17_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_17_01_mem_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_17_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_01_17_01_mem_l, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_17_00_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1791] +}; + +const ND_TABLE_VEX_L gVexTable_root_01_17_00_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_17_00_mem_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_17_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_01_17_00_mem_l, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_17_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_17_00_modrmmod, + /* 01 */ (const void *)&gVexTable_root_01_17_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_13_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1797] +}; + +const ND_TABLE_VEX_L gVexTable_root_01_13_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_13_01_mem_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_13_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_01_13_01_mem_l, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_13_00_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1801] +}; + +const ND_TABLE_VEX_L gVexTable_root_01_13_00_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_13_00_mem_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_13_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_01_13_00_mem_l, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_13_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_13_00_modrmmod, + /* 01 */ (const void *)&gVexTable_root_01_13_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_50_01_reg_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1802] +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_50_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_50_01_reg_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_50_00_reg_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1803] +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_50_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_50_00_reg_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_50_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_50_00_modrmmod, + /* 01 */ (const void *)&gVexTable_root_01_50_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_e7_01_mem_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1805] +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_e7_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_01_e7_01_mem_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_e7_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_e7_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_2b_01_mem_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1809] +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_2b_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_01_2b_01_mem_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_2b_00_mem_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1811] +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_2b_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_01_2b_00_mem_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_2b_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_2b_00_modrmmod, + /* 01 */ (const void *)&gVexTable_root_01_2b_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_d6_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1819] +}; + +const ND_TABLE_VEX_L gVexTable_root_01_d6_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_d6_01_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_d6_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_d6_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_10_03_reg_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1824] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_10_03_mem_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1825] +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_10_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_01_10_03_mem_leaf, + /* 01 */ (const void *)&gVexTable_root_01_10_03_reg_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_10_02_reg_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1836] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_10_02_mem_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1837] +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_10_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_01_10_02_mem_leaf, + /* 01 */ (const void *)&gVexTable_root_01_10_02_reg_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_10_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1842] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_10_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1846] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_10_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_10_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_10_01_leaf, + /* 02 */ (const void *)&gVexTable_root_01_10_02_modrmmod, + /* 03 */ (const void *)&gVexTable_root_01_10_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_11_03_reg_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1826] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_11_03_mem_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1827] +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_11_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_01_11_03_mem_leaf, + /* 01 */ (const void *)&gVexTable_root_01_11_03_reg_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_11_02_reg_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1838] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_11_02_mem_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1839] +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_11_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_01_11_02_mem_leaf, + /* 01 */ (const void *)&gVexTable_root_01_11_02_reg_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_11_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1843] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_11_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1847] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_11_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_11_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_11_01_leaf, + /* 02 */ (const void *)&gVexTable_root_01_11_02_modrmmod, + /* 03 */ (const void *)&gVexTable_root_01_11_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_59_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1856] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_59_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1858] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_59_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1860] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_59_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1862] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_59_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_59_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_59_01_leaf, + /* 02 */ (const void *)&gVexTable_root_01_59_02_leaf, + /* 03 */ (const void *)&gVexTable_root_01_59_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_56_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1867] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_56_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1869] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_56_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_56_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_56_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_6b_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1882] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_6b_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_6b_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_63_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1884] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_63_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_63_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_67_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1888] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_67_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_67_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_fc_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1890] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_fc_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_fc_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_fe_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1892] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_fe_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_fe_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_d4_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1894] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_d4_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_d4_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_ec_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1896] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_ec_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_ec_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_ed_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1898] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_ed_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_ed_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_dc_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1900] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_dc_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_dc_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_dd_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1902] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_dd_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_dd_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_fd_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1904] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_fd_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_fd_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_db_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1907] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_db_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_db_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_df_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1909] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_df_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_df_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_e0_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1914] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_e0_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_e0_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_e3_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1916] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_e3_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_e3_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_74_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1945] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_74_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_74_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_76_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1947] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_76_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_76_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_75_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1951] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_75_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_75_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_64_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1955] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_64_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_64_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_66_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1957] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_66_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_66_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_65_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1961] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_65_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_65_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_c5_01_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2043] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_c5_01_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_c5_01_reg_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_c5_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_c5_01_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_c5_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_c5_01_reg_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_c5_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_c5_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_c4_01_mem_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2086] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_c4_01_mem_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_c4_01_mem_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_c4_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_c4_01_mem_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_c4_01_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2087] +}; + +const ND_TABLE_VEX_W gVexTable_root_01_c4_01_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_01_c4_01_reg_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_01_c4_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_c4_01_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_c4_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_01_c4_01_mem_l, + /* 01 */ (const void *)&gVexTable_root_01_c4_01_reg_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_c4_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_c4_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_f5_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2107] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_f5_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_f5_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_ee_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2118] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_ee_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_ee_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_de_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2120] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_de_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_de_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_ea_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2132] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_ea_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_ea_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_da_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2134] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_da_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_da_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_d7_01_reg_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2148] +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_d7_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_d7_01_reg_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_d7_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_d7_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_e4_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2208] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_e4_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_e4_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_e5_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2210] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_e5_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_e5_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_d5_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2215] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_d5_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_d5_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_f4_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2218] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_f4_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_f4_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_eb_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2223] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_eb_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_eb_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_f6_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2249] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_f6_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_f6_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_70_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2286] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_70_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2288] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_70_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2290] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_70_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_70_01_leaf, + /* 02 */ (const void *)&gVexTable_root_01_70_02_leaf, + /* 03 */ (const void *)&gVexTable_root_01_70_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_72_01_reg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2296] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_72_01_reg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2315] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_72_01_reg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2329] +}; + +const ND_TABLE_MODRM_REG gVexTable_root_01_72_01_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gVexTable_root_01_72_01_reg_02_leaf, + /* 03 */ NULL, + /* 04 */ (const void *)&gVexTable_root_01_72_01_reg_04_leaf, + /* 05 */ NULL, + /* 06 */ (const void *)&gVexTable_root_01_72_01_reg_06_leaf, + /* 07 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_72_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_72_01_reg_modrmreg, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_72_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_72_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_f2_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2297] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_f2_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_f2_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2299] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2302] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2332] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2335] +}; + +const ND_TABLE_MODRM_REG gVexTable_root_01_73_01_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gVexTable_root_01_73_01_reg_02_leaf, + /* 03 */ (const void *)&gVexTable_root_01_73_01_reg_03_leaf, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ (const void *)&gVexTable_root_01_73_01_reg_06_leaf, + /* 07 */ (const void *)&gVexTable_root_01_73_01_reg_07_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_73_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_73_01_reg_modrmreg, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_73_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_73_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_f3_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2303] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_f3_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_f3_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_71_01_reg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2311] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_71_01_reg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2325] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_71_01_reg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2344] +}; + +const ND_TABLE_MODRM_REG gVexTable_root_01_71_01_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gVexTable_root_01_71_01_reg_02_leaf, + /* 03 */ NULL, + /* 04 */ (const void *)&gVexTable_root_01_71_01_reg_04_leaf, + /* 05 */ NULL, + /* 06 */ (const void *)&gVexTable_root_01_71_01_reg_06_leaf, + /* 07 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_01_71_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_71_01_reg_modrmreg, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_71_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_71_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_f1_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2312] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_f1_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_f1_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_e2_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2316] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_e2_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_e2_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_e1_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2326] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_e1_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_e1_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_d2_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2330] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_d2_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_d2_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_d3_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2336] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_d3_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_d3_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_d1_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2345] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_d1_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_d1_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_f8_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2347] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_f8_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_f8_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_fa_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2349] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_fa_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_fa_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_fb_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2351] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_fb_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_fb_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_e8_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2353] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_e8_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_e8_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_e9_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2355] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_e9_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_e9_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_d8_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2357] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_d8_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_d8_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_d9_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2359] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_d9_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_d9_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_f9_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2361] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_f9_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_f9_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_68_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2374] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_68_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_68_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_6a_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2376] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_6a_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_6a_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_6d_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2378] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_6d_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_6d_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_69_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2380] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_69_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_69_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_60_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2382] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_60_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_60_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_62_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2384] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_62_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_62_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_6c_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2386] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_6c_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_6c_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_61_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2388] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_61_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_61_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_ef_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2389] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_ef_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_ef_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_53_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2404] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_53_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2405] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_53_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_53_00_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gVexTable_root_01_53_02_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_52_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2426] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_52_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2427] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_52_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_52_00_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gVexTable_root_01_52_02_leaf, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_c6_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2449] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_c6_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2451] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_c6_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_c6_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_c6_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_51_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2453] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_51_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2455] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_51_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2457] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_51_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2459] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_51_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_51_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_51_01_leaf, + /* 02 */ (const void *)&gVexTable_root_01_51_02_leaf, + /* 03 */ (const void *)&gVexTable_root_01_51_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2462] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2464] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2466] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2468] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_5c_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_5c_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_5c_01_leaf, + /* 02 */ (const void *)&gVexTable_root_01_5c_02_leaf, + /* 03 */ (const void *)&gVexTable_root_01_5c_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_2e_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2472] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_2e_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2474] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_2e_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_2e_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_2e_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_15_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2476] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_15_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2478] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_15_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_15_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_15_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_14_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2480] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_14_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2482] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_14_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_14_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_14_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_57_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2484] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_57_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2486] +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_57_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_57_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_57_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_77_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2487] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_01_77_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2488] +}; + +const ND_TABLE_VEX_L gVexTable_root_01_77_00_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_01_77_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_01_77_00_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_01_77_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_01_77_00_l, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_OPCODE gVexTable_root_01_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + /* 08 */ NULL, + /* 09 */ NULL, + /* 0a */ NULL, + /* 0b */ NULL, + /* 0c */ NULL, + /* 0d */ NULL, + /* 0e */ NULL, + /* 0f */ NULL, + /* 10 */ (const void *)&gVexTable_root_01_10_pp, + /* 11 */ (const void *)&gVexTable_root_01_11_pp, + /* 12 */ (const void *)&gVexTable_root_01_12_pp, + /* 13 */ (const void *)&gVexTable_root_01_13_pp, + /* 14 */ (const void *)&gVexTable_root_01_14_pp, + /* 15 */ (const void *)&gVexTable_root_01_15_pp, + /* 16 */ (const void *)&gVexTable_root_01_16_pp, + /* 17 */ (const void *)&gVexTable_root_01_17_pp, + /* 18 */ NULL, + /* 19 */ NULL, + /* 1a */ NULL, + /* 1b */ NULL, + /* 1c */ NULL, + /* 1d */ NULL, + /* 1e */ NULL, + /* 1f */ NULL, + /* 20 */ NULL, + /* 21 */ NULL, + /* 22 */ NULL, + /* 23 */ NULL, + /* 24 */ NULL, + /* 25 */ NULL, + /* 26 */ NULL, + /* 27 */ NULL, + /* 28 */ (const void *)&gVexTable_root_01_28_pp, + /* 29 */ (const void *)&gVexTable_root_01_29_pp, + /* 2a */ (const void *)&gVexTable_root_01_2a_pp, + /* 2b */ (const void *)&gVexTable_root_01_2b_pp, + /* 2c */ (const void *)&gVexTable_root_01_2c_pp, + /* 2d */ (const void *)&gVexTable_root_01_2d_pp, + /* 2e */ (const void *)&gVexTable_root_01_2e_pp, + /* 2f */ (const void *)&gVexTable_root_01_2f_pp, + /* 30 */ NULL, + /* 31 */ NULL, + /* 32 */ NULL, + /* 33 */ NULL, + /* 34 */ NULL, + /* 35 */ NULL, + /* 36 */ NULL, + /* 37 */ NULL, + /* 38 */ NULL, + /* 39 */ NULL, + /* 3a */ NULL, + /* 3b */ NULL, + /* 3c */ NULL, + /* 3d */ NULL, + /* 3e */ NULL, + /* 3f */ NULL, + /* 40 */ NULL, + /* 41 */ (const void *)&gVexTable_root_01_41_pp, + /* 42 */ (const void *)&gVexTable_root_01_42_pp, + /* 43 */ NULL, + /* 44 */ (const void *)&gVexTable_root_01_44_pp, + /* 45 */ (const void *)&gVexTable_root_01_45_pp, + /* 46 */ (const void *)&gVexTable_root_01_46_pp, + /* 47 */ (const void *)&gVexTable_root_01_47_pp, + /* 48 */ (const void *)&gVexTable_root_01_48_pp, + /* 49 */ (const void *)&gVexTable_root_01_49_pp, + /* 4a */ (const void *)&gVexTable_root_01_4a_pp, + /* 4b */ (const void *)&gVexTable_root_01_4b_pp, + /* 4c */ NULL, + /* 4d */ NULL, + /* 4e */ NULL, + /* 4f */ NULL, + /* 50 */ (const void *)&gVexTable_root_01_50_pp, + /* 51 */ (const void *)&gVexTable_root_01_51_pp, + /* 52 */ (const void *)&gVexTable_root_01_52_pp, + /* 53 */ (const void *)&gVexTable_root_01_53_pp, + /* 54 */ (const void *)&gVexTable_root_01_54_pp, + /* 55 */ (const void *)&gVexTable_root_01_55_pp, + /* 56 */ (const void *)&gVexTable_root_01_56_pp, + /* 57 */ (const void *)&gVexTable_root_01_57_pp, + /* 58 */ (const void *)&gVexTable_root_01_58_pp, + /* 59 */ (const void *)&gVexTable_root_01_59_pp, + /* 5a */ (const void *)&gVexTable_root_01_5a_pp, + /* 5b */ (const void *)&gVexTable_root_01_5b_pp, + /* 5c */ (const void *)&gVexTable_root_01_5c_pp, + /* 5d */ (const void *)&gVexTable_root_01_5d_pp, + /* 5e */ (const void *)&gVexTable_root_01_5e_pp, + /* 5f */ (const void *)&gVexTable_root_01_5f_pp, + /* 60 */ (const void *)&gVexTable_root_01_60_pp, + /* 61 */ (const void *)&gVexTable_root_01_61_pp, + /* 62 */ (const void *)&gVexTable_root_01_62_pp, + /* 63 */ (const void *)&gVexTable_root_01_63_pp, + /* 64 */ (const void *)&gVexTable_root_01_64_pp, + /* 65 */ (const void *)&gVexTable_root_01_65_pp, + /* 66 */ (const void *)&gVexTable_root_01_66_pp, + /* 67 */ (const void *)&gVexTable_root_01_67_pp, + /* 68 */ (const void *)&gVexTable_root_01_68_pp, + /* 69 */ (const void *)&gVexTable_root_01_69_pp, + /* 6a */ (const void *)&gVexTable_root_01_6a_pp, + /* 6b */ (const void *)&gVexTable_root_01_6b_pp, + /* 6c */ (const void *)&gVexTable_root_01_6c_pp, + /* 6d */ (const void *)&gVexTable_root_01_6d_pp, + /* 6e */ (const void *)&gVexTable_root_01_6e_pp, + /* 6f */ (const void *)&gVexTable_root_01_6f_pp, + /* 70 */ (const void *)&gVexTable_root_01_70_pp, + /* 71 */ (const void *)&gVexTable_root_01_71_pp, + /* 72 */ (const void *)&gVexTable_root_01_72_pp, + /* 73 */ (const void *)&gVexTable_root_01_73_pp, + /* 74 */ (const void *)&gVexTable_root_01_74_pp, + /* 75 */ (const void *)&gVexTable_root_01_75_pp, + /* 76 */ (const void *)&gVexTable_root_01_76_pp, + /* 77 */ (const void *)&gVexTable_root_01_77_pp, + /* 78 */ NULL, + /* 79 */ NULL, + /* 7a */ NULL, + /* 7b */ NULL, + /* 7c */ (const void *)&gVexTable_root_01_7c_pp, + /* 7d */ (const void *)&gVexTable_root_01_7d_pp, + /* 7e */ (const void *)&gVexTable_root_01_7e_pp, + /* 7f */ (const void *)&gVexTable_root_01_7f_pp, + /* 80 */ NULL, + /* 81 */ NULL, + /* 82 */ NULL, + /* 83 */ NULL, + /* 84 */ NULL, + /* 85 */ NULL, + /* 86 */ NULL, + /* 87 */ NULL, + /* 88 */ NULL, + /* 89 */ NULL, + /* 8a */ NULL, + /* 8b */ NULL, + /* 8c */ NULL, + /* 8d */ NULL, + /* 8e */ NULL, + /* 8f */ NULL, + /* 90 */ (const void *)&gVexTable_root_01_90_pp, + /* 91 */ (const void *)&gVexTable_root_01_91_pp, + /* 92 */ (const void *)&gVexTable_root_01_92_pp, + /* 93 */ (const void *)&gVexTable_root_01_93_pp, + /* 94 */ NULL, + /* 95 */ NULL, + /* 96 */ NULL, + /* 97 */ NULL, + /* 98 */ (const void *)&gVexTable_root_01_98_pp, + /* 99 */ (const void *)&gVexTable_root_01_99_pp, + /* 9a */ NULL, + /* 9b */ NULL, + /* 9c */ NULL, + /* 9d */ NULL, + /* 9e */ NULL, + /* 9f */ NULL, + /* a0 */ NULL, + /* a1 */ NULL, + /* a2 */ NULL, + /* a3 */ NULL, + /* a4 */ NULL, + /* a5 */ NULL, + /* a6 */ NULL, + /* a7 */ NULL, + /* a8 */ NULL, + /* a9 */ NULL, + /* aa */ NULL, + /* ab */ NULL, + /* ac */ NULL, + /* ad */ NULL, + /* ae */ (const void *)&gVexTable_root_01_ae_pp, + /* af */ NULL, + /* b0 */ NULL, + /* b1 */ NULL, + /* b2 */ NULL, + /* b3 */ NULL, + /* b4 */ NULL, + /* b5 */ NULL, + /* b6 */ NULL, + /* b7 */ NULL, + /* b8 */ NULL, + /* b9 */ NULL, + /* ba */ NULL, + /* bb */ NULL, + /* bc */ NULL, + /* bd */ NULL, + /* be */ NULL, + /* bf */ NULL, + /* c0 */ NULL, + /* c1 */ NULL, + /* c2 */ (const void *)&gVexTable_root_01_c2_pp, + /* c3 */ NULL, + /* c4 */ (const void *)&gVexTable_root_01_c4_pp, + /* c5 */ (const void *)&gVexTable_root_01_c5_pp, + /* c6 */ (const void *)&gVexTable_root_01_c6_pp, + /* c7 */ NULL, + /* c8 */ NULL, + /* c9 */ NULL, + /* ca */ NULL, + /* cb */ NULL, + /* cc */ NULL, + /* cd */ NULL, + /* ce */ NULL, + /* cf */ NULL, + /* d0 */ (const void *)&gVexTable_root_01_d0_pp, + /* d1 */ (const void *)&gVexTable_root_01_d1_pp, + /* d2 */ (const void *)&gVexTable_root_01_d2_pp, + /* d3 */ (const void *)&gVexTable_root_01_d3_pp, + /* d4 */ (const void *)&gVexTable_root_01_d4_pp, + /* d5 */ (const void *)&gVexTable_root_01_d5_pp, + /* d6 */ (const void *)&gVexTable_root_01_d6_pp, + /* d7 */ (const void *)&gVexTable_root_01_d7_pp, + /* d8 */ (const void *)&gVexTable_root_01_d8_pp, + /* d9 */ (const void *)&gVexTable_root_01_d9_pp, + /* da */ (const void *)&gVexTable_root_01_da_pp, + /* db */ (const void *)&gVexTable_root_01_db_pp, + /* dc */ (const void *)&gVexTable_root_01_dc_pp, + /* dd */ (const void *)&gVexTable_root_01_dd_pp, + /* de */ (const void *)&gVexTable_root_01_de_pp, + /* df */ (const void *)&gVexTable_root_01_df_pp, + /* e0 */ (const void *)&gVexTable_root_01_e0_pp, + /* e1 */ (const void *)&gVexTable_root_01_e1_pp, + /* e2 */ (const void *)&gVexTable_root_01_e2_pp, + /* e3 */ (const void *)&gVexTable_root_01_e3_pp, + /* e4 */ (const void *)&gVexTable_root_01_e4_pp, + /* e5 */ (const void *)&gVexTable_root_01_e5_pp, + /* e6 */ (const void *)&gVexTable_root_01_e6_pp, + /* e7 */ (const void *)&gVexTable_root_01_e7_pp, + /* e8 */ (const void *)&gVexTable_root_01_e8_pp, + /* e9 */ (const void *)&gVexTable_root_01_e9_pp, + /* ea */ (const void *)&gVexTable_root_01_ea_pp, + /* eb */ (const void *)&gVexTable_root_01_eb_pp, + /* ec */ (const void *)&gVexTable_root_01_ec_pp, + /* ed */ (const void *)&gVexTable_root_01_ed_pp, + /* ee */ (const void *)&gVexTable_root_01_ee_pp, + /* ef */ (const void *)&gVexTable_root_01_ef_pp, + /* f0 */ (const void *)&gVexTable_root_01_f0_pp, + /* f1 */ (const void *)&gVexTable_root_01_f1_pp, + /* f2 */ (const void *)&gVexTable_root_01_f2_pp, + /* f3 */ (const void *)&gVexTable_root_01_f3_pp, + /* f4 */ (const void *)&gVexTable_root_01_f4_pp, + /* f5 */ (const void *)&gVexTable_root_01_f5_pp, + /* f6 */ (const void *)&gVexTable_root_01_f6_pp, + /* f7 */ (const void *)&gVexTable_root_01_f7_pp, + /* f8 */ (const void *)&gVexTable_root_01_f8_pp, + /* f9 */ (const void *)&gVexTable_root_01_f9_pp, + /* fa */ (const void *)&gVexTable_root_01_fa_pp, + /* fb */ (const void *)&gVexTable_root_01_fb_pp, + /* fc */ (const void *)&gVexTable_root_01_fc_pp, + /* fd */ (const void *)&gVexTable_root_01_fd_pp, + /* fe */ (const void *)&gVexTable_root_01_fe_pp, + /* ff */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_32_01_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[526] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_32_01_reg_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[529] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_32_01_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_32_01_reg_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_32_01_reg_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_03_32_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_03_32_01_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_03_32_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_32_01_reg_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_32_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_32_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_33_01_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[527] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_33_01_reg_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[528] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_33_01_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_33_01_reg_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_33_01_reg_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_03_33_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_03_33_01_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_03_33_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_33_01_reg_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_33_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_33_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_30_01_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[530] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_30_01_reg_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[533] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_30_01_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_30_01_reg_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_30_01_reg_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_03_30_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_03_30_01_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_03_30_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_30_01_reg_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_30_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_30_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_31_01_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[531] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_31_01_reg_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[532] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_31_01_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_31_01_reg_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_31_01_reg_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_03_31_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_03_31_01_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_03_31_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_31_01_reg_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_31_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_31_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_f0_03_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1148] +}; + +const ND_TABLE_VEX_L gVexTable_root_03_f0_03_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_03_f0_03_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_f0_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ (const void *)&gVexTable_root_03_f0_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_df_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1350] +}; + +const ND_TABLE_VEX_L gVexTable_root_03_df_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_03_df_01_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_df_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_df_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_0d_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1363] +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_0d_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_0d_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_0c_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1364] +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_0c_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_0c_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_4b_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1365] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_4b_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_4b_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_4b_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_4b_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_4a_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1366] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_4a_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_4a_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_4a_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_4a_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_1d_01_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1421] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_1d_01_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_1d_01_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_1d_01_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1422] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_1d_01_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_1d_01_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_03_1d_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_03_1d_01_00_w, + /* 01 */ (const void *)&gVexTable_root_03_1d_01_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_1d_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_1d_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_41_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1476] +}; + +const ND_TABLE_VEX_L gVexTable_root_03_41_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_03_41_01_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_41_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_41_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_40_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1477] +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_40_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_40_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_19_01_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1484] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_19_01_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_19_01_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_03_19_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_19_01_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_19_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_19_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_39_01_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1489] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_39_01_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_39_01_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_03_39_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_39_01_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_39_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_39_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_17_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1496] +}; + +const ND_TABLE_VEX_L gVexTable_root_03_17_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_03_17_01_mem_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_17_01_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1497] +}; + +const ND_TABLE_VEX_L gVexTable_root_03_17_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_03_17_01_reg_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_03_17_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_03_17_01_mem_l, + /* 01 */ (const void *)&gVexTable_root_03_17_01_reg_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_17_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_17_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_69_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1526] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_69_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1527] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_69_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_69_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_69_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_69_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_69_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_68_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1528] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_68_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1529] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_68_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_68_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_68_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_68_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_68_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_6b_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1530] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_6b_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1531] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_6b_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_6b_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_6b_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_6b_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_6b_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_6a_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1532] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_6a_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1533] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_6a_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_6a_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_6a_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_6a_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_6a_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_5d_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1546] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_5d_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1547] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_5d_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_5d_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_5d_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_5d_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_5d_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_5c_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1548] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_5c_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1549] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_5c_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_5c_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_5c_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_5c_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_5c_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_5f_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1586] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_5f_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1587] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_5f_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_5f_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_5f_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_5f_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_5f_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_5e_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1588] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_5e_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1589] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_5e_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_5e_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_5e_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_5e_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_5e_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_6d_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1590] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_6d_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1591] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_6d_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_6d_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_6d_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_6d_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_6d_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_6c_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1592] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_6c_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1593] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_6c_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_6c_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_6c_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_6c_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_6c_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_6f_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1594] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_6f_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1595] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_6f_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_6f_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_6f_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_6f_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_6f_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_6e_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1596] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_6e_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1597] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_6e_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_6e_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_6e_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_6e_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_6e_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_79_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1622] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_79_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1623] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_79_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_79_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_79_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_79_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_79_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_78_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1624] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_78_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1625] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_78_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_78_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_78_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_78_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_78_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_7b_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1626] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_7b_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1627] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_7b_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_7b_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_7b_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_7b_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_7b_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_7a_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1628] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_7a_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1629] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_7a_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_7a_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_7a_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_7a_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_7a_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_7d_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1654] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_7d_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1655] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_7d_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_7d_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_7d_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_7d_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_7d_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_7c_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1656] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_7c_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1657] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_7c_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_7c_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_7c_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_7c_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_7c_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_7f_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1658] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_7f_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1659] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_7f_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_7f_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_7f_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_7f_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_7f_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_7e_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1660] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_7e_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1661] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_7e_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_7e_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_7e_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_7e_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_7e_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_cf_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1695] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_cf_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_cf_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_cf_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_cf_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_ce_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1697] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_ce_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_ce_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_ce_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_ce_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_18_01_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1704] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_18_01_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_18_01_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_03_18_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_18_01_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_18_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_18_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_38_01_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1709] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_38_01_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_38_01_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_03_38_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_38_01_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_38_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_38_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_21_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1716] +}; + +const ND_TABLE_VEX_L gVexTable_root_03_21_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_03_21_01_mem_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_21_01_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1717] +}; + +const ND_TABLE_VEX_L gVexTable_root_03_21_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_03_21_01_reg_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_03_21_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_03_21_01_mem_l, + /* 01 */ (const void *)&gVexTable_root_03_21_01_reg_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_21_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_21_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_42_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1848] +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_42_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_42_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_0f_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1906] +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_0f_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_0f_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_02_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1917] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_02_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_02_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_02_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_02_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_4c_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1922] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_4c_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_4c_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_4c_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_4c_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_0e_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1923] +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_0e_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_0e_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_44_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1939] +}; + +const ND_TABLE_VEX_L gVexTable_root_03_44_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_03_44_01_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_44_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_44_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_61_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1952] +}; + +const ND_TABLE_VEX_L gVexTable_root_03_61_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_03_61_01_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_61_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_61_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_60_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1953] +}; + +const ND_TABLE_VEX_L gVexTable_root_03_60_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_03_60_01_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_60_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_60_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_63_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1962] +}; + +const ND_TABLE_VEX_L gVexTable_root_03_63_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_03_63_01_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_63_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_63_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_62_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1963] +}; + +const ND_TABLE_VEX_L gVexTable_root_03_62_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_03_62_01_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_62_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_62_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_06_01_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1988] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_06_01_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_06_01_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_03_06_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_06_01_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_06_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_06_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_46_01_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1989] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_46_01_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_46_01_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_03_46_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_46_01_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_46_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_46_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_05_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2002] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_05_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_05_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_05_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_05_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_04_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2006] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_04_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_04_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_04_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_04_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_49_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2007] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_49_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2008] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_49_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_49_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_49_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_49_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_49_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_48_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2009] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_48_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2010] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_48_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_48_01_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_48_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_48_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_48_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_01_01_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2014] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_01_01_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_01_01_01_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_03_01_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_01_01_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_01_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_01_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_00_01_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2020] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_00_01_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_00_01_01_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_03_00_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_00_01_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_00_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_00_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_14_01_mem_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2034] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_14_01_mem_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_14_01_mem_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_03_14_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_03_14_01_mem_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_14_01_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2035] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_14_01_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_14_01_reg_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_03_14_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_03_14_01_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_03_14_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_03_14_01_mem_l, + /* 01 */ (const void *)&gVexTable_root_03_14_01_reg_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_14_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_14_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_16_01_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2037] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_16_01_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2039] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_16_01_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_16_01_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_16_01_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_03_16_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_03_16_01_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_16_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_16_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_15_01_mem_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2044] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_15_01_mem_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_15_01_mem_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_03_15_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_03_15_01_mem_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_15_01_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2045] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_15_01_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_15_01_reg_00_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_03_15_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_03_15_01_reg_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_03_15_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_03_15_01_mem_l, + /* 01 */ (const void *)&gVexTable_root_03_15_01_reg_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_15_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_15_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_20_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2078] +}; + +const ND_TABLE_VEX_L gVexTable_root_03_20_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_03_20_01_mem_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_20_01_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2079] +}; + +const ND_TABLE_VEX_L gVexTable_root_03_20_01_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_03_20_01_reg_00_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_03_20_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_03_20_01_mem_l, + /* 01 */ (const void *)&gVexTable_root_03_20_01_reg_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_20_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_20_01_modrmmod, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_22_01_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2081] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_22_01_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2083] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_22_01_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_03_22_01_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_22_01_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_03_22_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_03_22_01_00_w, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_22_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_22_01_l, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_09_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2414] +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_09_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_09_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_08_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2415] +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_08_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_08_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_0b_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2416] +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_0b_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_0b_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_0a_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2417] +}; + +const ND_TABLE_VEX_PP gVexTable_root_03_0a_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_03_0a_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_OPCODE gVexTable_root_03_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ (const void *)&gVexTable_root_03_00_pp, + /* 01 */ (const void *)&gVexTable_root_03_01_pp, + /* 02 */ (const void *)&gVexTable_root_03_02_pp, + /* 03 */ NULL, + /* 04 */ (const void *)&gVexTable_root_03_04_pp, + /* 05 */ (const void *)&gVexTable_root_03_05_pp, + /* 06 */ (const void *)&gVexTable_root_03_06_pp, + /* 07 */ NULL, + /* 08 */ (const void *)&gVexTable_root_03_08_pp, + /* 09 */ (const void *)&gVexTable_root_03_09_pp, + /* 0a */ (const void *)&gVexTable_root_03_0a_pp, + /* 0b */ (const void *)&gVexTable_root_03_0b_pp, + /* 0c */ (const void *)&gVexTable_root_03_0c_pp, + /* 0d */ (const void *)&gVexTable_root_03_0d_pp, + /* 0e */ (const void *)&gVexTable_root_03_0e_pp, + /* 0f */ (const void *)&gVexTable_root_03_0f_pp, + /* 10 */ NULL, + /* 11 */ NULL, + /* 12 */ NULL, + /* 13 */ NULL, + /* 14 */ (const void *)&gVexTable_root_03_14_pp, + /* 15 */ (const void *)&gVexTable_root_03_15_pp, + /* 16 */ (const void *)&gVexTable_root_03_16_pp, + /* 17 */ (const void *)&gVexTable_root_03_17_pp, + /* 18 */ (const void *)&gVexTable_root_03_18_pp, + /* 19 */ (const void *)&gVexTable_root_03_19_pp, + /* 1a */ NULL, + /* 1b */ NULL, + /* 1c */ NULL, + /* 1d */ (const void *)&gVexTable_root_03_1d_pp, + /* 1e */ NULL, + /* 1f */ NULL, + /* 20 */ (const void *)&gVexTable_root_03_20_pp, + /* 21 */ (const void *)&gVexTable_root_03_21_pp, + /* 22 */ (const void *)&gVexTable_root_03_22_pp, + /* 23 */ NULL, + /* 24 */ NULL, + /* 25 */ NULL, + /* 26 */ NULL, + /* 27 */ NULL, + /* 28 */ NULL, + /* 29 */ NULL, + /* 2a */ NULL, + /* 2b */ NULL, + /* 2c */ NULL, + /* 2d */ NULL, + /* 2e */ NULL, + /* 2f */ NULL, + /* 30 */ (const void *)&gVexTable_root_03_30_pp, + /* 31 */ (const void *)&gVexTable_root_03_31_pp, + /* 32 */ (const void *)&gVexTable_root_03_32_pp, + /* 33 */ (const void *)&gVexTable_root_03_33_pp, + /* 34 */ NULL, + /* 35 */ NULL, + /* 36 */ NULL, + /* 37 */ NULL, + /* 38 */ (const void *)&gVexTable_root_03_38_pp, + /* 39 */ (const void *)&gVexTable_root_03_39_pp, + /* 3a */ NULL, + /* 3b */ NULL, + /* 3c */ NULL, + /* 3d */ NULL, + /* 3e */ NULL, + /* 3f */ NULL, + /* 40 */ (const void *)&gVexTable_root_03_40_pp, + /* 41 */ (const void *)&gVexTable_root_03_41_pp, + /* 42 */ (const void *)&gVexTable_root_03_42_pp, + /* 43 */ NULL, + /* 44 */ (const void *)&gVexTable_root_03_44_pp, + /* 45 */ NULL, + /* 46 */ (const void *)&gVexTable_root_03_46_pp, + /* 47 */ NULL, + /* 48 */ (const void *)&gVexTable_root_03_48_pp, + /* 49 */ (const void *)&gVexTable_root_03_49_pp, + /* 4a */ (const void *)&gVexTable_root_03_4a_pp, + /* 4b */ (const void *)&gVexTable_root_03_4b_pp, + /* 4c */ (const void *)&gVexTable_root_03_4c_pp, + /* 4d */ NULL, + /* 4e */ NULL, + /* 4f */ NULL, + /* 50 */ NULL, + /* 51 */ NULL, + /* 52 */ NULL, + /* 53 */ NULL, + /* 54 */ NULL, + /* 55 */ NULL, + /* 56 */ NULL, + /* 57 */ NULL, + /* 58 */ NULL, + /* 59 */ NULL, + /* 5a */ NULL, + /* 5b */ NULL, + /* 5c */ (const void *)&gVexTable_root_03_5c_pp, + /* 5d */ (const void *)&gVexTable_root_03_5d_pp, + /* 5e */ (const void *)&gVexTable_root_03_5e_pp, + /* 5f */ (const void *)&gVexTable_root_03_5f_pp, + /* 60 */ (const void *)&gVexTable_root_03_60_pp, + /* 61 */ (const void *)&gVexTable_root_03_61_pp, + /* 62 */ (const void *)&gVexTable_root_03_62_pp, + /* 63 */ (const void *)&gVexTable_root_03_63_pp, + /* 64 */ NULL, + /* 65 */ NULL, + /* 66 */ NULL, + /* 67 */ NULL, + /* 68 */ (const void *)&gVexTable_root_03_68_pp, + /* 69 */ (const void *)&gVexTable_root_03_69_pp, + /* 6a */ (const void *)&gVexTable_root_03_6a_pp, + /* 6b */ (const void *)&gVexTable_root_03_6b_pp, + /* 6c */ (const void *)&gVexTable_root_03_6c_pp, + /* 6d */ (const void *)&gVexTable_root_03_6d_pp, + /* 6e */ (const void *)&gVexTable_root_03_6e_pp, + /* 6f */ (const void *)&gVexTable_root_03_6f_pp, + /* 70 */ NULL, + /* 71 */ NULL, + /* 72 */ NULL, + /* 73 */ NULL, + /* 74 */ NULL, + /* 75 */ NULL, + /* 76 */ NULL, + /* 77 */ NULL, + /* 78 */ (const void *)&gVexTable_root_03_78_pp, + /* 79 */ (const void *)&gVexTable_root_03_79_pp, + /* 7a */ (const void *)&gVexTable_root_03_7a_pp, + /* 7b */ (const void *)&gVexTable_root_03_7b_pp, + /* 7c */ (const void *)&gVexTable_root_03_7c_pp, + /* 7d */ (const void *)&gVexTable_root_03_7d_pp, + /* 7e */ (const void *)&gVexTable_root_03_7e_pp, + /* 7f */ (const void *)&gVexTable_root_03_7f_pp, + /* 80 */ NULL, + /* 81 */ NULL, + /* 82 */ NULL, + /* 83 */ NULL, + /* 84 */ NULL, + /* 85 */ NULL, + /* 86 */ NULL, + /* 87 */ NULL, + /* 88 */ NULL, + /* 89 */ NULL, + /* 8a */ NULL, + /* 8b */ NULL, + /* 8c */ NULL, + /* 8d */ NULL, + /* 8e */ NULL, + /* 8f */ NULL, + /* 90 */ NULL, + /* 91 */ NULL, + /* 92 */ NULL, + /* 93 */ NULL, + /* 94 */ NULL, + /* 95 */ NULL, + /* 96 */ NULL, + /* 97 */ NULL, + /* 98 */ NULL, + /* 99 */ NULL, + /* 9a */ NULL, + /* 9b */ NULL, + /* 9c */ NULL, + /* 9d */ NULL, + /* 9e */ NULL, + /* 9f */ NULL, + /* a0 */ NULL, + /* a1 */ NULL, + /* a2 */ NULL, + /* a3 */ NULL, + /* a4 */ NULL, + /* a5 */ NULL, + /* a6 */ NULL, + /* a7 */ NULL, + /* a8 */ NULL, + /* a9 */ NULL, + /* aa */ NULL, + /* ab */ NULL, + /* ac */ NULL, + /* ad */ NULL, + /* ae */ NULL, + /* af */ NULL, + /* b0 */ NULL, + /* b1 */ NULL, + /* b2 */ NULL, + /* b3 */ NULL, + /* b4 */ NULL, + /* b5 */ NULL, + /* b6 */ NULL, + /* b7 */ NULL, + /* b8 */ NULL, + /* b9 */ NULL, + /* ba */ NULL, + /* bb */ NULL, + /* bc */ NULL, + /* bd */ NULL, + /* be */ NULL, + /* bf */ NULL, + /* c0 */ NULL, + /* c1 */ NULL, + /* c2 */ NULL, + /* c3 */ NULL, + /* c4 */ NULL, + /* c5 */ NULL, + /* c6 */ NULL, + /* c7 */ NULL, + /* c8 */ NULL, + /* c9 */ NULL, + /* ca */ NULL, + /* cb */ NULL, + /* cc */ NULL, + /* cd */ NULL, + /* ce */ (const void *)&gVexTable_root_03_ce_pp, + /* cf */ (const void *)&gVexTable_root_03_cf_pp, + /* d0 */ NULL, + /* d1 */ NULL, + /* d2 */ NULL, + /* d3 */ NULL, + /* d4 */ NULL, + /* d5 */ NULL, + /* d6 */ NULL, + /* d7 */ NULL, + /* d8 */ NULL, + /* d9 */ NULL, + /* da */ NULL, + /* db */ NULL, + /* dc */ NULL, + /* dd */ NULL, + /* de */ NULL, + /* df */ (const void *)&gVexTable_root_03_df_pp, + /* e0 */ NULL, + /* e1 */ NULL, + /* e2 */ NULL, + /* e3 */ NULL, + /* e4 */ NULL, + /* e5 */ NULL, + /* e6 */ NULL, + /* e7 */ NULL, + /* e8 */ NULL, + /* e9 */ NULL, + /* ea */ NULL, + /* eb */ NULL, + /* ec */ NULL, + /* ed */ NULL, + /* ee */ NULL, + /* ef */ NULL, + /* f0 */ (const void *)&gVexTable_root_03_f0_pp, + /* f1 */ NULL, + /* f2 */ NULL, + /* f3 */ NULL, + /* f4 */ NULL, + /* f5 */ NULL, + /* f6 */ NULL, + /* f7 */ NULL, + /* f8 */ NULL, + /* f9 */ NULL, + /* fa */ NULL, + /* fb */ NULL, + /* fc */ NULL, + /* fd */ NULL, + /* fe */ NULL, + /* ff */ NULL, + } +}; + +const ND_TABLE_VEX_MMMMM gVexTable_root_mmmmm = +{ + ND_ILUT_VEX_MMMMM, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_01_opcode, + /* 02 */ (const void *)&gVexTable_root_02_opcode, + /* 03 */ (const void *)&gVexTable_root_03_opcode, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + /* 08 */ NULL, + /* 09 */ NULL, + /* 0a */ NULL, + /* 0b */ NULL, + /* 0c */ NULL, + /* 0d */ NULL, + /* 0e */ NULL, + /* 0f */ NULL, + /* 10 */ NULL, + /* 11 */ NULL, + /* 12 */ NULL, + /* 13 */ NULL, + /* 14 */ NULL, + /* 15 */ NULL, + /* 16 */ NULL, + /* 17 */ NULL, + /* 18 */ NULL, + /* 19 */ NULL, + /* 1a */ NULL, + /* 1b */ NULL, + /* 1c */ NULL, + /* 1d */ NULL, + /* 1e */ NULL, + /* 1f */ NULL, + } +}; + +const PND_TABLE gVexTable = (const PND_TABLE)&gVexTable_root_mmmmm; + + +#endif + diff --git a/bddisasm/include/table_xop.h b/bddisasm/include/table_xop.h new file mode 100644 index 0000000..9d0901e --- /dev/null +++ b/bddisasm/include/table_xop.h @@ -0,0 +1,1541 @@ +#ifndef _TABLE_XOP_H_ +#define _TABLE_XOP_H_ + +const ND_TABLE_INSTRUCTION gXopTable_root_0a_10_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[56] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_0a_12_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[584] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_0a_12_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[585] +}; + +const ND_TABLE_MODRM_REG gXopTable_root_0a_12_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gXopTable_root_0a_12_00_leaf, + /* 01 */ (const void *)&gXopTable_root_0a_12_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_OPCODE gXopTable_root_0a_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + /* 08 */ NULL, + /* 09 */ NULL, + /* 0a */ NULL, + /* 0b */ NULL, + /* 0c */ NULL, + /* 0d */ NULL, + /* 0e */ NULL, + /* 0f */ NULL, + /* 10 */ (const void *)&gXopTable_root_0a_10_leaf, + /* 11 */ NULL, + /* 12 */ (const void *)&gXopTable_root_0a_12_modrmreg, + /* 13 */ NULL, + /* 14 */ NULL, + /* 15 */ NULL, + /* 16 */ NULL, + /* 17 */ NULL, + /* 18 */ NULL, + /* 19 */ NULL, + /* 1a */ NULL, + /* 1b */ NULL, + /* 1c */ NULL, + /* 1d */ NULL, + /* 1e */ NULL, + /* 1f */ NULL, + /* 20 */ NULL, + /* 21 */ NULL, + /* 22 */ NULL, + /* 23 */ NULL, + /* 24 */ NULL, + /* 25 */ NULL, + /* 26 */ NULL, + /* 27 */ NULL, + /* 28 */ NULL, + /* 29 */ NULL, + /* 2a */ NULL, + /* 2b */ NULL, + /* 2c */ NULL, + /* 2d */ NULL, + /* 2e */ NULL, + /* 2f */ NULL, + /* 30 */ NULL, + /* 31 */ NULL, + /* 32 */ NULL, + /* 33 */ NULL, + /* 34 */ NULL, + /* 35 */ NULL, + /* 36 */ NULL, + /* 37 */ NULL, + /* 38 */ NULL, + /* 39 */ NULL, + /* 3a */ NULL, + /* 3b */ NULL, + /* 3c */ NULL, + /* 3d */ NULL, + /* 3e */ NULL, + /* 3f */ NULL, + /* 40 */ NULL, + /* 41 */ NULL, + /* 42 */ NULL, + /* 43 */ NULL, + /* 44 */ NULL, + /* 45 */ NULL, + /* 46 */ NULL, + /* 47 */ NULL, + /* 48 */ NULL, + /* 49 */ NULL, + /* 4a */ NULL, + /* 4b */ NULL, + /* 4c */ NULL, + /* 4d */ NULL, + /* 4e */ NULL, + /* 4f */ NULL, + /* 50 */ NULL, + /* 51 */ NULL, + /* 52 */ NULL, + /* 53 */ NULL, + /* 54 */ NULL, + /* 55 */ NULL, + /* 56 */ NULL, + /* 57 */ NULL, + /* 58 */ NULL, + /* 59 */ NULL, + /* 5a */ NULL, + /* 5b */ NULL, + /* 5c */ NULL, + /* 5d */ NULL, + /* 5e */ NULL, + /* 5f */ NULL, + /* 60 */ NULL, + /* 61 */ NULL, + /* 62 */ NULL, + /* 63 */ NULL, + /* 64 */ NULL, + /* 65 */ NULL, + /* 66 */ NULL, + /* 67 */ NULL, + /* 68 */ NULL, + /* 69 */ NULL, + /* 6a */ NULL, + /* 6b */ NULL, + /* 6c */ NULL, + /* 6d */ NULL, + /* 6e */ NULL, + /* 6f */ NULL, + /* 70 */ NULL, + /* 71 */ NULL, + /* 72 */ NULL, + /* 73 */ NULL, + /* 74 */ NULL, + /* 75 */ NULL, + /* 76 */ NULL, + /* 77 */ NULL, + /* 78 */ NULL, + /* 79 */ NULL, + /* 7a */ NULL, + /* 7b */ NULL, + /* 7c */ NULL, + /* 7d */ NULL, + /* 7e */ NULL, + /* 7f */ NULL, + /* 80 */ NULL, + /* 81 */ NULL, + /* 82 */ NULL, + /* 83 */ NULL, + /* 84 */ NULL, + /* 85 */ NULL, + /* 86 */ NULL, + /* 87 */ NULL, + /* 88 */ NULL, + /* 89 */ NULL, + /* 8a */ NULL, + /* 8b */ NULL, + /* 8c */ NULL, + /* 8d */ NULL, + /* 8e */ NULL, + /* 8f */ NULL, + /* 90 */ NULL, + /* 91 */ NULL, + /* 92 */ NULL, + /* 93 */ NULL, + /* 94 */ NULL, + /* 95 */ NULL, + /* 96 */ NULL, + /* 97 */ NULL, + /* 98 */ NULL, + /* 99 */ NULL, + /* 9a */ NULL, + /* 9b */ NULL, + /* 9c */ NULL, + /* 9d */ NULL, + /* 9e */ NULL, + /* 9f */ NULL, + /* a0 */ NULL, + /* a1 */ NULL, + /* a2 */ NULL, + /* a3 */ NULL, + /* a4 */ NULL, + /* a5 */ NULL, + /* a6 */ NULL, + /* a7 */ NULL, + /* a8 */ NULL, + /* a9 */ NULL, + /* aa */ NULL, + /* ab */ NULL, + /* ac */ NULL, + /* ad */ NULL, + /* ae */ NULL, + /* af */ NULL, + /* b0 */ NULL, + /* b1 */ NULL, + /* b2 */ NULL, + /* b3 */ NULL, + /* b4 */ NULL, + /* b5 */ NULL, + /* b6 */ NULL, + /* b7 */ NULL, + /* b8 */ NULL, + /* b9 */ NULL, + /* ba */ NULL, + /* bb */ NULL, + /* bc */ NULL, + /* bd */ NULL, + /* be */ NULL, + /* bf */ NULL, + /* c0 */ NULL, + /* c1 */ NULL, + /* c2 */ NULL, + /* c3 */ NULL, + /* c4 */ NULL, + /* c5 */ NULL, + /* c6 */ NULL, + /* c7 */ NULL, + /* c8 */ NULL, + /* c9 */ NULL, + /* ca */ NULL, + /* cb */ NULL, + /* cc */ NULL, + /* cd */ NULL, + /* ce */ NULL, + /* cf */ NULL, + /* d0 */ NULL, + /* d1 */ NULL, + /* d2 */ NULL, + /* d3 */ NULL, + /* d4 */ NULL, + /* d5 */ NULL, + /* d6 */ NULL, + /* d7 */ NULL, + /* d8 */ NULL, + /* d9 */ NULL, + /* da */ NULL, + /* db */ NULL, + /* dc */ NULL, + /* dd */ NULL, + /* de */ NULL, + /* df */ NULL, + /* e0 */ NULL, + /* e1 */ NULL, + /* e2 */ NULL, + /* e3 */ NULL, + /* e4 */ NULL, + /* e5 */ NULL, + /* e6 */ NULL, + /* e7 */ NULL, + /* e8 */ NULL, + /* e9 */ NULL, + /* ea */ NULL, + /* eb */ NULL, + /* ec */ NULL, + /* ed */ NULL, + /* ee */ NULL, + /* ef */ NULL, + /* f0 */ NULL, + /* f1 */ NULL, + /* f2 */ NULL, + /* f3 */ NULL, + /* f4 */ NULL, + /* f5 */ NULL, + /* f6 */ NULL, + /* f7 */ NULL, + /* f8 */ NULL, + /* f9 */ NULL, + /* fa */ NULL, + /* fb */ NULL, + /* fc */ NULL, + /* fd */ NULL, + /* fe */ NULL, + /* ff */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[57] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_01_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[59] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_01_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[61] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_01_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[66] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_01_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[68] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_01_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1293] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_01_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1315] +}; + +const ND_TABLE_MODRM_REG gXopTable_root_09_01_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gXopTable_root_09_01_01_leaf, + /* 02 */ (const void *)&gXopTable_root_09_01_02_leaf, + /* 03 */ (const void *)&gXopTable_root_09_01_03_leaf, + /* 04 */ (const void *)&gXopTable_root_09_01_04_leaf, + /* 05 */ (const void *)&gXopTable_root_09_01_05_leaf, + /* 06 */ (const void *)&gXopTable_root_09_01_06_leaf, + /* 07 */ (const void *)&gXopTable_root_09_01_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_02_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[58] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_02_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[60] +}; + +const ND_TABLE_MODRM_REG gXopTable_root_09_02_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gXopTable_root_09_02_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ (const void *)&gXopTable_root_09_02_06_leaf, + /* 07 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_12_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[565] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_12_reg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1245] +}; + +const ND_TABLE_MODRM_REG gXopTable_root_09_12_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gXopTable_root_09_12_reg_00_leaf, + /* 01 */ (const void *)&gXopTable_root_09_12_reg_01_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gXopTable_root_09_12_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gXopTable_root_09_12_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_81_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1666] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_80_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1667] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_83_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1668] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_82_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1669] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_c2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2054] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_c3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2055] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_c1_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2056] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_cb_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2058] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_d2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2060] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_d3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2061] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_d1_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2062] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_db_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2063] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_d6_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2064] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_d7_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2065] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_c6_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2067] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_c7_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2068] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_e1_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2070] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_e3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2072] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_e2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2075] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_90_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2237] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_90_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2238] +}; + +const ND_TABLE_VEX_W gXopTable_root_09_90_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gXopTable_root_09_90_00_leaf, + /* 01 */ (const void *)&gXopTable_root_09_90_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_92_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2240] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_92_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2241] +}; + +const ND_TABLE_VEX_W gXopTable_root_09_92_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gXopTable_root_09_92_00_leaf, + /* 01 */ (const void *)&gXopTable_root_09_92_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_93_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2243] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_93_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2244] +}; + +const ND_TABLE_VEX_W gXopTable_root_09_93_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gXopTable_root_09_93_00_leaf, + /* 01 */ (const void *)&gXopTable_root_09_93_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_91_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2246] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_91_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2247] +}; + +const ND_TABLE_VEX_W gXopTable_root_09_91_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gXopTable_root_09_91_00_leaf, + /* 01 */ (const void *)&gXopTable_root_09_91_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_98_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2254] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_98_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2255] +}; + +const ND_TABLE_VEX_W gXopTable_root_09_98_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gXopTable_root_09_98_00_leaf, + /* 01 */ (const void *)&gXopTable_root_09_98_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_9a_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2256] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_9a_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2257] +}; + +const ND_TABLE_VEX_W gXopTable_root_09_9a_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gXopTable_root_09_9a_00_leaf, + /* 01 */ (const void *)&gXopTable_root_09_9a_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_9b_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2258] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_9b_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2259] +}; + +const ND_TABLE_VEX_W gXopTable_root_09_9b_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gXopTable_root_09_9b_00_leaf, + /* 01 */ (const void *)&gXopTable_root_09_9b_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_99_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2260] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_99_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2261] +}; + +const ND_TABLE_VEX_W gXopTable_root_09_99_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gXopTable_root_09_99_00_leaf, + /* 01 */ (const void *)&gXopTable_root_09_99_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_94_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2262] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_94_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2263] +}; + +const ND_TABLE_VEX_W gXopTable_root_09_94_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gXopTable_root_09_94_00_leaf, + /* 01 */ (const void *)&gXopTable_root_09_94_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_95_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2264] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_95_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2265] +}; + +const ND_TABLE_VEX_W gXopTable_root_09_95_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gXopTable_root_09_95_00_leaf, + /* 01 */ (const void *)&gXopTable_root_09_95_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_96_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2266] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_96_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2267] +}; + +const ND_TABLE_VEX_W gXopTable_root_09_96_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gXopTable_root_09_96_00_leaf, + /* 01 */ (const void *)&gXopTable_root_09_96_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_97_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2274] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_09_97_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2275] +}; + +const ND_TABLE_VEX_W gXopTable_root_09_97_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gXopTable_root_09_97_00_leaf, + /* 01 */ (const void *)&gXopTable_root_09_97_01_leaf, + } +}; + +const ND_TABLE_OPCODE gXopTable_root_09_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gXopTable_root_09_01_modrmreg, + /* 02 */ (const void *)&gXopTable_root_09_02_modrmreg, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + /* 08 */ NULL, + /* 09 */ NULL, + /* 0a */ NULL, + /* 0b */ NULL, + /* 0c */ NULL, + /* 0d */ NULL, + /* 0e */ NULL, + /* 0f */ NULL, + /* 10 */ NULL, + /* 11 */ NULL, + /* 12 */ (const void *)&gXopTable_root_09_12_modrmmod, + /* 13 */ NULL, + /* 14 */ NULL, + /* 15 */ NULL, + /* 16 */ NULL, + /* 17 */ NULL, + /* 18 */ NULL, + /* 19 */ NULL, + /* 1a */ NULL, + /* 1b */ NULL, + /* 1c */ NULL, + /* 1d */ NULL, + /* 1e */ NULL, + /* 1f */ NULL, + /* 20 */ NULL, + /* 21 */ NULL, + /* 22 */ NULL, + /* 23 */ NULL, + /* 24 */ NULL, + /* 25 */ NULL, + /* 26 */ NULL, + /* 27 */ NULL, + /* 28 */ NULL, + /* 29 */ NULL, + /* 2a */ NULL, + /* 2b */ NULL, + /* 2c */ NULL, + /* 2d */ NULL, + /* 2e */ NULL, + /* 2f */ NULL, + /* 30 */ NULL, + /* 31 */ NULL, + /* 32 */ NULL, + /* 33 */ NULL, + /* 34 */ NULL, + /* 35 */ NULL, + /* 36 */ NULL, + /* 37 */ NULL, + /* 38 */ NULL, + /* 39 */ NULL, + /* 3a */ NULL, + /* 3b */ NULL, + /* 3c */ NULL, + /* 3d */ NULL, + /* 3e */ NULL, + /* 3f */ NULL, + /* 40 */ NULL, + /* 41 */ NULL, + /* 42 */ NULL, + /* 43 */ NULL, + /* 44 */ NULL, + /* 45 */ NULL, + /* 46 */ NULL, + /* 47 */ NULL, + /* 48 */ NULL, + /* 49 */ NULL, + /* 4a */ NULL, + /* 4b */ NULL, + /* 4c */ NULL, + /* 4d */ NULL, + /* 4e */ NULL, + /* 4f */ NULL, + /* 50 */ NULL, + /* 51 */ NULL, + /* 52 */ NULL, + /* 53 */ NULL, + /* 54 */ NULL, + /* 55 */ NULL, + /* 56 */ NULL, + /* 57 */ NULL, + /* 58 */ NULL, + /* 59 */ NULL, + /* 5a */ NULL, + /* 5b */ NULL, + /* 5c */ NULL, + /* 5d */ NULL, + /* 5e */ NULL, + /* 5f */ NULL, + /* 60 */ NULL, + /* 61 */ NULL, + /* 62 */ NULL, + /* 63 */ NULL, + /* 64 */ NULL, + /* 65 */ NULL, + /* 66 */ NULL, + /* 67 */ NULL, + /* 68 */ NULL, + /* 69 */ NULL, + /* 6a */ NULL, + /* 6b */ NULL, + /* 6c */ NULL, + /* 6d */ NULL, + /* 6e */ NULL, + /* 6f */ NULL, + /* 70 */ NULL, + /* 71 */ NULL, + /* 72 */ NULL, + /* 73 */ NULL, + /* 74 */ NULL, + /* 75 */ NULL, + /* 76 */ NULL, + /* 77 */ NULL, + /* 78 */ NULL, + /* 79 */ NULL, + /* 7a */ NULL, + /* 7b */ NULL, + /* 7c */ NULL, + /* 7d */ NULL, + /* 7e */ NULL, + /* 7f */ NULL, + /* 80 */ (const void *)&gXopTable_root_09_80_leaf, + /* 81 */ (const void *)&gXopTable_root_09_81_leaf, + /* 82 */ (const void *)&gXopTable_root_09_82_leaf, + /* 83 */ (const void *)&gXopTable_root_09_83_leaf, + /* 84 */ NULL, + /* 85 */ NULL, + /* 86 */ NULL, + /* 87 */ NULL, + /* 88 */ NULL, + /* 89 */ NULL, + /* 8a */ NULL, + /* 8b */ NULL, + /* 8c */ NULL, + /* 8d */ NULL, + /* 8e */ NULL, + /* 8f */ NULL, + /* 90 */ (const void *)&gXopTable_root_09_90_w, + /* 91 */ (const void *)&gXopTable_root_09_91_w, + /* 92 */ (const void *)&gXopTable_root_09_92_w, + /* 93 */ (const void *)&gXopTable_root_09_93_w, + /* 94 */ (const void *)&gXopTable_root_09_94_w, + /* 95 */ (const void *)&gXopTable_root_09_95_w, + /* 96 */ (const void *)&gXopTable_root_09_96_w, + /* 97 */ (const void *)&gXopTable_root_09_97_w, + /* 98 */ (const void *)&gXopTable_root_09_98_w, + /* 99 */ (const void *)&gXopTable_root_09_99_w, + /* 9a */ (const void *)&gXopTable_root_09_9a_w, + /* 9b */ (const void *)&gXopTable_root_09_9b_w, + /* 9c */ NULL, + /* 9d */ NULL, + /* 9e */ NULL, + /* 9f */ NULL, + /* a0 */ NULL, + /* a1 */ NULL, + /* a2 */ NULL, + /* a3 */ NULL, + /* a4 */ NULL, + /* a5 */ NULL, + /* a6 */ NULL, + /* a7 */ NULL, + /* a8 */ NULL, + /* a9 */ NULL, + /* aa */ NULL, + /* ab */ NULL, + /* ac */ NULL, + /* ad */ NULL, + /* ae */ NULL, + /* af */ NULL, + /* b0 */ NULL, + /* b1 */ NULL, + /* b2 */ NULL, + /* b3 */ NULL, + /* b4 */ NULL, + /* b5 */ NULL, + /* b6 */ NULL, + /* b7 */ NULL, + /* b8 */ NULL, + /* b9 */ NULL, + /* ba */ NULL, + /* bb */ NULL, + /* bc */ NULL, + /* bd */ NULL, + /* be */ NULL, + /* bf */ NULL, + /* c0 */ NULL, + /* c1 */ (const void *)&gXopTable_root_09_c1_leaf, + /* c2 */ (const void *)&gXopTable_root_09_c2_leaf, + /* c3 */ (const void *)&gXopTable_root_09_c3_leaf, + /* c4 */ NULL, + /* c5 */ NULL, + /* c6 */ (const void *)&gXopTable_root_09_c6_leaf, + /* c7 */ (const void *)&gXopTable_root_09_c7_leaf, + /* c8 */ NULL, + /* c9 */ NULL, + /* ca */ NULL, + /* cb */ (const void *)&gXopTable_root_09_cb_leaf, + /* cc */ NULL, + /* cd */ NULL, + /* ce */ NULL, + /* cf */ NULL, + /* d0 */ NULL, + /* d1 */ (const void *)&gXopTable_root_09_d1_leaf, + /* d2 */ (const void *)&gXopTable_root_09_d2_leaf, + /* d3 */ (const void *)&gXopTable_root_09_d3_leaf, + /* d4 */ NULL, + /* d5 */ NULL, + /* d6 */ (const void *)&gXopTable_root_09_d6_leaf, + /* d7 */ (const void *)&gXopTable_root_09_d7_leaf, + /* d8 */ NULL, + /* d9 */ NULL, + /* da */ NULL, + /* db */ (const void *)&gXopTable_root_09_db_leaf, + /* dc */ NULL, + /* dd */ NULL, + /* de */ NULL, + /* df */ NULL, + /* e0 */ NULL, + /* e1 */ (const void *)&gXopTable_root_09_e1_leaf, + /* e2 */ (const void *)&gXopTable_root_09_e2_leaf, + /* e3 */ (const void *)&gXopTable_root_09_e3_leaf, + /* e4 */ NULL, + /* e5 */ NULL, + /* e6 */ NULL, + /* e7 */ NULL, + /* e8 */ NULL, + /* e9 */ NULL, + /* ea */ NULL, + /* eb */ NULL, + /* ec */ NULL, + /* ed */ NULL, + /* ee */ NULL, + /* ef */ NULL, + /* f0 */ NULL, + /* f1 */ NULL, + /* f2 */ NULL, + /* f3 */ NULL, + /* f4 */ NULL, + /* f5 */ NULL, + /* f6 */ NULL, + /* f7 */ NULL, + /* f8 */ NULL, + /* f9 */ NULL, + /* fa */ NULL, + /* fb */ NULL, + /* fc */ NULL, + /* fd */ NULL, + /* fe */ NULL, + /* ff */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_08_a2_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1940] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_08_a2_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1941] +}; + +const ND_TABLE_VEX_W gXopTable_root_08_a2_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gXopTable_root_08_a2_00_leaf, + /* 01 */ (const void *)&gXopTable_root_08_a2_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_08_cc_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1970] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_08_ce_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1971] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_08_cf_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1976] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_08_ec_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1977] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_08_ee_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1978] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_08_ef_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1979] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_08_ed_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1980] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_08_cd_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1981] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_08_9e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2090] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_08_9f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2091] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_08_97_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2092] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_08_8e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2093] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_08_8f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2094] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_08_87_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2095] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_08_86_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2096] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_08_85_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2097] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_08_96_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2098] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_08_95_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2099] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_08_a6_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2100] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_08_b6_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2101] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_08_a3_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2226] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_08_a3_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2227] +}; + +const ND_TABLE_VEX_W gXopTable_root_08_a3_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gXopTable_root_08_a3_00_leaf, + /* 01 */ (const void *)&gXopTable_root_08_a3_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_08_c0_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2236] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_08_c2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2239] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_08_c3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2242] +}; + +const ND_TABLE_INSTRUCTION gXopTable_root_08_c1_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2245] +}; + +const ND_TABLE_OPCODE gXopTable_root_08_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + /* 08 */ NULL, + /* 09 */ NULL, + /* 0a */ NULL, + /* 0b */ NULL, + /* 0c */ NULL, + /* 0d */ NULL, + /* 0e */ NULL, + /* 0f */ NULL, + /* 10 */ NULL, + /* 11 */ NULL, + /* 12 */ NULL, + /* 13 */ NULL, + /* 14 */ NULL, + /* 15 */ NULL, + /* 16 */ NULL, + /* 17 */ NULL, + /* 18 */ NULL, + /* 19 */ NULL, + /* 1a */ NULL, + /* 1b */ NULL, + /* 1c */ NULL, + /* 1d */ NULL, + /* 1e */ NULL, + /* 1f */ NULL, + /* 20 */ NULL, + /* 21 */ NULL, + /* 22 */ NULL, + /* 23 */ NULL, + /* 24 */ NULL, + /* 25 */ NULL, + /* 26 */ NULL, + /* 27 */ NULL, + /* 28 */ NULL, + /* 29 */ NULL, + /* 2a */ NULL, + /* 2b */ NULL, + /* 2c */ NULL, + /* 2d */ NULL, + /* 2e */ NULL, + /* 2f */ NULL, + /* 30 */ NULL, + /* 31 */ NULL, + /* 32 */ NULL, + /* 33 */ NULL, + /* 34 */ NULL, + /* 35 */ NULL, + /* 36 */ NULL, + /* 37 */ NULL, + /* 38 */ NULL, + /* 39 */ NULL, + /* 3a */ NULL, + /* 3b */ NULL, + /* 3c */ NULL, + /* 3d */ NULL, + /* 3e */ NULL, + /* 3f */ NULL, + /* 40 */ NULL, + /* 41 */ NULL, + /* 42 */ NULL, + /* 43 */ NULL, + /* 44 */ NULL, + /* 45 */ NULL, + /* 46 */ NULL, + /* 47 */ NULL, + /* 48 */ NULL, + /* 49 */ NULL, + /* 4a */ NULL, + /* 4b */ NULL, + /* 4c */ NULL, + /* 4d */ NULL, + /* 4e */ NULL, + /* 4f */ NULL, + /* 50 */ NULL, + /* 51 */ NULL, + /* 52 */ NULL, + /* 53 */ NULL, + /* 54 */ NULL, + /* 55 */ NULL, + /* 56 */ NULL, + /* 57 */ NULL, + /* 58 */ NULL, + /* 59 */ NULL, + /* 5a */ NULL, + /* 5b */ NULL, + /* 5c */ NULL, + /* 5d */ NULL, + /* 5e */ NULL, + /* 5f */ NULL, + /* 60 */ NULL, + /* 61 */ NULL, + /* 62 */ NULL, + /* 63 */ NULL, + /* 64 */ NULL, + /* 65 */ NULL, + /* 66 */ NULL, + /* 67 */ NULL, + /* 68 */ NULL, + /* 69 */ NULL, + /* 6a */ NULL, + /* 6b */ NULL, + /* 6c */ NULL, + /* 6d */ NULL, + /* 6e */ NULL, + /* 6f */ NULL, + /* 70 */ NULL, + /* 71 */ NULL, + /* 72 */ NULL, + /* 73 */ NULL, + /* 74 */ NULL, + /* 75 */ NULL, + /* 76 */ NULL, + /* 77 */ NULL, + /* 78 */ NULL, + /* 79 */ NULL, + /* 7a */ NULL, + /* 7b */ NULL, + /* 7c */ NULL, + /* 7d */ NULL, + /* 7e */ NULL, + /* 7f */ NULL, + /* 80 */ NULL, + /* 81 */ NULL, + /* 82 */ NULL, + /* 83 */ NULL, + /* 84 */ NULL, + /* 85 */ (const void *)&gXopTable_root_08_85_leaf, + /* 86 */ (const void *)&gXopTable_root_08_86_leaf, + /* 87 */ (const void *)&gXopTable_root_08_87_leaf, + /* 88 */ NULL, + /* 89 */ NULL, + /* 8a */ NULL, + /* 8b */ NULL, + /* 8c */ NULL, + /* 8d */ NULL, + /* 8e */ (const void *)&gXopTable_root_08_8e_leaf, + /* 8f */ (const void *)&gXopTable_root_08_8f_leaf, + /* 90 */ NULL, + /* 91 */ NULL, + /* 92 */ NULL, + /* 93 */ NULL, + /* 94 */ NULL, + /* 95 */ (const void *)&gXopTable_root_08_95_leaf, + /* 96 */ (const void *)&gXopTable_root_08_96_leaf, + /* 97 */ (const void *)&gXopTable_root_08_97_leaf, + /* 98 */ NULL, + /* 99 */ NULL, + /* 9a */ NULL, + /* 9b */ NULL, + /* 9c */ NULL, + /* 9d */ NULL, + /* 9e */ (const void *)&gXopTable_root_08_9e_leaf, + /* 9f */ (const void *)&gXopTable_root_08_9f_leaf, + /* a0 */ NULL, + /* a1 */ NULL, + /* a2 */ (const void *)&gXopTable_root_08_a2_w, + /* a3 */ (const void *)&gXopTable_root_08_a3_w, + /* a4 */ NULL, + /* a5 */ NULL, + /* a6 */ (const void *)&gXopTable_root_08_a6_leaf, + /* a7 */ NULL, + /* a8 */ NULL, + /* a9 */ NULL, + /* aa */ NULL, + /* ab */ NULL, + /* ac */ NULL, + /* ad */ NULL, + /* ae */ NULL, + /* af */ NULL, + /* b0 */ NULL, + /* b1 */ NULL, + /* b2 */ NULL, + /* b3 */ NULL, + /* b4 */ NULL, + /* b5 */ NULL, + /* b6 */ (const void *)&gXopTable_root_08_b6_leaf, + /* b7 */ NULL, + /* b8 */ NULL, + /* b9 */ NULL, + /* ba */ NULL, + /* bb */ NULL, + /* bc */ NULL, + /* bd */ NULL, + /* be */ NULL, + /* bf */ NULL, + /* c0 */ (const void *)&gXopTable_root_08_c0_leaf, + /* c1 */ (const void *)&gXopTable_root_08_c1_leaf, + /* c2 */ (const void *)&gXopTable_root_08_c2_leaf, + /* c3 */ (const void *)&gXopTable_root_08_c3_leaf, + /* c4 */ NULL, + /* c5 */ NULL, + /* c6 */ NULL, + /* c7 */ NULL, + /* c8 */ NULL, + /* c9 */ NULL, + /* ca */ NULL, + /* cb */ NULL, + /* cc */ (const void *)&gXopTable_root_08_cc_leaf, + /* cd */ (const void *)&gXopTable_root_08_cd_leaf, + /* ce */ (const void *)&gXopTable_root_08_ce_leaf, + /* cf */ (const void *)&gXopTable_root_08_cf_leaf, + /* d0 */ NULL, + /* d1 */ NULL, + /* d2 */ NULL, + /* d3 */ NULL, + /* d4 */ NULL, + /* d5 */ NULL, + /* d6 */ NULL, + /* d7 */ NULL, + /* d8 */ NULL, + /* d9 */ NULL, + /* da */ NULL, + /* db */ NULL, + /* dc */ NULL, + /* dd */ NULL, + /* de */ NULL, + /* df */ NULL, + /* e0 */ NULL, + /* e1 */ NULL, + /* e2 */ NULL, + /* e3 */ NULL, + /* e4 */ NULL, + /* e5 */ NULL, + /* e6 */ NULL, + /* e7 */ NULL, + /* e8 */ NULL, + /* e9 */ NULL, + /* ea */ NULL, + /* eb */ NULL, + /* ec */ (const void *)&gXopTable_root_08_ec_leaf, + /* ed */ (const void *)&gXopTable_root_08_ed_leaf, + /* ee */ (const void *)&gXopTable_root_08_ee_leaf, + /* ef */ (const void *)&gXopTable_root_08_ef_leaf, + /* f0 */ NULL, + /* f1 */ NULL, + /* f2 */ NULL, + /* f3 */ NULL, + /* f4 */ NULL, + /* f5 */ NULL, + /* f6 */ NULL, + /* f7 */ NULL, + /* f8 */ NULL, + /* f9 */ NULL, + /* fa */ NULL, + /* fb */ NULL, + /* fc */ NULL, + /* fd */ NULL, + /* fe */ NULL, + /* ff */ NULL, + } +}; + +const ND_TABLE_VEX_MMMMM gXopTable_root_mmmmm = +{ + ND_ILUT_VEX_MMMMM, + { + /* 00 */ NULL, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + /* 08 */ (const void *)&gXopTable_root_08_opcode, + /* 09 */ (const void *)&gXopTable_root_09_opcode, + /* 0a */ (const void *)&gXopTable_root_0a_opcode, + /* 0b */ NULL, + /* 0c */ NULL, + /* 0d */ NULL, + /* 0e */ NULL, + /* 0f */ NULL, + /* 10 */ NULL, + /* 11 */ NULL, + /* 12 */ NULL, + /* 13 */ NULL, + /* 14 */ NULL, + /* 15 */ NULL, + /* 16 */ NULL, + /* 17 */ NULL, + /* 18 */ NULL, + /* 19 */ NULL, + /* 1a */ NULL, + /* 1b */ NULL, + /* 1c */ NULL, + /* 1d */ NULL, + /* 1e */ NULL, + /* 1f */ NULL, + } +}; + +const PND_TABLE gXopTable = (const PND_TABLE)&gXopTable_root_mmmmm; + + +#endif + diff --git a/bddisasm/include/tabledefs.h b/bddisasm/include/tabledefs.h new file mode 100644 index 0000000..795f04e --- /dev/null +++ b/bddisasm/include/tabledefs.h @@ -0,0 +1,480 @@ +/* + * Copyright (c) 2020 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _TABLEDEFS_H_ +#define _TABLEDEFS_H_ + +// +// Types of tables. +// +typedef enum _ND_ILUT_TYPE +{ + ND_ILUT_INSTRUCTION = 0,// Table contains one entry that directly points to an instruction. + ND_ILUT_OPCODE, // Table contains 256 entries. Next entry is selected using an opcode. + ND_ILUT_OPCODE_3DNOW, // Table contains 256 entries. Next entry is selected using an opcode, but the + // opcode follows the instruction. + ND_ILUT_MODRM_MOD, // Table contains 2 entries. Next entry is selected using modrm.mod (0 - mem, 1 - reg) + ND_ILUT_MODRM_REG, // Table contains 8 entries. Next entry is selected using modrm.reg. + ND_ILUT_MODRM_RM, // Table contains 8 entries. Next entry is selected using modrm.rm. + ND_ILUT_MAN_PREFIX, // Table contains 4 entries. Next entry is 0 (no prefix), 1 (0x66), 2 (0xF3), 3 (0xF2). + ND_ILUT_MODE, // Table contains 4 entries. Next entry is 0 (16 bit mode), 1 (32 bit mode), 2 (64 bit mode). + ND_ILUT_DSIZE, // Table contains 4 entries. Next entry is 0 (16 bit size), 1 (32 bit size), 2 (64 bit size). + // This DOES NOT take into consideration forced/default sizes. + ND_ILUT_ASIZE, // Default addressing mode is used to transition + ND_ILUT_AUXILIARY, // Table contains 8 entries. Next entry is 0 (no prefix), 1 (rex), 2 (rex.w), 3 (64 bit), + // 4 (default op size 16), 5 (default op size 32), 6 (default op size 64), + ND_ILUT_VENDOR, // Preferred vendor is used to transition. Default is entry 0. Otherwise, preferred + // vendor selects an alternate entry. + ND_ILUT_VEX_MMMMM, // Table contains 32 entries. Next entry is vex/xop/evex.mmmmm + ND_ILUT_VEX_PP, // Table contains 4 entries. Next entry is vex/xop/evex.pp + ND_ILUT_VEX_L, // Table contains 4 entries. Next entry is vex/xop.l or evex.l'l + ND_ILUT_VEX_W, // Table contains 2 entries. Next entry is vex/xop/evex.w +} ND_ILUT_TYPE; + + +// Index definitions +#define ND_ILUT_INDEX_MOD_MEM 0 +#define ND_ILUT_INDEX_MOD_REG 1 + +#define ND_ILUT_INDEX_MAN_PREF_NONE 0 +#define ND_ILUT_INDEX_MAN_PREF_66 1 +#define ND_ILUT_INDEX_MAN_PREF_F3 2 +#define ND_ILUT_INDEX_MAN_PREF_F2 3 + +#define ND_ILUT_INDEX_MODE_NONE 0 +#define ND_ILUT_INDEX_MODE_16 1 +#define ND_ILUT_INDEX_MODE_32 2 +#define ND_ILUT_INDEX_MODE_64 3 + +#define ND_ILUT_INDEX_DSIZE_NONE 0 +#define ND_ILUT_INDEX_DSIZE_16 1 +#define ND_ILUT_INDEX_DSIZE_32 2 +#define ND_ILUT_INDEX_DSIZE_64 3 +#define ND_ILUT_INDEX_DSIZE_DEF64 4 +#define ND_ILUT_INDEX_DSIZE_F64 5 + +#define ND_ILUT_INDEX_ASIZE_NONE 0 +#define ND_ILUT_INDEX_ASIZE_16 1 +#define ND_ILUT_INDEX_ASIZE_32 2 +#define ND_ILUT_INDEX_ASIZE_64 3 + +#define ND_ILUT_INDEX_AUX_NONE 0 +#define ND_ILUT_INDEX_AUX_REX 1 +#define ND_ILUT_INDEX_AUX_REXW 2 +#define ND_ILUT_INDEX_AUX_O64 3 +#define ND_ILUT_INDEX_AUX_F3 4 +#define ND_ILUT_INDEX_AUX_REP 5 + + + + +typedef struct _ND_TABLE +{ + uint32_t Type; + const void *Table[1]; +} ND_TABLE, *PND_TABLE; + +typedef struct _ND_TABLE_INSTRUCTION +{ + uint32_t Type; + const void *Instruction; +} ND_TABLE_INSTRUCTION, *PND_TABLE_INSTRUCTION; + +typedef struct _ND_TABLE_OPCODE +{ + uint32_t Type; + const void *Table[256]; +} ND_TABLE_OPCODE, *PND_TABLE_OPCODE; + +typedef struct _ND_TABLE_MODRM_MOD +{ + uint32_t Type; + const void *Table[2]; +} ND_TABLE_MODRM_MOD, *PND_TABLE_MODRM_MOD; + +typedef struct _ND_TABLE_MODRM_REG +{ + uint32_t Type; + const void *Table[8]; +} ND_TABLE_MODRM_REG, *PND_TABLE_MODRM_REG; + +typedef struct _ND_TABLE_MODRM_RM +{ + uint32_t Type; + const void *Table[8]; +} ND_TABLE_MODRM_RM, *PND_TABLE_MODRM_RM; + +typedef struct _ND_TABLE_MPREFIX +{ + uint32_t Type; + const void *Table[4]; +} ND_TABLE_MPREFIX, *PND_TABLE_MPREFIX; + + +typedef struct _ND_TABLE_AUXILIARY +{ + uint32_t Type; + const void *Table[6]; +} ND_TABLE_AUXILIARY, *PND_TABLE_AUXILIARY; + +typedef struct _ND_TABLE_VENDOR +{ + uint32_t Type; + const void *Table[6]; +} ND_TABLE_VENDOR; + +typedef struct _ND_TABLE_DSIZE +{ + uint32_t Type; + const void *Table[6]; +} ND_TABLE_DSIZE, *PND_TABLE_DSIZE; + +typedef struct _ND_TABLE_ASIZE +{ + uint32_t Type; + const void *Table[4]; +} ND_TABLE_ASIZE, *PND_TABLE_ASIZE; + +typedef struct _ND_TABLE_MODE +{ + uint32_t Type; + const void *Table[4]; +} ND_TABLE_MODE, *PND_TABLE_MODE; + +typedef struct _ND_TABLE_VEX_MMMMM +{ + uint32_t Type; + const void *Table[32]; +} ND_TABLE_VEX_MMMMM, *PND_TABLE_VEX_MMMMM; + +typedef struct _ND_TABLE_VEX_PP +{ + uint32_t Type; + const void *Table[4]; +} ND_TABLE_VEX_PP, *PND_TABLE_VEX_PP; + +typedef struct _ND_TABLE_VEX_L +{ + uint32_t Type; + const void *Table[4]; +} ND_TABLE_VEX_L, *PND_TABLE_VEX_L; + +typedef struct _ND_TABLE_VEX_W +{ + uint32_t Type; + const void *Table[8]; +} ND_TABLE_VEX_W, *PND_TABLE_VEX_W; + + +// +// One instruction entry. This structure should be maintained bellow 2 cache lines in size (128 bytes). +// +#ifdef _MSC_VER +__declspec(align(128)) +#pragma warning(push) +#pragma warning(disable: 4214) +#else +__attribute__((aligned(128))) +#endif +typedef struct _ND_INSTRUCTION +{ + uint16_t Instruction; // Instruction identifier. Check ND_INS_CLASS definitions. + uint8_t Category; // Instruction category. Check ND_INS_TYPE. + uint8_t IsaSet; // Instruction set. Check ND_INS_SET. + uint16_t Mnemonic; // Mnemonic (index inside the global mnemonic table). + + uint16_t ValidModes; // Valid operating modes for the instruction. + uint16_t ValidPrefixes; // Accepted prefixes. + uint8_t ValidDecorators;// Accepted decorators (valid for EVEX instructions). + + uint8_t OpsCount; // Low 4 bits: explicit operands count; high 4 bits: implicit ops count. + + uint8_t TupleType; // EVEX tuple type. + uint8_t ExcType : 5; // SSE/VEX/EVEX/OPMASK/AMX exception type. + uint8_t ExcClass : 3; // Indicates the exception class (SSE/AVX, EVEX, OPMASK or AMX). + + uint8_t FpuFlags; // FPU status word C0, C1, C2 & C3 access type. + + uint8_t Reserved2; + uint32_t Reserved3; + + uint32_t Attributes; // Instruction attributes. + uint64_t CpuidFlag; // Required CPUID feature flag. + + // Per-flag access. Undefined flags will have their bit set in both the "Set" and "Cleared" mask, since a flag + // cannot be both cleared and set. + uint32_t TestedFlags; // Tested flags. + uint32_t ModifiedFlags; // Modified flags. + uint32_t SetFlags; // Flags that are always set to 1. + uint32_t ClearedFlags; // Flags that are always cleared. + + uint64_t Operands[10]; +} ND_INSTRUCTION, *PND_INSTRUCTION; +#ifdef _MSC_VER +#pragma warning(pop) +#endif + +// +// The following definitions are per-operand specific. +// +// Packed operand structure: +// Byte 0: operand type +// Byte 1: operand size +// Byte 2: operand flags +// Byte 3: operand decorators +// Byte 4: operand block addressing mode - 0 if not block addressing +// +#define ND_OP(type, size, flags, dec, block) (((uint64_t)((type) & 0xFF) << 0) | \ + ((uint64_t)((size) & 0xFF) << 8) | \ + ((uint64_t)((flags) & 0xFF) << 16) | \ + ((uint64_t)((dec) & 0xFF) << 24) | \ + ((uint64_t)((block) & 0xFF) << 32)) + +#define OP ND_OP + +#define ND_OPS_CNT(expo, impo) ((expo) | ((impo) << 4)) +#define ND_EXP_OPS_CNT(cnt) ((cnt) & 0xF) +#define ND_IMP_OPS_CNT(cnt) ((cnt) >> 4) + +#define ND_OP_TYPE(op) ((op) & 0xFF) +#define ND_OP_SIZE(op) (((op) >> 8) & 0xFF) +#define ND_OP_FLAGS(op) (((op) >> 16) & 0xFF) +#define ND_OP_DECORATORS(op) (((op) >> 24) & 0xFF) +#define ND_OP_BLOCK(op) (((op) >> 32) & 0xFF) + + + +// +// Operand sizes descriptors. These are internal and stored inside the specifier. They must be interpreted +// accordingly to extract the actual size used in the instruction. These should not be used by anyone using +// the disassembler. Use the "Size" and "RawSize" fields inside the operand instead. +// +// For info on what each enum means, check out the valid_opsize field inside disasmlib.py. +// +typedef enum _ND_OPERAND_SIZE_SPEC +{ + ND_OPS_none = 0, + ND_OPS_0, + ND_OPS_asz, + ND_OPS_ssz, + ND_OPS_a, + ND_OPS_c, + ND_OPS_b, + ND_OPS_w, + ND_OPS_d, + ND_OPS_q, + ND_OPS_dq, + ND_OPS_qq, + ND_OPS_oq, + ND_OPS_v, + ND_OPS_y, + ND_OPS_yf, + ND_OPS_z, + ND_OPS_s, + ND_OPS_p, + ND_OPS_fa, + ND_OPS_fw, + ND_OPS_fd, + ND_OPS_fq, + ND_OPS_ft, + ND_OPS_fe, + ND_OPS_fs, + ND_OPS_l, + ND_OPS_rx, + ND_OPS_cl, + ND_OPS_sd, + ND_OPS_ss, + ND_OPS_ps, + ND_OPS_pd, + ND_OPS_e, + ND_OPS_f, + ND_OPS_h, + ND_OPS_x, + ND_OPS_n, + ND_OPS_u, + ND_OPS_t, // Tile register size, can be up to 1K. + // Stack sizes - indicates number of words. Also, hybrid sizes - sizes where from a large register (say 32 bit GPR) + // only a smaller amount of data is used (for example, 8 bit). + ND_OPS_v2, + ND_OPS_v3, + ND_OPS_v4, + ND_OPS_v8, + // MIB + ND_OPS_mib, + // VSIB sizes (for both the index and the accessed data). + ND_OPS_vm32x, + ND_OPS_vm32y, + ND_OPS_vm32z, + ND_OPS_vm32h, + ND_OPS_vm32n, + ND_OPS_vm64x, + ND_OPS_vm64y, + ND_OPS_vm64z, + ND_OPS_vm64h, + ND_OPS_vm64n, + // Used for arbitrary sized buffers. + ND_OPS_unknown, + +} ND_OPERAND_SIZE_SPEC; + + +// +// Operand types. These definitions are internal and have to be interpreted in order to find out what each +// operand represents. These should not be used by anyone using the disassembler. Use the "Type" field inside +// the operand structure instead. +// +// For more info on what each operand type means, please check out the valid_optype field inside disasmlib.py. +// +typedef enum _ND_OPERAND_TYPE_SPEC +{ + ND_OPT_A, + ND_OPT_B, + ND_OPT_C, + ND_OPT_D, + ND_OPT_E, + ND_OPT_F, + ND_OPT_G, + ND_OPT_H, + ND_OPT_I, + ND_OPT_J, + ND_OPT_K, + + ND_OPT_L, + ND_OPT_M, + ND_OPT_N, + ND_OPT_O, + ND_OPT_P, + ND_OPT_Q, + ND_OPT_R, + ND_OPT_S, + ND_OPT_T, + ND_OPT_U, + + ND_OPT_V, + ND_OPT_W, + ND_OPT_X, + ND_OPT_Y, + ND_OPT_Z, + ND_OPT_rB, + ND_OPT_mB, + ND_OPT_rK, + ND_OPT_vK, + ND_OPT_mK, + ND_OPT_aK, + ND_OPT_rM, + ND_OPT_mM, + ND_OPT_rT, + ND_OPT_mT, + ND_OPT_vT, + ND_OPT_CONST_1, + + // These are implicit arguments inside instructions. + + // Special registers. + ND_OPT_RIP, + ND_OPT_MXCSR, + ND_OPT_PKRU, + ND_OPT_SSP, + + // General Purpose REgisters. + ND_OPT_GPR_AH, + ND_OPT_GPR_rAX, + ND_OPT_GPR_rCX, + ND_OPT_GPR_rDX, + ND_OPT_GPR_rBX, + ND_OPT_GPR_rSP, + ND_OPT_GPR_rBP, + ND_OPT_GPR_rSI, + ND_OPT_GPR_rDI, + ND_OPT_GPR_rR11, + + // Segment registers. + ND_OPT_SEG_CS, + ND_OPT_SEG_SS, + ND_OPT_SEG_DS, + ND_OPT_SEG_ES, + ND_OPT_SEG_FS, + ND_OPT_SEG_GS, + + // FPU registers. + ND_OPT_FPU_ST0, + ND_OPT_FPU_STX, + + // SSE registers. + ND_OPT_SSE_XMM0, + + // Implicit memory operands. + ND_OPT_MEM_rBX_AL, + ND_OPT_MEM_rDI, + ND_OPT_MEM_SHS, + + // Misc CR/XCR/MSR/SYS registers. + ND_OPT_CR_0, + ND_OPT_SYS_IDTR, + ND_OPT_SYS_GDTR, + ND_OPT_SYS_LDTR, + ND_OPT_SYS_TR, + ND_OPT_X87_CONTROL, + ND_OPT_X87_TAG, + ND_OPT_X87_STATUS, + ND_OPT_MSR, + ND_OPT_XCR, + ND_OPT_MSR_TSC, + ND_OPT_MSR_TSCAUX, + ND_OPT_MSR_SEIP, + ND_OPT_MSR_SESP, + ND_OPT_MSR_SCS, + ND_OPT_MSR_STAR, + ND_OPT_MSR_LSTAR, + ND_OPT_MSR_FMASK, + ND_OPT_MSR_FSBASE, + ND_OPT_MSR_GSBASE, + ND_OPT_MSR_KGSBASE, + ND_OPT_XCR_0, + ND_OPT_REG_BANK, + +} ND_OPERAND_TYPE_SPEC; + + +// +// Operand flags. +// +#define ND_OPF_DEFAULT 0x01 // The operand is default, no need to show it in disassembly. +#define ND_OPF_SEX_OP1 0x02 // The operand is sign-extended to the first operands' size. +#define ND_OPF_SEX_DWS 0x04 // The operand is sign-extended to the default word size. +#define ND_OPF_N 0x00 // The operand is not accessed. +#define ND_OPF_R 0x10 // The operand is read. +#define ND_OPF_W 0x20 // The operand is written. +#define ND_OPF_CR 0x40 // The operand is read conditionally. +#define ND_OPF_CW 0x80 // The operand is written conditionally. +#define ND_OPF_RW 0x30 // Read-Write access. +#define ND_OPF_RCW 0x90 // Read-Conditional Write access. +#define ND_OPF_CRW 0X60 // Conditional Read-Write access. +#define ND_OPF_CRCW 0xC0 // Conditional Read-Conditional Write access. + + +// +// Operand decorator flags. +// +#define ND_OPD_MASK 0x01 // Mask accepted. +#define ND_OPD_Z 0x02 // Zeroing accepted. +#define ND_OPD_B32 0x04 // 32 bit broadcast supported. +#define ND_OPD_B64 0x08 // 64 bit broadcast supported. +#define ND_OPD_SAE 0x10 // Suppress all exceptions supported. +#define ND_OPD_ER 0x20 // Embedded rounding supported. + + +// +// Include auto-generated stuff. +// +#include "mnemonics.h" +#include "../inc/constants.h" +#include "instructions.h" +#include "prefixes.h" +#include "table_root.h" +#include "table_xop.h" +#include "table_vex.h" +#include "table_evex.h" + +#endif // _TABLEDEFS_H_ diff --git a/bddisasm_test/README.md b/bddisasm_test/README.md new file mode 100644 index 0000000..32841d4 --- /dev/null +++ b/bddisasm_test/README.md @@ -0,0 +1,12 @@ +# Disassembler Tests + +These tests are used to validate bddisasm. Each test consists of up to three files: +* The binary test file. The name format for this type of file is `name_16|32|64`. No extension must be provided; 16/32/64 indicates disassembly mode +* The output result file. Must be named the same as the binary test file, but with the extension .result +* Optional assembly file, used to generate the binary test file + +The `test_all.py` script will iterate all the test folders, and it will run bddisasm on each identified test file. +The result file will be compared with the output of the test run. If they are not the same, the test will fail. +Note that bddisasm will be run with the `-exi` option, in order to dump all possible information about the instructions. + +NOTE: This test will assume `disasm` is in the path. Works on Windows only. \ No newline at end of file diff --git a/bddisasm_test/amx/amx1_64 b/bddisasm_test/amx/amx1_64 new file mode 100644 index 0000000000000000000000000000000000000000..035ed72bbbbed5c64abc255faaeba81a2803b4a2 GIT binary patch literal 98 zcmX@|sKS%s$fHUSQ5Ey$$fJrlAW;b-sz5|FnCr~~l&%JoRbaBxyM+M+K%y{K6`WP! Lc>pK@A$|Y=?yoP? literal 0 HcmV?d00001 diff --git a/bddisasm_test/amx/amx1_64.asm b/bddisasm_test/amx/amx1_64.asm new file mode 100644 index 0000000..81e0f68 --- /dev/null +++ b/bddisasm_test/amx/amx1_64.asm @@ -0,0 +1,23 @@ + bits 64 + + db 0xc4, 0xe2, 0x78, 0x49, 0x00 ; LDTILECFG zmmword ptr [rax] + db 0xc4, 0xe2, 0x79, 0x49, 0x00 ; STTILECFG zmmword ptr [rax] + + db 0xc4, 0xe2, 0x7A, 0x5c, 0xF4 ; TDPBF16PS tmm6, tmm4, tmm0 + + db 0xc4, 0xe2, 0x78, 0x5e, 0xF4 ; TDPBUUD tmm6, tmm4, tmm0 + db 0xc4, 0xe2, 0x79, 0x5e, 0xF4 ; TDPBUSD tmm6, tmm4, tmm0 + db 0xc4, 0xe2, 0x7A, 0x5e, 0xF4 ; TDPBSUD tmm6, tmm4, tmm0 + db 0xc4, 0xe2, 0x7B, 0x5e, 0xF4 ; TDPBSSD tmm6, tmm4, tmm0 + + db 0xc4, 0xe2, 0x79, 0x4b, 0x04, 0x00 ; TILELOADDT1 tmm0, [rax+rax] + db 0xc4, 0xe2, 0x7b, 0x4b, 0x04, 0x00 ; TILELOADD tmm0, [rax+rax] + db 0xc4, 0xe2, 0x7a, 0x4b, 0x04, 0x00 ; TILESTORED tmm0, [rax+rax] + + db 0xc4, 0xe2, 0x79, 0x4b, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 ; TILELOADDT1 tmm0, [rax+rax+0] + db 0xc4, 0xe2, 0x7b, 0x4b, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 ; TILELOADD tmm0, [rax+rax+0] + db 0xc4, 0xe2, 0x7a, 0x4b, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 ; TILESTORED tmm0, [rax+rax+0] + + db 0xc4, 0xe2, 0x78, 0x49, 0xC0 ; TILERELEASE + db 0xc4, 0xe2, 0x7b, 0x49, 0xC0 ; TILEZERO tmm0 + db 0xc4, 0xe2, 0x7b, 0x49, 0xf8 ; TILEZERO tmm7 diff --git a/bddisasm_test/amx/amx1_64.result b/bddisasm_test/amx/amx1_64.result new file mode 100644 index 0000000..b09f2a6 --- /dev/null +++ b/bddisasm_test/amx/amx1_64.result @@ -0,0 +1,263 @@ +0000000000000000 c4e2784900 LDTILECFG zmmword ptr [rax] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-TILE, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: edx, bit: 24 + Exception class: AMX, exception type: AMX-E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: no, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 0, + +0000000000000005 c4e2794900 STTILECFG zmmword ptr [rax] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-TILE, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: edx, bit: 24 + Exception class: AMX, exception type: AMX-E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: no, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 0, + +000000000000000A c4e27a5cf4 TDPBF16PS tmm6, tmm4, tmm0 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-BF16, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: edx, bit: 22 + Exception class: AMX, exception type: AMX-E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: no, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 6, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 4, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1 + +000000000000000F c4e2785ef4 TDPBUUD tmm6, tmm4, tmm0 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-INT8, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: edx, bit: 25 + Exception class: AMX, exception type: AMX-E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: no, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 6, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 4, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1 + +0000000000000014 c4e2795ef4 TDPBUSD tmm6, tmm4, tmm0 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-INT8, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: edx, bit: 25 + Exception class: AMX, exception type: AMX-E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: no, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 6, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 4, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1 + +0000000000000019 c4e27a5ef4 TDPBSUD tmm6, tmm4, tmm0 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-INT8, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: edx, bit: 25 + Exception class: AMX, exception type: AMX-E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: no, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 6, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 4, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1 + +000000000000001E c4e27b5ef4 TDPBSSD tmm6, tmm4, tmm0 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-INT8, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: edx, bit: 25 + Exception class: AMX, exception type: AMX-E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: no, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 6, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 4, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1 + +0000000000000023 c4e2794b0400 TILELOADDT1 tmm0, [rax+rax] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-TILE, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: edx, bit: 24 + Exception class: AMX, exception type: AMX-E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: no, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1024, RawSize: 1024, Encoding: M, Sibmem Addressing: yes, + Segment: 3, Base: 0, Index: 0 * 1, + +0000000000000029 c4e27b4b0400 TILELOADD tmm0, [rax+rax] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-TILE, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: edx, bit: 24 + Exception class: AMX, exception type: AMX-E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: no, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1024, RawSize: 1024, Encoding: M, Sibmem Addressing: yes, + Segment: 3, Base: 0, Index: 0 * 1, + +000000000000002F c4e27a4b0400 TILESTORED [rax+rax], tmm0 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-TILE, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: edx, bit: 24 + Exception class: AMX, exception type: AMX-E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: no, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1024, RawSize: 1024, Encoding: M, Sibmem Addressing: yes, + Segment: 3, Base: 0, Index: 0 * 1, + Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1 + +0000000000000035 c4e2794b840000000000 TILELOADDT1 tmm0, [rax+rax+0x0] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-TILE, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: edx, bit: 24 + Exception class: AMX, exception type: AMX-E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: no, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1024, RawSize: 1024, Encoding: M, Sibmem Addressing: yes, + Segment: 3, Base: 0, Index: 0 * 1, Displacement: 0x0000000000000000, + +000000000000003F c4e27b4b840000000000 TILELOADD tmm0, [rax+rax+0x0] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-TILE, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: edx, bit: 24 + Exception class: AMX, exception type: AMX-E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: no, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1024, RawSize: 1024, Encoding: M, Sibmem Addressing: yes, + Segment: 3, Base: 0, Index: 0 * 1, Displacement: 0x0000000000000000, + +0000000000000049 c4e27a4b840000000000 TILESTORED [rax+rax+0x0], tmm0 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-TILE, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: edx, bit: 24 + Exception class: AMX, exception type: AMX-E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: no, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1024, RawSize: 1024, Encoding: M, Sibmem Addressing: yes, + Segment: 3, Base: 0, Index: 0 * 1, Displacement: 0x0000000000000000, + Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1 + +0000000000000053 c4e27849c0 TILERELEASE + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-TILE, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: edx, bit: 24 + Exception class: AMX, exception type: AMX-E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: no, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000058 c4e27b49c0 TILEZERO tmm0 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-TILE, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: edx, bit: 24 + Exception class: AMX, exception type: AMX-E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: no, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1 + +000000000000005D c4e27b49f8 TILEZERO tmm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-TILE, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: edx, bit: 24 + Exception class: AMX, exception type: AMX-E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: no, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 7, RegCount: 1 + diff --git a/bddisasm_test/avx/avx2_64 b/bddisasm_test/avx/avx2_64 new file mode 100644 index 0000000000000000000000000000000000000000..4bccd231da534ae6fdb607c7c078fe1aee53cb67 GIT binary patch literal 2198 zcmYM!y-piJ6vc4^DJUbMP}^Qxa_P@>k#OX%M=zmlC~T4cIeR^6=3eG_e>2({cKv5~{JdN!Nk_=Sa>ZS>3lTQ5jJgN1JNYmptFk$TXrdDl6*?U?H`T zS|n9n?6vS-3-7h~|2B%z=DRjZtkK&&#O&DduTQPdPx&h&Pcx1-r%~VX<1ZIvIU|oU zjy4~n?(*OJ*3r{4|3f)h=JynyJT!01{A52<{*6MOQF!{$?3Ov}o_pPMuX`TrQoSx2 z>yoi9b6%I~bt~n%m2%z6VO^SXUFEE+oOPKl*QMDl*RR8$XBuw)>e5B$3o*P_aGe5m z4pw?%m7Z`{26|$Zo^a=&sOh|FI6(v&F59~Ensf6;T9}rWEy=~%ze}y zqizA~QtMLdNmUnW-D=%xJ#H-39vLbb8gtw&SKY0u)T-2KQq_f8wOX}W)qeOtplRZVzkQKsZ{D4U{h*SYBQi63AdnH3<&hM3~_d1X|kUB`Jx=;sJ2UZ86QmqcGlA$tZl`6F-wI{WgRCS^D ztoE$-LZw>mStUbd&MH-EUus`!KdI_M?OW|z?Z;_ReOhGsVn&9_oKK6oPqS=sqU=aT4h9KwCalba3Pfu zmC>pz>TsgHPPEra+N-+Q>%@DVc(0S#E7f}?W3OcFl{xQ~Ds?P%EOnezb)k-}j;)SE srCKFJB|~M-DphYl>PqS=sqW$pNWE=IWsEmast*@Z8T|%ImA_E`0rf-8_y7O^ literal 0 HcmV?d00001 diff --git a/bddisasm_test/avx/avx2_64.asm b/bddisasm_test/avx/avx2_64.asm new file mode 100644 index 0000000..2de012b --- /dev/null +++ b/bddisasm_test/avx/avx2_64.asm @@ -0,0 +1,302 @@ + bits 64 + + vpblendd xmm2, xmm7, xmm0, 0x90 + vpblendd xmm2, xmm7, [rbx], 0x90 + vpblendd xmm2, xmm7, [rbx+r11*8+256], 0x90 + vpblendd xmm2, xmm7, [rbx+r11*8-256], 0x90 + vpbroadcastb xmm2, xmm0 + vpbroadcastb xmm2, [rbx] + vpbroadcastb xmm2, [rbx+r11*8+256] + vpbroadcastb xmm2, [rbx+r11*8-256] + vpbroadcastb ymm16, xmm0 + vpbroadcastb ymm16, [rbx] + vpbroadcastb ymm16, [rbx+r11*8+256] + vpbroadcastb ymm16, [rbx+r11*8-256] + vpbroadcastb zmm24, xmm0 + vpbroadcastb zmm24, [rbx] + vpbroadcastb zmm24, [rbx+r11*8+256] + vpbroadcastb zmm24, [rbx+r11*8-256] + vpbroadcastd xmm2, xmm0 + vpbroadcastd xmm2, [rbx] + vpbroadcastd xmm2, [rbx+r11*8+256] + vpbroadcastd xmm2, [rbx+r11*8-256] + vpbroadcastd ymm16, xmm0 + vpbroadcastd ymm16, [rbx] + vpbroadcastd ymm16, [rbx+r11*8+256] + vpbroadcastd ymm16, [rbx+r11*8-256] + vpbroadcastd zmm24, xmm0 + vpbroadcastd zmm24, [rbx] + vpbroadcastd zmm24, [rbx+r11*8+256] + vpbroadcastd zmm24, [rbx+r11*8-256] + vpbroadcastq xmm2, xmm0 + vpbroadcastq xmm2, [rbx] + vpbroadcastq xmm2, [rbx+r11*8+256] + vpbroadcastq xmm2, [rbx+r11*8-256] + vpbroadcastq ymm16, xmm0 + vpbroadcastq ymm16, [rbx] + vpbroadcastq ymm16, [rbx+r11*8+256] + vpbroadcastq ymm16, [rbx+r11*8-256] + vpbroadcastq zmm24, xmm0 + vpbroadcastq zmm24, [rbx] + vpbroadcastq zmm24, [rbx+r11*8+256] + vpbroadcastq zmm24, [rbx+r11*8-256] + vpbroadcastw xmm2, xmm0 + vpbroadcastw xmm2, [rbx] + vpbroadcastw xmm2, [rbx+r11*8+256] + vpbroadcastw xmm2, [rbx+r11*8-256] + vpbroadcastw ymm16, xmm0 + vpbroadcastw ymm16, [rbx] + vpbroadcastw ymm16, [rbx+r11*8+256] + vpbroadcastw ymm16, [rbx+r11*8-256] + vpbroadcastw zmm24, xmm0 + vpbroadcastw zmm24, [rbx] + vpbroadcastw zmm24, [rbx+r11*8+256] + vpbroadcastw zmm24, [rbx+r11*8-256] + vpermd ymm16, ymm13, ymm15 + vpermd ymm16, ymm13, [rbx] + vpermd ymm16, ymm13, [rbx+r11*8+256] + vpermd ymm16, ymm13, [rbx+r11*8-256] + vpermd zmm24, zmm24, zmm31 + vpermd zmm24, zmm24, [rbx] + vpermd zmm24, zmm24, [rbx+r11*8+256] + vpermd zmm24, zmm24, [rbx+r11*8-256] + vpermpd ymm16, ymm15, 0x90 + vpermpd ymm16, [rbx], 0x90 + vpermpd ymm16, [rbx+r11*8+256], 0x90 + vpermpd ymm16, [rbx+r11*8-256], 0x90 + vpermpd zmm24, zmm31, 0x90 + vpermpd zmm24, [rbx], 0x90 + vpermpd zmm24, [rbx+r11*8+256], 0x90 + vpermpd zmm24, [rbx+r11*8-256], 0x90 + vpermps ymm16, ymm13, ymm15 + vpermps ymm16, ymm13, [rbx] + vpermps ymm16, ymm13, [rbx+r11*8+256] + vpermps ymm16, ymm13, [rbx+r11*8-256] + vpermps zmm24, zmm24, zmm31 + vpermps zmm24, zmm24, [rbx] + vpermps zmm24, zmm24, [rbx+r11*8+256] + vpermps zmm24, zmm24, [rbx+r11*8-256] + vpermq ymm16, ymm15, 0x90 + vpermq ymm16, [rbx], 0x90 + vpermq ymm16, [rbx+r11*8+256], 0x90 + vpermq ymm16, [rbx+r11*8-256], 0x90 + vpermq zmm24, zmm31, 0x90 + vpermq zmm24, [rbx], 0x90 + vpermq zmm24, [rbx+r11*8+256], 0x90 + vpermq zmm24, [rbx+r11*8-256], 0x90 + vpmaskmovd xmm2, xmm7, [rbx] + vpmaskmovd xmm2, xmm7, [rbx+rsi*8+256] + vpmaskmovd xmm2, xmm7, [rbx+rsi*8-256] + vpmaskmovd [rbx], xmm7, xmm2 + vpmaskmovd [rbx+rsi*8+256], xmm7, xmm2 + vpmaskmovd [rbx+rsi*8-256], xmm7, xmm2 + vpmaskmovq xmm2, xmm7, [rbx] + vpmaskmovq xmm2, xmm7, [rbx+rsi*8+256] + vpmaskmovq xmm2, xmm7, [rbx+rsi*8-256] + vpmaskmovq [rbx], xmm7, xmm2 + vpmaskmovq [rbx+rsi*8+256], xmm7, xmm2 + vpmaskmovq [rbx+rsi*8-256], xmm7, xmm2 + vpmovsxbd xmm2, xmm0 + vpmovsxbd xmm2, [rbx] + vpmovsxbd xmm2, [rbx+r11*8+256] + vpmovsxbd xmm2, [rbx+r11*8-256] + vpmovsxbd ymm16, xmm0 + vpmovsxbd ymm16, [rbx] + vpmovsxbd ymm16, [rbx+r11*8+256] + vpmovsxbd ymm16, [rbx+r11*8-256] + vpmovsxbd zmm24, xmm0 + vpmovsxbd zmm24, [rbx] + vpmovsxbd zmm24, [rbx+r11*8+256] + vpmovsxbd zmm24, [rbx+r11*8-256] + vpmovsxbq xmm2, xmm0 + vpmovsxbq xmm2, [rbx] + vpmovsxbq xmm2, [rbx+r11*8+256] + vpmovsxbq xmm2, [rbx+r11*8-256] + vpmovsxbq ymm16, xmm0 + vpmovsxbq ymm16, [rbx] + vpmovsxbq ymm16, [rbx+r11*8+256] + vpmovsxbq ymm16, [rbx+r11*8-256] + vpmovsxbq zmm24, xmm0 + vpmovsxbq zmm24, [rbx] + vpmovsxbq zmm24, [rbx+r11*8+256] + vpmovsxbq zmm24, [rbx+r11*8-256] + vpmovsxbw xmm2, xmm0 + vpmovsxbw xmm2, [rbx] + vpmovsxbw xmm2, [rbx+r11*8+256] + vpmovsxbw xmm2, [rbx+r11*8-256] + vpmovsxbw ymm16, xmm0 + vpmovsxbw ymm16, [rbx] + vpmovsxbw ymm16, [rbx+r11*8+256] + vpmovsxbw ymm16, [rbx+r11*8-256] + vpmovsxbw zmm24, ymm15 + vpmovsxbw zmm24, [rbx] + vpmovsxbw zmm24, [rbx+r11*8+256] + vpmovsxbw zmm24, [rbx+r11*8-256] + vpmovsxdq xmm2, xmm0 + vpmovsxdq xmm2, [rbx] + vpmovsxdq xmm2, [rbx+r11*8+256] + vpmovsxdq xmm2, [rbx+r11*8-256] + vpmovsxdq ymm16, xmm0 + vpmovsxdq ymm16, [rbx] + vpmovsxdq ymm16, [rbx+r11*8+256] + vpmovsxdq ymm16, [rbx+r11*8-256] + vpmovsxdq zmm24, ymm15 + vpmovsxdq zmm24, [rbx] + vpmovsxdq zmm24, [rbx+r11*8+256] + vpmovsxdq zmm24, [rbx+r11*8-256] + vpmovsxwd xmm2, xmm0 + vpmovsxwd xmm2, [rbx] + vpmovsxwd xmm2, [rbx+r11*8+256] + vpmovsxwd xmm2, [rbx+r11*8-256] + vpmovsxwd ymm16, xmm0 + vpmovsxwd ymm16, [rbx] + vpmovsxwd ymm16, [rbx+r11*8+256] + vpmovsxwd ymm16, [rbx+r11*8-256] + vpmovsxwd zmm24, ymm15 + vpmovsxwd zmm24, [rbx] + vpmovsxwd zmm24, [rbx+r11*8+256] + vpmovsxwd zmm24, [rbx+r11*8-256] + vpmovsxwq xmm2, xmm0 + vpmovsxwq xmm2, [rbx] + vpmovsxwq xmm2, [rbx+r11*8+256] + vpmovsxwq xmm2, [rbx+r11*8-256] + vpmovsxwq ymm16, xmm0 + vpmovsxwq ymm16, [rbx] + vpmovsxwq ymm16, [rbx+r11*8+256] + vpmovsxwq ymm16, [rbx+r11*8-256] + vpmovsxwq zmm24, xmm0 + vpmovsxwq zmm24, [rbx] + vpmovsxwq zmm24, [rbx+r11*8+256] + vpmovsxwq zmm24, [rbx+r11*8-256] + vpmovzxbd xmm2, xmm0 + vpmovzxbd xmm2, [rbx] + vpmovzxbd xmm2, [rbx+r11*8+256] + vpmovzxbd xmm2, [rbx+r11*8-256] + vpmovzxbd ymm16, xmm0 + vpmovzxbd ymm16, [rbx] + vpmovzxbd ymm16, [rbx+r11*8+256] + vpmovzxbd ymm16, [rbx+r11*8-256] + vpmovzxbd zmm24, xmm0 + vpmovzxbd zmm24, [rbx] + vpmovzxbd zmm24, [rbx+r11*8+256] + vpmovzxbd zmm24, [rbx+r11*8-256] + vpmovzxbq xmm2, xmm0 + vpmovzxbq xmm2, [rbx] + vpmovzxbq xmm2, [rbx+r11*8+256] + vpmovzxbq xmm2, [rbx+r11*8-256] + vpmovzxbq ymm16, xmm0 + vpmovzxbq ymm16, [rbx] + vpmovzxbq ymm16, [rbx+r11*8+256] + vpmovzxbq ymm16, [rbx+r11*8-256] + vpmovzxbq zmm24, xmm0 + vpmovzxbq zmm24, [rbx] + vpmovzxbq zmm24, [rbx+r11*8+256] + vpmovzxbq zmm24, [rbx+r11*8-256] + vpmovzxbw xmm2, xmm0 + vpmovzxbw xmm2, [rbx] + vpmovzxbw xmm2, [rbx+r11*8+256] + vpmovzxbw xmm2, [rbx+r11*8-256] + vpmovzxbw ymm16, xmm0 + vpmovzxbw ymm16, [rbx] + vpmovzxbw ymm16, [rbx+r11*8+256] + vpmovzxbw ymm16, [rbx+r11*8-256] + vpmovzxbw zmm24, ymm15 + vpmovzxbw zmm24, [rbx] + vpmovzxbw zmm24, [rbx+r11*8+256] + vpmovzxbw zmm24, [rbx+r11*8-256] + vpmovzxdq xmm2, xmm0 + vpmovzxdq xmm2, [rbx] + vpmovzxdq xmm2, [rbx+r11*8+256] + vpmovzxdq xmm2, [rbx+r11*8-256] + vpmovzxdq ymm16, xmm0 + vpmovzxdq ymm16, [rbx] + vpmovzxdq ymm16, [rbx+r11*8+256] + vpmovzxdq ymm16, [rbx+r11*8-256] + vpmovzxdq zmm24, ymm15 + vpmovzxdq zmm24, [rbx] + vpmovzxdq zmm24, [rbx+r11*8+256] + vpmovzxdq zmm24, [rbx+r11*8-256] + vpmovzxwd xmm2, xmm0 + vpmovzxwd xmm2, [rbx] + vpmovzxwd xmm2, [rbx+r11*8+256] + vpmovzxwd xmm2, [rbx+r11*8-256] + vpmovzxwd ymm16, xmm0 + vpmovzxwd ymm16, [rbx] + vpmovzxwd ymm16, [rbx+r11*8+256] + vpmovzxwd ymm16, [rbx+r11*8-256] + vpmovzxwd zmm24, ymm15 + vpmovzxwd zmm24, [rbx] + vpmovzxwd zmm24, [rbx+r11*8+256] + vpmovzxwd zmm24, [rbx+r11*8-256] + vpmovzxwq xmm2, xmm0 + vpmovzxwq xmm2, [rbx] + vpmovzxwq xmm2, [rbx+r11*8+256] + vpmovzxwq xmm2, [rbx+r11*8-256] + vpmovzxwq ymm16, xmm0 + vpmovzxwq ymm16, [rbx] + vpmovzxwq ymm16, [rbx+r11*8+256] + vpmovzxwq ymm16, [rbx+r11*8-256] + vpmovzxwq zmm24, xmm0 + vpmovzxwq zmm24, [rbx] + vpmovzxwq zmm24, [rbx+r11*8+256] + vpmovzxwq zmm24, [rbx+r11*8-256] + vpsllvd xmm2, xmm7, xmm0 + vpsllvd xmm2, xmm7, [rbx] + vpsllvd xmm2, xmm7, [rbx+r11*8+256] + vpsllvd xmm2, xmm7, [rbx+r11*8-256] + vpsllvd ymm16, ymm13, ymm15 + vpsllvd ymm16, ymm13, [rbx] + vpsllvd ymm16, ymm13, [rbx+r11*8+256] + vpsllvd ymm16, ymm13, [rbx+r11*8-256] + vpsllvd zmm24, zmm24, zmm31 + vpsllvd zmm24, zmm24, [rbx] + vpsllvd zmm24, zmm24, [rbx+r11*8+256] + vpsllvd zmm24, zmm24, [rbx+r11*8-256] + vpsllvq xmm2, xmm7, xmm0 + vpsllvq xmm2, xmm7, [rbx] + vpsllvq xmm2, xmm7, [rbx+r11*8+256] + vpsllvq xmm2, xmm7, [rbx+r11*8-256] + vpsllvq ymm16, ymm13, ymm15 + vpsllvq ymm16, ymm13, [rbx] + vpsllvq ymm16, ymm13, [rbx+r11*8+256] + vpsllvq ymm16, ymm13, [rbx+r11*8-256] + vpsllvq zmm24, zmm24, zmm31 + vpsllvq zmm24, zmm24, [rbx] + vpsllvq zmm24, zmm24, [rbx+r11*8+256] + vpsllvq zmm24, zmm24, [rbx+r11*8-256] + vpsravd xmm2, xmm7, xmm0 + vpsravd xmm2, xmm7, [rbx] + vpsravd xmm2, xmm7, [rbx+r11*8+256] + vpsravd xmm2, xmm7, [rbx+r11*8-256] + vpsravd ymm16, ymm13, ymm15 + vpsravd ymm16, ymm13, [rbx] + vpsravd ymm16, ymm13, [rbx+r11*8+256] + vpsravd ymm16, ymm13, [rbx+r11*8-256] + vpsravd zmm24, zmm24, zmm31 + vpsravd zmm24, zmm24, [rbx] + vpsravd zmm24, zmm24, [rbx+r11*8+256] + vpsravd zmm24, zmm24, [rbx+r11*8-256] + vpsrlvd xmm2, xmm7, xmm0 + vpsrlvd xmm2, xmm7, [rbx] + vpsrlvd xmm2, xmm7, [rbx+r11*8+256] + vpsrlvd xmm2, xmm7, [rbx+r11*8-256] + vpsrlvd ymm16, ymm13, ymm15 + vpsrlvd ymm16, ymm13, [rbx] + vpsrlvd ymm16, ymm13, [rbx+r11*8+256] + vpsrlvd ymm16, ymm13, [rbx+r11*8-256] + vpsrlvd zmm24, zmm24, zmm31 + vpsrlvd zmm24, zmm24, [rbx] + vpsrlvd zmm24, zmm24, [rbx+r11*8+256] + vpsrlvd zmm24, zmm24, [rbx+r11*8-256] + vpsrlvq xmm2, xmm7, xmm0 + vpsrlvq xmm2, xmm7, [rbx] + vpsrlvq xmm2, xmm7, [rbx+r11*8+256] + vpsrlvq xmm2, xmm7, [rbx+r11*8-256] + vpsrlvq ymm16, ymm13, ymm15 + vpsrlvq ymm16, ymm13, [rbx] + vpsrlvq ymm16, ymm13, [rbx+r11*8+256] + vpsrlvq ymm16, ymm13, [rbx+r11*8-256] + vpsrlvq zmm24, zmm24, zmm31 + vpsrlvq zmm24, zmm24, [rbx] + vpsrlvq zmm24, zmm24, [rbx+r11*8+256] + vpsrlvq zmm24, zmm24, [rbx+r11*8-256] diff --git a/bddisasm_test/avx/avx2_64.result b/bddisasm_test/avx/avx2_64.result new file mode 100644 index 0000000..3232c4a --- /dev/null +++ b/bddisasm_test/avx/avx2_64.result @@ -0,0 +1,5540 @@ +0000000000000000 c4e34102d090 VPBLENDD xmm2, xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000006 c4e341021390 VPBLENDD xmm2, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000000C c4a3410294db0001000090 VPBLENDD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000017 c4a3410294db00ffffff90 VPBLENDD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000022 c4e27978d0 VPBROADCASTB xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000027 c4e2797813 VPBROADCASTB xmm2, byte ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + +000000000000002C c4a2797894db00010000 VPBROADCASTB xmm2, byte ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000036 c4a2797894db00ffffff VPBROADCASTB xmm2, byte ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000040 62e27d2878c0 VPBROADCASTB ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Tuple 1 scalar, 8 bit + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000046 62e27d287803 VPBROADCASTB ymm16, byte ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Tuple 1 scalar, 8 bit + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + +000000000000004C 62a27d287884db00010000 VPBROADCASTB ymm16, byte ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Tuple 1 scalar, 8 bit + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000057 62a27d287884db00ffffff VPBROADCASTB ymm16, byte ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Tuple 1 scalar, 8 bit + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000062 62627d4878c0 VPBROADCASTB zmm24, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Tuple 1 scalar, 8 bit + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000068 62627d487803 VPBROADCASTB zmm24, byte ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Tuple 1 scalar, 8 bit + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + +000000000000006E 62227d487884db00010000 VPBROADCASTB zmm24, byte ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Tuple 1 scalar, 8 bit + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000079 62227d487884db00ffffff VPBROADCASTB zmm24, byte ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Tuple 1 scalar, 8 bit + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000084 c4e27958d0 VPBROADCASTD xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000089 c4e2795813 VPBROADCASTD xmm2, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +000000000000008E c4a2795894db00010000 VPBROADCASTD xmm2, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000098 c4a2795894db00ffffff VPBROADCASTD xmm2, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000000A2 62e27d2858c0 VPBROADCASTD ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000000A8 62e27d285803 VPBROADCASTD ymm16, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +00000000000000AE 62a27d285844db40 VPBROADCASTD ymm16, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000040, + +00000000000000B6 62a27d285844dbc0 VPBROADCASTD ymm16, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffc0, + +00000000000000BE 62627d4858c0 VPBROADCASTD zmm24, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000000C4 62627d485803 VPBROADCASTD zmm24, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +00000000000000CA 62227d485844db40 VPBROADCASTD zmm24, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000040, + +00000000000000D2 62227d485844dbc0 VPBROADCASTD zmm24, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffc0, + +00000000000000DA c4e27959d0 VPBROADCASTQ xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000000DF c4e2795913 VPBROADCASTQ xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000000E4 c4a2795994db00010000 VPBROADCASTQ xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000000EE c4a2795994db00ffffff VPBROADCASTQ xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000000F8 62e2fd2859c0 VPBROADCASTQ ymm16, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000000FE 62e2fd285903 VPBROADCASTQ ymm16, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000104 62a2fd285944db20 VPBROADCASTQ ymm16, qword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +000000000000010C 62a2fd285944dbe0 VPBROADCASTQ ymm16, qword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +0000000000000114 6262fd4859c0 VPBROADCASTQ zmm24, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000011A 6262fd485903 VPBROADCASTQ zmm24, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000120 6222fd485944db20 VPBROADCASTQ zmm24, qword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000000128 6222fd485944dbe0 VPBROADCASTQ zmm24, qword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +0000000000000130 c4e27979d0 VPBROADCASTW xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000135 c4e2797913 VPBROADCASTW xmm2, word ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + +000000000000013A c4a2797994db00010000 VPBROADCASTW xmm2, word ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000144 c4a2797994db00ffffff VPBROADCASTW xmm2, word ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +000000000000014E 62e27d2879c0 VPBROADCASTW ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Tuple 1 scalar, 16 bit + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000154 62e27d287903 VPBROADCASTW ymm16, word ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Tuple 1 scalar, 16 bit + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + +000000000000015A 62a27d287984db00010000 VPBROADCASTW ymm16, word ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Tuple 1 scalar, 16 bit + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000165 62a27d287944db80 VPBROADCASTW ymm16, word ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Tuple 1 scalar, 16 bit + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff80, + +000000000000016D 62627d4879c0 VPBROADCASTW zmm24, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Tuple 1 scalar, 16 bit + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000173 62627d487903 VPBROADCASTW zmm24, word ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Tuple 1 scalar, 16 bit + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + +0000000000000179 62227d487984db00010000 VPBROADCASTW zmm24, word ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Tuple 1 scalar, 16 bit + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000184 62227d487944db80 VPBROADCASTW zmm24, word ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Tuple 1 scalar, 16 bit + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff80, + +000000000000018C 62c2152836c7 VPERMD ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000192 62e215283603 VPERMD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000198 62a215283644db08 VPERMD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000001A0 62a215283644dbf8 VPERMD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000001A8 62023d4036c7 VPERMD zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000001AE 62623d403603 VPERMD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000001B4 62223d403644db04 VPERMD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000001BC 62223d403644dbfc VPERMD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000001C4 62c3fd2801c790 VPERMPD ymm16, ymm15, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000001CB 62e3fd28010390 VPERMPD ymm16, ymmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000001D2 62a3fd280144db0890 VPERMPD ymm16, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000001DB 62a3fd280144dbf890 VPERMPD ymm16, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000001E4 6203fd4801c790 VPERMPD zmm24, zmm31, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000001EB 6263fd48010390 VPERMPD zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000001F2 6223fd480144db0490 VPERMPD zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000001FB 6223fd480144dbfc90 VPERMPD zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000204 62c2152816c7 VPERMPS ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000020A 62e215281603 VPERMPS ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000210 62a215281644db08 VPERMPS ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000218 62a215281644dbf8 VPERMPS ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000220 62023d4016c7 VPERMPS zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000226 62623d401603 VPERMPS zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000022C 62223d401644db04 VPERMPS zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000234 62223d401644dbfc VPERMPS zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000023C 62c3fd2800c790 VPERMQ ymm16, ymm15, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000243 62e3fd28000390 VPERMQ ymm16, ymmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000024A 62a3fd280044db0890 VPERMQ ymm16, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000253 62a3fd280044dbf890 VPERMQ ymm16, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000025C 6203fd4800c790 VPERMQ zmm24, zmm31, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000263 6263fd48000390 VPERMQ zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000026A 6223fd480044db0490 VPERMQ zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000273 6223fd480044dbfc90 VPERMQ zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000027C c4e2418c13 VPMASKMOVD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000281 c4e2418c94f300010000 VPMASKMOVD xmm2, xmm7, xmmword ptr [rbx+rsi*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + +000000000000028B c4e2418c94f300ffffff VPMASKMOVD xmm2, xmm7, xmmword ptr [rbx+rsi*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + +0000000000000295 c4e2418e13 VPMASKMOVD xmmword ptr [rbx], xmm7, xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +000000000000029A c4e2418e94f300010000 VPMASKMOVD xmmword ptr [rbx+rsi*8+0x100], xmm7, xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +00000000000002A4 c4e2418e94f300ffffff VPMASKMOVD xmmword ptr [rbx+rsi*8-0x100], xmm7, xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +00000000000002AE c4e2c18c13 VPMASKMOVQ xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000002B3 c4e2c18c94f300010000 VPMASKMOVQ xmm2, xmm7, xmmword ptr [rbx+rsi*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + +00000000000002BD c4e2c18c94f300ffffff VPMASKMOVQ xmm2, xmm7, xmmword ptr [rbx+rsi*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + +00000000000002C7 c4e2c18e13 VPMASKMOVQ xmmword ptr [rbx], xmm7, xmm2 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +00000000000002CC c4e2c18e94f300010000 VPMASKMOVQ xmmword ptr [rbx+rsi*8+0x100], xmm7, xmm2 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +00000000000002D6 c4e2c18e94f300ffffff VPMASKMOVQ xmmword ptr [rbx+rsi*8-0x100], xmm7, xmm2 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +00000000000002E0 c4e27921d0 VPMOVSXBD xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000002E5 c4e2792113 VPMOVSXBD xmm2, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +00000000000002EA c4a2792194db00010000 VPMOVSXBD xmm2, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000002F4 c4a2792194db00ffffff VPMOVSXBD xmm2, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000002FE 62e27d2821c0 VPMOVSXBD ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000304 62e27d282103 VPMOVSXBD ymm16, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000030A 62a27d282144db20 VPMOVSXBD ymm16, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000000312 62a27d282144dbe0 VPMOVSXBD ymm16, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +000000000000031A 62627d4821c0 VPMOVSXBD zmm24, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000320 62627d482103 VPMOVSXBD zmm24, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000326 62227d482144db10 VPMOVSXBD zmm24, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000032E 62227d482144dbf0 VPMOVSXBD zmm24, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000336 c4e27922d0 VPMOVSXBQ xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000033B c4e2792213 VPMOVSXBQ xmm2, word ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + +0000000000000340 c4a2792294db00010000 VPMOVSXBQ xmm2, word ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000034A c4a2792294db00ffffff VPMOVSXBQ xmm2, word ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000354 62e27d2822c0 VPMOVSXBQ ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000035A 62e27d282203 VPMOVSXBQ ymm16, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +0000000000000360 62a27d282244db40 VPMOVSXBQ ymm16, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000040, + +0000000000000368 62a27d282244dbc0 VPMOVSXBQ ymm16, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffc0, + +0000000000000370 62627d4822c0 VPMOVSXBQ zmm24, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000376 62627d482203 VPMOVSXBQ zmm24, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000037C 62227d482244db20 VPMOVSXBQ zmm24, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000000384 62227d482244dbe0 VPMOVSXBQ zmm24, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +000000000000038C c4e27920d0 VPMOVSXBW xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000391 c4e2792013 VPMOVSXBW xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000396 c4a2792094db00010000 VPMOVSXBW xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000003A0 c4a2792094db00ffffff VPMOVSXBW xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000003AA 62e27d2820c0 VPMOVSXBW ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000003B0 62e27d282003 VPMOVSXBW ymm16, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000003B6 62a27d282044db10 VPMOVSXBW ymm16, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000003BE 62a27d282044dbf0 VPMOVSXBW ymm16, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000003C6 62427d4820c7 VPMOVSXBW zmm24, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000003CC 62627d482003 VPMOVSXBW zmm24, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000003D2 62227d482044db08 VPMOVSXBW zmm24, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000003DA 62227d482044dbf8 VPMOVSXBW zmm24, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000003E2 c4e27925d0 VPMOVSXDQ xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000003E7 c4e2792513 VPMOVSXDQ xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000003EC c4a2792594db00010000 VPMOVSXDQ xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000003F6 c4a2792594db00ffffff VPMOVSXDQ xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000400 62e27d2825c0 VPMOVSXDQ ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000406 62e27d282503 VPMOVSXDQ ymm16, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000040C 62a27d282544db10 VPMOVSXDQ ymm16, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000414 62a27d282544dbf0 VPMOVSXDQ ymm16, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000041C 62427d4825c7 VPMOVSXDQ zmm24, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000422 62627d482503 VPMOVSXDQ zmm24, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000428 62227d482544db08 VPMOVSXDQ zmm24, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000430 62227d482544dbf8 VPMOVSXDQ zmm24, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000438 c4e27923d0 VPMOVSXWD xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000043D c4e2792313 VPMOVSXWD xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000442 c4a2792394db00010000 VPMOVSXWD xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000044C c4a2792394db00ffffff VPMOVSXWD xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000456 62e27d2823c0 VPMOVSXWD ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000045C 62e27d282303 VPMOVSXWD ymm16, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000462 62a27d282344db10 VPMOVSXWD ymm16, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000046A 62a27d282344dbf0 VPMOVSXWD ymm16, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000472 62427d4823c7 VPMOVSXWD zmm24, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000478 62627d482303 VPMOVSXWD zmm24, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000047E 62227d482344db08 VPMOVSXWD zmm24, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000486 62227d482344dbf8 VPMOVSXWD zmm24, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000048E c4e27924d0 VPMOVSXWQ xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000493 c4e2792413 VPMOVSXWQ xmm2, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +0000000000000498 c4a2792494db00010000 VPMOVSXWQ xmm2, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000004A2 c4a2792494db00ffffff VPMOVSXWQ xmm2, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000004AC 62e27d2824c0 VPMOVSXWQ ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000004B2 62e27d282403 VPMOVSXWQ ymm16, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000004B8 62a27d282444db20 VPMOVSXWQ ymm16, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +00000000000004C0 62a27d282444dbe0 VPMOVSXWQ ymm16, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +00000000000004C8 62627d4824c0 VPMOVSXWQ zmm24, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000004CE 62627d482403 VPMOVSXWQ zmm24, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000004D4 62227d482444db10 VPMOVSXWQ zmm24, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000004DC 62227d482444dbf0 VPMOVSXWQ zmm24, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000004E4 c4e27931d0 VPMOVZXBD xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000004E9 c4e2793113 VPMOVZXBD xmm2, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +00000000000004EE c4a2793194db00010000 VPMOVZXBD xmm2, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000004F8 c4a2793194db00ffffff VPMOVZXBD xmm2, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000502 62e27d2831c0 VPMOVZXBD ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000508 62e27d283103 VPMOVZXBD ymm16, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000050E 62a27d283144db20 VPMOVZXBD ymm16, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000000516 62a27d283144dbe0 VPMOVZXBD ymm16, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +000000000000051E 62627d4831c0 VPMOVZXBD zmm24, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000524 62627d483103 VPMOVZXBD zmm24, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000052A 62227d483144db10 VPMOVZXBD zmm24, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000532 62227d483144dbf0 VPMOVZXBD zmm24, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000053A c4e27932d0 VPMOVZXBQ xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000053F c4e2793213 VPMOVZXBQ xmm2, word ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + +0000000000000544 c4a2793294db00010000 VPMOVZXBQ xmm2, word ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000054E c4a2793294db00ffffff VPMOVZXBQ xmm2, word ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000558 62e27d2832c0 VPMOVZXBQ ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000055E 62e27d283203 VPMOVZXBQ ymm16, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +0000000000000564 62a27d283244db40 VPMOVZXBQ ymm16, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000040, + +000000000000056C 62a27d283244dbc0 VPMOVZXBQ ymm16, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffc0, + +0000000000000574 62627d4832c0 VPMOVZXBQ zmm24, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000057A 62627d483203 VPMOVZXBQ zmm24, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000580 62227d483244db20 VPMOVZXBQ zmm24, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000000588 62227d483244dbe0 VPMOVZXBQ zmm24, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +0000000000000590 c4e27930d0 VPMOVZXBW xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000595 c4e2793013 VPMOVZXBW xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000059A c4a2793094db00010000 VPMOVZXBW xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000005A4 c4a2793094db00ffffff VPMOVZXBW xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000005AE 62e27d2830c0 VPMOVZXBW ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000005B4 62e27d283003 VPMOVZXBW ymm16, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000005BA 62a27d283044db10 VPMOVZXBW ymm16, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000005C2 62a27d283044dbf0 VPMOVZXBW ymm16, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000005CA 62427d4830c7 VPMOVZXBW zmm24, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000005D0 62627d483003 VPMOVZXBW zmm24, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000005D6 62227d483044db08 VPMOVZXBW zmm24, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000005DE 62227d483044dbf8 VPMOVZXBW zmm24, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000005E6 c4e27935d0 VPMOVZXDQ xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000005EB c4e2793513 VPMOVZXDQ xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000005F0 c4a2793594db00010000 VPMOVZXDQ xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000005FA c4a2793594db00ffffff VPMOVZXDQ xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000604 62e27d2835c0 VPMOVZXDQ ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000060A 62e27d283503 VPMOVZXDQ ymm16, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000610 62a27d283544db10 VPMOVZXDQ ymm16, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000618 62a27d283544dbf0 VPMOVZXDQ ymm16, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000620 62427d4835c7 VPMOVZXDQ zmm24, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000626 62627d483503 VPMOVZXDQ zmm24, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000062C 62227d483544db08 VPMOVZXDQ zmm24, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000634 62227d483544dbf8 VPMOVZXDQ zmm24, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000063C c4e27933d0 VPMOVZXWD xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000641 c4e2793313 VPMOVZXWD xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000646 c4a2793394db00010000 VPMOVZXWD xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000650 c4a2793394db00ffffff VPMOVZXWD xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +000000000000065A 62e27d2833c0 VPMOVZXWD ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000660 62e27d283303 VPMOVZXWD ymm16, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000666 62a27d283344db10 VPMOVZXWD ymm16, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000066E 62a27d283344dbf0 VPMOVZXWD ymm16, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000676 62427d4833c7 VPMOVZXWD zmm24, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000067C 62627d483303 VPMOVZXWD zmm24, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000682 62227d483344db08 VPMOVZXWD zmm24, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000068A 62227d483344dbf8 VPMOVZXWD zmm24, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000692 c4e27934d0 VPMOVZXWQ xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000697 c4e2793413 VPMOVZXWQ xmm2, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +000000000000069C c4a2793494db00010000 VPMOVZXWQ xmm2, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000006A6 c4a2793494db00ffffff VPMOVZXWQ xmm2, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000006B0 62e27d2834c0 VPMOVZXWQ ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000006B6 62e27d283403 VPMOVZXWQ ymm16, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000006BC 62a27d283444db20 VPMOVZXWQ ymm16, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +00000000000006C4 62a27d283444dbe0 VPMOVZXWQ ymm16, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +00000000000006CC 62627d4834c0 VPMOVZXWQ zmm24, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000006D2 62627d483403 VPMOVZXWQ zmm24, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000006D8 62227d483444db10 VPMOVZXWQ zmm24, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000006E0 62227d483444dbf0 VPMOVZXWQ zmm24, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000006E8 c4e24147d0 VPSLLVD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000006ED c4e2414713 VPSLLVD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000006F2 c4a2414794db00010000 VPSLLVD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000006FC c4a2414794db00ffffff VPSLLVD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000706 62c2152847c7 VPSLLVD ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000070C 62e215284703 VPSLLVD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000712 62a215284744db08 VPSLLVD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000071A 62a215284744dbf8 VPSLLVD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000722 62023d4047c7 VPSLLVD zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000728 62623d404703 VPSLLVD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000072E 62223d404744db04 VPSLLVD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000736 62223d404744dbfc VPSLLVD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000073E c4e2c147d0 VPSLLVQ xmm2, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000743 c4e2c14713 VPSLLVQ xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000748 c4a2c14794db00010000 VPSLLVQ xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000752 c4a2c14794db00ffffff VPSLLVQ xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +000000000000075C 62c2952847c7 VPSLLVQ ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000762 62e295284703 VPSLLVQ ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000768 62a295284744db08 VPSLLVQ ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000770 62a295284744dbf8 VPSLLVQ ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000778 6202bd4047c7 VPSLLVQ zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000077E 6262bd404703 VPSLLVQ zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000784 6222bd404744db04 VPSLLVQ zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000078C 6222bd404744dbfc VPSLLVQ zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000794 c4e24146d0 VPSRAVD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000799 c4e2414613 VPSRAVD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000079E c4a2414694db00010000 VPSRAVD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000007A8 c4a2414694db00ffffff VPSRAVD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000007B2 62c2152846c7 VPSRAVD ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000007B8 62e215284603 VPSRAVD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000007BE 62a215284644db08 VPSRAVD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000007C6 62a215284644dbf8 VPSRAVD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000007CE 62023d4046c7 VPSRAVD zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000007D4 62623d404603 VPSRAVD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000007DA 62223d404644db04 VPSRAVD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000007E2 62223d404644dbfc VPSRAVD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000007EA c4e24145d0 VPSRLVD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000007EF c4e2414513 VPSRLVD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000007F4 c4a2414594db00010000 VPSRLVD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000007FE c4a2414594db00ffffff VPSRLVD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000808 62c2152845c7 VPSRLVD ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000080E 62e215284503 VPSRLVD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000814 62a215284544db08 VPSRLVD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000081C 62a215284544dbf8 VPSRLVD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000824 62023d4045c7 VPSRLVD zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000082A 62623d404503 VPSRLVD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000830 62223d404544db04 VPSRLVD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000838 62223d404544dbfc VPSRLVD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000840 c4e2c145d0 VPSRLVQ xmm2, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000845 c4e2c14513 VPSRLVQ xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000084A c4a2c14594db00010000 VPSRLVQ xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000854 c4a2c14594db00ffffff VPSRLVQ xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX2, Ins cat: AVX2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +000000000000085E 62c2952845c7 VPSRLVQ ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000864 62e295284503 VPSRLVQ ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000086A 62a295284544db08 VPSRLVQ ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000872 62a295284544dbf8 VPSRLVQ ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000087A 6202bd4045c7 VPSRLVQ zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000880 6262bd404503 VPSRLVQ zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000886 6222bd404544db04 VPSRLVQ zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000088E 6222bd404544dbfc VPSRLVQ zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + diff --git a/bddisasm_test/avx/avx2gather_64 b/bddisasm_test/avx/avx2gather_64 new file mode 100644 index 0000000000000000000000000000000000000000..80af5f6e61a1c94d591a4f75fad4ce3a3b7bcd52 GIT binary patch literal 100 zcmX@|XyT+PzZnD=7>+y=gtI12hKs>jqLZhbhN_zYlbr}>2~LEGiB5#6n+O#H0APS9 AwEzGB literal 0 HcmV?d00001 diff --git a/bddisasm_test/avx/avx2gather_64.asm b/bddisasm_test/avx/avx2gather_64.asm new file mode 100644 index 0000000..bdbfe21 --- /dev/null +++ b/bddisasm_test/avx/avx2gather_64.asm @@ -0,0 +1,12 @@ + bits 64 + + vgatherdpd xmm2, [rbx+xmm7*8+0x1000], xmm13 + vgatherdps xmm2, [rbx+xmm7*8+0x1000], xmm13 + vgatherqpd xmm2, [rbx+xmm7*8+0x1000], xmm13 + vgatherqps xmm2, [rbx+xmm7*8+0x1000], xmm13 + vgatherqps xmm2, [rbx+ymm17*8+0x1000], xmm13 + vpgatherdd xmm2, [rbx+xmm7*8+0x1000], xmm13 + vpgatherdq xmm2, [rbx+xmm7*8+0x1000], xmm13 + vpgatherqd xmm2, [rbx+xmm7*8+0x1000], xmm13 + vpgatherqd xmm2, [rbx+ymm17*8+0x1000], xmm13 + vpgatherqq xmm2, [rbx+xmm7*8+0x1000], xmm13 diff --git a/bddisasm_test/avx/avx2gather_64.result b/bddisasm_test/avx/avx2gather_64.result new file mode 100644 index 0000000..349a3c4 --- /dev/null +++ b/bddisasm_test/avx/avx2gather_64.result @@ -0,0 +1,180 @@ +0000000000000000 c4e2919294fb00100000 VGATHERDPD xmm2, xmmword ptr [rbx+xmm7*8+0x1000], xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no + Exception class: SSE/VEX, exception type: 12 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, VSIB Addressing: yes, + Segment: 3, Base: 3, Index: 7 * 8, Displacement: 0x0000000000001000, + VSIB index size: 4, VSIB element size: 8, VSIB element count: 2 + Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000000A c4e2119294fb00100000 VGATHERDPS xmm2, xmmword ptr [rbx+xmm7*8+0x1000], xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no + Exception class: SSE/VEX, exception type: 12 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, VSIB Addressing: yes, + Segment: 3, Base: 3, Index: 7 * 8, Displacement: 0x0000000000001000, + VSIB index size: 4, VSIB element size: 4, VSIB element count: 4 + Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000014 c4e2919394fb00100000 VGATHERQPD xmm2, xmmword ptr [rbx+xmm7*8+0x1000], xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no + Exception class: SSE/VEX, exception type: 12 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, VSIB Addressing: yes, + Segment: 3, Base: 3, Index: 7 * 8, Displacement: 0x0000000000001000, + VSIB index size: 8, VSIB element size: 8, VSIB element count: 2 + Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000001E c4e2119394fb00100000 VGATHERQPS xmm2, qword ptr [rbx+xmm7*8+0x1000], xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no + Exception class: SSE/VEX, exception type: 12 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, VSIB Addressing: yes, + Segment: 3, Base: 3, Index: 7 * 8, Displacement: 0x0000000000001000, + VSIB index size: 8, VSIB element size: 4, VSIB element count: 2 + Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000028 c4e2159394cb00100000 VGATHERQPS xmm2, xmmword ptr [rbx+ymm1*8+0x1000], xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no + Exception class: SSE/VEX, exception type: 12 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, VSIB Addressing: yes, + Segment: 3, Base: 3, Index: 1 * 8, Displacement: 0x0000000000001000, + VSIB index size: 8, VSIB element size: 4, VSIB element count: 4 + Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000032 c4e2119094fb00100000 VPGATHERDD xmm2, xmmword ptr [rbx+xmm7*8+0x1000], xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no + Exception class: SSE/VEX, exception type: 12 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, VSIB Addressing: yes, + Segment: 3, Base: 3, Index: 7 * 8, Displacement: 0x0000000000001000, + VSIB index size: 4, VSIB element size: 4, VSIB element count: 4 + Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000003C c4e2919094fb00100000 VPGATHERDQ xmm2, xmmword ptr [rbx+xmm7*8+0x1000], xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no + Exception class: SSE/VEX, exception type: 12 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, VSIB Addressing: yes, + Segment: 3, Base: 3, Index: 7 * 8, Displacement: 0x0000000000001000, + VSIB index size: 4, VSIB element size: 8, VSIB element count: 2 + Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000046 c4e2119194fb00100000 VPGATHERQD xmm2, qword ptr [rbx+xmm7*8+0x1000], xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no + Exception class: SSE/VEX, exception type: 12 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, VSIB Addressing: yes, + Segment: 3, Base: 3, Index: 7 * 8, Displacement: 0x0000000000001000, + VSIB index size: 8, VSIB element size: 4, VSIB element count: 2 + Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000050 c4e2159194cb00100000 VPGATHERQD xmm2, xmmword ptr [rbx+ymm1*8+0x1000], xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no + Exception class: SSE/VEX, exception type: 12 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, VSIB Addressing: yes, + Segment: 3, Base: 3, Index: 1 * 8, Displacement: 0x0000000000001000, + VSIB index size: 8, VSIB element size: 4, VSIB element count: 4 + Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000005A c4e2919194fb00100000 VPGATHERQQ xmm2, xmmword ptr [rbx+xmm7*8+0x1000], xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no + Exception class: SSE/VEX, exception type: 12 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, VSIB Addressing: yes, + Segment: 3, Base: 3, Index: 7 * 8, Displacement: 0x0000000000001000, + VSIB index size: 8, VSIB element size: 8, VSIB element count: 2 + Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + diff --git a/bddisasm_test/avx/avx_64 b/bddisasm_test/avx/avx_64 new file mode 100644 index 0000000000000000000000000000000000000000..5cbafc8db5c773f60b570047686c367a6a213c12 GIT binary patch literal 15667 zcmcJW$#Yy)mc|V-g~0}FB$?`HAUxoRG-j|dj$)7@Q}#kZu_!3!(Mm%xcQF)%(?}v} z-wSm_dDk1mzWxJ6C^Pk-qBkuw8q8o>%*9|ZP?;$S`uBbJysKVzL`N-r&Zqmm_q*rZ zyzjltlw36Lnk|}l_0Jrx-SwAaD^6RnBGfOx{8Dcos@(NjeU8{yKTO(|NII!)%MWCo`>J7A?G% zyy5Iw$!pHi->mwZ&HYKqYvZ-$?a7{%&%2%TZr6FY=kuiSv@W-MU2gZf+#c&f_PXG) zE_kd9V_p|B>jHCH%xY#@nK@u4(d&|!{AA`(RZODSB{BI)%;s&>d7J9IE!Qa(b>8MW zZ*!fuMV(~ViASAy)XA9ZBvU8MX)&vrX%%&fIZzRk7_VPq4pqe@y3WMpCzvzywR2`C z75gV=Ua6gvYAq#Td24*c8XvJ{`3T84;}+Ymwn6s zli$5^w&-5TE8VypO)uY;nn9RDxXd}vO~~&kFAY- zvR<1Q`IH?(WQP#7ds6QFQ<$B5>ET}WaBo?smFjGcRqkac6RDHvo$SojF*brXN~BJr zuMX$MV&T)-ndVEMzJmb#VqO3%f&cuAnw%p7ChFvr7mMyaoIHNdI|xp0+*4L%<&&32 z?%`x2Clh_L^Z)l`mZGbrXym1^@=}a@DTqu;^invp6yshBB1=K^QaCRboqJebHF6*~ zVkIUEdk@=y=;fsmwgErwJ;pW|QIb-*i1a~pAI^RP;_(E; z;|Yl8Cm@+8Ak1kotC?wK=75<*m_#$3VGdQrB*G+`>C8JAm~AolWTusRXyLWw4QI~^ zk7ruV&&8Ubi?!6Fo}7{#Fv$^BA5rxY)#W23(-Dme@a7vAr0rPB(mOI)KQ+GUf+IYO z##qcTE#_FlgyP7ejn|g9Cwo@%n&X@|uJgw8c~U+PuPtv+_N?$IeWMDiZOnyPVtJIO z+rr6y{>5cvA!g^V{rrnj3ypUF!85vcdA~yPLTRcKH6CV!Y)B>JG8va;Ln;|p$haaK zQktjvAl*KwZXe9uO5thCJ?Jg>ptszEvE|6#a(HYxJhmKT-g0EN9L#AktC?wK=75<* zZ@I+er+9NH=8&1h*m7pJVYbEGlbKfPp@r9yH=I2y_jf=2-LL-c&;3b7fA_n;``zFD z(I46U;n5!+{W0eL$n*zuTFh!@T19_i4phV>#wC@QLsc<}zN8Y9pTum#Y>T-kGp*bo zUQ6C^_N?S}D?AG;c#TTgpOtG_s#K_jNG(Ly;!J-_BY2}kY9YEmXCBU#R(%J@rK37U zcWb{WTl;kU);{Lin&uL9tEdpjE5p&;$?1f{^OZU~s`Egu)5>*@xlST=5?!Y=6^yw~ zB6Sj7r?Z&U$#Ll@p0}!V%yo{r&I7qlMqMZ4uG5a|v_qYC=>6Z0@UNeL=~5}W6AVl+ zFcAX_=g$@k=hMlH=a(yP4fM`oT>4b5xh|%oep6Be4bVET18Li9n9xh$(yE!=K6mA#X?zlwhLIk zxL+sX<2iP^Jk~;^9ggjk$6BOgVV@8C{E{tUc0cU?7`5>696MbeYhgCWcFJQdO!(d3 zc<1rE|1P?v=tzt)l12A3cGh_1Gp>N~ky?q_L65AHp+%ENn4txN{gFgjr@@_Fl0 zZorLr6BSAa@=5E`K1Xr%)811Zea2!`5o%;M=Qdx6+k7Ezql|538B3LIE@NqgOc^p< zh7HQF!6hTYSVe@f5eS`3V9*4HMX+Il4G1m!6fp_F68jwLB!(2FM~gtzuyv&brc(FmF9`t=C-ZOP&>; z-utcRawKv&5`8&3b2(0o;EfWw9ErXhoq0dWR_^H%KbS9Zt6=I9pYSD43?|u3UE&kI z#EHQqFBUC&>(N`U?9DbGmD_R%^@NtX#)ZWvy@SYkhNH>pB>7 z9ZMs4yyke^ni=Ea<;)&h>zn&ps%336!baP*q=F%;Eov55i*3Dgx=1z`p z?l|l!>g=e_1G!Es*E!}oiN3j~I{C?Uj=4^vZ|{9uVX|o6&5h=6I;q{A+)(c1P~~n` zoJc1`uedWcPF3-EyMV{r1w6l9AoF$s=CqjA%(OCdz)T`cqM6Pxhs-3xB%0~W+Xa|y zG52Jq70jZA*OE7!Ju7+5JLvBY^>;_^Pb&Jm!~Nai{_cqW$nFo1{_yCJG51HNKbX^E zRx{Ho`V(`YA|^5VOU$9Fm_+xNnEa$y>O|v0-v2f()OS=DMx{xK+8VE1_?qsO7y3J@ z3q^gIpH%7T<0E+7Iq^0TRcXqiUM%XxqF$V-QbE1g)Qe5MIH+V(@u1>CW6V^ts27QP zk*F7Cs#H)fGW8-;FA6HzR6MA7P#H6o%(tOW@JcJ!DP%#GR!w&zA5ILnJH!Fp~{;ui7<&~I>Vf*;&F}QagE}^bcXpA%&)}!Dl?^` z&aYhOSFZD`sFUnE@u(AzIvI1FWSC#W{94SfGgB&0nO_H!Y$hH|JeZ7`Nrw48 z%=g87KQpC*`M#O&oB4h)$!6lg#DmG0nPiwB!2CeW4>D6Km>-z=fteo!lWZm)Ogxy3 znMsDZ1anEurOcEH=8~C9W-bMjY$hH|JeZ7`N!HWpJU^Yz^V8|P#MRSD67XcbJy<#K zwaNNCsc*9W3JG>8I+OLj-BtPfN%)&d@Jq2cSu~GP^)Xd_ELSZByl8%e_mRAhvL|Kl zINou2$FnCD-5z(h$KCDm=$7nm@#q$hZW(j8WL9t<=De8mnJE>_c{AtDoDU}1Ogxx) zFc~wGtQEZ3zcabnzcaZxarIjjNx<7V;#{xsxnARQ(-B%@NsgE-nt!6MKdG)iB{vji z(R=~#1$i%IPYRD);8xuSx9UC^A3H<&%;!1td7b%uK2u6(&NoI?Q)5&$HAa(PN)C{> z&qwU@5&M>pkkk=H^C9>TiT_Y?LwW8$;Qc|~AF?NKpx{s(Qf{u^`G0DW|X!dh7d;A_P6n4FJsB#X^ z4kFJEqIN;bJUgbUcy%Jr4x)BJ%It#18J_nH&wIx5ypo!?-d?Jlq3ejG>xh)DBMV(e zOC$34lXM-C(sg99sJhpv?lr1=P2z`g-Gh}ie&((5GjEOSW=y-6XC5BUJUpIxj8V6< z>R#!(SGw+%%XLepy2mRkRX0g>lTzIls(XAy{(h3`CZ)P9sC&LK0GpUTM3vHPzBL_4 zU!Ib5%>Rn(ts|NcpW8XG>*4Nt4R_07eFr<(oGiM<-%DIeYR zaC4J}o8@rPoayJ%pNXTA5)!2^zzI~eQe~}FS+S);abUeQ$cEC}vz6Ye+D>|#M)p?4 zW2@q^MYWY8bMyX@8^e#fG5i<{k(8Lt!OD-mdH?8}_m5)oCY9`)Hy$@{JZ|2M`Q}a5 z8_6M6I;2X6^72YWr9-ZC$dwL7rDRu%N2PdF%9tx9i@ICX-JluHg&hDyMszL z6%Q&NRK`pt)BiX0|Bd?pCYVV@|KGU(Z`}Vk(LdS!J6DH71SF{y}{HQf=V_O4=Ns1#!MxPdX1>phAQ?D`gnxK+R#e<3m zl`&JvqFyWNwW3~|sZv3`*3@fFy*8+1Q}LkUL1oNTGOyK_yjEZ8wfZucNr}n+|I)A3 zmwv6j6qEf=_G^X5YlX*a#h70!GR*g2z9;5;nJE>__so3H%=dyxHWLpf9!$o}B&+-D z)&2GA{`#OM72RL&?yq7Sk7amdHDFh(SNA2k$KSm^A~6S{AGLu zPmy_ud-;uh$|nJC5_OZPn=(}@sGCgPWa_5)^B1ytcu?`6F~%R&IO~sUHi)`G)D4*` z71Rx;ZZLI&>Y--x$@=j4$OhJgXewi?L?w3sZV`2hs9Q2sDyUmb-D2vNpps49Vk#aq z#!MxPx>?lCqHfMqsi1B)b+f6PgGx4av#EGc88ekE>LsFHBI+fXDizdAOufX^OXAfc z`_;l@1@NFU=2we+65tL|cZj+pQ>B8s!_*z7?g%Q`R6MA7P#H6oEb3LFUM1>PnJN|3 zt4zJh)T?3-kj=w`iU*Z3?*X#*z;;o$i@H5irGmQM)a|Bjk98$`UAKE(@t`v1btP+E zcZs@7)Loe>71Uj(?lN^(P|2q5G8GRhW2TZt-6`r$QFmslR8V)Cy3^F1K_#2I(^NdD zjG0On^=eVC7WL{(l?v+Bre1C8)$wYP{c7RW$4Bs>GUiu{e3DyD1!|4o9==>Fe|wme zsC-P|H<^4);5USPJn(N1Q|5j%RmJ0D0v;a^{M*Bnbr)ML>S|F}m$h1%I#^llyVz=| zXmy#g?_zk|#qhX`;rT8`<}Us*ckz#P7ymezNr}mm;bY&$KlWYxV=;L$kbM`&<1UWJ zU7RuB#mO)~f%%D;pJb*~Fh4Q#6Ei;vCfQ6pn0PQ5Gn1_DtLnb0?yI?bsp!7y?yK&; z8r_rKJs#cT(LH1Co=l~0QR!Q%^sQW}R8;zwD}BqAz7>^{T`3-w;!!DMu9OV(2be#I z`9o$(nR%%4156@JqM6Pxr>b~-9frr(V0bW{Vg4QF-^KiUW=g>6&;AJbQ9)mLfNSLIcg0*`UF+_UALon5Kqo+bAzxo2fp3b$xJdvbE7Ir!{9 zChPyPyGkmW-?MAJ*RJ_Kj!ufB^+o;n{QV%&yXJe{+qmw@C$(Sj6uoQgv3ukd&F4Cr zqbqwUGfM|%N6b!U zN{QJVtaNoo9g-`E?E5YrOgvbO`Myi$KHr1c6SJ3@Qo-z**)y{jOtP7HF!5kA zW+oZt0?Y+57cx`I%tMt0KaUo?!V6|HX695Cj}^vaWf}AHhz#>{n4gRJd1gvQou9kT z&t2!|Q774T;!!6abu#8U$uPfw`GuHYWTsRwzcBL)GrtHX*-Si`crY0=lMM4H%%fr+ z%}l9a9yRl*nMZ?3HWLpf9!$o}B*T0c=DT9Po0(FNJi{9o@I>IRPkC>9K~R%|S~MSJ#z!^dqj^TD znDJ51_^4-mG-f1wMm%Q3V@Ae2BbhE9hxxdek7uS-FdsMbaWfweCfQ6pn0PQ5Gm{MS zDVR@*`BY{~nR%%46igyaqM6Pxr>c1DUOaX$9!zJLkHLIQ%*QfQD(Za9bw1`gAB#H4 zt`mt@!? ztOt{9CLT;Yn2ec8hWRASC&hd+Go@lZpY(b@>Ggav)|2e@#A7}2SVzXZo@AJ#Fh|84 z%}lANbJTT?y3Wz4lk7V2s1uJm8FQUvnBT(uR?KfRQwnC$`8|KW^LxAlzb`#2c`dw_ zyy5Iw;qjgRSv(ksyaRouaaKCFlpG*$m5*5EBUUXRA(@WgQ<%Q|Uacd_&tavEBhK~_ zXZwhFr=}y~t=eSKxt02FRsFZ-`lUF%XyLWw4QJ0vUh~!2Ndnx%wO7m9lGM!l`{!5n z{+XorpCneh6dm4wPF3aeBFg7g#Mk?03*O&Oi$86Cb(wFO_ydVg5}%a#7UB;jK1qC1 z;#@3N!R&~6ATzDZ z95a&$lW3+h%rP^GFo|Y5FBWZ>Z87&`rWMShh1ZfdoINXfoxlDo|Nb-mXA}#KHt%C6 z-^UrX`^v7ZT;ZY0eZJ!E^A&fWD`YILI6Ph~JYFKke8rLZ6DF9`VpcQL%FF>Xi7<&~ zI@9$~RZJpGqM6Qg4YMugp3JmT4=ucwyy5Iw;qiz$Z&pFinfN1sP{}=4?zwW~*Vm!M z?Owr-;4l3TH?Anx#!6lXuOsh3_N?SJ2U*iWyxL%So)w<1fDQ&l|H z6puA!%xg+!O<_)pSJ)RJA|^5FOw6IGm_*l^nEV9u Fe*jSd6bt|W literal 0 HcmV?d00001 diff --git a/bddisasm_test/avx/avx_64.asm b/bddisasm_test/avx/avx_64.asm new file mode 100644 index 0000000..bca9ad0 --- /dev/null +++ b/bddisasm_test/avx/avx_64.asm @@ -0,0 +1,2200 @@ + bits 64 + + vaddpd xmm2, xmm7, xmm0 + vaddpd xmm2, xmm7, [rbx] + vaddpd xmm2, xmm7, [rbx+r11*8+256] + vaddpd xmm2, xmm7, [rbx+r11*8-256] + vaddpd ymm16, ymm13, ymm15 + vaddpd ymm16, ymm13, [rbx] + vaddpd ymm16, ymm13, [rbx+r11*8+256] + vaddpd ymm16, ymm13, [rbx+r11*8-256] + vaddpd zmm24, zmm24, zmm31 + vaddpd zmm24, zmm24, [rbx] + vaddpd zmm24, zmm24, [rbx+r11*8+256] + vaddpd zmm24, zmm24, [rbx+r11*8-256] + vaddps xmm2, xmm7, xmm0 + vaddps xmm2, xmm7, [rbx] + vaddps xmm2, xmm7, [rbx+r11*8+256] + vaddps xmm2, xmm7, [rbx+r11*8-256] + vaddps ymm16, ymm13, ymm15 + vaddps ymm16, ymm13, [rbx] + vaddps ymm16, ymm13, [rbx+r11*8+256] + vaddps ymm16, ymm13, [rbx+r11*8-256] + vaddps zmm24, zmm24, zmm31 + vaddps zmm24, zmm24, [rbx] + vaddps zmm24, zmm24, [rbx+r11*8+256] + vaddps zmm24, zmm24, [rbx+r11*8-256] + vaddsd xmm2, xmm7, xmm0 + vaddsd xmm2, xmm7, [rbx] + vaddsd xmm2, xmm7, [rbx+r11*8+256] + vaddsd xmm2, xmm7, [rbx+r11*8-256] + vaddss xmm2, xmm7, xmm0 + vaddss xmm2, xmm7, [rbx] + vaddss xmm2, xmm7, [rbx+r11*8+256] + vaddss xmm2, xmm7, [rbx+r11*8-256] + vaddsubpd xmm2, xmm7, xmm0 + vaddsubpd xmm2, xmm7, [rbx] + vaddsubpd xmm2, xmm7, [rbx+r11*8+256] + vaddsubpd xmm2, xmm7, [rbx+r11*8-256] + vaddsubps xmm2, xmm7, xmm0 + vaddsubps xmm2, xmm7, [rbx] + vaddsubps xmm2, xmm7, [rbx+r11*8+256] + vaddsubps xmm2, xmm7, [rbx+r11*8-256] + vandnpd xmm2, xmm7, xmm0 + vandnpd xmm2, xmm7, [rbx] + vandnpd xmm2, xmm7, [rbx+r11*8+256] + vandnpd xmm2, xmm7, [rbx+r11*8-256] + vandnpd ymm16, ymm13, ymm15 + vandnpd ymm16, ymm13, [rbx] + vandnpd ymm16, ymm13, [rbx+r11*8+256] + vandnpd ymm16, ymm13, [rbx+r11*8-256] + vandnpd zmm24, zmm24, zmm31 + vandnpd zmm24, zmm24, [rbx] + vandnpd zmm24, zmm24, [rbx+r11*8+256] + vandnpd zmm24, zmm24, [rbx+r11*8-256] + vandnps xmm2, xmm7, xmm0 + vandnps xmm2, xmm7, [rbx] + vandnps xmm2, xmm7, [rbx+r11*8+256] + vandnps xmm2, xmm7, [rbx+r11*8-256] + vandnps ymm16, ymm13, ymm15 + vandnps ymm16, ymm13, [rbx] + vandnps ymm16, ymm13, [rbx+r11*8+256] + vandnps ymm16, ymm13, [rbx+r11*8-256] + vandnps zmm24, zmm24, zmm31 + vandnps zmm24, zmm24, [rbx] + vandnps zmm24, zmm24, [rbx+r11*8+256] + vandnps zmm24, zmm24, [rbx+r11*8-256] + vandpd xmm2, xmm7, xmm0 + vandpd xmm2, xmm7, [rbx] + vandpd xmm2, xmm7, [rbx+r11*8+256] + vandpd xmm2, xmm7, [rbx+r11*8-256] + vandpd ymm16, ymm13, ymm15 + vandpd ymm16, ymm13, [rbx] + vandpd ymm16, ymm13, [rbx+r11*8+256] + vandpd ymm16, ymm13, [rbx+r11*8-256] + vandpd zmm24, zmm24, zmm31 + vandpd zmm24, zmm24, [rbx] + vandpd zmm24, zmm24, [rbx+r11*8+256] + vandpd zmm24, zmm24, [rbx+r11*8-256] + vandps xmm2, xmm7, xmm0 + vandps xmm2, xmm7, [rbx] + vandps xmm2, xmm7, [rbx+r11*8+256] + vandps xmm2, xmm7, [rbx+r11*8-256] + vandps ymm16, ymm13, ymm15 + vandps ymm16, ymm13, [rbx] + vandps ymm16, ymm13, [rbx+r11*8+256] + vandps ymm16, ymm13, [rbx+r11*8-256] + vandps zmm24, zmm24, zmm31 + vandps zmm24, zmm24, [rbx] + vandps zmm24, zmm24, [rbx+r11*8+256] + vandps zmm24, zmm24, [rbx+r11*8-256] + vblendpd xmm2, xmm7, xmm0, 0x90 + vblendpd xmm2, xmm7, [rbx], 0x90 + vblendpd xmm2, xmm7, [rbx+r11*8+256], 0x90 + vblendpd xmm2, xmm7, [rbx+r11*8-256], 0x90 + vblendps xmm2, xmm7, xmm0, 0x90 + vblendps xmm2, xmm7, [rbx], 0x90 + vblendps xmm2, xmm7, [rbx+r11*8+256], 0x90 + vblendps xmm2, xmm7, [rbx+r11*8-256], 0x90 + vblendvpd xmm2, xmm7, xmm0, xmm3 + vblendvpd xmm2, xmm7, [rbx], xmm3 + vblendvpd xmm2, xmm7, [rbx+r11*8+256], xmm3 + vblendvpd xmm2, xmm7, [rbx+r11*8-256], xmm3 + vblendvps xmm2, xmm7, xmm0, xmm3 + vblendvps xmm2, xmm7, [rbx], xmm3 + vblendvps xmm2, xmm7, [rbx+r11*8+256], xmm3 + vblendvps xmm2, xmm7, [rbx+r11*8-256], xmm3 + vbroadcastsd ymm16, xmm0 + vbroadcastsd ymm16, [rbx] + vbroadcastsd ymm16, [rbx+r11*8+256] + vbroadcastsd ymm16, [rbx+r11*8-256] + vbroadcastsd zmm24, xmm0 + vbroadcastsd zmm24, [rbx] + vbroadcastsd zmm24, [rbx+r11*8+256] + vbroadcastsd zmm24, [rbx+r11*8-256] + vbroadcastss xmm2, xmm0 + vbroadcastss xmm2, [rbx] + vbroadcastss xmm2, [rbx+r11*8+256] + vbroadcastss xmm2, [rbx+r11*8-256] + vbroadcastss ymm16, xmm0 + vbroadcastss ymm16, [rbx] + vbroadcastss ymm16, [rbx+r11*8+256] + vbroadcastss ymm16, [rbx+r11*8-256] + vbroadcastss zmm24, xmm0 + vbroadcastss zmm24, [rbx] + vbroadcastss zmm24, [rbx+r11*8+256] + vbroadcastss zmm24, [rbx+r11*8-256] + vcmppd xmm2, xmm7, xmm0, 0x90 + vcmppd xmm2, xmm7, [rbx], 0x90 + vcmppd xmm2, xmm7, [rbx+r11*8+256], 0x90 + vcmppd xmm2, xmm7, [rbx+r11*8-256], 0x90 + vcmpsd xmm2, xmm7, xmm0, 0x90 + vcmpsd xmm2, xmm7, [rbx], 0x90 + vcmpsd xmm2, xmm7, [rbx+r11*8+256], 0x90 + vcmpsd xmm2, xmm7, [rbx+r11*8-256], 0x90 + vcmpss xmm2, xmm7, xmm0, 0x90 + vcmpss xmm2, xmm7, [rbx], 0x90 + vcmpss xmm2, xmm7, [rbx+r11*8+256], 0x90 + vcmpss xmm2, xmm7, [rbx+r11*8-256], 0x90 + vcmpss xmm2, xmm7, xmm0, 0x90 + vcmpss xmm2, xmm7, [rbx], 0x90 + vcmpss xmm2, xmm7, [rbx+r11*8+256], 0x90 + vcmpss xmm2, xmm7, [rbx+r11*8-256], 0x90 + vcomisd xmm2, xmm0 + vcomisd xmm2, [rbx] + vcomisd xmm2, [rbx+r11*8+256] + vcomisd xmm2, [rbx+r11*8-256] + vcomiss xmm2, xmm0 + vcomiss xmm2, [rbx] + vcomiss xmm2, [rbx+r11*8+256] + vcomiss xmm2, [rbx+r11*8-256] + vcvtdq2pd xmm2, xmm0 + vcvtdq2pd xmm2, [rbx] + vcvtdq2pd xmm2, [rbx+r11*8+256] + vcvtdq2pd xmm2, [rbx+r11*8-256] + vcvtdq2pd ymm16, xmm0 + vcvtdq2pd ymm16, [rbx] + vcvtdq2pd ymm16, [rbx+r11*8+256] + vcvtdq2pd ymm16, [rbx+r11*8-256] + vcvtdq2pd zmm24, ymm15 + vcvtdq2pd zmm24, [rbx] + vcvtdq2pd zmm24, [rbx+r11*8+256] + vcvtdq2pd zmm24, [rbx+r11*8-256] + vcvtdq2pd xmm2, xmm0 + vcvtdq2pd xmm2, [rbx] + vcvtdq2pd xmm2, [rbx+r11*8+256] + vcvtdq2pd xmm2, [rbx+r11*8-256] + vcvtdq2pd ymm16, xmm0 + vcvtdq2pd ymm16, [rbx] + vcvtdq2pd ymm16, [rbx+r11*8+256] + vcvtdq2pd ymm16, [rbx+r11*8-256] + vcvtdq2pd zmm24, ymm15 + vcvtdq2pd zmm24, [rbx] + vcvtdq2pd zmm24, [rbx+r11*8+256] + vcvtdq2pd zmm24, [rbx+r11*8-256] + vcvtdq2ps xmm2, xmm0 + vcvtdq2ps xmm2, [rbx] + vcvtdq2ps xmm2, [rbx+r11*8+256] + vcvtdq2ps xmm2, [rbx+r11*8-256] + vcvtdq2ps ymm16, ymm15 + vcvtdq2ps ymm16, [rbx] + vcvtdq2ps ymm16, [rbx+r11*8+256] + vcvtdq2ps ymm16, [rbx+r11*8-256] + vcvtdq2ps zmm24, zmm31 + vcvtdq2ps zmm24, [rbx] + vcvtdq2ps zmm24, [rbx+r11*8+256] + vcvtdq2ps zmm24, [rbx+r11*8-256] + vcvtpd2dq xmm2, xmm0 + vcvtpd2dq xmm2, ymm15 + vcvtpd2dq xmm2, [rbx] + vcvtpd2dq xmm2, [rbx+r11*8+256] + vcvtpd2dq xmm2, [rbx+r11*8-256] + vcvtpd2dq ymm16, zmm31 + vcvtpd2dq ymm16, [rbx] + vcvtpd2dq ymm16, [rbx+r11*8+256] + vcvtpd2dq ymm16, [rbx+r11*8-256] + vcvtpd2ps xmm2, xmm0 + vcvtpd2ps xmm2, ymm15 + vcvtpd2ps xmm2, [rbx] + vcvtpd2ps xmm2, [rbx+r11*8+256] + vcvtpd2ps xmm2, [rbx+r11*8-256] + vcvtpd2ps ymm16, zmm31 + vcvtpd2ps ymm16, [rbx] + vcvtpd2ps ymm16, [rbx+r11*8+256] + vcvtpd2ps ymm16, [rbx+r11*8-256] + vcvtpd2ps xmm2, xmm0 + vcvtpd2ps xmm2, ymm15 + vcvtpd2ps xmm2, [rbx] + vcvtpd2ps xmm2, [rbx+r11*8+256] + vcvtpd2ps xmm2, [rbx+r11*8-256] + vcvtpd2ps ymm16, zmm31 + vcvtpd2ps ymm16, [rbx] + vcvtpd2ps ymm16, [rbx+r11*8+256] + vcvtpd2ps ymm16, [rbx+r11*8-256] + vcvtps2dq xmm2, xmm0 + vcvtps2dq xmm2, [rbx] + vcvtps2dq xmm2, [rbx+r11*8+256] + vcvtps2dq xmm2, [rbx+r11*8-256] + vcvtps2dq ymm16, ymm15 + vcvtps2dq ymm16, [rbx] + vcvtps2dq ymm16, [rbx+r11*8+256] + vcvtps2dq ymm16, [rbx+r11*8-256] + vcvtps2dq zmm24, zmm31 + vcvtps2dq zmm24, [rbx] + vcvtps2dq zmm24, [rbx+r11*8+256] + vcvtps2dq zmm24, [rbx+r11*8-256] + vcvtps2pd xmm2, xmm0 + vcvtps2pd xmm2, [rbx] + vcvtps2pd xmm2, [rbx+r11*8+256] + vcvtps2pd xmm2, [rbx+r11*8-256] + vcvtps2pd ymm16, xmm0 + vcvtps2pd ymm16, [rbx] + vcvtps2pd ymm16, [rbx+r11*8+256] + vcvtps2pd ymm16, [rbx+r11*8-256] + vcvtps2pd zmm24, ymm15 + vcvtps2pd zmm24, [rbx] + vcvtps2pd zmm24, [rbx+r11*8+256] + vcvtps2pd zmm24, [rbx+r11*8-256] + vcvtps2pd xmm2, xmm0 + vcvtps2pd xmm2, [rbx] + vcvtps2pd xmm2, [rbx+r11*8+256] + vcvtps2pd xmm2, [rbx+r11*8-256] + vcvtps2pd ymm16, xmm0 + vcvtps2pd ymm16, [rbx] + vcvtps2pd ymm16, [rbx+r11*8+256] + vcvtps2pd ymm16, [rbx+r11*8-256] + vcvtps2pd zmm24, ymm15 + vcvtps2pd zmm24, [rbx] + vcvtps2pd zmm24, [rbx+r11*8+256] + vcvtps2pd zmm24, [rbx+r11*8-256] + vcvtsd2si ecx, xmm0 + vcvtsd2si ecx, [rbx] + vcvtsd2si ecx, [rbx+r11*8+256] + vcvtsd2si ecx, [rbx+r11*8-256] + vcvtsd2si rcx, xmm0 + vcvtsd2si rcx, [rbx] + vcvtsd2si rcx, [rbx+r11*8+256] + vcvtsd2si rcx, [rbx+r11*8-256] + vcvtsd2ss xmm2, xmm7, xmm0 + vcvtsd2ss xmm2, xmm7, [rbx] + vcvtsd2ss xmm2, xmm7, [rbx+r11*8+256] + vcvtsd2ss xmm2, xmm7, [rbx+r11*8-256] + vcvtsi2sd xmm2, xmm7, ecx + vcvtsi2sd xmm2, xmm7, rcx + vcvtsi2sd xmm2, xmm7, [rbx] + vcvtsi2sd xmm2, xmm7, [rbx+rsi*8+256] + vcvtsi2ss xmm2, xmm7, ecx + vcvtsi2ss xmm2, xmm7, rcx + vcvtsi2ss xmm2, xmm7, [rbx] + vcvtsi2ss xmm2, xmm7, [rbx+rsi*8+256] + vcvtss2sd xmm2, xmm7, xmm0 + vcvtss2sd xmm2, xmm7, [rbx] + vcvtss2sd xmm2, xmm7, [rbx+r11*8+256] + vcvtss2sd xmm2, xmm7, [rbx+r11*8-256] + vcvtss2si ecx, xmm0 + vcvtss2si ecx, [rbx] + vcvtss2si ecx, [rbx+r11*8+256] + vcvtss2si ecx, [rbx+r11*8-256] + vcvtss2si rcx, xmm0 + vcvtss2si rcx, [rbx] + vcvtss2si rcx, [rbx+r11*8+256] + vcvtss2si rcx, [rbx+r11*8-256] + vcvttpd2dq xmm2, xmm0 + vcvttpd2dq xmm2, ymm15 + vcvttpd2dq xmm2, [rbx] + vcvttpd2dq xmm2, [rbx+r11*8+256] + vcvttpd2dq xmm2, [rbx+r11*8-256] + vcvttpd2dq ymm16, zmm31 + vcvttpd2dq ymm16, [rbx] + vcvttpd2dq ymm16, [rbx+r11*8+256] + vcvttpd2dq ymm16, [rbx+r11*8-256] + vcvttps2dq xmm2, xmm0 + vcvttps2dq xmm2, [rbx] + vcvttps2dq xmm2, [rbx+r11*8+256] + vcvttps2dq xmm2, [rbx+r11*8-256] + vcvttps2dq ymm16, ymm15 + vcvttps2dq ymm16, [rbx] + vcvttps2dq ymm16, [rbx+r11*8+256] + vcvttps2dq ymm16, [rbx+r11*8-256] + vcvttps2dq zmm24, zmm31 + vcvttps2dq zmm24, [rbx] + vcvttps2dq zmm24, [rbx+r11*8+256] + vcvttps2dq zmm24, [rbx+r11*8-256] + vcvttsd2si ecx, xmm0 + vcvttsd2si ecx, [rbx] + vcvttsd2si ecx, [rbx+r11*8+256] + vcvttsd2si ecx, [rbx+r11*8-256] + vcvttsd2si rcx, xmm0 + vcvttsd2si rcx, [rbx] + vcvttsd2si rcx, [rbx+r11*8+256] + vcvttsd2si rcx, [rbx+r11*8-256] + vcvttss2si ecx, xmm0 + vcvttss2si ecx, [rbx] + vcvttss2si ecx, [rbx+r11*8+256] + vcvttss2si ecx, [rbx+r11*8-256] + vcvttss2si rcx, xmm0 + vcvttss2si rcx, [rbx] + vcvttss2si rcx, [rbx+r11*8+256] + vcvttss2si rcx, [rbx+r11*8-256] + vdivpd xmm2, xmm7, xmm0 + vdivpd xmm2, xmm7, [rbx] + vdivpd xmm2, xmm7, [rbx+r11*8+256] + vdivpd xmm2, xmm7, [rbx+r11*8-256] + vdivpd ymm16, ymm13, ymm15 + vdivpd ymm16, ymm13, [rbx] + vdivpd ymm16, ymm13, [rbx+r11*8+256] + vdivpd ymm16, ymm13, [rbx+r11*8-256] + vdivpd zmm24, zmm24, zmm31 + vdivpd zmm24, zmm24, [rbx] + vdivpd zmm24, zmm24, [rbx+r11*8+256] + vdivpd zmm24, zmm24, [rbx+r11*8-256] + vdivps xmm2, xmm7, xmm0 + vdivps xmm2, xmm7, [rbx] + vdivps xmm2, xmm7, [rbx+r11*8+256] + vdivps xmm2, xmm7, [rbx+r11*8-256] + vdivps ymm16, ymm13, ymm15 + vdivps ymm16, ymm13, [rbx] + vdivps ymm16, ymm13, [rbx+r11*8+256] + vdivps ymm16, ymm13, [rbx+r11*8-256] + vdivps zmm24, zmm24, zmm31 + vdivps zmm24, zmm24, [rbx] + vdivps zmm24, zmm24, [rbx+r11*8+256] + vdivps zmm24, zmm24, [rbx+r11*8-256] + vdivsd xmm2, xmm7, xmm0 + vdivsd xmm2, xmm7, [rbx] + vdivsd xmm2, xmm7, [rbx+r11*8+256] + vdivsd xmm2, xmm7, [rbx+r11*8-256] + vdivss xmm2, xmm7, xmm0 + vdivss xmm2, xmm7, [rbx] + vdivss xmm2, xmm7, [rbx+r11*8+256] + vdivss xmm2, xmm7, [rbx+r11*8-256] + vdppd xmm2, xmm7, xmm0, 0x90 + vdppd xmm2, xmm7, [rbx], 0x90 + vdppd xmm2, xmm7, [rbx+r11*8+256], 0x90 + vdppd xmm2, xmm7, [rbx+r11*8-256], 0x90 + vdpps xmm2, xmm7, xmm0, 0x90 + vdpps xmm2, xmm7, [rbx], 0x90 + vdpps xmm2, xmm7, [rbx+r11*8+256], 0x90 + vdpps xmm2, xmm7, [rbx+r11*8-256], 0x90 + vextractps [rbx], xmm2, 0x90 + vextractps [rbx+rsi*8+256], xmm2, 0x90 + vextractps [rbx+rsi*8-256], xmm2, 0x90 + vextractps ecx, xmm2, 0x90 + vextractps rcx, xmm2, 0x90 + vhaddpd xmm2, xmm7, xmm0 + vhaddpd xmm2, xmm7, [rbx] + vhaddpd xmm2, xmm7, [rbx+r11*8+256] + vhaddpd xmm2, xmm7, [rbx+r11*8-256] + vhaddps xmm2, xmm7, xmm0 + vhaddps xmm2, xmm7, [rbx] + vhaddps xmm2, xmm7, [rbx+r11*8+256] + vhaddps xmm2, xmm7, [rbx+r11*8-256] + vhsubpd xmm2, xmm7, xmm0 + vhsubpd xmm2, xmm7, [rbx] + vhsubpd xmm2, xmm7, [rbx+r11*8+256] + vhsubpd xmm2, xmm7, [rbx+r11*8-256] + vhsubps xmm2, xmm7, xmm0 + vhsubps xmm2, xmm7, [rbx] + vhsubps xmm2, xmm7, [rbx+r11*8+256] + vhsubps xmm2, xmm7, [rbx+r11*8-256] + vinsertps xmm2, xmm7, [rbx], 0x90 + vinsertps xmm2, xmm7, [rbx+rsi*8+256], 0x90 + vinsertps xmm2, xmm7, [rbx+rsi*8-256], 0x90 + vinsertps xmm2, xmm7, xmm0, 0x90 + vlddqu xmm2, [rbx] + vlddqu xmm2, [rbx+rsi*8+256] + vlddqu xmm2, [rbx+rsi*8-256] + vldmxcsr [rbx] + vldmxcsr [rbx+rsi*8+256] + vldmxcsr [rbx+rsi*8-256] + vmaskmovdqu xmm2, xmm0 + vmaskmovpd xmm2, xmm7, [rbx] + vmaskmovpd xmm2, xmm7, [rbx+rsi*8+256] + vmaskmovpd xmm2, xmm7, [rbx+rsi*8-256] + vmaskmovpd [rbx], xmm7, xmm2 + vmaskmovpd [rbx+rsi*8+256], xmm7, xmm2 + vmaskmovpd [rbx+rsi*8-256], xmm7, xmm2 + vmaskmovps xmm2, xmm7, [rbx] + vmaskmovps xmm2, xmm7, [rbx+rsi*8+256] + vmaskmovps xmm2, xmm7, [rbx+rsi*8-256] + vmaskmovps [rbx], xmm7, xmm2 + vmaskmovps [rbx+rsi*8+256], xmm7, xmm2 + vmaskmovps [rbx+rsi*8-256], xmm7, xmm2 + vmaxpd xmm2, xmm7, xmm0 + vmaxpd xmm2, xmm7, [rbx] + vmaxpd xmm2, xmm7, [rbx+r11*8+256] + vmaxpd xmm2, xmm7, [rbx+r11*8-256] + vmaxpd ymm16, ymm13, ymm15 + vmaxpd ymm16, ymm13, [rbx] + vmaxpd ymm16, ymm13, [rbx+r11*8+256] + vmaxpd ymm16, ymm13, [rbx+r11*8-256] + vmaxpd zmm24, zmm24, zmm31 + vmaxpd zmm24, zmm24, [rbx] + vmaxpd zmm24, zmm24, [rbx+r11*8+256] + vmaxpd zmm24, zmm24, [rbx+r11*8-256] + vmaxps xmm2, xmm7, xmm0 + vmaxps xmm2, xmm7, [rbx] + vmaxps xmm2, xmm7, [rbx+r11*8+256] + vmaxps xmm2, xmm7, [rbx+r11*8-256] + vmaxps ymm16, ymm13, ymm15 + vmaxps ymm16, ymm13, [rbx] + vmaxps ymm16, ymm13, [rbx+r11*8+256] + vmaxps ymm16, ymm13, [rbx+r11*8-256] + vmaxps zmm24, zmm24, zmm31 + vmaxps zmm24, zmm24, [rbx] + vmaxps zmm24, zmm24, [rbx+r11*8+256] + vmaxps zmm24, zmm24, [rbx+r11*8-256] + vmaxsd xmm2, xmm7, xmm0 + vmaxsd xmm2, xmm7, [rbx] + vmaxsd xmm2, xmm7, [rbx+r11*8+256] + vmaxsd xmm2, xmm7, [rbx+r11*8-256] + vmaxss xmm2, xmm7, xmm0 + vmaxss xmm2, xmm7, [rbx] + vmaxss xmm2, xmm7, [rbx+r11*8+256] + vmaxss xmm2, xmm7, [rbx+r11*8-256] + vminpd xmm2, xmm7, xmm0 + vminpd xmm2, xmm7, [rbx] + vminpd xmm2, xmm7, [rbx+r11*8+256] + vminpd xmm2, xmm7, [rbx+r11*8-256] + vminpd ymm16, ymm13, ymm15 + vminpd ymm16, ymm13, [rbx] + vminpd ymm16, ymm13, [rbx+r11*8+256] + vminpd ymm16, ymm13, [rbx+r11*8-256] + vminpd zmm24, zmm24, zmm31 + vminpd zmm24, zmm24, [rbx] + vminpd zmm24, zmm24, [rbx+r11*8+256] + vminpd zmm24, zmm24, [rbx+r11*8-256] + vminps xmm2, xmm7, xmm0 + vminps xmm2, xmm7, [rbx] + vminps xmm2, xmm7, [rbx+r11*8+256] + vminps xmm2, xmm7, [rbx+r11*8-256] + vminps ymm16, ymm13, ymm15 + vminps ymm16, ymm13, [rbx] + vminps ymm16, ymm13, [rbx+r11*8+256] + vminps ymm16, ymm13, [rbx+r11*8-256] + vminps zmm24, zmm24, zmm31 + vminps zmm24, zmm24, [rbx] + vminps zmm24, zmm24, [rbx+r11*8+256] + vminps zmm24, zmm24, [rbx+r11*8-256] + vminsd xmm2, xmm7, xmm0 + vminsd xmm2, xmm7, [rbx] + vminsd xmm2, xmm7, [rbx+r11*8+256] + vminsd xmm2, xmm7, [rbx+r11*8-256] + vminss xmm2, xmm7, xmm0 + vminss xmm2, xmm7, [rbx] + vminss xmm2, xmm7, [rbx+r11*8+256] + vminss xmm2, xmm7, [rbx+r11*8-256] + vmovapd xmm2, xmm0 + vmovapd xmm2, [rbx] + vmovapd xmm2, [rbx+r11*8+256] + vmovapd xmm2, [rbx+r11*8-256] + vmovapd ymm16, ymm15 + vmovapd ymm16, [rbx] + vmovapd ymm16, [rbx+r11*8+256] + vmovapd ymm16, [rbx+r11*8-256] + vmovapd zmm24, zmm31 + vmovapd zmm24, [rbx] + vmovapd zmm24, [rbx+r11*8+256] + vmovapd zmm24, [rbx+r11*8-256] + vmovapd xmm0, xmm2 + vmovapd ymm15, ymm16 + vmovapd zmm31, zmm24 + vmovapd [rbx], xmm2 + vmovapd [rbx], ymm16 + vmovapd [rbx], zmm24 + vmovapd [rbx+r11*8+256], xmm2 + vmovapd [rbx+r11*8+256], ymm16 + vmovapd [rbx+r11*8+256], zmm24 + vmovapd [rbx+r11*8-256], xmm2 + vmovapd [rbx+r11*8-256], ymm16 + vmovapd [rbx+r11*8-256], zmm24 + vmovaps xmm2, xmm0 + vmovaps xmm2, [rbx] + vmovaps xmm2, [rbx+r11*8+256] + vmovaps xmm2, [rbx+r11*8-256] + vmovaps ymm16, ymm15 + vmovaps ymm16, [rbx] + vmovaps ymm16, [rbx+r11*8+256] + vmovaps ymm16, [rbx+r11*8-256] + vmovaps zmm24, zmm31 + vmovaps zmm24, [rbx] + vmovaps zmm24, [rbx+r11*8+256] + vmovaps zmm24, [rbx+r11*8-256] + vmovaps xmm0, xmm2 + vmovaps ymm15, ymm16 + vmovaps zmm31, zmm24 + vmovaps [rbx], xmm2 + vmovaps [rbx], ymm16 + vmovaps [rbx], zmm24 + vmovaps [rbx+r11*8+256], xmm2 + vmovaps [rbx+r11*8+256], ymm16 + vmovaps [rbx+r11*8+256], zmm24 + vmovaps [rbx+r11*8-256], xmm2 + vmovaps [rbx+r11*8-256], ymm16 + vmovaps [rbx+r11*8-256], zmm24 + vmovd xmm2, ecx + vmovd xmm2, [rbx] + vmovd xmm2, [rbx+rsi*8+256] + vmovd ecx, xmm2 + vmovd [rbx], xmm2 + vmovd [rbx+rsi*8+256], xmm2 + vmovddup xmm2, xmm0 + vmovddup xmm2, [rbx] + vmovddup xmm2, [rbx+r11*8+256] + vmovddup xmm2, [rbx+r11*8-256] + vmovddup ymm16, ymm15 + vmovddup ymm16, [rbx] + vmovddup ymm16, [rbx+r11*8+256] + vmovddup ymm16, [rbx+r11*8-256] + vmovddup zmm24, zmm31 + vmovddup zmm24, [rbx] + vmovddup zmm24, [rbx+r11*8+256] + vmovddup zmm24, [rbx+r11*8-256] + vmovddup xmm2, xmm0 + vmovddup xmm2, [rbx] + vmovddup xmm2, [rbx+r11*8+256] + vmovddup xmm2, [rbx+r11*8-256] + vmovddup ymm16, ymm15 + vmovddup ymm16, [rbx] + vmovddup ymm16, [rbx+r11*8+256] + vmovddup ymm16, [rbx+r11*8-256] + vmovddup zmm24, zmm31 + vmovddup zmm24, [rbx] + vmovddup zmm24, [rbx+r11*8+256] + vmovddup zmm24, [rbx+r11*8-256] + vmovdqa xmm2, xmm0 + vmovdqa xmm2, [rbx] + vmovdqa xmm2, [rbx+r11*8+256] + vmovdqa xmm2, [rbx+r11*8-256] + vmovdqa xmm0, xmm2 + vmovdqa [rbx], xmm2 + vmovdqa [rbx+r11*8+256], xmm2 + vmovdqa [rbx+r11*8-256], xmm2 + vmovdqu xmm2, xmm0 + vmovdqu xmm2, [rbx] + vmovdqu xmm2, [rbx+r11*8+256] + vmovdqu xmm2, [rbx+r11*8-256] + vmovdqu xmm0, xmm2 + vmovdqu [rbx], xmm2 + vmovdqu [rbx+r11*8+256], xmm2 + vmovdqu [rbx+r11*8-256], xmm2 + vmovhlps xmm2, xmm7, xmm0 + vmovhpd xmm2, xmm7, [rbx] + vmovhpd xmm2, xmm7, [rbx+rsi*8+256] + vmovhpd xmm2, xmm7, [rbx+rsi*8-256] + vmovhpd [rbx], xmm2 + vmovhpd [rbx+rsi*8+256], xmm2 + vmovhpd [rbx+rsi*8-256], xmm2 + vmovhps xmm2, xmm7, [rbx] + vmovhps xmm2, xmm7, [rbx+rsi*8+256] + vmovhps xmm2, xmm7, [rbx+rsi*8-256] + vmovhps [rbx], xmm2 + vmovhps [rbx+rsi*8+256], xmm2 + vmovhps [rbx+rsi*8-256], xmm2 + vmovlhps xmm2, xmm7, xmm0 + vmovlpd xmm2, xmm7, [rbx] + vmovlpd xmm2, xmm7, [rbx+rsi*8+256] + vmovlpd xmm2, xmm7, [rbx+rsi*8-256] + vmovlpd [rbx], xmm2 + vmovlpd [rbx+rsi*8+256], xmm2 + vmovlpd [rbx+rsi*8-256], xmm2 + vmovlps xmm2, xmm7, [rbx] + vmovlps xmm2, xmm7, [rbx+rsi*8+256] + vmovlps xmm2, xmm7, [rbx+rsi*8-256] + vmovlps [rbx], xmm2 + vmovlps [rbx+rsi*8+256], xmm2 + vmovlps [rbx+rsi*8-256], xmm2 + vmovmskpd ecx, xmm0 + vmovmskpd ecx, ymm15 + vmovmskpd rcx, xmm0 + vmovmskpd rcx, ymm15 + vmovmskps ecx, xmm0 + vmovmskps ecx, ymm15 + vmovmskps rcx, xmm0 + vmovmskps rcx, ymm15 + vmovntdq [rbx], xmm2 + vmovntdq [rbx], ymm16 + vmovntdq [rbx], zmm24 + vmovntdq [rbx+rsi*8+256], xmm2 + vmovntdq [rbx+rsi*8+256], ymm16 + vmovntdq [rbx+rsi*8+256], zmm24 + vmovntdq [rbx+rsi*8-256], xmm2 + vmovntdq [rbx+rsi*8-256], ymm16 + vmovntdq [rbx+rsi*8-256], zmm24 + vmovntdqa xmm2, [rbx] + vmovntdqa xmm2, [rbx+rsi*8+256] + vmovntdqa xmm2, [rbx+rsi*8-256] + vmovntdqa ymm16, [rbx] + vmovntdqa ymm16, [rbx+rsi*8+256] + vmovntdqa ymm16, [rbx+rsi*8-256] + vmovntdqa zmm24, [rbx] + vmovntdqa zmm24, [rbx+rsi*8+256] + vmovntdqa zmm24, [rbx+rsi*8-256] + vmovntpd [rbx], xmm2 + vmovntpd [rbx], ymm16 + vmovntpd [rbx], zmm24 + vmovntpd [rbx+rsi*8+256], xmm2 + vmovntpd [rbx+rsi*8+256], ymm16 + vmovntpd [rbx+rsi*8+256], zmm24 + vmovntpd [rbx+rsi*8-256], xmm2 + vmovntpd [rbx+rsi*8-256], ymm16 + vmovntpd [rbx+rsi*8-256], zmm24 + vmovntps [rbx], xmm2 + vmovntps [rbx], ymm16 + vmovntps [rbx], zmm24 + vmovntps [rbx+rsi*8+256], xmm2 + vmovntps [rbx+rsi*8+256], ymm16 + vmovntps [rbx+rsi*8+256], zmm24 + vmovntps [rbx+rsi*8-256], xmm2 + vmovntps [rbx+rsi*8-256], ymm16 + vmovntps [rbx+rsi*8-256], zmm24 + vmovq xmm2, rcx + vmovq xmm2, [rbx] + vmovq xmm2, [rbx+rsi*8+256] + vmovq rcx, xmm2 + vmovq [rbx], xmm2 + vmovq [rbx+rsi*8+256], xmm2 + vmovq xmm2, xmm0 + vmovq xmm2, [rbx] + vmovq xmm2, [rbx+r11*8+256] + vmovq xmm2, [rbx+r11*8-256] + vmovq xmm0, xmm2 + vmovq [rbx], xmm2 + vmovq [rbx+r11*8+256], xmm2 + vmovq [rbx+r11*8-256], xmm2 + vmovsd xmm2, xmm7, xmm0 + vmovsd xmm2, [rbx] + vmovsd xmm2, [rbx+rsi*8+256] + vmovsd xmm2, [rbx+rsi*8-256] + vmovsd xmm0, xmm7, xmm2 + vmovsd [rbx], xmm2 + vmovsd [rbx+rsi*8+256], xmm2 + vmovsd [rbx+rsi*8-256], xmm2 + vmovshdup xmm2, xmm0 + vmovshdup xmm2, [rbx] + vmovshdup xmm2, [rbx+r11*8+256] + vmovshdup xmm2, [rbx+r11*8-256] + vmovshdup ymm16, ymm15 + vmovshdup ymm16, [rbx] + vmovshdup ymm16, [rbx+r11*8+256] + vmovshdup ymm16, [rbx+r11*8-256] + vmovshdup zmm24, zmm31 + vmovshdup zmm24, [rbx] + vmovshdup zmm24, [rbx+r11*8+256] + vmovshdup zmm24, [rbx+r11*8-256] + vmovsldup xmm2, xmm0 + vmovsldup xmm2, [rbx] + vmovsldup xmm2, [rbx+r11*8+256] + vmovsldup xmm2, [rbx+r11*8-256] + vmovsldup ymm16, ymm15 + vmovsldup ymm16, [rbx] + vmovsldup ymm16, [rbx+r11*8+256] + vmovsldup ymm16, [rbx+r11*8-256] + vmovsldup zmm24, zmm31 + vmovsldup zmm24, [rbx] + vmovsldup zmm24, [rbx+r11*8+256] + vmovsldup zmm24, [rbx+r11*8-256] + vmovss xmm2, xmm7, xmm0 + vmovss xmm2, [rbx] + vmovss xmm2, [rbx+rsi*8+256] + vmovss xmm2, [rbx+rsi*8-256] + vmovss xmm0, xmm7, xmm2 + vmovss [rbx], xmm2 + vmovss [rbx+rsi*8+256], xmm2 + vmovss [rbx+rsi*8-256], xmm2 + vmovupd xmm2, xmm0 + vmovupd xmm2, [rbx] + vmovupd xmm2, [rbx+r11*8+256] + vmovupd xmm2, [rbx+r11*8-256] + vmovupd ymm16, ymm15 + vmovupd ymm16, [rbx] + vmovupd ymm16, [rbx+r11*8+256] + vmovupd ymm16, [rbx+r11*8-256] + vmovupd zmm24, zmm31 + vmovupd zmm24, [rbx] + vmovupd zmm24, [rbx+r11*8+256] + vmovupd zmm24, [rbx+r11*8-256] + vmovupd xmm0, xmm2 + vmovupd ymm15, ymm16 + vmovupd zmm31, zmm24 + vmovupd [rbx], xmm2 + vmovupd [rbx], ymm16 + vmovupd [rbx], zmm24 + vmovupd [rbx+r11*8+256], xmm2 + vmovupd [rbx+r11*8+256], ymm16 + vmovupd [rbx+r11*8+256], zmm24 + vmovupd [rbx+r11*8-256], xmm2 + vmovupd [rbx+r11*8-256], ymm16 + vmovupd [rbx+r11*8-256], zmm24 + vmovups xmm2, xmm0 + vmovups xmm2, [rbx] + vmovups xmm2, [rbx+r11*8+256] + vmovups xmm2, [rbx+r11*8-256] + vmovups ymm16, ymm15 + vmovups ymm16, [rbx] + vmovups ymm16, [rbx+r11*8+256] + vmovups ymm16, [rbx+r11*8-256] + vmovups zmm24, zmm31 + vmovups zmm24, [rbx] + vmovups zmm24, [rbx+r11*8+256] + vmovups zmm24, [rbx+r11*8-256] + vmovups xmm0, xmm2 + vmovups ymm15, ymm16 + vmovups zmm31, zmm24 + vmovups [rbx], xmm2 + vmovups [rbx], ymm16 + vmovups [rbx], zmm24 + vmovups [rbx+r11*8+256], xmm2 + vmovups [rbx+r11*8+256], ymm16 + vmovups [rbx+r11*8+256], zmm24 + vmovups [rbx+r11*8-256], xmm2 + vmovups [rbx+r11*8-256], ymm16 + vmovups [rbx+r11*8-256], zmm24 + vmpsadbw xmm2, xmm7, xmm0, 0x90 + vmpsadbw xmm2, xmm7, [rbx], 0x90 + vmpsadbw xmm2, xmm7, [rbx+r11*8+256], 0x90 + vmpsadbw xmm2, xmm7, [rbx+r11*8-256], 0x90 + vmulpd xmm2, xmm7, xmm0 + vmulpd xmm2, xmm7, [rbx] + vmulpd xmm2, xmm7, [rbx+r11*8+256] + vmulpd xmm2, xmm7, [rbx+r11*8-256] + vmulpd ymm16, ymm13, ymm15 + vmulpd ymm16, ymm13, [rbx] + vmulpd ymm16, ymm13, [rbx+r11*8+256] + vmulpd ymm16, ymm13, [rbx+r11*8-256] + vmulpd zmm24, zmm24, zmm31 + vmulpd zmm24, zmm24, [rbx] + vmulpd zmm24, zmm24, [rbx+r11*8+256] + vmulpd zmm24, zmm24, [rbx+r11*8-256] + vmulps xmm2, xmm7, xmm0 + vmulps xmm2, xmm7, [rbx] + vmulps xmm2, xmm7, [rbx+r11*8+256] + vmulps xmm2, xmm7, [rbx+r11*8-256] + vmulps ymm16, ymm13, ymm15 + vmulps ymm16, ymm13, [rbx] + vmulps ymm16, ymm13, [rbx+r11*8+256] + vmulps ymm16, ymm13, [rbx+r11*8-256] + vmulps zmm24, zmm24, zmm31 + vmulps zmm24, zmm24, [rbx] + vmulps zmm24, zmm24, [rbx+r11*8+256] + vmulps zmm24, zmm24, [rbx+r11*8-256] + vmulsd xmm2, xmm7, xmm0 + vmulsd xmm2, xmm7, [rbx] + vmulsd xmm2, xmm7, [rbx+r11*8+256] + vmulsd xmm2, xmm7, [rbx+r11*8-256] + vmulss xmm2, xmm7, xmm0 + vmulss xmm2, xmm7, [rbx] + vmulss xmm2, xmm7, [rbx+r11*8+256] + vmulss xmm2, xmm7, [rbx+r11*8-256] + vorpd xmm2, xmm7, xmm0 + vorpd xmm2, xmm7, [rbx] + vorpd xmm2, xmm7, [rbx+r11*8+256] + vorpd xmm2, xmm7, [rbx+r11*8-256] + vorpd ymm16, ymm13, ymm15 + vorpd ymm16, ymm13, [rbx] + vorpd ymm16, ymm13, [rbx+r11*8+256] + vorpd ymm16, ymm13, [rbx+r11*8-256] + vorpd zmm24, zmm24, zmm31 + vorpd zmm24, zmm24, [rbx] + vorpd zmm24, zmm24, [rbx+r11*8+256] + vorpd zmm24, zmm24, [rbx+r11*8-256] + vorps xmm2, xmm7, xmm0 + vorps xmm2, xmm7, [rbx] + vorps xmm2, xmm7, [rbx+r11*8+256] + vorps xmm2, xmm7, [rbx+r11*8-256] + vorps ymm16, ymm13, ymm15 + vorps ymm16, ymm13, [rbx] + vorps ymm16, ymm13, [rbx+r11*8+256] + vorps ymm16, ymm13, [rbx+r11*8-256] + vorps zmm24, zmm24, zmm31 + vorps zmm24, zmm24, [rbx] + vorps zmm24, zmm24, [rbx+r11*8+256] + vorps zmm24, zmm24, [rbx+r11*8-256] + vpabsb xmm2, xmm0 + vpabsb xmm2, [rbx] + vpabsb xmm2, [rbx+r11*8+256] + vpabsb xmm2, [rbx+r11*8-256] + vpabsb ymm16, ymm15 + vpabsb ymm16, [rbx] + vpabsb ymm16, [rbx+r11*8+256] + vpabsb ymm16, [rbx+r11*8-256] + vpabsb zmm24, zmm31 + vpabsb zmm24, [rbx] + vpabsb zmm24, [rbx+r11*8+256] + vpabsb zmm24, [rbx+r11*8-256] + vpabsd xmm2, xmm0 + vpabsd xmm2, [rbx] + vpabsd xmm2, [rbx+r11*8+256] + vpabsd xmm2, [rbx+r11*8-256] + vpabsd ymm16, ymm15 + vpabsd ymm16, [rbx] + vpabsd ymm16, [rbx+r11*8+256] + vpabsd ymm16, [rbx+r11*8-256] + vpabsd zmm24, zmm31 + vpabsd zmm24, [rbx] + vpabsd zmm24, [rbx+r11*8+256] + vpabsd zmm24, [rbx+r11*8-256] + vpabsw xmm2, xmm0 + vpabsw xmm2, [rbx] + vpabsw xmm2, [rbx+r11*8+256] + vpabsw xmm2, [rbx+r11*8-256] + vpabsw ymm16, ymm15 + vpabsw ymm16, [rbx] + vpabsw ymm16, [rbx+r11*8+256] + vpabsw ymm16, [rbx+r11*8-256] + vpabsw zmm24, zmm31 + vpabsw zmm24, [rbx] + vpabsw zmm24, [rbx+r11*8+256] + vpabsw zmm24, [rbx+r11*8-256] + vpackssdw xmm2, xmm7, xmm0 + vpackssdw xmm2, xmm7, [rbx] + vpackssdw xmm2, xmm7, [rbx+r11*8+256] + vpackssdw xmm2, xmm7, [rbx+r11*8-256] + vpackssdw ymm16, ymm13, ymm15 + vpackssdw ymm16, ymm13, [rbx] + vpackssdw ymm16, ymm13, [rbx+r11*8+256] + vpackssdw ymm16, ymm13, [rbx+r11*8-256] + vpackssdw zmm24, zmm24, zmm31 + vpackssdw zmm24, zmm24, [rbx] + vpackssdw zmm24, zmm24, [rbx+r11*8+256] + vpackssdw zmm24, zmm24, [rbx+r11*8-256] + vpacksswb xmm2, xmm7, xmm0 + vpacksswb xmm2, xmm7, [rbx] + vpacksswb xmm2, xmm7, [rbx+r11*8+256] + vpacksswb xmm2, xmm7, [rbx+r11*8-256] + vpacksswb ymm16, ymm13, ymm15 + vpacksswb ymm16, ymm13, [rbx] + vpacksswb ymm16, ymm13, [rbx+r11*8+256] + vpacksswb ymm16, ymm13, [rbx+r11*8-256] + vpacksswb zmm24, zmm24, zmm31 + vpacksswb zmm24, zmm24, [rbx] + vpacksswb zmm24, zmm24, [rbx+r11*8+256] + vpacksswb zmm24, zmm24, [rbx+r11*8-256] + vpackusdw xmm2, xmm7, xmm0 + vpackusdw xmm2, xmm7, [rbx] + vpackusdw xmm2, xmm7, [rbx+r11*8+256] + vpackusdw xmm2, xmm7, [rbx+r11*8-256] + vpackusdw ymm16, ymm13, ymm15 + vpackusdw ymm16, ymm13, [rbx] + vpackusdw ymm16, ymm13, [rbx+r11*8+256] + vpackusdw ymm16, ymm13, [rbx+r11*8-256] + vpackusdw zmm24, zmm24, zmm31 + vpackusdw zmm24, zmm24, [rbx] + vpackusdw zmm24, zmm24, [rbx+r11*8+256] + vpackusdw zmm24, zmm24, [rbx+r11*8-256] + vpackuswb xmm2, xmm7, xmm0 + vpackuswb xmm2, xmm7, [rbx] + vpackuswb xmm2, xmm7, [rbx+r11*8+256] + vpackuswb xmm2, xmm7, [rbx+r11*8-256] + vpackuswb ymm16, ymm13, ymm15 + vpackuswb ymm16, ymm13, [rbx] + vpackuswb ymm16, ymm13, [rbx+r11*8+256] + vpackuswb ymm16, ymm13, [rbx+r11*8-256] + vpackuswb zmm24, zmm24, zmm31 + vpackuswb zmm24, zmm24, [rbx] + vpackuswb zmm24, zmm24, [rbx+r11*8+256] + vpackuswb zmm24, zmm24, [rbx+r11*8-256] + vpaddb xmm2, xmm7, xmm0 + vpaddb xmm2, xmm7, [rbx] + vpaddb xmm2, xmm7, [rbx+r11*8+256] + vpaddb xmm2, xmm7, [rbx+r11*8-256] + vpaddb ymm16, ymm13, ymm15 + vpaddb ymm16, ymm13, [rbx] + vpaddb ymm16, ymm13, [rbx+r11*8+256] + vpaddb ymm16, ymm13, [rbx+r11*8-256] + vpaddb zmm24, zmm24, zmm31 + vpaddb zmm24, zmm24, [rbx] + vpaddb zmm24, zmm24, [rbx+r11*8+256] + vpaddb zmm24, zmm24, [rbx+r11*8-256] + vpaddd xmm2, xmm7, xmm0 + vpaddd xmm2, xmm7, [rbx] + vpaddd xmm2, xmm7, [rbx+r11*8+256] + vpaddd xmm2, xmm7, [rbx+r11*8-256] + vpaddd ymm16, ymm13, ymm15 + vpaddd ymm16, ymm13, [rbx] + vpaddd ymm16, ymm13, [rbx+r11*8+256] + vpaddd ymm16, ymm13, [rbx+r11*8-256] + vpaddd zmm24, zmm24, zmm31 + vpaddd zmm24, zmm24, [rbx] + vpaddd zmm24, zmm24, [rbx+r11*8+256] + vpaddd zmm24, zmm24, [rbx+r11*8-256] + vpaddq xmm2, xmm7, xmm0 + vpaddq xmm2, xmm7, [rbx] + vpaddq xmm2, xmm7, [rbx+r11*8+256] + vpaddq xmm2, xmm7, [rbx+r11*8-256] + vpaddq ymm16, ymm13, ymm15 + vpaddq ymm16, ymm13, [rbx] + vpaddq ymm16, ymm13, [rbx+r11*8+256] + vpaddq ymm16, ymm13, [rbx+r11*8-256] + vpaddq zmm24, zmm24, zmm31 + vpaddq zmm24, zmm24, [rbx] + vpaddq zmm24, zmm24, [rbx+r11*8+256] + vpaddq zmm24, zmm24, [rbx+r11*8-256] + vpaddsb xmm2, xmm7, xmm0 + vpaddsb xmm2, xmm7, [rbx] + vpaddsb xmm2, xmm7, [rbx+r11*8+256] + vpaddsb xmm2, xmm7, [rbx+r11*8-256] + vpaddsb ymm16, ymm13, ymm15 + vpaddsb ymm16, ymm13, [rbx] + vpaddsb ymm16, ymm13, [rbx+r11*8+256] + vpaddsb ymm16, ymm13, [rbx+r11*8-256] + vpaddsb zmm24, zmm24, zmm31 + vpaddsb zmm24, zmm24, [rbx] + vpaddsb zmm24, zmm24, [rbx+r11*8+256] + vpaddsb zmm24, zmm24, [rbx+r11*8-256] + vpaddsw xmm2, xmm7, xmm0 + vpaddsw xmm2, xmm7, [rbx] + vpaddsw xmm2, xmm7, [rbx+r11*8+256] + vpaddsw xmm2, xmm7, [rbx+r11*8-256] + vpaddsw ymm16, ymm13, ymm15 + vpaddsw ymm16, ymm13, [rbx] + vpaddsw ymm16, ymm13, [rbx+r11*8+256] + vpaddsw ymm16, ymm13, [rbx+r11*8-256] + vpaddsw zmm24, zmm24, zmm31 + vpaddsw zmm24, zmm24, [rbx] + vpaddsw zmm24, zmm24, [rbx+r11*8+256] + vpaddsw zmm24, zmm24, [rbx+r11*8-256] + vpaddusb xmm2, xmm7, xmm0 + vpaddusb xmm2, xmm7, [rbx] + vpaddusb xmm2, xmm7, [rbx+r11*8+256] + vpaddusb xmm2, xmm7, [rbx+r11*8-256] + vpaddusb ymm16, ymm13, ymm15 + vpaddusb ymm16, ymm13, [rbx] + vpaddusb ymm16, ymm13, [rbx+r11*8+256] + vpaddusb ymm16, ymm13, [rbx+r11*8-256] + vpaddusb zmm24, zmm24, zmm31 + vpaddusb zmm24, zmm24, [rbx] + vpaddusb zmm24, zmm24, [rbx+r11*8+256] + vpaddusb zmm24, zmm24, [rbx+r11*8-256] + vpaddusw xmm2, xmm7, xmm0 + vpaddusw xmm2, xmm7, [rbx] + vpaddusw xmm2, xmm7, [rbx+r11*8+256] + vpaddusw xmm2, xmm7, [rbx+r11*8-256] + vpaddusw ymm16, ymm13, ymm15 + vpaddusw ymm16, ymm13, [rbx] + vpaddusw ymm16, ymm13, [rbx+r11*8+256] + vpaddusw ymm16, ymm13, [rbx+r11*8-256] + vpaddusw zmm24, zmm24, zmm31 + vpaddusw zmm24, zmm24, [rbx] + vpaddusw zmm24, zmm24, [rbx+r11*8+256] + vpaddusw zmm24, zmm24, [rbx+r11*8-256] + vpaddw xmm2, xmm7, xmm0 + vpaddw xmm2, xmm7, [rbx] + vpaddw xmm2, xmm7, [rbx+r11*8+256] + vpaddw xmm2, xmm7, [rbx+r11*8-256] + vpaddw ymm16, ymm13, ymm15 + vpaddw ymm16, ymm13, [rbx] + vpaddw ymm16, ymm13, [rbx+r11*8+256] + vpaddw ymm16, ymm13, [rbx+r11*8-256] + vpaddw zmm24, zmm24, zmm31 + vpaddw zmm24, zmm24, [rbx] + vpaddw zmm24, zmm24, [rbx+r11*8+256] + vpaddw zmm24, zmm24, [rbx+r11*8-256] + vpalignr xmm2, xmm7, xmm0, 0x90 + vpalignr xmm2, xmm7, [rbx], 0x90 + vpalignr xmm2, xmm7, [rbx+r11*8+256], 0x90 + vpalignr xmm2, xmm7, [rbx+r11*8-256], 0x90 + vpalignr ymm16, ymm13, ymm15, 0x90 + vpalignr ymm16, ymm13, [rbx], 0x90 + vpalignr ymm16, ymm13, [rbx+r11*8+256], 0x90 + vpalignr ymm16, ymm13, [rbx+r11*8-256], 0x90 + vpalignr zmm24, zmm24, zmm31, 0x90 + vpalignr zmm24, zmm24, [rbx], 0x90 + vpalignr zmm24, zmm24, [rbx+r11*8+256], 0x90 + vpalignr zmm24, zmm24, [rbx+r11*8-256], 0x90 + vpand xmm2, xmm7, xmm0 + vpand xmm2, xmm7, [rbx] + vpand xmm2, xmm7, [rbx+r11*8+256] + vpand xmm2, xmm7, [rbx+r11*8-256] + vpandn xmm2, xmm7, xmm0 + vpandn xmm2, xmm7, [rbx] + vpandn xmm2, xmm7, [rbx+r11*8+256] + vpandn xmm2, xmm7, [rbx+r11*8-256] + vpavgb xmm2, xmm7, xmm0 + vpavgb xmm2, xmm7, [rbx] + vpavgb xmm2, xmm7, [rbx+r11*8+256] + vpavgb xmm2, xmm7, [rbx+r11*8-256] + vpavgb ymm16, ymm13, ymm15 + vpavgb ymm16, ymm13, [rbx] + vpavgb ymm16, ymm13, [rbx+r11*8+256] + vpavgb ymm16, ymm13, [rbx+r11*8-256] + vpavgb zmm24, zmm24, zmm31 + vpavgb zmm24, zmm24, [rbx] + vpavgb zmm24, zmm24, [rbx+r11*8+256] + vpavgb zmm24, zmm24, [rbx+r11*8-256] + vpavgw xmm2, xmm7, xmm0 + vpavgw xmm2, xmm7, [rbx] + vpavgw xmm2, xmm7, [rbx+r11*8+256] + vpavgw xmm2, xmm7, [rbx+r11*8-256] + vpavgw ymm16, ymm13, ymm15 + vpavgw ymm16, ymm13, [rbx] + vpavgw ymm16, ymm13, [rbx+r11*8+256] + vpavgw ymm16, ymm13, [rbx+r11*8-256] + vpavgw zmm24, zmm24, zmm31 + vpavgw zmm24, zmm24, [rbx] + vpavgw zmm24, zmm24, [rbx+r11*8+256] + vpavgw zmm24, zmm24, [rbx+r11*8-256] + vpblendvb xmm2, xmm7, xmm0, xmm3 + vpblendvb xmm2, xmm7, [rbx], xmm3 + vpblendvb xmm2, xmm7, [rbx+r11*8+256], xmm3 + vpblendvb xmm2, xmm7, [rbx+r11*8-256], xmm3 + vpblendw xmm2, xmm7, xmm0, 0x90 + vpblendw xmm2, xmm7, [rbx], 0x90 + vpblendw xmm2, xmm7, [rbx+r11*8+256], 0x90 + vpblendw xmm2, xmm7, [rbx+r11*8-256], 0x90 + vpcmpeqb xmm2, xmm7, xmm0 + vpcmpeqb xmm2, xmm7, [rbx] + vpcmpeqb xmm2, xmm7, [rbx+r11*8+256] + vpcmpeqb xmm2, xmm7, [rbx+r11*8-256] + vpcmpeqd xmm2, xmm7, xmm0 + vpcmpeqd xmm2, xmm7, [rbx] + vpcmpeqd xmm2, xmm7, [rbx+r11*8+256] + vpcmpeqd xmm2, xmm7, [rbx+r11*8-256] + vpcmpeqq xmm2, xmm7, xmm0 + vpcmpeqq xmm2, xmm7, [rbx] + vpcmpeqq xmm2, xmm7, [rbx+r11*8+256] + vpcmpeqq xmm2, xmm7, [rbx+r11*8-256] + vpcmpeqw xmm2, xmm7, xmm0 + vpcmpeqw xmm2, xmm7, [rbx] + vpcmpeqw xmm2, xmm7, [rbx+r11*8+256] + vpcmpeqw xmm2, xmm7, [rbx+r11*8-256] + vpcmpestri xmm2, xmm0, 0x90 + vpcmpestri xmm2, [rbx], 0x90 + vpcmpestri xmm2, [rbx+r11*8+256], 0x90 + vpcmpestri xmm2, [rbx+r11*8-256], 0x90 + vpcmpestrm xmm2, xmm0, 0x90 + vpcmpestrm xmm2, [rbx], 0x90 + vpcmpestrm xmm2, [rbx+r11*8+256], 0x90 + vpcmpestrm xmm2, [rbx+r11*8-256], 0x90 + vpcmpgtb xmm2, xmm7, xmm0 + vpcmpgtb xmm2, xmm7, [rbx] + vpcmpgtb xmm2, xmm7, [rbx+r11*8+256] + vpcmpgtb xmm2, xmm7, [rbx+r11*8-256] + vpcmpgtd xmm2, xmm7, xmm0 + vpcmpgtd xmm2, xmm7, [rbx] + vpcmpgtd xmm2, xmm7, [rbx+r11*8+256] + vpcmpgtd xmm2, xmm7, [rbx+r11*8-256] + vpcmpgtq xmm2, xmm7, xmm0 + vpcmpgtq xmm2, xmm7, [rbx] + vpcmpgtq xmm2, xmm7, [rbx+r11*8+256] + vpcmpgtq xmm2, xmm7, [rbx+r11*8-256] + vpcmpgtw xmm2, xmm7, xmm0 + vpcmpgtw xmm2, xmm7, [rbx] + vpcmpgtw xmm2, xmm7, [rbx+r11*8+256] + vpcmpgtw xmm2, xmm7, [rbx+r11*8-256] + vpcmpistri xmm2, xmm0, 0x90 + vpcmpistri xmm2, [rbx], 0x90 + vpcmpistri xmm2, [rbx+r11*8+256], 0x90 + vpcmpistri xmm2, [rbx+r11*8-256], 0x90 + vpcmpistrm xmm2, xmm0, 0x90 + vpcmpistrm xmm2, [rbx], 0x90 + vpcmpistrm xmm2, [rbx+r11*8+256], 0x90 + vpcmpistrm xmm2, [rbx+r11*8-256], 0x90 + vpermilpd xmm2, xmm7, xmm0 + vpermilpd xmm2, xmm7, [rbx] + vpermilpd xmm2, xmm7, [rbx+r11*8+256] + vpermilpd xmm2, xmm7, [rbx+r11*8-256] + vpermilpd ymm16, ymm13, ymm15 + vpermilpd ymm16, ymm13, [rbx] + vpermilpd ymm16, ymm13, [rbx+r11*8+256] + vpermilpd ymm16, ymm13, [rbx+r11*8-256] + vpermilpd zmm24, zmm24, zmm31 + vpermilpd zmm24, zmm24, [rbx] + vpermilpd zmm24, zmm24, [rbx+r11*8+256] + vpermilpd zmm24, zmm24, [rbx+r11*8-256] + vpermilpd xmm2, xmm0, 0x90 + vpermilpd xmm2, [rbx], 0x90 + vpermilpd xmm2, [rbx+r11*8+256], 0x90 + vpermilpd xmm2, [rbx+r11*8-256], 0x90 + vpermilpd ymm16, ymm15, 0x90 + vpermilpd ymm16, [rbx], 0x90 + vpermilpd ymm16, [rbx+r11*8+256], 0x90 + vpermilpd ymm16, [rbx+r11*8-256], 0x90 + vpermilpd zmm24, zmm31, 0x90 + vpermilpd zmm24, [rbx], 0x90 + vpermilpd zmm24, [rbx+r11*8+256], 0x90 + vpermilpd zmm24, [rbx+r11*8-256], 0x90 + vpermilps xmm2, xmm7, xmm0 + vpermilps xmm2, xmm7, [rbx] + vpermilps xmm2, xmm7, [rbx+r11*8+256] + vpermilps xmm2, xmm7, [rbx+r11*8-256] + vpermilps ymm16, ymm13, ymm15 + vpermilps ymm16, ymm13, [rbx] + vpermilps ymm16, ymm13, [rbx+r11*8+256] + vpermilps ymm16, ymm13, [rbx+r11*8-256] + vpermilps zmm24, zmm24, zmm31 + vpermilps zmm24, zmm24, [rbx] + vpermilps zmm24, zmm24, [rbx+r11*8+256] + vpermilps zmm24, zmm24, [rbx+r11*8-256] + vpermilps xmm2, xmm0, 0x90 + vpermilps xmm2, [rbx], 0x90 + vpermilps xmm2, [rbx+r11*8+256], 0x90 + vpermilps xmm2, [rbx+r11*8-256], 0x90 + vpermilps ymm16, ymm15, 0x90 + vpermilps ymm16, [rbx], 0x90 + vpermilps ymm16, [rbx+r11*8+256], 0x90 + vpermilps ymm16, [rbx+r11*8-256], 0x90 + vpermilps zmm24, zmm31, 0x90 + vpermilps zmm24, [rbx], 0x90 + vpermilps zmm24, [rbx+r11*8+256], 0x90 + vpermilps zmm24, [rbx+r11*8-256], 0x90 + vpextrb [rbx], xmm2, 0x90 + vpextrb [rbx+rsi*8+256], xmm2, 0x90 + vpextrb [rbx+rsi*8-256], xmm2, 0x90 + vpextrb cl, xmm2, 0x90 + vpextrb cx, xmm2, 0x90 + vpextrb ecx, xmm2, 0x90 + vpextrb rcx, xmm2, 0x90 + vpextrd ecx, xmm2, 0x90 + vpextrd rcx, xmm2, 0x90 + vpextrd [rbx], xmm2, 0x90 + vpextrd [rbx+rsi*8+256], xmm2, 0x90 + vpextrq rcx, xmm2, 0x90 + vpextrq [rbx], xmm2, 0x90 + vpextrq [rbx+rsi*8+256], xmm2, 0x90 + vpextrw cx, xmm0, 0x90 + vpextrw ecx, xmm0, 0x90 + vpextrw rcx, xmm0, 0x90 + vpextrw [rbx], xmm2, 0x90 + vpextrw [rbx+rsi*8+256], xmm2, 0x90 + vpextrw [rbx+rsi*8-256], xmm2, 0x90 + vpextrw cx, xmm2, 0x90 + vpextrw ecx, xmm2, 0x90 + vpextrw rcx, xmm2, 0x90 + vphaddd xmm2, xmm7, xmm0 + vphaddd xmm2, xmm7, [rbx] + vphaddd xmm2, xmm7, [rbx+r11*8+256] + vphaddd xmm2, xmm7, [rbx+r11*8-256] + vphaddsw xmm2, xmm7, xmm0 + vphaddsw xmm2, xmm7, [rbx] + vphaddsw xmm2, xmm7, [rbx+r11*8+256] + vphaddsw xmm2, xmm7, [rbx+r11*8-256] + vphaddw xmm2, xmm7, xmm0 + vphaddw xmm2, xmm7, [rbx] + vphaddw xmm2, xmm7, [rbx+r11*8+256] + vphaddw xmm2, xmm7, [rbx+r11*8-256] + vphminposuw xmm2, xmm0 + vphminposuw xmm2, [rbx] + vphminposuw xmm2, [rbx+r11*8+256] + vphminposuw xmm2, [rbx+r11*8-256] + vphsubd xmm2, xmm7, xmm0 + vphsubd xmm2, xmm7, [rbx] + vphsubd xmm2, xmm7, [rbx+r11*8+256] + vphsubd xmm2, xmm7, [rbx+r11*8-256] + vphsubsw xmm2, xmm7, xmm0 + vphsubsw xmm2, xmm7, [rbx] + vphsubsw xmm2, xmm7, [rbx+r11*8+256] + vphsubsw xmm2, xmm7, [rbx+r11*8-256] + vphsubw xmm2, xmm7, xmm0 + vphsubw xmm2, xmm7, [rbx] + vphsubw xmm2, xmm7, [rbx+r11*8+256] + vphsubw xmm2, xmm7, [rbx+r11*8-256] + vpinsrb xmm2, xmm7, [rbx], 0x90 + vpinsrb xmm2, xmm7, [rbx+rsi*8+256], 0x90 + vpinsrb xmm2, xmm7, [rbx+rsi*8-256], 0x90 + vpinsrb xmm2, xmm7, cl, 0x90 + vpinsrb xmm2, xmm7, ecx, 0x90 + vpinsrd xmm2, xmm7, ecx, 0x90 + vpinsrd xmm2, xmm7, [rbx], 0x90 + vpinsrd xmm2, xmm7, [rbx+rsi*8+256], 0x90 + vpinsrq xmm2, xmm7, rcx, 0x90 + vpinsrq xmm2, xmm7, [rbx], 0x90 + vpinsrq xmm2, xmm7, [rbx+rsi*8+256], 0x90 + vpinsrw xmm2, xmm7, [rbx], 0x90 + vpinsrw xmm2, xmm7, [rbx+rsi*8+256], 0x90 + vpinsrw xmm2, xmm7, [rbx+rsi*8-256], 0x90 + vpinsrw xmm2, xmm7, cx, 0x90 + vpinsrw xmm2, xmm7, ecx, 0x90 + vpmaddubsw xmm2, xmm7, xmm0 + vpmaddubsw xmm2, xmm7, [rbx] + vpmaddubsw xmm2, xmm7, [rbx+r11*8+256] + vpmaddubsw xmm2, xmm7, [rbx+r11*8-256] + vpmaddubsw ymm16, ymm13, ymm15 + vpmaddubsw ymm16, ymm13, [rbx] + vpmaddubsw ymm16, ymm13, [rbx+r11*8+256] + vpmaddubsw ymm16, ymm13, [rbx+r11*8-256] + vpmaddubsw zmm24, zmm24, zmm31 + vpmaddubsw zmm24, zmm24, [rbx] + vpmaddubsw zmm24, zmm24, [rbx+r11*8+256] + vpmaddubsw zmm24, zmm24, [rbx+r11*8-256] + vpmaddwd xmm2, xmm7, xmm0 + vpmaddwd xmm2, xmm7, [rbx] + vpmaddwd xmm2, xmm7, [rbx+r11*8+256] + vpmaddwd xmm2, xmm7, [rbx+r11*8-256] + vpmaddwd ymm16, ymm13, ymm15 + vpmaddwd ymm16, ymm13, [rbx] + vpmaddwd ymm16, ymm13, [rbx+r11*8+256] + vpmaddwd ymm16, ymm13, [rbx+r11*8-256] + vpmaddwd zmm24, zmm24, zmm31 + vpmaddwd zmm24, zmm24, [rbx] + vpmaddwd zmm24, zmm24, [rbx+r11*8+256] + vpmaddwd zmm24, zmm24, [rbx+r11*8-256] + vpmaxsb xmm2, xmm7, xmm0 + vpmaxsb xmm2, xmm7, [rbx] + vpmaxsb xmm2, xmm7, [rbx+r11*8+256] + vpmaxsb xmm2, xmm7, [rbx+r11*8-256] + vpmaxsb ymm16, ymm13, ymm15 + vpmaxsb ymm16, ymm13, [rbx] + vpmaxsb ymm16, ymm13, [rbx+r11*8+256] + vpmaxsb ymm16, ymm13, [rbx+r11*8-256] + vpmaxsb zmm24, zmm24, zmm31 + vpmaxsb zmm24, zmm24, [rbx] + vpmaxsb zmm24, zmm24, [rbx+r11*8+256] + vpmaxsb zmm24, zmm24, [rbx+r11*8-256] + vpmaxsd xmm2, xmm7, xmm0 + vpmaxsd xmm2, xmm7, [rbx] + vpmaxsd xmm2, xmm7, [rbx+r11*8+256] + vpmaxsd xmm2, xmm7, [rbx+r11*8-256] + vpmaxsd ymm16, ymm13, ymm15 + vpmaxsd ymm16, ymm13, [rbx] + vpmaxsd ymm16, ymm13, [rbx+r11*8+256] + vpmaxsd ymm16, ymm13, [rbx+r11*8-256] + vpmaxsd zmm24, zmm24, zmm31 + vpmaxsd zmm24, zmm24, [rbx] + vpmaxsd zmm24, zmm24, [rbx+r11*8+256] + vpmaxsd zmm24, zmm24, [rbx+r11*8-256] + vpmaxsw xmm2, xmm7, xmm0 + vpmaxsw xmm2, xmm7, [rbx] + vpmaxsw xmm2, xmm7, [rbx+r11*8+256] + vpmaxsw xmm2, xmm7, [rbx+r11*8-256] + vpmaxsw ymm16, ymm13, ymm15 + vpmaxsw ymm16, ymm13, [rbx] + vpmaxsw ymm16, ymm13, [rbx+r11*8+256] + vpmaxsw ymm16, ymm13, [rbx+r11*8-256] + vpmaxsw zmm24, zmm24, zmm31 + vpmaxsw zmm24, zmm24, [rbx] + vpmaxsw zmm24, zmm24, [rbx+r11*8+256] + vpmaxsw zmm24, zmm24, [rbx+r11*8-256] + vpmaxub xmm2, xmm7, xmm0 + vpmaxub xmm2, xmm7, [rbx] + vpmaxub xmm2, xmm7, [rbx+r11*8+256] + vpmaxub xmm2, xmm7, [rbx+r11*8-256] + vpmaxub ymm16, ymm13, ymm15 + vpmaxub ymm16, ymm13, [rbx] + vpmaxub ymm16, ymm13, [rbx+r11*8+256] + vpmaxub ymm16, ymm13, [rbx+r11*8-256] + vpmaxub zmm24, zmm24, zmm31 + vpmaxub zmm24, zmm24, [rbx] + vpmaxub zmm24, zmm24, [rbx+r11*8+256] + vpmaxub zmm24, zmm24, [rbx+r11*8-256] + vpmaxud xmm2, xmm7, xmm0 + vpmaxud xmm2, xmm7, [rbx] + vpmaxud xmm2, xmm7, [rbx+r11*8+256] + vpmaxud xmm2, xmm7, [rbx+r11*8-256] + vpmaxud ymm16, ymm13, ymm15 + vpmaxud ymm16, ymm13, [rbx] + vpmaxud ymm16, ymm13, [rbx+r11*8+256] + vpmaxud ymm16, ymm13, [rbx+r11*8-256] + vpmaxud zmm24, zmm24, zmm31 + vpmaxud zmm24, zmm24, [rbx] + vpmaxud zmm24, zmm24, [rbx+r11*8+256] + vpmaxud zmm24, zmm24, [rbx+r11*8-256] + vpmaxuw xmm2, xmm7, xmm0 + vpmaxuw xmm2, xmm7, [rbx] + vpmaxuw xmm2, xmm7, [rbx+r11*8+256] + vpmaxuw xmm2, xmm7, [rbx+r11*8-256] + vpmaxuw ymm16, ymm13, ymm15 + vpmaxuw ymm16, ymm13, [rbx] + vpmaxuw ymm16, ymm13, [rbx+r11*8+256] + vpmaxuw ymm16, ymm13, [rbx+r11*8-256] + vpmaxuw zmm24, zmm24, zmm31 + vpmaxuw zmm24, zmm24, [rbx] + vpmaxuw zmm24, zmm24, [rbx+r11*8+256] + vpmaxuw zmm24, zmm24, [rbx+r11*8-256] + vpminsb xmm2, xmm7, xmm0 + vpminsb xmm2, xmm7, [rbx] + vpminsb xmm2, xmm7, [rbx+r11*8+256] + vpminsb xmm2, xmm7, [rbx+r11*8-256] + vpminsb ymm16, ymm13, ymm15 + vpminsb ymm16, ymm13, [rbx] + vpminsb ymm16, ymm13, [rbx+r11*8+256] + vpminsb ymm16, ymm13, [rbx+r11*8-256] + vpminsb zmm24, zmm24, zmm31 + vpminsb zmm24, zmm24, [rbx] + vpminsb zmm24, zmm24, [rbx+r11*8+256] + vpminsb zmm24, zmm24, [rbx+r11*8-256] + vpminsd xmm2, xmm7, xmm0 + vpminsd xmm2, xmm7, [rbx] + vpminsd xmm2, xmm7, [rbx+r11*8+256] + vpminsd xmm2, xmm7, [rbx+r11*8-256] + vpminsd ymm16, ymm13, ymm15 + vpminsd ymm16, ymm13, [rbx] + vpminsd ymm16, ymm13, [rbx+r11*8+256] + vpminsd ymm16, ymm13, [rbx+r11*8-256] + vpminsd zmm24, zmm24, zmm31 + vpminsd zmm24, zmm24, [rbx] + vpminsd zmm24, zmm24, [rbx+r11*8+256] + vpminsd zmm24, zmm24, [rbx+r11*8-256] + vpminsw xmm2, xmm7, xmm0 + vpminsw xmm2, xmm7, [rbx] + vpminsw xmm2, xmm7, [rbx+r11*8+256] + vpminsw xmm2, xmm7, [rbx+r11*8-256] + vpminsw ymm16, ymm13, ymm15 + vpminsw ymm16, ymm13, [rbx] + vpminsw ymm16, ymm13, [rbx+r11*8+256] + vpminsw ymm16, ymm13, [rbx+r11*8-256] + vpminsw zmm24, zmm24, zmm31 + vpminsw zmm24, zmm24, [rbx] + vpminsw zmm24, zmm24, [rbx+r11*8+256] + vpminsw zmm24, zmm24, [rbx+r11*8-256] + vpminub xmm2, xmm7, xmm0 + vpminub xmm2, xmm7, [rbx] + vpminub xmm2, xmm7, [rbx+r11*8+256] + vpminub xmm2, xmm7, [rbx+r11*8-256] + vpminub ymm16, ymm13, ymm15 + vpminub ymm16, ymm13, [rbx] + vpminub ymm16, ymm13, [rbx+r11*8+256] + vpminub ymm16, ymm13, [rbx+r11*8-256] + vpminub zmm24, zmm24, zmm31 + vpminub zmm24, zmm24, [rbx] + vpminub zmm24, zmm24, [rbx+r11*8+256] + vpminub zmm24, zmm24, [rbx+r11*8-256] + vpminud xmm2, xmm7, xmm0 + vpminud xmm2, xmm7, [rbx] + vpminud xmm2, xmm7, [rbx+r11*8+256] + vpminud xmm2, xmm7, [rbx+r11*8-256] + vpminud ymm16, ymm13, ymm15 + vpminud ymm16, ymm13, [rbx] + vpminud ymm16, ymm13, [rbx+r11*8+256] + vpminud ymm16, ymm13, [rbx+r11*8-256] + vpminud zmm24, zmm24, zmm31 + vpminud zmm24, zmm24, [rbx] + vpminud zmm24, zmm24, [rbx+r11*8+256] + vpminud zmm24, zmm24, [rbx+r11*8-256] + vpminuw xmm2, xmm7, xmm0 + vpminuw xmm2, xmm7, [rbx] + vpminuw xmm2, xmm7, [rbx+r11*8+256] + vpminuw xmm2, xmm7, [rbx+r11*8-256] + vpminuw ymm16, ymm13, ymm15 + vpminuw ymm16, ymm13, [rbx] + vpminuw ymm16, ymm13, [rbx+r11*8+256] + vpminuw ymm16, ymm13, [rbx+r11*8-256] + vpminuw zmm24, zmm24, zmm31 + vpminuw zmm24, zmm24, [rbx] + vpminuw zmm24, zmm24, [rbx+r11*8+256] + vpminuw zmm24, zmm24, [rbx+r11*8-256] + vpmovmskb ecx, xmm0 + vpmovmskb ecx, ymm15 + vpmovmskb rcx, xmm0 + vpmovmskb rcx, ymm15 + vpmovsxbd xmm2, xmm0 + vpmovsxbd xmm2, [rbx] + vpmovsxbd xmm2, [rbx+r11*8+256] + vpmovsxbd xmm2, [rbx+r11*8-256] + vpmovsxbd ymm16, xmm0 + vpmovsxbd ymm16, [rbx] + vpmovsxbd ymm16, [rbx+r11*8+256] + vpmovsxbd ymm16, [rbx+r11*8-256] + vpmovsxbd zmm24, xmm0 + vpmovsxbd zmm24, [rbx] + vpmovsxbd zmm24, [rbx+r11*8+256] + vpmovsxbd zmm24, [rbx+r11*8-256] + vpmovsxbq xmm2, xmm0 + vpmovsxbq xmm2, [rbx] + vpmovsxbq xmm2, [rbx+r11*8+256] + vpmovsxbq xmm2, [rbx+r11*8-256] + vpmovsxbq ymm16, xmm0 + vpmovsxbq ymm16, [rbx] + vpmovsxbq ymm16, [rbx+r11*8+256] + vpmovsxbq ymm16, [rbx+r11*8-256] + vpmovsxbq zmm24, xmm0 + vpmovsxbq zmm24, [rbx] + vpmovsxbq zmm24, [rbx+r11*8+256] + vpmovsxbq zmm24, [rbx+r11*8-256] + vpmovsxbw xmm2, xmm0 + vpmovsxbw xmm2, [rbx] + vpmovsxbw xmm2, [rbx+r11*8+256] + vpmovsxbw xmm2, [rbx+r11*8-256] + vpmovsxbw ymm16, xmm0 + vpmovsxbw ymm16, [rbx] + vpmovsxbw ymm16, [rbx+r11*8+256] + vpmovsxbw ymm16, [rbx+r11*8-256] + vpmovsxbw zmm24, ymm15 + vpmovsxbw zmm24, [rbx] + vpmovsxbw zmm24, [rbx+r11*8+256] + vpmovsxbw zmm24, [rbx+r11*8-256] + vpmovsxdq xmm2, xmm0 + vpmovsxdq xmm2, [rbx] + vpmovsxdq xmm2, [rbx+r11*8+256] + vpmovsxdq xmm2, [rbx+r11*8-256] + vpmovsxdq ymm16, xmm0 + vpmovsxdq ymm16, [rbx] + vpmovsxdq ymm16, [rbx+r11*8+256] + vpmovsxdq ymm16, [rbx+r11*8-256] + vpmovsxdq zmm24, ymm15 + vpmovsxdq zmm24, [rbx] + vpmovsxdq zmm24, [rbx+r11*8+256] + vpmovsxdq zmm24, [rbx+r11*8-256] + vpmovsxwd xmm2, xmm0 + vpmovsxwd xmm2, [rbx] + vpmovsxwd xmm2, [rbx+r11*8+256] + vpmovsxwd xmm2, [rbx+r11*8-256] + vpmovsxwd ymm16, xmm0 + vpmovsxwd ymm16, [rbx] + vpmovsxwd ymm16, [rbx+r11*8+256] + vpmovsxwd ymm16, [rbx+r11*8-256] + vpmovsxwd zmm24, ymm15 + vpmovsxwd zmm24, [rbx] + vpmovsxwd zmm24, [rbx+r11*8+256] + vpmovsxwd zmm24, [rbx+r11*8-256] + vpmovsxwq xmm2, xmm0 + vpmovsxwq xmm2, [rbx] + vpmovsxwq xmm2, [rbx+r11*8+256] + vpmovsxwq xmm2, [rbx+r11*8-256] + vpmovsxwq ymm16, xmm0 + vpmovsxwq ymm16, [rbx] + vpmovsxwq ymm16, [rbx+r11*8+256] + vpmovsxwq ymm16, [rbx+r11*8-256] + vpmovsxwq zmm24, xmm0 + vpmovsxwq zmm24, [rbx] + vpmovsxwq zmm24, [rbx+r11*8+256] + vpmovsxwq zmm24, [rbx+r11*8-256] + vpmovzxbd xmm2, xmm0 + vpmovzxbd xmm2, [rbx] + vpmovzxbd xmm2, [rbx+r11*8+256] + vpmovzxbd xmm2, [rbx+r11*8-256] + vpmovzxbd ymm16, xmm0 + vpmovzxbd ymm16, [rbx] + vpmovzxbd ymm16, [rbx+r11*8+256] + vpmovzxbd ymm16, [rbx+r11*8-256] + vpmovzxbd zmm24, xmm0 + vpmovzxbd zmm24, [rbx] + vpmovzxbd zmm24, [rbx+r11*8+256] + vpmovzxbd zmm24, [rbx+r11*8-256] + vpmovzxbq xmm2, xmm0 + vpmovzxbq xmm2, [rbx] + vpmovzxbq xmm2, [rbx+r11*8+256] + vpmovzxbq xmm2, [rbx+r11*8-256] + vpmovzxbq ymm16, xmm0 + vpmovzxbq ymm16, [rbx] + vpmovzxbq ymm16, [rbx+r11*8+256] + vpmovzxbq ymm16, [rbx+r11*8-256] + vpmovzxbq zmm24, xmm0 + vpmovzxbq zmm24, [rbx] + vpmovzxbq zmm24, [rbx+r11*8+256] + vpmovzxbq zmm24, [rbx+r11*8-256] + vpmovzxbw xmm2, xmm0 + vpmovzxbw xmm2, [rbx] + vpmovzxbw xmm2, [rbx+r11*8+256] + vpmovzxbw xmm2, [rbx+r11*8-256] + vpmovzxbw ymm16, xmm0 + vpmovzxbw ymm16, [rbx] + vpmovzxbw ymm16, [rbx+r11*8+256] + vpmovzxbw ymm16, [rbx+r11*8-256] + vpmovzxbw zmm24, ymm15 + vpmovzxbw zmm24, [rbx] + vpmovzxbw zmm24, [rbx+r11*8+256] + vpmovzxbw zmm24, [rbx+r11*8-256] + vpmovzxdq xmm2, xmm0 + vpmovzxdq xmm2, [rbx] + vpmovzxdq xmm2, [rbx+r11*8+256] + vpmovzxdq xmm2, [rbx+r11*8-256] + vpmovzxdq ymm16, xmm0 + vpmovzxdq ymm16, [rbx] + vpmovzxdq ymm16, [rbx+r11*8+256] + vpmovzxdq ymm16, [rbx+r11*8-256] + vpmovzxdq zmm24, ymm15 + vpmovzxdq zmm24, [rbx] + vpmovzxdq zmm24, [rbx+r11*8+256] + vpmovzxdq zmm24, [rbx+r11*8-256] + vpmovzxwd xmm2, xmm0 + vpmovzxwd xmm2, [rbx] + vpmovzxwd xmm2, [rbx+r11*8+256] + vpmovzxwd xmm2, [rbx+r11*8-256] + vpmovzxwd ymm16, xmm0 + vpmovzxwd ymm16, [rbx] + vpmovzxwd ymm16, [rbx+r11*8+256] + vpmovzxwd ymm16, [rbx+r11*8-256] + vpmovzxwd zmm24, ymm15 + vpmovzxwd zmm24, [rbx] + vpmovzxwd zmm24, [rbx+r11*8+256] + vpmovzxwd zmm24, [rbx+r11*8-256] + vpmovzxwq xmm2, xmm0 + vpmovzxwq xmm2, [rbx] + vpmovzxwq xmm2, [rbx+r11*8+256] + vpmovzxwq xmm2, [rbx+r11*8-256] + vpmovzxwq ymm16, xmm0 + vpmovzxwq ymm16, [rbx] + vpmovzxwq ymm16, [rbx+r11*8+256] + vpmovzxwq ymm16, [rbx+r11*8-256] + vpmovzxwq zmm24, xmm0 + vpmovzxwq zmm24, [rbx] + vpmovzxwq zmm24, [rbx+r11*8+256] + vpmovzxwq zmm24, [rbx+r11*8-256] + vpmuldq xmm2, xmm7, xmm0 + vpmuldq xmm2, xmm7, [rbx] + vpmuldq xmm2, xmm7, [rbx+r11*8+256] + vpmuldq xmm2, xmm7, [rbx+r11*8-256] + vpmuldq ymm16, ymm13, ymm15 + vpmuldq ymm16, ymm13, [rbx] + vpmuldq ymm16, ymm13, [rbx+r11*8+256] + vpmuldq ymm16, ymm13, [rbx+r11*8-256] + vpmuldq zmm24, zmm24, zmm31 + vpmuldq zmm24, zmm24, [rbx] + vpmuldq zmm24, zmm24, [rbx+r11*8+256] + vpmuldq zmm24, zmm24, [rbx+r11*8-256] + vpmulhrsw xmm2, xmm7, xmm0 + vpmulhrsw xmm2, xmm7, [rbx] + vpmulhrsw xmm2, xmm7, [rbx+r11*8+256] + vpmulhrsw xmm2, xmm7, [rbx+r11*8-256] + vpmulhrsw ymm16, ymm13, ymm15 + vpmulhrsw ymm16, ymm13, [rbx] + vpmulhrsw ymm16, ymm13, [rbx+r11*8+256] + vpmulhrsw ymm16, ymm13, [rbx+r11*8-256] + vpmulhrsw zmm24, zmm24, zmm31 + vpmulhrsw zmm24, zmm24, [rbx] + vpmulhrsw zmm24, zmm24, [rbx+r11*8+256] + vpmulhrsw zmm24, zmm24, [rbx+r11*8-256] + vpmulhuw xmm2, xmm7, xmm0 + vpmulhuw xmm2, xmm7, [rbx] + vpmulhuw xmm2, xmm7, [rbx+r11*8+256] + vpmulhuw xmm2, xmm7, [rbx+r11*8-256] + vpmulhuw ymm16, ymm13, ymm15 + vpmulhuw ymm16, ymm13, [rbx] + vpmulhuw ymm16, ymm13, [rbx+r11*8+256] + vpmulhuw ymm16, ymm13, [rbx+r11*8-256] + vpmulhuw zmm24, zmm24, zmm31 + vpmulhuw zmm24, zmm24, [rbx] + vpmulhuw zmm24, zmm24, [rbx+r11*8+256] + vpmulhuw zmm24, zmm24, [rbx+r11*8-256] + vpmulhw xmm2, xmm7, xmm0 + vpmulhw xmm2, xmm7, [rbx] + vpmulhw xmm2, xmm7, [rbx+r11*8+256] + vpmulhw xmm2, xmm7, [rbx+r11*8-256] + vpmulhw ymm16, ymm13, ymm15 + vpmulhw ymm16, ymm13, [rbx] + vpmulhw ymm16, ymm13, [rbx+r11*8+256] + vpmulhw ymm16, ymm13, [rbx+r11*8-256] + vpmulhw zmm24, zmm24, zmm31 + vpmulhw zmm24, zmm24, [rbx] + vpmulhw zmm24, zmm24, [rbx+r11*8+256] + vpmulhw zmm24, zmm24, [rbx+r11*8-256] + vpmulld xmm2, xmm7, xmm0 + vpmulld xmm2, xmm7, [rbx] + vpmulld xmm2, xmm7, [rbx+r11*8+256] + vpmulld xmm2, xmm7, [rbx+r11*8-256] + vpmulld ymm16, ymm13, ymm15 + vpmulld ymm16, ymm13, [rbx] + vpmulld ymm16, ymm13, [rbx+r11*8+256] + vpmulld ymm16, ymm13, [rbx+r11*8-256] + vpmulld zmm24, zmm24, zmm31 + vpmulld zmm24, zmm24, [rbx] + vpmulld zmm24, zmm24, [rbx+r11*8+256] + vpmulld zmm24, zmm24, [rbx+r11*8-256] + vpmullw xmm2, xmm7, xmm0 + vpmullw xmm2, xmm7, [rbx] + vpmullw xmm2, xmm7, [rbx+r11*8+256] + vpmullw xmm2, xmm7, [rbx+r11*8-256] + vpmullw ymm16, ymm13, ymm15 + vpmullw ymm16, ymm13, [rbx] + vpmullw ymm16, ymm13, [rbx+r11*8+256] + vpmullw ymm16, ymm13, [rbx+r11*8-256] + vpmullw zmm24, zmm24, zmm31 + vpmullw zmm24, zmm24, [rbx] + vpmullw zmm24, zmm24, [rbx+r11*8+256] + vpmullw zmm24, zmm24, [rbx+r11*8-256] + vpmuludq xmm2, xmm7, xmm0 + vpmuludq xmm2, xmm7, [rbx] + vpmuludq xmm2, xmm7, [rbx+r11*8+256] + vpmuludq xmm2, xmm7, [rbx+r11*8-256] + vpmuludq ymm16, ymm13, ymm15 + vpmuludq ymm16, ymm13, [rbx] + vpmuludq ymm16, ymm13, [rbx+r11*8+256] + vpmuludq ymm16, ymm13, [rbx+r11*8-256] + vpmuludq zmm24, zmm24, zmm31 + vpmuludq zmm24, zmm24, [rbx] + vpmuludq zmm24, zmm24, [rbx+r11*8+256] + vpmuludq zmm24, zmm24, [rbx+r11*8-256] + vpor xmm2, xmm7, xmm0 + vpor xmm2, xmm7, [rbx] + vpor xmm2, xmm7, [rbx+r11*8+256] + vpor xmm2, xmm7, [rbx+r11*8-256] + vpsadbw xmm2, xmm7, xmm0 + vpsadbw xmm2, xmm7, [rbx] + vpsadbw xmm2, xmm7, [rbx+r11*8+256] + vpsadbw xmm2, xmm7, [rbx+r11*8-256] + vpsadbw ymm16, ymm13, ymm15 + vpsadbw ymm16, ymm13, [rbx] + vpsadbw ymm16, ymm13, [rbx+r11*8+256] + vpsadbw ymm16, ymm13, [rbx+r11*8-256] + vpsadbw zmm24, zmm24, zmm31 + vpsadbw zmm24, zmm24, [rbx] + vpsadbw zmm24, zmm24, [rbx+r11*8+256] + vpsadbw zmm24, zmm24, [rbx+r11*8-256] + vpshufb xmm2, xmm7, xmm0 + vpshufb xmm2, xmm7, [rbx] + vpshufb xmm2, xmm7, [rbx+r11*8+256] + vpshufb xmm2, xmm7, [rbx+r11*8-256] + vpshufb ymm16, ymm13, ymm15 + vpshufb ymm16, ymm13, [rbx] + vpshufb ymm16, ymm13, [rbx+r11*8+256] + vpshufb ymm16, ymm13, [rbx+r11*8-256] + vpshufb zmm24, zmm24, zmm31 + vpshufb zmm24, zmm24, [rbx] + vpshufb zmm24, zmm24, [rbx+r11*8+256] + vpshufb zmm24, zmm24, [rbx+r11*8-256] + vpshufd xmm2, xmm0, 0x90 + vpshufd xmm2, [rbx], 0x90 + vpshufd xmm2, [rbx+r11*8+256], 0x90 + vpshufd xmm2, [rbx+r11*8-256], 0x90 + vpshufd ymm16, ymm15, 0x90 + vpshufd ymm16, [rbx], 0x90 + vpshufd ymm16, [rbx+r11*8+256], 0x90 + vpshufd ymm16, [rbx+r11*8-256], 0x90 + vpshufd zmm24, zmm31, 0x90 + vpshufd zmm24, [rbx], 0x90 + vpshufd zmm24, [rbx+r11*8+256], 0x90 + vpshufd zmm24, [rbx+r11*8-256], 0x90 + vpshufhw xmm2, xmm0, 0x90 + vpshufhw xmm2, [rbx], 0x90 + vpshufhw xmm2, [rbx+r11*8+256], 0x90 + vpshufhw xmm2, [rbx+r11*8-256], 0x90 + vpshufhw ymm16, ymm15, 0x90 + vpshufhw ymm16, [rbx], 0x90 + vpshufhw ymm16, [rbx+r11*8+256], 0x90 + vpshufhw ymm16, [rbx+r11*8-256], 0x90 + vpshufhw zmm24, zmm31, 0x90 + vpshufhw zmm24, [rbx], 0x90 + vpshufhw zmm24, [rbx+r11*8+256], 0x90 + vpshufhw zmm24, [rbx+r11*8-256], 0x90 + vpshuflw xmm2, xmm0, 0x90 + vpshuflw xmm2, [rbx], 0x90 + vpshuflw xmm2, [rbx+r11*8+256], 0x90 + vpshuflw xmm2, [rbx+r11*8-256], 0x90 + vpshuflw ymm16, ymm15, 0x90 + vpshuflw ymm16, [rbx], 0x90 + vpshuflw ymm16, [rbx+r11*8+256], 0x90 + vpshuflw ymm16, [rbx+r11*8-256], 0x90 + vpshuflw zmm24, zmm31, 0x90 + vpshuflw zmm24, [rbx], 0x90 + vpshuflw zmm24, [rbx+r11*8+256], 0x90 + vpshuflw zmm24, [rbx+r11*8-256], 0x90 + vpsignb xmm2, xmm7, xmm0 + vpsignb xmm2, xmm7, [rbx] + vpsignb xmm2, xmm7, [rbx+r11*8+256] + vpsignb xmm2, xmm7, [rbx+r11*8-256] + vpsignd xmm2, xmm7, xmm0 + vpsignd xmm2, xmm7, [rbx] + vpsignd xmm2, xmm7, [rbx+r11*8+256] + vpsignd xmm2, xmm7, [rbx+r11*8-256] + vpsignw xmm2, xmm7, xmm0 + vpsignw xmm2, xmm7, [rbx] + vpsignw xmm2, xmm7, [rbx+r11*8+256] + vpsignw xmm2, xmm7, [rbx+r11*8-256] + vpslld xmm7, xmm0, 0x90 + vpslld ymm13, ymm15, 0x90 + vpslld zmm24, zmm31, 0x90 + vpslld xmm2, xmm7, xmm0 + vpslld xmm2, xmm7, [rbx] + vpslld xmm2, xmm7, [rbx+r11*8+256] + vpslld xmm2, xmm7, [rbx+r11*8-256] + vpslld ymm16, ymm13, xmm0 + vpslld ymm16, ymm13, [rbx] + vpslld ymm16, ymm13, [rbx+r11*8+256] + vpslld ymm16, ymm13, [rbx+r11*8-256] + vpslld zmm24, zmm24, xmm0 + vpslld zmm24, zmm24, [rbx] + vpslld zmm24, zmm24, [rbx+r11*8+256] + vpslld zmm24, zmm24, [rbx+r11*8-256] + vpslldq xmm7, xmm0, 0x90 + vpslldq ymm13, ymm15, 0x90 + vpslldq zmm24, zmm31, 0x90 + vpsllq xmm7, xmm0, 0x90 + vpsllq ymm13, ymm15, 0x90 + vpsllq zmm24, zmm31, 0x90 + vpsllq xmm2, xmm7, xmm0 + vpsllq xmm2, xmm7, [rbx] + vpsllq xmm2, xmm7, [rbx+r11*8+256] + vpsllq xmm2, xmm7, [rbx+r11*8-256] + vpsllq ymm16, ymm13, xmm0 + vpsllq ymm16, ymm13, [rbx] + vpsllq ymm16, ymm13, [rbx+r11*8+256] + vpsllq ymm16, ymm13, [rbx+r11*8-256] + vpsllq zmm24, zmm24, xmm0 + vpsllq zmm24, zmm24, [rbx] + vpsllq zmm24, zmm24, [rbx+r11*8+256] + vpsllq zmm24, zmm24, [rbx+r11*8-256] + vpsllw xmm7, xmm0, 0x90 + vpsllw ymm13, ymm15, 0x90 + vpsllw zmm24, zmm31, 0x90 + vpsllw xmm2, xmm7, xmm0 + vpsllw xmm2, xmm7, [rbx] + vpsllw xmm2, xmm7, [rbx+r11*8+256] + vpsllw xmm2, xmm7, [rbx+r11*8-256] + vpsllw ymm16, ymm13, xmm0 + vpsllw ymm16, ymm13, [rbx] + vpsllw ymm16, ymm13, [rbx+r11*8+256] + vpsllw ymm16, ymm13, [rbx+r11*8-256] + vpsllw zmm24, zmm24, xmm0 + vpsllw zmm24, zmm24, [rbx] + vpsllw zmm24, zmm24, [rbx+r11*8+256] + vpsllw zmm24, zmm24, [rbx+r11*8-256] + vpsrad xmm7, xmm0, 0x90 + vpsrad ymm13, ymm15, 0x90 + vpsrad zmm24, zmm31, 0x90 + vpsrad xmm2, xmm7, xmm0 + vpsrad xmm2, xmm7, [rbx] + vpsrad xmm2, xmm7, [rbx+r11*8+256] + vpsrad xmm2, xmm7, [rbx+r11*8-256] + vpsrad ymm16, ymm13, xmm0 + vpsrad ymm16, ymm13, [rbx] + vpsrad ymm16, ymm13, [rbx+r11*8+256] + vpsrad ymm16, ymm13, [rbx+r11*8-256] + vpsrad zmm24, zmm24, xmm0 + vpsrad zmm24, zmm24, [rbx] + vpsrad zmm24, zmm24, [rbx+r11*8+256] + vpsrad zmm24, zmm24, [rbx+r11*8-256] + vpsraw xmm7, xmm0, 0x90 + vpsraw ymm13, ymm15, 0x90 + vpsraw zmm24, zmm31, 0x90 + vpsraw xmm2, xmm7, xmm0 + vpsraw xmm2, xmm7, [rbx] + vpsraw xmm2, xmm7, [rbx+r11*8+256] + vpsraw xmm2, xmm7, [rbx+r11*8-256] + vpsraw ymm16, ymm13, xmm0 + vpsraw ymm16, ymm13, [rbx] + vpsraw ymm16, ymm13, [rbx+r11*8+256] + vpsraw ymm16, ymm13, [rbx+r11*8-256] + vpsraw zmm24, zmm24, xmm0 + vpsraw zmm24, zmm24, [rbx] + vpsraw zmm24, zmm24, [rbx+r11*8+256] + vpsraw zmm24, zmm24, [rbx+r11*8-256] + vpsrld xmm7, xmm0, 0x90 + vpsrld ymm13, ymm15, 0x90 + vpsrld zmm24, zmm31, 0x90 + vpsrld xmm2, xmm7, xmm0 + vpsrld xmm2, xmm7, [rbx] + vpsrld xmm2, xmm7, [rbx+r11*8+256] + vpsrld xmm2, xmm7, [rbx+r11*8-256] + vpsrld ymm16, ymm13, xmm0 + vpsrld ymm16, ymm13, [rbx] + vpsrld ymm16, ymm13, [rbx+r11*8+256] + vpsrld ymm16, ymm13, [rbx+r11*8-256] + vpsrld zmm24, zmm24, xmm0 + vpsrld zmm24, zmm24, [rbx] + vpsrld zmm24, zmm24, [rbx+r11*8+256] + vpsrld zmm24, zmm24, [rbx+r11*8-256] + vpsrldq xmm7, xmm0, 0x90 + vpsrldq ymm13, ymm15, 0x90 + vpsrldq zmm24, zmm31, 0x90 + vpsrlq xmm7, xmm0, 0x90 + vpsrlq ymm13, ymm15, 0x90 + vpsrlq zmm24, zmm31, 0x90 + vpsrlq xmm2, xmm7, xmm0 + vpsrlq xmm2, xmm7, [rbx] + vpsrlq xmm2, xmm7, [rbx+r11*8+256] + vpsrlq xmm2, xmm7, [rbx+r11*8-256] + vpsrlq ymm16, ymm13, xmm0 + vpsrlq ymm16, ymm13, [rbx] + vpsrlq ymm16, ymm13, [rbx+r11*8+256] + vpsrlq ymm16, ymm13, [rbx+r11*8-256] + vpsrlq zmm24, zmm24, xmm0 + vpsrlq zmm24, zmm24, [rbx] + vpsrlq zmm24, zmm24, [rbx+r11*8+256] + vpsrlq zmm24, zmm24, [rbx+r11*8-256] + vpsrlw xmm7, xmm0, 0x90 + vpsrlw ymm13, ymm15, 0x90 + vpsrlw zmm24, zmm31, 0x90 + vpsrlw xmm2, xmm7, xmm0 + vpsrlw xmm2, xmm7, [rbx] + vpsrlw xmm2, xmm7, [rbx+r11*8+256] + vpsrlw xmm2, xmm7, [rbx+r11*8-256] + vpsrlw ymm16, ymm13, xmm0 + vpsrlw ymm16, ymm13, [rbx] + vpsrlw ymm16, ymm13, [rbx+r11*8+256] + vpsrlw ymm16, ymm13, [rbx+r11*8-256] + vpsrlw zmm24, zmm24, xmm0 + vpsrlw zmm24, zmm24, [rbx] + vpsrlw zmm24, zmm24, [rbx+r11*8+256] + vpsrlw zmm24, zmm24, [rbx+r11*8-256] + vpsubb xmm2, xmm7, xmm0 + vpsubb xmm2, xmm7, [rbx] + vpsubb xmm2, xmm7, [rbx+r11*8+256] + vpsubb xmm2, xmm7, [rbx+r11*8-256] + vpsubb ymm16, ymm13, ymm15 + vpsubb ymm16, ymm13, [rbx] + vpsubb ymm16, ymm13, [rbx+r11*8+256] + vpsubb ymm16, ymm13, [rbx+r11*8-256] + vpsubb zmm24, zmm24, zmm31 + vpsubb zmm24, zmm24, [rbx] + vpsubb zmm24, zmm24, [rbx+r11*8+256] + vpsubb zmm24, zmm24, [rbx+r11*8-256] + vpsubd xmm2, xmm7, xmm0 + vpsubd xmm2, xmm7, [rbx] + vpsubd xmm2, xmm7, [rbx+r11*8+256] + vpsubd xmm2, xmm7, [rbx+r11*8-256] + vpsubd ymm16, ymm13, ymm15 + vpsubd ymm16, ymm13, [rbx] + vpsubd ymm16, ymm13, [rbx+r11*8+256] + vpsubd ymm16, ymm13, [rbx+r11*8-256] + vpsubd zmm24, zmm24, zmm31 + vpsubd zmm24, zmm24, [rbx] + vpsubd zmm24, zmm24, [rbx+r11*8+256] + vpsubd zmm24, zmm24, [rbx+r11*8-256] + vpsubq xmm2, xmm7, xmm0 + vpsubq xmm2, xmm7, [rbx] + vpsubq xmm2, xmm7, [rbx+r11*8+256] + vpsubq xmm2, xmm7, [rbx+r11*8-256] + vpsubq ymm16, ymm13, ymm15 + vpsubq ymm16, ymm13, [rbx] + vpsubq ymm16, ymm13, [rbx+r11*8+256] + vpsubq ymm16, ymm13, [rbx+r11*8-256] + vpsubq zmm24, zmm24, zmm31 + vpsubq zmm24, zmm24, [rbx] + vpsubq zmm24, zmm24, [rbx+r11*8+256] + vpsubq zmm24, zmm24, [rbx+r11*8-256] + vpsubsb xmm2, xmm7, xmm0 + vpsubsb xmm2, xmm7, [rbx] + vpsubsb xmm2, xmm7, [rbx+r11*8+256] + vpsubsb xmm2, xmm7, [rbx+r11*8-256] + vpsubsb ymm16, ymm13, ymm15 + vpsubsb ymm16, ymm13, [rbx] + vpsubsb ymm16, ymm13, [rbx+r11*8+256] + vpsubsb ymm16, ymm13, [rbx+r11*8-256] + vpsubsb zmm24, zmm24, zmm31 + vpsubsb zmm24, zmm24, [rbx] + vpsubsb zmm24, zmm24, [rbx+r11*8+256] + vpsubsb zmm24, zmm24, [rbx+r11*8-256] + vpsubsw xmm2, xmm7, xmm0 + vpsubsw xmm2, xmm7, [rbx] + vpsubsw xmm2, xmm7, [rbx+r11*8+256] + vpsubsw xmm2, xmm7, [rbx+r11*8-256] + vpsubsw ymm16, ymm13, ymm15 + vpsubsw ymm16, ymm13, [rbx] + vpsubsw ymm16, ymm13, [rbx+r11*8+256] + vpsubsw ymm16, ymm13, [rbx+r11*8-256] + vpsubsw zmm24, zmm24, zmm31 + vpsubsw zmm24, zmm24, [rbx] + vpsubsw zmm24, zmm24, [rbx+r11*8+256] + vpsubsw zmm24, zmm24, [rbx+r11*8-256] + vpsubusb xmm2, xmm7, xmm0 + vpsubusb xmm2, xmm7, [rbx] + vpsubusb xmm2, xmm7, [rbx+r11*8+256] + vpsubusb xmm2, xmm7, [rbx+r11*8-256] + vpsubusb ymm16, ymm13, ymm15 + vpsubusb ymm16, ymm13, [rbx] + vpsubusb ymm16, ymm13, [rbx+r11*8+256] + vpsubusb ymm16, ymm13, [rbx+r11*8-256] + vpsubusb zmm24, zmm24, zmm31 + vpsubusb zmm24, zmm24, [rbx] + vpsubusb zmm24, zmm24, [rbx+r11*8+256] + vpsubusb zmm24, zmm24, [rbx+r11*8-256] + vpsubusw xmm2, xmm7, xmm0 + vpsubusw xmm2, xmm7, [rbx] + vpsubusw xmm2, xmm7, [rbx+r11*8+256] + vpsubusw xmm2, xmm7, [rbx+r11*8-256] + vpsubusw ymm16, ymm13, ymm15 + vpsubusw ymm16, ymm13, [rbx] + vpsubusw ymm16, ymm13, [rbx+r11*8+256] + vpsubusw ymm16, ymm13, [rbx+r11*8-256] + vpsubusw zmm24, zmm24, zmm31 + vpsubusw zmm24, zmm24, [rbx] + vpsubusw zmm24, zmm24, [rbx+r11*8+256] + vpsubusw zmm24, zmm24, [rbx+r11*8-256] + vpsubw xmm2, xmm7, xmm0 + vpsubw xmm2, xmm7, [rbx] + vpsubw xmm2, xmm7, [rbx+r11*8+256] + vpsubw xmm2, xmm7, [rbx+r11*8-256] + vpsubw ymm16, ymm13, ymm15 + vpsubw ymm16, ymm13, [rbx] + vpsubw ymm16, ymm13, [rbx+r11*8+256] + vpsubw ymm16, ymm13, [rbx+r11*8-256] + vpsubw zmm24, zmm24, zmm31 + vpsubw zmm24, zmm24, [rbx] + vpsubw zmm24, zmm24, [rbx+r11*8+256] + vpsubw zmm24, zmm24, [rbx+r11*8-256] + vptest xmm2, xmm0 + vptest xmm2, [rbx] + vptest xmm2, [rbx+r11*8+256] + vptest xmm2, [rbx+r11*8-256] + vpunpckhbw xmm2, xmm7, xmm0 + vpunpckhbw xmm2, xmm7, [rbx] + vpunpckhbw xmm2, xmm7, [rbx+r11*8+256] + vpunpckhbw xmm2, xmm7, [rbx+r11*8-256] + vpunpckhbw ymm16, ymm13, ymm15 + vpunpckhbw ymm16, ymm13, [rbx] + vpunpckhbw ymm16, ymm13, [rbx+r11*8+256] + vpunpckhbw ymm16, ymm13, [rbx+r11*8-256] + vpunpckhbw zmm24, zmm24, zmm31 + vpunpckhbw zmm24, zmm24, [rbx] + vpunpckhbw zmm24, zmm24, [rbx+r11*8+256] + vpunpckhbw zmm24, zmm24, [rbx+r11*8-256] + vpunpckhdq xmm2, xmm7, xmm0 + vpunpckhdq xmm2, xmm7, [rbx] + vpunpckhdq xmm2, xmm7, [rbx+r11*8+256] + vpunpckhdq xmm2, xmm7, [rbx+r11*8-256] + vpunpckhdq ymm16, ymm13, ymm15 + vpunpckhdq ymm16, ymm13, [rbx] + vpunpckhdq ymm16, ymm13, [rbx+r11*8+256] + vpunpckhdq ymm16, ymm13, [rbx+r11*8-256] + vpunpckhdq zmm24, zmm24, zmm31 + vpunpckhdq zmm24, zmm24, [rbx] + vpunpckhdq zmm24, zmm24, [rbx+r11*8+256] + vpunpckhdq zmm24, zmm24, [rbx+r11*8-256] + vpunpckhqdq xmm2, xmm7, xmm0 + vpunpckhqdq xmm2, xmm7, [rbx] + vpunpckhqdq xmm2, xmm7, [rbx+r11*8+256] + vpunpckhqdq xmm2, xmm7, [rbx+r11*8-256] + vpunpckhqdq ymm16, ymm13, ymm15 + vpunpckhqdq ymm16, ymm13, [rbx] + vpunpckhqdq ymm16, ymm13, [rbx+r11*8+256] + vpunpckhqdq ymm16, ymm13, [rbx+r11*8-256] + vpunpckhqdq zmm24, zmm24, zmm31 + vpunpckhqdq zmm24, zmm24, [rbx] + vpunpckhqdq zmm24, zmm24, [rbx+r11*8+256] + vpunpckhqdq zmm24, zmm24, [rbx+r11*8-256] + vpunpckhwd xmm2, xmm7, xmm0 + vpunpckhwd xmm2, xmm7, [rbx] + vpunpckhwd xmm2, xmm7, [rbx+r11*8+256] + vpunpckhwd xmm2, xmm7, [rbx+r11*8-256] + vpunpckhwd ymm16, ymm13, ymm15 + vpunpckhwd ymm16, ymm13, [rbx] + vpunpckhwd ymm16, ymm13, [rbx+r11*8+256] + vpunpckhwd ymm16, ymm13, [rbx+r11*8-256] + vpunpckhwd zmm24, zmm24, zmm31 + vpunpckhwd zmm24, zmm24, [rbx] + vpunpckhwd zmm24, zmm24, [rbx+r11*8+256] + vpunpckhwd zmm24, zmm24, [rbx+r11*8-256] + vpunpcklbw xmm2, xmm7, xmm0 + vpunpcklbw xmm2, xmm7, [rbx] + vpunpcklbw xmm2, xmm7, [rbx+r11*8+256] + vpunpcklbw xmm2, xmm7, [rbx+r11*8-256] + vpunpcklbw ymm16, ymm13, ymm15 + vpunpcklbw ymm16, ymm13, [rbx] + vpunpcklbw ymm16, ymm13, [rbx+r11*8+256] + vpunpcklbw ymm16, ymm13, [rbx+r11*8-256] + vpunpcklbw zmm24, zmm24, zmm31 + vpunpcklbw zmm24, zmm24, [rbx] + vpunpcklbw zmm24, zmm24, [rbx+r11*8+256] + vpunpcklbw zmm24, zmm24, [rbx+r11*8-256] + vpunpckldq xmm2, xmm7, xmm0 + vpunpckldq xmm2, xmm7, [rbx] + vpunpckldq xmm2, xmm7, [rbx+r11*8+256] + vpunpckldq xmm2, xmm7, [rbx+r11*8-256] + vpunpckldq ymm16, ymm13, ymm15 + vpunpckldq ymm16, ymm13, [rbx] + vpunpckldq ymm16, ymm13, [rbx+r11*8+256] + vpunpckldq ymm16, ymm13, [rbx+r11*8-256] + vpunpckldq zmm24, zmm24, zmm31 + vpunpckldq zmm24, zmm24, [rbx] + vpunpckldq zmm24, zmm24, [rbx+r11*8+256] + vpunpckldq zmm24, zmm24, [rbx+r11*8-256] + vpunpcklqdq xmm2, xmm7, xmm0 + vpunpcklqdq xmm2, xmm7, [rbx] + vpunpcklqdq xmm2, xmm7, [rbx+r11*8+256] + vpunpcklqdq xmm2, xmm7, [rbx+r11*8-256] + vpunpcklqdq ymm16, ymm13, ymm15 + vpunpcklqdq ymm16, ymm13, [rbx] + vpunpcklqdq ymm16, ymm13, [rbx+r11*8+256] + vpunpcklqdq ymm16, ymm13, [rbx+r11*8-256] + vpunpcklqdq zmm24, zmm24, zmm31 + vpunpcklqdq zmm24, zmm24, [rbx] + vpunpcklqdq zmm24, zmm24, [rbx+r11*8+256] + vpunpcklqdq zmm24, zmm24, [rbx+r11*8-256] + vpunpcklwd xmm2, xmm7, xmm0 + vpunpcklwd xmm2, xmm7, [rbx] + vpunpcklwd xmm2, xmm7, [rbx+r11*8+256] + vpunpcklwd xmm2, xmm7, [rbx+r11*8-256] + vpunpcklwd ymm16, ymm13, ymm15 + vpunpcklwd ymm16, ymm13, [rbx] + vpunpcklwd ymm16, ymm13, [rbx+r11*8+256] + vpunpcklwd ymm16, ymm13, [rbx+r11*8-256] + vpunpcklwd zmm24, zmm24, zmm31 + vpunpcklwd zmm24, zmm24, [rbx] + vpunpcklwd zmm24, zmm24, [rbx+r11*8+256] + vpunpcklwd zmm24, zmm24, [rbx+r11*8-256] + vpxor xmm2, xmm7, xmm0 + vpxor xmm2, xmm7, [rbx] + vpxor xmm2, xmm7, [rbx+r11*8+256] + vpxor xmm2, xmm7, [rbx+r11*8-256] + vrcpps xmm2, xmm0 + vrcpps xmm2, [rbx] + vrcpps xmm2, [rbx+r11*8+256] + vrcpps xmm2, [rbx+r11*8-256] + vrcpss xmm2, xmm7, xmm0 + vrcpss xmm2, xmm7, [rbx] + vrcpss xmm2, xmm7, [rbx+r11*8+256] + vrcpss xmm2, xmm7, [rbx+r11*8-256] + vroundpd xmm2, xmm0, 0x90 + vroundpd xmm2, [rbx], 0x90 + vroundpd xmm2, [rbx+r11*8+256], 0x90 + vroundpd xmm2, [rbx+r11*8-256], 0x90 + vroundps xmm2, xmm0, 0x90 + vroundps xmm2, [rbx], 0x90 + vroundps xmm2, [rbx+r11*8+256], 0x90 + vroundps xmm2, [rbx+r11*8-256], 0x90 + vroundsd xmm2, xmm7, xmm0, 0x90 + vroundsd xmm2, xmm7, [rbx], 0x90 + vroundsd xmm2, xmm7, [rbx+r11*8+256], 0x90 + vroundsd xmm2, xmm7, [rbx+r11*8-256], 0x90 + vroundss xmm2, xmm7, xmm0, 0x90 + vroundss xmm2, xmm7, [rbx], 0x90 + vroundss xmm2, xmm7, [rbx+r11*8+256], 0x90 + vroundss xmm2, xmm7, [rbx+r11*8-256], 0x90 + vrsqrtps xmm2, xmm0 + vrsqrtps xmm2, [rbx] + vrsqrtps xmm2, [rbx+r11*8+256] + vrsqrtps xmm2, [rbx+r11*8-256] + vrsqrtss xmm2, xmm7, xmm0 + vrsqrtss xmm2, xmm7, [rbx] + vrsqrtss xmm2, xmm7, [rbx+r11*8+256] + vrsqrtss xmm2, xmm7, [rbx+r11*8-256] + vshufpd xmm2, xmm7, xmm0, 0x90 + vshufpd xmm2, xmm7, [rbx], 0x90 + vshufpd xmm2, xmm7, [rbx+r11*8+256], 0x90 + vshufpd xmm2, xmm7, [rbx+r11*8-256], 0x90 + vshufpd ymm16, ymm13, ymm15, 0x90 + vshufpd ymm16, ymm13, [rbx], 0x90 + vshufpd ymm16, ymm13, [rbx+r11*8+256], 0x90 + vshufpd ymm16, ymm13, [rbx+r11*8-256], 0x90 + vshufpd zmm24, zmm24, zmm31, 0x90 + vshufpd zmm24, zmm24, [rbx], 0x90 + vshufpd zmm24, zmm24, [rbx+r11*8+256], 0x90 + vshufpd zmm24, zmm24, [rbx+r11*8-256], 0x90 + vshufps xmm2, xmm7, xmm0, 0x90 + vshufps xmm2, xmm7, [rbx], 0x90 + vshufps xmm2, xmm7, [rbx+r11*8+256], 0x90 + vshufps xmm2, xmm7, [rbx+r11*8-256], 0x90 + vshufps ymm16, ymm13, ymm15, 0x90 + vshufps ymm16, ymm13, [rbx], 0x90 + vshufps ymm16, ymm13, [rbx+r11*8+256], 0x90 + vshufps ymm16, ymm13, [rbx+r11*8-256], 0x90 + vshufps zmm24, zmm24, zmm31, 0x90 + vshufps zmm24, zmm24, [rbx], 0x90 + vshufps zmm24, zmm24, [rbx+r11*8+256], 0x90 + vshufps zmm24, zmm24, [rbx+r11*8-256], 0x90 + vsqrtpd xmm2, xmm0 + vsqrtpd xmm2, [rbx] + vsqrtpd xmm2, [rbx+r11*8+256] + vsqrtpd xmm2, [rbx+r11*8-256] + vsqrtpd ymm16, ymm15 + vsqrtpd ymm16, [rbx] + vsqrtpd ymm16, [rbx+r11*8+256] + vsqrtpd ymm16, [rbx+r11*8-256] + vsqrtpd zmm24, zmm31 + vsqrtpd zmm24, [rbx] + vsqrtpd zmm24, [rbx+r11*8+256] + vsqrtpd zmm24, [rbx+r11*8-256] + vsqrtps xmm2, xmm0 + vsqrtps xmm2, [rbx] + vsqrtps xmm2, [rbx+r11*8+256] + vsqrtps xmm2, [rbx+r11*8-256] + vsqrtps ymm16, ymm15 + vsqrtps ymm16, [rbx] + vsqrtps ymm16, [rbx+r11*8+256] + vsqrtps ymm16, [rbx+r11*8-256] + vsqrtps zmm24, zmm31 + vsqrtps zmm24, [rbx] + vsqrtps zmm24, [rbx+r11*8+256] + vsqrtps zmm24, [rbx+r11*8-256] + vsqrtsd xmm2, xmm7, xmm0 + vsqrtsd xmm2, xmm7, [rbx] + vsqrtsd xmm2, xmm7, [rbx+r11*8+256] + vsqrtsd xmm2, xmm7, [rbx+r11*8-256] + vsqrtss xmm2, xmm7, xmm0 + vsqrtss xmm2, xmm7, [rbx] + vsqrtss xmm2, xmm7, [rbx+r11*8+256] + vsqrtss xmm2, xmm7, [rbx+r11*8-256] + vstmxcsr [rbx] + vstmxcsr [rbx+rsi*8+256] + vstmxcsr [rbx+rsi*8-256] + vsubpd xmm2, xmm7, xmm0 + vsubpd xmm2, xmm7, [rbx] + vsubpd xmm2, xmm7, [rbx+r11*8+256] + vsubpd xmm2, xmm7, [rbx+r11*8-256] + vsubpd ymm16, ymm13, ymm15 + vsubpd ymm16, ymm13, [rbx] + vsubpd ymm16, ymm13, [rbx+r11*8+256] + vsubpd ymm16, ymm13, [rbx+r11*8-256] + vsubpd zmm24, zmm24, zmm31 + vsubpd zmm24, zmm24, [rbx] + vsubpd zmm24, zmm24, [rbx+r11*8+256] + vsubpd zmm24, zmm24, [rbx+r11*8-256] + vsubps xmm2, xmm7, xmm0 + vsubps xmm2, xmm7, [rbx] + vsubps xmm2, xmm7, [rbx+r11*8+256] + vsubps xmm2, xmm7, [rbx+r11*8-256] + vsubps ymm16, ymm13, ymm15 + vsubps ymm16, ymm13, [rbx] + vsubps ymm16, ymm13, [rbx+r11*8+256] + vsubps ymm16, ymm13, [rbx+r11*8-256] + vsubps zmm24, zmm24, zmm31 + vsubps zmm24, zmm24, [rbx] + vsubps zmm24, zmm24, [rbx+r11*8+256] + vsubps zmm24, zmm24, [rbx+r11*8-256] + vsubsd xmm2, xmm7, xmm0 + vsubsd xmm2, xmm7, [rbx] + vsubsd xmm2, xmm7, [rbx+r11*8+256] + vsubsd xmm2, xmm7, [rbx+r11*8-256] + vsubss xmm2, xmm7, xmm0 + vsubss xmm2, xmm7, [rbx] + vsubss xmm2, xmm7, [rbx+r11*8+256] + vsubss xmm2, xmm7, [rbx+r11*8-256] + vtestpd xmm2, xmm0 + vtestpd xmm2, [rbx] + vtestpd xmm2, [rbx+r11*8+256] + vtestpd xmm2, [rbx+r11*8-256] + vtestps xmm2, xmm0 + vtestps xmm2, [rbx] + vtestps xmm2, [rbx+r11*8+256] + vtestps xmm2, [rbx+r11*8-256] + vucomisd xmm2, xmm0 + vucomisd xmm2, [rbx] + vucomisd xmm2, [rbx+r11*8+256] + vucomisd xmm2, [rbx+r11*8-256] + vucomiss xmm2, xmm0 + vucomiss xmm2, [rbx] + vucomiss xmm2, [rbx+r11*8+256] + vucomiss xmm2, [rbx+r11*8-256] + vunpckhpd xmm2, xmm7, xmm0 + vunpckhpd xmm2, xmm7, [rbx] + vunpckhpd xmm2, xmm7, [rbx+r11*8+256] + vunpckhpd xmm2, xmm7, [rbx+r11*8-256] + vunpckhpd ymm16, ymm13, ymm15 + vunpckhpd ymm16, ymm13, [rbx] + vunpckhpd ymm16, ymm13, [rbx+r11*8+256] + vunpckhpd ymm16, ymm13, [rbx+r11*8-256] + vunpckhpd zmm24, zmm24, zmm31 + vunpckhpd zmm24, zmm24, [rbx] + vunpckhpd zmm24, zmm24, [rbx+r11*8+256] + vunpckhpd zmm24, zmm24, [rbx+r11*8-256] + vunpckhps xmm2, xmm7, xmm0 + vunpckhps xmm2, xmm7, [rbx] + vunpckhps xmm2, xmm7, [rbx+r11*8+256] + vunpckhps xmm2, xmm7, [rbx+r11*8-256] + vunpckhps ymm16, ymm13, ymm15 + vunpckhps ymm16, ymm13, [rbx] + vunpckhps ymm16, ymm13, [rbx+r11*8+256] + vunpckhps ymm16, ymm13, [rbx+r11*8-256] + vunpckhps zmm24, zmm24, zmm31 + vunpckhps zmm24, zmm24, [rbx] + vunpckhps zmm24, zmm24, [rbx+r11*8+256] + vunpckhps zmm24, zmm24, [rbx+r11*8-256] + vunpcklpd xmm2, xmm7, xmm0 + vunpcklpd xmm2, xmm7, [rbx] + vunpcklpd xmm2, xmm7, [rbx+r11*8+256] + vunpcklpd xmm2, xmm7, [rbx+r11*8-256] + vunpcklpd ymm16, ymm13, ymm15 + vunpcklpd ymm16, ymm13, [rbx] + vunpcklpd ymm16, ymm13, [rbx+r11*8+256] + vunpcklpd ymm16, ymm13, [rbx+r11*8-256] + vunpcklpd zmm24, zmm24, zmm31 + vunpcklpd zmm24, zmm24, [rbx] + vunpcklpd zmm24, zmm24, [rbx+r11*8+256] + vunpcklpd zmm24, zmm24, [rbx+r11*8-256] + vunpcklps xmm2, xmm7, xmm0 + vunpcklps xmm2, xmm7, [rbx] + vunpcklps xmm2, xmm7, [rbx+r11*8+256] + vunpcklps xmm2, xmm7, [rbx+r11*8-256] + vunpcklps ymm16, ymm13, ymm15 + vunpcklps ymm16, ymm13, [rbx] + vunpcklps ymm16, ymm13, [rbx+r11*8+256] + vunpcklps ymm16, ymm13, [rbx+r11*8-256] + vunpcklps zmm24, zmm24, zmm31 + vunpcklps zmm24, zmm24, [rbx] + vunpcklps zmm24, zmm24, [rbx+r11*8+256] + vunpcklps zmm24, zmm24, [rbx+r11*8-256] + vxorpd xmm2, xmm7, xmm0 + vxorpd xmm2, xmm7, [rbx] + vxorpd xmm2, xmm7, [rbx+r11*8+256] + vxorpd xmm2, xmm7, [rbx+r11*8-256] + vxorpd ymm16, ymm13, ymm15 + vxorpd ymm16, ymm13, [rbx] + vxorpd ymm16, ymm13, [rbx+r11*8+256] + vxorpd ymm16, ymm13, [rbx+r11*8-256] + vxorpd zmm24, zmm24, zmm31 + vxorpd zmm24, zmm24, [rbx] + vxorpd zmm24, zmm24, [rbx+r11*8+256] + vxorpd zmm24, zmm24, [rbx+r11*8-256] + vxorps xmm2, xmm7, xmm0 + vxorps xmm2, xmm7, [rbx] + vxorps xmm2, xmm7, [rbx+r11*8+256] + vxorps xmm2, xmm7, [rbx+r11*8-256] + vxorps ymm16, ymm13, ymm15 + vxorps ymm16, ymm13, [rbx] + vxorps ymm16, ymm13, [rbx+r11*8+256] + vxorps ymm16, ymm13, [rbx+r11*8-256] + vxorps zmm24, zmm24, zmm31 + vxorps zmm24, zmm24, [rbx] + vxorps zmm24, zmm24, [rbx+r11*8+256] + vxorps zmm24, zmm24, [rbx+r11*8-256] diff --git a/bddisasm_test/avx/avx_64.result b/bddisasm_test/avx/avx_64.result new file mode 100644 index 0000000..74eeb88 --- /dev/null +++ b/bddisasm_test/avx/avx_64.result @@ -0,0 +1,40788 @@ +0000000000000000 c5c158d0 VADDPD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000004 c5c15813 VADDPD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000008 c4a1415894db00010000 VADDPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000012 c4a1415894db00ffffff VADDPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +000000000000001C 62c1952858c7 VADDPD ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000022 62e195285803 VADDPD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000028 62a195285844db08 VADDPD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000030 62a195285844dbf8 VADDPD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000038 6201bd4058c7 VADDPD zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000003E 6261bd405803 VADDPD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000044 6221bd405844db04 VADDPD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000004C 6221bd405844dbfc VADDPD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000054 c5c058d0 VADDPS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000058 c5c05813 VADDPS xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000005C c4a1405894db00010000 VADDPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000066 c4a1405894db00ffffff VADDPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000070 62c1142858c7 VADDPS ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000076 62e114285803 VADDPS ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000007C 62a114285844db08 VADDPS ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000084 62a114285844dbf8 VADDPS ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000008C 62013c4058c7 VADDPS zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000092 62613c405803 VADDPS zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000098 62213c405844db04 VADDPS zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000000A0 62213c405844dbfc VADDPS zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000000A8 c5c358d0 VADDSD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000000AC c5c35813 VADDSD xmm2, xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000000B0 c4a1435894db00010000 VADDSD xmm2, xmm7, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000000BA c4a1435894db00ffffff VADDSD xmm2, xmm7, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000000C4 c5c258d0 VADDSS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000000C8 c5c25813 VADDSS xmm2, xmm7, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +00000000000000CC c4a1425894db00010000 VADDSS xmm2, xmm7, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000000D6 c4a1425894db00ffffff VADDSS xmm2, xmm7, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000000E0 c5c1d0d0 VADDSUBPD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000000E4 c5c1d013 VADDSUBPD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000000E8 c4a141d094db00010000 VADDSUBPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000000F2 c4a141d094db00ffffff VADDSUBPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000000FC c5c3d0d0 VADDSUBPS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000100 c5c3d013 VADDSUBPS xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000104 c4a143d094db00010000 VADDSUBPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000010E c4a143d094db00ffffff VADDSUBPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000118 c5c155d0 VANDNPD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000011C c5c15513 VANDNPD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000120 c4a1415594db00010000 VANDNPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000012A c4a1415594db00ffffff VANDNPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000134 62c1952855c7 VANDNPD ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000013A 62e195285503 VANDNPD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000140 62a195285544db08 VANDNPD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000148 62a195285544dbf8 VANDNPD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000150 6201bd4055c7 VANDNPD zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000156 6261bd405503 VANDNPD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000015C 6221bd405544db04 VANDNPD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000164 6221bd405544dbfc VANDNPD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000016C c5c055d0 VANDNPS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000170 c5c05513 VANDNPS xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000174 c4a1405594db00010000 VANDNPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000017E c4a1405594db00ffffff VANDNPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000188 62c1142855c7 VANDNPS ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000018E 62e114285503 VANDNPS ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000194 62a114285544db08 VANDNPS ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000019C 62a114285544dbf8 VANDNPS ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000001A4 62013c4055c7 VANDNPS zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000001AA 62613c405503 VANDNPS zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000001B0 62213c405544db04 VANDNPS zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000001B8 62213c405544dbfc VANDNPS zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000001C0 c5c154d0 VANDPD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000001C4 c5c15413 VANDPD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000001C8 c4a1415494db00010000 VANDPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000001D2 c4a1415494db00ffffff VANDPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000001DC 62c1952854c7 VANDPD ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000001E2 62e195285403 VANDPD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000001E8 62a195285444db08 VANDPD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000001F0 62a195285444dbf8 VANDPD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000001F8 6201bd4054c7 VANDPD zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000001FE 6261bd405403 VANDPD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000204 6221bd405444db04 VANDPD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000020C 6221bd405444dbfc VANDPD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000214 c5c054d0 VANDPS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000218 c5c05413 VANDPS xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000021C c4a1405494db00010000 VANDPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000226 c4a1405494db00ffffff VANDPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000230 62c1142854c7 VANDPS ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000236 62e114285403 VANDPS ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000023C 62a114285444db08 VANDPS ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000244 62a114285444dbf8 VANDPS ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000024C 62013c4054c7 VANDPS zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000252 62613c405403 VANDPS zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000258 62213c405444db04 VANDPS zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000260 62213c405444dbfc VANDPS zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000268 c4e3410dd090 VBLENDPD xmm2, xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000026E c4e3410d1390 VBLENDPD xmm2, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000274 c4a3410d94db0001000090 VBLENDPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000027F c4a3410d94db00ffffff90 VBLENDPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000028A c4e3410cd090 VBLENDPS xmm2, xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000290 c4e3410c1390 VBLENDPS xmm2, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000296 c4a3410c94db0001000090 VBLENDPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000002A1 c4a3410c94db00ffffff90 VBLENDPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000002AC c4e3414bd030 VBLENDVPD xmm2, xmm7, xmm0, xmm3 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 3, RegCount: 1 + +00000000000002B2 c4e3414b1330 VBLENDVPD xmm2, xmm7, xmmword ptr [rbx], xmm3 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 3, RegCount: 1 + +00000000000002B8 c4a3414b94db0001000030 VBLENDVPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], xmm3 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 3, RegCount: 1 + +00000000000002C3 c4a3414b94db00ffffff30 VBLENDVPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], xmm3 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 3, RegCount: 1 + +00000000000002CE c4e3414ad030 VBLENDVPS xmm2, xmm7, xmm0, xmm3 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 3, RegCount: 1 + +00000000000002D4 c4e3414a1330 VBLENDVPS xmm2, xmm7, xmmword ptr [rbx], xmm3 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 3, RegCount: 1 + +00000000000002DA c4a3414a94db0001000030 VBLENDVPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], xmm3 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 3, RegCount: 1 + +00000000000002E5 c4a3414a94db00ffffff30 VBLENDVPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], xmm3 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 3, RegCount: 1 + +00000000000002F0 62e2fd2819c0 VBROADCASTSD ymm16, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000002F6 62e2fd281903 VBROADCASTSD ymm16, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000002FC 62a2fd281944db20 VBROADCASTSD ymm16, qword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000000304 62a2fd281944dbe0 VBROADCASTSD ymm16, qword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +000000000000030C 6262fd4819c0 VBROADCASTSD zmm24, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000312 6262fd481903 VBROADCASTSD zmm24, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000318 6222fd481944db20 VBROADCASTSD zmm24, qword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000000320 6222fd481944dbe0 VBROADCASTSD zmm24, qword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +0000000000000328 c4e27918d0 VBROADCASTSS xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000032D c4e2791813 VBROADCASTSS xmm2, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +0000000000000332 c4a2791894db00010000 VBROADCASTSS xmm2, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000033C c4a2791894db00ffffff VBROADCASTSS xmm2, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000346 62e27d2818c0 VBROADCASTSS ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000034C 62e27d281803 VBROADCASTSS ymm16, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +0000000000000352 62a27d281844db40 VBROADCASTSS ymm16, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000040, + +000000000000035A 62a27d281844dbc0 VBROADCASTSS ymm16, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffc0, + +0000000000000362 62627d4818c0 VBROADCASTSS zmm24, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000368 62627d481803 VBROADCASTSS zmm24, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +000000000000036E 62227d481844db40 VBROADCASTSS zmm24, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000040, + +0000000000000376 62227d481844dbc0 VBROADCASTSS zmm24, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffc0, + +000000000000037E c5c1c2d090 VCMPPD xmm2, xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000383 c5c1c21390 VCMPPD xmm2, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000388 c4a141c294db0001000090 VCMPPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000393 c4a141c294db00ffffff90 VCMPPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000039E c5c3c2d090 VCMPSD xmm2, xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000003A3 c5c3c21390 VCMPSD xmm2, xmm7, qword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000003A8 c4a143c294db0001000090 VCMPSD xmm2, xmm7, qword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000003B3 c4a143c294db00ffffff90 VCMPSD xmm2, xmm7, qword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000003BE c5c2c2d090 VCMPSS xmm2, xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000003C3 c5c2c21390 VCMPSS xmm2, xmm7, dword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000003C8 c4a142c294db0001000090 VCMPSS xmm2, xmm7, dword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000003D3 c4a142c294db00ffffff90 VCMPSS xmm2, xmm7, dword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000003DE c5c2c2d090 VCMPSS xmm2, xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000003E3 c5c2c21390 VCMPSS xmm2, xmm7, dword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000003E8 c4a142c294db0001000090 VCMPSS xmm2, xmm7, dword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000003F3 c4a142c294db00ffffff90 VCMPSS xmm2, xmm7, dword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000003FE c5f92fd0 VCOMISD xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + FLAGS access + CF: m, PF: m, ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000402 c5f92f13 VCOMISD xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + FLAGS access + CF: m, PF: m, ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000406 c4a1792f94db00010000 VCOMISD xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + FLAGS access + CF: m, PF: m, ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000410 c4a1792f94db00ffffff VCOMISD xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + FLAGS access + CF: m, PF: m, ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000041A c5f82fd0 VCOMISS xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + FLAGS access + CF: m, PF: m, ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000041E c5f82f13 VCOMISS xmm2, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + FLAGS access + CF: m, PF: m, ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000422 c4a1782f94db00010000 VCOMISS xmm2, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + FLAGS access + CF: m, PF: m, ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000042C c4a1782f94db00ffffff VCOMISS xmm2, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + FLAGS access + CF: m, PF: m, ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000436 c5fae6d0 VCVTDQ2PD xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000043A c5fae613 VCVTDQ2PD xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000043E c4a17ae694db00010000 VCVTDQ2PD xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000448 c4a17ae694db00ffffff VCVTDQ2PD xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000452 62e17e28e6c0 VCVTDQ2PD ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000458 62e17e28e603 VCVTDQ2PD ymm16, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000045E 62a17e28e644db10 VCVTDQ2PD ymm16, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000466 62a17e28e644dbf0 VCVTDQ2PD ymm16, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000046E 62417e48e6c7 VCVTDQ2PD zmm24, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000474 62617e48e603 VCVTDQ2PD zmm24, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000047A 62217e48e644db08 VCVTDQ2PD zmm24, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000482 62217e48e644dbf8 VCVTDQ2PD zmm24, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000048A c5fae6d0 VCVTDQ2PD xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000048E c5fae613 VCVTDQ2PD xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000492 c4a17ae694db00010000 VCVTDQ2PD xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000049C c4a17ae694db00ffffff VCVTDQ2PD xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000004A6 62e17e28e6c0 VCVTDQ2PD ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000004AC 62e17e28e603 VCVTDQ2PD ymm16, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000004B2 62a17e28e644db10 VCVTDQ2PD ymm16, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000004BA 62a17e28e644dbf0 VCVTDQ2PD ymm16, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000004C2 62417e48e6c7 VCVTDQ2PD zmm24, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000004C8 62617e48e603 VCVTDQ2PD zmm24, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000004CE 62217e48e644db08 VCVTDQ2PD zmm24, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000004D6 62217e48e644dbf8 VCVTDQ2PD zmm24, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000004DE c5f85bd0 VCVTDQ2PS xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000004E2 c5f85b13 VCVTDQ2PS xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000004E6 c4a1785b94db00010000 VCVTDQ2PS xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000004F0 c4a1785b94db00ffffff VCVTDQ2PS xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000004FA 62c17c285bc7 VCVTDQ2PS ymm16, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000500 62e17c285b03 VCVTDQ2PS ymm16, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000506 62a17c285b44db08 VCVTDQ2PS ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000050E 62a17c285b44dbf8 VCVTDQ2PS ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000516 62017c485bc7 VCVTDQ2PS zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000051C 62617c485b03 VCVTDQ2PS zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000522 62217c485b44db04 VCVTDQ2PS zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000052A 62217c485b44dbfc VCVTDQ2PS zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000532 c5fbe6d0 VCVTPD2DQ xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000536 c4c17fe6d7 VCVTPD2DQ xmm2, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000053B c5fbe613 VCVTPD2DQ xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000053F c4a17be694db00010000 VCVTPD2DQ xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000549 c4a17be694db00ffffff VCVTPD2DQ xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000553 6281ff48e6c7 VCVTPD2DQ ymm16, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000559 62e1ff48e603 VCVTPD2DQ ymm16, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000055F 62a1ff48e644db04 VCVTPD2DQ ymm16, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000567 62a1ff48e644dbfc VCVTPD2DQ ymm16, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000056F c5f95ad0 VCVTPD2PS xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000573 c4c17d5ad7 VCVTPD2PS xmm2, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000578 c5f95a13 VCVTPD2PS xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000057C c4a1795a94db00010000 VCVTPD2PS xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000586 c4a1795a94db00ffffff VCVTPD2PS xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000590 6281fd485ac7 VCVTPD2PS ymm16, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000596 62e1fd485a03 VCVTPD2PS ymm16, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000059C 62a1fd485a44db04 VCVTPD2PS ymm16, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000005A4 62a1fd485a44dbfc VCVTPD2PS ymm16, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000005AC c5f95ad0 VCVTPD2PS xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000005B0 c4c17d5ad7 VCVTPD2PS xmm2, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000005B5 c5f95a13 VCVTPD2PS xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000005B9 c4a1795a94db00010000 VCVTPD2PS xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000005C3 c4a1795a94db00ffffff VCVTPD2PS xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000005CD 6281fd485ac7 VCVTPD2PS ymm16, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000005D3 62e1fd485a03 VCVTPD2PS ymm16, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000005D9 62a1fd485a44db04 VCVTPD2PS ymm16, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000005E1 62a1fd485a44dbfc VCVTPD2PS ymm16, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000005E9 c5f95bd0 VCVTPS2DQ xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000005ED c5f95b13 VCVTPS2DQ xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000005F1 c4a1795b94db00010000 VCVTPS2DQ xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000005FB c4a1795b94db00ffffff VCVTPS2DQ xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000605 62c17d285bc7 VCVTPS2DQ ymm16, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000060B 62e17d285b03 VCVTPS2DQ ymm16, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000611 62a17d285b44db08 VCVTPS2DQ ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000619 62a17d285b44dbf8 VCVTPS2DQ ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000621 62017d485bc7 VCVTPS2DQ zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000627 62617d485b03 VCVTPS2DQ zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000062D 62217d485b44db04 VCVTPS2DQ zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000635 62217d485b44dbfc VCVTPS2DQ zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000063D c5f85ad0 VCVTPS2PD xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000641 c5f85a13 VCVTPS2PD xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000645 c4a1785a94db00010000 VCVTPS2PD xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000064F c4a1785a94db00ffffff VCVTPS2PD xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000659 62e17c285ac0 VCVTPS2PD ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000065F 62e17c285a03 VCVTPS2PD ymm16, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000665 62a17c285a44db10 VCVTPS2PD ymm16, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000066D 62a17c285a44dbf0 VCVTPS2PD ymm16, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000675 62417c485ac7 VCVTPS2PD zmm24, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000067B 62617c485a03 VCVTPS2PD zmm24, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000681 62217c485a44db08 VCVTPS2PD zmm24, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000689 62217c485a44dbf8 VCVTPS2PD zmm24, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000691 c5f85ad0 VCVTPS2PD xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000695 c5f85a13 VCVTPS2PD xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000699 c4a1785a94db00010000 VCVTPS2PD xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000006A3 c4a1785a94db00ffffff VCVTPS2PD xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000006AD 62e17c285ac0 VCVTPS2PD ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000006B3 62e17c285a03 VCVTPS2PD ymm16, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000006B9 62a17c285a44db10 VCVTPS2PD ymm16, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000006C1 62a17c285a44dbf0 VCVTPS2PD ymm16, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000006C9 62417c485ac7 VCVTPS2PD zmm24, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000006CF 62617c485a03 VCVTPS2PD zmm24, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000006D5 62217c485a44db08 VCVTPS2PD zmm24, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000006DD 62217c485a44dbf8 VCVTPS2PD zmm24, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000006E5 c5fb2dc8 VCVTSD2SI ecx, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000006E9 c5fb2d0b VCVTSD2SI ecx, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000006ED c4a17b2d8cdb00010000 VCVTSD2SI ecx, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000006F7 c4a17b2d8cdb00ffffff VCVTSD2SI ecx, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000701 c4e1fb2dc8 VCVTSD2SI rcx, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000706 c4e1fb2d0b VCVTSD2SI rcx, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000070B c4a1fb2d8cdb00010000 VCVTSD2SI rcx, qword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000715 c4a1fb2d8cdb00ffffff VCVTSD2SI rcx, qword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +000000000000071F c5c35ad0 VCVTSD2SS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000723 c5c35a13 VCVTSD2SS xmm2, xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000727 c4a1435a94db00010000 VCVTSD2SS xmm2, xmm7, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000731 c4a1435a94db00ffffff VCVTSD2SS xmm2, xmm7, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +000000000000073B c5c32ad1 VCVTSI2SD xmm2, xmm7, ecx + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + +000000000000073F c4e1c32ad1 VCVTSI2SD xmm2, xmm7, rcx + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + +0000000000000744 c5c32a13 VCVTSI2SD xmm2, xmm7, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +0000000000000748 c5c32a94f300010000 VCVTSI2SD xmm2, xmm7, dword ptr [rbx+rsi*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + +0000000000000751 c5c22ad1 VCVTSI2SS xmm2, xmm7, ecx + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + +0000000000000755 c4e1c22ad1 VCVTSI2SS xmm2, xmm7, rcx + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + +000000000000075A c5c22a13 VCVTSI2SS xmm2, xmm7, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +000000000000075E c5c22a94f300010000 VCVTSI2SS xmm2, xmm7, dword ptr [rbx+rsi*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + +0000000000000767 c5c25ad0 VCVTSS2SD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000076B c5c25a13 VCVTSS2SD xmm2, xmm7, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +000000000000076F c4a1425a94db00010000 VCVTSS2SD xmm2, xmm7, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000779 c4a1425a94db00ffffff VCVTSS2SD xmm2, xmm7, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000783 c5fa2dc8 VCVTSS2SI ecx, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000787 c5fa2d0b VCVTSS2SI ecx, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +000000000000078B c4a17a2d8cdb00010000 VCVTSS2SI ecx, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000795 c4a17a2d8cdb00ffffff VCVTSS2SI ecx, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +000000000000079F c4e1fa2dc8 VCVTSS2SI rcx, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000007A4 c4e1fa2d0b VCVTSS2SI rcx, dword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +00000000000007A9 c4a1fa2d8cdb00010000 VCVTSS2SI rcx, dword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000007B3 c4a1fa2d8cdb00ffffff VCVTSS2SI rcx, dword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000007BD c5f9e6d0 VCVTTPD2DQ xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000007C1 c4c17de6d7 VCVTTPD2DQ xmm2, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000007C6 c5f9e613 VCVTTPD2DQ xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000007CA c4a179e694db00010000 VCVTTPD2DQ xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000007D4 c4a179e694db00ffffff VCVTTPD2DQ xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000007DE 6281fd48e6c7 VCVTTPD2DQ ymm16, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000007E4 62e1fd48e603 VCVTTPD2DQ ymm16, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000007EA 62a1fd48e644db04 VCVTTPD2DQ ymm16, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000007F2 62a1fd48e644dbfc VCVTTPD2DQ ymm16, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000007FA c5fa5bd0 VCVTTPS2DQ xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000007FE c5fa5b13 VCVTTPS2DQ xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000802 c4a17a5b94db00010000 VCVTTPS2DQ xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000080C c4a17a5b94db00ffffff VCVTTPS2DQ xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000816 62c17e285bc7 VCVTTPS2DQ ymm16, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000081C 62e17e285b03 VCVTTPS2DQ ymm16, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000822 62a17e285b44db08 VCVTTPS2DQ ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000082A 62a17e285b44dbf8 VCVTTPS2DQ ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000832 62017e485bc7 VCVTTPS2DQ zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000838 62617e485b03 VCVTTPS2DQ zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000083E 62217e485b44db04 VCVTTPS2DQ zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000846 62217e485b44dbfc VCVTTPS2DQ zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000084E c5fb2cc8 VCVTTSD2SI ecx, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000852 c5fb2c0b VCVTTSD2SI ecx, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000856 c4a17b2c8cdb00010000 VCVTTSD2SI ecx, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000860 c4a17b2c8cdb00ffffff VCVTTSD2SI ecx, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +000000000000086A c4e1fb2cc8 VCVTTSD2SI rcx, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000086F c4e1fb2c0b VCVTTSD2SI rcx, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000874 c4a1fb2c8cdb00010000 VCVTTSD2SI rcx, qword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000087E c4a1fb2c8cdb00ffffff VCVTTSD2SI rcx, qword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000888 c5fa2cc8 VCVTTSS2SI ecx, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000088C c5fa2c0b VCVTTSS2SI ecx, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +0000000000000890 c4a17a2c8cdb00010000 VCVTTSS2SI ecx, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000089A c4a17a2c8cdb00ffffff VCVTTSS2SI ecx, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000008A4 c4e1fa2cc8 VCVTTSS2SI rcx, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000008A9 c4e1fa2c0b VCVTTSS2SI rcx, dword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +00000000000008AE c4a1fa2c8cdb00010000 VCVTTSS2SI rcx, dword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000008B8 c4a1fa2c8cdb00ffffff VCVTTSS2SI rcx, dword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000008C2 c5c15ed0 VDIVPD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000008C6 c5c15e13 VDIVPD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000008CA c4a1415e94db00010000 VDIVPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000008D4 c4a1415e94db00ffffff VDIVPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000008DE 62c195285ec7 VDIVPD ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000008E4 62e195285e03 VDIVPD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000008EA 62a195285e44db08 VDIVPD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000008F2 62a195285e44dbf8 VDIVPD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000008FA 6201bd405ec7 VDIVPD zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000900 6261bd405e03 VDIVPD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000906 6221bd405e44db04 VDIVPD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000090E 6221bd405e44dbfc VDIVPD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000916 c5c05ed0 VDIVPS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000091A c5c05e13 VDIVPS xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000091E c4a1405e94db00010000 VDIVPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000928 c4a1405e94db00ffffff VDIVPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000932 62c114285ec7 VDIVPS ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000938 62e114285e03 VDIVPS ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000093E 62a114285e44db08 VDIVPS ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000946 62a114285e44dbf8 VDIVPS ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000094E 62013c405ec7 VDIVPS zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000954 62613c405e03 VDIVPS zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000095A 62213c405e44db04 VDIVPS zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000962 62213c405e44dbfc VDIVPS zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000096A c5c35ed0 VDIVSD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000096E c5c35e13 VDIVSD xmm2, xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000972 c4a1435e94db00010000 VDIVSD xmm2, xmm7, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000097C c4a1435e94db00ffffff VDIVSD xmm2, xmm7, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000986 c5c25ed0 VDIVSS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000098A c5c25e13 VDIVSS xmm2, xmm7, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +000000000000098E c4a1425e94db00010000 VDIVSS xmm2, xmm7, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000998 c4a1425e94db00ffffff VDIVSS xmm2, xmm7, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000009A2 c4e34141d090 VDPPD xmm2, xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000009A8 c4e341411390 VDPPD xmm2, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000009AE c4a3414194db0001000090 VDPPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000009B9 c4a3414194db00ffffff90 VDPPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000009C4 c4e34140d090 VDPPS xmm2, xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000009CA c4e341401390 VDPPS xmm2, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000009D0 c4a3414094db0001000090 VDPPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000009DB c4a3414094db00ffffff90 VDPPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000009E6 c4e379171390 VEXTRACTPS dword ptr [rbx], xmm2, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000009EC c4e3791794f30001000090 VEXTRACTPS dword ptr [rbx+rsi*8+0x100], xmm2, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000009F7 c4e3791794f300ffffff90 VEXTRACTPS dword ptr [rbx+rsi*8-0x100], xmm2, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000A02 c4e37917d190 VEXTRACTPS ecx, xmm2, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000A08 62f37d0817d190 VEXTRACTPS ecx, xmm2, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E9NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000A0F c5c17cd0 VHADDPD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000A13 c5c17c13 VHADDPD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000A17 c4a1417c94db00010000 VHADDPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000A21 c4a1417c94db00ffffff VHADDPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000A2B c5c37cd0 VHADDPS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000A2F c5c37c13 VHADDPS xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000A33 c4a1437c94db00010000 VHADDPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000A3D c4a1437c94db00ffffff VHADDPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000A47 c5c17dd0 VHSUBPD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000A4B c5c17d13 VHSUBPD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000A4F c4a1417d94db00010000 VHSUBPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000A59 c4a1417d94db00ffffff VHSUBPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000A63 c5c37dd0 VHSUBPS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000A67 c5c37d13 VHSUBPS xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000A6B c4a1437d94db00010000 VHSUBPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000A75 c4a1437d94db00ffffff VHSUBPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000A7F c4e341211390 VINSERTPS xmm2, xmm7, dword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000A85 c4e3412194f30001000090 VINSERTPS xmm2, xmm7, dword ptr [rbx+rsi*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000A90 c4e3412194f300ffffff90 VINSERTPS xmm2, xmm7, dword ptr [rbx+rsi*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000A9B c4e34121d090 VINSERTPS xmm2, xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000AA1 c5fbf013 VLDDQU xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000AA5 c5fbf094f300010000 VLDDQU xmm2, xmmword ptr [rbx+rsi*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + +0000000000000AAE c5fbf094f300ffffff VLDDQU xmm2, xmmword ptr [rbx+rsi*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + +0000000000000AB7 c5f8ae13 VLDMXCSR dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: MXCSR, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000ABB c5f8ae94f300010000 VLDMXCSR dword ptr [rbx+rsi*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: MXCSR, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000AC4 c5f8ae94f300ffffff VLDMXCSR dword ptr [rbx+rsi*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: MXCSR, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000ACD c5f9f7d0 VMASKMOVDQU xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: S, + Segment: 3, Base: 7, + +0000000000000AD1 c4e2412d13 VMASKMOVPD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000AD6 c4e2412d94f300010000 VMASKMOVPD xmm2, xmm7, xmmword ptr [rbx+rsi*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + +0000000000000AE0 c4e2412d94f300ffffff VMASKMOVPD xmm2, xmm7, xmmword ptr [rbx+rsi*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + +0000000000000AEA c4e2412f13 VMASKMOVPD xmmword ptr [rbx], xmm7, xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000AEF c4e2412f94f300010000 VMASKMOVPD xmmword ptr [rbx+rsi*8+0x100], xmm7, xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000AF9 c4e2412f94f300ffffff VMASKMOVPD xmmword ptr [rbx+rsi*8-0x100], xmm7, xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000B03 c4e2412c13 VMASKMOVPS xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000B08 c4e2412c94f300010000 VMASKMOVPS xmm2, xmm7, xmmword ptr [rbx+rsi*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + +0000000000000B12 c4e2412c94f300ffffff VMASKMOVPS xmm2, xmm7, xmmword ptr [rbx+rsi*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + +0000000000000B1C c4e2412e13 VMASKMOVPS xmmword ptr [rbx], xmm7, xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000B21 c4e2412e94f300010000 VMASKMOVPS xmmword ptr [rbx+rsi*8+0x100], xmm7, xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000B2B c4e2412e94f300ffffff VMASKMOVPS xmmword ptr [rbx+rsi*8-0x100], xmm7, xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000B35 c5c15fd0 VMAXPD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000B39 c5c15f13 VMAXPD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000B3D c4a1415f94db00010000 VMAXPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000B47 c4a1415f94db00ffffff VMAXPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000B51 62c195285fc7 VMAXPD ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000B57 62e195285f03 VMAXPD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000B5D 62a195285f44db08 VMAXPD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000B65 62a195285f44dbf8 VMAXPD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000B6D 6201bd405fc7 VMAXPD zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000B73 6261bd405f03 VMAXPD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000B79 6221bd405f44db04 VMAXPD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000B81 6221bd405f44dbfc VMAXPD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000B89 c5c05fd0 VMAXPS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000B8D c5c05f13 VMAXPS xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000B91 c4a1405f94db00010000 VMAXPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000B9B c4a1405f94db00ffffff VMAXPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000BA5 62c114285fc7 VMAXPS ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000BAB 62e114285f03 VMAXPS ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000BB1 62a114285f44db08 VMAXPS ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000BB9 62a114285f44dbf8 VMAXPS ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000BC1 62013c405fc7 VMAXPS zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000BC7 62613c405f03 VMAXPS zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000BCD 62213c405f44db04 VMAXPS zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000BD5 62213c405f44dbfc VMAXPS zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000BDD c5c35fd0 VMAXSD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000BE1 c5c35f13 VMAXSD xmm2, xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000BE5 c4a1435f94db00010000 VMAXSD xmm2, xmm7, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000BEF c4a1435f94db00ffffff VMAXSD xmm2, xmm7, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000BF9 c5c25fd0 VMAXSS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000BFD c5c25f13 VMAXSS xmm2, xmm7, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +0000000000000C01 c4a1425f94db00010000 VMAXSS xmm2, xmm7, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000C0B c4a1425f94db00ffffff VMAXSS xmm2, xmm7, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000C15 c5c15dd0 VMINPD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000C19 c5c15d13 VMINPD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000C1D c4a1415d94db00010000 VMINPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000C27 c4a1415d94db00ffffff VMINPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000C31 62c195285dc7 VMINPD ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000C37 62e195285d03 VMINPD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000C3D 62a195285d44db08 VMINPD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000C45 62a195285d44dbf8 VMINPD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000C4D 6201bd405dc7 VMINPD zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000C53 6261bd405d03 VMINPD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000C59 6221bd405d44db04 VMINPD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000C61 6221bd405d44dbfc VMINPD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000C69 c5c05dd0 VMINPS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000C6D c5c05d13 VMINPS xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000C71 c4a1405d94db00010000 VMINPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000C7B c4a1405d94db00ffffff VMINPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000C85 62c114285dc7 VMINPS ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000C8B 62e114285d03 VMINPS ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000C91 62a114285d44db08 VMINPS ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000C99 62a114285d44dbf8 VMINPS ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000CA1 62013c405dc7 VMINPS zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000CA7 62613c405d03 VMINPS zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000CAD 62213c405d44db04 VMINPS zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000CB5 62213c405d44dbfc VMINPS zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000CBD c5c35dd0 VMINSD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000CC1 c5c35d13 VMINSD xmm2, xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000CC5 c4a1435d94db00010000 VMINSD xmm2, xmm7, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000CCF c4a1435d94db00ffffff VMINSD xmm2, xmm7, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000CD9 c5c25dd0 VMINSS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000CDD c5c25d13 VMINSS xmm2, xmm7, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +0000000000000CE1 c4a1425d94db00010000 VMINSS xmm2, xmm7, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000CEB c4a1425d94db00ffffff VMINSS xmm2, xmm7, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000CF5 c5f928d0 VMOVAPD xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000CF9 c5f92813 VMOVAPD xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000CFD c4a1792894db00010000 VMOVAPD xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000D07 c4a1792894db00ffffff VMOVAPD xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000D11 62c1fd2828c7 VMOVAPD ymm16, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000D17 62e1fd282803 VMOVAPD ymm16, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000D1D 62a1fd282844db08 VMOVAPD ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000D25 62a1fd282844dbf8 VMOVAPD ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000D2D 6201fd4828c7 VMOVAPD zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000D33 6261fd482803 VMOVAPD zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000D39 6221fd482844db04 VMOVAPD zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000D41 6221fd482844dbfc VMOVAPD zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000D49 c5f928c2 VMOVAPD xmm0, xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000D4D 6231fd2828f8 VMOVAPD ymm15, ymm16 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +0000000000000D53 6201fd4828f8 VMOVAPD zmm31, zmm24 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +0000000000000D59 c5f92913 VMOVAPD xmmword ptr [rbx], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000D5D 62e1fd282903 VMOVAPD ymmword ptr [rbx], ymm16 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +0000000000000D63 6261fd482903 VMOVAPD zmmword ptr [rbx], zmm24 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +0000000000000D69 c4a1792994db00010000 VMOVAPD xmmword ptr [rbx+r11*8+0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000D73 62a1fd282944db08 VMOVAPD ymmword ptr [rbx+r11*8+0x100], ymm16 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +0000000000000D7B 6221fd482944db04 VMOVAPD zmmword ptr [rbx+r11*8+0x100], zmm24 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +0000000000000D83 c4a1792994db00ffffff VMOVAPD xmmword ptr [rbx+r11*8-0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000D8D 62a1fd282944dbf8 VMOVAPD ymmword ptr [rbx+r11*8-0x100], ymm16 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +0000000000000D95 6221fd482944dbfc VMOVAPD zmmword ptr [rbx+r11*8-0x100], zmm24 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +0000000000000D9D c5f828d0 VMOVAPS xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000DA1 c5f82813 VMOVAPS xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000DA5 c4a1782894db00010000 VMOVAPS xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000DAF c4a1782894db00ffffff VMOVAPS xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000DB9 62c17c2828c7 VMOVAPS ymm16, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000DBF 62e17c282803 VMOVAPS ymm16, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000DC5 62a17c282844db08 VMOVAPS ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000DCD 62a17c282844dbf8 VMOVAPS ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000DD5 62017c4828c7 VMOVAPS zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000DDB 62617c482803 VMOVAPS zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000DE1 62217c482844db04 VMOVAPS zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000DE9 62217c482844dbfc VMOVAPS zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000DF1 c5f828c2 VMOVAPS xmm0, xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000DF5 62317c2828f8 VMOVAPS ymm15, ymm16 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +0000000000000DFB 62017c4828f8 VMOVAPS zmm31, zmm24 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +0000000000000E01 c5f82913 VMOVAPS xmmword ptr [rbx], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000E05 62e17c282903 VMOVAPS ymmword ptr [rbx], ymm16 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +0000000000000E0B 62617c482903 VMOVAPS zmmword ptr [rbx], zmm24 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +0000000000000E11 c4a1782994db00010000 VMOVAPS xmmword ptr [rbx+r11*8+0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000E1B 62a17c282944db08 VMOVAPS ymmword ptr [rbx+r11*8+0x100], ymm16 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +0000000000000E23 62217c482944db04 VMOVAPS zmmword ptr [rbx+r11*8+0x100], zmm24 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +0000000000000E2B c4a1782994db00ffffff VMOVAPS xmmword ptr [rbx+r11*8-0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000E35 62a17c282944dbf8 VMOVAPS ymmword ptr [rbx+r11*8-0x100], ymm16 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +0000000000000E3D 62217c482944dbfc VMOVAPS zmmword ptr [rbx+r11*8-0x100], zmm24 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +0000000000000E45 c5f96ed1 VMOVD xmm2, ecx + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + +0000000000000E49 c5f96e13 VMOVD xmm2, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +0000000000000E4D c5f96e94f300010000 VMOVD xmm2, dword ptr [rbx+rsi*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + +0000000000000E56 c5f97ed1 VMOVD ecx, xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000E5A c5f97e13 VMOVD dword ptr [rbx], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000E5E c5f97e94f300010000 VMOVD dword ptr [rbx+rsi*8+0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000E67 c5fb12d0 VMOVDDUP xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000E6B c5fb1213 VMOVDDUP xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000E6F c4a17b1294db00010000 VMOVDDUP xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000E79 c4a17b1294db00ffffff VMOVDDUP xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000E83 62c1ff2812c7 VMOVDDUP ymm16, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: MOVDDUP + Exception class: EVEX, exception type: E5NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000E89 62e1ff281203 VMOVDDUP ymm16, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: MOVDDUP + Exception class: EVEX, exception type: E5NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000E8F 62a1ff281244db08 VMOVDDUP ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: MOVDDUP + Exception class: EVEX, exception type: E5NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000E97 62a1ff281244dbf8 VMOVDDUP ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: MOVDDUP + Exception class: EVEX, exception type: E5NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000E9F 6201ff4812c7 VMOVDDUP zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: MOVDDUP + Exception class: EVEX, exception type: E5NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000EA5 6261ff481203 VMOVDDUP zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: MOVDDUP + Exception class: EVEX, exception type: E5NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000EAB 6221ff481244db04 VMOVDDUP zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: MOVDDUP + Exception class: EVEX, exception type: E5NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000EB3 6221ff481244dbfc VMOVDDUP zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: MOVDDUP + Exception class: EVEX, exception type: E5NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000EBB c5fb12d0 VMOVDDUP xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000EBF c5fb1213 VMOVDDUP xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000EC3 c4a17b1294db00010000 VMOVDDUP xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000ECD c4a17b1294db00ffffff VMOVDDUP xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000ED7 62c1ff2812c7 VMOVDDUP ymm16, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: MOVDDUP + Exception class: EVEX, exception type: E5NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000EDD 62e1ff281203 VMOVDDUP ymm16, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: MOVDDUP + Exception class: EVEX, exception type: E5NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000EE3 62a1ff281244db08 VMOVDDUP ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: MOVDDUP + Exception class: EVEX, exception type: E5NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000EEB 62a1ff281244dbf8 VMOVDDUP ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: MOVDDUP + Exception class: EVEX, exception type: E5NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000EF3 6201ff4812c7 VMOVDDUP zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: MOVDDUP + Exception class: EVEX, exception type: E5NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000EF9 6261ff481203 VMOVDDUP zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: MOVDDUP + Exception class: EVEX, exception type: E5NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000EFF 6221ff481244db04 VMOVDDUP zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: MOVDDUP + Exception class: EVEX, exception type: E5NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000F07 6221ff481244dbfc VMOVDDUP zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: MOVDDUP + Exception class: EVEX, exception type: E5NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000F0F c5f96fd0 VMOVDQA xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000F13 c5f96f13 VMOVDQA xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000F17 c4a1796f94db00010000 VMOVDQA xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000F21 c4a1796f94db00ffffff VMOVDQA xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000F2B c5f96fc2 VMOVDQA xmm0, xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000F2F c5f97f13 VMOVDQA xmmword ptr [rbx], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000F33 c4a1797f94db00010000 VMOVDQA xmmword ptr [rbx+r11*8+0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000F3D c4a1797f94db00ffffff VMOVDQA xmmword ptr [rbx+r11*8-0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000F47 c5fa6fd0 VMOVDQU xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000F4B c5fa6f13 VMOVDQU xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000F4F c4a17a6f94db00010000 VMOVDQU xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000F59 c4a17a6f94db00ffffff VMOVDQU xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000F63 c5fa6fc2 VMOVDQU xmm0, xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000F67 c5fa7f13 VMOVDQU xmmword ptr [rbx], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000F6B c4a17a7f94db00010000 VMOVDQU xmmword ptr [rbx+r11*8+0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000F75 c4a17a7f94db00ffffff VMOVDQU xmmword ptr [rbx+r11*8-0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000F7F c5c012d0 VMOVHLPS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000F83 c5c11613 VMOVHPD xmm2, xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000F87 c5c11694f300010000 VMOVHPD xmm2, xmm7, qword ptr [rbx+rsi*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + +0000000000000F90 c5c11694f300ffffff VMOVHPD xmm2, xmm7, qword ptr [rbx+rsi*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + +0000000000000F99 c5f91713 VMOVHPD qword ptr [rbx], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000F9D c5f91794f300010000 VMOVHPD qword ptr [rbx+rsi*8+0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000FA6 c5f91794f300ffffff VMOVHPD qword ptr [rbx+rsi*8-0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000FAF c5c01613 VMOVHPS xmm2, xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000FB3 c5c01694f300010000 VMOVHPS xmm2, xmm7, qword ptr [rbx+rsi*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + +0000000000000FBC c5c01694f300ffffff VMOVHPS xmm2, xmm7, qword ptr [rbx+rsi*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + +0000000000000FC5 c5f81713 VMOVHPS qword ptr [rbx], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000FC9 c5f81794f300010000 VMOVHPS qword ptr [rbx+rsi*8+0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000FD2 c5f81794f300ffffff VMOVHPS qword ptr [rbx+rsi*8-0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000FDB c5c016d0 VMOVLHPS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000FDF c5c11213 VMOVLPD xmm2, xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000FE3 c5c11294f300010000 VMOVLPD xmm2, xmm7, qword ptr [rbx+rsi*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + +0000000000000FEC c5c11294f300ffffff VMOVLPD xmm2, xmm7, qword ptr [rbx+rsi*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + +0000000000000FF5 c5f91313 VMOVLPD qword ptr [rbx], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000FF9 c5f91394f300010000 VMOVLPD qword ptr [rbx+rsi*8+0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000001002 c5f91394f300ffffff VMOVLPD qword ptr [rbx+rsi*8-0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +000000000000100B c5c01213 VMOVLPS xmm2, xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000100F c5c01294f300010000 VMOVLPS xmm2, xmm7, qword ptr [rbx+rsi*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + +0000000000001018 c5c01294f300ffffff VMOVLPS xmm2, xmm7, qword ptr [rbx+rsi*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + +0000000000001021 c5f81313 VMOVLPS qword ptr [rbx], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000001025 c5f81394f300010000 VMOVLPS qword ptr [rbx+rsi*8+0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +000000000000102E c5f81394f300ffffff VMOVLPS qword ptr [rbx+rsi*8-0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000001037 c5f950c8 VMOVMSKPD ecx, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000103B c4c17d50cf VMOVMSKPD ecx, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001040 c5f950c8 VMOVMSKPD ecx, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001044 c4c17d50cf VMOVMSKPD ecx, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001049 c5f850c8 VMOVMSKPS ecx, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000104D c4c17c50cf VMOVMSKPS ecx, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001052 c5f850c8 VMOVMSKPS ecx, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001056 c4c17c50cf VMOVMSKPS ecx, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000105B c5f9e713 VMOVNTDQ xmmword ptr [rbx], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +000000000000105F 62e17d28e703 VMOVNTDQ ymmword ptr [rbx], ymm16 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +0000000000001065 62617d48e703 VMOVNTDQ zmmword ptr [rbx], zmm24 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +000000000000106B c5f9e794f300010000 VMOVNTDQ xmmword ptr [rbx+rsi*8+0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000001074 62e17d28e744f308 VMOVNTDQ ymmword ptr [rbx+rsi*8+0x100], ymm16 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000008, + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +000000000000107C 62617d48e744f304 VMOVNTDQ zmmword ptr [rbx+rsi*8+0x100], zmm24 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000004, + Operand: 1, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +0000000000001084 c5f9e794f300ffffff VMOVNTDQ xmmword ptr [rbx+rsi*8-0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +000000000000108D 62e17d28e744f3f8 VMOVNTDQ ymmword ptr [rbx+rsi*8-0x100], ymm16 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffff8, + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +0000000000001095 62617d48e744f3fc VMOVNTDQ zmmword ptr [rbx+rsi*8-0x100], zmm24 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffffc, + Operand: 1, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +000000000000109D c4e2792a13 VMOVNTDQA xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000010A2 c4e2792a94f300010000 VMOVNTDQA xmm2, xmmword ptr [rbx+rsi*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + +00000000000010AC c4e2792a94f300ffffff VMOVNTDQA xmm2, xmmword ptr [rbx+rsi*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + +00000000000010B6 62e27d282a03 VMOVNTDQA ymm16, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000010BC 62e27d282a44f308 VMOVNTDQA ymm16, ymmword ptr [rbx+rsi*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000008, + +00000000000010C4 62e27d282a44f3f8 VMOVNTDQA ymm16, ymmword ptr [rbx+rsi*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffff8, + +00000000000010CC 62627d482a03 VMOVNTDQA zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000010D2 62627d482a44f304 VMOVNTDQA zmm24, zmmword ptr [rbx+rsi*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000004, + +00000000000010DA 62627d482a44f3fc VMOVNTDQA zmm24, zmmword ptr [rbx+rsi*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffffc, + +00000000000010E2 c5f92b13 VMOVNTPD xmmword ptr [rbx], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +00000000000010E6 62e1fd282b03 VMOVNTPD ymmword ptr [rbx], ymm16 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +00000000000010EC 6261fd482b03 VMOVNTPD zmmword ptr [rbx], zmm24 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +00000000000010F2 c5f92b94f300010000 VMOVNTPD xmmword ptr [rbx+rsi*8+0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +00000000000010FB 62e1fd282b44f308 VMOVNTPD ymmword ptr [rbx+rsi*8+0x100], ymm16 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000008, + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +0000000000001103 6261fd482b44f304 VMOVNTPD zmmword ptr [rbx+rsi*8+0x100], zmm24 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000004, + Operand: 1, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +000000000000110B c5f92b94f300ffffff VMOVNTPD xmmword ptr [rbx+rsi*8-0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000001114 62e1fd282b44f3f8 VMOVNTPD ymmword ptr [rbx+rsi*8-0x100], ymm16 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffff8, + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +000000000000111C 6261fd482b44f3fc VMOVNTPD zmmword ptr [rbx+rsi*8-0x100], zmm24 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffffc, + Operand: 1, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +0000000000001124 c5f82b13 VMOVNTPS xmmword ptr [rbx], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000001128 62e17c282b03 VMOVNTPS ymmword ptr [rbx], ymm16 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +000000000000112E 62617c482b03 VMOVNTPS zmmword ptr [rbx], zmm24 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +0000000000001134 c5f82b94f300010000 VMOVNTPS xmmword ptr [rbx+rsi*8+0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +000000000000113D 62e17c282b44f308 VMOVNTPS ymmword ptr [rbx+rsi*8+0x100], ymm16 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000008, + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +0000000000001145 62617c482b44f304 VMOVNTPS zmmword ptr [rbx+rsi*8+0x100], zmm24 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000004, + Operand: 1, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +000000000000114D c5f82b94f300ffffff VMOVNTPS xmmword ptr [rbx+rsi*8-0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000001156 62e17c282b44f3f8 VMOVNTPS ymmword ptr [rbx+rsi*8-0x100], ymm16 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffff8, + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +000000000000115E 62617c482b44f3fc VMOVNTPS zmmword ptr [rbx+rsi*8-0x100], zmm24 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E1NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffffc, + Operand: 1, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +0000000000001166 c4e1f96ed1 VMOVQ xmm2, rcx + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + +000000000000116B c5fa7e13 VMOVQ xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000116F c5fa7e94f300010000 VMOVQ xmm2, qword ptr [rbx+rsi*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + +0000000000001178 c4e1f97ed1 VMOVQ rcx, xmm2 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +000000000000117D c5f9d613 VMOVQ qword ptr [rbx], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000001181 c5f9d694f300010000 VMOVQ qword ptr [rbx+rsi*8+0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +000000000000118A c5fa7ed0 VMOVQ xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000118E c5fa7e13 VMOVQ xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000001192 c4a17a7e94db00010000 VMOVQ xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000119C c4a17a7e94db00ffffff VMOVQ xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000011A6 c5fa7ec2 VMOVQ xmm0, xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +00000000000011AA c5f9d613 VMOVQ qword ptr [rbx], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +00000000000011AE c4a179d694db00010000 VMOVQ qword ptr [rbx+r11*8+0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +00000000000011B8 c4a179d694db00ffffff VMOVQ qword ptr [rbx+r11*8-0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +00000000000011C2 c5c310d0 VMOVSD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000011C6 c5fb1013 VMOVSD xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000011CA c5fb1094f300010000 VMOVSD xmm2, qword ptr [rbx+rsi*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + +00000000000011D3 c5fb1094f300ffffff VMOVSD xmm2, qword ptr [rbx+rsi*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + +00000000000011DC c5c310c2 VMOVSD xmm0, xmm7, xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +00000000000011E0 c5fb1113 VMOVSD qword ptr [rbx], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +00000000000011E4 c5fb1194f300010000 VMOVSD qword ptr [rbx+rsi*8+0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +00000000000011ED c5fb1194f300ffffff VMOVSD qword ptr [rbx+rsi*8-0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +00000000000011F6 c5fa16d0 VMOVSHDUP xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000011FA c5fa1613 VMOVSHDUP xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000011FE c4a17a1694db00010000 VMOVSHDUP xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000001208 c4a17a1694db00ffffff VMOVSHDUP xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001212 62c17e2816c7 VMOVSHDUP ymm16, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001218 62e17e281603 VMOVSHDUP ymm16, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000121E 62a17e281644db08 VMOVSHDUP ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001226 62a17e281644dbf8 VMOVSHDUP ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000122E 62017e4816c7 VMOVSHDUP zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001234 62617e481603 VMOVSHDUP zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000123A 62217e481644db04 VMOVSHDUP zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001242 62217e481644dbfc VMOVSHDUP zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000124A c5fa12d0 VMOVSLDUP xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000124E c5fa1213 VMOVSLDUP xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001252 c4a17a1294db00010000 VMOVSLDUP xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000125C c4a17a1294db00ffffff VMOVSLDUP xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001266 62c17e2812c7 VMOVSLDUP ymm16, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000126C 62e17e281203 VMOVSLDUP ymm16, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000001272 62a17e281244db08 VMOVSLDUP ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000127A 62a17e281244dbf8 VMOVSLDUP ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001282 62017e4812c7 VMOVSLDUP zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001288 62617e481203 VMOVSLDUP zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000128E 62217e481244db04 VMOVSLDUP zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001296 62217e481244dbfc VMOVSLDUP zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000129E c5c210d0 VMOVSS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000012A2 c5fa1013 VMOVSS xmm2, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +00000000000012A6 c5fa1094f300010000 VMOVSS xmm2, dword ptr [rbx+rsi*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + +00000000000012AF c5fa1094f300ffffff VMOVSS xmm2, dword ptr [rbx+rsi*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + +00000000000012B8 c5c210c2 VMOVSS xmm0, xmm7, xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +00000000000012BC c5fa1113 VMOVSS dword ptr [rbx], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +00000000000012C0 c5fa1194f300010000 VMOVSS dword ptr [rbx+rsi*8+0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +00000000000012C9 c5fa1194f300ffffff VMOVSS dword ptr [rbx+rsi*8-0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +00000000000012D2 c5f910d0 VMOVUPD xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000012D6 c5f91013 VMOVUPD xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000012DA c4a1791094db00010000 VMOVUPD xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000012E4 c4a1791094db00ffffff VMOVUPD xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000012EE 62c1fd2810c7 VMOVUPD ymm16, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000012F4 62e1fd281003 VMOVUPD ymm16, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000012FA 62a1fd281044db08 VMOVUPD ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001302 62a1fd281044dbf8 VMOVUPD ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000130A 6201fd4810c7 VMOVUPD zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001310 6261fd481003 VMOVUPD zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001316 6221fd481044db04 VMOVUPD zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000131E 6221fd481044dbfc VMOVUPD zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001326 c5f910c2 VMOVUPD xmm0, xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +000000000000132A 6231fd2810f8 VMOVUPD ymm15, ymm16 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +0000000000001330 6201fd4810f8 VMOVUPD zmm31, zmm24 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +0000000000001336 c5f91113 VMOVUPD xmmword ptr [rbx], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +000000000000133A 62e1fd281103 VMOVUPD ymmword ptr [rbx], ymm16 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +0000000000001340 6261fd481103 VMOVUPD zmmword ptr [rbx], zmm24 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +0000000000001346 c4a1791194db00010000 VMOVUPD xmmword ptr [rbx+r11*8+0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000001350 62a1fd281144db08 VMOVUPD ymmword ptr [rbx+r11*8+0x100], ymm16 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +0000000000001358 6221fd481144db04 VMOVUPD zmmword ptr [rbx+r11*8+0x100], zmm24 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +0000000000001360 c4a1791194db00ffffff VMOVUPD xmmword ptr [rbx+r11*8-0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +000000000000136A 62a1fd281144dbf8 VMOVUPD ymmword ptr [rbx+r11*8-0x100], ymm16 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +0000000000001372 6221fd481144dbfc VMOVUPD zmmword ptr [rbx+r11*8-0x100], zmm24 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +000000000000137A c5f810d0 VMOVUPS xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000137E c5f81013 VMOVUPS xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001382 c4a1781094db00010000 VMOVUPS xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000138C c4a1781094db00ffffff VMOVUPS xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001396 62c17c2810c7 VMOVUPS ymm16, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000139C 62e17c281003 VMOVUPS ymm16, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000013A2 62a17c281044db08 VMOVUPS ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000013AA 62a17c281044dbf8 VMOVUPS ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000013B2 62017c4810c7 VMOVUPS zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000013B8 62617c481003 VMOVUPS zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000013BE 62217c481044db04 VMOVUPS zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000013C6 62217c481044dbfc VMOVUPS zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000013CE c5f810c2 VMOVUPS xmm0, xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +00000000000013D2 62317c2810f8 VMOVUPS ymm15, ymm16 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +00000000000013D8 62017c4810f8 VMOVUPS zmm31, zmm24 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +00000000000013DE c5f81113 VMOVUPS xmmword ptr [rbx], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +00000000000013E2 62e17c281103 VMOVUPS ymmword ptr [rbx], ymm16 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +00000000000013E8 62617c481103 VMOVUPS zmmword ptr [rbx], zmm24 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +00000000000013EE c4a1781194db00010000 VMOVUPS xmmword ptr [rbx+r11*8+0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +00000000000013F8 62a17c281144db08 VMOVUPS ymmword ptr [rbx+r11*8+0x100], ymm16 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +0000000000001400 62217c481144db04 VMOVUPS zmmword ptr [rbx+r11*8+0x100], zmm24 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +0000000000001408 c4a1781194db00ffffff VMOVUPS xmmword ptr [rbx+r11*8-0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000001412 62a17c281144dbf8 VMOVUPS ymmword ptr [rbx+r11*8-0x100], ymm16 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +000000000000141A 62217c481144dbfc VMOVUPS zmmword ptr [rbx+r11*8-0x100], zmm24 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +0000000000001422 c4e34142d090 VMPSADBW xmm2, xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001428 c4e341421390 VMPSADBW xmm2, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000142E c4a3414294db0001000090 VMPSADBW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001439 c4a3414294db00ffffff90 VMPSADBW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001444 c5c159d0 VMULPD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001448 c5c15913 VMULPD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000144C c4a1415994db00010000 VMULPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000001456 c4a1415994db00ffffff VMULPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001460 62c1952859c7 VMULPD ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001466 62e195285903 VMULPD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000146C 62a195285944db08 VMULPD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001474 62a195285944dbf8 VMULPD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000147C 6201bd4059c7 VMULPD zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001482 6261bd405903 VMULPD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001488 6221bd405944db04 VMULPD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001490 6221bd405944dbfc VMULPD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001498 c5c059d0 VMULPS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000149C c5c05913 VMULPS xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000014A0 c4a1405994db00010000 VMULPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000014AA c4a1405994db00ffffff VMULPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000014B4 62c1142859c7 VMULPS ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000014BA 62e114285903 VMULPS ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000014C0 62a114285944db08 VMULPS ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000014C8 62a114285944dbf8 VMULPS ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000014D0 62013c4059c7 VMULPS zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000014D6 62613c405903 VMULPS zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000014DC 62213c405944db04 VMULPS zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000014E4 62213c405944dbfc VMULPS zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000014EC c5c359d0 VMULSD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000014F0 c5c35913 VMULSD xmm2, xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000014F4 c4a1435994db00010000 VMULSD xmm2, xmm7, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000014FE c4a1435994db00ffffff VMULSD xmm2, xmm7, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001508 c5c259d0 VMULSS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000150C c5c25913 VMULSS xmm2, xmm7, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +0000000000001510 c4a1425994db00010000 VMULSS xmm2, xmm7, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000151A c4a1425994db00ffffff VMULSS xmm2, xmm7, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001524 c5c156d0 VORPD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001528 c5c15613 VORPD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000152C c4a1415694db00010000 VORPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000001536 c4a1415694db00ffffff VORPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001540 62c1952856c7 VORPD ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001546 62e195285603 VORPD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000154C 62a195285644db08 VORPD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001554 62a195285644dbf8 VORPD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000155C 6201bd4056c7 VORPD zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001562 6261bd405603 VORPD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001568 6221bd405644db04 VORPD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001570 6221bd405644dbfc VORPD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001578 c5c056d0 VORPS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000157C c5c05613 VORPS xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001580 c4a1405694db00010000 VORPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000158A c4a1405694db00ffffff VORPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001594 62c1142856c7 VORPS ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000159A 62e114285603 VORPS ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000015A0 62a114285644db08 VORPS ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000015A8 62a114285644dbf8 VORPS ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000015B0 62013c4056c7 VORPS zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000015B6 62613c405603 VORPS zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000015BC 62213c405644db04 VORPS zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000015C4 62213c405644dbfc VORPS zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000015CC c4e2791cd0 VPABSB xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000015D1 c4e2791c13 VPABSB xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000015D6 c4a2791c94db00010000 VPABSB xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000015E0 c4a2791c94db00ffffff VPABSB xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000015EA 62c27d281cc7 VPABSB ymm16, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000015F0 62e27d281c03 VPABSB ymm16, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000015F6 62a27d281c44db08 VPABSB ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000015FE 62a27d281c44dbf8 VPABSB ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001606 62027d481cc7 VPABSB zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000160C 62627d481c03 VPABSB zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001612 62227d481c44db04 VPABSB zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000161A 62227d481c44dbfc VPABSB zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001622 c4e2791ed0 VPABSD xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001627 c4e2791e13 VPABSD xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000162C c4a2791e94db00010000 VPABSD xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000001636 c4a2791e94db00ffffff VPABSD xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001640 62c27d281ec7 VPABSD ymm16, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001646 62e27d281e03 VPABSD ymm16, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000164C 62a27d281e44db08 VPABSD ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001654 62a27d281e44dbf8 VPABSD ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000165C 62027d481ec7 VPABSD zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001662 62627d481e03 VPABSD zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001668 62227d481e44db04 VPABSD zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001670 62227d481e44dbfc VPABSD zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001678 c4e2791dd0 VPABSW xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000167D c4e2791d13 VPABSW xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001682 c4a2791d94db00010000 VPABSW xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000168C c4a2791d94db00ffffff VPABSW xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001696 62c27d281dc7 VPABSW ymm16, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000169C 62e27d281d03 VPABSW ymm16, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000016A2 62a27d281d44db08 VPABSW ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000016AA 62a27d281d44dbf8 VPABSW ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000016B2 62027d481dc7 VPABSW zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000016B8 62627d481d03 VPABSW zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000016BE 62227d481d44db04 VPABSW zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000016C6 62227d481d44dbfc VPABSW zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000016CE c5c16bd0 VPACKSSDW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000016D2 c5c16b13 VPACKSSDW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000016D6 c4a1416b94db00010000 VPACKSSDW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000016E0 c4a1416b94db00ffffff VPACKSSDW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000016EA 62c115286bc7 VPACKSSDW ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000016F0 62e115286b03 VPACKSSDW ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000016F6 62a115286b44db08 VPACKSSDW ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000016FE 62a115286b44dbf8 VPACKSSDW ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001706 62013d406bc7 VPACKSSDW zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000170C 62613d406b03 VPACKSSDW zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001712 62213d406b44db04 VPACKSSDW zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000171A 62213d406b44dbfc VPACKSSDW zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001722 c5c163d0 VPACKSSWB xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001726 c5c16313 VPACKSSWB xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000172A c4a1416394db00010000 VPACKSSWB xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000001734 c4a1416394db00ffffff VPACKSSWB xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +000000000000173E 62c1152863c7 VPACKSSWB ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001744 62e115286303 VPACKSSWB ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000174A 62a115286344db08 VPACKSSWB ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001752 62a115286344dbf8 VPACKSSWB ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000175A 62013d4063c7 VPACKSSWB zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001760 62613d406303 VPACKSSWB zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001766 62213d406344db04 VPACKSSWB zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000176E 62213d406344dbfc VPACKSSWB zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001776 c4e2412bd0 VPACKUSDW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000177B c4e2412b13 VPACKUSDW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001780 c4a2412b94db00010000 VPACKUSDW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000178A c4a2412b94db00ffffff VPACKUSDW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001794 62c215282bc7 VPACKUSDW ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000179A 62e215282b03 VPACKUSDW ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000017A0 62a215282b44db08 VPACKUSDW ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000017A8 62a215282b44dbf8 VPACKUSDW ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000017B0 62023d402bc7 VPACKUSDW zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000017B6 62623d402b03 VPACKUSDW zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000017BC 62223d402b44db04 VPACKUSDW zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000017C4 62223d402b44dbfc VPACKUSDW zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000017CC c5c167d0 VPACKUSWB xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000017D0 c5c16713 VPACKUSWB xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000017D4 c4a1416794db00010000 VPACKUSWB xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000017DE c4a1416794db00ffffff VPACKUSWB xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000017E8 62c1152867c7 VPACKUSWB ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000017EE 62e115286703 VPACKUSWB ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000017F4 62a115286744db08 VPACKUSWB ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000017FC 62a115286744dbf8 VPACKUSWB ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001804 62013d4067c7 VPACKUSWB zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000180A 62613d406703 VPACKUSWB zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001810 62213d406744db04 VPACKUSWB zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001818 62213d406744dbfc VPACKUSWB zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001820 c5c1fcd0 VPADDB xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001824 c5c1fc13 VPADDB xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001828 c4a141fc94db00010000 VPADDB xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000001832 c4a141fc94db00ffffff VPADDB xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +000000000000183C 62c11528fcc7 VPADDB ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001842 62e11528fc03 VPADDB ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000001848 62a11528fc44db08 VPADDB ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001850 62a11528fc44dbf8 VPADDB ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001858 62013d40fcc7 VPADDB zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000185E 62613d40fc03 VPADDB zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001864 62213d40fc44db04 VPADDB zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000186C 62213d40fc44dbfc VPADDB zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001874 c5c1fed0 VPADDD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001878 c5c1fe13 VPADDD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000187C c4a141fe94db00010000 VPADDD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000001886 c4a141fe94db00ffffff VPADDD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001890 62c11528fec7 VPADDD ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001896 62e11528fe03 VPADDD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000189C 62a11528fe44db08 VPADDD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000018A4 62a11528fe44dbf8 VPADDD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000018AC 62013d40fec7 VPADDD zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000018B2 62613d40fe03 VPADDD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000018B8 62213d40fe44db04 VPADDD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000018C0 62213d40fe44dbfc VPADDD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000018C8 c5c1d4d0 VPADDQ xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000018CC c5c1d413 VPADDQ xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000018D0 c4a141d494db00010000 VPADDQ xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000018DA c4a141d494db00ffffff VPADDQ xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000018E4 62c19528d4c7 VPADDQ ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000018EA 62e19528d403 VPADDQ ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000018F0 62a19528d444db08 VPADDQ ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000018F8 62a19528d444dbf8 VPADDQ ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001900 6201bd40d4c7 VPADDQ zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001906 6261bd40d403 VPADDQ zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000190C 6221bd40d444db04 VPADDQ zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001914 6221bd40d444dbfc VPADDQ zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000191C c5c1ecd0 VPADDSB xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001920 c5c1ec13 VPADDSB xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001924 c4a141ec94db00010000 VPADDSB xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000192E c4a141ec94db00ffffff VPADDSB xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001938 62c11528ecc7 VPADDSB ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000193E 62e11528ec03 VPADDSB ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000001944 62a11528ec44db08 VPADDSB ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000194C 62a11528ec44dbf8 VPADDSB ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001954 62013d40ecc7 VPADDSB zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000195A 62613d40ec03 VPADDSB zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001960 62213d40ec44db04 VPADDSB zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001968 62213d40ec44dbfc VPADDSB zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001970 c5c1edd0 VPADDSW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001974 c5c1ed13 VPADDSW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001978 c4a141ed94db00010000 VPADDSW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000001982 c4a141ed94db00ffffff VPADDSW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +000000000000198C 62c11528edc7 VPADDSW ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001992 62e11528ed03 VPADDSW ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000001998 62a11528ed44db08 VPADDSW ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000019A0 62a11528ed44dbf8 VPADDSW ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000019A8 62013d40edc7 VPADDSW zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000019AE 62613d40ed03 VPADDSW zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000019B4 62213d40ed44db04 VPADDSW zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000019BC 62213d40ed44dbfc VPADDSW zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000019C4 c5c1dcd0 VPADDUSB xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000019C8 c5c1dc13 VPADDUSB xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000019CC c4a141dc94db00010000 VPADDUSB xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000019D6 c4a141dc94db00ffffff VPADDUSB xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000019E0 62c11528dcc7 VPADDUSB ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000019E6 62e11528dc03 VPADDUSB ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000019EC 62a11528dc44db08 VPADDUSB ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000019F4 62a11528dc44dbf8 VPADDUSB ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000019FC 62013d40dcc7 VPADDUSB zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001A02 62613d40dc03 VPADDUSB zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001A08 62213d40dc44db04 VPADDUSB zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001A10 62213d40dc44dbfc VPADDUSB zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001A18 c5c1ddd0 VPADDUSW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001A1C c5c1dd13 VPADDUSW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001A20 c4a141dd94db00010000 VPADDUSW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000001A2A c4a141dd94db00ffffff VPADDUSW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001A34 62c11528ddc7 VPADDUSW ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001A3A 62e11528dd03 VPADDUSW ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000001A40 62a11528dd44db08 VPADDUSW ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001A48 62a11528dd44dbf8 VPADDUSW ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001A50 62013d40ddc7 VPADDUSW zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001A56 62613d40dd03 VPADDUSW zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001A5C 62213d40dd44db04 VPADDUSW zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001A64 62213d40dd44dbfc VPADDUSW zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001A6C c5c1fdd0 VPADDW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001A70 c5c1fd13 VPADDW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001A74 c4a141fd94db00010000 VPADDW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000001A7E c4a141fd94db00ffffff VPADDW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001A88 62c11528fdc7 VPADDW ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001A8E 62e11528fd03 VPADDW ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000001A94 62a11528fd44db08 VPADDW ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001A9C 62a11528fd44dbf8 VPADDW ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001AA4 62013d40fdc7 VPADDW zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001AAA 62613d40fd03 VPADDW zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001AB0 62213d40fd44db04 VPADDW zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001AB8 62213d40fd44dbfc VPADDW zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001AC0 c4e3410fd090 VPALIGNR xmm2, xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001AC6 c4e3410f1390 VPALIGNR xmm2, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001ACC c4a3410f94db0001000090 VPALIGNR xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001AD7 c4a3410f94db00ffffff90 VPALIGNR xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001AE2 62c315280fc790 VPALIGNR ymm16, ymm13, ymm15, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001AE9 62e315280f0390 VPALIGNR ymm16, ymm13, ymmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001AF0 62a315280f44db0890 VPALIGNR ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001AF9 62a315280f44dbf890 VPALIGNR ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001B02 62033d400fc790 VPALIGNR zmm24, zmm24, zmm31, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001B09 62633d400f0390 VPALIGNR zmm24, zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001B10 62233d400f44db0490 VPALIGNR zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001B19 62233d400f44dbfc90 VPALIGNR zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001B22 c5c1dbd0 VPAND xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001B26 c5c1db13 VPAND xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001B2A c4a141db94db00010000 VPAND xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000001B34 c4a141db94db00ffffff VPAND xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001B3E c5c1dfd0 VPANDN xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001B42 c5c1df13 VPANDN xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001B46 c4a141df94db00010000 VPANDN xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000001B50 c4a141df94db00ffffff VPANDN xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001B5A c5c1e0d0 VPAVGB xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001B5E c5c1e013 VPAVGB xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001B62 c4a141e094db00010000 VPAVGB xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000001B6C c4a141e094db00ffffff VPAVGB xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001B76 62c11528e0c7 VPAVGB ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001B7C 62e11528e003 VPAVGB ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000001B82 62a11528e044db08 VPAVGB ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001B8A 62a11528e044dbf8 VPAVGB ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001B92 62013d40e0c7 VPAVGB zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001B98 62613d40e003 VPAVGB zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001B9E 62213d40e044db04 VPAVGB zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001BA6 62213d40e044dbfc VPAVGB zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001BAE c5c1e3d0 VPAVGW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001BB2 c5c1e313 VPAVGW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001BB6 c4a141e394db00010000 VPAVGW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000001BC0 c4a141e394db00ffffff VPAVGW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001BCA 62c11528e3c7 VPAVGW ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001BD0 62e11528e303 VPAVGW ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000001BD6 62a11528e344db08 VPAVGW ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001BDE 62a11528e344dbf8 VPAVGW ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001BE6 62013d40e3c7 VPAVGW zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001BEC 62613d40e303 VPAVGW zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001BF2 62213d40e344db04 VPAVGW zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001BFA 62213d40e344dbfc VPAVGW zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001C02 c4e3414cd030 VPBLENDVB xmm2, xmm7, xmm0, xmm3 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 3, RegCount: 1 + +0000000000001C08 c4e3414c1330 VPBLENDVB xmm2, xmm7, xmmword ptr [rbx], xmm3 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 3, RegCount: 1 + +0000000000001C0E c4a3414c94db0001000030 VPBLENDVB xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], xmm3 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 3, RegCount: 1 + +0000000000001C19 c4a3414c94db00ffffff30 VPBLENDVB xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], xmm3 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 3, RegCount: 1 + +0000000000001C24 c4e3410ed090 VPBLENDW xmm2, xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001C2A c4e3410e1390 VPBLENDW xmm2, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001C30 c4a3410e94db0001000090 VPBLENDW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001C3B c4a3410e94db00ffffff90 VPBLENDW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001C46 c5c174d0 VPCMPEQB xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001C4A c5c17413 VPCMPEQB xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001C4E c4a1417494db00010000 VPCMPEQB xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000001C58 c4a1417494db00ffffff VPCMPEQB xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001C62 c5c176d0 VPCMPEQD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001C66 c5c17613 VPCMPEQD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001C6A c4a1417694db00010000 VPCMPEQD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000001C74 c4a1417694db00ffffff VPCMPEQD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001C7E c4e24129d0 VPCMPEQQ xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001C83 c4e2412913 VPCMPEQQ xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001C88 c4a2412994db00010000 VPCMPEQQ xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000001C92 c4a2412994db00ffffff VPCMPEQQ xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001C9C c5c175d0 VPCMPEQW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001CA0 c5c17513 VPCMPEQW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001CA4 c4a1417594db00010000 VPCMPEQW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000001CAE c4a1417594db00ffffff VPCMPEQW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001CB8 c4e37961d090 VPCMPESTRI xmm2, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: STTNI, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 5, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 6, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001CBE c4e379611390 VPCMPESTRI xmm2, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: STTNI, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 5, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 6, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001CC4 c4a3796194db0001000090 VPCMPESTRI xmm2, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: STTNI, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 5, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 6, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001CCF c4a3796194db00ffffff90 VPCMPESTRI xmm2, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: STTNI, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 5, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 6, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001CDA c4e37960d090 VPCMPESTRM xmm2, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: STTNI, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 5, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 6, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001CE0 c4e379601390 VPCMPESTRM xmm2, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: STTNI, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 5, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 6, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001CE6 c4a3796094db0001000090 VPCMPESTRM xmm2, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: STTNI, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 5, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 6, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001CF1 c4a3796094db00ffffff90 VPCMPESTRM xmm2, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: STTNI, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 5, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 6, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001CFC c5c164d0 VPCMPGTB xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001D00 c5c16413 VPCMPGTB xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001D04 c4a1416494db00010000 VPCMPGTB xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000001D0E c4a1416494db00ffffff VPCMPGTB xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001D18 c5c166d0 VPCMPGTD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001D1C c5c16613 VPCMPGTD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001D20 c4a1416694db00010000 VPCMPGTD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000001D2A c4a1416694db00ffffff VPCMPGTD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001D34 c4e24137d0 VPCMPGTQ xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001D39 c4e2413713 VPCMPGTQ xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001D3E c4a2413794db00010000 VPCMPGTQ xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000001D48 c4a2413794db00ffffff VPCMPGTQ xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001D52 c5c165d0 VPCMPGTW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001D56 c5c16513 VPCMPGTW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001D5A c4a1416594db00010000 VPCMPGTW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000001D64 c4a1416594db00ffffff VPCMPGTW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001D6E c4e37963d090 VPCMPISTRI xmm2, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: STTNI, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001D74 c4e379631390 VPCMPISTRI xmm2, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: STTNI, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001D7A c4a3796394db0001000090 VPCMPISTRI xmm2, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: STTNI, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001D85 c4a3796394db00ffffff90 VPCMPISTRI xmm2, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: STTNI, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001D90 c4e37962d090 VPCMPISTRM xmm2, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: STTNI, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001D96 c4e379621390 VPCMPISTRM xmm2, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: STTNI, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001D9C c4a3796294db0001000090 VPCMPISTRM xmm2, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: STTNI, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001DA7 c4a3796294db00ffffff90 VPCMPISTRM xmm2, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: STTNI, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001DB2 c4e2410dd0 VPERMILPD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001DB7 c4e2410d13 VPERMILPD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001DBC c4a2410d94db00010000 VPERMILPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000001DC6 c4a2410d94db00ffffff VPERMILPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001DD0 62c295280dc7 VPERMILPD ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001DD6 62e295280d03 VPERMILPD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000001DDC 62a295280d44db08 VPERMILPD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001DE4 62a295280d44dbf8 VPERMILPD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001DEC 6202bd400dc7 VPERMILPD zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001DF2 6262bd400d03 VPERMILPD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001DF8 6222bd400d44db04 VPERMILPD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001E00 6222bd400d44dbfc VPERMILPD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001E08 c4e37905d090 VPERMILPD xmm2, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E0E c4e379051390 VPERMILPD xmm2, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E14 c4a3790594db0001000090 VPERMILPD xmm2, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E1F c4a3790594db00ffffff90 VPERMILPD xmm2, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E2A 62c3fd2805c790 VPERMILPD ymm16, ymm15, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E31 62e3fd28050390 VPERMILPD ymm16, ymmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E38 62a3fd280544db0890 VPERMILPD ymm16, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E41 62a3fd280544dbf890 VPERMILPD ymm16, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E4A 6203fd4805c790 VPERMILPD zmm24, zmm31, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E51 6263fd48050390 VPERMILPD zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E58 6223fd480544db0490 VPERMILPD zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E61 6223fd480544dbfc90 VPERMILPD zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E6A c4e2410cd0 VPERMILPS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001E6F c4e2410c13 VPERMILPS xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001E74 c4a2410c94db00010000 VPERMILPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000001E7E c4a2410c94db00ffffff VPERMILPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001E88 62c215280cc7 VPERMILPS ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001E8E 62e215280c03 VPERMILPS ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000001E94 62a215280c44db08 VPERMILPS ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001E9C 62a215280c44dbf8 VPERMILPS ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001EA4 62023d400cc7 VPERMILPS zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001EAA 62623d400c03 VPERMILPS zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001EB0 62223d400c44db04 VPERMILPS zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001EB8 62223d400c44dbfc VPERMILPS zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001EC0 c4e37904d090 VPERMILPS xmm2, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001EC6 c4e379041390 VPERMILPS xmm2, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001ECC c4a3790494db0001000090 VPERMILPS xmm2, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001ED7 c4a3790494db00ffffff90 VPERMILPS xmm2, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001EE2 62c37d2804c790 VPERMILPS ymm16, ymm15, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001EE9 62e37d28040390 VPERMILPS ymm16, ymmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001EF0 62a37d280444db0890 VPERMILPS ymm16, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001EF9 62a37d280444dbf890 VPERMILPS ymm16, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F02 62037d4804c790 VPERMILPS zmm24, zmm31, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F09 62637d48040390 VPERMILPS zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F10 62237d480444db0490 VPERMILPS zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F19 62237d480444dbfc90 VPERMILPS zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F22 c4e379141390 VPEXTRB byte ptr [rbx], xmm2, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F28 c4e3791494f30001000090 VPEXTRB byte ptr [rbx+rsi*8+0x100], xmm2, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F33 c4e3791494f300ffffff90 VPEXTRB byte ptr [rbx+rsi*8-0x100], xmm2, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F3E 62f37d0814d190 VPEXTRB ecx, xmm2, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E9NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F45 62f37d0814d190 VPEXTRB ecx, xmm2, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E9NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F4C c4e37914d190 VPEXTRB ecx, xmm2, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F52 c4e37914d190 VPEXTRB ecx, xmm2, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F58 c4e37916d190 VPEXTRD ecx, xmm2, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F5E c4e37916d190 VPEXTRD ecx, xmm2, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F64 c4e379161390 VPEXTRD dword ptr [rbx], xmm2, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F6A c4e3791694f30001000090 VPEXTRD dword ptr [rbx+rsi*8+0x100], xmm2, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F75 c4e3f916d190 VPEXTRQ rcx, xmm2, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F7B c4e3f9161390 VPEXTRQ qword ptr [rbx], xmm2, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F81 c4e3f91694f30001000090 VPEXTRQ qword ptr [rbx+rsi*8+0x100], xmm2, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F8C 62f37d0815c190 VPEXTRW ecx, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E9NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F93 c5f9c5c890 VPEXTRW ecx, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F98 c5f9c5c890 VPEXTRW ecx, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F9D c4e379151390 VPEXTRW word ptr [rbx], xmm2, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001FA3 c4e3791594f30001000090 VPEXTRW word ptr [rbx+rsi*8+0x100], xmm2, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001FAE c4e3791594f300ffffff90 VPEXTRW word ptr [rbx+rsi*8-0x100], xmm2, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001FB9 62f37d0815d190 VPEXTRW ecx, xmm2, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E9NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001FC0 c5f9c5ca90 VPEXTRW ecx, xmm2, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001FC5 c5f9c5ca90 VPEXTRW ecx, xmm2, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001FCA c4e24102d0 VPHADDD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001FCF c4e2410213 VPHADDD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001FD4 c4a2410294db00010000 VPHADDD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000001FDE c4a2410294db00ffffff VPHADDD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000001FE8 c4e24103d0 VPHADDSW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001FED c4e2410313 VPHADDSW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001FF2 c4a2410394db00010000 VPHADDSW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000001FFC c4a2410394db00ffffff VPHADDSW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002006 c4e24101d0 VPHADDW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000200B c4e2410113 VPHADDW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002010 c4a2410194db00010000 VPHADDW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000201A c4a2410194db00ffffff VPHADDW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002024 c4e27941d0 VPHMINPOSUW xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002029 c4e2794113 VPHMINPOSUW xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000202E c4a2794194db00010000 VPHMINPOSUW xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002038 c4a2794194db00ffffff VPHMINPOSUW xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002042 c4e24106d0 VPHSUBD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002047 c4e2410613 VPHSUBD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000204C c4a2410694db00010000 VPHSUBD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002056 c4a2410694db00ffffff VPHSUBD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002060 c4e24107d0 VPHSUBSW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002065 c4e2410713 VPHSUBSW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000206A c4a2410794db00010000 VPHSUBSW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002074 c4a2410794db00ffffff VPHSUBSW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +000000000000207E c4e24105d0 VPHSUBW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002083 c4e2410513 VPHSUBW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002088 c4a2410594db00010000 VPHSUBW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002092 c4a2410594db00ffffff VPHSUBW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +000000000000209C c4e341201390 VPINSRB xmm2, xmm7, byte ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000020A2 c4e3412094f30001000090 VPINSRB xmm2, xmm7, byte ptr [rbx+rsi*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000020AD c4e3412094f300ffffff90 VPINSRB xmm2, xmm7, byte ptr [rbx+rsi*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000020B8 c4e34120d190 VPINSRB xmm2, xmm7, ecx, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000020BE c4e34120d190 VPINSRB xmm2, xmm7, ecx, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000020C4 c4e34122d190 VPINSRD xmm2, xmm7, ecx, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000020CA c4e341221390 VPINSRD xmm2, xmm7, dword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000020D0 c4e3412294f30001000090 VPINSRD xmm2, xmm7, dword ptr [rbx+rsi*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000020DB c4e3c122d190 VPINSRQ xmm2, xmm7, rcx, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000020E1 c4e3c1221390 VPINSRQ xmm2, xmm7, qword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000020E7 c4e3c12294f30001000090 VPINSRQ xmm2, xmm7, qword ptr [rbx+rsi*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000020F2 c5c1c41390 VPINSRW xmm2, xmm7, word ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000020F7 c5c1c494f30001000090 VPINSRW xmm2, xmm7, word ptr [rbx+rsi*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002101 c5c1c494f300ffffff90 VPINSRW xmm2, xmm7, word ptr [rbx+rsi*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000210B c5c1c4d190 VPINSRW xmm2, xmm7, ecx, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002110 c5c1c4d190 VPINSRW xmm2, xmm7, ecx, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002115 c4e24104d0 VPMADDUBSW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000211A c4e2410413 VPMADDUBSW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000211F c4a2410494db00010000 VPMADDUBSW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002129 c4a2410494db00ffffff VPMADDUBSW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002133 62c2152804c7 VPMADDUBSW ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000002139 62e215280403 VPMADDUBSW ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000213F 62a215280444db08 VPMADDUBSW ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000002147 62a215280444dbf8 VPMADDUBSW ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000214F 62023d4004c7 VPMADDUBSW zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000002155 62623d400403 VPMADDUBSW zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000215B 62223d400444db04 VPMADDUBSW zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000002163 62223d400444dbfc VPMADDUBSW zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000216B c5c1f5d0 VPMADDWD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000216F c5c1f513 VPMADDWD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002173 c4a141f594db00010000 VPMADDWD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000217D c4a141f594db00ffffff VPMADDWD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002187 62c11528f5c7 VPMADDWD ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000218D 62e11528f503 VPMADDWD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000002193 62a11528f544db08 VPMADDWD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000219B 62a11528f544dbf8 VPMADDWD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000021A3 62013d40f5c7 VPMADDWD zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000021A9 62613d40f503 VPMADDWD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000021AF 62213d40f544db04 VPMADDWD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000021B7 62213d40f544dbfc VPMADDWD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000021BF c4e2413cd0 VPMAXSB xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000021C4 c4e2413c13 VPMAXSB xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000021C9 c4a2413c94db00010000 VPMAXSB xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000021D3 c4a2413c94db00ffffff VPMAXSB xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000021DD 62c215283cc7 VPMAXSB ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000021E3 62e215283c03 VPMAXSB ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000021E9 62a215283c44db08 VPMAXSB ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000021F1 62a215283c44dbf8 VPMAXSB ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000021F9 62023d403cc7 VPMAXSB zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000021FF 62623d403c03 VPMAXSB zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000002205 62223d403c44db04 VPMAXSB zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000220D 62223d403c44dbfc VPMAXSB zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000002215 c4e2413dd0 VPMAXSD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000221A c4e2413d13 VPMAXSD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000221F c4a2413d94db00010000 VPMAXSD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002229 c4a2413d94db00ffffff VPMAXSD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002233 62c215283dc7 VPMAXSD ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000002239 62e215283d03 VPMAXSD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000223F 62a215283d44db08 VPMAXSD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000002247 62a215283d44dbf8 VPMAXSD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000224F 62023d403dc7 VPMAXSD zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000002255 62623d403d03 VPMAXSD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000225B 62223d403d44db04 VPMAXSD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000002263 62223d403d44dbfc VPMAXSD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000226B c5c1eed0 VPMAXSW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000226F c5c1ee13 VPMAXSW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002273 c4a141ee94db00010000 VPMAXSW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000227D c4a141ee94db00ffffff VPMAXSW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002287 62c11528eec7 VPMAXSW ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000228D 62e11528ee03 VPMAXSW ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000002293 62a11528ee44db08 VPMAXSW ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000229B 62a11528ee44dbf8 VPMAXSW ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000022A3 62013d40eec7 VPMAXSW zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000022A9 62613d40ee03 VPMAXSW zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000022AF 62213d40ee44db04 VPMAXSW zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000022B7 62213d40ee44dbfc VPMAXSW zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000022BF c5c1ded0 VPMAXUB xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000022C3 c5c1de13 VPMAXUB xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000022C7 c4a141de94db00010000 VPMAXUB xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000022D1 c4a141de94db00ffffff VPMAXUB xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000022DB 62c11528dec7 VPMAXUB ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000022E1 62e11528de03 VPMAXUB ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000022E7 62a11528de44db08 VPMAXUB ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000022EF 62a11528de44dbf8 VPMAXUB ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000022F7 62013d40dec7 VPMAXUB zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000022FD 62613d40de03 VPMAXUB zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000002303 62213d40de44db04 VPMAXUB zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000230B 62213d40de44dbfc VPMAXUB zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000002313 c4e2413fd0 VPMAXUD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002318 c4e2413f13 VPMAXUD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000231D c4a2413f94db00010000 VPMAXUD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002327 c4a2413f94db00ffffff VPMAXUD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002331 62c215283fc7 VPMAXUD ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000002337 62e215283f03 VPMAXUD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000233D 62a215283f44db08 VPMAXUD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000002345 62a215283f44dbf8 VPMAXUD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000234D 62023d403fc7 VPMAXUD zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000002353 62623d403f03 VPMAXUD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000002359 62223d403f44db04 VPMAXUD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000002361 62223d403f44dbfc VPMAXUD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000002369 c4e2413ed0 VPMAXUW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000236E c4e2413e13 VPMAXUW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002373 c4a2413e94db00010000 VPMAXUW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000237D c4a2413e94db00ffffff VPMAXUW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002387 62c215283ec7 VPMAXUW ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000238D 62e215283e03 VPMAXUW ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000002393 62a215283e44db08 VPMAXUW ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000239B 62a215283e44dbf8 VPMAXUW ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000023A3 62023d403ec7 VPMAXUW zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000023A9 62623d403e03 VPMAXUW zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000023AF 62223d403e44db04 VPMAXUW zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000023B7 62223d403e44dbfc VPMAXUW zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000023BF c4e24138d0 VPMINSB xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000023C4 c4e2413813 VPMINSB xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000023C9 c4a2413894db00010000 VPMINSB xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000023D3 c4a2413894db00ffffff VPMINSB xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000023DD 62c2152838c7 VPMINSB ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000023E3 62e215283803 VPMINSB ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000023E9 62a215283844db08 VPMINSB ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000023F1 62a215283844dbf8 VPMINSB ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000023F9 62023d4038c7 VPMINSB zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000023FF 62623d403803 VPMINSB zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000002405 62223d403844db04 VPMINSB zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000240D 62223d403844dbfc VPMINSB zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000002415 c4e24139d0 VPMINSD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000241A c4e2413913 VPMINSD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000241F c4a2413994db00010000 VPMINSD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002429 c4a2413994db00ffffff VPMINSD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002433 62c2152839c7 VPMINSD ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000002439 62e215283903 VPMINSD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000243F 62a215283944db08 VPMINSD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000002447 62a215283944dbf8 VPMINSD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000244F 62023d4039c7 VPMINSD zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000002455 62623d403903 VPMINSD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000245B 62223d403944db04 VPMINSD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000002463 62223d403944dbfc VPMINSD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000246B c5c1ead0 VPMINSW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000246F c5c1ea13 VPMINSW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002473 c4a141ea94db00010000 VPMINSW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000247D c4a141ea94db00ffffff VPMINSW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002487 62c11528eac7 VPMINSW ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000248D 62e11528ea03 VPMINSW ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000002493 62a11528ea44db08 VPMINSW ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000249B 62a11528ea44dbf8 VPMINSW ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000024A3 62013d40eac7 VPMINSW zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000024A9 62613d40ea03 VPMINSW zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000024AF 62213d40ea44db04 VPMINSW zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000024B7 62213d40ea44dbfc VPMINSW zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000024BF c5c1dad0 VPMINUB xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000024C3 c5c1da13 VPMINUB xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000024C7 c4a141da94db00010000 VPMINUB xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000024D1 c4a141da94db00ffffff VPMINUB xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000024DB 62c11528dac7 VPMINUB ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000024E1 62e11528da03 VPMINUB ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000024E7 62a11528da44db08 VPMINUB ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000024EF 62a11528da44dbf8 VPMINUB ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000024F7 62013d40dac7 VPMINUB zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000024FD 62613d40da03 VPMINUB zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000002503 62213d40da44db04 VPMINUB zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000250B 62213d40da44dbfc VPMINUB zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000002513 c4e2413bd0 VPMINUD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002518 c4e2413b13 VPMINUD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000251D c4a2413b94db00010000 VPMINUD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002527 c4a2413b94db00ffffff VPMINUD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002531 62c215283bc7 VPMINUD ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000002537 62e215283b03 VPMINUD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000253D 62a215283b44db08 VPMINUD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000002545 62a215283b44dbf8 VPMINUD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000254D 62023d403bc7 VPMINUD zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000002553 62623d403b03 VPMINUD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000002559 62223d403b44db04 VPMINUD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000002561 62223d403b44dbfc VPMINUD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000002569 c4e2413ad0 VPMINUW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000256E c4e2413a13 VPMINUW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002573 c4a2413a94db00010000 VPMINUW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000257D c4a2413a94db00ffffff VPMINUW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002587 62c215283ac7 VPMINUW ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000258D 62e215283a03 VPMINUW ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000002593 62a215283a44db08 VPMINUW ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000259B 62a215283a44dbf8 VPMINUW ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000025A3 62023d403ac7 VPMINUW zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000025A9 62623d403a03 VPMINUW zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000025AF 62223d403a44db04 VPMINUW zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000025B7 62223d403a44dbfc VPMINUW zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000025BF c5f9d7c8 VPMOVMSKB ecx, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000025C3 c4c17dd7cf VPMOVMSKB ecx, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000025C8 c5f9d7c8 VPMOVMSKB ecx, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000025CC c4c17dd7cf VPMOVMSKB ecx, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000025D1 c4e27921d0 VPMOVSXBD xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000025D6 c4e2792113 VPMOVSXBD xmm2, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +00000000000025DB c4a2792194db00010000 VPMOVSXBD xmm2, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000025E5 c4a2792194db00ffffff VPMOVSXBD xmm2, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000025EF 62e27d2821c0 VPMOVSXBD ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000025F5 62e27d282103 VPMOVSXBD ymm16, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000025FB 62a27d282144db20 VPMOVSXBD ymm16, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000002603 62a27d282144dbe0 VPMOVSXBD ymm16, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +000000000000260B 62627d4821c0 VPMOVSXBD zmm24, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002611 62627d482103 VPMOVSXBD zmm24, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002617 62227d482144db10 VPMOVSXBD zmm24, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000261F 62227d482144dbf0 VPMOVSXBD zmm24, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000002627 c4e27922d0 VPMOVSXBQ xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000262C c4e2792213 VPMOVSXBQ xmm2, word ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + +0000000000002631 c4a2792294db00010000 VPMOVSXBQ xmm2, word ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000263B c4a2792294db00ffffff VPMOVSXBQ xmm2, word ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002645 62e27d2822c0 VPMOVSXBQ ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000264B 62e27d282203 VPMOVSXBQ ymm16, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +0000000000002651 62a27d282244db40 VPMOVSXBQ ymm16, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000040, + +0000000000002659 62a27d282244dbc0 VPMOVSXBQ ymm16, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffc0, + +0000000000002661 62627d4822c0 VPMOVSXBQ zmm24, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002667 62627d482203 VPMOVSXBQ zmm24, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000266D 62227d482244db20 VPMOVSXBQ zmm24, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000002675 62227d482244dbe0 VPMOVSXBQ zmm24, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +000000000000267D c4e27920d0 VPMOVSXBW xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002682 c4e2792013 VPMOVSXBW xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000002687 c4a2792094db00010000 VPMOVSXBW xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002691 c4a2792094db00ffffff VPMOVSXBW xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +000000000000269B 62e27d2820c0 VPMOVSXBW ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000026A1 62e27d282003 VPMOVSXBW ymm16, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000026A7 62a27d282044db10 VPMOVSXBW ymm16, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000026AF 62a27d282044dbf0 VPMOVSXBW ymm16, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000026B7 62427d4820c7 VPMOVSXBW zmm24, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000026BD 62627d482003 VPMOVSXBW zmm24, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000026C3 62227d482044db08 VPMOVSXBW zmm24, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000026CB 62227d482044dbf8 VPMOVSXBW zmm24, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000026D3 c4e27925d0 VPMOVSXDQ xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000026D8 c4e2792513 VPMOVSXDQ xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000026DD c4a2792594db00010000 VPMOVSXDQ xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000026E7 c4a2792594db00ffffff VPMOVSXDQ xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000026F1 62e27d2825c0 VPMOVSXDQ ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000026F7 62e27d282503 VPMOVSXDQ ymm16, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000026FD 62a27d282544db10 VPMOVSXDQ ymm16, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000002705 62a27d282544dbf0 VPMOVSXDQ ymm16, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000270D 62427d4825c7 VPMOVSXDQ zmm24, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000002713 62627d482503 VPMOVSXDQ zmm24, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000002719 62227d482544db08 VPMOVSXDQ zmm24, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000002721 62227d482544dbf8 VPMOVSXDQ zmm24, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000002729 c4e27923d0 VPMOVSXWD xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000272E c4e2792313 VPMOVSXWD xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000002733 c4a2792394db00010000 VPMOVSXWD xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000273D c4a2792394db00ffffff VPMOVSXWD xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002747 62e27d2823c0 VPMOVSXWD ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000274D 62e27d282303 VPMOVSXWD ymm16, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002753 62a27d282344db10 VPMOVSXWD ymm16, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000275B 62a27d282344dbf0 VPMOVSXWD ymm16, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000002763 62427d4823c7 VPMOVSXWD zmm24, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000002769 62627d482303 VPMOVSXWD zmm24, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000276F 62227d482344db08 VPMOVSXWD zmm24, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000002777 62227d482344dbf8 VPMOVSXWD zmm24, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000277F c4e27924d0 VPMOVSXWQ xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002784 c4e2792413 VPMOVSXWQ xmm2, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +0000000000002789 c4a2792494db00010000 VPMOVSXWQ xmm2, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002793 c4a2792494db00ffffff VPMOVSXWQ xmm2, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +000000000000279D 62e27d2824c0 VPMOVSXWQ ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000027A3 62e27d282403 VPMOVSXWQ ymm16, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000027A9 62a27d282444db20 VPMOVSXWQ ymm16, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +00000000000027B1 62a27d282444dbe0 VPMOVSXWQ ymm16, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +00000000000027B9 62627d4824c0 VPMOVSXWQ zmm24, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000027BF 62627d482403 VPMOVSXWQ zmm24, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000027C5 62227d482444db10 VPMOVSXWQ zmm24, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000027CD 62227d482444dbf0 VPMOVSXWQ zmm24, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000027D5 c4e27931d0 VPMOVZXBD xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000027DA c4e2793113 VPMOVZXBD xmm2, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +00000000000027DF c4a2793194db00010000 VPMOVZXBD xmm2, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000027E9 c4a2793194db00ffffff VPMOVZXBD xmm2, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000027F3 62e27d2831c0 VPMOVZXBD ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000027F9 62e27d283103 VPMOVZXBD ymm16, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000027FF 62a27d283144db20 VPMOVZXBD ymm16, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000002807 62a27d283144dbe0 VPMOVZXBD ymm16, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +000000000000280F 62627d4831c0 VPMOVZXBD zmm24, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002815 62627d483103 VPMOVZXBD zmm24, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000281B 62227d483144db10 VPMOVZXBD zmm24, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000002823 62227d483144dbf0 VPMOVZXBD zmm24, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000282B c4e27932d0 VPMOVZXBQ xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002830 c4e2793213 VPMOVZXBQ xmm2, word ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + +0000000000002835 c4a2793294db00010000 VPMOVZXBQ xmm2, word ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000283F c4a2793294db00ffffff VPMOVZXBQ xmm2, word ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002849 62e27d2832c0 VPMOVZXBQ ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000284F 62e27d283203 VPMOVZXBQ ymm16, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +0000000000002855 62a27d283244db40 VPMOVZXBQ ymm16, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000040, + +000000000000285D 62a27d283244dbc0 VPMOVZXBQ ymm16, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffc0, + +0000000000002865 62627d4832c0 VPMOVZXBQ zmm24, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000286B 62627d483203 VPMOVZXBQ zmm24, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000002871 62227d483244db20 VPMOVZXBQ zmm24, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000002879 62227d483244dbe0 VPMOVZXBQ zmm24, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Eigth Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +0000000000002881 c4e27930d0 VPMOVZXBW xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002886 c4e2793013 VPMOVZXBW xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000288B c4a2793094db00010000 VPMOVZXBW xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002895 c4a2793094db00ffffff VPMOVZXBW xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +000000000000289F 62e27d2830c0 VPMOVZXBW ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000028A5 62e27d283003 VPMOVZXBW ymm16, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000028AB 62a27d283044db10 VPMOVZXBW ymm16, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000028B3 62a27d283044dbf0 VPMOVZXBW ymm16, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000028BB 62427d4830c7 VPMOVZXBW zmm24, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000028C1 62627d483003 VPMOVZXBW zmm24, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000028C7 62227d483044db08 VPMOVZXBW zmm24, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000028CF 62227d483044dbf8 VPMOVZXBW zmm24, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000028D7 c4e27935d0 VPMOVZXDQ xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000028DC c4e2793513 VPMOVZXDQ xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000028E1 c4a2793594db00010000 VPMOVZXDQ xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000028EB c4a2793594db00ffffff VPMOVZXDQ xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000028F5 62e27d2835c0 VPMOVZXDQ ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000028FB 62e27d283503 VPMOVZXDQ ymm16, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002901 62a27d283544db10 VPMOVZXDQ ymm16, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000002909 62a27d283544dbf0 VPMOVZXDQ ymm16, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000002911 62427d4835c7 VPMOVZXDQ zmm24, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000002917 62627d483503 VPMOVZXDQ zmm24, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000291D 62227d483544db08 VPMOVZXDQ zmm24, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000002925 62227d483544dbf8 VPMOVZXDQ zmm24, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000292D c4e27933d0 VPMOVZXWD xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002932 c4e2793313 VPMOVZXWD xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000002937 c4a2793394db00010000 VPMOVZXWD xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002941 c4a2793394db00ffffff VPMOVZXWD xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +000000000000294B 62e27d2833c0 VPMOVZXWD ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002951 62e27d283303 VPMOVZXWD ymm16, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002957 62a27d283344db10 VPMOVZXWD ymm16, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000295F 62a27d283344dbf0 VPMOVZXWD ymm16, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000002967 62427d4833c7 VPMOVZXWD zmm24, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000296D 62627d483303 VPMOVZXWD zmm24, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000002973 62227d483344db08 VPMOVZXWD zmm24, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000297B 62227d483344dbf8 VPMOVZXWD zmm24, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Half Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000002983 c4e27934d0 VPMOVZXWQ xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002988 c4e2793413 VPMOVZXWQ xmm2, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +000000000000298D c4a2793494db00010000 VPMOVZXWQ xmm2, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002997 c4a2793494db00ffffff VPMOVZXWQ xmm2, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000029A1 62e27d2834c0 VPMOVZXWQ ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000029A7 62e27d283403 VPMOVZXWQ ymm16, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000029AD 62a27d283444db20 VPMOVZXWQ ymm16, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +00000000000029B5 62a27d283444dbe0 VPMOVZXWQ ymm16, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +00000000000029BD 62627d4834c0 VPMOVZXWQ zmm24, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000029C3 62627d483403 VPMOVZXWQ zmm24, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000029C9 62227d483444db10 VPMOVZXWQ zmm24, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000029D1 62227d483444dbf0 VPMOVZXWQ zmm24, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Quarter Mem + Exception class: EVEX, exception type: E5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000029D9 c4e24128d0 VPMULDQ xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000029DE c4e2412813 VPMULDQ xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000029E3 c4a2412894db00010000 VPMULDQ xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000029ED c4a2412894db00ffffff VPMULDQ xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000029F7 62c2952828c7 VPMULDQ ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000029FD 62e295282803 VPMULDQ ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000002A03 62a295282844db08 VPMULDQ ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000002A0B 62a295282844dbf8 VPMULDQ ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000002A13 6202bd4028c7 VPMULDQ zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000002A19 6262bd402803 VPMULDQ zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000002A1F 6222bd402844db04 VPMULDQ zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000002A27 6222bd402844dbfc VPMULDQ zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000002A2F c4e2410bd0 VPMULHRSW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002A34 c4e2410b13 VPMULHRSW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002A39 c4a2410b94db00010000 VPMULHRSW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002A43 c4a2410b94db00ffffff VPMULHRSW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002A4D 62c215280bc7 VPMULHRSW ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000002A53 62e215280b03 VPMULHRSW ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000002A59 62a215280b44db08 VPMULHRSW ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000002A61 62a215280b44dbf8 VPMULHRSW ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000002A69 62023d400bc7 VPMULHRSW zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000002A6F 62623d400b03 VPMULHRSW zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000002A75 62223d400b44db04 VPMULHRSW zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000002A7D 62223d400b44dbfc VPMULHRSW zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000002A85 c5c1e4d0 VPMULHUW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002A89 c5c1e413 VPMULHUW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002A8D c4a141e494db00010000 VPMULHUW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002A97 c4a141e494db00ffffff VPMULHUW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002AA1 62c11528e4c7 VPMULHUW ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000002AA7 62e11528e403 VPMULHUW ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000002AAD 62a11528e444db08 VPMULHUW ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000002AB5 62a11528e444dbf8 VPMULHUW ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000002ABD 62013d40e4c7 VPMULHUW zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000002AC3 62613d40e403 VPMULHUW zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000002AC9 62213d40e444db04 VPMULHUW zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000002AD1 62213d40e444dbfc VPMULHUW zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000002AD9 c5c1e5d0 VPMULHW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002ADD c5c1e513 VPMULHW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002AE1 c4a141e594db00010000 VPMULHW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002AEB c4a141e594db00ffffff VPMULHW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002AF5 62c11528e5c7 VPMULHW ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000002AFB 62e11528e503 VPMULHW ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000002B01 62a11528e544db08 VPMULHW ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000002B09 62a11528e544dbf8 VPMULHW ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000002B11 62013d40e5c7 VPMULHW zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000002B17 62613d40e503 VPMULHW zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000002B1D 62213d40e544db04 VPMULHW zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000002B25 62213d40e544dbfc VPMULHW zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000002B2D c4e24140d0 VPMULLD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002B32 c4e2414013 VPMULLD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002B37 c4a2414094db00010000 VPMULLD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002B41 c4a2414094db00ffffff VPMULLD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002B4B 62c2152840c7 VPMULLD ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000002B51 62e215284003 VPMULLD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000002B57 62a215284044db08 VPMULLD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000002B5F 62a215284044dbf8 VPMULLD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000002B67 62023d4040c7 VPMULLD zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000002B6D 62623d404003 VPMULLD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000002B73 62223d404044db04 VPMULLD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000002B7B 62223d404044dbfc VPMULLD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000002B83 c5c1d5d0 VPMULLW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002B87 c5c1d513 VPMULLW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002B8B c4a141d594db00010000 VPMULLW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002B95 c4a141d594db00ffffff VPMULLW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002B9F 62c11528d5c7 VPMULLW ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000002BA5 62e11528d503 VPMULLW ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000002BAB 62a11528d544db08 VPMULLW ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000002BB3 62a11528d544dbf8 VPMULLW ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000002BBB 62013d40d5c7 VPMULLW zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000002BC1 62613d40d503 VPMULLW zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000002BC7 62213d40d544db04 VPMULLW zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000002BCF 62213d40d544dbfc VPMULLW zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000002BD7 c5c1f4d0 VPMULUDQ xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002BDB c5c1f413 VPMULUDQ xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002BDF c4a141f494db00010000 VPMULUDQ xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002BE9 c4a141f494db00ffffff VPMULUDQ xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002BF3 62c19528f4c7 VPMULUDQ ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000002BF9 62e19528f403 VPMULUDQ ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000002BFF 62a19528f444db08 VPMULUDQ ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000002C07 62a19528f444dbf8 VPMULUDQ ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000002C0F 6201bd40f4c7 VPMULUDQ zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000002C15 6261bd40f403 VPMULUDQ zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000002C1B 6221bd40f444db04 VPMULUDQ zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000002C23 6221bd40f444dbfc VPMULUDQ zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000002C2B c5c1ebd0 VPOR xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002C2F c5c1eb13 VPOR xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002C33 c4a141eb94db00010000 VPOR xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002C3D c4a141eb94db00ffffff VPOR xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002C47 c5c1f6d0 VPSADBW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002C4B c5c1f613 VPSADBW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002C4F c4a141f694db00010000 VPSADBW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002C59 c4a141f694db00ffffff VPSADBW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002C63 62c11528f6c7 VPSADBW ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000002C69 62e11528f603 VPSADBW ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000002C6F 62a11528f644db08 VPSADBW ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000002C77 62a11528f644dbf8 VPSADBW ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000002C7F 62013d40f6c7 VPSADBW zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000002C85 62613d40f603 VPSADBW zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000002C8B 62213d40f644db04 VPSADBW zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000002C93 62213d40f644dbfc VPSADBW zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000002C9B c4e24100d0 VPSHUFB xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002CA0 c4e2410013 VPSHUFB xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002CA5 c4a2410094db00010000 VPSHUFB xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002CAF c4a2410094db00ffffff VPSHUFB xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002CB9 62c2152800c7 VPSHUFB ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000002CBF 62e215280003 VPSHUFB ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000002CC5 62a215280044db08 VPSHUFB ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000002CCD 62a215280044dbf8 VPSHUFB ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000002CD5 62023d4000c7 VPSHUFB zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000002CDB 62623d400003 VPSHUFB zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000002CE1 62223d400044db04 VPSHUFB zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000002CE9 62223d400044dbfc VPSHUFB zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000002CF1 c5f970d090 VPSHUFD xmm2, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002CF6 c5f9701390 VPSHUFD xmm2, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002CFB c4a1797094db0001000090 VPSHUFD xmm2, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D06 c4a1797094db00ffffff90 VPSHUFD xmm2, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D11 62c17d2870c790 VPSHUFD ymm16, ymm15, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D18 62e17d28700390 VPSHUFD ymm16, ymmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D1F 62a17d287044db0890 VPSHUFD ymm16, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D28 62a17d287044dbf890 VPSHUFD ymm16, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D31 62017d4870c790 VPSHUFD zmm24, zmm31, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D38 62617d48700390 VPSHUFD zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D3F 62217d487044db0490 VPSHUFD zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D48 62217d487044dbfc90 VPSHUFD zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D51 c5fa70d090 VPSHUFHW xmm2, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D56 c5fa701390 VPSHUFHW xmm2, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D5B c4a17a7094db0001000090 VPSHUFHW xmm2, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D66 c4a17a7094db00ffffff90 VPSHUFHW xmm2, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D71 62c17e2870c790 VPSHUFHW ymm16, ymm15, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D78 62e17e28700390 VPSHUFHW ymm16, ymmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D7F 62a17e287044db0890 VPSHUFHW ymm16, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D88 62a17e287044dbf890 VPSHUFHW ymm16, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D91 62017e4870c790 VPSHUFHW zmm24, zmm31, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D98 62617e48700390 VPSHUFHW zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D9F 62217e487044db0490 VPSHUFHW zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002DA8 62217e487044dbfc90 VPSHUFHW zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002DB1 c5fb70d090 VPSHUFLW xmm2, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002DB6 c5fb701390 VPSHUFLW xmm2, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002DBB c4a17b7094db0001000090 VPSHUFLW xmm2, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002DC6 c4a17b7094db00ffffff90 VPSHUFLW xmm2, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002DD1 62c17f2870c790 VPSHUFLW ymm16, ymm15, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002DD8 62e17f28700390 VPSHUFLW ymm16, ymmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002DDF 62a17f287044db0890 VPSHUFLW ymm16, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002DE8 62a17f287044dbf890 VPSHUFLW ymm16, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002DF1 62017f4870c790 VPSHUFLW zmm24, zmm31, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002DF8 62617f48700390 VPSHUFLW zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002DFF 62217f487044db0490 VPSHUFLW zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002E08 62217f487044dbfc90 VPSHUFLW zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002E11 c4e24108d0 VPSIGNB xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002E16 c4e2410813 VPSIGNB xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002E1B c4a2410894db00010000 VPSIGNB xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002E25 c4a2410894db00ffffff VPSIGNB xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002E2F c4e2410ad0 VPSIGND xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002E34 c4e2410a13 VPSIGND xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002E39 c4a2410a94db00010000 VPSIGND xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002E43 c4a2410a94db00ffffff VPSIGND xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002E4D c4e24109d0 VPSIGNW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002E52 c4e2410913 VPSIGNW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002E57 c4a2410994db00010000 VPSIGNW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002E61 c4a2410994db00ffffff VPSIGNW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002E6B c5c172f090 VPSLLD xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002E70 c4c11572f790 VPSLLD ymm13, ymm15, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002E76 62913d4072f790 VPSLLD zmm24, zmm31, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002E7D c5c1f2d0 VPSLLD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002E81 c5c1f213 VPSLLD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002E85 c4a141f294db00010000 VPSLLD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002E8F c4a141f294db00ffffff VPSLLD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002E99 62e11528f2c0 VPSLLD ymm16, ymm13, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002E9F 62e11528f203 VPSLLD ymm16, ymm13, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002EA5 62a11528f244db10 VPSLLD ymm16, ymm13, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000002EAD 62a11528f244dbf0 VPSLLD ymm16, ymm13, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000002EB5 62613d40f2c0 VPSLLD zmm24, zmm24, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002EBB 62613d40f203 VPSLLD zmm24, zmm24, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002EC1 62213d40f244db10 VPSLLD zmm24, zmm24, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000002EC9 62213d40f244dbf0 VPSLLD zmm24, zmm24, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000002ED1 c5c173f890 VPSLLDQ xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002ED6 c4c11573ff90 VPSLLDQ ymm13, ymm15, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002EDC 62913d4073ff90 VPSLLDQ zmm24, zmm31, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002EE3 c5c173f090 VPSLLQ xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002EE8 c4c11573f790 VPSLLQ ymm13, ymm15, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002EEE 6291bd4073f790 VPSLLQ zmm24, zmm31, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002EF5 c5c1f3d0 VPSLLQ xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002EF9 c5c1f313 VPSLLQ xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002EFD c4a141f394db00010000 VPSLLQ xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002F07 c4a141f394db00ffffff VPSLLQ xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002F11 62e19528f3c0 VPSLLQ ymm16, ymm13, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002F17 62e19528f303 VPSLLQ ymm16, ymm13, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002F1D 62a19528f344db10 VPSLLQ ymm16, ymm13, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000002F25 62a19528f344dbf0 VPSLLQ ymm16, ymm13, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000002F2D 6261bd40f3c0 VPSLLQ zmm24, zmm24, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002F33 6261bd40f303 VPSLLQ zmm24, zmm24, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002F39 6221bd40f344db10 VPSLLQ zmm24, zmm24, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000002F41 6221bd40f344dbf0 VPSLLQ zmm24, zmm24, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000002F49 c5c171f090 VPSLLW xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002F4E c4c11571f790 VPSLLW ymm13, ymm15, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002F54 62913d4071f790 VPSLLW zmm24, zmm31, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002F5B c5c1f1d0 VPSLLW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002F5F c5c1f113 VPSLLW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002F63 c4a141f194db00010000 VPSLLW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002F6D c4a141f194db00ffffff VPSLLW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002F77 62e11528f1c0 VPSLLW ymm16, ymm13, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002F7D 62e11528f103 VPSLLW ymm16, ymm13, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002F83 62a11528f144db10 VPSLLW ymm16, ymm13, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000002F8B 62a11528f144dbf0 VPSLLW ymm16, ymm13, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000002F93 62613d40f1c0 VPSLLW zmm24, zmm24, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002F99 62613d40f103 VPSLLW zmm24, zmm24, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002F9F 62213d40f144db10 VPSLLW zmm24, zmm24, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000002FA7 62213d40f144dbf0 VPSLLW zmm24, zmm24, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000002FAF c5c172e090 VPSRAD xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002FB4 c4c11572e790 VPSRAD ymm13, ymm15, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002FBA 62913d4072e790 VPSRAD zmm24, zmm31, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002FC1 c5c1e2d0 VPSRAD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002FC5 c5c1e213 VPSRAD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002FC9 c4a141e294db00010000 VPSRAD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000002FD3 c4a141e294db00ffffff VPSRAD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002FDD 62e11528e2c0 VPSRAD ymm16, ymm13, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002FE3 62e11528e203 VPSRAD ymm16, ymm13, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002FE9 62a11528e244db10 VPSRAD ymm16, ymm13, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000002FF1 62a11528e244dbf0 VPSRAD ymm16, ymm13, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000002FF9 62613d40e2c0 VPSRAD zmm24, zmm24, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002FFF 62613d40e203 VPSRAD zmm24, zmm24, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000003005 62213d40e244db10 VPSRAD zmm24, zmm24, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000300D 62213d40e244dbf0 VPSRAD zmm24, zmm24, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000003015 c5c171e090 VPSRAW xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000301A c4c11571e790 VPSRAW ymm13, ymm15, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003020 62913d4071e790 VPSRAW zmm24, zmm31, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003027 c5c1e1d0 VPSRAW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000302B c5c1e113 VPSRAW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000302F c4a141e194db00010000 VPSRAW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000003039 c4a141e194db00ffffff VPSRAW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000003043 62e11528e1c0 VPSRAW ymm16, ymm13, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000003049 62e11528e103 VPSRAW ymm16, ymm13, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000304F 62a11528e144db10 VPSRAW ymm16, ymm13, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000003057 62a11528e144dbf0 VPSRAW ymm16, ymm13, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000305F 62613d40e1c0 VPSRAW zmm24, zmm24, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000003065 62613d40e103 VPSRAW zmm24, zmm24, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000306B 62213d40e144db10 VPSRAW zmm24, zmm24, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000003073 62213d40e144dbf0 VPSRAW zmm24, zmm24, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000307B c5c172d090 VPSRLD xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003080 c4c11572d790 VPSRLD ymm13, ymm15, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003086 62913d4072d790 VPSRLD zmm24, zmm31, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000308D c5c1d2d0 VPSRLD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000003091 c5c1d213 VPSRLD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000003095 c4a141d294db00010000 VPSRLD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000309F c4a141d294db00ffffff VPSRLD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000030A9 62e11528d2c0 VPSRLD ymm16, ymm13, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000030AF 62e11528d203 VPSRLD ymm16, ymm13, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000030B5 62a11528d244db10 VPSRLD ymm16, ymm13, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000030BD 62a11528d244dbf0 VPSRLD ymm16, ymm13, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000030C5 62613d40d2c0 VPSRLD zmm24, zmm24, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000030CB 62613d40d203 VPSRLD zmm24, zmm24, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000030D1 62213d40d244db10 VPSRLD zmm24, zmm24, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000030D9 62213d40d244dbf0 VPSRLD zmm24, zmm24, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000030E1 c5c173d890 VPSRLDQ xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000030E6 c4c11573df90 VPSRLDQ ymm13, ymm15, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000030EC 62913d4073df90 VPSRLDQ zmm24, zmm31, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000030F3 c5c173d090 VPSRLQ xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000030F8 c4c11573d790 VPSRLQ ymm13, ymm15, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000030FE 6291bd4073d790 VPSRLQ zmm24, zmm31, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003105 c5c1d3d0 VPSRLQ xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000003109 c5c1d313 VPSRLQ xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000310D c4a141d394db00010000 VPSRLQ xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000003117 c4a141d394db00ffffff VPSRLQ xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000003121 62e19528d3c0 VPSRLQ ymm16, ymm13, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000003127 62e19528d303 VPSRLQ ymm16, ymm13, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000312D 62a19528d344db10 VPSRLQ ymm16, ymm13, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000003135 62a19528d344dbf0 VPSRLQ ymm16, ymm13, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000313D 6261bd40d3c0 VPSRLQ zmm24, zmm24, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000003143 6261bd40d303 VPSRLQ zmm24, zmm24, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000003149 6221bd40d344db10 VPSRLQ zmm24, zmm24, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000003151 6221bd40d344dbf0 VPSRLQ zmm24, zmm24, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000003159 c5c171d090 VPSRLW xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000315E c4c11571d790 VPSRLW ymm13, ymm15, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003164 62913d4071d790 VPSRLW zmm24, zmm31, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000316B c5c1d1d0 VPSRLW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000316F c5c1d113 VPSRLW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000003173 c4a141d194db00010000 VPSRLW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000317D c4a141d194db00ffffff VPSRLW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000003187 62e11528d1c0 VPSRLW ymm16, ymm13, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000318D 62e11528d103 VPSRLW ymm16, ymm13, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000003193 62a11528d144db10 VPSRLW ymm16, ymm13, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000319B 62a11528d144dbf0 VPSRLW ymm16, ymm13, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000031A3 62613d40d1c0 VPSRLW zmm24, zmm24, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000031A9 62613d40d103 VPSRLW zmm24, zmm24, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000031AF 62213d40d144db10 VPSRLW zmm24, zmm24, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000031B7 62213d40d144dbf0 VPSRLW zmm24, zmm24, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Mem 128 + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000031BF c5c1f8d0 VPSUBB xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000031C3 c5c1f813 VPSUBB xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000031C7 c4a141f894db00010000 VPSUBB xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000031D1 c4a141f894db00ffffff VPSUBB xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000031DB 62c11528f8c7 VPSUBB ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000031E1 62e11528f803 VPSUBB ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000031E7 62a11528f844db08 VPSUBB ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000031EF 62a11528f844dbf8 VPSUBB ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000031F7 62013d40f8c7 VPSUBB zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000031FD 62613d40f803 VPSUBB zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000003203 62213d40f844db04 VPSUBB zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000320B 62213d40f844dbfc VPSUBB zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000003213 c5c1fad0 VPSUBD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000003217 c5c1fa13 VPSUBD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000321B c4a141fa94db00010000 VPSUBD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000003225 c4a141fa94db00ffffff VPSUBD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +000000000000322F 62c11528fac7 VPSUBD ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000003235 62e11528fa03 VPSUBD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000323B 62a11528fa44db08 VPSUBD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000003243 62a11528fa44dbf8 VPSUBD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000324B 62013d40fac7 VPSUBD zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000003251 62613d40fa03 VPSUBD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000003257 62213d40fa44db04 VPSUBD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000325F 62213d40fa44dbfc VPSUBD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000003267 c5c1fbd0 VPSUBQ xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000326B c5c1fb13 VPSUBQ xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000326F c4a141fb94db00010000 VPSUBQ xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000003279 c4a141fb94db00ffffff VPSUBQ xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000003283 62c19528fbc7 VPSUBQ ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000003289 62e19528fb03 VPSUBQ ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000328F 62a19528fb44db08 VPSUBQ ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000003297 62a19528fb44dbf8 VPSUBQ ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000329F 6201bd40fbc7 VPSUBQ zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000032A5 6261bd40fb03 VPSUBQ zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000032AB 6221bd40fb44db04 VPSUBQ zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000032B3 6221bd40fb44dbfc VPSUBQ zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000032BB c5c1e8d0 VPSUBSB xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000032BF c5c1e813 VPSUBSB xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000032C3 c4a141e894db00010000 VPSUBSB xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000032CD c4a141e894db00ffffff VPSUBSB xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000032D7 62c11528e8c7 VPSUBSB ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000032DD 62e11528e803 VPSUBSB ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000032E3 62a11528e844db08 VPSUBSB ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000032EB 62a11528e844dbf8 VPSUBSB ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000032F3 62013d40e8c7 VPSUBSB zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000032F9 62613d40e803 VPSUBSB zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000032FF 62213d40e844db04 VPSUBSB zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000003307 62213d40e844dbfc VPSUBSB zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000330F c5c1e9d0 VPSUBSW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000003313 c5c1e913 VPSUBSW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000003317 c4a141e994db00010000 VPSUBSW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000003321 c4a141e994db00ffffff VPSUBSW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +000000000000332B 62c11528e9c7 VPSUBSW ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000003331 62e11528e903 VPSUBSW ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000003337 62a11528e944db08 VPSUBSW ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000333F 62a11528e944dbf8 VPSUBSW ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000003347 62013d40e9c7 VPSUBSW zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000334D 62613d40e903 VPSUBSW zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000003353 62213d40e944db04 VPSUBSW zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000335B 62213d40e944dbfc VPSUBSW zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000003363 c5c1d8d0 VPSUBUSB xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000003367 c5c1d813 VPSUBUSB xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000336B c4a141d894db00010000 VPSUBUSB xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000003375 c4a141d894db00ffffff VPSUBUSB xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +000000000000337F 62c11528d8c7 VPSUBUSB ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000003385 62e11528d803 VPSUBUSB ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000338B 62a11528d844db08 VPSUBUSB ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000003393 62a11528d844dbf8 VPSUBUSB ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000339B 62013d40d8c7 VPSUBUSB zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000033A1 62613d40d803 VPSUBUSB zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000033A7 62213d40d844db04 VPSUBUSB zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000033AF 62213d40d844dbfc VPSUBUSB zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000033B7 c5c1d9d0 VPSUBUSW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000033BB c5c1d913 VPSUBUSW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000033BF c4a141d994db00010000 VPSUBUSW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000033C9 c4a141d994db00ffffff VPSUBUSW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000033D3 62c11528d9c7 VPSUBUSW ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000033D9 62e11528d903 VPSUBUSW ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000033DF 62a11528d944db08 VPSUBUSW ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000033E7 62a11528d944dbf8 VPSUBUSW ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000033EF 62013d40d9c7 VPSUBUSW zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000033F5 62613d40d903 VPSUBUSW zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000033FB 62213d40d944db04 VPSUBUSW zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000003403 62213d40d944dbfc VPSUBUSW zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000340B c5c1f9d0 VPSUBW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000340F c5c1f913 VPSUBW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000003413 c4a141f994db00010000 VPSUBW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000341D c4a141f994db00ffffff VPSUBW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000003427 62c11528f9c7 VPSUBW ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000342D 62e11528f903 VPSUBW ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000003433 62a11528f944db08 VPSUBW ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000343B 62a11528f944dbf8 VPSUBW ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000003443 62013d40f9c7 VPSUBW zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000003449 62613d40f903 VPSUBW zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000344F 62213d40f944db04 VPSUBW zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000003457 62213d40f944dbfc VPSUBW zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000345F c4e27917d0 VPTEST xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003464 c4e2791713 VPTEST xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003469 c4a2791794db00010000 VPTEST xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003473 c4a2791794db00ffffff VPTEST xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000347D c5c168d0 VPUNPCKHBW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000003481 c5c16813 VPUNPCKHBW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000003485 c4a1416894db00010000 VPUNPCKHBW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000348F c4a1416894db00ffffff VPUNPCKHBW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000003499 62c1152868c7 VPUNPCKHBW ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000349F 62e115286803 VPUNPCKHBW ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000034A5 62a115286844db08 VPUNPCKHBW ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000034AD 62a115286844dbf8 VPUNPCKHBW ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000034B5 62013d4068c7 VPUNPCKHBW zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000034BB 62613d406803 VPUNPCKHBW zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000034C1 62213d406844db04 VPUNPCKHBW zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000034C9 62213d406844dbfc VPUNPCKHBW zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000034D1 c5c16ad0 VPUNPCKHDQ xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000034D5 c5c16a13 VPUNPCKHDQ xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000034D9 c4a1416a94db00010000 VPUNPCKHDQ xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000034E3 c4a1416a94db00ffffff VPUNPCKHDQ xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000034ED 62c115286ac7 VPUNPCKHDQ ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000034F3 62e115286a03 VPUNPCKHDQ ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000034F9 62a115286a44db08 VPUNPCKHDQ ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000003501 62a115286a44dbf8 VPUNPCKHDQ ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000003509 62013d406ac7 VPUNPCKHDQ zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000350F 62613d406a03 VPUNPCKHDQ zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000003515 62213d406a44db04 VPUNPCKHDQ zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000351D 62213d406a44dbfc VPUNPCKHDQ zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000003525 c5c16dd0 VPUNPCKHQDQ xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000003529 c5c16d13 VPUNPCKHQDQ xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000352D c4a1416d94db00010000 VPUNPCKHQDQ xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000003537 c4a1416d94db00ffffff VPUNPCKHQDQ xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000003541 62c195286dc7 VPUNPCKHQDQ ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000003547 62e195286d03 VPUNPCKHQDQ ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000354D 62a195286d44db08 VPUNPCKHQDQ ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000003555 62a195286d44dbf8 VPUNPCKHQDQ ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000355D 6201bd406dc7 VPUNPCKHQDQ zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000003563 6261bd406d03 VPUNPCKHQDQ zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000003569 6221bd406d44db04 VPUNPCKHQDQ zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000003571 6221bd406d44dbfc VPUNPCKHQDQ zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000003579 c5c169d0 VPUNPCKHWD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000357D c5c16913 VPUNPCKHWD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000003581 c4a1416994db00010000 VPUNPCKHWD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000358B c4a1416994db00ffffff VPUNPCKHWD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000003595 62c1152869c7 VPUNPCKHWD ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000359B 62e115286903 VPUNPCKHWD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000035A1 62a115286944db08 VPUNPCKHWD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000035A9 62a115286944dbf8 VPUNPCKHWD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000035B1 62013d4069c7 VPUNPCKHWD zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000035B7 62613d406903 VPUNPCKHWD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000035BD 62213d406944db04 VPUNPCKHWD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000035C5 62213d406944dbfc VPUNPCKHWD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000035CD c5c160d0 VPUNPCKLBW xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000035D1 c5c16013 VPUNPCKLBW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000035D5 c4a1416094db00010000 VPUNPCKLBW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000035DF c4a1416094db00ffffff VPUNPCKLBW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000035E9 62c1152860c7 VPUNPCKLBW ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000035EF 62e115286003 VPUNPCKLBW ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000035F5 62a115286044db08 VPUNPCKLBW ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000035FD 62a115286044dbf8 VPUNPCKLBW ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000003605 62013d4060c7 VPUNPCKLBW zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000360B 62613d406003 VPUNPCKLBW zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000003611 62213d406044db04 VPUNPCKLBW zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000003619 62213d406044dbfc VPUNPCKLBW zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000003621 c5c162d0 VPUNPCKLDQ xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000003625 c5c16213 VPUNPCKLDQ xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000003629 c4a1416294db00010000 VPUNPCKLDQ xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000003633 c4a1416294db00ffffff VPUNPCKLDQ xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +000000000000363D 62c1152862c7 VPUNPCKLDQ ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000003643 62e115286203 VPUNPCKLDQ ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000003649 62a115286244db08 VPUNPCKLDQ ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000003651 62a115286244dbf8 VPUNPCKLDQ ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000003659 62013d4062c7 VPUNPCKLDQ zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000365F 62613d406203 VPUNPCKLDQ zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000003665 62213d406244db04 VPUNPCKLDQ zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000366D 62213d406244dbfc VPUNPCKLDQ zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000003675 c5c16cd0 VPUNPCKLQDQ xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000003679 c5c16c13 VPUNPCKLQDQ xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000367D c4a1416c94db00010000 VPUNPCKLQDQ xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000003687 c4a1416c94db00ffffff VPUNPCKLQDQ xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000003691 62c195286cc7 VPUNPCKLQDQ ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000003697 62e195286c03 VPUNPCKLQDQ ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000369D 62a195286c44db08 VPUNPCKLQDQ ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000036A5 62a195286c44dbf8 VPUNPCKLQDQ ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000036AD 6201bd406cc7 VPUNPCKLQDQ zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000036B3 6261bd406c03 VPUNPCKLQDQ zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000036B9 6221bd406c44db04 VPUNPCKLQDQ zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000036C1 6221bd406c44dbfc VPUNPCKLQDQ zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000036C9 c5c161d0 VPUNPCKLWD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000036CD c5c16113 VPUNPCKLWD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000036D1 c4a1416194db00010000 VPUNPCKLWD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000036DB c4a1416194db00ffffff VPUNPCKLWD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000036E5 62c1152861c7 VPUNPCKLWD ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000036EB 62e115286103 VPUNPCKLWD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000036F1 62a115286144db08 VPUNPCKLWD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000036F9 62a115286144dbf8 VPUNPCKLWD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000003701 62013d4061c7 VPUNPCKLWD zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000003707 62613d406103 VPUNPCKLWD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000370D 62213d406144db04 VPUNPCKLWD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000003715 62213d406144dbfc VPUNPCKLWD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000371D c5c1efd0 VPXOR xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000003721 c5c1ef13 VPXOR xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000003725 c4a141ef94db00010000 VPXOR xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000372F c4a141ef94db00ffffff VPXOR xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000003739 c5f853d0 VRCPPS xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000373D c5f85313 VRCPPS xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000003741 c4a1785394db00010000 VRCPPS xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000374B c4a1785394db00ffffff VRCPPS xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000003755 c5c253d0 VRCPSS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000003759 c5c25313 VRCPSS xmm2, xmm7, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +000000000000375D c4a1425394db00010000 VRCPSS xmm2, xmm7, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000003767 c4a1425394db00ffffff VRCPSS xmm2, xmm7, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000003771 c4e37909d090 VROUNDPD xmm2, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003777 c4e379091390 VROUNDPD xmm2, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000377D c4a3790994db0001000090 VROUNDPD xmm2, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003788 c4a3790994db00ffffff90 VROUNDPD xmm2, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003793 c4e37908d090 VROUNDPS xmm2, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003799 c4e379081390 VROUNDPS xmm2, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000379F c4a3790894db0001000090 VROUNDPS xmm2, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000037AA c4a3790894db00ffffff90 VROUNDPS xmm2, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000037B5 c4e3410bd090 VROUNDSD xmm2, xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000037BB c4e3410b1390 VROUNDSD xmm2, xmm7, qword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000037C1 c4a3410b94db0001000090 VROUNDSD xmm2, xmm7, qword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000037CC c4a3410b94db00ffffff90 VROUNDSD xmm2, xmm7, qword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000037D7 c4e3410ad090 VROUNDSS xmm2, xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000037DD c4e3410a1390 VROUNDSS xmm2, xmm7, dword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000037E3 c4a3410a94db0001000090 VROUNDSS xmm2, xmm7, dword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000037EE c4a3410a94db00ffffff90 VROUNDSS xmm2, xmm7, dword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000037F9 c5f852d0 VRSQRTPS xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000037FD c5f85213 VRSQRTPS xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000003801 c4a1785294db00010000 VRSQRTPS xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000380B c4a1785294db00ffffff VRSQRTPS xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000003815 c5c252d0 VRSQRTSS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000003819 c5c25213 VRSQRTSS xmm2, xmm7, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +000000000000381D c4a1425294db00010000 VRSQRTSS xmm2, xmm7, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000003827 c4a1425294db00ffffff VRSQRTSS xmm2, xmm7, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000003831 c5c1c6d090 VSHUFPD xmm2, xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003836 c5c1c61390 VSHUFPD xmm2, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000383B c4a141c694db0001000090 VSHUFPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003846 c4a141c694db00ffffff90 VSHUFPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003851 62c19528c6c790 VSHUFPD ymm16, ymm13, ymm15, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003858 62e19528c60390 VSHUFPD ymm16, ymm13, ymmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000385F 62a19528c644db0890 VSHUFPD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003868 62a19528c644dbf890 VSHUFPD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003871 6201bd40c6c790 VSHUFPD zmm24, zmm24, zmm31, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003878 6261bd40c60390 VSHUFPD zmm24, zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000387F 6221bd40c644db0490 VSHUFPD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003888 6221bd40c644dbfc90 VSHUFPD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003891 c5c0c6d090 VSHUFPS xmm2, xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003896 c5c0c61390 VSHUFPS xmm2, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000389B c4a140c694db0001000090 VSHUFPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000038A6 c4a140c694db00ffffff90 VSHUFPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000038B1 62c11428c6c790 VSHUFPS ymm16, ymm13, ymm15, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000038B8 62e11428c60390 VSHUFPS ymm16, ymm13, ymmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000038BF 62a11428c644db0890 VSHUFPS ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000038C8 62a11428c644dbf890 VSHUFPS ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000038D1 62013c40c6c790 VSHUFPS zmm24, zmm24, zmm31, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000038D8 62613c40c60390 VSHUFPS zmm24, zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000038DF 62213c40c644db0490 VSHUFPS zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000038E8 62213c40c644dbfc90 VSHUFPS zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000038F1 c5f951d0 VSQRTPD xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000038F5 c5f95113 VSQRTPD xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000038F9 c4a1795194db00010000 VSQRTPD xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000003903 c4a1795194db00ffffff VSQRTPD xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +000000000000390D 62c1fd2851c7 VSQRTPD ymm16, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000003913 62e1fd285103 VSQRTPD ymm16, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000003919 62a1fd285144db08 VSQRTPD ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000003921 62a1fd285144dbf8 VSQRTPD ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000003929 6201fd4851c7 VSQRTPD zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000392F 6261fd485103 VSQRTPD zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000003935 6221fd485144db04 VSQRTPD zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000393D 6221fd485144dbfc VSQRTPD zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000003945 c5f851d0 VSQRTPS xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000003949 c5f85113 VSQRTPS xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000394D c4a1785194db00010000 VSQRTPS xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000003957 c4a1785194db00ffffff VSQRTPS xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000003961 62c17c2851c7 VSQRTPS ymm16, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000003967 62e17c285103 VSQRTPS ymm16, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000396D 62a17c285144db08 VSQRTPS ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000003975 62a17c285144dbf8 VSQRTPS ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000397D 62017c4851c7 VSQRTPS zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000003983 62617c485103 VSQRTPS zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000003989 62217c485144db04 VSQRTPS zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000003991 62217c485144dbfc VSQRTPS zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000003999 c5c351d0 VSQRTSD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000399D c5c35113 VSQRTSD xmm2, xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000039A1 c4a1435194db00010000 VSQRTSD xmm2, xmm7, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000039AB c4a1435194db00ffffff VSQRTSD xmm2, xmm7, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000039B5 c5c251d0 VSQRTSS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000039B9 c5c25113 VSQRTSS xmm2, xmm7, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +00000000000039BD c4a1425194db00010000 VSQRTSS xmm2, xmm7, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000039C7 c4a1425194db00ffffff VSQRTSS xmm2, xmm7, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000039D1 c5f8ae1b VSTMXCSR dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: MXCSR, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000039D5 c5f8ae9cf300010000 VSTMXCSR dword ptr [rbx+rsi*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: MXCSR, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000039DE c5f8ae9cf300ffffff VSTMXCSR dword ptr [rbx+rsi*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: MXCSR, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000039E7 c5c15cd0 VSUBPD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000039EB c5c15c13 VSUBPD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000039EF c4a1415c94db00010000 VSUBPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000039F9 c4a1415c94db00ffffff VSUBPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000003A03 62c195285cc7 VSUBPD ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000003A09 62e195285c03 VSUBPD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000003A0F 62a195285c44db08 VSUBPD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000003A17 62a195285c44dbf8 VSUBPD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000003A1F 6201bd405cc7 VSUBPD zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000003A25 6261bd405c03 VSUBPD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000003A2B 6221bd405c44db04 VSUBPD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000003A33 6221bd405c44dbfc VSUBPD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000003A3B c5c05cd0 VSUBPS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000003A3F c5c05c13 VSUBPS xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000003A43 c4a1405c94db00010000 VSUBPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000003A4D c4a1405c94db00ffffff VSUBPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000003A57 62c114285cc7 VSUBPS ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000003A5D 62e114285c03 VSUBPS ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000003A63 62a114285c44db08 VSUBPS ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000003A6B 62a114285c44dbf8 VSUBPS ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000003A73 62013c405cc7 VSUBPS zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000003A79 62613c405c03 VSUBPS zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000003A7F 62213c405c44db04 VSUBPS zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000003A87 62213c405c44dbfc VSUBPS zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000003A8F c5c35cd0 VSUBSD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000003A93 c5c35c13 VSUBSD xmm2, xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000003A97 c4a1435c94db00010000 VSUBSD xmm2, xmm7, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000003AA1 c4a1435c94db00ffffff VSUBSD xmm2, xmm7, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000003AAB c5c25cd0 VSUBSS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000003AAF c5c25c13 VSUBSS xmm2, xmm7, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +0000000000003AB3 c4a1425c94db00010000 VSUBSS xmm2, xmm7, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000003ABD c4a1425c94db00ffffff VSUBSS xmm2, xmm7, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000003AC7 c4e2790fd0 VTESTPD xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003ACC c4e2790f13 VTESTPD xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003AD1 c4a2790f94db00010000 VTESTPD xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003ADB c4a2790f94db00ffffff VTESTPD xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003AE5 c4e2790ed0 VTESTPS xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003AEA c4e2790e13 VTESTPS xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003AEF c4a2790e94db00010000 VTESTPS xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003AF9 c4a2790e94db00ffffff VTESTPS xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003B03 c5f92ed0 VUCOMISD xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + FLAGS access + CF: m, PF: m, ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003B07 c5f92e13 VUCOMISD xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + FLAGS access + CF: m, PF: m, ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003B0B c4a1792e94db00010000 VUCOMISD xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + FLAGS access + CF: m, PF: m, ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003B15 c4a1792e94db00ffffff VUCOMISD xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + FLAGS access + CF: m, PF: m, ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003B1F c5f82ed0 VUCOMISS xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + FLAGS access + CF: m, PF: m, ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003B23 c5f82e13 VUCOMISS xmm2, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + FLAGS access + CF: m, PF: m, ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003B27 c4a1782e94db00010000 VUCOMISS xmm2, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + FLAGS access + CF: m, PF: m, ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003B31 c4a1782e94db00ffffff VUCOMISS xmm2, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 3 + FLAGS access + CF: m, PF: m, ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003B3B c5c115d0 VUNPCKHPD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000003B3F c5c11513 VUNPCKHPD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000003B43 c4a1411594db00010000 VUNPCKHPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000003B4D c4a1411594db00ffffff VUNPCKHPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000003B57 62c1952815c7 VUNPCKHPD ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000003B5D 62e195281503 VUNPCKHPD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000003B63 62a195281544db08 VUNPCKHPD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000003B6B 62a195281544dbf8 VUNPCKHPD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000003B73 6201bd4015c7 VUNPCKHPD zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000003B79 6261bd401503 VUNPCKHPD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000003B7F 6221bd401544db04 VUNPCKHPD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000003B87 6221bd401544dbfc VUNPCKHPD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000003B8F c5c015d0 VUNPCKHPS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000003B93 c5c01513 VUNPCKHPS xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000003B97 c4a1401594db00010000 VUNPCKHPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000003BA1 c4a1401594db00ffffff VUNPCKHPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000003BAB 62c1142815c7 VUNPCKHPS ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000003BB1 62e114281503 VUNPCKHPS ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000003BB7 62a114281544db08 VUNPCKHPS ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000003BBF 62a114281544dbf8 VUNPCKHPS ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000003BC7 62013c4015c7 VUNPCKHPS zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000003BCD 62613c401503 VUNPCKHPS zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000003BD3 62213c401544db04 VUNPCKHPS zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000003BDB 62213c401544dbfc VUNPCKHPS zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000003BE3 c5c114d0 VUNPCKLPD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000003BE7 c5c11413 VUNPCKLPD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000003BEB c4a1411494db00010000 VUNPCKLPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000003BF5 c4a1411494db00ffffff VUNPCKLPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000003BFF 62c1952814c7 VUNPCKLPD ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000003C05 62e195281403 VUNPCKLPD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000003C0B 62a195281444db08 VUNPCKLPD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000003C13 62a195281444dbf8 VUNPCKLPD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000003C1B 6201bd4014c7 VUNPCKLPD zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000003C21 6261bd401403 VUNPCKLPD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000003C27 6221bd401444db04 VUNPCKLPD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000003C2F 6221bd401444dbfc VUNPCKLPD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000003C37 c5c014d0 VUNPCKLPS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000003C3B c5c01413 VUNPCKLPS xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000003C3F c4a1401494db00010000 VUNPCKLPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000003C49 c4a1401494db00ffffff VUNPCKLPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000003C53 62c1142814c7 VUNPCKLPS ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000003C59 62e114281403 VUNPCKLPS ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000003C5F 62a114281444db08 VUNPCKLPS ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000003C67 62a114281444dbf8 VUNPCKLPS ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000003C6F 62013c4014c7 VUNPCKLPS zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000003C75 62613c401403 VUNPCKLPS zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000003C7B 62213c401444db04 VUNPCKLPS zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000003C83 62213c401444dbfc VUNPCKLPS zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512F, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000003C8B c5c157d0 VXORPD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000003C8F c5c15713 VXORPD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000003C93 c4a1415794db00010000 VXORPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000003C9D c4a1415794db00ffffff VXORPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000003CA7 62c1952857c7 VXORPD ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000003CAD 62e195285703 VXORPD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000003CB3 62a195285744db08 VXORPD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000003CBB 62a195285744dbf8 VXORPD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000003CC3 6201bd4057c7 VXORPD zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000003CC9 6261bd405703 VXORPD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000003CCF 6221bd405744db04 VXORPD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000003CD7 6221bd405744dbfc VXORPD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000003CDF c5c057d0 VXORPS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000003CE3 c5c05713 VXORPS xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000003CE7 c4a1405794db00010000 VXORPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000003CF1 c4a1405794db00ffffff VXORPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000003CFB 62c1142857c7 VXORPS ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000003D01 62e114285703 VXORPS ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000003D07 62a114285744db08 VXORPS ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000003D0F 62a114285744dbf8 VXORPS ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000003D17 62013c4057c7 VXORPS zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000003D1D 62613c405703 VXORPS zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000003D23 62213c405744db04 VXORPS zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000003D2B 62213c405744dbfc VXORPS zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + diff --git a/bddisasm_test/avx/f16c_64 b/bddisasm_test/avx/f16c_64 new file mode 100644 index 0000000..dc45785 --- /dev/null +++ b/bddisasm_test/avx/f16c_64 @@ -0,0 +1,4 @@ +y}y +} +y;};y; +}; diff --git a/bddisasm_test/avx/f16c_64.asm b/bddisasm_test/avx/f16c_64.asm new file mode 100644 index 0000000..c537f09 --- /dev/null +++ b/bddisasm_test/avx/f16c_64.asm @@ -0,0 +1,11 @@ + bits 64 + + vcvtph2ps xmm7,xmm13 + vcvtph2ps ymm7,xmm13 + vcvtps2ph xmm13,xmm7,10 + vcvtps2ph xmm13,ymm7,10 + + vcvtph2ps xmm7,[rbx] + vcvtph2ps ymm7,[rbx] + vcvtps2ph [rbx],xmm7,10 + vcvtps2ph [rbx],ymm7,10 \ No newline at end of file diff --git a/bddisasm_test/avx/f16c_64.result b/bddisasm_test/avx/f16c_64.result new file mode 100644 index 0000000..feb173a --- /dev/null +++ b/bddisasm_test/avx/f16c_64.result @@ -0,0 +1,136 @@ +0000000000000000 c4c27913fd VCVTPH2PS xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: F16C, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 29 + Exception class: SSE/VEX, exception type: 11 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000005 c4c27d13fd VCVTPH2PS ymm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: F16C, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 29 + Exception class: SSE/VEX, exception type: 11 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000000A c4c3791dfd0a VCVTPS2PH xmm13, xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: F16C, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 29 + Exception class: SSE/VEX, exception type: 11 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000010 c4c37d1dfd0a VCVTPS2PH xmm13, ymm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: F16C, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 29 + Exception class: SSE/VEX, exception type: 11 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000016 c4e279133b VCVTPH2PS xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: F16C, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 29 + Exception class: SSE/VEX, exception type: 11 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000001B c4e27d133b VCVTPH2PS ymm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: F16C, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 29 + Exception class: SSE/VEX, exception type: 11 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000020 c4e3791d3b0a VCVTPS2PH qword ptr [rbx], xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: F16C, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 29 + Exception class: SSE/VEX, exception type: 11 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000026 c4e37d1d3b0a VCVTPS2PH xmmword ptr [rbx], ymm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: F16C, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 29 + Exception class: SSE/VEX, exception type: 11 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + diff --git a/bddisasm_test/avx/fma4_64 b/bddisasm_test/avx/fma4_64 new file mode 100644 index 0000000..37196ee --- /dev/null +++ b/bddisasm_test/avx/fma4_64 @@ -0,0 +1 @@ +\\]]^^__hhiijjkkllmmnnooxxyyzz{{||}}~~\;\;];];^;^;_;_;h;h;i;i;j;j;k;k;l;l;m;m;n;n;o;o;x;x;y;y;z;z;{;{;|;|;};};~;~;;;\\]]^^__hhiillmmxxyy||}}\;\;];];^;^;_;_;h;h;i;i;l;l;m;m;x;x;y;y;|;|;};}; \ No newline at end of file diff --git a/bddisasm_test/avx/fma4_64.asm b/bddisasm_test/avx/fma4_64.asm new file mode 100644 index 0000000..5486660 --- /dev/null +++ b/bddisasm_test/avx/fma4_64.asm @@ -0,0 +1,133 @@ + bits 64 + + vfmaddsubps xmm7,xmm15,xmm13,xmm8 + vfmaddsubps xmm7,xmm15,xmm8,xmm13 + vfmaddsubpd xmm7,xmm15,xmm13,xmm8 + vfmaddsubpd xmm7,xmm15,xmm8,xmm13 + vfmsubaddps xmm7,xmm15,xmm13,xmm8 + vfmsubaddps xmm7,xmm15,xmm8,xmm13 + vfmsubaddpd xmm7,xmm15,xmm13,xmm8 + vfmsubaddpd xmm7,xmm15,xmm8,xmm13 + vfmaddps xmm7,xmm15,xmm13,xmm8 + vfmaddps xmm7,xmm15,xmm8,xmm13 + vfmaddpd xmm7,xmm15,xmm13,xmm8 + vfmaddpd xmm7,xmm15,xmm8,xmm13 + vfmaddss xmm7,xmm15,xmm13,xmm8 + vfmaddss xmm7,xmm15,xmm8,xmm13 + vfmaddsd xmm7,xmm15,xmm13,xmm8 + vfmaddsd xmm7,xmm15,xmm8,xmm13 + vfmsubps xmm7,xmm15,xmm13,xmm8 + vfmsubps xmm7,xmm15,xmm8,xmm13 + vfmsubpd xmm7,xmm15,xmm13,xmm8 + vfmsubpd xmm7,xmm15,xmm8,xmm13 + vfmsubss xmm7,xmm15,xmm13,xmm8 + vfmsubss xmm7,xmm15,xmm8,xmm13 + vfmsubsd xmm7,xmm15,xmm13,xmm8 + vfmsubsd xmm7,xmm15,xmm8,xmm13 + vfnmaddps xmm7,xmm15,xmm13,xmm8 + vfnmaddps xmm7,xmm15,xmm8,xmm13 + vfnmaddpd xmm7,xmm15,xmm13,xmm8 + vfnmaddpd xmm7,xmm15,xmm8,xmm13 + vfnmaddss xmm7,xmm15,xmm13,xmm8 + vfnmaddss xmm7,xmm15,xmm8,xmm13 + vfnmaddsd xmm7,xmm15,xmm13,xmm8 + vfnmaddsd xmm7,xmm15,xmm8,xmm13 + vfnmsubps xmm7,xmm15,xmm13,xmm8 + vfnmsubps xmm7,xmm15,xmm8,xmm13 + vfnmsubpd xmm7,xmm15,xmm13,xmm8 + vfnmsubpd xmm7,xmm15,xmm8,xmm13 + vfnmsubss xmm7,xmm15,xmm13,xmm8 + vfnmsubss xmm7,xmm15,xmm8,xmm13 + vfnmsubsd xmm7,xmm15,xmm13,xmm8 + vfnmsubsd xmm7,xmm15,xmm8,xmm13 + + vfmaddsubps xmm7,xmm15,[rbx],xmm8 + vfmaddsubps xmm7,xmm15,xmm8,[rbx] + vfmaddsubpd xmm7,xmm15,[rbx],xmm8 + vfmaddsubpd xmm7,xmm15,xmm8,[rbx] + vfmsubaddps xmm7,xmm15,[rbx],xmm8 + vfmsubaddps xmm7,xmm15,xmm8,[rbx] + vfmsubaddpd xmm7,xmm15,[rbx],xmm8 + vfmsubaddpd xmm7,xmm15,xmm8,[rbx] + vfmaddps xmm7,xmm15,[rbx],xmm8 + vfmaddps xmm7,xmm15,xmm8,[rbx] + vfmaddpd xmm7,xmm15,[rbx],xmm8 + vfmaddpd xmm7,xmm15,xmm8,[rbx] + vfmaddss xmm7,xmm15,[rbx],xmm8 + vfmaddss xmm7,xmm15,xmm8,[rbx] + vfmaddsd xmm7,xmm15,[rbx],xmm8 + vfmaddsd xmm7,xmm15,xmm8,[rbx] + vfmsubps xmm7,xmm15,[rbx],xmm8 + vfmsubps xmm7,xmm15,xmm8,[rbx] + vfmsubpd xmm7,xmm15,[rbx],xmm8 + vfmsubpd xmm7,xmm15,xmm8,[rbx] + vfmsubss xmm7,xmm15,[rbx],xmm8 + vfmsubss xmm7,xmm15,xmm8,[rbx] + vfmsubsd xmm7,xmm15,[rbx],xmm8 + vfmsubsd xmm7,xmm15,xmm8,[rbx] + vfnmaddps xmm7,xmm15,[rbx],xmm8 + vfnmaddps xmm7,xmm15,xmm8,[rbx] + vfnmaddpd xmm7,xmm15,[rbx],xmm8 + vfnmaddpd xmm7,xmm15,xmm8,[rbx] + vfnmaddss xmm7,xmm15,[rbx],xmm8 + vfnmaddss xmm7,xmm15,xmm8,[rbx] + vfnmaddsd xmm7,xmm15,[rbx],xmm8 + vfnmaddsd xmm7,xmm15,xmm8,[rbx] + vfnmsubps xmm7,xmm15,[rbx],xmm8 + vfnmsubps xmm7,xmm15,xmm8,[rbx] + vfnmsubpd xmm7,xmm15,[rbx],xmm8 + vfnmsubpd xmm7,xmm15,xmm8,[rbx] + vfnmsubss xmm7,xmm15,[rbx],xmm8 + vfnmsubss xmm7,xmm15,xmm8,[rbx] + vfnmsubsd xmm7,xmm15,[rbx],xmm8 + vfnmsubsd xmm7,xmm15,xmm8,[rbx] + + vfmaddsubps ymm7,ymm15,ymm13,ymm8 + vfmaddsubps ymm7,ymm15,ymm8,ymm13 + vfmaddsubpd ymm7,ymm15,ymm13,ymm8 + vfmaddsubpd ymm7,ymm15,ymm8,ymm13 + vfmsubaddps ymm7,ymm15,ymm13,ymm8 + vfmsubaddps ymm7,ymm15,ymm8,ymm13 + vfmsubaddpd ymm7,ymm15,ymm13,ymm8 + vfmsubaddpd ymm7,ymm15,ymm8,ymm13 + vfmaddps ymm7,ymm15,ymm13,ymm8 + vfmaddps ymm7,ymm15,ymm8,ymm13 + vfmaddpd ymm7,ymm15,ymm13,ymm8 + vfmaddpd ymm7,ymm15,ymm8,ymm13 + vfmsubps ymm7,ymm15,ymm13,ymm8 + vfmsubps ymm7,ymm15,ymm8,ymm13 + vfmsubpd ymm7,ymm15,ymm13,ymm8 + vfmsubpd ymm7,ymm15,ymm8,ymm13 + vfnmaddps ymm7,ymm15,ymm13,ymm8 + vfnmaddps ymm7,ymm15,ymm8,ymm13 + vfnmaddpd ymm7,ymm15,ymm13,ymm8 + vfnmaddpd ymm7,ymm15,ymm8,ymm13 + vfnmsubps ymm7,ymm15,ymm13,ymm8 + vfnmsubps ymm7,ymm15,ymm8,ymm13 + vfnmsubpd ymm7,ymm15,ymm13,ymm8 + vfnmsubpd ymm7,ymm15,ymm8,ymm13 + + vfmaddsubps ymm7,ymm15,[rbx],ymm8 + vfmaddsubps ymm7,ymm15,ymm8,[rbx] + vfmaddsubpd ymm7,ymm15,[rbx],ymm8 + vfmaddsubpd ymm7,ymm15,ymm8,[rbx] + vfmsubaddps ymm7,ymm15,[rbx],ymm8 + vfmsubaddps ymm7,ymm15,ymm8,[rbx] + vfmsubaddpd ymm7,ymm15,[rbx],ymm8 + vfmsubaddpd ymm7,ymm15,ymm8,[rbx] + vfmaddps ymm7,ymm15,[rbx],ymm8 + vfmaddps ymm7,ymm15,ymm8,[rbx] + vfmaddpd ymm7,ymm15,[rbx],ymm8 + vfmaddpd ymm7,ymm15,ymm8,[rbx] + vfmsubps ymm7,ymm15,[rbx],ymm8 + vfmsubps ymm7,ymm15,ymm8,[rbx] + vfmsubpd ymm7,ymm15,[rbx],ymm8 + vfmsubpd ymm7,ymm15,ymm8,[rbx] + vfnmaddps ymm7,ymm15,[rbx],ymm8 + vfnmaddps ymm7,ymm15,ymm8,[rbx] + vfnmaddpd ymm7,ymm15,[rbx],ymm8 + vfnmaddpd ymm7,ymm15,ymm8,[rbx] + vfnmsubps ymm7,ymm15,[rbx],ymm8 + vfnmsubps ymm7,ymm15,ymm8,[rbx] + vfnmsubpd ymm7,ymm15,[rbx],ymm8 + vfnmsubpd ymm7,ymm15,ymm8,[rbx] diff --git a/bddisasm_test/avx/fma4_64.result b/bddisasm_test/avx/fma4_64.result new file mode 100644 index 0000000..4502976 --- /dev/null +++ b/bddisasm_test/avx/fma4_64.result @@ -0,0 +1,2240 @@ +0000000000000000 c4c3015cfd80 VFMADDSUBPS xmm7, xmm15, xmm13, xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +0000000000000006 c4c3015cf8d0 VFMADDSUBPS xmm7, xmm15, xmm8, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000000C c4c3015dfd80 VFMADDSUBPD xmm7, xmm15, xmm13, xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +0000000000000012 c4c3015df8d0 VFMADDSUBPD xmm7, xmm15, xmm8, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000018 c4c3015efd80 VFMSUBADDPS xmm7, xmm15, xmm13, xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +000000000000001E c4c3015ef8d0 VFMSUBADDPS xmm7, xmm15, xmm8, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000024 c4c3015ffd80 VFMSUBADDPD xmm7, xmm15, xmm13, xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +000000000000002A c4c3015ff8d0 VFMSUBADDPD xmm7, xmm15, xmm8, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000030 c4c30168fd80 VFMADDPS xmm7, xmm15, xmm13, xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +0000000000000036 c4c30168f8d0 VFMADDPS xmm7, xmm15, xmm8, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000003C c4c30169fd80 VFMADDPD xmm7, xmm15, xmm13, xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +0000000000000042 c4c30169f8d0 VFMADDPD xmm7, xmm15, xmm8, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000048 c4c3016afd80 VFMADDSS xmm7, xmm15, xmm13, xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +000000000000004E c4c3016af8d0 VFMADDSS xmm7, xmm15, xmm8, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000054 c4c3016bfd80 VFMADDSD xmm7, xmm15, xmm13, xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +000000000000005A c4c3016bf8d0 VFMADDSD xmm7, xmm15, xmm8, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000060 c4c3016cfd80 VFMSUBPS xmm7, xmm15, xmm13, xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +0000000000000066 c4c3016cf8d0 VFMSUBPS xmm7, xmm15, xmm8, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000006C c4c3016dfd80 VFMSUBPD xmm7, xmm15, xmm13, xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +0000000000000072 c4c3016df8d0 VFMSUBPD xmm7, xmm15, xmm8, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000078 c4c3016efd80 VFMSUBSS xmm7, xmm15, xmm13, xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +000000000000007E c4c3016ef8d0 VFMSUBSS xmm7, xmm15, xmm8, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000084 c4c3016ffd80 VFMSUBSD xmm7, xmm15, xmm13, xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +000000000000008A c4c3016ff8d0 VFMSUBSD xmm7, xmm15, xmm8, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000090 c4c30178fd80 VFNMADDPS xmm7, xmm15, xmm13, xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +0000000000000096 c4c30178f8d0 VFNMADDPS xmm7, xmm15, xmm8, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000009C c4c30179fd80 VFNMADDPD xmm7, xmm15, xmm13, xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +00000000000000A2 c4c30179f8d0 VFNMADDPD xmm7, xmm15, xmm8, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000A8 c4c3017afd80 VFNMADDSS xmm7, xmm15, xmm13, xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +00000000000000AE c4c3017af8d0 VFNMADDSS xmm7, xmm15, xmm8, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000B4 c4c3017bfd80 VFNMADDSD xmm7, xmm15, xmm13, xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +00000000000000BA c4c3017bf8d0 VFNMADDSD xmm7, xmm15, xmm8, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000C0 c4c3017cfd80 VFNMSUBPS xmm7, xmm15, xmm13, xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +00000000000000C6 c4c3017cf8d0 VFNMSUBPS xmm7, xmm15, xmm8, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000CC c4c3017dfd80 VFNMSUBPD xmm7, xmm15, xmm13, xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +00000000000000D2 c4c3017df8d0 VFNMSUBPD xmm7, xmm15, xmm8, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000D8 c4c3017efd80 VFNMSUBSS xmm7, xmm15, xmm13, xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +00000000000000DE c4c3017ef8d0 VFNMSUBSS xmm7, xmm15, xmm8, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000E4 c4c3017ffd80 VFNMSUBSD xmm7, xmm15, xmm13, xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +00000000000000EA c4c3017ff8d0 VFNMSUBSD xmm7, xmm15, xmm8, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000F0 c4e3015c3b80 VFMADDSUBPS xmm7, xmm15, xmmword ptr [rbx], xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +00000000000000F6 c4e3815c3b80 VFMADDSUBPS xmm7, xmm15, xmm8, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000000FC c4e3015d3b80 VFMADDSUBPD xmm7, xmm15, xmmword ptr [rbx], xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +0000000000000102 c4e3815d3b80 VFMADDSUBPD xmm7, xmm15, xmm8, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000108 c4e3015e3b80 VFMSUBADDPS xmm7, xmm15, xmmword ptr [rbx], xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +000000000000010E c4e3815e3b80 VFMSUBADDPS xmm7, xmm15, xmm8, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000114 c4e3015f3b80 VFMSUBADDPD xmm7, xmm15, xmmword ptr [rbx], xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +000000000000011A c4e3815f3b80 VFMSUBADDPD xmm7, xmm15, xmm8, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000120 c4e301683b80 VFMADDPS xmm7, xmm15, xmmword ptr [rbx], xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +0000000000000126 c4e381683b80 VFMADDPS xmm7, xmm15, xmm8, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000012C c4e301693b80 VFMADDPD xmm7, xmm15, xmmword ptr [rbx], xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +0000000000000132 c4e381693b80 VFMADDPD xmm7, xmm15, xmm8, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000138 c4e3016a3b80 VFMADDSS xmm7, xmm15, dword ptr [rbx], xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +000000000000013E c4e3816a3b80 VFMADDSS xmm7, xmm15, xmm8, dword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +0000000000000144 c4e3016b3b80 VFMADDSD xmm7, xmm15, qword ptr [rbx], xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +000000000000014A c4e3816b3b80 VFMADDSD xmm7, xmm15, xmm8, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000150 c4e3016c3b80 VFMSUBPS xmm7, xmm15, xmmword ptr [rbx], xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +0000000000000156 c4e3816c3b80 VFMSUBPS xmm7, xmm15, xmm8, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000015C c4e3016d3b80 VFMSUBPD xmm7, xmm15, xmmword ptr [rbx], xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +0000000000000162 c4e3816d3b80 VFMSUBPD xmm7, xmm15, xmm8, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000168 c4e3016e3b80 VFMSUBSS xmm7, xmm15, dword ptr [rbx], xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +000000000000016E c4e3816e3b80 VFMSUBSS xmm7, xmm15, xmm8, dword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +0000000000000174 c4e3016f3b80 VFMSUBSD xmm7, xmm15, qword ptr [rbx], xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +000000000000017A c4e3816f3b80 VFMSUBSD xmm7, xmm15, xmm8, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000180 c4e301783b80 VFNMADDPS xmm7, xmm15, xmmword ptr [rbx], xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +0000000000000186 c4e381783b80 VFNMADDPS xmm7, xmm15, xmm8, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000018C c4e301793b80 VFNMADDPD xmm7, xmm15, xmmword ptr [rbx], xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +0000000000000192 c4e381793b80 VFNMADDPD xmm7, xmm15, xmm8, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000198 c4e3017a3b80 VFNMADDSS xmm7, xmm15, dword ptr [rbx], xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +000000000000019E c4e3817a3b80 VFNMADDSS xmm7, xmm15, xmm8, dword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +00000000000001A4 c4e3017b3b80 VFNMADDSD xmm7, xmm15, qword ptr [rbx], xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +00000000000001AA c4e3817b3b80 VFNMADDSD xmm7, xmm15, xmm8, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000001B0 c4e3017c3b80 VFNMSUBPS xmm7, xmm15, xmmword ptr [rbx], xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +00000000000001B6 c4e3817c3b80 VFNMSUBPS xmm7, xmm15, xmm8, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000001BC c4e3017d3b80 VFNMSUBPD xmm7, xmm15, xmmword ptr [rbx], xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +00000000000001C2 c4e3817d3b80 VFNMSUBPD xmm7, xmm15, xmm8, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000001C8 c4e3017e3b80 VFNMSUBSS xmm7, xmm15, dword ptr [rbx], xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +00000000000001CE c4e3817e3b80 VFNMSUBSS xmm7, xmm15, xmm8, dword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +00000000000001D4 c4e3017f3b80 VFNMSUBSD xmm7, xmm15, qword ptr [rbx], xmm8 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + +00000000000001DA c4e3817f3b80 VFNMSUBSD xmm7, xmm15, xmm8, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: L, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000001E0 c4c3055cfd80 VFMADDSUBPS ymm7, ymm15, ymm13, ymm8 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + +00000000000001E6 c4c3055cf8d0 VFMADDSUBPS ymm7, ymm15, ymm8, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +00000000000001EC c4c3055dfd80 VFMADDSUBPD ymm7, ymm15, ymm13, ymm8 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + +00000000000001F2 c4c3055df8d0 VFMADDSUBPD ymm7, ymm15, ymm8, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +00000000000001F8 c4c3055efd80 VFMSUBADDPS ymm7, ymm15, ymm13, ymm8 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + +00000000000001FE c4c3055ef8d0 VFMSUBADDPS ymm7, ymm15, ymm8, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +0000000000000204 c4c3055ffd80 VFMSUBADDPD ymm7, ymm15, ymm13, ymm8 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + +000000000000020A c4c3055ff8d0 VFMSUBADDPD ymm7, ymm15, ymm8, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +0000000000000210 c4c30568fd80 VFMADDPS ymm7, ymm15, ymm13, ymm8 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + +0000000000000216 c4c30568f8d0 VFMADDPS ymm7, ymm15, ymm8, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +000000000000021C c4c30569fd80 VFMADDPD ymm7, ymm15, ymm13, ymm8 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + +0000000000000222 c4c30569f8d0 VFMADDPD ymm7, ymm15, ymm8, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +0000000000000228 c4c3056cfd80 VFMSUBPS ymm7, ymm15, ymm13, ymm8 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + +000000000000022E c4c3056cf8d0 VFMSUBPS ymm7, ymm15, ymm8, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +0000000000000234 c4c3056dfd80 VFMSUBPD ymm7, ymm15, ymm13, ymm8 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + +000000000000023A c4c3056df8d0 VFMSUBPD ymm7, ymm15, ymm8, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +0000000000000240 c4c30578fd80 VFNMADDPS ymm7, ymm15, ymm13, ymm8 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + +0000000000000246 c4c30578f8d0 VFNMADDPS ymm7, ymm15, ymm8, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +000000000000024C c4c30579fd80 VFNMADDPD ymm7, ymm15, ymm13, ymm8 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + +0000000000000252 c4c30579f8d0 VFNMADDPD ymm7, ymm15, ymm8, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +0000000000000258 c4c3057cfd80 VFNMSUBPS ymm7, ymm15, ymm13, ymm8 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + +000000000000025E c4c3057cf8d0 VFNMSUBPS ymm7, ymm15, ymm8, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +0000000000000264 c4c3057dfd80 VFNMSUBPD ymm7, ymm15, ymm13, ymm8 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + +000000000000026A c4c3057df8d0 VFNMSUBPD ymm7, ymm15, ymm8, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +0000000000000270 c4e3055c3b80 VFMADDSUBPS ymm7, ymm15, ymmword ptr [rbx], ymm8 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + +0000000000000276 c4e3855c3b80 VFMADDSUBPS ymm7, ymm15, ymm8, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000027C c4e3055d3b80 VFMADDSUBPD ymm7, ymm15, ymmword ptr [rbx], ymm8 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + +0000000000000282 c4e3855d3b80 VFMADDSUBPD ymm7, ymm15, ymm8, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000288 c4e3055e3b80 VFMSUBADDPS ymm7, ymm15, ymmword ptr [rbx], ymm8 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + +000000000000028E c4e3855e3b80 VFMSUBADDPS ymm7, ymm15, ymm8, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000294 c4e3055f3b80 VFMSUBADDPD ymm7, ymm15, ymmword ptr [rbx], ymm8 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + +000000000000029A c4e3855f3b80 VFMSUBADDPD ymm7, ymm15, ymm8, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000002A0 c4e305683b80 VFMADDPS ymm7, ymm15, ymmword ptr [rbx], ymm8 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + +00000000000002A6 c4e385683b80 VFMADDPS ymm7, ymm15, ymm8, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000002AC c4e305693b80 VFMADDPD ymm7, ymm15, ymmword ptr [rbx], ymm8 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + +00000000000002B2 c4e385693b80 VFMADDPD ymm7, ymm15, ymm8, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000002B8 c4e3056c3b80 VFMSUBPS ymm7, ymm15, ymmword ptr [rbx], ymm8 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + +00000000000002BE c4e3856c3b80 VFMSUBPS ymm7, ymm15, ymm8, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000002C4 c4e3056d3b80 VFMSUBPD ymm7, ymm15, ymmword ptr [rbx], ymm8 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + +00000000000002CA c4e3856d3b80 VFMSUBPD ymm7, ymm15, ymm8, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000002D0 c4e305783b80 VFNMADDPS ymm7, ymm15, ymmword ptr [rbx], ymm8 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + +00000000000002D6 c4e385783b80 VFNMADDPS ymm7, ymm15, ymm8, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000002DC c4e305793b80 VFNMADDPD ymm7, ymm15, ymmword ptr [rbx], ymm8 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + +00000000000002E2 c4e385793b80 VFNMADDPD ymm7, ymm15, ymm8, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000002E8 c4e3057c3b80 VFNMSUBPS ymm7, ymm15, ymmword ptr [rbx], ymm8 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + +00000000000002EE c4e3857c3b80 VFNMSUBPS ymm7, ymm15, ymm8, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000002F4 c4e3057d3b80 VFNMSUBPD ymm7, ymm15, ymmword ptr [rbx], ymm8 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + +00000000000002FA c4e3857d3b80 VFNMSUBPD ymm7, ymm15, ymm8, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA4, Ins cat: FMA4, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: L, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + diff --git a/bddisasm_test/avx/fma_64 b/bddisasm_test/avx/fma_64 new file mode 100644 index 0000000..a83c345 --- /dev/null +++ b/bddisasm_test/avx/fma_64 @@ -0,0 +1 @@ +;⁖;;⁗;;⁘;;⁙;;⁚;;⁛;;⁜;;⁝;;⁞;; ;;⁦;;⁧;;⁨;;⁩;;;;;;;;;;;;;;⁶;;⁷;;⁸;;⁹;;⁺;;⁻;;⁼;;⁽;;⁾;;ⁿ;………………………………………………;⅖;;⅗;;⅘;;⅚;;⅜;;⅞;;Ⅶ;;Ⅷ;;Ⅸ;;Ⅺ;;Ⅼ;;Ⅾ;;ⅶ;;ⅷ;;ⅸ;;ⅺ;;ⅼ;;ⅾ; \ No newline at end of file diff --git a/bddisasm_test/avx/fma_64.asm b/bddisasm_test/avx/fma_64.asm new file mode 100644 index 0000000..d974731 --- /dev/null +++ b/bddisasm_test/avx/fma_64.asm @@ -0,0 +1,198 @@ + bits 64 + + vfmaddsub132ps xmm7,xmm15,xmm13 + vfmaddsub132pd xmm7,xmm15,xmm13 + vfmsubadd132ps xmm7,xmm15,xmm13 + vfmsubadd132pd xmm7,xmm15,xmm13 + vfmadd132ps xmm7,xmm15,xmm13 + vfmadd132pd xmm7,xmm15,xmm13 + vfmadd132ss xmm7,xmm15,xmm13 + vfmadd132sd xmm7,xmm15,xmm13 + vfmsub132ps xmm7,xmm15,xmm13 + vfmsub132pd xmm7,xmm15,xmm13 + vfmsub132ss xmm7,xmm15,xmm13 + vfmsub132sd xmm7,xmm15,xmm13 + vfnmadd132ps xmm7,xmm15,xmm13 + vfnmadd132pd xmm7,xmm15,xmm13 + vfnmadd132ss xmm7,xmm15,xmm13 + vfnmadd132sd xmm7,xmm15,xmm13 + vfnmsub132ps xmm7,xmm15,xmm13 + vfnmsub132pd xmm7,xmm15,xmm13 + vfnmsub132ss xmm7,xmm15,xmm13 + vfnmsub132sd xmm7,xmm15,xmm13 + vfmaddsub213ps xmm7,xmm15,xmm13 + vfmaddsub213pd xmm7,xmm15,xmm13 + vfmsubadd213ps xmm7,xmm15,xmm13 + vfmsubadd213pd xmm7,xmm15,xmm13 + vfmadd213ps xmm7,xmm15,xmm13 + vfmadd213pd xmm7,xmm15,xmm13 + vfmadd213ss xmm7,xmm15,xmm13 + vfmadd213sd xmm7,xmm15,xmm13 + vfmsub213ps xmm7,xmm15,xmm13 + vfmsub213pd xmm7,xmm15,xmm13 + vfmsub213ss xmm7,xmm15,xmm13 + vfmsub213sd xmm7,xmm15,xmm13 + vfnmadd213ps xmm7,xmm15,xmm13 + vfnmadd213pd xmm7,xmm15,xmm13 + vfnmadd213ss xmm7,xmm15,xmm13 + vfnmadd213sd xmm7,xmm15,xmm13 + vfnmsub213ps xmm7,xmm15,xmm13 + vfnmsub213pd xmm7,xmm15,xmm13 + vfnmsub213ss xmm7,xmm15,xmm13 + vfnmsub213sd xmm7,xmm15,xmm13 + vfmaddsub231ps xmm7,xmm15,xmm13 + vfmaddsub231pd xmm7,xmm15,xmm13 + vfmsubadd231ps xmm7,xmm15,xmm13 + vfmsubadd231pd xmm7,xmm15,xmm13 + vfmadd231ps xmm7,xmm15,xmm13 + vfmadd231pd xmm7,xmm15,xmm13 + vfmadd231ss xmm7,xmm15,xmm13 + vfmadd231sd xmm7,xmm15,xmm13 + vfmsub231ps xmm7,xmm15,xmm13 + vfmsub231pd xmm7,xmm15,xmm13 + vfmsub231ss xmm7,xmm15,xmm13 + vfmsub231sd xmm7,xmm15,xmm13 + vfnmadd231ps xmm7,xmm15,xmm13 + vfnmadd231pd xmm7,xmm15,xmm13 + vfnmadd231ss xmm7,xmm15,xmm13 + vfnmadd231sd xmm7,xmm15,xmm13 + vfnmsub231ps xmm7,xmm15,xmm13 + vfnmsub231pd xmm7,xmm15,xmm13 + vfnmsub231ss xmm7,xmm15,xmm13 + vfnmsub231sd xmm7,xmm15,xmm13 + + vfmaddsub132ps xmm7,xmm15,[rbx] + vfmaddsub132pd xmm7,xmm15,[rbx] + vfmsubadd132ps xmm7,xmm15,[rbx] + vfmsubadd132pd xmm7,xmm15,[rbx] + vfmadd132ps xmm7,xmm15,[rbx] + vfmadd132pd xmm7,xmm15,[rbx] + vfmadd132ss xmm7,xmm15,[rbx] + vfmadd132sd xmm7,xmm15,[rbx] + vfmsub132ps xmm7,xmm15,[rbx] + vfmsub132pd xmm7,xmm15,[rbx] + vfmsub132ss xmm7,xmm15,[rbx] + vfmsub132sd xmm7,xmm15,[rbx] + vfnmadd132ps xmm7,xmm15,[rbx] + vfnmadd132pd xmm7,xmm15,[rbx] + vfnmadd132ss xmm7,xmm15,[rbx] + vfnmadd132sd xmm7,xmm15,[rbx] + vfnmsub132ps xmm7,xmm15,[rbx] + vfnmsub132pd xmm7,xmm15,[rbx] + vfnmsub132ss xmm7,xmm15,[rbx] + vfnmsub132sd xmm7,xmm15,[rbx] + vfmaddsub213ps xmm7,xmm15,[rbx] + vfmaddsub213pd xmm7,xmm15,[rbx] + vfmsubadd213ps xmm7,xmm15,[rbx] + vfmsubadd213pd xmm7,xmm15,[rbx] + vfmadd213ps xmm7,xmm15,[rbx] + vfmadd213pd xmm7,xmm15,[rbx] + vfmadd213ss xmm7,xmm15,[rbx] + vfmadd213sd xmm7,xmm15,[rbx] + vfmsub213ps xmm7,xmm15,[rbx] + vfmsub213pd xmm7,xmm15,[rbx] + vfmsub213ss xmm7,xmm15,[rbx] + vfmsub213sd xmm7,xmm15,[rbx] + vfnmadd213ps xmm7,xmm15,[rbx] + vfnmadd213pd xmm7,xmm15,[rbx] + vfnmadd213ss xmm7,xmm15,[rbx] + vfnmadd213sd xmm7,xmm15,[rbx] + vfnmsub213ps xmm7,xmm15,[rbx] + vfnmsub213pd xmm7,xmm15,[rbx] + vfnmsub213ss xmm7,xmm15,[rbx] + vfnmsub213sd xmm7,xmm15,[rbx] + vfmaddsub231ps xmm7,xmm15,[rbx] + vfmaddsub231pd xmm7,xmm15,[rbx] + vfmsubadd231ps xmm7,xmm15,[rbx] + vfmsubadd231pd xmm7,xmm15,[rbx] + vfmadd231ps xmm7,xmm15,[rbx] + vfmadd231pd xmm7,xmm15,[rbx] + vfmadd231ss xmm7,xmm15,[rbx] + vfmadd231sd xmm7,xmm15,[rbx] + vfmsub231ps xmm7,xmm15,[rbx] + vfmsub231pd xmm7,xmm15,[rbx] + vfmsub231ss xmm7,xmm15,[rbx] + vfmsub231sd xmm7,xmm15,[rbx] + vfnmadd231ps xmm7,xmm15,[rbx] + vfnmadd231pd xmm7,xmm15,[rbx] + vfnmadd231ss xmm7,xmm15,[rbx] + vfnmadd231sd xmm7,xmm15,[rbx] + vfnmsub231ps xmm7,xmm15,[rbx] + vfnmsub231pd xmm7,xmm15,[rbx] + vfnmsub231ss xmm7,xmm15,[rbx] + vfnmsub231sd xmm7,xmm15,[rbx] + + + vfmaddsub132ps ymm7,ymm15,ymm13 + vfmaddsub132pd ymm7,ymm15,ymm13 + vfmsubadd132ps ymm7,ymm15,ymm13 + vfmsubadd132pd ymm7,ymm15,ymm13 + vfmadd132ps ymm7,ymm15,ymm13 + vfmadd132pd ymm7,ymm15,ymm13 + vfmsub132ps ymm7,ymm15,ymm13 + vfmsub132pd ymm7,ymm15,ymm13 + vfnmadd132ps ymm7,ymm15,ymm13 + vfnmadd132pd ymm7,ymm15,ymm13 + vfnmsub132ps ymm7,ymm15,ymm13 + vfnmsub132pd ymm7,ymm15,ymm13 + vfmaddsub213ps ymm7,ymm15,ymm13 + vfmaddsub213pd ymm7,ymm15,ymm13 + vfmsubadd213ps ymm7,ymm15,ymm13 + vfmsubadd213pd ymm7,ymm15,ymm13 + vfmadd213ps ymm7,ymm15,ymm13 + vfmadd213pd ymm7,ymm15,ymm13 + vfmsub213ps ymm7,ymm15,ymm13 + vfmsub213pd ymm7,ymm15,ymm13 + vfnmadd213ps ymm7,ymm15,ymm13 + vfnmadd213pd ymm7,ymm15,ymm13 + vfnmsub213ps ymm7,ymm15,ymm13 + vfnmsub213pd ymm7,ymm15,ymm13 + vfmaddsub231ps ymm7,ymm15,ymm13 + vfmaddsub231pd ymm7,ymm15,ymm13 + vfmsubadd231ps ymm7,ymm15,ymm13 + vfmsubadd231pd ymm7,ymm15,ymm13 + vfmadd231ps ymm7,ymm15,ymm13 + vfmadd231pd ymm7,ymm15,ymm13 + vfmsub231ps ymm7,ymm15,ymm13 + vfmsub231pd ymm7,ymm15,ymm13 + vfnmadd231ps ymm7,ymm15,ymm13 + vfnmadd231pd ymm7,ymm15,ymm13 + vfnmsub231ps ymm7,ymm15,ymm13 + vfnmsub231pd ymm7,ymm15,ymm13 + + vfmaddsub132ps ymm7,ymm15,[rbx] + vfmaddsub132pd ymm7,ymm15,[rbx] + vfmsubadd132ps ymm7,ymm15,[rbx] + vfmsubadd132pd ymm7,ymm15,[rbx] + vfmadd132ps ymm7,ymm15,[rbx] + vfmadd132pd ymm7,ymm15,[rbx] + vfmsub132ps ymm7,ymm15,[rbx] + vfmsub132pd ymm7,ymm15,[rbx] + vfnmadd132ps ymm7,ymm15,[rbx] + vfnmadd132pd ymm7,ymm15,[rbx] + vfnmsub132ps ymm7,ymm15,[rbx] + vfnmsub132pd ymm7,ymm15,[rbx] + vfmaddsub213ps ymm7,ymm15,[rbx] + vfmaddsub213pd ymm7,ymm15,[rbx] + vfmsubadd213ps ymm7,ymm15,[rbx] + vfmsubadd213pd ymm7,ymm15,[rbx] + vfmadd213ps ymm7,ymm15,[rbx] + vfmadd213pd ymm7,ymm15,[rbx] + vfmsub213ps ymm7,ymm15,[rbx] + vfmsub213pd ymm7,ymm15,[rbx] + vfnmadd213ps ymm7,ymm15,[rbx] + vfnmadd213pd ymm7,ymm15,[rbx] + vfnmsub213ps ymm7,ymm15,[rbx] + vfnmsub213pd ymm7,ymm15,[rbx] + vfmaddsub231ps ymm7,ymm15,[rbx] + vfmaddsub231pd ymm7,ymm15,[rbx] + vfmsubadd231ps ymm7,ymm15,[rbx] + vfmsubadd231pd ymm7,ymm15,[rbx] + vfmadd231ps ymm7,ymm15,[rbx] + vfmadd231pd ymm7,ymm15,[rbx] + vfmsub231ps ymm7,ymm15,[rbx] + vfmsub231pd ymm7,ymm15,[rbx] + vfnmadd231ps ymm7,ymm15,[rbx] + vfnmadd231pd ymm7,ymm15,[rbx] + vfnmsub231ps ymm7,ymm15,[rbx] + vfnmsub231pd ymm7,ymm15,[rbx] diff --git a/bddisasm_test/avx/fma_64.result b/bddisasm_test/avx/fma_64.result new file mode 100644 index 0000000..9f589bc --- /dev/null +++ b/bddisasm_test/avx/fma_64.result @@ -0,0 +1,3360 @@ +0000000000000000 c4c20196fd VFMADDSUB132PS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000005 c4c28196fd VFMADDSUB132PD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000000A c4c20197fd VFMSUBADD132PS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000000F c4c28197fd VFMSUBADD132PD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000014 c4c20198fd VFMADD132PS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000019 c4c28198fd VFMADD132PD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000001E c4c20199fd VFMADD132SS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000023 c4c28199fd VFMADD132SD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000028 c4c2019afd VFMSUB132PS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000002D c4c2819afd VFMSUB132PD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000032 c4c2019bfd VFMSUB132SS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000037 c4c2819bfd VFMSUB132SD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000003C c4c2019cfd VFNMADD132PS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000041 c4c2819cfd VFNMADD132PD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000046 c4c2019dfd VFNMADD132SS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000004B c4c2819dfd VFNMADD132SD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000050 c4c2019efd VFNMSUB132PS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000055 c4c2819efd VFNMSUB132PD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000005A c4c2019ffd VFNMSUB132SS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000005F c4c2819ffd VFNMSUB132SD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000064 c4c201a6fd VFMADDSUB213PS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000069 c4c281a6fd VFMADDSUB213PD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000006E c4c201a7fd VFMSUBADD213PS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000073 c4c281a7fd VFMSUBADD213PD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000078 c4c201a8fd VFMADD213PS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000007D c4c281a8fd VFMADD213PD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000082 c4c201a9fd VFMADD213SS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000087 c4c281a9fd VFMADD213SD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000008C c4c201aafd VFMSUB213PS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000091 c4c281aafd VFMSUB213PD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000096 c4c201abfd VFMSUB213SS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000009B c4c281abfd VFMSUB213SD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000A0 c4c201acfd VFNMADD213PS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000A5 c4c281acfd VFNMADD213PD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000AA c4c201adfd VFNMADD213SS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000AF c4c281adfd VFNMADD213SD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000B4 c4c201aefd VFNMSUB213PS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000B9 c4c281aefd VFNMSUB213PD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000BE c4c201affd VFNMSUB213SS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000C3 c4c281affd VFNMSUB213SD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000C8 c4c201b6fd VFMADDSUB231PS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000CD c4c281b6fd VFMADDSUB231PD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000D2 c4c201b7fd VFMSUBADD231PS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000D7 c4c281b7fd VFMSUBADD231PD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000DC c4c201b8fd VFMADD231PS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000E1 c4c281b8fd VFMADD231PD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000E6 c4c201b9fd VFMADD231SS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000EB c4c281b9fd VFMADD231SD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000F0 c4c201bafd VFMSUB231PS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000F5 c4c281bafd VFMSUB231PD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000FA c4c201bbfd VFMSUB231SS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000FF c4c281bbfd VFMSUB231SD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000104 c4c201bcfd VFNMADD231PS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000109 c4c281bcfd VFNMADD231PD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000010E c4c201bdfd VFNMADD231SS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000113 c4c281bdfd VFNMADD231SD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000118 c4c201befd VFNMSUB231PS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000011D c4c281befd VFNMSUB231PD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000122 c4c201bffd VFNMSUB231SS xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000127 c4c281bffd VFNMSUB231SD xmm7, xmm15, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000012C c4e201963b VFMADDSUB132PS xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000131 c4e281963b VFMADDSUB132PD xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000136 c4e201973b VFMSUBADD132PS xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000013B c4e281973b VFMSUBADD132PD xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000140 c4e201983b VFMADD132PS xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000145 c4e281983b VFMADD132PD xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000014A c4e201993b VFMADD132SS xmm7, xmm15, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +000000000000014F c4e281993b VFMADD132SD xmm7, xmm15, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000154 c4e2019a3b VFMSUB132PS xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000159 c4e2819a3b VFMSUB132PD xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000015E c4e2019b3b VFMSUB132SS xmm7, xmm15, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +0000000000000163 c4e2819b3b VFMSUB132SD xmm7, xmm15, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000168 c4e2019c3b VFNMADD132PS xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000016D c4e2819c3b VFNMADD132PD xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000172 c4e2019d3b VFNMADD132SS xmm7, xmm15, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +0000000000000177 c4e2819d3b VFNMADD132SD xmm7, xmm15, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000017C c4e2019e3b VFNMSUB132PS xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000181 c4e2819e3b VFNMSUB132PD xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000186 c4e2019f3b VFNMSUB132SS xmm7, xmm15, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +000000000000018B c4e2819f3b VFNMSUB132SD xmm7, xmm15, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000190 c4e201a63b VFMADDSUB213PS xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000195 c4e281a63b VFMADDSUB213PD xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000019A c4e201a73b VFMSUBADD213PS xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000019F c4e281a73b VFMSUBADD213PD xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000001A4 c4e201a83b VFMADD213PS xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000001A9 c4e281a83b VFMADD213PD xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000001AE c4e201a93b VFMADD213SS xmm7, xmm15, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +00000000000001B3 c4e281a93b VFMADD213SD xmm7, xmm15, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000001B8 c4e201aa3b VFMSUB213PS xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000001BD c4e281aa3b VFMSUB213PD xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000001C2 c4e201ab3b VFMSUB213SS xmm7, xmm15, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +00000000000001C7 c4e281ab3b VFMSUB213SD xmm7, xmm15, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000001CC c4e201ac3b VFNMADD213PS xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000001D1 c4e281ac3b VFNMADD213PD xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000001D6 c4e201ad3b VFNMADD213SS xmm7, xmm15, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +00000000000001DB c4e281ad3b VFNMADD213SD xmm7, xmm15, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000001E0 c4e201ae3b VFNMSUB213PS xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000001E5 c4e281ae3b VFNMSUB213PD xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000001EA c4e201af3b VFNMSUB213SS xmm7, xmm15, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +00000000000001EF c4e281af3b VFNMSUB213SD xmm7, xmm15, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000001F4 c4e201b63b VFMADDSUB231PS xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000001F9 c4e281b63b VFMADDSUB231PD xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000001FE c4e201b73b VFMSUBADD231PS xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000203 c4e281b73b VFMSUBADD231PD xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000208 c4e201b83b VFMADD231PS xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000020D c4e281b83b VFMADD231PD xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000212 c4e201b93b VFMADD231SS xmm7, xmm15, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +0000000000000217 c4e281b93b VFMADD231SD xmm7, xmm15, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000021C c4e201ba3b VFMSUB231PS xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000221 c4e281ba3b VFMSUB231PD xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000226 c4e201bb3b VFMSUB231SS xmm7, xmm15, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +000000000000022B c4e281bb3b VFMSUB231SD xmm7, xmm15, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000230 c4e201bc3b VFNMADD231PS xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000235 c4e281bc3b VFNMADD231PD xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000023A c4e201bd3b VFNMADD231SS xmm7, xmm15, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +000000000000023F c4e281bd3b VFNMADD231SD xmm7, xmm15, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000244 c4e201be3b VFNMSUB231PS xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000249 c4e281be3b VFNMSUB231PD xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000024E c4e201bf3b VFNMSUB231SS xmm7, xmm15, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +0000000000000253 c4e281bf3b VFNMSUB231SD xmm7, xmm15, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000258 c4c20596fd VFMADDSUB132PS ymm7, ymm15, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +000000000000025D c4c28596fd VFMADDSUB132PD ymm7, ymm15, ymm13 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +0000000000000262 c4c20597fd VFMSUBADD132PS ymm7, ymm15, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +0000000000000267 c4c28597fd VFMSUBADD132PD ymm7, ymm15, ymm13 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +000000000000026C c4c20598fd VFMADD132PS ymm7, ymm15, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +0000000000000271 c4c28598fd VFMADD132PD ymm7, ymm15, ymm13 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +0000000000000276 c4c2059afd VFMSUB132PS ymm7, ymm15, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +000000000000027B c4c2859afd VFMSUB132PD ymm7, ymm15, ymm13 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +0000000000000280 c4c2059cfd VFNMADD132PS ymm7, ymm15, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +0000000000000285 c4c2859cfd VFNMADD132PD ymm7, ymm15, ymm13 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +000000000000028A c4c2059efd VFNMSUB132PS ymm7, ymm15, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +000000000000028F c4c2859efd VFNMSUB132PD ymm7, ymm15, ymm13 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +0000000000000294 c4c205a6fd VFMADDSUB213PS ymm7, ymm15, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +0000000000000299 c4c285a6fd VFMADDSUB213PD ymm7, ymm15, ymm13 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +000000000000029E c4c205a7fd VFMSUBADD213PS ymm7, ymm15, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +00000000000002A3 c4c285a7fd VFMSUBADD213PD ymm7, ymm15, ymm13 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +00000000000002A8 c4c205a8fd VFMADD213PS ymm7, ymm15, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +00000000000002AD c4c285a8fd VFMADD213PD ymm7, ymm15, ymm13 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +00000000000002B2 c4c205aafd VFMSUB213PS ymm7, ymm15, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +00000000000002B7 c4c285aafd VFMSUB213PD ymm7, ymm15, ymm13 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +00000000000002BC c4c205acfd VFNMADD213PS ymm7, ymm15, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +00000000000002C1 c4c285acfd VFNMADD213PD ymm7, ymm15, ymm13 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +00000000000002C6 c4c205aefd VFNMSUB213PS ymm7, ymm15, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +00000000000002CB c4c285aefd VFNMSUB213PD ymm7, ymm15, ymm13 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +00000000000002D0 c4c205b6fd VFMADDSUB231PS ymm7, ymm15, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +00000000000002D5 c4c285b6fd VFMADDSUB231PD ymm7, ymm15, ymm13 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +00000000000002DA c4c205b7fd VFMSUBADD231PS ymm7, ymm15, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +00000000000002DF c4c285b7fd VFMSUBADD231PD ymm7, ymm15, ymm13 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +00000000000002E4 c4c205b8fd VFMADD231PS ymm7, ymm15, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +00000000000002E9 c4c285b8fd VFMADD231PD ymm7, ymm15, ymm13 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +00000000000002EE c4c205bafd VFMSUB231PS ymm7, ymm15, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +00000000000002F3 c4c285bafd VFMSUB231PD ymm7, ymm15, ymm13 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +00000000000002F8 c4c205bcfd VFNMADD231PS ymm7, ymm15, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +00000000000002FD c4c285bcfd VFNMADD231PD ymm7, ymm15, ymm13 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +0000000000000302 c4c205befd VFNMSUB231PS ymm7, ymm15, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +0000000000000307 c4c285befd VFNMSUB231PD ymm7, ymm15, ymm13 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +000000000000030C c4e205963b VFMADDSUB132PS ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000311 c4e285963b VFMADDSUB132PD ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000316 c4e205973b VFMSUBADD132PS ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000031B c4e285973b VFMSUBADD132PD ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000320 c4e205983b VFMADD132PS ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000325 c4e285983b VFMADD132PD ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000032A c4e2059a3b VFMSUB132PS ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000032F c4e2859a3b VFMSUB132PD ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000334 c4e2059c3b VFNMADD132PS ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000339 c4e2859c3b VFNMADD132PD ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000033E c4e2059e3b VFNMSUB132PS ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000343 c4e2859e3b VFNMSUB132PD ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000348 c4e205a63b VFMADDSUB213PS ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000034D c4e285a63b VFMADDSUB213PD ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000352 c4e205a73b VFMSUBADD213PS ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000357 c4e285a73b VFMSUBADD213PD ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000035C c4e205a83b VFMADD213PS ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000361 c4e285a83b VFMADD213PD ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000366 c4e205aa3b VFMSUB213PS ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000036B c4e285aa3b VFMSUB213PD ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000370 c4e205ac3b VFNMADD213PS ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000375 c4e285ac3b VFNMADD213PD ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000037A c4e205ae3b VFNMSUB213PS ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000037F c4e285ae3b VFNMSUB213PD ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000384 c4e205b63b VFMADDSUB231PS ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000389 c4e285b63b VFMADDSUB231PD ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000038E c4e205b73b VFMSUBADD231PS ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000393 c4e285b73b VFMSUBADD231PD ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000398 c4e205b83b VFMADD231PS ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000039D c4e285b83b VFMADD231PD ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000003A2 c4e205ba3b VFMSUB231PS ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000003A7 c4e285ba3b VFMSUB231PD ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000003AC c4e205bc3b VFNMADD231PS ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000003B1 c4e285bc3b VFNMADD231PD ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000003B6 c4e205be3b VFNMSUB231PS ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000003BB c4e285be3b VFNMSUB231PD ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: FMA, Ins cat: VFMA, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 12 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + diff --git a/bddisasm_test/avx512/avx512bitalg_64 b/bddisasm_test/avx512/avx512bitalg_64 new file mode 100644 index 0000000..e5ff85b --- /dev/null +++ b/bddisasm_test/avx512/avx512bitalg_64 @@ -0,0 +1 @@ +b}Tb}Tb}TTb}TTb} Tb} Tb} TTb} TTb}Tb}Tb}TTb}TTb}Tb}Tb}TTb}TTb}(Tb}(Tb}(TDb}(TDb}-Tb}-Tb}-TDb}-TDb}Tb}Tb}TDb}TDb}Tb}Tb}TDb}TDb}HTbb}HTb"}HTDb"}HTDb}MTbb}MTb"}MTDb"}MTDb}Tbb}Tb"}TDb"}TDb}Tbb}Tb"}TDb"}TDbTbTbTTbTTb Tb Tb TTb TTbTbTbTTbTTbTbTbTTbTTb(Tb(Tb(TDb(TDb-Tb-Tb-TDb-TDbTbTbTDbTDbTbTbTDbTDbHTbbHTb"HTDb"HTDbMTbbMTb"MTDb"MTDbTbbTb"TDb"TDbTbbTb"TDb"TDbEbEbE\bE\b(b(b(\b(\b=@b=@b=@\b=@\bE bE bE \bE \b-b-b-\b-\b=Eb=Eb=E\b=E\ \ No newline at end of file diff --git a/bddisasm_test/avx512/avx512bitalg_64.asm b/bddisasm_test/avx512/avx512bitalg_64.asm new file mode 100644 index 0000000..47d7efd --- /dev/null +++ b/bddisasm_test/avx512/avx512bitalg_64.asm @@ -0,0 +1,122 @@ + bits 64 + + vpopcntb xmm2, xmm0 + vpopcntb xmm2, [rbx] + vpopcntb xmm2, [rbx+r11*8+256] + vpopcntb xmm2, [rbx+r11*8-256] + vpopcntb xmm2{k5}, xmm0 + vpopcntb xmm2{k5}, [rbx] + vpopcntb xmm2{k5}, [rbx+r11*8+256] + vpopcntb xmm2{k5}, [rbx+r11*8-256] + vpopcntb xmm2{z}, xmm0 + vpopcntb xmm2{z}, [rbx] + vpopcntb xmm2{z}, [rbx+r11*8+256] + vpopcntb xmm2{z}, [rbx+r11*8-256] + vpopcntb xmm2{k5}{z}, xmm0 + vpopcntb xmm2{k5}{z}, [rbx] + vpopcntb xmm2{k5}{z}, [rbx+r11*8+256] + vpopcntb xmm2{k5}{z}, [rbx+r11*8-256] + vpopcntb ymm16, ymm15 + vpopcntb ymm16, [rbx] + vpopcntb ymm16, [rbx+r11*8+256] + vpopcntb ymm16, [rbx+r11*8-256] + vpopcntb ymm16{k5}, ymm15 + vpopcntb ymm16{k5}, [rbx] + vpopcntb ymm16{k5}, [rbx+r11*8+256] + vpopcntb ymm16{k5}, [rbx+r11*8-256] + vpopcntb ymm16{z}, ymm15 + vpopcntb ymm16{z}, [rbx] + vpopcntb ymm16{z}, [rbx+r11*8+256] + vpopcntb ymm16{z}, [rbx+r11*8-256] + vpopcntb ymm16{k5}{z}, ymm15 + vpopcntb ymm16{k5}{z}, [rbx] + vpopcntb ymm16{k5}{z}, [rbx+r11*8+256] + vpopcntb ymm16{k5}{z}, [rbx+r11*8-256] + vpopcntb zmm24, zmm31 + vpopcntb zmm24, [rbx] + vpopcntb zmm24, [rbx+r11*8+256] + vpopcntb zmm24, [rbx+r11*8-256] + vpopcntb zmm24{k5}, zmm31 + vpopcntb zmm24{k5}, [rbx] + vpopcntb zmm24{k5}, [rbx+r11*8+256] + vpopcntb zmm24{k5}, [rbx+r11*8-256] + vpopcntb zmm24{z}, zmm31 + vpopcntb zmm24{z}, [rbx] + vpopcntb zmm24{z}, [rbx+r11*8+256] + vpopcntb zmm24{z}, [rbx+r11*8-256] + vpopcntb zmm24{k5}{z}, zmm31 + vpopcntb zmm24{k5}{z}, [rbx] + vpopcntb zmm24{k5}{z}, [rbx+r11*8+256] + vpopcntb zmm24{k5}{z}, [rbx+r11*8-256] + vpopcntw xmm2, xmm0 + vpopcntw xmm2, [rbx] + vpopcntw xmm2, [rbx+r11*8+256] + vpopcntw xmm2, [rbx+r11*8-256] + vpopcntw xmm2{k5}, xmm0 + vpopcntw xmm2{k5}, [rbx] + vpopcntw xmm2{k5}, [rbx+r11*8+256] + vpopcntw xmm2{k5}, [rbx+r11*8-256] + vpopcntw xmm2{z}, xmm0 + vpopcntw xmm2{z}, [rbx] + vpopcntw xmm2{z}, [rbx+r11*8+256] + vpopcntw xmm2{z}, [rbx+r11*8-256] + vpopcntw xmm2{k5}{z}, xmm0 + vpopcntw xmm2{k5}{z}, [rbx] + vpopcntw xmm2{k5}{z}, [rbx+r11*8+256] + vpopcntw xmm2{k5}{z}, [rbx+r11*8-256] + vpopcntw ymm16, ymm15 + vpopcntw ymm16, [rbx] + vpopcntw ymm16, [rbx+r11*8+256] + vpopcntw ymm16, [rbx+r11*8-256] + vpopcntw ymm16{k5}, ymm15 + vpopcntw ymm16{k5}, [rbx] + vpopcntw ymm16{k5}, [rbx+r11*8+256] + vpopcntw ymm16{k5}, [rbx+r11*8-256] + vpopcntw ymm16{z}, ymm15 + vpopcntw ymm16{z}, [rbx] + vpopcntw ymm16{z}, [rbx+r11*8+256] + vpopcntw ymm16{z}, [rbx+r11*8-256] + vpopcntw ymm16{k5}{z}, ymm15 + vpopcntw ymm16{k5}{z}, [rbx] + vpopcntw ymm16{k5}{z}, [rbx+r11*8+256] + vpopcntw ymm16{k5}{z}, [rbx+r11*8-256] + vpopcntw zmm24, zmm31 + vpopcntw zmm24, [rbx] + vpopcntw zmm24, [rbx+r11*8+256] + vpopcntw zmm24, [rbx+r11*8-256] + vpopcntw zmm24{k5}, zmm31 + vpopcntw zmm24{k5}, [rbx] + vpopcntw zmm24{k5}, [rbx+r11*8+256] + vpopcntw zmm24{k5}, [rbx+r11*8-256] + vpopcntw zmm24{z}, zmm31 + vpopcntw zmm24{z}, [rbx] + vpopcntw zmm24{z}, [rbx+r11*8+256] + vpopcntw zmm24{z}, [rbx+r11*8-256] + vpopcntw zmm24{k5}{z}, zmm31 + vpopcntw zmm24{k5}{z}, [rbx] + vpopcntw zmm24{k5}{z}, [rbx+r11*8+256] + vpopcntw zmm24{k5}{z}, [rbx+r11*8-256] + vpshufbitqmb k3, xmm7, xmm0 + vpshufbitqmb k3, xmm7, [rbx] + vpshufbitqmb k3, xmm7, [rbx+r11*8+256] + vpshufbitqmb k3, xmm7, [rbx+r11*8-256] + vpshufbitqmb k3, ymm13, ymm15 + vpshufbitqmb k3, ymm13, [rbx] + vpshufbitqmb k3, ymm13, [rbx+r11*8+256] + vpshufbitqmb k3, ymm13, [rbx+r11*8-256] + vpshufbitqmb k3, zmm24, zmm31 + vpshufbitqmb k3, zmm24, [rbx] + vpshufbitqmb k3, zmm24, [rbx+r11*8+256] + vpshufbitqmb k3, zmm24, [rbx+r11*8-256] + vpshufbitqmb k3{k5}, xmm7, xmm0 + vpshufbitqmb k3{k5}, xmm7, [rbx] + vpshufbitqmb k3{k5}, xmm7, [rbx+r11*8+256] + vpshufbitqmb k3{k5}, xmm7, [rbx+r11*8-256] + vpshufbitqmb k3{k5}, ymm13, ymm15 + vpshufbitqmb k3{k5}, ymm13, [rbx] + vpshufbitqmb k3{k5}, ymm13, [rbx+r11*8+256] + vpshufbitqmb k3{k5}, ymm13, [rbx+r11*8-256] + vpshufbitqmb k3{k5}, zmm24, zmm31 + vpshufbitqmb k3{k5}, zmm24, [rbx] + vpshufbitqmb k3{k5}, zmm24, [rbx+r11*8+256] + vpshufbitqmb k3{k5}, zmm24, [rbx+r11*8-256] diff --git a/bddisasm_test/avx512/avx512bitalg_64.result b/bddisasm_test/avx512/avx512bitalg_64.result new file mode 100644 index 0000000..6050b84 --- /dev/null +++ b/bddisasm_test/avx512/avx512bitalg_64.result @@ -0,0 +1,2358 @@ +0000000000000000 62f27d0854d0 VPOPCNTB xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000006 62f27d085413 VPOPCNTB xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000000C 62b27d085454db10 VPOPCNTB xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000014 62b27d085454dbf0 VPOPCNTB xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000001C 62f27d0d54d0 VPOPCNTB xmm2{k5}, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000022 62f27d0d5413 VPOPCNTB xmm2{k5}, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000028 62b27d0d5454db10 VPOPCNTB xmm2{k5}, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000030 62b27d0d5454dbf0 VPOPCNTB xmm2{k5}, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000038 62f27d8854d0 VPOPCNTB xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000003E 62f27d885413 VPOPCNTB xmm2, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000044 62b27d885454db10 VPOPCNTB xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000004C 62b27d885454dbf0 VPOPCNTB xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000054 62f27d8d54d0 VPOPCNTB xmm2{k5}{z}, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000005A 62f27d8d5413 VPOPCNTB xmm2{k5}{z}, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000060 62b27d8d5454db10 VPOPCNTB xmm2{k5}{z}, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000068 62b27d8d5454dbf0 VPOPCNTB xmm2{k5}{z}, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000070 62c27d2854c7 VPOPCNTB ymm16, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000076 62e27d285403 VPOPCNTB ymm16, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000007C 62a27d285444db08 VPOPCNTB ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000084 62a27d285444dbf8 VPOPCNTB ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000008C 62c27d2d54c7 VPOPCNTB ymm16{k5}, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000092 62e27d2d5403 VPOPCNTB ymm16{k5}, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000098 62a27d2d5444db08 VPOPCNTB ymm16{k5}, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000000A0 62a27d2d5444dbf8 VPOPCNTB ymm16{k5}, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000000A8 62c27da854c7 VPOPCNTB ymm16, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000000AE 62e27da85403 VPOPCNTB ymm16, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000000B4 62a27da85444db08 VPOPCNTB ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000000BC 62a27da85444dbf8 VPOPCNTB ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000000C4 62c27dad54c7 VPOPCNTB ymm16{k5}{z}, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000000CA 62e27dad5403 VPOPCNTB ymm16{k5}{z}, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000000D0 62a27dad5444db08 VPOPCNTB ymm16{k5}{z}, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000000D8 62a27dad5444dbf8 VPOPCNTB ymm16{k5}{z}, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000000E0 62027d4854c7 VPOPCNTB zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000000E6 62627d485403 VPOPCNTB zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000000EC 62227d485444db04 VPOPCNTB zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000000F4 62227d485444dbfc VPOPCNTB zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000000FC 62027d4d54c7 VPOPCNTB zmm24{k5}, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000102 62627d4d5403 VPOPCNTB zmm24{k5}, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000108 62227d4d5444db04 VPOPCNTB zmm24{k5}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000110 62227d4d5444dbfc VPOPCNTB zmm24{k5}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000118 62027dc854c7 VPOPCNTB zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000011E 62627dc85403 VPOPCNTB zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000124 62227dc85444db04 VPOPCNTB zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000012C 62227dc85444dbfc VPOPCNTB zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000134 62027dcd54c7 VPOPCNTB zmm24{k5}{z}, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000013A 62627dcd5403 VPOPCNTB zmm24{k5}{z}, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000140 62227dcd5444db04 VPOPCNTB zmm24{k5}{z}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000148 62227dcd5444dbfc VPOPCNTB zmm24{k5}{z}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000150 62f2fd0854d0 VPOPCNTW xmm2, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000156 62f2fd085413 VPOPCNTW xmm2, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000015C 62b2fd085454db10 VPOPCNTW xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000164 62b2fd085454dbf0 VPOPCNTW xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000016C 62f2fd0d54d0 VPOPCNTW xmm2{k5}, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000172 62f2fd0d5413 VPOPCNTW xmm2{k5}, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000178 62b2fd0d5454db10 VPOPCNTW xmm2{k5}, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000180 62b2fd0d5454dbf0 VPOPCNTW xmm2{k5}, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000188 62f2fd8854d0 VPOPCNTW xmm2, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000018E 62f2fd885413 VPOPCNTW xmm2, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000194 62b2fd885454db10 VPOPCNTW xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000019C 62b2fd885454dbf0 VPOPCNTW xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000001A4 62f2fd8d54d0 VPOPCNTW xmm2{k5}{z}, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000001AA 62f2fd8d5413 VPOPCNTW xmm2{k5}{z}, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000001B0 62b2fd8d5454db10 VPOPCNTW xmm2{k5}{z}, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000001B8 62b2fd8d5454dbf0 VPOPCNTW xmm2{k5}{z}, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000001C0 62c2fd2854c7 VPOPCNTW ymm16, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000001C6 62e2fd285403 VPOPCNTW ymm16, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000001CC 62a2fd285444db08 VPOPCNTW ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000001D4 62a2fd285444dbf8 VPOPCNTW ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000001DC 62c2fd2d54c7 VPOPCNTW ymm16{k5}, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000001E2 62e2fd2d5403 VPOPCNTW ymm16{k5}, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000001E8 62a2fd2d5444db08 VPOPCNTW ymm16{k5}, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000001F0 62a2fd2d5444dbf8 VPOPCNTW ymm16{k5}, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000001F8 62c2fda854c7 VPOPCNTW ymm16, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000001FE 62e2fda85403 VPOPCNTW ymm16, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000204 62a2fda85444db08 VPOPCNTW ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000020C 62a2fda85444dbf8 VPOPCNTW ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000214 62c2fdad54c7 VPOPCNTW ymm16{k5}{z}, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000021A 62e2fdad5403 VPOPCNTW ymm16{k5}{z}, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000220 62a2fdad5444db08 VPOPCNTW ymm16{k5}{z}, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000228 62a2fdad5444dbf8 VPOPCNTW ymm16{k5}{z}, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000230 6202fd4854c7 VPOPCNTW zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000236 6262fd485403 VPOPCNTW zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000023C 6222fd485444db04 VPOPCNTW zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000244 6222fd485444dbfc VPOPCNTW zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000024C 6202fd4d54c7 VPOPCNTW zmm24{k5}, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000252 6262fd4d5403 VPOPCNTW zmm24{k5}, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000258 6222fd4d5444db04 VPOPCNTW zmm24{k5}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000260 6222fd4d5444dbfc VPOPCNTW zmm24{k5}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000268 6202fdc854c7 VPOPCNTW zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000026E 6262fdc85403 VPOPCNTW zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000274 6222fdc85444db04 VPOPCNTW zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000027C 6222fdc85444dbfc VPOPCNTW zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000284 6202fdcd54c7 VPOPCNTW zmm24{k5}{z}, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000028A 6262fdcd5403 VPOPCNTW zmm24{k5}{z}, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000290 6222fdcd5444db04 VPOPCNTW zmm24{k5}{z}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000298 6222fdcd5444dbfc VPOPCNTW zmm24{k5}{z}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: VPOPCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000002A0 62f245088fd8 VPSHUFBITQMB k3, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000002A6 62f245088f1b VPSHUFBITQMB k3, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000002AC 62b245088f5cdb10 VPSHUFBITQMB k3, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000002B4 62b245088f5cdbf0 VPSHUFBITQMB k3, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000002BC 62d215288fdf VPSHUFBITQMB k3, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000002C2 62f215288f1b VPSHUFBITQMB k3, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000002C8 62b215288f5cdb08 VPSHUFBITQMB k3, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000002D0 62b215288f5cdbf8 VPSHUFBITQMB k3, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000002D8 62923d408fdf VPSHUFBITQMB k3, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000002DE 62f23d408f1b VPSHUFBITQMB k3, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000002E4 62b23d408f5cdb04 VPSHUFBITQMB k3, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000002EC 62b23d408f5cdbfc VPSHUFBITQMB k3, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000002F4 62f2450d8fd8 VPSHUFBITQMB k3{k5}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000002FA 62f2450d8f1b VPSHUFBITQMB k3{k5}, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000300 62b2450d8f5cdb10 VPSHUFBITQMB k3{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000308 62b2450d8f5cdbf0 VPSHUFBITQMB k3{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512BITALG, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000310 62d2152d8fdf VPSHUFBITQMB k3{k5}, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000316 62f2152d8f1b VPSHUFBITQMB k3{k5}, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000031C 62b2152d8f5cdb08 VPSHUFBITQMB k3{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000324 62b2152d8f5cdbf8 VPSHUFBITQMB k3{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512BITALG, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000032C 62923d458fdf VPSHUFBITQMB k3{k5}, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000332 62f23d458f1b VPSHUFBITQMB k3{k5}, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000338 62b23d458f5cdb04 VPSHUFBITQMB k3{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000340 62b23d458f5cdbfc VPSHUFBITQMB k3{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512BITALG, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 12 + EVEX Tuple Type: Full Mem + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + diff --git a/bddisasm_test/avx512/avx512bw_64 b/bddisasm_test/avx512/avx512bw_64 new file mode 100644 index 0000000000000000000000000000000000000000..1a68f6ad2296b90160c93ebfeaaab9a8383e2657 GIT binary patch literal 24734 zcmZvkPmCSceWmH477YpyqQdkbfJK0I0HXup0t~VtG-{d@REdy516e3LFT^ITKhVM! zECQl!vS%@i+7u8w;lKkV3ptzG)WV)kHXIZ)tZ~l(4UicSL+TGriWG(tM1gc5O>^9m z=A7@I_gb;C(ETp&cX|8r)bG}Nulm`SZcTrF{nD*VZl>dIp79@P{KtoX^>sIY`_Fs6 zwr5XzUwrX}dkgy$Px;AWihG(e{r0EVr{Dhd|G0E(+iPqu)}Y54+g_tuud%&YgC0|~ z$faAX^6*(tb~80y!S|U;k78 z$<6dOwQ;6hhwE@%oOyr!;ukC5`_=j_wR_j!RI9YZZMlLg zxDsdD^|&6_$C-8mZomz3=Jxv6zIaaVgxbC9-%zV`!yUOb+!}5z&a~UaZQ?fLOuH@I z7H%uf+#$(-T>oSJ%j(bG_Q=Ko|BE;FdLL?)^M-TQzkkF3e(g(qB;)rpzMXNcxxqD3 ztLvbaYXp_`2G>ZfU9J(d;~J^8%Qb>_TqCu1xkgaeXoG8{R@X=^*9a=>4X%+|yAo&G zagEg4^>L;h*GR415N9f<4X%+|T_d$zBdDx5xJGL2*5XV%u8~^1%{bGJYoyk0E6%KW z>Kf@^RDZUv(FWIOgKMFGw8)w>exDMCFnfKTK@$AYIzgmA!?cVjD ztMx7`x8(}1;7Xin*W-FzA7|PPxB)lBncM6C=InEF>uUF|e^af~sN9iT!>!@g;!L|u z+$L@_&a~UYZQ-`!OecEKi5_&K2N#LDmqZVe=s^-am_$Vq#kIIL&LmM>hwI`@5GdKOwSmYF)-r-GltACb@o?}X~qe)x-+l-h1zeZ&)o;=F0$G%qhZEhGNZ{1 z(=$e9jLf*qj4?Az&zP7oG2<#Trpz#PT~6w{ob(krxws*@_y=b6nPGayz>I+z7nm_*hN(Nv>M_k&SG!m3U#R`2`rL1z z?i;HOGa6?6B{Q1LFg;^r#>kAz%osDn^o)ra6Em(dW6BIumHv_{{UulWON&Z(FO~ih zmHrZy{!%Jkq|$LMu8lLPbXHSZjvH`8 zoJpn2snX?C;TogTMJgTF;F>s-O2>`3G0vpYaT9KeGnMC#^4xKrJBvKsOP)LAxkH{i z$x|dxT#IYtO!CBaxGv5l&mHpIA1b8*oFMNuF}bQ%-qm zj66m1#5K4k&LmIVh#TWf^2ANJDb7@$A1Tj|oaaZ2Jl#v4ACc!rdFB6;EpuEd$-iR*EFoJpRz0XM{%w!$WtUwT!U-k zO!CByxG~NoPuzr?;!NdvPkG*Rp7$1cx|clfk>@?~yq7#h^2D{cHqInZT!-u8O!B-( zp7+S}Uh)*l6IXC0&LmGQk|(agHE||+;zryUXObsw!cB3e@_bi$ zzUw^SUF7Lr@_d&(-zCp?lcz|YxE9yOndFJ*GxF#0|J1&LmGcySVrQ63JyR3(+#~(Ye@6z8Nf2?LY z?f5<@2j5lSRo~6MJMwxy`dEEF`dEEF`j|52 z`KUVe`Dpc}`ZD+K)aRqs_tp1v?@oO_TK!P{F!%1%=cD#|K5DP$qZ+QyN7bp%N2_nD zZ|2^e`h2wdvHEfD-Koz&eR>^w(`8~JZ~@ZbT4_{CePdCc{_QEZJbG- zxDMCFndEt!Ja3cd?c^zvC$8X1oJpRz9@od2`Rqd1{P2Me@WoxF*gd zPuz$b<4p3zO}Ht}+|g&yr5F7R{(ZiqAaz19swGdT zTrM;?@>IXN{Jjy%<`jy&}M_YFVAeZx<2-^hutJ)d|z7k@*ksa0xf z>x6l?&S;s@GNav{LATE6n9(t#+nqtzGxUu7jgeM)sQ({%JU{Q&8HE|;4bLdMGw9YC zJu`Y{^t&_Y))@mc24)PqGw6DTp7d&lTb}pMXXw$dyLHAIGuD`~wmXAvow3P`O=fKF z&Y)XoY%ybt8C$zE=z7L)&My7%%D>vq82@V9GXB-JWBhkp<^98p&igBEVdSfA&-ho{ zf$`sMm7vD|wRVm1ueO_vf3@9W{C8TF>lxSV8Q1KYMa{Zb)0>^4X3tQwnc$i|^ZeWY zL9w>z7TxaZHo8N1=x$ecXoYr$QawYdp4lzcGtX-A_s$k{L6==!qI-0Y?ss(`J)j5l zu&W2O0+n`4dCv7WHQ=AUes&GLhF;s%YtftNP4woj-i+QtZ=tt#^%hzs`6Ej5OYMyQ zm)n++FSi{dyRGv35vBK~w$T4_+cWazc3@<;RSFvUm+cxOUv4)U`Et9($Zo5zH+=gV zUvK#K*ZEe%x4)CGH>jhx*Z*sI<=elO7wm=a`0aJ==-w|0{%pR!JFH*o`lYU4=Igt|`b}NGsp~fyW_@?G{)1-e^=q_W*RO(>Uf1r!`|DSh zS6=`1`UACcYPIuld;KS?$L!R~snx2Xe*N0aSaW8leqGb_nuRqBYnH5Odd-G48`f+z z<~2>PxpbO+o@Sq?vrmzIo@SqR%PSgVpCbFTTRmo{Hv1IWCu`1FbEYx>+fDY#nuRrs z#=NGJFQ)Hi~*ykzsc`Ex9+2<+tX}7$hG4?64PrKD)c51Uvk$tk}j5TK( zW1k}XWX-~wMPuw!WS^|rux6t%_9?Q@@3PPDvd`~kpCbGGF8j1wUeOr)6xpZU>M=XD z*{8@pS#!pkGmWuNk$tjeVa=j3_9?PY)@)d_(HQ#_cl^DfqxF0pt>^2gR@M2?u$JX~ z9j)gJzr3R1dcM@D=L^4j3@>PP&X+p%eAV@5b^V!!S>K&{zUum=u3t3F`tH>8Ro8Fo z`i+L``BKO0Pj&x-_b=4->3IF~EBt-IUa0HS@%k5z;RSo4u1|;cXY7Bf`xmnQeE;W5 zUBB*Mf6Dsv{ajJIi0urB5(I`1y|xs-tOai zTpwrhb{{w3hB%YA`*M1_FQ>Qr8q>!o$lHBfgKOeUyAe0y#yHb%!cDj-&gA3MS@Jwf zo@bM%NS?SEZWd>fC$7b{aVB}v27w3ksGj+KJxW#kH+-#j-qrhh-HXpI{r;6XJm(6!4lQ5Y zH$9v-Ya_YLGRwQmxI15F`HJWL&)Vqm?IBM-erPe7t|xocKgI2I@zMb|nN@q9q#jli z-#h+@zuEAJztix@{F4biP4x4gM^r3oRV->L7O0Efw73@6#+h~JkS0FZj3YSCftOZ;!Hh{{6xu_D1$@9ohcpmu)&m%u^p8EEa$n!{C!Ie0Z=aIM`*Ts-=aIM(H^!MfkHk&5DbDnFZ=QCAKJ5y9dQqY7r9z*kLZ7BW zpH78}R4A^+wQ(jDitBJ)oO$0B`ZN{#G!^=EDpaIGaRpc6Oez%Di zw!$WtUw zT!U-kO!CByxG~NoPuzr?;!L0TqdxIRed3QM(b~(2Kgx+e%85Uk6EAY&aV@TmGdc0N z4%fw*ocN=h_@kWoqdD;+CmvUDCC=o;<9b{lXL90k18#^jIq`Bj@p3xx8so%^oOoP= zYvN2!JZ{8|aV94oH{qr@(}^B&qDP$Qkwv2JCD9`!dW1xeBvFw>aV@TmGf5QJ;kr1J zM30c@5fVL;L`4$C6C9`4GcR)HaSg7CGdc6P5jVz} zoO#@Yo8nC6`Ihp0%Xz-F$kV;#`4)M;MV@aZPmw%vEv}6-$rIP%x;T?O-y+Yq$n&k_ zDUv6y;7XiHp12;@$C>1b8*oFMNuF}bQ%-qmj66m1#5K4k&LmIVh#TWf^2ANJDbDnX zf66ERDWCYKl4$Ma#6QJ}e~J_TR8G9eiO03LHqPY4<2qayXL917;>172iGM05UgX5% z3a-SNoOoQ1>*GvLJZ``ZaV95TPA6VYCthQmc##v2Yj91R$%)5}xG~P;#N#I16ldy# z^SPxzy0-pL=T`pc*Xut$_ncadtXx@t@7&6Y9_*icPVH|#XXJB6K4;|I(xJL=%fE#c_oOyr!nX^u6U9GOITBlLDEw_eS!>z@ccAL0O+-96< zw}sonZN-_}z9##*O8dD=`?*T{xk~%FN@{gA_U9_?&s7q+N*d=X>CapxQEPrqy?jo+ ze4cta%uhMYPdUs_Im}Nv%ui9PpK>@q<#2wA$WPHYKSh7$r--hF!>)zHu7$&kT5vD5 zpr5E(&`(hfuyQ4}fNODWoJlRz@c)Bz*7pa+wbt&euvlgJI+&2 zL_}WOaRpc6OkUe@J+6;4d2PoHxFOEuwOvlH?Q(i;*BGzuBCqYZ2G_)yytd;;+!$x_ z+K!uWQ=F+h-&daRJJ0tQdAgT8-zU%a$@Bf>DUv6y#kFxJdEz=;7iW^^`{emPdA^@K zMe@WIT!}Nu6W8PVIFmea18#^j$x}{w$|+Bck*7$WxCYn6ndFHZabuiGp127&#hJ?U zs`9+*Jg+YDbT4^cCC{tmc{O>8ZJbG-xDMCFndEtuJg<`H)#NFXC$8X1oJpRz z9@od2`Rqd1{P2Me@WoxF*gdPuz$b<4p3zO}Ht}RGyzI&rhA_r;9w@ zbDkHMS3c$6{we?VPxEgV*{7WLDW`pEjD3oJKfA|wZZzP^Wj zOVIbQ-xQSayrW;_UOZQ-FV&a1cL(2B-&fzyy*v1!`l0$^?%k39+PUZKPYC+?-w>4e zyrW+ff9>2_^=s9y&AmJL&FVL+-<*4Q@LSbyRlha&?&y2qzjgkcf;MeBf9emAyqvkK<@4JJq`ES(xg?M-T zJ^UYN6Z)3V5B{Cf6@E;0)49Lz(#7Q;_zWzspoJg1IQ8Web@casvU&_J_^%5;cJb7X zez<=B|9iS2snrchEjJ{no6a=D&2Y0g)2_v}xHitT>u?>ei!*hzI=}LJx>>2!%}TAJ z4t3KxUvLFi;!L|9*W>y)({8{GxFOEe&FaE2IsKMZPQPWK(AL1{Cf3Z@p|Q+Us?42^Z~E`4|x55;0vkW*onOU<62xBXY%@w>u_D1dEfs( z1rJ7AUIQQabDrLxigpE89@v#Q)2_$$xIWIb8*l?|h%@i|6;;kHud6t{zQ#4U2G_)y z{(B>C#Eo&L-GrNPQ=I8SU3&a7Eye$MieI#w;bxE9&EibE7T4n1IMc4fb+|6hr1&4F z_#dbEA5Za%6hE%uN}NgY<9b{lXHxvQ0XM{%6u+E`Urt4@F^XTL_;C%ci8CpF+=v_F zOo|^j;ifp##ecIF{~y-kKQ%A@Qz`!cQ;XkP#eZsE{HNx{Z?CGi7f#KK{}jc4OT~Z7 z#eZv2{O+arZ&CcWDE?b1ev#tGwYWCUr1)_iu8T7%{#z9PEsFnEieIGoaRpc6Oo|`Z zQiRAEVnm(@;QR_yh9VlVLJvf8OHEBiTF`#D+rbFxHE7H)={#hIKe zT#IYtOimWA!*y{cCu=_^YdRj$-)&}i8DD_xE|NXnVc-#fE(gWPL`ZbmYhzO z#vTbdS-1w*#F?Bd+=v_FOimVV!cB3ePu68F)@y!;q*oW^Iq%e$mH*AfLhEEbKR;Q| z&rg=Uj+Fnp@cjH_J>rZ`h4Yg>74JJ0P!p6(^jZSveE&+X(Xk|(akwQ(kS;yPRxXYw(9n~$p7 z9`)($C-Rg#|^k4&gA2-obr@YjvC|RugJ%AT!U-kOg^UL zM%)-@@-ZDZ;ifoK#eY|M-gTaL7kRpuJnxd{UGlt}JVo-vwYWCUBu`w2>*7rEyi1;U z$@6aV6v-1;a3#(pPh5}d<4p3z4Y(oBBu_czDW^O&MxG*h;u>5NXObsw#Eo$#dEzGA z6lW^W50vKz&hvvsp6(^j56JTa^86rqisXrFac!JQp12Oz#hK*!0eOBvo*yJnkvwq) zSK>_a#Pzs7&LmIVfE(gW@|07aa>`R<=H{gailRV{= zr=0TC7&hz0SPxq4NL-Kq`o)43!NS?SB z*T$LTiR*A(oJpP!$@3w3K1`k>dEyGL#F^xY>v4UYNuIa?H^iCbDW^Q;l&8kXQzTDZ zgKOeU^2Cj}G0r4U+=QFrO#OnrS^CyB+OPY6aQ-d5a}MvX|I_lyxAY5lwQ_3pwmIBh z|LN*6JGF9Z^_DsGnlsj%*{NUGG`(hF&BB@`YnooOVaMGy8;IlYOf7n%O7Rnt#eZ)yk=5 zpHOT5TlT3|PA&U{TJtFTR4b>JeL}CvKGk~7>=SxT_NmruW}nb&vQM>MGy8;E^S`rC zwQ_3NC)Aq%iG8Y-Q_DV~*8H#RQ>~m@_6fZv`&8>Svrp(X*{52snSDa9$v)M3&FmBE zyuYmT{<6>e%Zu~wUe5c=ocEVG?=R=Pi=1~{i)-Ud&O5Hdb#W%={bkPk%bfR@bKXVH zJFehLoXL5|^|(IHkzT!MzS>)+n@_dCnUm?#|lBY*GxF#0|J1&LmGcw63JfS>KIL{M{Jl#v4C&=>z zd7em~B6;FkTpMSSC$7VFaVB}5AkP!zc_Mj=){t#$jv~bVnZtf!88*K{8lU!1>D3E6eV`EI)3G~{DHx8&ubI$L1t`~aGbKmpR zt*U$8=YFW{w*A*f?U(v#5A^d-kJ=yp?JfQM$BQ4m_M;y~adB~>BAwsK{axp}!2P}4 zKm2$5!$A8Osy=@7<+r#0@zG_C|M2K?`@_FKYG3N7{b&9B%cJ)GwKM&^KK`!Vy7u~) z_YSW8@v&bnEA3HE@7fuosco^JYv$_XpQJw5>;z)MevTm~NmxxxA*K)~5Yr^A&&T(V zcCLLjex~t~#$Ao~R1Y3+q`nkUK~xZZh$;!Ii5jAYIEAQ_u$pKf8i*N0lZ5r<__f)- zh+k{Gr16Tzw^a`w|2Xwr#1LW#aSdXagw@0xVh(WzF;Bv3qJ?N7zJ_R%u%5Sb#MCP(dE*edci|QaUmpyXPs9g5QMK!sgI;MN%qR|Ao zs171?*&`Q?Cdfr~5Shy!xo9*&E~}4+K`S_c%^V2!w zrSYFs4<7$K^{Hknyy~a+s`RY(YP=e+PS0wu!E5lE^sGe(f;%bc~o z9DlRg`Pn7L!Hb`yK9^R^RzHhbt7mIw>zuWEwqdr(S?lxhcy*{*kKRM5XGhGAa@OkE z1+$BswR(2R>@sJq&&S`FjgQV4UmyQj^;I4B(5IU1;q^YU*Gtc8Z-O_$o1|y8H^rOc zP1Cb_4eWe0XJlP{l+0iNS5np$v!k4~vaXn2q^SHVz$azE9;8cI%ln{D`uOVwR%+?YSv?}tDGG%JIYxr>x$V$&RSVl%r0}* zsw?4YZ_#1vu*aRM<-!m9K7 zYUj5)uWQtKeYLCco@&m?sLtA}3ZjDOLsUsvP1F!I#3@9bgw;d?(Ll@~nk1|`udfb8 zyry@cv%6}Y-B%xKd|NeVW>n|y)d;Q+H-ftfH%iWGZUJ`+w}5*Hw@A)vZV5MoTf#ko zTP9~c*OA<~O%>+z9R_+$cFKdBL5+E#Mx)Et0d67u*bP3HJnUnVeO575Yn~@+$O~YM;G7N1tkz z{?cfI{!$%;)dc;e(FFaaItZ%?`b(n;`b%{X)~DlVW#_kZM&(uLFU<_}lz9(*uGtEL z{wnmBW`eMqs3GXDLVsx{2&;((g8nM>mu7;nJ|7S8-oCb1Qj4&|iiAD()*2R`R+{URqPn%C1J`q!mS8 zQu2bJzY6_TswAxB1wnrm`m5AQSjh{5{wnlWX_By#msa?J-T`@eofrD69LgszDS5%s zUxofE^q1=3tmFkpe--+x&|j)EujH0+^jD$33jL)z^Mdqu z))hnr(TAv#u$rhLYKT*aIti_Z_a^cXWhSyBc-< zzQcM&eeJCvDu_Nrm4wwq4N*g!LexoEO*9Y<#0;WI!pikq#A`YdTCb}^5xRbBd|S1T zTd1$MBe-q25!_98fpMRHbiOSlubCEOFZWpY;Xx_KunXclGiQrx$qVinZUOfY zZjqdoyx>mYmT*ttmdRPU-@2o`3jI~+FV%VdmU8`upuY~F?THyye5?sH%&I|oj4&`(GmU8`uqrVFMRp>9(!CAR}!_i-b{wnmB z>fo&A++PPeHhx|DtI%JngR^qK<&|GHyzLje>1wnrm`l~caSjkH(TzPq&7y7HvU#c@NDS5%sUxofE^q1<)E4c+6{Z;6%LVu~w zypmhO(O-rBD)g7?%nMF;T6dI}M&-4pzf|Y_mQ?4mHProUACo!&!rE?ZX+^w*mH(o7Im6I{PEdLQ(c>L9Ep z8umedt?4h#1YzZVON8#XH0plK{k5jQRC7K=b^cn9;QDa%*P8y)d~jBCT)*^gyg&MD zO@FBl&T7v6^_t$3Ir?i&f2j`6s`KH6^LlWxb4T}E7tZUui(N*i^x&dm-YI=|(Pwlv z4=!rvoy~U_r;JYI!9~No6Z!69rt$8@q29q=?Ne!}){(sM=f9`g?;}+AM;HG5cl8?P z{P~|<`19XW9bA0=yBGfaclDa){P~|<`19XW9bA0=yBGfacl933`SU-!@aMm$I=J}! z@9Xc!UtJ!5;y)u_9{;^W>2<}+%j0iX`un;3mHw<9Tf)30`A>N|1Bli(Ma(?!W>jeZ zzli<+BKH4_ZvQG`|L?~BEqb+gWB(TI?cHwwQN&E_Uo$FRtTsM8WH@9+Q2IY^v?Byylo4)6De;Sa+fcD@VzdHD12=bi5YzYV_)zwLY%^1nUW+0xsv zI9W+77z*Y1?NJqe6@JzEF7WH{>+tK&cY)u8--O?Ez6<%E%=YbD{P`uZvMBI};Sa+f zcD@VzdHD12=bi5YzYV_)zwLY%@^$>*i{t-Z9RK&atj(_;`@aLWH zB94FfZTM~HyNKhz8^?b)j{k0V{8i}v>G+3Vg;B&S z`m68FUFG-Y*LCG?dr;dN^}YFZuBoW5y6psF0&xs6Ny2Jk3NeK^ftV&?)phx3=eo|w z8g)iK+SRD<&97@Mr0SY_R6$e_eTXUvtBD$-hB$?&ldzg-AR34nM3aP7*X7y12z_rZ zPv4ts)c59c_}*NqE9h(pF@(4VF-*d0Vh%BfID?ocVKvc0v=CoIv`JX?y}5Fk`)Ccw zW&c$!RQbKRkLiG12IQieTu>eL0l8@Oe#k|25Shz>Tr`>>7u7*zE}P_{QMqiAi)wN~ zbxb$OMWYFFQ5{6)vPmu)O^}P~ATpOta?xmlTvP{87mX&! zMRgFF%O1ICG(j$^gUDR=$VHSUI{y7BdCzx@F7q7i}q;uF#45McWIk7ua@Sy$*8$HVJGJ z*l}Q!4s!uE4Qv|NNnq0sb0O@Dqn#_d8tZQ4impcA9_?CmQ*uRdb%idPUmR6|Re|*b zt2)dDSRGg$*lA#Ohq(Z20&4=B1=e(!3t^XL`^I#owExNMibdB+xj*iTb7RB6hJjrR zY}jEgz~+I?13L?B-eE4l+Q8btz7DMIFc-pJ3?oyCGaW{z+KNmmoWd|Nm4HR2+Dfd; zbQqaRz#>y^CDvs+j7%k9k*T&4>oR>KGL<;fHzHGQMWz%^;f=^t0v4HSE3q!qHzHFB zSY)cL#JWu1h)gA5k*T&4>oV;}rV?SF^dnPkMWz%^p&yw_z#>y^CDvuyk4zoV;}rV_BoR9lI4nYJ4roVgD-KG5M+gMOgD`*g)q8@=#*;rBY<1^y)bN%)h_cY!|* ze;WR@^Ig~<#_LP``jV?WxlqhmO#J>ZUSE>F3;cNfVZ6R1eHZxg`onmAN%}7AuQsmx z^Gm$ER=N+-+t5}lFAA^eRWC5zhj>djBF4BA=?XC2i`duAh(&iJcDWtt3NYP}*w-D2 zMYkk&xhLrgVPC9tSE9u%QH0;FbYH?_u`bmNEGylb*w?*@MK>pQxjX3!Fa4G7 zPweXk#iBbDyWFC51(IWBOZw{ZCdOTJ)Cy-$rzW*Ys)> z*eI}@fsH!M1=u36MPLsDTXdKUuw`J&z@7xQ>@XL?^t8<3mH6S|U@4GcA#+wjxssr%)nO30P#Rt;Ae_MW!V( zEs?3V5_16-nU=`3M5fwG%!M;;H*TDTxL35*ou^bhwb2W|cLTrI`7ZD$;ZMS!biNDx zY53Fdr=9P@{xDu&;{8jy^OTCY{dj!|zF&6VpbPwX{b9Vmq&rV_e!TuLUSHCkr|{eR zH}nL1gD2PIv3WKEdA5lah{uscnsVg4HkcKP9AoKGl0*G;s{!_hG_nLhpjn z#0iAoi3uxDus3*uy`g8Aqg{=9g1w=2l*$tpkiTR^vU@wsEIiQx$KdPW?~vnnIOpJ{{eN=$*KSV literal 0 HcmV?d00001 diff --git a/bddisasm_test/avx512/avx512dq_64.asm b/bddisasm_test/avx512/avx512dq_64.asm new file mode 100644 index 0000000..a0e31c9 --- /dev/null +++ b/bddisasm_test/avx512/avx512dq_64.asm @@ -0,0 +1,1926 @@ + bits 64 + + kaddb k3, k7, k1 + kaddw k3, k7, k1 + kandb k3, k7, k1 + kandnb k3, k7, k1 + kmovb k3, [rbx] + kmovb k3, [rbx+rsi*8+256] + kmovb k3, [rbx+rsi*8-256] + kmovb k3, k1 + kmovb k3, [rbx] + kmovb [rbx], k3 + kmovb [rbx+rsi*8+256], k3 + kmovb [rbx+rsi*8-256], k3 + kmovb k3, ecx + kmovb ecx, k1 + knotb k3, k1 + korb k3, k7, k1 + kortestb k3, k1 + kshiftlb k3, k1, 10 + kshiftrb k3, k1, 10 + ktestb k3, k1 + ktestw k3, k1 + kxnorb k3, k7, k1 + kxorb k3, k7, k1 + vandnpd xmm2, xmm7, xmm0 + vandnpd xmm2, xmm7, [rbx] + vandnpd xmm2, xmm7, [rbx]{1to2} + vandnpd xmm2, xmm7, [rbx+r11*8+256] + vandnpd xmm2, xmm7, [rbx+r11*8-256] + vandnpd xmm2{k5}, xmm7, xmm0 + vandnpd xmm2{k5}, xmm7, [rbx] + vandnpd xmm2{k5}, xmm7, [rbx]{1to2} + vandnpd xmm2{k5}, xmm7, [rbx+r11*8+256] + vandnpd xmm2{k5}, xmm7, [rbx+r11*8-256] + vandnpd xmm2{z}, xmm7, xmm0 + vandnpd xmm2{z}, xmm7, [rbx] + vandnpd xmm2{z}, xmm7, [rbx]{1to2} + vandnpd xmm2{z}, xmm7, [rbx+r11*8+256] + vandnpd xmm2{z}, xmm7, [rbx+r11*8-256] + vandnpd xmm2{k5}{z}, xmm7, xmm0 + vandnpd xmm2{k5}{z}, xmm7, [rbx] + vandnpd xmm2{k5}{z}, xmm7, [rbx]{1to2} + vandnpd xmm2{k5}{z}, xmm7, [rbx+r11*8+256] + vandnpd xmm2{k5}{z}, xmm7, [rbx+r11*8-256] + vandnpd ymm16, ymm13, ymm15 + vandnpd ymm16, ymm13, [rbx] + vandnpd ymm16, ymm13, [rbx]{1to4} + vandnpd ymm16, ymm13, [rbx+r11*8+256] + vandnpd ymm16, ymm13, [rbx+r11*8-256] + vandnpd ymm16{k5}, ymm13, ymm15 + vandnpd ymm16{k5}, ymm13, [rbx] + vandnpd ymm16{k5}, ymm13, [rbx]{1to4} + vandnpd ymm16{k5}, ymm13, [rbx+r11*8+256] + vandnpd ymm16{k5}, ymm13, [rbx+r11*8-256] + vandnpd ymm16{z}, ymm13, ymm15 + vandnpd ymm16{z}, ymm13, [rbx] + vandnpd ymm16{z}, ymm13, [rbx]{1to4} + vandnpd ymm16{z}, ymm13, [rbx+r11*8+256] + vandnpd ymm16{z}, ymm13, [rbx+r11*8-256] + vandnpd ymm16{k5}{z}, ymm13, ymm15 + vandnpd ymm16{k5}{z}, ymm13, [rbx] + vandnpd ymm16{k5}{z}, ymm13, [rbx]{1to4} + vandnpd ymm16{k5}{z}, ymm13, [rbx+r11*8+256] + vandnpd ymm16{k5}{z}, ymm13, [rbx+r11*8-256] + vandnpd zmm24, zmm24, zmm31 + vandnpd zmm24, zmm24, [rbx] + vandnpd zmm24, zmm24, [rbx]{1to8} + vandnpd zmm24, zmm24, [rbx+r11*8+256] + vandnpd zmm24, zmm24, [rbx+r11*8-256] + vandnpd zmm24{k5}, zmm24, zmm31 + vandnpd zmm24{k5}, zmm24, [rbx] + vandnpd zmm24{k5}, zmm24, [rbx]{1to8} + vandnpd zmm24{k5}, zmm24, [rbx+r11*8+256] + vandnpd zmm24{k5}, zmm24, [rbx+r11*8-256] + vandnpd zmm24{z}, zmm24, zmm31 + vandnpd zmm24{z}, zmm24, [rbx] + vandnpd zmm24{z}, zmm24, [rbx]{1to8} + vandnpd zmm24{z}, zmm24, [rbx+r11*8+256] + vandnpd zmm24{z}, zmm24, [rbx+r11*8-256] + vandnpd zmm24{k5}{z}, zmm24, zmm31 + vandnpd zmm24{k5}{z}, zmm24, [rbx] + vandnpd zmm24{k5}{z}, zmm24, [rbx]{1to8} + vandnpd zmm24{k5}{z}, zmm24, [rbx+r11*8+256] + vandnpd zmm24{k5}{z}, zmm24, [rbx+r11*8-256] + vandnps xmm2, xmm7, xmm0 + vandnps xmm2, xmm7, [rbx] + vandnps xmm2, xmm7, [rbx]{1to4} + vandnps xmm2, xmm7, [rbx+r11*8+256] + vandnps xmm2, xmm7, [rbx+r11*8-256] + vandnps xmm2{k5}, xmm7, xmm0 + vandnps xmm2{k5}, xmm7, [rbx] + vandnps xmm2{k5}, xmm7, [rbx]{1to4} + vandnps xmm2{k5}, xmm7, [rbx+r11*8+256] + vandnps xmm2{k5}, xmm7, [rbx+r11*8-256] + vandnps xmm2{z}, xmm7, xmm0 + vandnps xmm2{z}, xmm7, [rbx] + vandnps xmm2{z}, xmm7, [rbx]{1to4} + vandnps xmm2{z}, xmm7, [rbx+r11*8+256] + vandnps xmm2{z}, xmm7, [rbx+r11*8-256] + vandnps xmm2{k5}{z}, xmm7, xmm0 + vandnps xmm2{k5}{z}, xmm7, [rbx] + vandnps xmm2{k5}{z}, xmm7, [rbx]{1to4} + vandnps xmm2{k5}{z}, xmm7, [rbx+r11*8+256] + vandnps xmm2{k5}{z}, xmm7, [rbx+r11*8-256] + vandnps ymm16, ymm13, ymm15 + vandnps ymm16, ymm13, [rbx] + vandnps ymm16, ymm13, [rbx]{1to8} + vandnps ymm16, ymm13, [rbx+r11*8+256] + vandnps ymm16, ymm13, [rbx+r11*8-256] + vandnps ymm16{k5}, ymm13, ymm15 + vandnps ymm16{k5}, ymm13, [rbx] + vandnps ymm16{k5}, ymm13, [rbx]{1to8} + vandnps ymm16{k5}, ymm13, [rbx+r11*8+256] + vandnps ymm16{k5}, ymm13, [rbx+r11*8-256] + vandnps ymm16{z}, ymm13, ymm15 + vandnps ymm16{z}, ymm13, [rbx] + vandnps ymm16{z}, ymm13, [rbx]{1to8} + vandnps ymm16{z}, ymm13, [rbx+r11*8+256] + vandnps ymm16{z}, ymm13, [rbx+r11*8-256] + vandnps ymm16{k5}{z}, ymm13, ymm15 + vandnps ymm16{k5}{z}, ymm13, [rbx] + vandnps ymm16{k5}{z}, ymm13, [rbx]{1to8} + vandnps ymm16{k5}{z}, ymm13, [rbx+r11*8+256] + vandnps ymm16{k5}{z}, ymm13, [rbx+r11*8-256] + vandnps zmm24, zmm24, zmm31 + vandnps zmm24, zmm24, [rbx] + vandnps zmm24, zmm24, [rbx]{1to16} + vandnps zmm24, zmm24, [rbx+r11*8+256] + vandnps zmm24, zmm24, [rbx+r11*8-256] + vandnps zmm24{k5}, zmm24, zmm31 + vandnps zmm24{k5}, zmm24, [rbx] + vandnps zmm24{k5}, zmm24, [rbx]{1to16} + vandnps zmm24{k5}, zmm24, [rbx+r11*8+256] + vandnps zmm24{k5}, zmm24, [rbx+r11*8-256] + vandnps zmm24{z}, zmm24, zmm31 + vandnps zmm24{z}, zmm24, [rbx] + vandnps zmm24{z}, zmm24, [rbx]{1to16} + vandnps zmm24{z}, zmm24, [rbx+r11*8+256] + vandnps zmm24{z}, zmm24, [rbx+r11*8-256] + vandnps zmm24{k5}{z}, zmm24, zmm31 + vandnps zmm24{k5}{z}, zmm24, [rbx] + vandnps zmm24{k5}{z}, zmm24, [rbx]{1to16} + vandnps zmm24{k5}{z}, zmm24, [rbx+r11*8+256] + vandnps zmm24{k5}{z}, zmm24, [rbx+r11*8-256] + vandpd xmm2, xmm7, xmm0 + vandpd xmm2, xmm7, [rbx] + vandpd xmm2, xmm7, [rbx]{1to2} + vandpd xmm2, xmm7, [rbx+r11*8+256] + vandpd xmm2, xmm7, [rbx+r11*8-256] + vandpd xmm2{k5}, xmm7, xmm0 + vandpd xmm2{k5}, xmm7, [rbx] + vandpd xmm2{k5}, xmm7, [rbx]{1to2} + vandpd xmm2{k5}, xmm7, [rbx+r11*8+256] + vandpd xmm2{k5}, xmm7, [rbx+r11*8-256] + vandpd xmm2{z}, xmm7, xmm0 + vandpd xmm2{z}, xmm7, [rbx] + vandpd xmm2{z}, xmm7, [rbx]{1to2} + vandpd xmm2{z}, xmm7, [rbx+r11*8+256] + vandpd xmm2{z}, xmm7, [rbx+r11*8-256] + vandpd xmm2{k5}{z}, xmm7, xmm0 + vandpd xmm2{k5}{z}, xmm7, [rbx] + vandpd xmm2{k5}{z}, xmm7, [rbx]{1to2} + vandpd xmm2{k5}{z}, xmm7, [rbx+r11*8+256] + vandpd xmm2{k5}{z}, xmm7, [rbx+r11*8-256] + vandpd ymm16, ymm13, ymm15 + vandpd ymm16, ymm13, [rbx] + vandpd ymm16, ymm13, [rbx]{1to4} + vandpd ymm16, ymm13, [rbx+r11*8+256] + vandpd ymm16, ymm13, [rbx+r11*8-256] + vandpd ymm16{k5}, ymm13, ymm15 + vandpd ymm16{k5}, ymm13, [rbx] + vandpd ymm16{k5}, ymm13, [rbx]{1to4} + vandpd ymm16{k5}, ymm13, [rbx+r11*8+256] + vandpd ymm16{k5}, ymm13, [rbx+r11*8-256] + vandpd ymm16{z}, ymm13, ymm15 + vandpd ymm16{z}, ymm13, [rbx] + vandpd ymm16{z}, ymm13, [rbx]{1to4} + vandpd ymm16{z}, ymm13, [rbx+r11*8+256] + vandpd ymm16{z}, ymm13, [rbx+r11*8-256] + vandpd ymm16{k5}{z}, ymm13, ymm15 + vandpd ymm16{k5}{z}, ymm13, [rbx] + vandpd ymm16{k5}{z}, ymm13, [rbx]{1to4} + vandpd ymm16{k5}{z}, ymm13, [rbx+r11*8+256] + vandpd ymm16{k5}{z}, ymm13, [rbx+r11*8-256] + vandpd zmm24, zmm24, zmm31 + vandpd zmm24, zmm24, [rbx] + vandpd zmm24, zmm24, [rbx]{1to8} + vandpd zmm24, zmm24, [rbx+r11*8+256] + vandpd zmm24, zmm24, [rbx+r11*8-256] + vandpd zmm24{k5}, zmm24, zmm31 + vandpd zmm24{k5}, zmm24, [rbx] + vandpd zmm24{k5}, zmm24, [rbx]{1to8} + vandpd zmm24{k5}, zmm24, [rbx+r11*8+256] + vandpd zmm24{k5}, zmm24, [rbx+r11*8-256] + vandpd zmm24{z}, zmm24, zmm31 + vandpd zmm24{z}, zmm24, [rbx] + vandpd zmm24{z}, zmm24, [rbx]{1to8} + vandpd zmm24{z}, zmm24, [rbx+r11*8+256] + vandpd zmm24{z}, zmm24, [rbx+r11*8-256] + vandpd zmm24{k5}{z}, zmm24, zmm31 + vandpd zmm24{k5}{z}, zmm24, [rbx] + vandpd zmm24{k5}{z}, zmm24, [rbx]{1to8} + vandpd zmm24{k5}{z}, zmm24, [rbx+r11*8+256] + vandpd zmm24{k5}{z}, zmm24, [rbx+r11*8-256] + vandps xmm2, xmm7, xmm0 + vandps xmm2, xmm7, [rbx] + vandps xmm2, xmm7, [rbx]{1to4} + vandps xmm2, xmm7, [rbx+r11*8+256] + vandps xmm2, xmm7, [rbx+r11*8-256] + vandps xmm2{k5}, xmm7, xmm0 + vandps xmm2{k5}, xmm7, [rbx] + vandps xmm2{k5}, xmm7, [rbx]{1to4} + vandps xmm2{k5}, xmm7, [rbx+r11*8+256] + vandps xmm2{k5}, xmm7, [rbx+r11*8-256] + vandps xmm2{z}, xmm7, xmm0 + vandps xmm2{z}, xmm7, [rbx] + vandps xmm2{z}, xmm7, [rbx]{1to4} + vandps xmm2{z}, xmm7, [rbx+r11*8+256] + vandps xmm2{z}, xmm7, [rbx+r11*8-256] + vandps xmm2{k5}{z}, xmm7, xmm0 + vandps xmm2{k5}{z}, xmm7, [rbx] + vandps xmm2{k5}{z}, xmm7, [rbx]{1to4} + vandps xmm2{k5}{z}, xmm7, [rbx+r11*8+256] + vandps xmm2{k5}{z}, xmm7, [rbx+r11*8-256] + vandps ymm16, ymm13, ymm15 + vandps ymm16, ymm13, [rbx] + vandps ymm16, ymm13, [rbx]{1to8} + vandps ymm16, ymm13, [rbx+r11*8+256] + vandps ymm16, ymm13, [rbx+r11*8-256] + vandps ymm16{k5}, ymm13, ymm15 + vandps ymm16{k5}, ymm13, [rbx] + vandps ymm16{k5}, ymm13, [rbx]{1to8} + vandps ymm16{k5}, ymm13, [rbx+r11*8+256] + vandps ymm16{k5}, ymm13, [rbx+r11*8-256] + vandps ymm16{z}, ymm13, ymm15 + vandps ymm16{z}, ymm13, [rbx] + vandps ymm16{z}, ymm13, [rbx]{1to8} + vandps ymm16{z}, ymm13, [rbx+r11*8+256] + vandps ymm16{z}, ymm13, [rbx+r11*8-256] + vandps ymm16{k5}{z}, ymm13, ymm15 + vandps ymm16{k5}{z}, ymm13, [rbx] + vandps ymm16{k5}{z}, ymm13, [rbx]{1to8} + vandps ymm16{k5}{z}, ymm13, [rbx+r11*8+256] + vandps ymm16{k5}{z}, ymm13, [rbx+r11*8-256] + vandps zmm24, zmm24, zmm31 + vandps zmm24, zmm24, [rbx] + vandps zmm24, zmm24, [rbx]{1to16} + vandps zmm24, zmm24, [rbx+r11*8+256] + vandps zmm24, zmm24, [rbx+r11*8-256] + vandps zmm24{k5}, zmm24, zmm31 + vandps zmm24{k5}, zmm24, [rbx] + vandps zmm24{k5}, zmm24, [rbx]{1to16} + vandps zmm24{k5}, zmm24, [rbx+r11*8+256] + vandps zmm24{k5}, zmm24, [rbx+r11*8-256] + vandps zmm24{z}, zmm24, zmm31 + vandps zmm24{z}, zmm24, [rbx] + vandps zmm24{z}, zmm24, [rbx]{1to16} + vandps zmm24{z}, zmm24, [rbx+r11*8+256] + vandps zmm24{z}, zmm24, [rbx+r11*8-256] + vandps zmm24{k5}{z}, zmm24, zmm31 + vandps zmm24{k5}{z}, zmm24, [rbx] + vandps zmm24{k5}{z}, zmm24, [rbx]{1to16} + vandps zmm24{k5}{z}, zmm24, [rbx+r11*8+256] + vandps zmm24{k5}{z}, zmm24, [rbx+r11*8-256] + vbroadcastf32x2 ymm16, xmm0 + vbroadcastf32x2 ymm16, [rbx] + vbroadcastf32x2 ymm16, [rbx+r11*8+256] + vbroadcastf32x2 ymm16, [rbx+r11*8-256] + vbroadcastf32x2 ymm16{k5}, xmm0 + vbroadcastf32x2 ymm16{k5}, [rbx] + vbroadcastf32x2 ymm16{k5}, [rbx+r11*8+256] + vbroadcastf32x2 ymm16{k5}, [rbx+r11*8-256] + vbroadcastf32x2 ymm16{z}, xmm0 + vbroadcastf32x2 ymm16{z}, [rbx] + vbroadcastf32x2 ymm16{z}, [rbx+r11*8+256] + vbroadcastf32x2 ymm16{z}, [rbx+r11*8-256] + vbroadcastf32x2 ymm16{k5}{z}, xmm0 + vbroadcastf32x2 ymm16{k5}{z}, [rbx] + vbroadcastf32x2 ymm16{k5}{z}, [rbx+r11*8+256] + vbroadcastf32x2 ymm16{k5}{z}, [rbx+r11*8-256] + vbroadcastf32x2 zmm24, xmm0 + vbroadcastf32x2 zmm24, [rbx] + vbroadcastf32x2 zmm24, [rbx+r11*8+256] + vbroadcastf32x2 zmm24, [rbx+r11*8-256] + vbroadcastf32x2 zmm24{k5}, xmm0 + vbroadcastf32x2 zmm24{k5}, [rbx] + vbroadcastf32x2 zmm24{k5}, [rbx+r11*8+256] + vbroadcastf32x2 zmm24{k5}, [rbx+r11*8-256] + vbroadcastf32x2 zmm24{z}, xmm0 + vbroadcastf32x2 zmm24{z}, [rbx] + vbroadcastf32x2 zmm24{z}, [rbx+r11*8+256] + vbroadcastf32x2 zmm24{z}, [rbx+r11*8-256] + vbroadcastf32x2 zmm24{k5}{z}, xmm0 + vbroadcastf32x2 zmm24{k5}{z}, [rbx] + vbroadcastf32x2 zmm24{k5}{z}, [rbx+r11*8+256] + vbroadcastf32x2 zmm24{k5}{z}, [rbx+r11*8-256] + vbroadcastf32x8 zmm24, [rbx] + vbroadcastf32x8 zmm24, [rbx+rsi*8+256] + vbroadcastf32x8 zmm24, [rbx+rsi*8-256] + vbroadcastf32x8 zmm24{k5}, [rbx] + vbroadcastf32x8 zmm24{k5}, [rbx+rsi*8+256] + vbroadcastf32x8 zmm24{k5}, [rbx+rsi*8-256] + vbroadcastf32x8 zmm24{z}, [rbx] + vbroadcastf32x8 zmm24{z}, [rbx+rsi*8+256] + vbroadcastf32x8 zmm24{z}, [rbx+rsi*8-256] + vbroadcastf32x8 zmm24{k5}{z}, [rbx] + vbroadcastf32x8 zmm24{k5}{z}, [rbx+rsi*8+256] + vbroadcastf32x8 zmm24{k5}{z}, [rbx+rsi*8-256] + vbroadcastf64x2 ymm16, [rbx] + vbroadcastf64x2 ymm16, [rbx+rsi*8+256] + vbroadcastf64x2 ymm16, [rbx+rsi*8-256] + vbroadcastf64x2 ymm16{k5}, [rbx] + vbroadcastf64x2 ymm16{k5}, [rbx+rsi*8+256] + vbroadcastf64x2 ymm16{k5}, [rbx+rsi*8-256] + vbroadcastf64x2 ymm16{z}, [rbx] + vbroadcastf64x2 ymm16{z}, [rbx+rsi*8+256] + vbroadcastf64x2 ymm16{z}, [rbx+rsi*8-256] + vbroadcastf64x2 ymm16{k5}{z}, [rbx] + vbroadcastf64x2 ymm16{k5}{z}, [rbx+rsi*8+256] + vbroadcastf64x2 ymm16{k5}{z}, [rbx+rsi*8-256] + vbroadcastf64x2 zmm24, [rbx] + vbroadcastf64x2 zmm24, [rbx+rsi*8+256] + vbroadcastf64x2 zmm24, [rbx+rsi*8-256] + vbroadcastf64x2 zmm24{k5}, [rbx] + vbroadcastf64x2 zmm24{k5}, [rbx+rsi*8+256] + vbroadcastf64x2 zmm24{k5}, [rbx+rsi*8-256] + vbroadcastf64x2 zmm24{z}, [rbx] + vbroadcastf64x2 zmm24{z}, [rbx+rsi*8+256] + vbroadcastf64x2 zmm24{z}, [rbx+rsi*8-256] + vbroadcastf64x2 zmm24{k5}{z}, [rbx] + vbroadcastf64x2 zmm24{k5}{z}, [rbx+rsi*8+256] + vbroadcastf64x2 zmm24{k5}{z}, [rbx+rsi*8-256] + vbroadcasti32x2 xmm2, xmm0 + vbroadcasti32x2 xmm2, [rbx] + vbroadcasti32x2 xmm2, [rbx+r11*8+256] + vbroadcasti32x2 xmm2, [rbx+r11*8-256] + vbroadcasti32x2 xmm2{k5}, xmm0 + vbroadcasti32x2 xmm2{k5}, [rbx] + vbroadcasti32x2 xmm2{k5}, [rbx+r11*8+256] + vbroadcasti32x2 xmm2{k5}, [rbx+r11*8-256] + vbroadcasti32x2 xmm2{z}, xmm0 + vbroadcasti32x2 xmm2{z}, [rbx] + vbroadcasti32x2 xmm2{z}, [rbx+r11*8+256] + vbroadcasti32x2 xmm2{z}, [rbx+r11*8-256] + vbroadcasti32x2 xmm2{k5}{z}, xmm0 + vbroadcasti32x2 xmm2{k5}{z}, [rbx] + vbroadcasti32x2 xmm2{k5}{z}, [rbx+r11*8+256] + vbroadcasti32x2 xmm2{k5}{z}, [rbx+r11*8-256] + vbroadcasti32x2 ymm16, xmm0 + vbroadcasti32x2 ymm16, [rbx] + vbroadcasti32x2 ymm16, [rbx+r11*8+256] + vbroadcasti32x2 ymm16, [rbx+r11*8-256] + vbroadcasti32x2 ymm16{k5}, xmm0 + vbroadcasti32x2 ymm16{k5}, [rbx] + vbroadcasti32x2 ymm16{k5}, [rbx+r11*8+256] + vbroadcasti32x2 ymm16{k5}, [rbx+r11*8-256] + vbroadcasti32x2 ymm16{z}, xmm0 + vbroadcasti32x2 ymm16{z}, [rbx] + vbroadcasti32x2 ymm16{z}, [rbx+r11*8+256] + vbroadcasti32x2 ymm16{z}, [rbx+r11*8-256] + vbroadcasti32x2 ymm16{k5}{z}, xmm0 + vbroadcasti32x2 ymm16{k5}{z}, [rbx] + vbroadcasti32x2 ymm16{k5}{z}, [rbx+r11*8+256] + vbroadcasti32x2 ymm16{k5}{z}, [rbx+r11*8-256] + vbroadcasti32x2 zmm24, xmm0 + vbroadcasti32x2 zmm24, [rbx] + vbroadcasti32x2 zmm24, [rbx+r11*8+256] + vbroadcasti32x2 zmm24, [rbx+r11*8-256] + vbroadcasti32x2 zmm24{k5}, xmm0 + vbroadcasti32x2 zmm24{k5}, [rbx] + vbroadcasti32x2 zmm24{k5}, [rbx+r11*8+256] + vbroadcasti32x2 zmm24{k5}, [rbx+r11*8-256] + vbroadcasti32x2 zmm24{z}, xmm0 + vbroadcasti32x2 zmm24{z}, [rbx] + vbroadcasti32x2 zmm24{z}, [rbx+r11*8+256] + vbroadcasti32x2 zmm24{z}, [rbx+r11*8-256] + vbroadcasti32x2 zmm24{k5}{z}, xmm0 + vbroadcasti32x2 zmm24{k5}{z}, [rbx] + vbroadcasti32x2 zmm24{k5}{z}, [rbx+r11*8+256] + vbroadcasti32x2 zmm24{k5}{z}, [rbx+r11*8-256] + vbroadcasti32x8 zmm24, [rbx] + vbroadcasti32x8 zmm24, [rbx+rsi*8+256] + vbroadcasti32x8 zmm24, [rbx+rsi*8-256] + vbroadcasti32x8 zmm24{k5}, [rbx] + vbroadcasti32x8 zmm24{k5}, [rbx+rsi*8+256] + vbroadcasti32x8 zmm24{k5}, [rbx+rsi*8-256] + vbroadcasti32x8 zmm24{z}, [rbx] + vbroadcasti32x8 zmm24{z}, [rbx+rsi*8+256] + vbroadcasti32x8 zmm24{z}, [rbx+rsi*8-256] + vbroadcasti32x8 zmm24{k5}{z}, [rbx] + vbroadcasti32x8 zmm24{k5}{z}, [rbx+rsi*8+256] + vbroadcasti32x8 zmm24{k5}{z}, [rbx+rsi*8-256] + vbroadcasti64x2 ymm16, [rbx] + vbroadcasti64x2 ymm16, [rbx+rsi*8+256] + vbroadcasti64x2 ymm16, [rbx+rsi*8-256] + vbroadcasti64x2 ymm16{k5}, [rbx] + vbroadcasti64x2 ymm16{k5}, [rbx+rsi*8+256] + vbroadcasti64x2 ymm16{k5}, [rbx+rsi*8-256] + vbroadcasti64x2 ymm16{z}, [rbx] + vbroadcasti64x2 ymm16{z}, [rbx+rsi*8+256] + vbroadcasti64x2 ymm16{z}, [rbx+rsi*8-256] + vbroadcasti64x2 ymm16{k5}{z}, [rbx] + vbroadcasti64x2 ymm16{k5}{z}, [rbx+rsi*8+256] + vbroadcasti64x2 ymm16{k5}{z}, [rbx+rsi*8-256] + vbroadcasti64x2 zmm24, [rbx] + vbroadcasti64x2 zmm24, [rbx+rsi*8+256] + vbroadcasti64x2 zmm24, [rbx+rsi*8-256] + vbroadcasti64x2 zmm24{k5}, [rbx] + vbroadcasti64x2 zmm24{k5}, [rbx+rsi*8+256] + vbroadcasti64x2 zmm24{k5}, [rbx+rsi*8-256] + vbroadcasti64x2 zmm24{z}, [rbx] + vbroadcasti64x2 zmm24{z}, [rbx+rsi*8+256] + vbroadcasti64x2 zmm24{z}, [rbx+rsi*8-256] + vbroadcasti64x2 zmm24{k5}{z}, [rbx] + vbroadcasti64x2 zmm24{k5}{z}, [rbx+rsi*8+256] + vbroadcasti64x2 zmm24{k5}{z}, [rbx+rsi*8-256] + vcvtpd2qq xmm2, xmm0 + vcvtpd2qq xmm2, [rbx] + vcvtpd2qq xmm2, [rbx]{1to2} + vcvtpd2qq xmm2, [rbx+r11*8+256] + vcvtpd2qq xmm2, [rbx+r11*8-256] + vcvtpd2qq xmm2{k5}, xmm0 + vcvtpd2qq xmm2{k5}, [rbx] + vcvtpd2qq xmm2{k5}, [rbx]{1to2} + vcvtpd2qq xmm2{k5}, [rbx+r11*8+256] + vcvtpd2qq xmm2{k5}, [rbx+r11*8-256] + vcvtpd2qq xmm2{z}, xmm0 + vcvtpd2qq xmm2{z}, [rbx] + vcvtpd2qq xmm2{z}, [rbx]{1to2} + vcvtpd2qq xmm2{z}, [rbx+r11*8+256] + vcvtpd2qq xmm2{z}, [rbx+r11*8-256] + vcvtpd2qq xmm2{k5}{z}, xmm0 + vcvtpd2qq xmm2{k5}{z}, [rbx] + vcvtpd2qq xmm2{k5}{z}, [rbx]{1to2} + vcvtpd2qq xmm2{k5}{z}, [rbx+r11*8+256] + vcvtpd2qq xmm2{k5}{z}, [rbx+r11*8-256] + vcvtpd2qq ymm16, ymm15 + vcvtpd2qq ymm16, [rbx] + vcvtpd2qq ymm16, [rbx]{1to4} + vcvtpd2qq ymm16, [rbx+r11*8+256] + vcvtpd2qq ymm16, [rbx+r11*8-256] + vcvtpd2qq ymm16{k5}, ymm15 + vcvtpd2qq ymm16{k5}, [rbx] + vcvtpd2qq ymm16{k5}, [rbx]{1to4} + vcvtpd2qq ymm16{k5}, [rbx+r11*8+256] + vcvtpd2qq ymm16{k5}, [rbx+r11*8-256] + vcvtpd2qq ymm16{z}, ymm15 + vcvtpd2qq ymm16{z}, [rbx] + vcvtpd2qq ymm16{z}, [rbx]{1to4} + vcvtpd2qq ymm16{z}, [rbx+r11*8+256] + vcvtpd2qq ymm16{z}, [rbx+r11*8-256] + vcvtpd2qq ymm16{k5}{z}, ymm15 + vcvtpd2qq ymm16{k5}{z}, [rbx] + vcvtpd2qq ymm16{k5}{z}, [rbx]{1to4} + vcvtpd2qq ymm16{k5}{z}, [rbx+r11*8+256] + vcvtpd2qq ymm16{k5}{z}, [rbx+r11*8-256] + vcvtpd2qq zmm24, zmm31 + vcvtpd2qq zmm24, zmm31, {rd-sae} + vcvtpd2qq zmm24, [rbx] + vcvtpd2qq zmm24, [rbx]{1to8} + vcvtpd2qq zmm24, [rbx+r11*8+256] + vcvtpd2qq zmm24, [rbx+r11*8-256] + vcvtpd2qq zmm24{k5}, zmm31 + vcvtpd2qq zmm24{k5}, zmm31, {rd-sae} + vcvtpd2qq zmm24{k5}, [rbx] + vcvtpd2qq zmm24{k5}, [rbx]{1to8} + vcvtpd2qq zmm24{k5}, [rbx+r11*8+256] + vcvtpd2qq zmm24{k5}, [rbx+r11*8-256] + vcvtpd2qq zmm24{z}, zmm31 + vcvtpd2qq zmm24{z}, zmm31, {rd-sae} + vcvtpd2qq zmm24{z}, [rbx] + vcvtpd2qq zmm24{z}, [rbx]{1to8} + vcvtpd2qq zmm24{z}, [rbx+r11*8+256] + vcvtpd2qq zmm24{z}, [rbx+r11*8-256] + vcvtpd2qq zmm24{k5}{z}, zmm31 + vcvtpd2qq zmm24{k5}{z}, zmm31, {rd-sae} + vcvtpd2qq zmm24{k5}{z}, [rbx] + vcvtpd2qq zmm24{k5}{z}, [rbx]{1to8} + vcvtpd2qq zmm24{k5}{z}, [rbx+r11*8+256] + vcvtpd2qq zmm24{k5}{z}, [rbx+r11*8-256] + vcvtpd2uqq xmm2, xmm0 + vcvtpd2uqq xmm2, [rbx] + vcvtpd2uqq xmm2, [rbx]{1to2} + vcvtpd2uqq xmm2, [rbx+r11*8+256] + vcvtpd2uqq xmm2, [rbx+r11*8-256] + vcvtpd2uqq xmm2{k5}, xmm0 + vcvtpd2uqq xmm2{k5}, [rbx] + vcvtpd2uqq xmm2{k5}, [rbx]{1to2} + vcvtpd2uqq xmm2{k5}, [rbx+r11*8+256] + vcvtpd2uqq xmm2{k5}, [rbx+r11*8-256] + vcvtpd2uqq xmm2{z}, xmm0 + vcvtpd2uqq xmm2{z}, [rbx] + vcvtpd2uqq xmm2{z}, [rbx]{1to2} + vcvtpd2uqq xmm2{z}, [rbx+r11*8+256] + vcvtpd2uqq xmm2{z}, [rbx+r11*8-256] + vcvtpd2uqq xmm2{k5}{z}, xmm0 + vcvtpd2uqq xmm2{k5}{z}, [rbx] + vcvtpd2uqq xmm2{k5}{z}, [rbx]{1to2} + vcvtpd2uqq xmm2{k5}{z}, [rbx+r11*8+256] + vcvtpd2uqq xmm2{k5}{z}, [rbx+r11*8-256] + vcvtpd2uqq ymm16, ymm15 + vcvtpd2uqq ymm16, [rbx] + vcvtpd2uqq ymm16, [rbx]{1to4} + vcvtpd2uqq ymm16, [rbx+r11*8+256] + vcvtpd2uqq ymm16, [rbx+r11*8-256] + vcvtpd2uqq ymm16{k5}, ymm15 + vcvtpd2uqq ymm16{k5}, [rbx] + vcvtpd2uqq ymm16{k5}, [rbx]{1to4} + vcvtpd2uqq ymm16{k5}, [rbx+r11*8+256] + vcvtpd2uqq ymm16{k5}, [rbx+r11*8-256] + vcvtpd2uqq ymm16{z}, ymm15 + vcvtpd2uqq ymm16{z}, [rbx] + vcvtpd2uqq ymm16{z}, [rbx]{1to4} + vcvtpd2uqq ymm16{z}, [rbx+r11*8+256] + vcvtpd2uqq ymm16{z}, [rbx+r11*8-256] + vcvtpd2uqq ymm16{k5}{z}, ymm15 + vcvtpd2uqq ymm16{k5}{z}, [rbx] + vcvtpd2uqq ymm16{k5}{z}, [rbx]{1to4} + vcvtpd2uqq ymm16{k5}{z}, [rbx+r11*8+256] + vcvtpd2uqq ymm16{k5}{z}, [rbx+r11*8-256] + vcvtpd2uqq zmm24, zmm31 + vcvtpd2uqq zmm24, zmm31, {rd-sae} + vcvtpd2uqq zmm24, [rbx] + vcvtpd2uqq zmm24, [rbx]{1to8} + vcvtpd2uqq zmm24, [rbx+r11*8+256] + vcvtpd2uqq zmm24, [rbx+r11*8-256] + vcvtpd2uqq zmm24{k5}, zmm31 + vcvtpd2uqq zmm24{k5}, zmm31, {rd-sae} + vcvtpd2uqq zmm24{k5}, [rbx] + vcvtpd2uqq zmm24{k5}, [rbx]{1to8} + vcvtpd2uqq zmm24{k5}, [rbx+r11*8+256] + vcvtpd2uqq zmm24{k5}, [rbx+r11*8-256] + vcvtpd2uqq zmm24{z}, zmm31 + vcvtpd2uqq zmm24{z}, zmm31, {rd-sae} + vcvtpd2uqq zmm24{z}, [rbx] + vcvtpd2uqq zmm24{z}, [rbx]{1to8} + vcvtpd2uqq zmm24{z}, [rbx+r11*8+256] + vcvtpd2uqq zmm24{z}, [rbx+r11*8-256] + vcvtpd2uqq zmm24{k5}{z}, zmm31 + vcvtpd2uqq zmm24{k5}{z}, zmm31, {rd-sae} + vcvtpd2uqq zmm24{k5}{z}, [rbx] + vcvtpd2uqq zmm24{k5}{z}, [rbx]{1to8} + vcvtpd2uqq zmm24{k5}{z}, [rbx+r11*8+256] + vcvtpd2uqq zmm24{k5}{z}, [rbx+r11*8-256] + vcvtps2qq xmm2, xmm0 + vcvtps2qq xmm2, [rbx] + vcvtps2qq xmm2, [rbx]{1to2} + vcvtps2qq xmm2, [rbx+r11*8+256] + vcvtps2qq xmm2, [rbx+r11*8-256] + vcvtps2qq xmm2{k5}, xmm0 + vcvtps2qq xmm2{k5}, [rbx] + vcvtps2qq xmm2{k5}, [rbx]{1to2} + vcvtps2qq xmm2{k5}, [rbx+r11*8+256] + vcvtps2qq xmm2{k5}, [rbx+r11*8-256] + vcvtps2qq xmm2{z}, xmm0 + vcvtps2qq xmm2{z}, [rbx] + vcvtps2qq xmm2{z}, [rbx]{1to2} + vcvtps2qq xmm2{z}, [rbx+r11*8+256] + vcvtps2qq xmm2{z}, [rbx+r11*8-256] + vcvtps2qq xmm2{k5}{z}, xmm0 + vcvtps2qq xmm2{k5}{z}, [rbx] + vcvtps2qq xmm2{k5}{z}, [rbx]{1to2} + vcvtps2qq xmm2{k5}{z}, [rbx+r11*8+256] + vcvtps2qq xmm2{k5}{z}, [rbx+r11*8-256] + vcvtps2qq ymm16, xmm0 + vcvtps2qq ymm16, [rbx] + vcvtps2qq ymm16, [rbx]{1to4} + vcvtps2qq ymm16, [rbx+r11*8+256] + vcvtps2qq ymm16, [rbx+r11*8-256] + vcvtps2qq ymm16{k5}, xmm0 + vcvtps2qq ymm16{k5}, [rbx] + vcvtps2qq ymm16{k5}, [rbx]{1to4} + vcvtps2qq ymm16{k5}, [rbx+r11*8+256] + vcvtps2qq ymm16{k5}, [rbx+r11*8-256] + vcvtps2qq ymm16{z}, xmm0 + vcvtps2qq ymm16{z}, [rbx] + vcvtps2qq ymm16{z}, [rbx]{1to4} + vcvtps2qq ymm16{z}, [rbx+r11*8+256] + vcvtps2qq ymm16{z}, [rbx+r11*8-256] + vcvtps2qq ymm16{k5}{z}, xmm0 + vcvtps2qq ymm16{k5}{z}, [rbx] + vcvtps2qq ymm16{k5}{z}, [rbx]{1to4} + vcvtps2qq ymm16{k5}{z}, [rbx+r11*8+256] + vcvtps2qq ymm16{k5}{z}, [rbx+r11*8-256] + vcvtps2qq zmm24, ymm15 + vcvtps2qq zmm24, ymm15, {rd-sae} + vcvtps2qq zmm24, [rbx] + vcvtps2qq zmm24, [rbx]{1to8} + vcvtps2qq zmm24, [rbx+r11*8+256] + vcvtps2qq zmm24, [rbx+r11*8-256] + vcvtps2qq zmm24{k5}, ymm15 + vcvtps2qq zmm24{k5}, ymm15, {rd-sae} + vcvtps2qq zmm24{k5}, [rbx] + vcvtps2qq zmm24{k5}, [rbx]{1to8} + vcvtps2qq zmm24{k5}, [rbx+r11*8+256] + vcvtps2qq zmm24{k5}, [rbx+r11*8-256] + vcvtps2qq zmm24{z}, ymm15 + vcvtps2qq zmm24{z}, ymm15, {rd-sae} + vcvtps2qq zmm24{z}, [rbx] + vcvtps2qq zmm24{z}, [rbx]{1to8} + vcvtps2qq zmm24{z}, [rbx+r11*8+256] + vcvtps2qq zmm24{z}, [rbx+r11*8-256] + vcvtps2qq zmm24{k5}{z}, ymm15 + vcvtps2qq zmm24{k5}{z}, ymm15, {rd-sae} + vcvtps2qq zmm24{k5}{z}, [rbx] + vcvtps2qq zmm24{k5}{z}, [rbx]{1to8} + vcvtps2qq zmm24{k5}{z}, [rbx+r11*8+256] + vcvtps2qq zmm24{k5}{z}, [rbx+r11*8-256] + vcvtps2uqq xmm2, xmm0 + vcvtps2uqq xmm2, [rbx] + vcvtps2uqq xmm2, [rbx]{1to2} + vcvtps2uqq xmm2, [rbx+r11*8+256] + vcvtps2uqq xmm2, [rbx+r11*8-256] + vcvtps2uqq xmm2{k5}, xmm0 + vcvtps2uqq xmm2{k5}, [rbx] + vcvtps2uqq xmm2{k5}, [rbx]{1to2} + vcvtps2uqq xmm2{k5}, [rbx+r11*8+256] + vcvtps2uqq xmm2{k5}, [rbx+r11*8-256] + vcvtps2uqq xmm2{z}, xmm0 + vcvtps2uqq xmm2{z}, [rbx] + vcvtps2uqq xmm2{z}, [rbx]{1to2} + vcvtps2uqq xmm2{z}, [rbx+r11*8+256] + vcvtps2uqq xmm2{z}, [rbx+r11*8-256] + vcvtps2uqq xmm2{k5}{z}, xmm0 + vcvtps2uqq xmm2{k5}{z}, [rbx] + vcvtps2uqq xmm2{k5}{z}, [rbx]{1to2} + vcvtps2uqq xmm2{k5}{z}, [rbx+r11*8+256] + vcvtps2uqq xmm2{k5}{z}, [rbx+r11*8-256] + vcvtps2uqq ymm16, xmm0 + vcvtps2uqq ymm16, [rbx] + vcvtps2uqq ymm16, [rbx]{1to4} + vcvtps2uqq ymm16, [rbx+r11*8+256] + vcvtps2uqq ymm16, [rbx+r11*8-256] + vcvtps2uqq ymm16{k5}, xmm0 + vcvtps2uqq ymm16{k5}, [rbx] + vcvtps2uqq ymm16{k5}, [rbx]{1to4} + vcvtps2uqq ymm16{k5}, [rbx+r11*8+256] + vcvtps2uqq ymm16{k5}, [rbx+r11*8-256] + vcvtps2uqq ymm16{z}, xmm0 + vcvtps2uqq ymm16{z}, [rbx] + vcvtps2uqq ymm16{z}, [rbx]{1to4} + vcvtps2uqq ymm16{z}, [rbx+r11*8+256] + vcvtps2uqq ymm16{z}, [rbx+r11*8-256] + vcvtps2uqq ymm16{k5}{z}, xmm0 + vcvtps2uqq ymm16{k5}{z}, [rbx] + vcvtps2uqq ymm16{k5}{z}, [rbx]{1to4} + vcvtps2uqq ymm16{k5}{z}, [rbx+r11*8+256] + vcvtps2uqq ymm16{k5}{z}, [rbx+r11*8-256] + vcvtps2uqq zmm24, ymm15 + vcvtps2uqq zmm24, ymm15, {rd-sae} + vcvtps2uqq zmm24, [rbx] + vcvtps2uqq zmm24, [rbx]{1to8} + vcvtps2uqq zmm24, [rbx+r11*8+256] + vcvtps2uqq zmm24, [rbx+r11*8-256] + vcvtps2uqq zmm24{k5}, ymm15 + vcvtps2uqq zmm24{k5}, ymm15, {rd-sae} + vcvtps2uqq zmm24{k5}, [rbx] + vcvtps2uqq zmm24{k5}, [rbx]{1to8} + vcvtps2uqq zmm24{k5}, [rbx+r11*8+256] + vcvtps2uqq zmm24{k5}, [rbx+r11*8-256] + vcvtps2uqq zmm24{z}, ymm15 + vcvtps2uqq zmm24{z}, ymm15, {rd-sae} + vcvtps2uqq zmm24{z}, [rbx] + vcvtps2uqq zmm24{z}, [rbx]{1to8} + vcvtps2uqq zmm24{z}, [rbx+r11*8+256] + vcvtps2uqq zmm24{z}, [rbx+r11*8-256] + vcvtps2uqq zmm24{k5}{z}, ymm15 + vcvtps2uqq zmm24{k5}{z}, ymm15, {rd-sae} + vcvtps2uqq zmm24{k5}{z}, [rbx] + vcvtps2uqq zmm24{k5}{z}, [rbx]{1to8} + vcvtps2uqq zmm24{k5}{z}, [rbx+r11*8+256] + vcvtps2uqq zmm24{k5}{z}, [rbx+r11*8-256] + vcvtqq2pd xmm2, xmm0 + vcvtqq2pd xmm2, [rbx] + vcvtqq2pd xmm2, [rbx]{1to2} + vcvtqq2pd xmm2, [rbx+r11*8+256] + vcvtqq2pd xmm2, [rbx+r11*8-256] + vcvtqq2pd xmm2{k5}, xmm0 + vcvtqq2pd xmm2{k5}, [rbx] + vcvtqq2pd xmm2{k5}, [rbx]{1to2} + vcvtqq2pd xmm2{k5}, [rbx+r11*8+256] + vcvtqq2pd xmm2{k5}, [rbx+r11*8-256] + vcvtqq2pd xmm2{z}, xmm0 + vcvtqq2pd xmm2{z}, [rbx] + vcvtqq2pd xmm2{z}, [rbx]{1to2} + vcvtqq2pd xmm2{z}, [rbx+r11*8+256] + vcvtqq2pd xmm2{z}, [rbx+r11*8-256] + vcvtqq2pd xmm2{k5}{z}, xmm0 + vcvtqq2pd xmm2{k5}{z}, [rbx] + vcvtqq2pd xmm2{k5}{z}, [rbx]{1to2} + vcvtqq2pd xmm2{k5}{z}, [rbx+r11*8+256] + vcvtqq2pd xmm2{k5}{z}, [rbx+r11*8-256] + vcvtqq2pd ymm16, ymm15 + vcvtqq2pd ymm16, [rbx] + vcvtqq2pd ymm16, [rbx]{1to4} + vcvtqq2pd ymm16, [rbx+r11*8+256] + vcvtqq2pd ymm16, [rbx+r11*8-256] + vcvtqq2pd ymm16{k5}, ymm15 + vcvtqq2pd ymm16{k5}, [rbx] + vcvtqq2pd ymm16{k5}, [rbx]{1to4} + vcvtqq2pd ymm16{k5}, [rbx+r11*8+256] + vcvtqq2pd ymm16{k5}, [rbx+r11*8-256] + vcvtqq2pd ymm16{z}, ymm15 + vcvtqq2pd ymm16{z}, [rbx] + vcvtqq2pd ymm16{z}, [rbx]{1to4} + vcvtqq2pd ymm16{z}, [rbx+r11*8+256] + vcvtqq2pd ymm16{z}, [rbx+r11*8-256] + vcvtqq2pd ymm16{k5}{z}, ymm15 + vcvtqq2pd ymm16{k5}{z}, [rbx] + vcvtqq2pd ymm16{k5}{z}, [rbx]{1to4} + vcvtqq2pd ymm16{k5}{z}, [rbx+r11*8+256] + vcvtqq2pd ymm16{k5}{z}, [rbx+r11*8-256] + vcvtqq2pd zmm24, zmm31 + vcvtqq2pd zmm24, zmm31, {rd-sae} + vcvtqq2pd zmm24, [rbx] + vcvtqq2pd zmm24, [rbx]{1to8} + vcvtqq2pd zmm24, [rbx+r11*8+256] + vcvtqq2pd zmm24, [rbx+r11*8-256] + vcvtqq2pd zmm24{k5}, zmm31 + vcvtqq2pd zmm24{k5}, zmm31, {rd-sae} + vcvtqq2pd zmm24{k5}, [rbx] + vcvtqq2pd zmm24{k5}, [rbx]{1to8} + vcvtqq2pd zmm24{k5}, [rbx+r11*8+256] + vcvtqq2pd zmm24{k5}, [rbx+r11*8-256] + vcvtqq2pd zmm24{z}, zmm31 + vcvtqq2pd zmm24{z}, zmm31, {rd-sae} + vcvtqq2pd zmm24{z}, [rbx] + vcvtqq2pd zmm24{z}, [rbx]{1to8} + vcvtqq2pd zmm24{z}, [rbx+r11*8+256] + vcvtqq2pd zmm24{z}, [rbx+r11*8-256] + vcvtqq2pd zmm24{k5}{z}, zmm31 + vcvtqq2pd zmm24{k5}{z}, zmm31, {rd-sae} + vcvtqq2pd zmm24{k5}{z}, [rbx] + vcvtqq2pd zmm24{k5}{z}, [rbx]{1to8} + vcvtqq2pd zmm24{k5}{z}, [rbx+r11*8+256] + vcvtqq2pd zmm24{k5}{z}, [rbx+r11*8-256] + vcvtqq2ps xmm2, xmm0 + vcvtqq2ps xmm2, ymm15 + vcvtqq2ps xmm2, [rbx]{1to2} + vcvtqq2ps xmm2, [rbx]{1to4} + vcvtqq2ps xmm2{k5}, xmm0 + vcvtqq2ps xmm2{k5}, ymm15 + vcvtqq2ps xmm2{k5}, [rbx]{1to2} + vcvtqq2ps xmm2{k5}, [rbx]{1to4} + vcvtqq2ps xmm2{z}, xmm0 + vcvtqq2ps xmm2{z}, ymm15 + vcvtqq2ps xmm2{z}, [rbx]{1to2} + vcvtqq2ps xmm2{z}, [rbx]{1to4} + vcvtqq2ps xmm2{k5}{z}, xmm0 + vcvtqq2ps xmm2{k5}{z}, ymm15 + vcvtqq2ps xmm2{k5}{z}, [rbx]{1to2} + vcvtqq2ps xmm2{k5}{z}, [rbx]{1to4} + vcvtqq2ps ymm16, zmm31 + vcvtqq2ps ymm16, zmm31, {rd-sae} + vcvtqq2ps ymm16, [rbx] + vcvtqq2ps ymm16, [rbx]{1to8} + vcvtqq2ps ymm16, [rbx+r11*8+256] + vcvtqq2ps ymm16, [rbx+r11*8-256] + vcvtqq2ps ymm16{k5}, zmm31 + vcvtqq2ps ymm16{k5}, zmm31, {rd-sae} + vcvtqq2ps ymm16{k5}, [rbx] + vcvtqq2ps ymm16{k5}, [rbx]{1to8} + vcvtqq2ps ymm16{k5}, [rbx+r11*8+256] + vcvtqq2ps ymm16{k5}, [rbx+r11*8-256] + vcvtqq2ps ymm16{z}, zmm31 + vcvtqq2ps ymm16{z}, zmm31, {rd-sae} + vcvtqq2ps ymm16{z}, [rbx] + vcvtqq2ps ymm16{z}, [rbx]{1to8} + vcvtqq2ps ymm16{z}, [rbx+r11*8+256] + vcvtqq2ps ymm16{z}, [rbx+r11*8-256] + vcvtqq2ps ymm16{k5}{z}, zmm31 + vcvtqq2ps ymm16{k5}{z}, zmm31, {rd-sae} + vcvtqq2ps ymm16{k5}{z}, [rbx] + vcvtqq2ps ymm16{k5}{z}, [rbx]{1to8} + vcvtqq2ps ymm16{k5}{z}, [rbx+r11*8+256] + vcvtqq2ps ymm16{k5}{z}, [rbx+r11*8-256] + vcvttpd2qq xmm2, xmm0 + vcvttpd2qq xmm2, [rbx] + vcvttpd2qq xmm2, [rbx]{1to2} + vcvttpd2qq xmm2, [rbx+r11*8+256] + vcvttpd2qq xmm2, [rbx+r11*8-256] + vcvttpd2qq xmm2{k5}, xmm0 + vcvttpd2qq xmm2{k5}, [rbx] + vcvttpd2qq xmm2{k5}, [rbx]{1to2} + vcvttpd2qq xmm2{k5}, [rbx+r11*8+256] + vcvttpd2qq xmm2{k5}, [rbx+r11*8-256] + vcvttpd2qq xmm2{z}, xmm0 + vcvttpd2qq xmm2{z}, [rbx] + vcvttpd2qq xmm2{z}, [rbx]{1to2} + vcvttpd2qq xmm2{z}, [rbx+r11*8+256] + vcvttpd2qq xmm2{z}, [rbx+r11*8-256] + vcvttpd2qq xmm2{k5}{z}, xmm0 + vcvttpd2qq xmm2{k5}{z}, [rbx] + vcvttpd2qq xmm2{k5}{z}, [rbx]{1to2} + vcvttpd2qq xmm2{k5}{z}, [rbx+r11*8+256] + vcvttpd2qq xmm2{k5}{z}, [rbx+r11*8-256] + vcvttpd2qq ymm16, ymm15 + vcvttpd2qq ymm16, [rbx] + vcvttpd2qq ymm16, [rbx]{1to4} + vcvttpd2qq ymm16, [rbx+r11*8+256] + vcvttpd2qq ymm16, [rbx+r11*8-256] + vcvttpd2qq ymm16{k5}, ymm15 + vcvttpd2qq ymm16{k5}, [rbx] + vcvttpd2qq ymm16{k5}, [rbx]{1to4} + vcvttpd2qq ymm16{k5}, [rbx+r11*8+256] + vcvttpd2qq ymm16{k5}, [rbx+r11*8-256] + vcvttpd2qq ymm16{z}, ymm15 + vcvttpd2qq ymm16{z}, [rbx] + vcvttpd2qq ymm16{z}, [rbx]{1to4} + vcvttpd2qq ymm16{z}, [rbx+r11*8+256] + vcvttpd2qq ymm16{z}, [rbx+r11*8-256] + vcvttpd2qq ymm16{k5}{z}, ymm15 + vcvttpd2qq ymm16{k5}{z}, [rbx] + vcvttpd2qq ymm16{k5}{z}, [rbx]{1to4} + vcvttpd2qq ymm16{k5}{z}, [rbx+r11*8+256] + vcvttpd2qq ymm16{k5}{z}, [rbx+r11*8-256] + vcvttpd2qq zmm24, zmm31 + vcvttpd2qq zmm24, zmm31, {sae} + vcvttpd2qq zmm24, [rbx] + vcvttpd2qq zmm24, [rbx]{1to8} + vcvttpd2qq zmm24, [rbx+r11*8+256] + vcvttpd2qq zmm24, [rbx+r11*8-256] + vcvttpd2qq zmm24{k5}, zmm31 + vcvttpd2qq zmm24{k5}, zmm31, {sae} + vcvttpd2qq zmm24{k5}, [rbx] + vcvttpd2qq zmm24{k5}, [rbx]{1to8} + vcvttpd2qq zmm24{k5}, [rbx+r11*8+256] + vcvttpd2qq zmm24{k5}, [rbx+r11*8-256] + vcvttpd2qq zmm24{z}, zmm31 + vcvttpd2qq zmm24{z}, zmm31, {sae} + vcvttpd2qq zmm24{z}, [rbx] + vcvttpd2qq zmm24{z}, [rbx]{1to8} + vcvttpd2qq zmm24{z}, [rbx+r11*8+256] + vcvttpd2qq zmm24{z}, [rbx+r11*8-256] + vcvttpd2qq zmm24{k5}{z}, zmm31 + vcvttpd2qq zmm24{k5}{z}, zmm31, {sae} + vcvttpd2qq zmm24{k5}{z}, [rbx] + vcvttpd2qq zmm24{k5}{z}, [rbx]{1to8} + vcvttpd2qq zmm24{k5}{z}, [rbx+r11*8+256] + vcvttpd2qq zmm24{k5}{z}, [rbx+r11*8-256] + vcvttpd2uqq xmm2, xmm0 + vcvttpd2uqq xmm2, [rbx] + vcvttpd2uqq xmm2, [rbx]{1to2} + vcvttpd2uqq xmm2, [rbx+r11*8+256] + vcvttpd2uqq xmm2, [rbx+r11*8-256] + vcvttpd2uqq xmm2{k5}, xmm0 + vcvttpd2uqq xmm2{k5}, [rbx] + vcvttpd2uqq xmm2{k5}, [rbx]{1to2} + vcvttpd2uqq xmm2{k5}, [rbx+r11*8+256] + vcvttpd2uqq xmm2{k5}, [rbx+r11*8-256] + vcvttpd2uqq xmm2{z}, xmm0 + vcvttpd2uqq xmm2{z}, [rbx] + vcvttpd2uqq xmm2{z}, [rbx]{1to2} + vcvttpd2uqq xmm2{z}, [rbx+r11*8+256] + vcvttpd2uqq xmm2{z}, [rbx+r11*8-256] + vcvttpd2uqq xmm2{k5}{z}, xmm0 + vcvttpd2uqq xmm2{k5}{z}, [rbx] + vcvttpd2uqq xmm2{k5}{z}, [rbx]{1to2} + vcvttpd2uqq xmm2{k5}{z}, [rbx+r11*8+256] + vcvttpd2uqq xmm2{k5}{z}, [rbx+r11*8-256] + vcvttpd2uqq ymm16, ymm15 + vcvttpd2uqq ymm16, [rbx] + vcvttpd2uqq ymm16, [rbx]{1to4} + vcvttpd2uqq ymm16, [rbx+r11*8+256] + vcvttpd2uqq ymm16, [rbx+r11*8-256] + vcvttpd2uqq ymm16{k5}, ymm15 + vcvttpd2uqq ymm16{k5}, [rbx] + vcvttpd2uqq ymm16{k5}, [rbx]{1to4} + vcvttpd2uqq ymm16{k5}, [rbx+r11*8+256] + vcvttpd2uqq ymm16{k5}, [rbx+r11*8-256] + vcvttpd2uqq ymm16{z}, ymm15 + vcvttpd2uqq ymm16{z}, [rbx] + vcvttpd2uqq ymm16{z}, [rbx]{1to4} + vcvttpd2uqq ymm16{z}, [rbx+r11*8+256] + vcvttpd2uqq ymm16{z}, [rbx+r11*8-256] + vcvttpd2uqq ymm16{k5}{z}, ymm15 + vcvttpd2uqq ymm16{k5}{z}, [rbx] + vcvttpd2uqq ymm16{k5}{z}, [rbx]{1to4} + vcvttpd2uqq ymm16{k5}{z}, [rbx+r11*8+256] + vcvttpd2uqq ymm16{k5}{z}, [rbx+r11*8-256] + vcvttpd2uqq zmm24, zmm31 + vcvttpd2uqq zmm24, zmm31, {sae} + vcvttpd2uqq zmm24, [rbx] + vcvttpd2uqq zmm24, [rbx]{1to8} + vcvttpd2uqq zmm24, [rbx+r11*8+256] + vcvttpd2uqq zmm24, [rbx+r11*8-256] + vcvttpd2uqq zmm24{k5}, zmm31 + vcvttpd2uqq zmm24{k5}, zmm31, {sae} + vcvttpd2uqq zmm24{k5}, [rbx] + vcvttpd2uqq zmm24{k5}, [rbx]{1to8} + vcvttpd2uqq zmm24{k5}, [rbx+r11*8+256] + vcvttpd2uqq zmm24{k5}, [rbx+r11*8-256] + vcvttpd2uqq zmm24{z}, zmm31 + vcvttpd2uqq zmm24{z}, zmm31, {sae} + vcvttpd2uqq zmm24{z}, [rbx] + vcvttpd2uqq zmm24{z}, [rbx]{1to8} + vcvttpd2uqq zmm24{z}, [rbx+r11*8+256] + vcvttpd2uqq zmm24{z}, [rbx+r11*8-256] + vcvttpd2uqq zmm24{k5}{z}, zmm31 + vcvttpd2uqq zmm24{k5}{z}, zmm31, {sae} + vcvttpd2uqq zmm24{k5}{z}, [rbx] + vcvttpd2uqq zmm24{k5}{z}, [rbx]{1to8} + vcvttpd2uqq zmm24{k5}{z}, [rbx+r11*8+256] + vcvttpd2uqq zmm24{k5}{z}, [rbx+r11*8-256] + vcvttps2qq xmm2, xmm0 + vcvttps2qq xmm2, [rbx] + vcvttps2qq xmm2, [rbx]{1to2} + vcvttps2qq xmm2, [rbx+r11*8+256] + vcvttps2qq xmm2, [rbx+r11*8-256] + vcvttps2qq xmm2{k5}, xmm0 + vcvttps2qq xmm2{k5}, [rbx] + vcvttps2qq xmm2{k5}, [rbx]{1to2} + vcvttps2qq xmm2{k5}, [rbx+r11*8+256] + vcvttps2qq xmm2{k5}, [rbx+r11*8-256] + vcvttps2qq xmm2{z}, xmm0 + vcvttps2qq xmm2{z}, [rbx] + vcvttps2qq xmm2{z}, [rbx]{1to2} + vcvttps2qq xmm2{z}, [rbx+r11*8+256] + vcvttps2qq xmm2{z}, [rbx+r11*8-256] + vcvttps2qq xmm2{k5}{z}, xmm0 + vcvttps2qq xmm2{k5}{z}, [rbx] + vcvttps2qq xmm2{k5}{z}, [rbx]{1to2} + vcvttps2qq xmm2{k5}{z}, [rbx+r11*8+256] + vcvttps2qq xmm2{k5}{z}, [rbx+r11*8-256] + vcvttps2qq ymm16, xmm0 + vcvttps2qq ymm16, [rbx] + vcvttps2qq ymm16, [rbx]{1to4} + vcvttps2qq ymm16, [rbx+r11*8+256] + vcvttps2qq ymm16, [rbx+r11*8-256] + vcvttps2qq ymm16{k5}, xmm0 + vcvttps2qq ymm16{k5}, [rbx] + vcvttps2qq ymm16{k5}, [rbx]{1to4} + vcvttps2qq ymm16{k5}, [rbx+r11*8+256] + vcvttps2qq ymm16{k5}, [rbx+r11*8-256] + vcvttps2qq ymm16{z}, xmm0 + vcvttps2qq ymm16{z}, [rbx] + vcvttps2qq ymm16{z}, [rbx]{1to4} + vcvttps2qq ymm16{z}, [rbx+r11*8+256] + vcvttps2qq ymm16{z}, [rbx+r11*8-256] + vcvttps2qq ymm16{k5}{z}, xmm0 + vcvttps2qq ymm16{k5}{z}, [rbx] + vcvttps2qq ymm16{k5}{z}, [rbx]{1to4} + vcvttps2qq ymm16{k5}{z}, [rbx+r11*8+256] + vcvttps2qq ymm16{k5}{z}, [rbx+r11*8-256] + vcvttps2qq zmm24, ymm15 + vcvttps2qq zmm24, ymm15, {sae} + vcvttps2qq zmm24, [rbx] + vcvttps2qq zmm24, [rbx]{1to8} + vcvttps2qq zmm24, [rbx+r11*8+256] + vcvttps2qq zmm24, [rbx+r11*8-256] + vcvttps2qq zmm24{k5}, ymm15 + vcvttps2qq zmm24{k5}, ymm15, {sae} + vcvttps2qq zmm24{k5}, [rbx] + vcvttps2qq zmm24{k5}, [rbx]{1to8} + vcvttps2qq zmm24{k5}, [rbx+r11*8+256] + vcvttps2qq zmm24{k5}, [rbx+r11*8-256] + vcvttps2qq zmm24{z}, ymm15 + vcvttps2qq zmm24{z}, ymm15, {sae} + vcvttps2qq zmm24{z}, [rbx] + vcvttps2qq zmm24{z}, [rbx]{1to8} + vcvttps2qq zmm24{z}, [rbx+r11*8+256] + vcvttps2qq zmm24{z}, [rbx+r11*8-256] + vcvttps2qq zmm24{k5}{z}, ymm15 + vcvttps2qq zmm24{k5}{z}, ymm15, {sae} + vcvttps2qq zmm24{k5}{z}, [rbx] + vcvttps2qq zmm24{k5}{z}, [rbx]{1to8} + vcvttps2qq zmm24{k5}{z}, [rbx+r11*8+256] + vcvttps2qq zmm24{k5}{z}, [rbx+r11*8-256] + vcvttps2uqq xmm2, xmm0 + vcvttps2uqq xmm2, [rbx] + vcvttps2uqq xmm2, [rbx]{1to2} + vcvttps2uqq xmm2, [rbx+r11*8+256] + vcvttps2uqq xmm2, [rbx+r11*8-256] + vcvttps2uqq xmm2{k5}, xmm0 + vcvttps2uqq xmm2{k5}, [rbx] + vcvttps2uqq xmm2{k5}, [rbx]{1to2} + vcvttps2uqq xmm2{k5}, [rbx+r11*8+256] + vcvttps2uqq xmm2{k5}, [rbx+r11*8-256] + vcvttps2uqq xmm2{z}, xmm0 + vcvttps2uqq xmm2{z}, [rbx] + vcvttps2uqq xmm2{z}, [rbx]{1to2} + vcvttps2uqq xmm2{z}, [rbx+r11*8+256] + vcvttps2uqq xmm2{z}, [rbx+r11*8-256] + vcvttps2uqq xmm2{k5}{z}, xmm0 + vcvttps2uqq xmm2{k5}{z}, [rbx] + vcvttps2uqq xmm2{k5}{z}, [rbx]{1to2} + vcvttps2uqq xmm2{k5}{z}, [rbx+r11*8+256] + vcvttps2uqq xmm2{k5}{z}, [rbx+r11*8-256] + vcvttps2uqq ymm16, xmm0 + vcvttps2uqq ymm16, [rbx] + vcvttps2uqq ymm16, [rbx]{1to4} + vcvttps2uqq ymm16, [rbx+r11*8+256] + vcvttps2uqq ymm16, [rbx+r11*8-256] + vcvttps2uqq ymm16{k5}, xmm0 + vcvttps2uqq ymm16{k5}, [rbx] + vcvttps2uqq ymm16{k5}, [rbx]{1to4} + vcvttps2uqq ymm16{k5}, [rbx+r11*8+256] + vcvttps2uqq ymm16{k5}, [rbx+r11*8-256] + vcvttps2uqq ymm16{z}, xmm0 + vcvttps2uqq ymm16{z}, [rbx] + vcvttps2uqq ymm16{z}, [rbx]{1to4} + vcvttps2uqq ymm16{z}, [rbx+r11*8+256] + vcvttps2uqq ymm16{z}, [rbx+r11*8-256] + vcvttps2uqq ymm16{k5}{z}, xmm0 + vcvttps2uqq ymm16{k5}{z}, [rbx] + vcvttps2uqq ymm16{k5}{z}, [rbx]{1to4} + vcvttps2uqq ymm16{k5}{z}, [rbx+r11*8+256] + vcvttps2uqq ymm16{k5}{z}, [rbx+r11*8-256] + vcvttps2uqq zmm24, ymm15 + vcvttps2uqq zmm24, ymm15, {sae} + vcvttps2uqq zmm24, [rbx] + vcvttps2uqq zmm24, [rbx]{1to8} + vcvttps2uqq zmm24, [rbx+r11*8+256] + vcvttps2uqq zmm24, [rbx+r11*8-256] + vcvttps2uqq zmm24{k5}, ymm15 + vcvttps2uqq zmm24{k5}, ymm15, {sae} + vcvttps2uqq zmm24{k5}, [rbx] + vcvttps2uqq zmm24{k5}, [rbx]{1to8} + vcvttps2uqq zmm24{k5}, [rbx+r11*8+256] + vcvttps2uqq zmm24{k5}, [rbx+r11*8-256] + vcvttps2uqq zmm24{z}, ymm15 + vcvttps2uqq zmm24{z}, ymm15, {sae} + vcvttps2uqq zmm24{z}, [rbx] + vcvttps2uqq zmm24{z}, [rbx]{1to8} + vcvttps2uqq zmm24{z}, [rbx+r11*8+256] + vcvttps2uqq zmm24{z}, [rbx+r11*8-256] + vcvttps2uqq zmm24{k5}{z}, ymm15 + vcvttps2uqq zmm24{k5}{z}, ymm15, {sae} + vcvttps2uqq zmm24{k5}{z}, [rbx] + vcvttps2uqq zmm24{k5}{z}, [rbx]{1to8} + vcvttps2uqq zmm24{k5}{z}, [rbx+r11*8+256] + vcvttps2uqq zmm24{k5}{z}, [rbx+r11*8-256] + vcvtuqq2pd xmm2, xmm0 + vcvtuqq2pd xmm2, [rbx] + vcvtuqq2pd xmm2, [rbx]{1to2} + vcvtuqq2pd xmm2, [rbx+r11*8+256] + vcvtuqq2pd xmm2, [rbx+r11*8-256] + vcvtuqq2pd xmm2{k5}, xmm0 + vcvtuqq2pd xmm2{k5}, [rbx] + vcvtuqq2pd xmm2{k5}, [rbx]{1to2} + vcvtuqq2pd xmm2{k5}, [rbx+r11*8+256] + vcvtuqq2pd xmm2{k5}, [rbx+r11*8-256] + vcvtuqq2pd xmm2{z}, xmm0 + vcvtuqq2pd xmm2{z}, [rbx] + vcvtuqq2pd xmm2{z}, [rbx]{1to2} + vcvtuqq2pd xmm2{z}, [rbx+r11*8+256] + vcvtuqq2pd xmm2{z}, [rbx+r11*8-256] + vcvtuqq2pd xmm2{k5}{z}, xmm0 + vcvtuqq2pd xmm2{k5}{z}, [rbx] + vcvtuqq2pd xmm2{k5}{z}, [rbx]{1to2} + vcvtuqq2pd xmm2{k5}{z}, [rbx+r11*8+256] + vcvtuqq2pd xmm2{k5}{z}, [rbx+r11*8-256] + vcvtuqq2pd ymm16, ymm15 + vcvtuqq2pd ymm16, [rbx] + vcvtuqq2pd ymm16, [rbx]{1to4} + vcvtuqq2pd ymm16, [rbx+r11*8+256] + vcvtuqq2pd ymm16, [rbx+r11*8-256] + vcvtuqq2pd ymm16{k5}, ymm15 + vcvtuqq2pd ymm16{k5}, [rbx] + vcvtuqq2pd ymm16{k5}, [rbx]{1to4} + vcvtuqq2pd ymm16{k5}, [rbx+r11*8+256] + vcvtuqq2pd ymm16{k5}, [rbx+r11*8-256] + vcvtuqq2pd ymm16{z}, ymm15 + vcvtuqq2pd ymm16{z}, [rbx] + vcvtuqq2pd ymm16{z}, [rbx]{1to4} + vcvtuqq2pd ymm16{z}, [rbx+r11*8+256] + vcvtuqq2pd ymm16{z}, [rbx+r11*8-256] + vcvtuqq2pd ymm16{k5}{z}, ymm15 + vcvtuqq2pd ymm16{k5}{z}, [rbx] + vcvtuqq2pd ymm16{k5}{z}, [rbx]{1to4} + vcvtuqq2pd ymm16{k5}{z}, [rbx+r11*8+256] + vcvtuqq2pd ymm16{k5}{z}, [rbx+r11*8-256] + vcvtuqq2pd zmm24, zmm31 + vcvtuqq2pd zmm24, zmm31, {rd-sae} + vcvtuqq2pd zmm24, [rbx] + vcvtuqq2pd zmm24, [rbx]{1to8} + vcvtuqq2pd zmm24, [rbx+r11*8+256] + vcvtuqq2pd zmm24, [rbx+r11*8-256] + vcvtuqq2pd zmm24{k5}, zmm31 + vcvtuqq2pd zmm24{k5}, zmm31, {rd-sae} + vcvtuqq2pd zmm24{k5}, [rbx] + vcvtuqq2pd zmm24{k5}, [rbx]{1to8} + vcvtuqq2pd zmm24{k5}, [rbx+r11*8+256] + vcvtuqq2pd zmm24{k5}, [rbx+r11*8-256] + vcvtuqq2pd zmm24{z}, zmm31 + vcvtuqq2pd zmm24{z}, zmm31, {rd-sae} + vcvtuqq2pd zmm24{z}, [rbx] + vcvtuqq2pd zmm24{z}, [rbx]{1to8} + vcvtuqq2pd zmm24{z}, [rbx+r11*8+256] + vcvtuqq2pd zmm24{z}, [rbx+r11*8-256] + vcvtuqq2pd zmm24{k5}{z}, zmm31 + vcvtuqq2pd zmm24{k5}{z}, zmm31, {rd-sae} + vcvtuqq2pd zmm24{k5}{z}, [rbx] + vcvtuqq2pd zmm24{k5}{z}, [rbx]{1to8} + vcvtuqq2pd zmm24{k5}{z}, [rbx+r11*8+256] + vcvtuqq2pd zmm24{k5}{z}, [rbx+r11*8-256] + vcvtuqq2ps xmm2, xmm0 + vcvtuqq2ps xmm2, ymm15 + vcvtuqq2ps xmm2, [rbx]{1to2} + vcvtuqq2ps xmm2, [rbx]{1to4} + vcvtuqq2ps xmm2{k5}, xmm0 + vcvtuqq2ps xmm2{k5}, ymm15 + vcvtuqq2ps xmm2{k5}, [rbx]{1to2} + vcvtuqq2ps xmm2{k5}, [rbx]{1to4} + vcvtuqq2ps xmm2{z}, xmm0 + vcvtuqq2ps xmm2{z}, ymm15 + vcvtuqq2ps xmm2{z}, [rbx]{1to2} + vcvtuqq2ps xmm2{z}, [rbx]{1to4} + vcvtuqq2ps xmm2{k5}{z}, xmm0 + vcvtuqq2ps xmm2{k5}{z}, ymm15 + vcvtuqq2ps xmm2{k5}{z}, [rbx]{1to2} + vcvtuqq2ps xmm2{k5}{z}, [rbx]{1to4} + vcvtuqq2ps ymm16, zmm31 + vcvtuqq2ps ymm16, zmm31, {rd-sae} + vcvtuqq2ps ymm16, [rbx] + vcvtuqq2ps ymm16, [rbx]{1to8} + vcvtuqq2ps ymm16, [rbx+r11*8+256] + vcvtuqq2ps ymm16, [rbx+r11*8-256] + vcvtuqq2ps ymm16{k5}, zmm31 + vcvtuqq2ps ymm16{k5}, zmm31, {rd-sae} + vcvtuqq2ps ymm16{k5}, [rbx] + vcvtuqq2ps ymm16{k5}, [rbx]{1to8} + vcvtuqq2ps ymm16{k5}, [rbx+r11*8+256] + vcvtuqq2ps ymm16{k5}, [rbx+r11*8-256] + vcvtuqq2ps ymm16{z}, zmm31 + vcvtuqq2ps ymm16{z}, zmm31, {rd-sae} + vcvtuqq2ps ymm16{z}, [rbx] + vcvtuqq2ps ymm16{z}, [rbx]{1to8} + vcvtuqq2ps ymm16{z}, [rbx+r11*8+256] + vcvtuqq2ps ymm16{z}, [rbx+r11*8-256] + vcvtuqq2ps ymm16{k5}{z}, zmm31 + vcvtuqq2ps ymm16{k5}{z}, zmm31, {rd-sae} + vcvtuqq2ps ymm16{k5}{z}, [rbx] + vcvtuqq2ps ymm16{k5}{z}, [rbx]{1to8} + vcvtuqq2ps ymm16{k5}{z}, [rbx+r11*8+256] + vcvtuqq2ps ymm16{k5}{z}, [rbx+r11*8-256] + vextractf32x8 ymm15, zmm24, 10 + vextractf32x8 [rbx], zmm24, 10 + vextractf32x8 [rbx+r11*8+256], zmm24, 10 + vextractf32x8 [rbx+r11*8-256], zmm24, 10 + vextractf64x2 xmm0, ymm16, 10 + vextractf64x2 xmm0, zmm24, 10 + vextractf64x2 [rbx], ymm16, 10 + vextractf64x2 [rbx], zmm24, 10 + vextractf64x2 [rbx+r11*8+256], ymm16, 10 + vextractf64x2 [rbx+r11*8+256], zmm24, 10 + vextractf64x2 [rbx+r11*8-256], ymm16, 10 + vextractf64x2 [rbx+r11*8-256], zmm24, 10 + vextracti32x8 ymm15, zmm24, 10 + vextracti32x8 [rbx], zmm24, 10 + vextracti32x8 [rbx+r11*8+256], zmm24, 10 + vextracti32x8 [rbx+r11*8-256], zmm24, 10 + vextracti64x2 xmm0, ymm16, 10 + vextracti64x2 xmm0, zmm24, 10 + vextracti64x2 [rbx], ymm16, 10 + vextracti64x2 [rbx], zmm24, 10 + vextracti64x2 [rbx+r11*8+256], ymm16, 10 + vextracti64x2 [rbx+r11*8+256], zmm24, 10 + vextracti64x2 [rbx+r11*8-256], ymm16, 10 + vextracti64x2 [rbx+r11*8-256], zmm24, 10 + vfpclasspd k3, xmm0, 10 + vfpclasspd k3, ymm15, 10 + vfpclasspd k3, zmm31, 10 + vfpclasspd k3, [rbx]{1to2}, 10 + vfpclasspd k3, [rbx]{1to4}, 10 + vfpclasspd k3, [rbx]{1to8}, 10 + vfpclasspd k3{k5}, xmm0, 10 + vfpclasspd k3{k5}, ymm15, 10 + vfpclasspd k3{k5}, zmm31, 10 + vfpclasspd k3{k5}, [rbx]{1to2}, 10 + vfpclasspd k3{k5}, [rbx]{1to4}, 10 + vfpclasspd k3{k5}, [rbx]{1to8}, 10 + vfpclassps k3, xmm0, 10 + vfpclassps k3, ymm15, 10 + vfpclassps k3, zmm31, 10 + vfpclassps k3, [rbx]{1to4}, 10 + vfpclassps k3, [rbx]{1to8}, 10 + vfpclassps k3, [rbx]{1to16}, 10 + vfpclassps k3{k5}, xmm0, 10 + vfpclassps k3{k5}, ymm15, 10 + vfpclassps k3{k5}, zmm31, 10 + vfpclassps k3{k5}, [rbx]{1to4}, 10 + vfpclassps k3{k5}, [rbx]{1to8}, 10 + vfpclassps k3{k5}, [rbx]{1to16}, 10 + vfpclasssd k3, xmm0, 10 + vfpclasssd k3, [rbx], 10 + vfpclasssd k3, [rbx+r11*8+256], 10 + vfpclasssd k3, [rbx+r11*8-256], 10 + vfpclasssd k3{k5}, xmm0, 10 + vfpclasssd k3{k5}, [rbx], 10 + vfpclasssd k3{k5}, [rbx+r11*8+256], 10 + vfpclasssd k3{k5}, [rbx+r11*8-256], 10 + vfpclassss k3, xmm0, 10 + vfpclassss k3, [rbx], 10 + vfpclassss k3, [rbx+r11*8+256], 10 + vfpclassss k3, [rbx+r11*8-256], 10 + vfpclassss k3{k5}, xmm0, 10 + vfpclassss k3{k5}, [rbx], 10 + vfpclassss k3{k5}, [rbx+r11*8+256], 10 + vfpclassss k3{k5}, [rbx+r11*8-256], 10 + vinsertf32x8 zmm24, zmm24, ymm15, 10 + vinsertf32x8 zmm24, zmm24, [rbx], 10 + vinsertf32x8 zmm24, zmm24, [rbx+r11*8+256], 10 + vinsertf32x8 zmm24, zmm24, [rbx+r11*8-256], 10 + vinsertf32x8 zmm24{k5}, zmm24, ymm15, 10 + vinsertf32x8 zmm24{k5}, zmm24, [rbx], 10 + vinsertf32x8 zmm24{k5}, zmm24, [rbx+r11*8+256], 10 + vinsertf32x8 zmm24{k5}, zmm24, [rbx+r11*8-256], 10 + vinsertf32x8 zmm24{z}, zmm24, ymm15, 10 + vinsertf32x8 zmm24{z}, zmm24, [rbx], 10 + vinsertf32x8 zmm24{z}, zmm24, [rbx+r11*8+256], 10 + vinsertf32x8 zmm24{z}, zmm24, [rbx+r11*8-256], 10 + vinsertf32x8 zmm24{k5}{z}, zmm24, ymm15, 10 + vinsertf32x8 zmm24{k5}{z}, zmm24, [rbx], 10 + vinsertf32x8 zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 10 + vinsertf32x8 zmm24{k5}{z}, zmm24, [rbx+r11*8-256], 10 + vinsertf64x2 ymm16, ymm13, xmm0, 10 + vinsertf64x2 ymm16, ymm13, [rbx], 10 + vinsertf64x2 ymm16, ymm13, [rbx+r11*8+256], 10 + vinsertf64x2 ymm16, ymm13, [rbx+r11*8-256], 10 + vinsertf64x2 ymm16{k5}, ymm13, xmm0, 10 + vinsertf64x2 ymm16{k5}, ymm13, [rbx], 10 + vinsertf64x2 ymm16{k5}, ymm13, [rbx+r11*8+256], 10 + vinsertf64x2 ymm16{k5}, ymm13, [rbx+r11*8-256], 10 + vinsertf64x2 ymm16{z}, ymm13, xmm0, 10 + vinsertf64x2 ymm16{z}, ymm13, [rbx], 10 + vinsertf64x2 ymm16{z}, ymm13, [rbx+r11*8+256], 10 + vinsertf64x2 ymm16{z}, ymm13, [rbx+r11*8-256], 10 + vinsertf64x2 ymm16{k5}{z}, ymm13, xmm0, 10 + vinsertf64x2 ymm16{k5}{z}, ymm13, [rbx], 10 + vinsertf64x2 ymm16{k5}{z}, ymm13, [rbx+r11*8+256], 10 + vinsertf64x2 ymm16{k5}{z}, ymm13, [rbx+r11*8-256], 10 + vinsertf64x2 zmm24, zmm24, xmm0, 10 + vinsertf64x2 zmm24, zmm24, [rbx], 10 + vinsertf64x2 zmm24, zmm24, [rbx+r11*8+256], 10 + vinsertf64x2 zmm24, zmm24, [rbx+r11*8-256], 10 + vinsertf64x2 zmm24{k5}, zmm24, xmm0, 10 + vinsertf64x2 zmm24{k5}, zmm24, [rbx], 10 + vinsertf64x2 zmm24{k5}, zmm24, [rbx+r11*8+256], 10 + vinsertf64x2 zmm24{k5}, zmm24, [rbx+r11*8-256], 10 + vinsertf64x2 zmm24{z}, zmm24, xmm0, 10 + vinsertf64x2 zmm24{z}, zmm24, [rbx], 10 + vinsertf64x2 zmm24{z}, zmm24, [rbx+r11*8+256], 10 + vinsertf64x2 zmm24{z}, zmm24, [rbx+r11*8-256], 10 + vinsertf64x2 zmm24{k5}{z}, zmm24, xmm0, 10 + vinsertf64x2 zmm24{k5}{z}, zmm24, [rbx], 10 + vinsertf64x2 zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 10 + vinsertf64x2 zmm24{k5}{z}, zmm24, [rbx+r11*8-256], 10 + vinserti32x8 zmm24, zmm24, ymm15, 10 + vinserti32x8 zmm24, zmm24, [rbx], 10 + vinserti32x8 zmm24, zmm24, [rbx+r11*8+256], 10 + vinserti32x8 zmm24, zmm24, [rbx+r11*8-256], 10 + vinserti32x8 zmm24{k5}, zmm24, ymm15, 10 + vinserti32x8 zmm24{k5}, zmm24, [rbx], 10 + vinserti32x8 zmm24{k5}, zmm24, [rbx+r11*8+256], 10 + vinserti32x8 zmm24{k5}, zmm24, [rbx+r11*8-256], 10 + vinserti32x8 zmm24{z}, zmm24, ymm15, 10 + vinserti32x8 zmm24{z}, zmm24, [rbx], 10 + vinserti32x8 zmm24{z}, zmm24, [rbx+r11*8+256], 10 + vinserti32x8 zmm24{z}, zmm24, [rbx+r11*8-256], 10 + vinserti32x8 zmm24{k5}{z}, zmm24, ymm15, 10 + vinserti32x8 zmm24{k5}{z}, zmm24, [rbx], 10 + vinserti32x8 zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 10 + vinserti32x8 zmm24{k5}{z}, zmm24, [rbx+r11*8-256], 10 + vinserti64x2 ymm16, ymm13, xmm0, 10 + vinserti64x2 ymm16, ymm13, [rbx], 10 + vinserti64x2 ymm16, ymm13, [rbx+r11*8+256], 10 + vinserti64x2 ymm16, ymm13, [rbx+r11*8-256], 10 + vinserti64x2 ymm16{k5}, ymm13, xmm0, 10 + vinserti64x2 ymm16{k5}, ymm13, [rbx], 10 + vinserti64x2 ymm16{k5}, ymm13, [rbx+r11*8+256], 10 + vinserti64x2 ymm16{k5}, ymm13, [rbx+r11*8-256], 10 + vinserti64x2 ymm16{z}, ymm13, xmm0, 10 + vinserti64x2 ymm16{z}, ymm13, [rbx], 10 + vinserti64x2 ymm16{z}, ymm13, [rbx+r11*8+256], 10 + vinserti64x2 ymm16{z}, ymm13, [rbx+r11*8-256], 10 + vinserti64x2 ymm16{k5}{z}, ymm13, xmm0, 10 + vinserti64x2 ymm16{k5}{z}, ymm13, [rbx], 10 + vinserti64x2 ymm16{k5}{z}, ymm13, [rbx+r11*8+256], 10 + vinserti64x2 ymm16{k5}{z}, ymm13, [rbx+r11*8-256], 10 + vinserti64x2 zmm24, zmm24, xmm0, 10 + vinserti64x2 zmm24, zmm24, [rbx], 10 + vinserti64x2 zmm24, zmm24, [rbx+r11*8+256], 10 + vinserti64x2 zmm24, zmm24, [rbx+r11*8-256], 10 + vinserti64x2 zmm24{k5}, zmm24, xmm0, 10 + vinserti64x2 zmm24{k5}, zmm24, [rbx], 10 + vinserti64x2 zmm24{k5}, zmm24, [rbx+r11*8+256], 10 + vinserti64x2 zmm24{k5}, zmm24, [rbx+r11*8-256], 10 + vinserti64x2 zmm24{z}, zmm24, xmm0, 10 + vinserti64x2 zmm24{z}, zmm24, [rbx], 10 + vinserti64x2 zmm24{z}, zmm24, [rbx+r11*8+256], 10 + vinserti64x2 zmm24{z}, zmm24, [rbx+r11*8-256], 10 + vinserti64x2 zmm24{k5}{z}, zmm24, xmm0, 10 + vinserti64x2 zmm24{k5}{z}, zmm24, [rbx], 10 + vinserti64x2 zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 10 + vinserti64x2 zmm24{k5}{z}, zmm24, [rbx+r11*8-256], 10 + vorpd xmm2, xmm7, xmm0 + vorpd xmm2, xmm7, [rbx] + vorpd xmm2, xmm7, [rbx]{1to2} + vorpd xmm2, xmm7, [rbx+r11*8+256] + vorpd xmm2, xmm7, [rbx+r11*8-256] + vorpd xmm2{k5}, xmm7, xmm0 + vorpd xmm2{k5}, xmm7, [rbx] + vorpd xmm2{k5}, xmm7, [rbx]{1to2} + vorpd xmm2{k5}, xmm7, [rbx+r11*8+256] + vorpd xmm2{k5}, xmm7, [rbx+r11*8-256] + vorpd xmm2{z}, xmm7, xmm0 + vorpd xmm2{z}, xmm7, [rbx] + vorpd xmm2{z}, xmm7, [rbx]{1to2} + vorpd xmm2{z}, xmm7, [rbx+r11*8+256] + vorpd xmm2{z}, xmm7, [rbx+r11*8-256] + vorpd xmm2{k5}{z}, xmm7, xmm0 + vorpd xmm2{k5}{z}, xmm7, [rbx] + vorpd xmm2{k5}{z}, xmm7, [rbx]{1to2} + vorpd xmm2{k5}{z}, xmm7, [rbx+r11*8+256] + vorpd xmm2{k5}{z}, xmm7, [rbx+r11*8-256] + vorpd ymm16, ymm13, ymm15 + vorpd ymm16, ymm13, [rbx] + vorpd ymm16, ymm13, [rbx]{1to4} + vorpd ymm16, ymm13, [rbx+r11*8+256] + vorpd ymm16, ymm13, [rbx+r11*8-256] + vorpd ymm16{k5}, ymm13, ymm15 + vorpd ymm16{k5}, ymm13, [rbx] + vorpd ymm16{k5}, ymm13, [rbx]{1to4} + vorpd ymm16{k5}, ymm13, [rbx+r11*8+256] + vorpd ymm16{k5}, ymm13, [rbx+r11*8-256] + vorpd ymm16{z}, ymm13, ymm15 + vorpd ymm16{z}, ymm13, [rbx] + vorpd ymm16{z}, ymm13, [rbx]{1to4} + vorpd ymm16{z}, ymm13, [rbx+r11*8+256] + vorpd ymm16{z}, ymm13, [rbx+r11*8-256] + vorpd ymm16{k5}{z}, ymm13, ymm15 + vorpd ymm16{k5}{z}, ymm13, [rbx] + vorpd ymm16{k5}{z}, ymm13, [rbx]{1to4} + vorpd ymm16{k5}{z}, ymm13, [rbx+r11*8+256] + vorpd ymm16{k5}{z}, ymm13, [rbx+r11*8-256] + vorpd zmm24, zmm24, zmm31 + vorpd zmm24, zmm24, [rbx] + vorpd zmm24, zmm24, [rbx]{1to8} + vorpd zmm24, zmm24, [rbx+r11*8+256] + vorpd zmm24, zmm24, [rbx+r11*8-256] + vorpd zmm24{k5}, zmm24, zmm31 + vorpd zmm24{k5}, zmm24, [rbx] + vorpd zmm24{k5}, zmm24, [rbx]{1to8} + vorpd zmm24{k5}, zmm24, [rbx+r11*8+256] + vorpd zmm24{k5}, zmm24, [rbx+r11*8-256] + vorpd zmm24{z}, zmm24, zmm31 + vorpd zmm24{z}, zmm24, [rbx] + vorpd zmm24{z}, zmm24, [rbx]{1to8} + vorpd zmm24{z}, zmm24, [rbx+r11*8+256] + vorpd zmm24{z}, zmm24, [rbx+r11*8-256] + vorpd zmm24{k5}{z}, zmm24, zmm31 + vorpd zmm24{k5}{z}, zmm24, [rbx] + vorpd zmm24{k5}{z}, zmm24, [rbx]{1to8} + vorpd zmm24{k5}{z}, zmm24, [rbx+r11*8+256] + vorpd zmm24{k5}{z}, zmm24, [rbx+r11*8-256] + vorps xmm2, xmm7, xmm0 + vorps xmm2, xmm7, [rbx] + vorps xmm2, xmm7, [rbx]{1to4} + vorps xmm2, xmm7, [rbx+r11*8+256] + vorps xmm2, xmm7, [rbx+r11*8-256] + vorps xmm2{k5}, xmm7, xmm0 + vorps xmm2{k5}, xmm7, [rbx] + vorps xmm2{k5}, xmm7, [rbx]{1to4} + vorps xmm2{k5}, xmm7, [rbx+r11*8+256] + vorps xmm2{k5}, xmm7, [rbx+r11*8-256] + vorps xmm2{z}, xmm7, xmm0 + vorps xmm2{z}, xmm7, [rbx] + vorps xmm2{z}, xmm7, [rbx]{1to4} + vorps xmm2{z}, xmm7, [rbx+r11*8+256] + vorps xmm2{z}, xmm7, [rbx+r11*8-256] + vorps xmm2{k5}{z}, xmm7, xmm0 + vorps xmm2{k5}{z}, xmm7, [rbx] + vorps xmm2{k5}{z}, xmm7, [rbx]{1to4} + vorps xmm2{k5}{z}, xmm7, [rbx+r11*8+256] + vorps xmm2{k5}{z}, xmm7, [rbx+r11*8-256] + vorps ymm16, ymm13, ymm15 + vorps ymm16, ymm13, [rbx] + vorps ymm16, ymm13, [rbx]{1to8} + vorps ymm16, ymm13, [rbx+r11*8+256] + vorps ymm16, ymm13, [rbx+r11*8-256] + vorps ymm16{k5}, ymm13, ymm15 + vorps ymm16{k5}, ymm13, [rbx] + vorps ymm16{k5}, ymm13, [rbx]{1to8} + vorps ymm16{k5}, ymm13, [rbx+r11*8+256] + vorps ymm16{k5}, ymm13, [rbx+r11*8-256] + vorps ymm16{z}, ymm13, ymm15 + vorps ymm16{z}, ymm13, [rbx] + vorps ymm16{z}, ymm13, [rbx]{1to8} + vorps ymm16{z}, ymm13, [rbx+r11*8+256] + vorps ymm16{z}, ymm13, [rbx+r11*8-256] + vorps ymm16{k5}{z}, ymm13, ymm15 + vorps ymm16{k5}{z}, ymm13, [rbx] + vorps ymm16{k5}{z}, ymm13, [rbx]{1to8} + vorps ymm16{k5}{z}, ymm13, [rbx+r11*8+256] + vorps ymm16{k5}{z}, ymm13, [rbx+r11*8-256] + vorps zmm24, zmm24, zmm31 + vorps zmm24, zmm24, [rbx] + vorps zmm24, zmm24, [rbx]{1to16} + vorps zmm24, zmm24, [rbx+r11*8+256] + vorps zmm24, zmm24, [rbx+r11*8-256] + vorps zmm24{k5}, zmm24, zmm31 + vorps zmm24{k5}, zmm24, [rbx] + vorps zmm24{k5}, zmm24, [rbx]{1to16} + vorps zmm24{k5}, zmm24, [rbx+r11*8+256] + vorps zmm24{k5}, zmm24, [rbx+r11*8-256] + vorps zmm24{z}, zmm24, zmm31 + vorps zmm24{z}, zmm24, [rbx] + vorps zmm24{z}, zmm24, [rbx]{1to16} + vorps zmm24{z}, zmm24, [rbx+r11*8+256] + vorps zmm24{z}, zmm24, [rbx+r11*8-256] + vorps zmm24{k5}{z}, zmm24, zmm31 + vorps zmm24{k5}{z}, zmm24, [rbx] + vorps zmm24{k5}{z}, zmm24, [rbx]{1to16} + vorps zmm24{k5}{z}, zmm24, [rbx+r11*8+256] + vorps zmm24{k5}{z}, zmm24, [rbx+r11*8-256] + vpextrd ecx, xmm2, 10 + vpextrd rcx, xmm2, 10 + vpextrd [rbx], xmm2, 10 + vpextrd [rbx+rsi*8+256], xmm2, 10 + vpextrq rcx, xmm2, 10 + vpextrq [rbx], xmm2, 10 + vpextrq [rbx+rsi*8+256], xmm2, 10 + vpinsrd xmm2, xmm7, ecx, 10 + vpinsrd xmm2, xmm7, [rbx], 10 + vpinsrd xmm2, xmm7, [rbx+rsi*8+256], 10 + vpinsrq xmm2, xmm7, rcx, 10 + vpinsrq xmm2, xmm7, [rbx], 10 + vpinsrq xmm2, xmm7, [rbx+rsi*8+256], 10 + vpmovd2m k3, xmm0 + vpmovd2m k3, ymm15 + vpmovd2m k3, zmm31 + vpmovm2d xmm2, k1 + vpmovm2d ymm16, k1 + vpmovm2d zmm24, k1 + vpmovm2q xmm2, k1 + vpmovm2q ymm16, k1 + vpmovm2q zmm24, k1 + vpmovq2m k3, xmm0 + vpmovq2m k3, ymm15 + vpmovq2m k3, zmm31 + vpmullq xmm2, xmm7, xmm0 + vpmullq xmm2, xmm7, [rbx] + vpmullq xmm2, xmm7, [rbx]{1to2} + vpmullq xmm2, xmm7, [rbx+r11*8+256] + vpmullq xmm2, xmm7, [rbx+r11*8-256] + vpmullq xmm2{k5}, xmm7, xmm0 + vpmullq xmm2{k5}, xmm7, [rbx] + vpmullq xmm2{k5}, xmm7, [rbx]{1to2} + vpmullq xmm2{k5}, xmm7, [rbx+r11*8+256] + vpmullq xmm2{k5}, xmm7, [rbx+r11*8-256] + vpmullq xmm2{z}, xmm7, xmm0 + vpmullq xmm2{z}, xmm7, [rbx] + vpmullq xmm2{z}, xmm7, [rbx]{1to2} + vpmullq xmm2{z}, xmm7, [rbx+r11*8+256] + vpmullq xmm2{z}, xmm7, [rbx+r11*8-256] + vpmullq xmm2{k5}{z}, xmm7, xmm0 + vpmullq xmm2{k5}{z}, xmm7, [rbx] + vpmullq xmm2{k5}{z}, xmm7, [rbx]{1to2} + vpmullq xmm2{k5}{z}, xmm7, [rbx+r11*8+256] + vpmullq xmm2{k5}{z}, xmm7, [rbx+r11*8-256] + vpmullq ymm16, ymm13, ymm15 + vpmullq ymm16, ymm13, [rbx] + vpmullq ymm16, ymm13, [rbx]{1to4} + vpmullq ymm16, ymm13, [rbx+r11*8+256] + vpmullq ymm16, ymm13, [rbx+r11*8-256] + vpmullq ymm16{k5}, ymm13, ymm15 + vpmullq ymm16{k5}, ymm13, [rbx] + vpmullq ymm16{k5}, ymm13, [rbx]{1to4} + vpmullq ymm16{k5}, ymm13, [rbx+r11*8+256] + vpmullq ymm16{k5}, ymm13, [rbx+r11*8-256] + vpmullq ymm16{z}, ymm13, ymm15 + vpmullq ymm16{z}, ymm13, [rbx] + vpmullq ymm16{z}, ymm13, [rbx]{1to4} + vpmullq ymm16{z}, ymm13, [rbx+r11*8+256] + vpmullq ymm16{z}, ymm13, [rbx+r11*8-256] + vpmullq ymm16{k5}{z}, ymm13, ymm15 + vpmullq ymm16{k5}{z}, ymm13, [rbx] + vpmullq ymm16{k5}{z}, ymm13, [rbx]{1to4} + vpmullq ymm16{k5}{z}, ymm13, [rbx+r11*8+256] + vpmullq ymm16{k5}{z}, ymm13, [rbx+r11*8-256] + vpmullq zmm24, zmm24, zmm31 + vpmullq zmm24, zmm24, [rbx] + vpmullq zmm24, zmm24, [rbx]{1to8} + vpmullq zmm24, zmm24, [rbx+r11*8+256] + vpmullq zmm24, zmm24, [rbx+r11*8-256] + vpmullq zmm24{k5}, zmm24, zmm31 + vpmullq zmm24{k5}, zmm24, [rbx] + vpmullq zmm24{k5}, zmm24, [rbx]{1to8} + vpmullq zmm24{k5}, zmm24, [rbx+r11*8+256] + vpmullq zmm24{k5}, zmm24, [rbx+r11*8-256] + vpmullq zmm24{z}, zmm24, zmm31 + vpmullq zmm24{z}, zmm24, [rbx] + vpmullq zmm24{z}, zmm24, [rbx]{1to8} + vpmullq zmm24{z}, zmm24, [rbx+r11*8+256] + vpmullq zmm24{z}, zmm24, [rbx+r11*8-256] + vpmullq zmm24{k5}{z}, zmm24, zmm31 + vpmullq zmm24{k5}{z}, zmm24, [rbx] + vpmullq zmm24{k5}{z}, zmm24, [rbx]{1to8} + vpmullq zmm24{k5}{z}, zmm24, [rbx+r11*8+256] + vpmullq zmm24{k5}{z}, zmm24, [rbx+r11*8-256] + vrangepd xmm2, xmm7, xmm0, 10 + vrangepd xmm2, xmm7, [rbx], 10 + vrangepd xmm2, xmm7, [rbx]{1to2}, 10 + vrangepd xmm2, xmm7, [rbx+r11*8+256], 10 + vrangepd xmm2, xmm7, [rbx+r11*8-256], 10 + vrangepd xmm2{k5}, xmm7, xmm0, 10 + vrangepd xmm2{k5}, xmm7, [rbx], 10 + vrangepd xmm2{k5}, xmm7, [rbx]{1to2}, 10 + vrangepd xmm2{k5}, xmm7, [rbx+r11*8+256], 10 + vrangepd xmm2{k5}, xmm7, [rbx+r11*8-256], 10 + vrangepd xmm2{z}, xmm7, xmm0, 10 + vrangepd xmm2{z}, xmm7, [rbx], 10 + vrangepd xmm2{z}, xmm7, [rbx]{1to2}, 10 + vrangepd xmm2{z}, xmm7, [rbx+r11*8+256], 10 + vrangepd xmm2{z}, xmm7, [rbx+r11*8-256], 10 + vrangepd xmm2{k5}{z}, xmm7, xmm0, 10 + vrangepd xmm2{k5}{z}, xmm7, [rbx], 10 + vrangepd xmm2{k5}{z}, xmm7, [rbx]{1to2}, 10 + vrangepd xmm2{k5}{z}, xmm7, [rbx+r11*8+256], 10 + vrangepd xmm2{k5}{z}, xmm7, [rbx+r11*8-256], 10 + vrangepd ymm16, ymm13, ymm15, 10 + vrangepd ymm16, ymm13, [rbx], 10 + vrangepd ymm16, ymm13, [rbx]{1to4}, 10 + vrangepd ymm16, ymm13, [rbx+r11*8+256], 10 + vrangepd ymm16, ymm13, [rbx+r11*8-256], 10 + vrangepd ymm16{k5}, ymm13, ymm15, 10 + vrangepd ymm16{k5}, ymm13, [rbx], 10 + vrangepd ymm16{k5}, ymm13, [rbx]{1to4}, 10 + vrangepd ymm16{k5}, ymm13, [rbx+r11*8+256], 10 + vrangepd ymm16{k5}, ymm13, [rbx+r11*8-256], 10 + vrangepd ymm16{z}, ymm13, ymm15, 10 + vrangepd ymm16{z}, ymm13, [rbx], 10 + vrangepd ymm16{z}, ymm13, [rbx]{1to4}, 10 + vrangepd ymm16{z}, ymm13, [rbx+r11*8+256], 10 + vrangepd ymm16{z}, ymm13, [rbx+r11*8-256], 10 + vrangepd ymm16{k5}{z}, ymm13, ymm15, 10 + vrangepd ymm16{k5}{z}, ymm13, [rbx], 10 + vrangepd ymm16{k5}{z}, ymm13, [rbx]{1to4}, 10 + vrangepd ymm16{k5}{z}, ymm13, [rbx+r11*8+256], 10 + vrangepd ymm16{k5}{z}, ymm13, [rbx+r11*8-256], 10 + vrangepd zmm24, zmm24, zmm31, 10 + vrangepd zmm24, zmm24, [rbx], 10 + vrangepd zmm24, zmm24, [rbx]{1to8}, 10 + vrangepd zmm24, zmm24, [rbx+r11*8+256], 10 + vrangepd zmm24, zmm24, [rbx+r11*8-256], 10 + vrangepd zmm24{k5}, zmm24, zmm31, 10 + vrangepd zmm24{k5}, zmm24, [rbx], 10 + vrangepd zmm24{k5}, zmm24, [rbx]{1to8}, 10 + vrangepd zmm24{k5}, zmm24, [rbx+r11*8+256], 10 + vrangepd zmm24{k5}, zmm24, [rbx+r11*8-256], 10 + vrangepd zmm24{z}, zmm24, zmm31, 10 + vrangepd zmm24{z}, zmm24, [rbx], 10 + vrangepd zmm24{z}, zmm24, [rbx]{1to8}, 10 + vrangepd zmm24{z}, zmm24, [rbx+r11*8+256], 10 + vrangepd zmm24{z}, zmm24, [rbx+r11*8-256], 10 + vrangepd zmm24{k5}{z}, zmm24, zmm31, 10 + vrangepd zmm24{k5}{z}, zmm24, [rbx], 10 + vrangepd zmm24{k5}{z}, zmm24, [rbx]{1to8}, 10 + vrangepd zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 10 + vrangepd zmm24{k5}{z}, zmm24, [rbx+r11*8-256], 10 + vrangeps xmm2, xmm7, xmm0, 10 + vrangeps xmm2, xmm7, [rbx], 10 + vrangeps xmm2, xmm7, [rbx]{1to4}, 10 + vrangeps xmm2, xmm7, [rbx+r11*8+256], 10 + vrangeps xmm2, xmm7, [rbx+r11*8-256], 10 + vrangeps xmm2{k5}, xmm7, xmm0, 10 + vrangeps xmm2{k5}, xmm7, [rbx], 10 + vrangeps xmm2{k5}, xmm7, [rbx]{1to4}, 10 + vrangeps xmm2{k5}, xmm7, [rbx+r11*8+256], 10 + vrangeps xmm2{k5}, xmm7, [rbx+r11*8-256], 10 + vrangeps xmm2{z}, xmm7, xmm0, 10 + vrangeps xmm2{z}, xmm7, [rbx], 10 + vrangeps xmm2{z}, xmm7, [rbx]{1to4}, 10 + vrangeps xmm2{z}, xmm7, [rbx+r11*8+256], 10 + vrangeps xmm2{z}, xmm7, [rbx+r11*8-256], 10 + vrangeps xmm2{k5}{z}, xmm7, xmm0, 10 + vrangeps xmm2{k5}{z}, xmm7, [rbx], 10 + vrangeps xmm2{k5}{z}, xmm7, [rbx]{1to4}, 10 + vrangeps xmm2{k5}{z}, xmm7, [rbx+r11*8+256], 10 + vrangeps xmm2{k5}{z}, xmm7, [rbx+r11*8-256], 10 + vrangeps ymm16, ymm13, ymm15, 10 + vrangeps ymm16, ymm13, [rbx], 10 + vrangeps ymm16, ymm13, [rbx]{1to8}, 10 + vrangeps ymm16, ymm13, [rbx+r11*8+256], 10 + vrangeps ymm16, ymm13, [rbx+r11*8-256], 10 + vrangeps ymm16{k5}, ymm13, ymm15, 10 + vrangeps ymm16{k5}, ymm13, [rbx], 10 + vrangeps ymm16{k5}, ymm13, [rbx]{1to8}, 10 + vrangeps ymm16{k5}, ymm13, [rbx+r11*8+256], 10 + vrangeps ymm16{k5}, ymm13, [rbx+r11*8-256], 10 + vrangeps ymm16{z}, ymm13, ymm15, 10 + vrangeps ymm16{z}, ymm13, [rbx], 10 + vrangeps ymm16{z}, ymm13, [rbx]{1to8}, 10 + vrangeps ymm16{z}, ymm13, [rbx+r11*8+256], 10 + vrangeps ymm16{z}, ymm13, [rbx+r11*8-256], 10 + vrangeps ymm16{k5}{z}, ymm13, ymm15, 10 + vrangeps ymm16{k5}{z}, ymm13, [rbx], 10 + vrangeps ymm16{k5}{z}, ymm13, [rbx]{1to8}, 10 + vrangeps ymm16{k5}{z}, ymm13, [rbx+r11*8+256], 10 + vrangeps ymm16{k5}{z}, ymm13, [rbx+r11*8-256], 10 + vrangeps zmm24, zmm24, zmm31, 10 + vrangeps zmm24, zmm24, [rbx], 10 + vrangeps zmm24, zmm24, [rbx]{1to16}, 10 + vrangeps zmm24, zmm24, [rbx+r11*8+256], 10 + vrangeps zmm24, zmm24, [rbx+r11*8-256], 10 + vrangeps zmm24{k5}, zmm24, zmm31, 10 + vrangeps zmm24{k5}, zmm24, [rbx], 10 + vrangeps zmm24{k5}, zmm24, [rbx]{1to16}, 10 + vrangeps zmm24{k5}, zmm24, [rbx+r11*8+256], 10 + vrangeps zmm24{k5}, zmm24, [rbx+r11*8-256], 10 + vrangeps zmm24{z}, zmm24, zmm31, 10 + vrangeps zmm24{z}, zmm24, [rbx], 10 + vrangeps zmm24{z}, zmm24, [rbx]{1to16}, 10 + vrangeps zmm24{z}, zmm24, [rbx+r11*8+256], 10 + vrangeps zmm24{z}, zmm24, [rbx+r11*8-256], 10 + vrangeps zmm24{k5}{z}, zmm24, zmm31, 10 + vrangeps zmm24{k5}{z}, zmm24, [rbx], 10 + vrangeps zmm24{k5}{z}, zmm24, [rbx]{1to16}, 10 + vrangeps zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 10 + vrangeps zmm24{k5}{z}, zmm24, [rbx+r11*8-256], 10 + vrangesd xmm2, xmm7, xmm0, 10 + vrangesd xmm2, xmm7, [rbx], 10 + vrangesd xmm2, xmm7, [rbx+r11*8+256], 10 + vrangesd xmm2, xmm7, [rbx+r11*8-256], 10 + vrangesd xmm2{k5}, xmm7, xmm0, 10 + vrangesd xmm2{k5}, xmm7, [rbx], 10 + vrangesd xmm2{k5}, xmm7, [rbx+r11*8+256], 10 + vrangesd xmm2{k5}, xmm7, [rbx+r11*8-256], 10 + vrangesd xmm2{z}, xmm7, xmm0, 10 + vrangesd xmm2{z}, xmm7, [rbx], 10 + vrangesd xmm2{z}, xmm7, [rbx+r11*8+256], 10 + vrangesd xmm2{z}, xmm7, [rbx+r11*8-256], 10 + vrangesd xmm2{k5}{z}, xmm7, xmm0, 10 + vrangesd xmm2{k5}{z}, xmm7, [rbx], 10 + vrangesd xmm2{k5}{z}, xmm7, [rbx+r11*8+256], 10 + vrangesd xmm2{k5}{z}, xmm7, [rbx+r11*8-256], 10 + vrangess xmm2, xmm7, xmm0, 10 + vrangess xmm2, xmm7, [rbx], 10 + vrangess xmm2, xmm7, [rbx+r11*8+256], 10 + vrangess xmm2, xmm7, [rbx+r11*8-256], 10 + vrangess xmm2{k5}, xmm7, xmm0, 10 + vrangess xmm2{k5}, xmm7, [rbx], 10 + vrangess xmm2{k5}, xmm7, [rbx+r11*8+256], 10 + vrangess xmm2{k5}, xmm7, [rbx+r11*8-256], 10 + vrangess xmm2{z}, xmm7, xmm0, 10 + vrangess xmm2{z}, xmm7, [rbx], 10 + vrangess xmm2{z}, xmm7, [rbx+r11*8+256], 10 + vrangess xmm2{z}, xmm7, [rbx+r11*8-256], 10 + vrangess xmm2{k5}{z}, xmm7, xmm0, 10 + vrangess xmm2{k5}{z}, xmm7, [rbx], 10 + vrangess xmm2{k5}{z}, xmm7, [rbx+r11*8+256], 10 + vrangess xmm2{k5}{z}, xmm7, [rbx+r11*8-256], 10 + vreducepd xmm2, xmm0, 10 + vreducepd xmm2, [rbx], 10 + vreducepd xmm2, [rbx]{1to2}, 10 + vreducepd xmm2, [rbx+r11*8+256], 10 + vreducepd xmm2, [rbx+r11*8-256], 10 + vreducepd xmm2{k5}, xmm0, 10 + vreducepd xmm2{k5}, [rbx], 10 + vreducepd xmm2{k5}, [rbx]{1to2}, 10 + vreducepd xmm2{k5}, [rbx+r11*8+256], 10 + vreducepd xmm2{k5}, [rbx+r11*8-256], 10 + vreducepd xmm2{z}, xmm0, 10 + vreducepd xmm2{z}, [rbx], 10 + vreducepd xmm2{z}, [rbx]{1to2}, 10 + vreducepd xmm2{z}, [rbx+r11*8+256], 10 + vreducepd xmm2{z}, [rbx+r11*8-256], 10 + vreducepd xmm2{k5}{z}, xmm0, 10 + vreducepd xmm2{k5}{z}, [rbx], 10 + vreducepd xmm2{k5}{z}, [rbx]{1to2}, 10 + vreducepd xmm2{k5}{z}, [rbx+r11*8+256], 10 + vreducepd xmm2{k5}{z}, [rbx+r11*8-256], 10 + vreducepd ymm16, ymm15, 10 + vreducepd ymm16, [rbx], 10 + vreducepd ymm16, [rbx]{1to4}, 10 + vreducepd ymm16, [rbx+r11*8+256], 10 + vreducepd ymm16, [rbx+r11*8-256], 10 + vreducepd ymm16{k5}, ymm15, 10 + vreducepd ymm16{k5}, [rbx], 10 + vreducepd ymm16{k5}, [rbx]{1to4}, 10 + vreducepd ymm16{k5}, [rbx+r11*8+256], 10 + vreducepd ymm16{k5}, [rbx+r11*8-256], 10 + vreducepd ymm16{z}, ymm15, 10 + vreducepd ymm16{z}, [rbx], 10 + vreducepd ymm16{z}, [rbx]{1to4}, 10 + vreducepd ymm16{z}, [rbx+r11*8+256], 10 + vreducepd ymm16{z}, [rbx+r11*8-256], 10 + vreducepd ymm16{k5}{z}, ymm15, 10 + vreducepd ymm16{k5}{z}, [rbx], 10 + vreducepd ymm16{k5}{z}, [rbx]{1to4}, 10 + vreducepd ymm16{k5}{z}, [rbx+r11*8+256], 10 + vreducepd ymm16{k5}{z}, [rbx+r11*8-256], 10 + vreducepd zmm24, zmm31, 10 + vreducepd zmm24, [rbx], 10 + vreducepd zmm24, [rbx]{1to8}, 10 + vreducepd zmm24, [rbx+r11*8+256], 10 + vreducepd zmm24, [rbx+r11*8-256], 10 + vreducepd zmm24{k5}, zmm31, 10 + vreducepd zmm24{k5}, [rbx], 10 + vreducepd zmm24{k5}, [rbx]{1to8}, 10 + vreducepd zmm24{k5}, [rbx+r11*8+256], 10 + vreducepd zmm24{k5}, [rbx+r11*8-256], 10 + vreducepd zmm24{z}, zmm31, 10 + vreducepd zmm24{z}, [rbx], 10 + vreducepd zmm24{z}, [rbx]{1to8}, 10 + vreducepd zmm24{z}, [rbx+r11*8+256], 10 + vreducepd zmm24{z}, [rbx+r11*8-256], 10 + vreducepd zmm24{k5}{z}, zmm31, 10 + vreducepd zmm24{k5}{z}, [rbx], 10 + vreducepd zmm24{k5}{z}, [rbx]{1to8}, 10 + vreducepd zmm24{k5}{z}, [rbx+r11*8+256], 10 + vreducepd zmm24{k5}{z}, [rbx+r11*8-256], 10 + vreduceps xmm2, xmm0, 10 + vreduceps xmm2, [rbx], 10 + vreduceps xmm2, [rbx]{1to4}, 10 + vreduceps xmm2, [rbx+r11*8+256], 10 + vreduceps xmm2, [rbx+r11*8-256], 10 + vreduceps xmm2{k5}, xmm0, 10 + vreduceps xmm2{k5}, [rbx], 10 + vreduceps xmm2{k5}, [rbx]{1to4}, 10 + vreduceps xmm2{k5}, [rbx+r11*8+256], 10 + vreduceps xmm2{k5}, [rbx+r11*8-256], 10 + vreduceps xmm2{z}, xmm0, 10 + vreduceps xmm2{z}, [rbx], 10 + vreduceps xmm2{z}, [rbx]{1to4}, 10 + vreduceps xmm2{z}, [rbx+r11*8+256], 10 + vreduceps xmm2{z}, [rbx+r11*8-256], 10 + vreduceps xmm2{k5}{z}, xmm0, 10 + vreduceps xmm2{k5}{z}, [rbx], 10 + vreduceps xmm2{k5}{z}, [rbx]{1to4}, 10 + vreduceps xmm2{k5}{z}, [rbx+r11*8+256], 10 + vreduceps xmm2{k5}{z}, [rbx+r11*8-256], 10 + vreduceps ymm16, ymm15, 10 + vreduceps ymm16, [rbx], 10 + vreduceps ymm16, [rbx]{1to8}, 10 + vreduceps ymm16, [rbx+r11*8+256], 10 + vreduceps ymm16, [rbx+r11*8-256], 10 + vreduceps ymm16{k5}, ymm15, 10 + vreduceps ymm16{k5}, [rbx], 10 + vreduceps ymm16{k5}, [rbx]{1to8}, 10 + vreduceps ymm16{k5}, [rbx+r11*8+256], 10 + vreduceps ymm16{k5}, [rbx+r11*8-256], 10 + vreduceps ymm16{z}, ymm15, 10 + vreduceps ymm16{z}, [rbx], 10 + vreduceps ymm16{z}, [rbx]{1to8}, 10 + vreduceps ymm16{z}, [rbx+r11*8+256], 10 + vreduceps ymm16{z}, [rbx+r11*8-256], 10 + vreduceps ymm16{k5}{z}, ymm15, 10 + vreduceps ymm16{k5}{z}, [rbx], 10 + vreduceps ymm16{k5}{z}, [rbx]{1to8}, 10 + vreduceps ymm16{k5}{z}, [rbx+r11*8+256], 10 + vreduceps ymm16{k5}{z}, [rbx+r11*8-256], 10 + vreduceps zmm24, zmm31, 10 + vreduceps zmm24, [rbx], 10 + vreduceps zmm24, [rbx]{1to16}, 10 + vreduceps zmm24, [rbx+r11*8+256], 10 + vreduceps zmm24, [rbx+r11*8-256], 10 + vreduceps zmm24{k5}, zmm31, 10 + vreduceps zmm24{k5}, [rbx], 10 + vreduceps zmm24{k5}, [rbx]{1to16}, 10 + vreduceps zmm24{k5}, [rbx+r11*8+256], 10 + vreduceps zmm24{k5}, [rbx+r11*8-256], 10 + vreduceps zmm24{z}, zmm31, 10 + vreduceps zmm24{z}, [rbx], 10 + vreduceps zmm24{z}, [rbx]{1to16}, 10 + vreduceps zmm24{z}, [rbx+r11*8+256], 10 + vreduceps zmm24{z}, [rbx+r11*8-256], 10 + vreduceps zmm24{k5}{z}, zmm31, 10 + vreduceps zmm24{k5}{z}, [rbx], 10 + vreduceps zmm24{k5}{z}, [rbx]{1to16}, 10 + vreduceps zmm24{k5}{z}, [rbx+r11*8+256], 10 + vreduceps zmm24{k5}{z}, [rbx+r11*8-256], 10 + vreducesd xmm2, xmm7, xmm0, 10 + vreducesd xmm2, xmm7, [rbx], 10 + vreducesd xmm2, xmm7, [rbx+r11*8+256], 10 + vreducesd xmm2, xmm7, [rbx+r11*8-256], 10 + vreducesd xmm2{k5}, xmm7, xmm0, 10 + vreducesd xmm2{k5}, xmm7, [rbx], 10 + vreducesd xmm2{k5}, xmm7, [rbx+r11*8+256], 10 + vreducesd xmm2{k5}, xmm7, [rbx+r11*8-256], 10 + vreducesd xmm2{z}, xmm7, xmm0, 10 + vreducesd xmm2{z}, xmm7, [rbx], 10 + vreducesd xmm2{z}, xmm7, [rbx+r11*8+256], 10 + vreducesd xmm2{z}, xmm7, [rbx+r11*8-256], 10 + vreducesd xmm2{k5}{z}, xmm7, xmm0, 10 + vreducesd xmm2{k5}{z}, xmm7, [rbx], 10 + vreducesd xmm2{k5}{z}, xmm7, [rbx+r11*8+256], 10 + vreducesd xmm2{k5}{z}, xmm7, [rbx+r11*8-256], 10 + vreducess xmm2, xmm7, xmm0, 10 + vreducess xmm2, xmm7, [rbx], 10 + vreducess xmm2, xmm7, [rbx+r11*8+256], 10 + vreducess xmm2, xmm7, [rbx+r11*8-256], 10 + vreducess xmm2{k5}, xmm7, xmm0, 10 + vreducess xmm2{k5}, xmm7, [rbx], 10 + vreducess xmm2{k5}, xmm7, [rbx+r11*8+256], 10 + vreducess xmm2{k5}, xmm7, [rbx+r11*8-256], 10 + vreducess xmm2{z}, xmm7, xmm0, 10 + vreducess xmm2{z}, xmm7, [rbx], 10 + vreducess xmm2{z}, xmm7, [rbx+r11*8+256], 10 + vreducess xmm2{z}, xmm7, [rbx+r11*8-256], 10 + vreducess xmm2{k5}{z}, xmm7, xmm0, 10 + vreducess xmm2{k5}{z}, xmm7, [rbx], 10 + vreducess xmm2{k5}{z}, xmm7, [rbx+r11*8+256], 10 + vreducess xmm2{k5}{z}, xmm7, [rbx+r11*8-256], 10 + vxorpd xmm2, xmm7, xmm0 + vxorpd xmm2, xmm7, [rbx] + vxorpd xmm2, xmm7, [rbx]{1to2} + vxorpd xmm2, xmm7, [rbx+r11*8+256] + vxorpd xmm2, xmm7, [rbx+r11*8-256] + vxorpd xmm2{k5}, xmm7, xmm0 + vxorpd xmm2{k5}, xmm7, [rbx] + vxorpd xmm2{k5}, xmm7, [rbx]{1to2} + vxorpd xmm2{k5}, xmm7, [rbx+r11*8+256] + vxorpd xmm2{k5}, xmm7, [rbx+r11*8-256] + vxorpd xmm2{z}, xmm7, xmm0 + vxorpd xmm2{z}, xmm7, [rbx] + vxorpd xmm2{z}, xmm7, [rbx]{1to2} + vxorpd xmm2{z}, xmm7, [rbx+r11*8+256] + vxorpd xmm2{z}, xmm7, [rbx+r11*8-256] + vxorpd xmm2{k5}{z}, xmm7, xmm0 + vxorpd xmm2{k5}{z}, xmm7, [rbx] + vxorpd xmm2{k5}{z}, xmm7, [rbx]{1to2} + vxorpd xmm2{k5}{z}, xmm7, [rbx+r11*8+256] + vxorpd xmm2{k5}{z}, xmm7, [rbx+r11*8-256] + vxorpd ymm16, ymm13, ymm15 + vxorpd ymm16, ymm13, [rbx] + vxorpd ymm16, ymm13, [rbx]{1to4} + vxorpd ymm16, ymm13, [rbx+r11*8+256] + vxorpd ymm16, ymm13, [rbx+r11*8-256] + vxorpd ymm16{k5}, ymm13, ymm15 + vxorpd ymm16{k5}, ymm13, [rbx] + vxorpd ymm16{k5}, ymm13, [rbx]{1to4} + vxorpd ymm16{k5}, ymm13, [rbx+r11*8+256] + vxorpd ymm16{k5}, ymm13, [rbx+r11*8-256] + vxorpd ymm16{z}, ymm13, ymm15 + vxorpd ymm16{z}, ymm13, [rbx] + vxorpd ymm16{z}, ymm13, [rbx]{1to4} + vxorpd ymm16{z}, ymm13, [rbx+r11*8+256] + vxorpd ymm16{z}, ymm13, [rbx+r11*8-256] + vxorpd ymm16{k5}{z}, ymm13, ymm15 + vxorpd ymm16{k5}{z}, ymm13, [rbx] + vxorpd ymm16{k5}{z}, ymm13, [rbx]{1to4} + vxorpd ymm16{k5}{z}, ymm13, [rbx+r11*8+256] + vxorpd ymm16{k5}{z}, ymm13, [rbx+r11*8-256] + vxorpd zmm24, zmm24, zmm31 + vxorpd zmm24, zmm24, [rbx] + vxorpd zmm24, zmm24, [rbx]{1to8} + vxorpd zmm24, zmm24, [rbx+r11*8+256] + vxorpd zmm24, zmm24, [rbx+r11*8-256] + vxorpd zmm24{k5}, zmm24, zmm31 + vxorpd zmm24{k5}, zmm24, [rbx] + vxorpd zmm24{k5}, zmm24, [rbx]{1to8} + vxorpd zmm24{k5}, zmm24, [rbx+r11*8+256] + vxorpd zmm24{k5}, zmm24, [rbx+r11*8-256] + vxorpd zmm24{z}, zmm24, zmm31 + vxorpd zmm24{z}, zmm24, [rbx] + vxorpd zmm24{z}, zmm24, [rbx]{1to8} + vxorpd zmm24{z}, zmm24, [rbx+r11*8+256] + vxorpd zmm24{z}, zmm24, [rbx+r11*8-256] + vxorpd zmm24{k5}{z}, zmm24, zmm31 + vxorpd zmm24{k5}{z}, zmm24, [rbx] + vxorpd zmm24{k5}{z}, zmm24, [rbx]{1to8} + vxorpd zmm24{k5}{z}, zmm24, [rbx+r11*8+256] + vxorpd zmm24{k5}{z}, zmm24, [rbx+r11*8-256] + vxorps xmm2, xmm7, xmm0 + vxorps xmm2, xmm7, [rbx] + vxorps xmm2, xmm7, [rbx]{1to4} + vxorps xmm2, xmm7, [rbx+r11*8+256] + vxorps xmm2, xmm7, [rbx+r11*8-256] + vxorps xmm2{k5}, xmm7, xmm0 + vxorps xmm2{k5}, xmm7, [rbx] + vxorps xmm2{k5}, xmm7, [rbx]{1to4} + vxorps xmm2{k5}, xmm7, [rbx+r11*8+256] + vxorps xmm2{k5}, xmm7, [rbx+r11*8-256] + vxorps xmm2{z}, xmm7, xmm0 + vxorps xmm2{z}, xmm7, [rbx] + vxorps xmm2{z}, xmm7, [rbx]{1to4} + vxorps xmm2{z}, xmm7, [rbx+r11*8+256] + vxorps xmm2{z}, xmm7, [rbx+r11*8-256] + vxorps xmm2{k5}{z}, xmm7, xmm0 + vxorps xmm2{k5}{z}, xmm7, [rbx] + vxorps xmm2{k5}{z}, xmm7, [rbx]{1to4} + vxorps xmm2{k5}{z}, xmm7, [rbx+r11*8+256] + vxorps xmm2{k5}{z}, xmm7, [rbx+r11*8-256] + vxorps ymm16, ymm13, ymm15 + vxorps ymm16, ymm13, [rbx] + vxorps ymm16, ymm13, [rbx]{1to8} + vxorps ymm16, ymm13, [rbx+r11*8+256] + vxorps ymm16, ymm13, [rbx+r11*8-256] + vxorps ymm16{k5}, ymm13, ymm15 + vxorps ymm16{k5}, ymm13, [rbx] + vxorps ymm16{k5}, ymm13, [rbx]{1to8} + vxorps ymm16{k5}, ymm13, [rbx+r11*8+256] + vxorps ymm16{k5}, ymm13, [rbx+r11*8-256] + vxorps ymm16{z}, ymm13, ymm15 + vxorps ymm16{z}, ymm13, [rbx] + vxorps ymm16{z}, ymm13, [rbx]{1to8} + vxorps ymm16{z}, ymm13, [rbx+r11*8+256] + vxorps ymm16{z}, ymm13, [rbx+r11*8-256] + vxorps ymm16{k5}{z}, ymm13, ymm15 + vxorps ymm16{k5}{z}, ymm13, [rbx] + vxorps ymm16{k5}{z}, ymm13, [rbx]{1to8} + vxorps ymm16{k5}{z}, ymm13, [rbx+r11*8+256] + vxorps ymm16{k5}{z}, ymm13, [rbx+r11*8-256] + vxorps zmm24, zmm24, zmm31 + vxorps zmm24, zmm24, [rbx] + vxorps zmm24, zmm24, [rbx]{1to16} + vxorps zmm24, zmm24, [rbx+r11*8+256] + vxorps zmm24, zmm24, [rbx+r11*8-256] + vxorps zmm24{k5}, zmm24, zmm31 + vxorps zmm24{k5}, zmm24, [rbx] + vxorps zmm24{k5}, zmm24, [rbx]{1to16} + vxorps zmm24{k5}, zmm24, [rbx+r11*8+256] + vxorps zmm24{k5}, zmm24, [rbx+r11*8-256] + vxorps zmm24{z}, zmm24, zmm31 + vxorps zmm24{z}, zmm24, [rbx] + vxorps zmm24{z}, zmm24, [rbx]{1to16} + vxorps zmm24{z}, zmm24, [rbx+r11*8+256] + vxorps zmm24{z}, zmm24, [rbx+r11*8-256] + vxorps zmm24{k5}{z}, zmm24, zmm31 + vxorps zmm24{k5}{z}, zmm24, [rbx] + vxorps zmm24{k5}{z}, zmm24, [rbx]{1to16} + vxorps zmm24{k5}{z}, zmm24, [rbx+r11*8+256] + vxorps zmm24{k5}{z}, zmm24, [rbx+r11*8-256] diff --git a/bddisasm_test/avx512/avx512dq_64.result b/bddisasm_test/avx512/avx512dq_64.result new file mode 100644 index 0000000..78f740a --- /dev/null +++ b/bddisasm_test/avx512/avx512dq_64.result @@ -0,0 +1,39404 @@ +0000000000000000 c5c54ad9 KADDB k3, k7, k1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512DQ, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + Exception class: Opmask, exception type: K20 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: Mask, RegSize: 8, RegId: 1, RegCount: 1 + +0000000000000004 c5c44ad9 KADDW k3, k7, k1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512DQ, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + Exception class: Opmask, exception type: K20 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: Mask, RegSize: 8, RegId: 1, RegCount: 1 + +0000000000000008 c5c541d9 KANDB k3, k7, k1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512DQ, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + Exception class: Opmask, exception type: K20 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: Mask, RegSize: 8, RegId: 1, RegCount: 1 + +000000000000000C c5c542d9 KANDNB k3, k7, k1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512DQ, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + Exception class: Opmask, exception type: K20 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: Mask, RegSize: 8, RegId: 1, RegCount: 1 + +0000000000000010 c5f9901b KMOVB k3, byte ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512DQ, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + Exception class: Opmask, exception type: K21 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + +0000000000000014 c5f9909cf300010000 KMOVB k3, byte ptr [rbx+rsi*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512DQ, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + Exception class: Opmask, exception type: K21 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + +000000000000001D c5f9909cf300ffffff KMOVB k3, byte ptr [rbx+rsi*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512DQ, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + Exception class: Opmask, exception type: K21 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + +0000000000000026 c5f990d9 KMOVB k3, k1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512DQ, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + Exception class: Opmask, exception type: K20 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: Mask, RegSize: 8, RegId: 1, RegCount: 1 + +000000000000002A c5f9901b KMOVB k3, byte ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512DQ, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + Exception class: Opmask, exception type: K21 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + +000000000000002E c5f9911b KMOVB byte ptr [rbx], k3 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512DQ, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + Exception class: Opmask, exception type: K21 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + +0000000000000032 c5f9919cf300010000 KMOVB byte ptr [rbx+rsi*8+0x100], k3 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512DQ, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + Exception class: Opmask, exception type: K21 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + +000000000000003B c5f9919cf300ffffff KMOVB byte ptr [rbx+rsi*8-0x100], k3 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512DQ, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + Exception class: Opmask, exception type: K21 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xffffffffffffff00, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + +0000000000000044 c5f992d9 KMOVB k3, ecx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512DQ, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + Exception class: Opmask, exception type: K20 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + +0000000000000048 c5f993c9 KMOVB ecx, k1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512DQ, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + Exception class: Opmask, exception type: K20 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: Mask, RegSize: 8, RegId: 1, RegCount: 1 + +000000000000004C c5f944d9 KNOTB k3, k1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512DQ, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + Exception class: Opmask, exception type: K20 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: Mask, RegSize: 8, RegId: 1, RegCount: 1 + +0000000000000050 c5c545d9 KORB k3, k7, k1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512DQ, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + Exception class: Opmask, exception type: K20 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: Mask, RegSize: 8, RegId: 1, RegCount: 1 + +0000000000000054 c5f998d9 KORTESTB k3, k1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512DQ, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + Exception class: Opmask, exception type: K20 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: Mask, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000058 c4e37932d90a KSHIFTLB k3, k1, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512DQ, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + Exception class: Opmask, exception type: K20 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: Mask, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000005E c4e37930d90a KSHIFTRB k3, k1, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512DQ, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + Exception class: Opmask, exception type: K20 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: Mask, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000064 c5f999d9 KTESTB k3, k1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512DQ, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + Exception class: Opmask, exception type: K20 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: Mask, RegSize: 8, RegId: 1, RegCount: 1 + +0000000000000068 c5f899d9 KTESTW k3, k1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512DQ, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + Exception class: Opmask, exception type: K20 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: Mask, RegSize: 8, RegId: 1, RegCount: 1 + +000000000000006C c5c546d9 KXNORB k3, k7, k1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512DQ, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + Exception class: Opmask, exception type: K20 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: Mask, RegSize: 8, RegId: 1, RegCount: 1 + +0000000000000070 c5c547d9 KXORB k3, k7, k1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512DQ, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + Exception class: Opmask, exception type: K20 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: Mask, RegSize: 8, RegId: 1, RegCount: 1 + +0000000000000074 c5c155d0 VANDNPD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000078 c5c15513 VANDNPD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000007C 62f1c5185513 VANDNPD xmm2, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000000082 c4a1415594db00010000 VANDNPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000008C c4a1415594db00ffffff VANDNPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000000096 62f1c50d55d0 VANDNPD xmm2{k5}, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000009C 62f1c50d5513 VANDNPD xmm2{k5}, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000000A2 62f1c51d5513 VANDNPD xmm2{k5}, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +00000000000000A8 62b1c50d5554db10 VANDNPD xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000000B0 62b1c50d5554dbf0 VANDNPD xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000000B8 62f1c58855d0 VANDNPD xmm2, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000000BE 62f1c5885513 VANDNPD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000000C4 62f1c5985513 VANDNPD xmm2, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +00000000000000CA 62b1c5885554db10 VANDNPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000000D2 62b1c5885554dbf0 VANDNPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000000DA 62f1c58d55d0 VANDNPD xmm2{k5}{z}, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000000E0 62f1c58d5513 VANDNPD xmm2{k5}{z}, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000000E6 62f1c59d5513 VANDNPD xmm2{k5}{z}, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +00000000000000EC 62b1c58d5554db10 VANDNPD xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000000F4 62b1c58d5554dbf0 VANDNPD xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000000FC 62c1952855c7 VANDNPD ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000102 62e195285503 VANDNPD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000108 62e195385503 VANDNPD ymm16, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +000000000000010E 62a195285544db08 VANDNPD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000116 62a195285544dbf8 VANDNPD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000011E 62c1952d55c7 VANDNPD ymm16{k5}, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000124 62e1952d5503 VANDNPD ymm16{k5}, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000012A 62e1953d5503 VANDNPD ymm16{k5}, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000000130 62a1952d5544db08 VANDNPD ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000138 62a1952d5544dbf8 VANDNPD ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000140 62c195a855c7 VANDNPD ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000146 62e195a85503 VANDNPD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000014C 62e195b85503 VANDNPD ymm16, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000000152 62a195a85544db08 VANDNPD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000015A 62a195a85544dbf8 VANDNPD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000162 62c195ad55c7 VANDNPD ymm16{k5}{z}, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000168 62e195ad5503 VANDNPD ymm16{k5}{z}, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000016E 62e195bd5503 VANDNPD ymm16{k5}{z}, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000000174 62a195ad5544db08 VANDNPD ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000017C 62a195ad5544dbf8 VANDNPD ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000184 6201bd4055c7 VANDNPD zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000018A 6261bd405503 VANDNPD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000190 6261bd505503 VANDNPD zmm24, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000000196 6221bd405544db04 VANDNPD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000019E 6221bd405544dbfc VANDNPD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000001A6 6201bd4555c7 VANDNPD zmm24{k5}, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000001AC 6261bd455503 VANDNPD zmm24{k5}, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000001B2 6261bd555503 VANDNPD zmm24{k5}, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +00000000000001B8 6221bd455544db04 VANDNPD zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000001C0 6221bd455544dbfc VANDNPD zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000001C8 6201bdc055c7 VANDNPD zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000001CE 6261bdc05503 VANDNPD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000001D4 6261bdd05503 VANDNPD zmm24, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +00000000000001DA 6221bdc05544db04 VANDNPD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000001E2 6221bdc05544dbfc VANDNPD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000001EA 6201bdc555c7 VANDNPD zmm24{k5}{z}, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000001F0 6261bdc55503 VANDNPD zmm24{k5}{z}, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000001F6 6261bdd55503 VANDNPD zmm24{k5}{z}, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +00000000000001FC 6221bdc55544db04 VANDNPD zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000204 6221bdc55544dbfc VANDNPD zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000020C c5c055d0 VANDNPS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000210 c5c05513 VANDNPS xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000214 62f144185513 VANDNPS xmm2, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +000000000000021A c4a1405594db00010000 VANDNPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000224 c4a1405594db00ffffff VANDNPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +000000000000022E 62f1440d55d0 VANDNPS xmm2{k5}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000234 62f1440d5513 VANDNPS xmm2{k5}, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000023A 62f1441d5513 VANDNPS xmm2{k5}, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000000240 62b1440d5554db10 VANDNPS xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000248 62b1440d5554dbf0 VANDNPS xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000250 62f1448855d0 VANDNPS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000256 62f144885513 VANDNPS xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000025C 62f144985513 VANDNPS xmm2, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000000262 62b144885554db10 VANDNPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000026A 62b144885554dbf0 VANDNPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000272 62f1448d55d0 VANDNPS xmm2{k5}{z}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000278 62f1448d5513 VANDNPS xmm2{k5}{z}, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000027E 62f1449d5513 VANDNPS xmm2{k5}{z}, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000000284 62b1448d5554db10 VANDNPS xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000028C 62b1448d5554dbf0 VANDNPS xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000294 62c1142855c7 VANDNPS ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000029A 62e114285503 VANDNPS ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000002A0 62e114385503 VANDNPS ymm16, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +00000000000002A6 62a114285544db08 VANDNPS ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000002AE 62a114285544dbf8 VANDNPS ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000002B6 62c1142d55c7 VANDNPS ymm16{k5}, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000002BC 62e1142d5503 VANDNPS ymm16{k5}, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000002C2 62e1143d5503 VANDNPS ymm16{k5}, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +00000000000002C8 62a1142d5544db08 VANDNPS ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000002D0 62a1142d5544dbf8 VANDNPS ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000002D8 62c114a855c7 VANDNPS ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000002DE 62e114a85503 VANDNPS ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000002E4 62e114b85503 VANDNPS ymm16, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +00000000000002EA 62a114a85544db08 VANDNPS ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000002F2 62a114a85544dbf8 VANDNPS ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000002FA 62c114ad55c7 VANDNPS ymm16{k5}{z}, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000300 62e114ad5503 VANDNPS ymm16{k5}{z}, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000306 62e114bd5503 VANDNPS ymm16{k5}{z}, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +000000000000030C 62a114ad5544db08 VANDNPS ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000314 62a114ad5544dbf8 VANDNPS ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000031C 62013c4055c7 VANDNPS zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000322 62613c405503 VANDNPS zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000328 62613c505503 VANDNPS zmm24, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +000000000000032E 62213c405544db04 VANDNPS zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000336 62213c405544dbfc VANDNPS zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000033E 62013c4555c7 VANDNPS zmm24{k5}, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000344 62613c455503 VANDNPS zmm24{k5}, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000034A 62613c555503 VANDNPS zmm24{k5}, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000000350 62213c455544db04 VANDNPS zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000358 62213c455544dbfc VANDNPS zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000360 62013cc055c7 VANDNPS zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000366 62613cc05503 VANDNPS zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000036C 62613cd05503 VANDNPS zmm24, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000000372 62213cc05544db04 VANDNPS zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000037A 62213cc05544dbfc VANDNPS zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000382 62013cc555c7 VANDNPS zmm24{k5}{z}, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000388 62613cc55503 VANDNPS zmm24{k5}{z}, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000038E 62613cd55503 VANDNPS zmm24{k5}{z}, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000000394 62213cc55544db04 VANDNPS zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000039C 62213cc55544dbfc VANDNPS zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000003A4 c5c154d0 VANDPD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000003A8 c5c15413 VANDPD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000003AC 62f1c5185413 VANDPD xmm2, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +00000000000003B2 c4a1415494db00010000 VANDPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000003BC c4a1415494db00ffffff VANDPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000003C6 62f1c50d54d0 VANDPD xmm2{k5}, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000003CC 62f1c50d5413 VANDPD xmm2{k5}, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000003D2 62f1c51d5413 VANDPD xmm2{k5}, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +00000000000003D8 62b1c50d5454db10 VANDPD xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000003E0 62b1c50d5454dbf0 VANDPD xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000003E8 62f1c58854d0 VANDPD xmm2, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000003EE 62f1c5885413 VANDPD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000003F4 62f1c5985413 VANDPD xmm2, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +00000000000003FA 62b1c5885454db10 VANDPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000402 62b1c5885454dbf0 VANDPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000040A 62f1c58d54d0 VANDPD xmm2{k5}{z}, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000410 62f1c58d5413 VANDPD xmm2{k5}{z}, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000416 62f1c59d5413 VANDPD xmm2{k5}{z}, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +000000000000041C 62b1c58d5454db10 VANDPD xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000424 62b1c58d5454dbf0 VANDPD xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000042C 62c1952854c7 VANDPD ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000432 62e195285403 VANDPD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000438 62e195385403 VANDPD ymm16, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +000000000000043E 62a195285444db08 VANDPD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000446 62a195285444dbf8 VANDPD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000044E 62c1952d54c7 VANDPD ymm16{k5}, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000454 62e1952d5403 VANDPD ymm16{k5}, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000045A 62e1953d5403 VANDPD ymm16{k5}, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000000460 62a1952d5444db08 VANDPD ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000468 62a1952d5444dbf8 VANDPD ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000470 62c195a854c7 VANDPD ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000476 62e195a85403 VANDPD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000047C 62e195b85403 VANDPD ymm16, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000000482 62a195a85444db08 VANDPD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000048A 62a195a85444dbf8 VANDPD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000492 62c195ad54c7 VANDPD ymm16{k5}{z}, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000498 62e195ad5403 VANDPD ymm16{k5}{z}, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000049E 62e195bd5403 VANDPD ymm16{k5}{z}, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +00000000000004A4 62a195ad5444db08 VANDPD ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000004AC 62a195ad5444dbf8 VANDPD ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000004B4 6201bd4054c7 VANDPD zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000004BA 6261bd405403 VANDPD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000004C0 6261bd505403 VANDPD zmm24, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +00000000000004C6 6221bd405444db04 VANDPD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000004CE 6221bd405444dbfc VANDPD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000004D6 6201bd4554c7 VANDPD zmm24{k5}, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000004DC 6261bd455403 VANDPD zmm24{k5}, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000004E2 6261bd555403 VANDPD zmm24{k5}, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +00000000000004E8 6221bd455444db04 VANDPD zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000004F0 6221bd455444dbfc VANDPD zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000004F8 6201bdc054c7 VANDPD zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000004FE 6261bdc05403 VANDPD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000504 6261bdd05403 VANDPD zmm24, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +000000000000050A 6221bdc05444db04 VANDPD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000512 6221bdc05444dbfc VANDPD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000051A 6201bdc554c7 VANDPD zmm24{k5}{z}, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000520 6261bdc55403 VANDPD zmm24{k5}{z}, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000526 6261bdd55403 VANDPD zmm24{k5}{z}, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +000000000000052C 6221bdc55444db04 VANDPD zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000534 6221bdc55444dbfc VANDPD zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000053C c5c054d0 VANDPS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000540 c5c05413 VANDPS xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000544 62f144185413 VANDPS xmm2, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +000000000000054A c4a1405494db00010000 VANDPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +0000000000000554 c4a1405494db00ffffff VANDPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +000000000000055E 62f1440d54d0 VANDPS xmm2{k5}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000564 62f1440d5413 VANDPS xmm2{k5}, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000056A 62f1441d5413 VANDPS xmm2{k5}, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000000570 62b1440d5454db10 VANDPS xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000578 62b1440d5454dbf0 VANDPS xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000580 62f1448854d0 VANDPS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000586 62f144885413 VANDPS xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000058C 62f144985413 VANDPS xmm2, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000000592 62b144885454db10 VANDPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000059A 62b144885454dbf0 VANDPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000005A2 62f1448d54d0 VANDPS xmm2{k5}{z}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000005A8 62f1448d5413 VANDPS xmm2{k5}{z}, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000005AE 62f1449d5413 VANDPS xmm2{k5}{z}, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +00000000000005B4 62b1448d5454db10 VANDPS xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000005BC 62b1448d5454dbf0 VANDPS xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000005C4 62c1142854c7 VANDPS ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000005CA 62e114285403 VANDPS ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000005D0 62e114385403 VANDPS ymm16, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +00000000000005D6 62a114285444db08 VANDPS ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000005DE 62a114285444dbf8 VANDPS ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000005E6 62c1142d54c7 VANDPS ymm16{k5}, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000005EC 62e1142d5403 VANDPS ymm16{k5}, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000005F2 62e1143d5403 VANDPS ymm16{k5}, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +00000000000005F8 62a1142d5444db08 VANDPS ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000600 62a1142d5444dbf8 VANDPS ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000608 62c114a854c7 VANDPS ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000060E 62e114a85403 VANDPS ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000614 62e114b85403 VANDPS ymm16, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +000000000000061A 62a114a85444db08 VANDPS ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000622 62a114a85444dbf8 VANDPS ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000062A 62c114ad54c7 VANDPS ymm16{k5}{z}, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000630 62e114ad5403 VANDPS ymm16{k5}{z}, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000636 62e114bd5403 VANDPS ymm16{k5}{z}, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +000000000000063C 62a114ad5444db08 VANDPS ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000644 62a114ad5444dbf8 VANDPS ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000064C 62013c4054c7 VANDPS zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000652 62613c405403 VANDPS zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000658 62613c505403 VANDPS zmm24, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +000000000000065E 62213c405444db04 VANDPS zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000666 62213c405444dbfc VANDPS zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000066E 62013c4554c7 VANDPS zmm24{k5}, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000674 62613c455403 VANDPS zmm24{k5}, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000067A 62613c555403 VANDPS zmm24{k5}, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000000680 62213c455444db04 VANDPS zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000688 62213c455444dbfc VANDPS zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000690 62013cc054c7 VANDPS zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000696 62613cc05403 VANDPS zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000069C 62613cd05403 VANDPS zmm24, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +00000000000006A2 62213cc05444db04 VANDPS zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000006AA 62213cc05444dbfc VANDPS zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000006B2 62013cc554c7 VANDPS zmm24{k5}{z}, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000006B8 62613cc55403 VANDPS zmm24{k5}{z}, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000006BE 62613cd55403 VANDPS zmm24{k5}{z}, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +00000000000006C4 62213cc55444db04 VANDPS zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000006CC 62213cc55444dbfc VANDPS zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000006D4 62e27d2819c0 VBROADCASTF32X2 ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000006DA 62e27d281903 VBROADCASTF32X2 ymm16, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000006E0 62a27d281944db20 VBROADCASTF32X2 ymm16, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +00000000000006E8 62a27d281944dbe0 VBROADCASTF32X2 ymm16, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +00000000000006F0 62e27d2d19c0 VBROADCASTF32X2 ymm16{k5}, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000006F6 62e27d2d1903 VBROADCASTF32X2 ymm16{k5}, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000006FC 62a27d2d1944db20 VBROADCASTF32X2 ymm16{k5}, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000000704 62a27d2d1944dbe0 VBROADCASTF32X2 ymm16{k5}, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +000000000000070C 62e27da819c0 VBROADCASTF32X2 ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000712 62e27da81903 VBROADCASTF32X2 ymm16, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000718 62a27da81944db20 VBROADCASTF32X2 ymm16, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000000720 62a27da81944dbe0 VBROADCASTF32X2 ymm16, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +0000000000000728 62e27dad19c0 VBROADCASTF32X2 ymm16{k5}{z}, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000072E 62e27dad1903 VBROADCASTF32X2 ymm16{k5}{z}, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000734 62a27dad1944db20 VBROADCASTF32X2 ymm16{k5}{z}, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +000000000000073C 62a27dad1944dbe0 VBROADCASTF32X2 ymm16{k5}{z}, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +0000000000000744 62627d4819c0 VBROADCASTF32X2 zmm24, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000074A 62627d481903 VBROADCASTF32X2 zmm24, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000750 62227d481944db20 VBROADCASTF32X2 zmm24, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000000758 62227d481944dbe0 VBROADCASTF32X2 zmm24, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +0000000000000760 62627d4d19c0 VBROADCASTF32X2 zmm24{k5}, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000766 62627d4d1903 VBROADCASTF32X2 zmm24{k5}, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000076C 62227d4d1944db20 VBROADCASTF32X2 zmm24{k5}, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000000774 62227d4d1944dbe0 VBROADCASTF32X2 zmm24{k5}, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +000000000000077C 62627dc819c0 VBROADCASTF32X2 zmm24, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000782 62627dc81903 VBROADCASTF32X2 zmm24, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000788 62227dc81944db20 VBROADCASTF32X2 zmm24, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000000790 62227dc81944dbe0 VBROADCASTF32X2 zmm24, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +0000000000000798 62627dcd19c0 VBROADCASTF32X2 zmm24{k5}{z}, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000079E 62627dcd1903 VBROADCASTF32X2 zmm24{k5}{z}, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000007A4 62227dcd1944db20 VBROADCASTF32X2 zmm24{k5}{z}, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +00000000000007AC 62227dcd1944dbe0 VBROADCASTF32X2 zmm24{k5}{z}, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +00000000000007B4 62627d481b03 VBROADCASTF32X8 zmm24, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000007BA 62627d481b44f308 VBROADCASTF32X8 zmm24, ymmword ptr [rbx+rsi*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000008, + +00000000000007C2 62627d481b44f3f8 VBROADCASTF32X8 zmm24, ymmword ptr [rbx+rsi*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffff8, + +00000000000007CA 62627d4d1b03 VBROADCASTF32X8 zmm24{k5}, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000007D0 62627d4d1b44f308 VBROADCASTF32X8 zmm24{k5}, ymmword ptr [rbx+rsi*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000008, + +00000000000007D8 62627d4d1b44f3f8 VBROADCASTF32X8 zmm24{k5}, ymmword ptr [rbx+rsi*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffff8, + +00000000000007E0 62627dc81b03 VBROADCASTF32X8 zmm24, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000007E6 62627dc81b44f308 VBROADCASTF32X8 zmm24, ymmword ptr [rbx+rsi*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000008, + +00000000000007EE 62627dc81b44f3f8 VBROADCASTF32X8 zmm24, ymmword ptr [rbx+rsi*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffff8, + +00000000000007F6 62627dcd1b03 VBROADCASTF32X8 zmm24{k5}{z}, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000007FC 62627dcd1b44f308 VBROADCASTF32X8 zmm24{k5}{z}, ymmword ptr [rbx+rsi*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000008, + +0000000000000804 62627dcd1b44f3f8 VBROADCASTF32X8 zmm24{k5}{z}, ymmword ptr [rbx+rsi*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffff8, + +000000000000080C 62e2fd281a03 VBROADCASTF64X2 ymm16, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000812 62e2fd281a44f310 VBROADCASTF64X2 ymm16, xmmword ptr [rbx+rsi*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000010, + +000000000000081A 62e2fd281a44f3f0 VBROADCASTF64X2 ymm16, xmmword ptr [rbx+rsi*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000822 62e2fd2d1a03 VBROADCASTF64X2 ymm16{k5}, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000828 62e2fd2d1a44f310 VBROADCASTF64X2 ymm16{k5}, xmmword ptr [rbx+rsi*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000010, + +0000000000000830 62e2fd2d1a44f3f0 VBROADCASTF64X2 ymm16{k5}, xmmword ptr [rbx+rsi*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000838 62e2fda81a03 VBROADCASTF64X2 ymm16, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000083E 62e2fda81a44f310 VBROADCASTF64X2 ymm16, xmmword ptr [rbx+rsi*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000010, + +0000000000000846 62e2fda81a44f3f0 VBROADCASTF64X2 ymm16, xmmword ptr [rbx+rsi*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffff0, + +000000000000084E 62e2fdad1a03 VBROADCASTF64X2 ymm16{k5}{z}, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000854 62e2fdad1a44f310 VBROADCASTF64X2 ymm16{k5}{z}, xmmword ptr [rbx+rsi*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000010, + +000000000000085C 62e2fdad1a44f3f0 VBROADCASTF64X2 ymm16{k5}{z}, xmmword ptr [rbx+rsi*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000864 6262fd481a03 VBROADCASTF64X2 zmm24, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000086A 6262fd481a44f310 VBROADCASTF64X2 zmm24, xmmword ptr [rbx+rsi*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000010, + +0000000000000872 6262fd481a44f3f0 VBROADCASTF64X2 zmm24, xmmword ptr [rbx+rsi*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffff0, + +000000000000087A 6262fd4d1a03 VBROADCASTF64X2 zmm24{k5}, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000880 6262fd4d1a44f310 VBROADCASTF64X2 zmm24{k5}, xmmword ptr [rbx+rsi*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000010, + +0000000000000888 6262fd4d1a44f3f0 VBROADCASTF64X2 zmm24{k5}, xmmword ptr [rbx+rsi*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000890 6262fdc81a03 VBROADCASTF64X2 zmm24, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000896 6262fdc81a44f310 VBROADCASTF64X2 zmm24, xmmword ptr [rbx+rsi*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000010, + +000000000000089E 6262fdc81a44f3f0 VBROADCASTF64X2 zmm24, xmmword ptr [rbx+rsi*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffff0, + +00000000000008A6 6262fdcd1a03 VBROADCASTF64X2 zmm24{k5}{z}, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000008AC 6262fdcd1a44f310 VBROADCASTF64X2 zmm24{k5}{z}, xmmword ptr [rbx+rsi*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000010, + +00000000000008B4 6262fdcd1a44f3f0 VBROADCASTF64X2 zmm24{k5}{z}, xmmword ptr [rbx+rsi*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffff0, + +00000000000008BC 62f27d0859d0 VBROADCASTI32X2 xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000008C2 62f27d085913 VBROADCASTI32X2 xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000008C8 62b27d085954db20 VBROADCASTI32X2 xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +00000000000008D0 62b27d085954dbe0 VBROADCASTI32X2 xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +00000000000008D8 62f27d0d59d0 VBROADCASTI32X2 xmm2{k5}, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000008DE 62f27d0d5913 VBROADCASTI32X2 xmm2{k5}, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000008E4 62b27d0d5954db20 VBROADCASTI32X2 xmm2{k5}, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +00000000000008EC 62b27d0d5954dbe0 VBROADCASTI32X2 xmm2{k5}, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +00000000000008F4 62f27d8859d0 VBROADCASTI32X2 xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000008FA 62f27d885913 VBROADCASTI32X2 xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000900 62b27d885954db20 VBROADCASTI32X2 xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000000908 62b27d885954dbe0 VBROADCASTI32X2 xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +0000000000000910 62f27d8d59d0 VBROADCASTI32X2 xmm2{k5}{z}, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000916 62f27d8d5913 VBROADCASTI32X2 xmm2{k5}{z}, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000091C 62b27d8d5954db20 VBROADCASTI32X2 xmm2{k5}{z}, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000000924 62b27d8d5954dbe0 VBROADCASTI32X2 xmm2{k5}{z}, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +000000000000092C 62e27d2859c0 VBROADCASTI32X2 ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000932 62e27d285903 VBROADCASTI32X2 ymm16, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000938 62a27d285944db20 VBROADCASTI32X2 ymm16, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000000940 62a27d285944dbe0 VBROADCASTI32X2 ymm16, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +0000000000000948 62e27d2d59c0 VBROADCASTI32X2 ymm16{k5}, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000094E 62e27d2d5903 VBROADCASTI32X2 ymm16{k5}, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000954 62a27d2d5944db20 VBROADCASTI32X2 ymm16{k5}, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +000000000000095C 62a27d2d5944dbe0 VBROADCASTI32X2 ymm16{k5}, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +0000000000000964 62e27da859c0 VBROADCASTI32X2 ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000096A 62e27da85903 VBROADCASTI32X2 ymm16, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000970 62a27da85944db20 VBROADCASTI32X2 ymm16, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000000978 62a27da85944dbe0 VBROADCASTI32X2 ymm16, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +0000000000000980 62e27dad59c0 VBROADCASTI32X2 ymm16{k5}{z}, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000986 62e27dad5903 VBROADCASTI32X2 ymm16{k5}{z}, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000098C 62a27dad5944db20 VBROADCASTI32X2 ymm16{k5}{z}, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000000994 62a27dad5944dbe0 VBROADCASTI32X2 ymm16{k5}{z}, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +000000000000099C 62627d4859c0 VBROADCASTI32X2 zmm24, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000009A2 62627d485903 VBROADCASTI32X2 zmm24, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000009A8 62227d485944db20 VBROADCASTI32X2 zmm24, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +00000000000009B0 62227d485944dbe0 VBROADCASTI32X2 zmm24, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +00000000000009B8 62627d4d59c0 VBROADCASTI32X2 zmm24{k5}, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000009BE 62627d4d5903 VBROADCASTI32X2 zmm24{k5}, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000009C4 62227d4d5944db20 VBROADCASTI32X2 zmm24{k5}, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +00000000000009CC 62227d4d5944dbe0 VBROADCASTI32X2 zmm24{k5}, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +00000000000009D4 62627dc859c0 VBROADCASTI32X2 zmm24, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000009DA 62627dc85903 VBROADCASTI32X2 zmm24, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000009E0 62227dc85944db20 VBROADCASTI32X2 zmm24, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +00000000000009E8 62227dc85944dbe0 VBROADCASTI32X2 zmm24, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +00000000000009F0 62627dcd59c0 VBROADCASTI32X2 zmm24{k5}{z}, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000009F6 62627dcd5903 VBROADCASTI32X2 zmm24{k5}{z}, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000009FC 62227dcd5944db20 VBROADCASTI32X2 zmm24{k5}{z}, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000000A04 62227dcd5944dbe0 VBROADCASTI32X2 zmm24{k5}{z}, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +0000000000000A0C 62627d485b03 VBROADCASTI32X8 zmm24, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000A12 62627d485b44f308 VBROADCASTI32X8 zmm24, ymmword ptr [rbx+rsi*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000008, + +0000000000000A1A 62627d485b44f3f8 VBROADCASTI32X8 zmm24, ymmword ptr [rbx+rsi*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000A22 62627d4d5b03 VBROADCASTI32X8 zmm24{k5}, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000A28 62627d4d5b44f308 VBROADCASTI32X8 zmm24{k5}, ymmword ptr [rbx+rsi*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000008, + +0000000000000A30 62627d4d5b44f3f8 VBROADCASTI32X8 zmm24{k5}, ymmword ptr [rbx+rsi*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000A38 62627dc85b03 VBROADCASTI32X8 zmm24, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000A3E 62627dc85b44f308 VBROADCASTI32X8 zmm24, ymmword ptr [rbx+rsi*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000008, + +0000000000000A46 62627dc85b44f3f8 VBROADCASTI32X8 zmm24, ymmword ptr [rbx+rsi*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000A4E 62627dcd5b03 VBROADCASTI32X8 zmm24{k5}{z}, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000A54 62627dcd5b44f308 VBROADCASTI32X8 zmm24{k5}{z}, ymmword ptr [rbx+rsi*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000008, + +0000000000000A5C 62627dcd5b44f3f8 VBROADCASTI32X8 zmm24{k5}{z}, ymmword ptr [rbx+rsi*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000A64 62e2fd285a03 VBROADCASTI64X2 ymm16, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000A6A 62e2fd285a44f310 VBROADCASTI64X2 ymm16, xmmword ptr [rbx+rsi*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000010, + +0000000000000A72 62e2fd285a44f3f0 VBROADCASTI64X2 ymm16, xmmword ptr [rbx+rsi*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000A7A 62e2fd2d5a03 VBROADCASTI64X2 ymm16{k5}, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000A80 62e2fd2d5a44f310 VBROADCASTI64X2 ymm16{k5}, xmmword ptr [rbx+rsi*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000010, + +0000000000000A88 62e2fd2d5a44f3f0 VBROADCASTI64X2 ymm16{k5}, xmmword ptr [rbx+rsi*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000A90 62e2fda85a03 VBROADCASTI64X2 ymm16, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000A96 62e2fda85a44f310 VBROADCASTI64X2 ymm16, xmmword ptr [rbx+rsi*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000010, + +0000000000000A9E 62e2fda85a44f3f0 VBROADCASTI64X2 ymm16, xmmword ptr [rbx+rsi*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000AA6 62e2fdad5a03 VBROADCASTI64X2 ymm16{k5}{z}, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000AAC 62e2fdad5a44f310 VBROADCASTI64X2 ymm16{k5}{z}, xmmword ptr [rbx+rsi*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000010, + +0000000000000AB4 62e2fdad5a44f3f0 VBROADCASTI64X2 ymm16{k5}{z}, xmmword ptr [rbx+rsi*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000ABC 6262fd485a03 VBROADCASTI64X2 zmm24, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000AC2 6262fd485a44f310 VBROADCASTI64X2 zmm24, xmmword ptr [rbx+rsi*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000010, + +0000000000000ACA 6262fd485a44f3f0 VBROADCASTI64X2 zmm24, xmmword ptr [rbx+rsi*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000AD2 6262fd4d5a03 VBROADCASTI64X2 zmm24{k5}, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000AD8 6262fd4d5a44f310 VBROADCASTI64X2 zmm24{k5}, xmmword ptr [rbx+rsi*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000010, + +0000000000000AE0 6262fd4d5a44f3f0 VBROADCASTI64X2 zmm24{k5}, xmmword ptr [rbx+rsi*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000AE8 6262fdc85a03 VBROADCASTI64X2 zmm24, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000AEE 6262fdc85a44f310 VBROADCASTI64X2 zmm24, xmmword ptr [rbx+rsi*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000010, + +0000000000000AF6 6262fdc85a44f3f0 VBROADCASTI64X2 zmm24, xmmword ptr [rbx+rsi*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000AFE 6262fdcd5a03 VBROADCASTI64X2 zmm24{k5}{z}, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000B04 6262fdcd5a44f310 VBROADCASTI64X2 zmm24{k5}{z}, xmmword ptr [rbx+rsi*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000010, + +0000000000000B0C 6262fdcd5a44f3f0 VBROADCASTI64X2 zmm24{k5}{z}, xmmword ptr [rbx+rsi*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: BROADCAST, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000B14 62f1fd087bd0 VCVTPD2QQ xmm2, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000B1A 62f1fd087b13 VCVTPD2QQ xmm2, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000B20 62f1fd187b13 VCVTPD2QQ xmm2, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000000B26 62b1fd087b54db10 VCVTPD2QQ xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000B2E 62b1fd087b54dbf0 VCVTPD2QQ xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000B36 62f1fd0d7bd0 VCVTPD2QQ xmm2{k5}, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000B3C 62f1fd0d7b13 VCVTPD2QQ xmm2{k5}, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000B42 62f1fd1d7b13 VCVTPD2QQ xmm2{k5}, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000000B48 62b1fd0d7b54db10 VCVTPD2QQ xmm2{k5}, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000B50 62b1fd0d7b54dbf0 VCVTPD2QQ xmm2{k5}, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000B58 62f1fd887bd0 VCVTPD2QQ xmm2, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000B5E 62f1fd887b13 VCVTPD2QQ xmm2, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000B64 62f1fd987b13 VCVTPD2QQ xmm2, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000000B6A 62b1fd887b54db10 VCVTPD2QQ xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000B72 62b1fd887b54dbf0 VCVTPD2QQ xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000B7A 62f1fd8d7bd0 VCVTPD2QQ xmm2{k5}{z}, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000B80 62f1fd8d7b13 VCVTPD2QQ xmm2{k5}{z}, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000B86 62f1fd9d7b13 VCVTPD2QQ xmm2{k5}{z}, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000000B8C 62b1fd8d7b54db10 VCVTPD2QQ xmm2{k5}{z}, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000B94 62b1fd8d7b54dbf0 VCVTPD2QQ xmm2{k5}{z}, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000B9C 62c1fd287bc7 VCVTPD2QQ ymm16, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000BA2 62e1fd287b03 VCVTPD2QQ ymm16, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000BA8 62e1fd387b03 VCVTPD2QQ ymm16, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000000BAE 62a1fd287b44db08 VCVTPD2QQ ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000BB6 62a1fd287b44dbf8 VCVTPD2QQ ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000BBE 62c1fd2d7bc7 VCVTPD2QQ ymm16{k5}, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000BC4 62e1fd2d7b03 VCVTPD2QQ ymm16{k5}, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000BCA 62e1fd3d7b03 VCVTPD2QQ ymm16{k5}, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000000BD0 62a1fd2d7b44db08 VCVTPD2QQ ymm16{k5}, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000BD8 62a1fd2d7b44dbf8 VCVTPD2QQ ymm16{k5}, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000BE0 62c1fda87bc7 VCVTPD2QQ ymm16, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000BE6 62e1fda87b03 VCVTPD2QQ ymm16, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000BEC 62e1fdb87b03 VCVTPD2QQ ymm16, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000000BF2 62a1fda87b44db08 VCVTPD2QQ ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000BFA 62a1fda87b44dbf8 VCVTPD2QQ ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000C02 62c1fdad7bc7 VCVTPD2QQ ymm16{k5}{z}, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000C08 62e1fdad7b03 VCVTPD2QQ ymm16{k5}{z}, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000C0E 62e1fdbd7b03 VCVTPD2QQ ymm16{k5}{z}, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000000C14 62a1fdad7b44db08 VCVTPD2QQ ymm16{k5}{z}, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000C1C 62a1fdad7b44dbf8 VCVTPD2QQ ymm16{k5}{z}, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000C24 6201fd487bc7 VCVTPD2QQ zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000C2A 6201fd387bc7 VCVTPD2QQ zmm24, zmm31, {rd-sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000C30 6261fd487b03 VCVTPD2QQ zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000C36 6261fd587b03 VCVTPD2QQ zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000000C3C 6221fd487b44db04 VCVTPD2QQ zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000C44 6221fd487b44dbfc VCVTPD2QQ zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000C4C 6201fd4d7bc7 VCVTPD2QQ zmm24{k5}, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000C52 6201fd3d7bc7 VCVTPD2QQ zmm24{k5}, zmm31, {rd-sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000C58 6261fd4d7b03 VCVTPD2QQ zmm24{k5}, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000C5E 6261fd5d7b03 VCVTPD2QQ zmm24{k5}, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000000C64 6221fd4d7b44db04 VCVTPD2QQ zmm24{k5}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000C6C 6221fd4d7b44dbfc VCVTPD2QQ zmm24{k5}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000C74 6201fdc87bc7 VCVTPD2QQ zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000C7A 6201fdb87bc7 VCVTPD2QQ zmm24, zmm31, {rd-sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000C80 6261fdc87b03 VCVTPD2QQ zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000C86 6261fdd87b03 VCVTPD2QQ zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000000C8C 6221fdc87b44db04 VCVTPD2QQ zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000C94 6221fdc87b44dbfc VCVTPD2QQ zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000C9C 6201fdcd7bc7 VCVTPD2QQ zmm24{k5}{z}, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000CA2 6201fdbd7bc7 VCVTPD2QQ zmm24{k5}{z}, zmm31, {rd-sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000CA8 6261fdcd7b03 VCVTPD2QQ zmm24{k5}{z}, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000CAE 6261fddd7b03 VCVTPD2QQ zmm24{k5}{z}, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000000CB4 6221fdcd7b44db04 VCVTPD2QQ zmm24{k5}{z}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000CBC 6221fdcd7b44dbfc VCVTPD2QQ zmm24{k5}{z}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000CC4 62f1fd0879d0 VCVTPD2UQQ xmm2, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000CCA 62f1fd087913 VCVTPD2UQQ xmm2, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000CD0 62f1fd187913 VCVTPD2UQQ xmm2, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000000CD6 62b1fd087954db10 VCVTPD2UQQ xmm2, xmmword ptr [rbx+r11*8+0x80] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000CDE 62b1fd087954dbf0 VCVTPD2UQQ xmm2, xmmword ptr [rbx+r11*8-0x80] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000CE6 62f1fd0d79d0 VCVTPD2UQQ xmm2{k5}, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000CEC 62f1fd0d7913 VCVTPD2UQQ xmm2{k5}, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000CF2 62f1fd1d7913 VCVTPD2UQQ xmm2{k5}, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000000CF8 62b1fd0d7954db10 VCVTPD2UQQ xmm2{k5}, xmmword ptr [rbx+r11*8+0x80] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000D00 62b1fd0d7954dbf0 VCVTPD2UQQ xmm2{k5}, xmmword ptr [rbx+r11*8-0x80] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000D08 62f1fd8879d0 VCVTPD2UQQ xmm2, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000D0E 62f1fd887913 VCVTPD2UQQ xmm2, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000D14 62f1fd987913 VCVTPD2UQQ xmm2, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000000D1A 62b1fd887954db10 VCVTPD2UQQ xmm2, xmmword ptr [rbx+r11*8+0x80] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000D22 62b1fd887954dbf0 VCVTPD2UQQ xmm2, xmmword ptr [rbx+r11*8-0x80] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000D2A 62f1fd8d79d0 VCVTPD2UQQ xmm2{k5}{z}, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000D30 62f1fd8d7913 VCVTPD2UQQ xmm2{k5}{z}, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000D36 62f1fd9d7913 VCVTPD2UQQ xmm2{k5}{z}, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000000D3C 62b1fd8d7954db10 VCVTPD2UQQ xmm2{k5}{z}, xmmword ptr [rbx+r11*8+0x80] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000D44 62b1fd8d7954dbf0 VCVTPD2UQQ xmm2{k5}{z}, xmmword ptr [rbx+r11*8-0x80] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000D4C 62c1fd2879c7 VCVTPD2UQQ ymm16, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000D52 62e1fd287903 VCVTPD2UQQ ymm16, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000D58 62e1fd387903 VCVTPD2UQQ ymm16, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000000D5E 62a1fd287944db08 VCVTPD2UQQ ymm16, ymmword ptr [rbx+r11*8+0x80] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000D66 62a1fd287944dbf8 VCVTPD2UQQ ymm16, ymmword ptr [rbx+r11*8-0x80] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000D6E 62c1fd2d79c7 VCVTPD2UQQ ymm16{k5}, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000D74 62e1fd2d7903 VCVTPD2UQQ ymm16{k5}, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000D7A 62e1fd3d7903 VCVTPD2UQQ ymm16{k5}, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000000D80 62a1fd2d7944db08 VCVTPD2UQQ ymm16{k5}, ymmword ptr [rbx+r11*8+0x80] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000D88 62a1fd2d7944dbf8 VCVTPD2UQQ ymm16{k5}, ymmword ptr [rbx+r11*8-0x80] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000D90 62c1fda879c7 VCVTPD2UQQ ymm16, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000D96 62e1fda87903 VCVTPD2UQQ ymm16, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000D9C 62e1fdb87903 VCVTPD2UQQ ymm16, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000000DA2 62a1fda87944db08 VCVTPD2UQQ ymm16, ymmword ptr [rbx+r11*8+0x80] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000DAA 62a1fda87944dbf8 VCVTPD2UQQ ymm16, ymmword ptr [rbx+r11*8-0x80] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000DB2 62c1fdad79c7 VCVTPD2UQQ ymm16{k5}{z}, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000DB8 62e1fdad7903 VCVTPD2UQQ ymm16{k5}{z}, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000DBE 62e1fdbd7903 VCVTPD2UQQ ymm16{k5}{z}, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000000DC4 62a1fdad7944db08 VCVTPD2UQQ ymm16{k5}{z}, ymmword ptr [rbx+r11*8+0x80] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000DCC 62a1fdad7944dbf8 VCVTPD2UQQ ymm16{k5}{z}, ymmword ptr [rbx+r11*8-0x80] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000DD4 6201fd4879c7 VCVTPD2UQQ zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000DDA 6201fd3879c7 VCVTPD2UQQ zmm24, zmm31, {rd-sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000DE0 6261fd487903 VCVTPD2UQQ zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000DE6 6261fd587903 VCVTPD2UQQ zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000000DEC 6221fd487944db04 VCVTPD2UQQ zmm24, zmmword ptr [rbx+r11*8+0x80] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000DF4 6221fd487944dbfc VCVTPD2UQQ zmm24, zmmword ptr [rbx+r11*8-0x80] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000DFC 6201fd4d79c7 VCVTPD2UQQ zmm24{k5}, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000E02 6201fd3d79c7 VCVTPD2UQQ zmm24{k5}, zmm31, {rd-sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000E08 6261fd4d7903 VCVTPD2UQQ zmm24{k5}, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000E0E 6261fd5d7903 VCVTPD2UQQ zmm24{k5}, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000000E14 6221fd4d7944db04 VCVTPD2UQQ zmm24{k5}, zmmword ptr [rbx+r11*8+0x80] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000E1C 6221fd4d7944dbfc VCVTPD2UQQ zmm24{k5}, zmmword ptr [rbx+r11*8-0x80] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000E24 6201fdc879c7 VCVTPD2UQQ zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000E2A 6201fdb879c7 VCVTPD2UQQ zmm24, zmm31, {rd-sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000E30 6261fdc87903 VCVTPD2UQQ zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000E36 6261fdd87903 VCVTPD2UQQ zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000000E3C 6221fdc87944db04 VCVTPD2UQQ zmm24, zmmword ptr [rbx+r11*8+0x80] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000E44 6221fdc87944dbfc VCVTPD2UQQ zmm24, zmmword ptr [rbx+r11*8-0x80] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000E4C 6201fdcd79c7 VCVTPD2UQQ zmm24{k5}{z}, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000E52 6201fdbd79c7 VCVTPD2UQQ zmm24{k5}{z}, zmm31, {rd-sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000E58 6261fdcd7903 VCVTPD2UQQ zmm24{k5}{z}, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000E5E 6261fddd7903 VCVTPD2UQQ zmm24{k5}{z}, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000000E64 6221fdcd7944db04 VCVTPD2UQQ zmm24{k5}{z}, zmmword ptr [rbx+r11*8+0x80] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000E6C 6221fdcd7944dbfc VCVTPD2UQQ zmm24{k5}{z}, zmmword ptr [rbx+r11*8-0x80] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000E74 62f17d087bd0 VCVTPS2QQ xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000E7A 62f17d087b13 VCVTPS2QQ xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000E80 62f17d187b13 VCVTPS2QQ xmm2, dword ptr [rbx]{1to2} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 2 times + +0000000000000E86 62b17d087b54db20 VCVTPS2QQ xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000000E8E 62b17d087b54dbe0 VCVTPS2QQ xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +0000000000000E96 62f17d0d7bd0 VCVTPS2QQ xmm2{k5}, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000E9C 62f17d0d7b13 VCVTPS2QQ xmm2{k5}, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000EA2 62f17d1d7b13 VCVTPS2QQ xmm2{k5}, dword ptr [rbx]{1to2} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 2 times + +0000000000000EA8 62b17d0d7b54db20 VCVTPS2QQ xmm2{k5}, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000000EB0 62b17d0d7b54dbe0 VCVTPS2QQ xmm2{k5}, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +0000000000000EB8 62f17d887bd0 VCVTPS2QQ xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000EBE 62f17d887b13 VCVTPS2QQ xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000EC4 62f17d987b13 VCVTPS2QQ xmm2, dword ptr [rbx]{1to2} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 2 times + +0000000000000ECA 62b17d887b54db20 VCVTPS2QQ xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000000ED2 62b17d887b54dbe0 VCVTPS2QQ xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +0000000000000EDA 62f17d8d7bd0 VCVTPS2QQ xmm2{k5}{z}, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000EE0 62f17d8d7b13 VCVTPS2QQ xmm2{k5}{z}, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000EE6 62f17d9d7b13 VCVTPS2QQ xmm2{k5}{z}, dword ptr [rbx]{1to2} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 2 times + +0000000000000EEC 62b17d8d7b54db20 VCVTPS2QQ xmm2{k5}{z}, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000000EF4 62b17d8d7b54dbe0 VCVTPS2QQ xmm2{k5}{z}, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +0000000000000EFC 62e17d287bc0 VCVTPS2QQ ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000F02 62e17d287b03 VCVTPS2QQ ymm16, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000F08 62e17d387b03 VCVTPS2QQ ymm16, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000000F0E 62a17d287b44db10 VCVTPS2QQ ymm16, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000F16 62a17d287b44dbf0 VCVTPS2QQ ymm16, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000F1E 62e17d2d7bc0 VCVTPS2QQ ymm16{k5}, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000F24 62e17d2d7b03 VCVTPS2QQ ymm16{k5}, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000F2A 62e17d3d7b03 VCVTPS2QQ ymm16{k5}, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000000F30 62a17d2d7b44db10 VCVTPS2QQ ymm16{k5}, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000F38 62a17d2d7b44dbf0 VCVTPS2QQ ymm16{k5}, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000F40 62e17da87bc0 VCVTPS2QQ ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000F46 62e17da87b03 VCVTPS2QQ ymm16, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000F4C 62e17db87b03 VCVTPS2QQ ymm16, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000000F52 62a17da87b44db10 VCVTPS2QQ ymm16, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000F5A 62a17da87b44dbf0 VCVTPS2QQ ymm16, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000F62 62e17dad7bc0 VCVTPS2QQ ymm16{k5}{z}, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000F68 62e17dad7b03 VCVTPS2QQ ymm16{k5}{z}, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000F6E 62e17dbd7b03 VCVTPS2QQ ymm16{k5}{z}, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000000F74 62a17dad7b44db10 VCVTPS2QQ ymm16{k5}{z}, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000F7C 62a17dad7b44dbf0 VCVTPS2QQ ymm16{k5}{z}, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000F84 62417d487bc7 VCVTPS2QQ zmm24, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000F8A 62417d387bc7 VCVTPS2QQ zmm24, ymm15, {rd-sae} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000F90 62617d487b03 VCVTPS2QQ zmm24, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000F96 62617d587b03 VCVTPS2QQ zmm24, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +0000000000000F9C 62217d487b44db08 VCVTPS2QQ zmm24, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000FA4 62217d487b44dbf8 VCVTPS2QQ zmm24, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000FAC 62417d4d7bc7 VCVTPS2QQ zmm24{k5}, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000FB2 62417d3d7bc7 VCVTPS2QQ zmm24{k5}, ymm15, {rd-sae} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000FB8 62617d4d7b03 VCVTPS2QQ zmm24{k5}, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000FBE 62617d5d7b03 VCVTPS2QQ zmm24{k5}, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +0000000000000FC4 62217d4d7b44db08 VCVTPS2QQ zmm24{k5}, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000FCC 62217d4d7b44dbf8 VCVTPS2QQ zmm24{k5}, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000FD4 62417dc87bc7 VCVTPS2QQ zmm24, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000FDA 62417db87bc7 VCVTPS2QQ zmm24, ymm15, {rd-sae} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000FE0 62617dc87b03 VCVTPS2QQ zmm24, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000FE6 62617dd87b03 VCVTPS2QQ zmm24, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +0000000000000FEC 62217dc87b44db08 VCVTPS2QQ zmm24, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000FF4 62217dc87b44dbf8 VCVTPS2QQ zmm24, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000FFC 62417dcd7bc7 VCVTPS2QQ zmm24{k5}{z}, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001002 62417dbd7bc7 VCVTPS2QQ zmm24{k5}{z}, ymm15, {rd-sae} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001008 62617dcd7b03 VCVTPS2QQ zmm24{k5}{z}, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000100E 62617ddd7b03 VCVTPS2QQ zmm24{k5}{z}, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +0000000000001014 62217dcd7b44db08 VCVTPS2QQ zmm24{k5}{z}, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000101C 62217dcd7b44dbf8 VCVTPS2QQ zmm24{k5}{z}, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001024 62f17d0879d0 VCVTPS2UQQ xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000102A 62f17d087913 VCVTPS2UQQ xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000001030 62f17d187913 VCVTPS2UQQ xmm2, dword ptr [rbx]{1to2} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 2 times + +0000000000001036 62b17d087954db20 VCVTPS2UQQ xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +000000000000103E 62b17d087954dbe0 VCVTPS2UQQ xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +0000000000001046 62f17d0d79d0 VCVTPS2UQQ xmm2{k5}, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000104C 62f17d0d7913 VCVTPS2UQQ xmm2{k5}, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000001052 62f17d1d7913 VCVTPS2UQQ xmm2{k5}, dword ptr [rbx]{1to2} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 2 times + +0000000000001058 62b17d0d7954db20 VCVTPS2UQQ xmm2{k5}, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000001060 62b17d0d7954dbe0 VCVTPS2UQQ xmm2{k5}, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +0000000000001068 62f17d8879d0 VCVTPS2UQQ xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000106E 62f17d887913 VCVTPS2UQQ xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000001074 62f17d987913 VCVTPS2UQQ xmm2, dword ptr [rbx]{1to2} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 2 times + +000000000000107A 62b17d887954db20 VCVTPS2UQQ xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000001082 62b17d887954dbe0 VCVTPS2UQQ xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +000000000000108A 62f17d8d79d0 VCVTPS2UQQ xmm2{k5}{z}, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001090 62f17d8d7913 VCVTPS2UQQ xmm2{k5}{z}, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000001096 62f17d9d7913 VCVTPS2UQQ xmm2{k5}{z}, dword ptr [rbx]{1to2} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 2 times + +000000000000109C 62b17d8d7954db20 VCVTPS2UQQ xmm2{k5}{z}, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +00000000000010A4 62b17d8d7954dbe0 VCVTPS2UQQ xmm2{k5}{z}, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +00000000000010AC 62e17d2879c0 VCVTPS2UQQ ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000010B2 62e17d287903 VCVTPS2UQQ ymm16, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000010B8 62e17d387903 VCVTPS2UQQ ymm16, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +00000000000010BE 62a17d287944db10 VCVTPS2UQQ ymm16, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000010C6 62a17d287944dbf0 VCVTPS2UQQ ymm16, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000010CE 62e17d2d79c0 VCVTPS2UQQ ymm16{k5}, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000010D4 62e17d2d7903 VCVTPS2UQQ ymm16{k5}, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000010DA 62e17d3d7903 VCVTPS2UQQ ymm16{k5}, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +00000000000010E0 62a17d2d7944db10 VCVTPS2UQQ ymm16{k5}, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000010E8 62a17d2d7944dbf0 VCVTPS2UQQ ymm16{k5}, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000010F0 62e17da879c0 VCVTPS2UQQ ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000010F6 62e17da87903 VCVTPS2UQQ ymm16, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000010FC 62e17db87903 VCVTPS2UQQ ymm16, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000001102 62a17da87944db10 VCVTPS2UQQ ymm16, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000110A 62a17da87944dbf0 VCVTPS2UQQ ymm16, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000001112 62e17dad79c0 VCVTPS2UQQ ymm16{k5}{z}, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001118 62e17dad7903 VCVTPS2UQQ ymm16{k5}{z}, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000111E 62e17dbd7903 VCVTPS2UQQ ymm16{k5}{z}, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000001124 62a17dad7944db10 VCVTPS2UQQ ymm16{k5}{z}, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000112C 62a17dad7944dbf0 VCVTPS2UQQ ymm16{k5}{z}, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000001134 62417d4879c7 VCVTPS2UQQ zmm24, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000113A 62417d3879c7 VCVTPS2UQQ zmm24, ymm15, {rd-sae} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001140 62617d487903 VCVTPS2UQQ zmm24, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000001146 62617d587903 VCVTPS2UQQ zmm24, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +000000000000114C 62217d487944db08 VCVTPS2UQQ zmm24, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001154 62217d487944dbf8 VCVTPS2UQQ zmm24, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000115C 62417d4d79c7 VCVTPS2UQQ zmm24{k5}, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001162 62417d3d79c7 VCVTPS2UQQ zmm24{k5}, ymm15, {rd-sae} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001168 62617d4d7903 VCVTPS2UQQ zmm24{k5}, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000116E 62617d5d7903 VCVTPS2UQQ zmm24{k5}, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +0000000000001174 62217d4d7944db08 VCVTPS2UQQ zmm24{k5}, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000117C 62217d4d7944dbf8 VCVTPS2UQQ zmm24{k5}, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001184 62417dc879c7 VCVTPS2UQQ zmm24, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000118A 62417db879c7 VCVTPS2UQQ zmm24, ymm15, {rd-sae} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001190 62617dc87903 VCVTPS2UQQ zmm24, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000001196 62617dd87903 VCVTPS2UQQ zmm24, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +000000000000119C 62217dc87944db08 VCVTPS2UQQ zmm24, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000011A4 62217dc87944dbf8 VCVTPS2UQQ zmm24, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000011AC 62417dcd79c7 VCVTPS2UQQ zmm24{k5}{z}, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000011B2 62417dbd79c7 VCVTPS2UQQ zmm24{k5}{z}, ymm15, {rd-sae} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000011B8 62617dcd7903 VCVTPS2UQQ zmm24{k5}{z}, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000011BE 62617ddd7903 VCVTPS2UQQ zmm24{k5}{z}, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +00000000000011C4 62217dcd7944db08 VCVTPS2UQQ zmm24{k5}{z}, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000011CC 62217dcd7944dbf8 VCVTPS2UQQ zmm24{k5}{z}, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000011D4 62f1fe08e6d0 VCVTQQ2PD xmm2, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000011DA 62f1fe08e613 VCVTQQ2PD xmm2, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000011E0 62f1fe18e613 VCVTQQ2PD xmm2, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +00000000000011E6 62b1fe08e654db10 VCVTQQ2PD xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000011EE 62b1fe08e654dbf0 VCVTQQ2PD xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000011F6 62f1fe0de6d0 VCVTQQ2PD xmm2{k5}, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000011FC 62f1fe0de613 VCVTQQ2PD xmm2{k5}, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001202 62f1fe1de613 VCVTQQ2PD xmm2{k5}, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000001208 62b1fe0de654db10 VCVTQQ2PD xmm2{k5}, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000001210 62b1fe0de654dbf0 VCVTQQ2PD xmm2{k5}, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000001218 62f1fe88e6d0 VCVTQQ2PD xmm2, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000121E 62f1fe88e613 VCVTQQ2PD xmm2, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001224 62f1fe98e613 VCVTQQ2PD xmm2, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +000000000000122A 62b1fe88e654db10 VCVTQQ2PD xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000001232 62b1fe88e654dbf0 VCVTQQ2PD xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000123A 62f1fe8de6d0 VCVTQQ2PD xmm2{k5}{z}, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001240 62f1fe8de613 VCVTQQ2PD xmm2{k5}{z}, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001246 62f1fe9de613 VCVTQQ2PD xmm2{k5}{z}, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +000000000000124C 62b1fe8de654db10 VCVTQQ2PD xmm2{k5}{z}, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000001254 62b1fe8de654dbf0 VCVTQQ2PD xmm2{k5}{z}, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000125C 62c1fe28e6c7 VCVTQQ2PD ymm16, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001262 62e1fe28e603 VCVTQQ2PD ymm16, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000001268 62e1fe38e603 VCVTQQ2PD ymm16, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +000000000000126E 62a1fe28e644db08 VCVTQQ2PD ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001276 62a1fe28e644dbf8 VCVTQQ2PD ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000127E 62c1fe2de6c7 VCVTQQ2PD ymm16{k5}, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001284 62e1fe2de603 VCVTQQ2PD ymm16{k5}, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000128A 62e1fe3de603 VCVTQQ2PD ymm16{k5}, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000001290 62a1fe2de644db08 VCVTQQ2PD ymm16{k5}, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001298 62a1fe2de644dbf8 VCVTQQ2PD ymm16{k5}, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000012A0 62c1fea8e6c7 VCVTQQ2PD ymm16, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000012A6 62e1fea8e603 VCVTQQ2PD ymm16, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000012AC 62e1feb8e603 VCVTQQ2PD ymm16, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +00000000000012B2 62a1fea8e644db08 VCVTQQ2PD ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000012BA 62a1fea8e644dbf8 VCVTQQ2PD ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000012C2 62c1feade6c7 VCVTQQ2PD ymm16{k5}{z}, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000012C8 62e1feade603 VCVTQQ2PD ymm16{k5}{z}, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000012CE 62e1febde603 VCVTQQ2PD ymm16{k5}{z}, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +00000000000012D4 62a1feade644db08 VCVTQQ2PD ymm16{k5}{z}, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000012DC 62a1feade644dbf8 VCVTQQ2PD ymm16{k5}{z}, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000012E4 6201fe48e6c7 VCVTQQ2PD zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000012EA 6201fe38e6c7 VCVTQQ2PD zmm24, zmm31, {rd-sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000012F0 6261fe48e603 VCVTQQ2PD zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000012F6 6261fe58e603 VCVTQQ2PD zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +00000000000012FC 6221fe48e644db04 VCVTQQ2PD zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001304 6221fe48e644dbfc VCVTQQ2PD zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000130C 6201fe4de6c7 VCVTQQ2PD zmm24{k5}, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001312 6201fe3de6c7 VCVTQQ2PD zmm24{k5}, zmm31, {rd-sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001318 6261fe4de603 VCVTQQ2PD zmm24{k5}, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000131E 6261fe5de603 VCVTQQ2PD zmm24{k5}, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000001324 6221fe4de644db04 VCVTQQ2PD zmm24{k5}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000132C 6221fe4de644dbfc VCVTQQ2PD zmm24{k5}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001334 6201fec8e6c7 VCVTQQ2PD zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000133A 6201feb8e6c7 VCVTQQ2PD zmm24, zmm31, {rd-sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001340 6261fec8e603 VCVTQQ2PD zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001346 6261fed8e603 VCVTQQ2PD zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +000000000000134C 6221fec8e644db04 VCVTQQ2PD zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001354 6221fec8e644dbfc VCVTQQ2PD zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000135C 6201fecde6c7 VCVTQQ2PD zmm24{k5}{z}, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001362 6201febde6c7 VCVTQQ2PD zmm24{k5}{z}, zmm31, {rd-sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001368 6261fecde603 VCVTQQ2PD zmm24{k5}{z}, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000136E 6261fedde603 VCVTQQ2PD zmm24{k5}{z}, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000001374 6221fecde644db04 VCVTQQ2PD zmm24{k5}{z}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000137C 6221fecde644dbfc VCVTQQ2PD zmm24{k5}{z}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001384 62f1fc085bd0 VCVTQQ2PS xmm2, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000138A 62d1fc285bd7 VCVTQQ2PS xmm2, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001390 62f1fc185b13 VCVTQQ2PS xmm2, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000001396 62f1fc385b13 VCVTQQ2PS xmm2, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +000000000000139C 62f1fc0d5bd0 VCVTQQ2PS xmm2{k5}, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000013A2 62d1fc2d5bd7 VCVTQQ2PS xmm2{k5}, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000013A8 62f1fc1d5b13 VCVTQQ2PS xmm2{k5}, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +00000000000013AE 62f1fc3d5b13 VCVTQQ2PS xmm2{k5}, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +00000000000013B4 62f1fc885bd0 VCVTQQ2PS xmm2, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000013BA 62d1fca85bd7 VCVTQQ2PS xmm2, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000013C0 62f1fc985b13 VCVTQQ2PS xmm2, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +00000000000013C6 62f1fcb85b13 VCVTQQ2PS xmm2, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +00000000000013CC 62f1fc8d5bd0 VCVTQQ2PS xmm2{k5}{z}, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000013D2 62d1fcad5bd7 VCVTQQ2PS xmm2{k5}{z}, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000013D8 62f1fc9d5b13 VCVTQQ2PS xmm2{k5}{z}, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +00000000000013DE 62f1fcbd5b13 VCVTQQ2PS xmm2{k5}{z}, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +00000000000013E4 6281fc485bc7 VCVTQQ2PS ymm16, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000013EA 6281fc385bc7 VCVTQQ2PS ymm16, zmm31, {rd-sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000013F0 62e1fc485b03 VCVTQQ2PS ymm16, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000013F6 62e1fc585b03 VCVTQQ2PS ymm16, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +00000000000013FC 62a1fc485b44db04 VCVTQQ2PS ymm16, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001404 62a1fc485b44dbfc VCVTQQ2PS ymm16, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000140C 6281fc4d5bc7 VCVTQQ2PS ymm16{k5}, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001412 6281fc3d5bc7 VCVTQQ2PS ymm16{k5}, zmm31, {rd-sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001418 62e1fc4d5b03 VCVTQQ2PS ymm16{k5}, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000141E 62e1fc5d5b03 VCVTQQ2PS ymm16{k5}, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000001424 62a1fc4d5b44db04 VCVTQQ2PS ymm16{k5}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000142C 62a1fc4d5b44dbfc VCVTQQ2PS ymm16{k5}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001434 6281fcc85bc7 VCVTQQ2PS ymm16, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000143A 6281fcb85bc7 VCVTQQ2PS ymm16, zmm31, {rd-sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001440 62e1fcc85b03 VCVTQQ2PS ymm16, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001446 62e1fcd85b03 VCVTQQ2PS ymm16, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +000000000000144C 62a1fcc85b44db04 VCVTQQ2PS ymm16, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001454 62a1fcc85b44dbfc VCVTQQ2PS ymm16, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000145C 6281fccd5bc7 VCVTQQ2PS ymm16{k5}{z}, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001462 6281fcbd5bc7 VCVTQQ2PS ymm16{k5}{z}, zmm31, {rd-sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001468 62e1fccd5b03 VCVTQQ2PS ymm16{k5}{z}, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000146E 62e1fcdd5b03 VCVTQQ2PS ymm16{k5}{z}, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000001474 62a1fccd5b44db04 VCVTQQ2PS ymm16{k5}{z}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000147C 62a1fccd5b44dbfc VCVTQQ2PS ymm16{k5}{z}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001484 62f1fd087ad0 VCVTTPD2QQ xmm2, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000148A 62f1fd087a13 VCVTTPD2QQ xmm2, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001490 62f1fd187a13 VCVTTPD2QQ xmm2, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000001496 62b1fd087a54db10 VCVTTPD2QQ xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000149E 62b1fd087a54dbf0 VCVTTPD2QQ xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000014A6 62f1fd0d7ad0 VCVTTPD2QQ xmm2{k5}, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000014AC 62f1fd0d7a13 VCVTTPD2QQ xmm2{k5}, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000014B2 62f1fd1d7a13 VCVTTPD2QQ xmm2{k5}, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +00000000000014B8 62b1fd0d7a54db10 VCVTTPD2QQ xmm2{k5}, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000014C0 62b1fd0d7a54dbf0 VCVTTPD2QQ xmm2{k5}, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000014C8 62f1fd887ad0 VCVTTPD2QQ xmm2, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000014CE 62f1fd887a13 VCVTTPD2QQ xmm2, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000014D4 62f1fd987a13 VCVTTPD2QQ xmm2, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +00000000000014DA 62b1fd887a54db10 VCVTTPD2QQ xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000014E2 62b1fd887a54dbf0 VCVTTPD2QQ xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000014EA 62f1fd8d7ad0 VCVTTPD2QQ xmm2{k5}{z}, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000014F0 62f1fd8d7a13 VCVTTPD2QQ xmm2{k5}{z}, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000014F6 62f1fd9d7a13 VCVTTPD2QQ xmm2{k5}{z}, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +00000000000014FC 62b1fd8d7a54db10 VCVTTPD2QQ xmm2{k5}{z}, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000001504 62b1fd8d7a54dbf0 VCVTTPD2QQ xmm2{k5}{z}, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000150C 62c1fd287ac7 VCVTTPD2QQ ymm16, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001512 62e1fd287a03 VCVTTPD2QQ ymm16, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000001518 62e1fd387a03 VCVTTPD2QQ ymm16, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +000000000000151E 62a1fd287a44db08 VCVTTPD2QQ ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001526 62a1fd287a44dbf8 VCVTTPD2QQ ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000152E 62c1fd2d7ac7 VCVTTPD2QQ ymm16{k5}, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001534 62e1fd2d7a03 VCVTTPD2QQ ymm16{k5}, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000153A 62e1fd3d7a03 VCVTTPD2QQ ymm16{k5}, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000001540 62a1fd2d7a44db08 VCVTTPD2QQ ymm16{k5}, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001548 62a1fd2d7a44dbf8 VCVTTPD2QQ ymm16{k5}, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001550 62c1fda87ac7 VCVTTPD2QQ ymm16, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001556 62e1fda87a03 VCVTTPD2QQ ymm16, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000155C 62e1fdb87a03 VCVTTPD2QQ ymm16, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000001562 62a1fda87a44db08 VCVTTPD2QQ ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000156A 62a1fda87a44dbf8 VCVTTPD2QQ ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001572 62c1fdad7ac7 VCVTTPD2QQ ymm16{k5}{z}, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001578 62e1fdad7a03 VCVTTPD2QQ ymm16{k5}{z}, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000157E 62e1fdbd7a03 VCVTTPD2QQ ymm16{k5}{z}, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000001584 62a1fdad7a44db08 VCVTTPD2QQ ymm16{k5}{z}, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000158C 62a1fdad7a44dbf8 VCVTTPD2QQ ymm16{k5}{z}, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001594 6201fd487ac7 VCVTTPD2QQ zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000159A 6201fd187ac7 VCVTTPD2QQ zmm24, zmm31, {sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000015A0 6261fd487a03 VCVTTPD2QQ zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000015A6 6261fd587a03 VCVTTPD2QQ zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +00000000000015AC 6221fd487a44db04 VCVTTPD2QQ zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000015B4 6221fd487a44dbfc VCVTTPD2QQ zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000015BC 6201fd4d7ac7 VCVTTPD2QQ zmm24{k5}, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000015C2 6201fd1d7ac7 VCVTTPD2QQ zmm24{k5}, zmm31, {sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000015C8 6261fd4d7a03 VCVTTPD2QQ zmm24{k5}, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000015CE 6261fd5d7a03 VCVTTPD2QQ zmm24{k5}, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +00000000000015D4 6221fd4d7a44db04 VCVTTPD2QQ zmm24{k5}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000015DC 6221fd4d7a44dbfc VCVTTPD2QQ zmm24{k5}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000015E4 6201fdc87ac7 VCVTTPD2QQ zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000015EA 6201fd987ac7 VCVTTPD2QQ zmm24, zmm31, {sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000015F0 6261fdc87a03 VCVTTPD2QQ zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000015F6 6261fdd87a03 VCVTTPD2QQ zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +00000000000015FC 6221fdc87a44db04 VCVTTPD2QQ zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001604 6221fdc87a44dbfc VCVTTPD2QQ zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000160C 6201fdcd7ac7 VCVTTPD2QQ zmm24{k5}{z}, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001612 6201fd9d7ac7 VCVTTPD2QQ zmm24{k5}{z}, zmm31, {sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001618 6261fdcd7a03 VCVTTPD2QQ zmm24{k5}{z}, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000161E 6261fddd7a03 VCVTTPD2QQ zmm24{k5}{z}, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000001624 6221fdcd7a44db04 VCVTTPD2QQ zmm24{k5}{z}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000162C 6221fdcd7a44dbfc VCVTTPD2QQ zmm24{k5}{z}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001634 62f1fd0878d0 VCVTTPD2UQQ xmm2, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000163A 62f1fd087813 VCVTTPD2UQQ xmm2, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001640 62f1fd187813 VCVTTPD2UQQ xmm2, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000001646 62b1fd087854db10 VCVTTPD2UQQ xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000164E 62b1fd087854dbf0 VCVTTPD2UQQ xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000001656 62f1fd0d78d0 VCVTTPD2UQQ xmm2{k5}, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000165C 62f1fd0d7813 VCVTTPD2UQQ xmm2{k5}, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001662 62f1fd1d7813 VCVTTPD2UQQ xmm2{k5}, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000001668 62b1fd0d7854db10 VCVTTPD2UQQ xmm2{k5}, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000001670 62b1fd0d7854dbf0 VCVTTPD2UQQ xmm2{k5}, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000001678 62f1fd8878d0 VCVTTPD2UQQ xmm2, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000167E 62f1fd887813 VCVTTPD2UQQ xmm2, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001684 62f1fd987813 VCVTTPD2UQQ xmm2, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +000000000000168A 62b1fd887854db10 VCVTTPD2UQQ xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000001692 62b1fd887854dbf0 VCVTTPD2UQQ xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000169A 62f1fd8d78d0 VCVTTPD2UQQ xmm2{k5}{z}, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000016A0 62f1fd8d7813 VCVTTPD2UQQ xmm2{k5}{z}, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000016A6 62f1fd9d7813 VCVTTPD2UQQ xmm2{k5}{z}, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +00000000000016AC 62b1fd8d7854db10 VCVTTPD2UQQ xmm2{k5}{z}, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000016B4 62b1fd8d7854dbf0 VCVTTPD2UQQ xmm2{k5}{z}, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000016BC 62c1fd2878c7 VCVTTPD2UQQ ymm16, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000016C2 62e1fd287803 VCVTTPD2UQQ ymm16, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000016C8 62e1fd387803 VCVTTPD2UQQ ymm16, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +00000000000016CE 62a1fd287844db08 VCVTTPD2UQQ ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000016D6 62a1fd287844dbf8 VCVTTPD2UQQ ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000016DE 62c1fd2d78c7 VCVTTPD2UQQ ymm16{k5}, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000016E4 62e1fd2d7803 VCVTTPD2UQQ ymm16{k5}, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000016EA 62e1fd3d7803 VCVTTPD2UQQ ymm16{k5}, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +00000000000016F0 62a1fd2d7844db08 VCVTTPD2UQQ ymm16{k5}, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000016F8 62a1fd2d7844dbf8 VCVTTPD2UQQ ymm16{k5}, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001700 62c1fda878c7 VCVTTPD2UQQ ymm16, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001706 62e1fda87803 VCVTTPD2UQQ ymm16, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000170C 62e1fdb87803 VCVTTPD2UQQ ymm16, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000001712 62a1fda87844db08 VCVTTPD2UQQ ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000171A 62a1fda87844dbf8 VCVTTPD2UQQ ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001722 62c1fdad78c7 VCVTTPD2UQQ ymm16{k5}{z}, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001728 62e1fdad7803 VCVTTPD2UQQ ymm16{k5}{z}, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000172E 62e1fdbd7803 VCVTTPD2UQQ ymm16{k5}{z}, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000001734 62a1fdad7844db08 VCVTTPD2UQQ ymm16{k5}{z}, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000173C 62a1fdad7844dbf8 VCVTTPD2UQQ ymm16{k5}{z}, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001744 6201fd4878c7 VCVTTPD2UQQ zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000174A 6201fd1878c7 VCVTTPD2UQQ zmm24, zmm31, {sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001750 6261fd487803 VCVTTPD2UQQ zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001756 6261fd587803 VCVTTPD2UQQ zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +000000000000175C 6221fd487844db04 VCVTTPD2UQQ zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001764 6221fd487844dbfc VCVTTPD2UQQ zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000176C 6201fd4d78c7 VCVTTPD2UQQ zmm24{k5}, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001772 6201fd1d78c7 VCVTTPD2UQQ zmm24{k5}, zmm31, {sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001778 6261fd4d7803 VCVTTPD2UQQ zmm24{k5}, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000177E 6261fd5d7803 VCVTTPD2UQQ zmm24{k5}, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000001784 6221fd4d7844db04 VCVTTPD2UQQ zmm24{k5}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000178C 6221fd4d7844dbfc VCVTTPD2UQQ zmm24{k5}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001794 6201fdc878c7 VCVTTPD2UQQ zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000179A 6201fd9878c7 VCVTTPD2UQQ zmm24, zmm31, {sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000017A0 6261fdc87803 VCVTTPD2UQQ zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000017A6 6261fdd87803 VCVTTPD2UQQ zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +00000000000017AC 6221fdc87844db04 VCVTTPD2UQQ zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000017B4 6221fdc87844dbfc VCVTTPD2UQQ zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000017BC 6201fdcd78c7 VCVTTPD2UQQ zmm24{k5}{z}, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000017C2 6201fd9d78c7 VCVTTPD2UQQ zmm24{k5}{z}, zmm31, {sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000017C8 6261fdcd7803 VCVTTPD2UQQ zmm24{k5}{z}, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000017CE 6261fddd7803 VCVTTPD2UQQ zmm24{k5}{z}, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +00000000000017D4 6221fdcd7844db04 VCVTTPD2UQQ zmm24{k5}{z}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000017DC 6221fdcd7844dbfc VCVTTPD2UQQ zmm24{k5}{z}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000017E4 62f17d087ad0 VCVTTPS2QQ xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000017EA 62f17d087a13 VCVTTPS2QQ xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000017F0 62f17d187a13 VCVTTPS2QQ xmm2, dword ptr [rbx]{1to2} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 2 times + +00000000000017F6 62b17d087a54db20 VCVTTPS2QQ xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +00000000000017FE 62b17d087a54dbe0 VCVTTPS2QQ xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +0000000000001806 62f17d0d7ad0 VCVTTPS2QQ xmm2{k5}, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000180C 62f17d0d7a13 VCVTTPS2QQ xmm2{k5}, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000001812 62f17d1d7a13 VCVTTPS2QQ xmm2{k5}, dword ptr [rbx]{1to2} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 2 times + +0000000000001818 62b17d0d7a54db20 VCVTTPS2QQ xmm2{k5}, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000001820 62b17d0d7a54dbe0 VCVTTPS2QQ xmm2{k5}, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +0000000000001828 62f17d887ad0 VCVTTPS2QQ xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000182E 62f17d887a13 VCVTTPS2QQ xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000001834 62f17d987a13 VCVTTPS2QQ xmm2, dword ptr [rbx]{1to2} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 2 times + +000000000000183A 62b17d887a54db20 VCVTTPS2QQ xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000001842 62b17d887a54dbe0 VCVTTPS2QQ xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +000000000000184A 62f17d8d7ad0 VCVTTPS2QQ xmm2{k5}{z}, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001850 62f17d8d7a13 VCVTTPS2QQ xmm2{k5}{z}, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000001856 62f17d9d7a13 VCVTTPS2QQ xmm2{k5}{z}, dword ptr [rbx]{1to2} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 2 times + +000000000000185C 62b17d8d7a54db20 VCVTTPS2QQ xmm2{k5}{z}, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000001864 62b17d8d7a54dbe0 VCVTTPS2QQ xmm2{k5}{z}, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +000000000000186C 62e17d287ac0 VCVTTPS2QQ ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001872 62e17d287a03 VCVTTPS2QQ ymm16, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001878 62e17d387a03 VCVTTPS2QQ ymm16, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +000000000000187E 62a17d287a44db10 VCVTTPS2QQ ymm16, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000001886 62a17d287a44dbf0 VCVTTPS2QQ ymm16, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000188E 62e17d2d7ac0 VCVTTPS2QQ ymm16{k5}, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001894 62e17d2d7a03 VCVTTPS2QQ ymm16{k5}, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000189A 62e17d3d7a03 VCVTTPS2QQ ymm16{k5}, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +00000000000018A0 62a17d2d7a44db10 VCVTTPS2QQ ymm16{k5}, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000018A8 62a17d2d7a44dbf0 VCVTTPS2QQ ymm16{k5}, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000018B0 62e17da87ac0 VCVTTPS2QQ ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000018B6 62e17da87a03 VCVTTPS2QQ ymm16, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000018BC 62e17db87a03 VCVTTPS2QQ ymm16, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +00000000000018C2 62a17da87a44db10 VCVTTPS2QQ ymm16, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000018CA 62a17da87a44dbf0 VCVTTPS2QQ ymm16, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000018D2 62e17dad7ac0 VCVTTPS2QQ ymm16{k5}{z}, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000018D8 62e17dad7a03 VCVTTPS2QQ ymm16{k5}{z}, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000018DE 62e17dbd7a03 VCVTTPS2QQ ymm16{k5}{z}, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +00000000000018E4 62a17dad7a44db10 VCVTTPS2QQ ymm16{k5}{z}, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000018EC 62a17dad7a44dbf0 VCVTTPS2QQ ymm16{k5}{z}, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000018F4 62417d487ac7 VCVTTPS2QQ zmm24, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000018FA 62417d187ac7 VCVTTPS2QQ zmm24, ymm15, {sae} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001900 62617d487a03 VCVTTPS2QQ zmm24, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000001906 62617d587a03 VCVTTPS2QQ zmm24, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +000000000000190C 62217d487a44db08 VCVTTPS2QQ zmm24, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001914 62217d487a44dbf8 VCVTTPS2QQ zmm24, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000191C 62417d4d7ac7 VCVTTPS2QQ zmm24{k5}, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001922 62417d1d7ac7 VCVTTPS2QQ zmm24{k5}, ymm15, {sae} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001928 62617d4d7a03 VCVTTPS2QQ zmm24{k5}, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000192E 62617d5d7a03 VCVTTPS2QQ zmm24{k5}, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +0000000000001934 62217d4d7a44db08 VCVTTPS2QQ zmm24{k5}, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000193C 62217d4d7a44dbf8 VCVTTPS2QQ zmm24{k5}, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001944 62417dc87ac7 VCVTTPS2QQ zmm24, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000194A 62417d987ac7 VCVTTPS2QQ zmm24, ymm15, {sae} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001950 62617dc87a03 VCVTTPS2QQ zmm24, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000001956 62617dd87a03 VCVTTPS2QQ zmm24, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +000000000000195C 62217dc87a44db08 VCVTTPS2QQ zmm24, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001964 62217dc87a44dbf8 VCVTTPS2QQ zmm24, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000196C 62417dcd7ac7 VCVTTPS2QQ zmm24{k5}{z}, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001972 62417d9d7ac7 VCVTTPS2QQ zmm24{k5}{z}, ymm15, {sae} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001978 62617dcd7a03 VCVTTPS2QQ zmm24{k5}{z}, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000197E 62617ddd7a03 VCVTTPS2QQ zmm24{k5}{z}, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +0000000000001984 62217dcd7a44db08 VCVTTPS2QQ zmm24{k5}{z}, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000198C 62217dcd7a44dbf8 VCVTTPS2QQ zmm24{k5}{z}, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001994 62f17d0878d0 VCVTTPS2UQQ xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000199A 62f17d087813 VCVTTPS2UQQ xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000019A0 62f17d187813 VCVTTPS2UQQ xmm2, dword ptr [rbx]{1to2} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 2 times + +00000000000019A6 62b17d087854db20 VCVTTPS2UQQ xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +00000000000019AE 62b17d087854dbe0 VCVTTPS2UQQ xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +00000000000019B6 62f17d0d78d0 VCVTTPS2UQQ xmm2{k5}, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000019BC 62f17d0d7813 VCVTTPS2UQQ xmm2{k5}, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000019C2 62f17d1d7813 VCVTTPS2UQQ xmm2{k5}, dword ptr [rbx]{1to2} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 2 times + +00000000000019C8 62b17d0d7854db20 VCVTTPS2UQQ xmm2{k5}, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +00000000000019D0 62b17d0d7854dbe0 VCVTTPS2UQQ xmm2{k5}, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +00000000000019D8 62f17d8878d0 VCVTTPS2UQQ xmm2, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000019DE 62f17d887813 VCVTTPS2UQQ xmm2, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000019E4 62f17d987813 VCVTTPS2UQQ xmm2, dword ptr [rbx]{1to2} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 2 times + +00000000000019EA 62b17d887854db20 VCVTTPS2UQQ xmm2, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +00000000000019F2 62b17d887854dbe0 VCVTTPS2UQQ xmm2, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +00000000000019FA 62f17d8d78d0 VCVTTPS2UQQ xmm2{k5}{z}, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001A00 62f17d8d7813 VCVTTPS2UQQ xmm2{k5}{z}, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000001A06 62f17d9d7813 VCVTTPS2UQQ xmm2{k5}{z}, dword ptr [rbx]{1to2} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 2 times + +0000000000001A0C 62b17d8d7854db20 VCVTTPS2UQQ xmm2{k5}{z}, qword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000001A14 62b17d8d7854dbe0 VCVTTPS2UQQ xmm2{k5}{z}, qword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +0000000000001A1C 62e17d2878c0 VCVTTPS2UQQ ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001A22 62e17d287803 VCVTTPS2UQQ ymm16, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001A28 62e17d387803 VCVTTPS2UQQ ymm16, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000001A2E 62a17d287844db10 VCVTTPS2UQQ ymm16, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000001A36 62a17d287844dbf0 VCVTTPS2UQQ ymm16, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000001A3E 62e17d2d78c0 VCVTTPS2UQQ ymm16{k5}, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001A44 62e17d2d7803 VCVTTPS2UQQ ymm16{k5}, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001A4A 62e17d3d7803 VCVTTPS2UQQ ymm16{k5}, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000001A50 62a17d2d7844db10 VCVTTPS2UQQ ymm16{k5}, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000001A58 62a17d2d7844dbf0 VCVTTPS2UQQ ymm16{k5}, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000001A60 62e17da878c0 VCVTTPS2UQQ ymm16, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001A66 62e17da87803 VCVTTPS2UQQ ymm16, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001A6C 62e17db87803 VCVTTPS2UQQ ymm16, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000001A72 62a17da87844db10 VCVTTPS2UQQ ymm16, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000001A7A 62a17da87844dbf0 VCVTTPS2UQQ ymm16, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000001A82 62e17dad78c0 VCVTTPS2UQQ ymm16{k5}{z}, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001A88 62e17dad7803 VCVTTPS2UQQ ymm16{k5}{z}, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001A8E 62e17dbd7803 VCVTTPS2UQQ ymm16{k5}{z}, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000001A94 62a17dad7844db10 VCVTTPS2UQQ ymm16{k5}{z}, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000001A9C 62a17dad7844dbf0 VCVTTPS2UQQ ymm16{k5}{z}, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000001AA4 62417d4878c7 VCVTTPS2UQQ zmm24, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001AAA 62417d1878c7 VCVTTPS2UQQ zmm24, ymm15, {sae} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001AB0 62617d487803 VCVTTPS2UQQ zmm24, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000001AB6 62617d587803 VCVTTPS2UQQ zmm24, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +0000000000001ABC 62217d487844db08 VCVTTPS2UQQ zmm24, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001AC4 62217d487844dbf8 VCVTTPS2UQQ zmm24, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001ACC 62417d4d78c7 VCVTTPS2UQQ zmm24{k5}, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001AD2 62417d1d78c7 VCVTTPS2UQQ zmm24{k5}, ymm15, {sae} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001AD8 62617d4d7803 VCVTTPS2UQQ zmm24{k5}, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000001ADE 62617d5d7803 VCVTTPS2UQQ zmm24{k5}, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +0000000000001AE4 62217d4d7844db08 VCVTTPS2UQQ zmm24{k5}, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001AEC 62217d4d7844dbf8 VCVTTPS2UQQ zmm24{k5}, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001AF4 62417dc878c7 VCVTTPS2UQQ zmm24, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001AFA 62417d9878c7 VCVTTPS2UQQ zmm24, ymm15, {sae} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001B00 62617dc87803 VCVTTPS2UQQ zmm24, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000001B06 62617dd87803 VCVTTPS2UQQ zmm24, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +0000000000001B0C 62217dc87844db08 VCVTTPS2UQQ zmm24, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001B14 62217dc87844dbf8 VCVTTPS2UQQ zmm24, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001B1C 62417dcd78c7 VCVTTPS2UQQ zmm24{k5}{z}, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001B22 62417d9d78c7 VCVTTPS2UQQ zmm24{k5}{z}, ymm15, {sae} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001B28 62617dcd7803 VCVTTPS2UQQ zmm24{k5}{z}, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000001B2E 62617ddd7803 VCVTTPS2UQQ zmm24{k5}{z}, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +0000000000001B34 62217dcd7844db08 VCVTTPS2UQQ zmm24{k5}{z}, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001B3C 62217dcd7844dbf8 VCVTTPS2UQQ zmm24{k5}{z}, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Half + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001B44 62f1fe087ad0 VCVTUQQ2PD xmm2, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001B4A 62f1fe087a13 VCVTUQQ2PD xmm2, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001B50 62f1fe187a13 VCVTUQQ2PD xmm2, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000001B56 62b1fe087a54db10 VCVTUQQ2PD xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000001B5E 62b1fe087a54dbf0 VCVTUQQ2PD xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000001B66 62f1fe0d7ad0 VCVTUQQ2PD xmm2{k5}, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001B6C 62f1fe0d7a13 VCVTUQQ2PD xmm2{k5}, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001B72 62f1fe1d7a13 VCVTUQQ2PD xmm2{k5}, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000001B78 62b1fe0d7a54db10 VCVTUQQ2PD xmm2{k5}, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000001B80 62b1fe0d7a54dbf0 VCVTUQQ2PD xmm2{k5}, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000001B88 62f1fe887ad0 VCVTUQQ2PD xmm2, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001B8E 62f1fe887a13 VCVTUQQ2PD xmm2, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001B94 62f1fe987a13 VCVTUQQ2PD xmm2, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000001B9A 62b1fe887a54db10 VCVTUQQ2PD xmm2, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000001BA2 62b1fe887a54dbf0 VCVTUQQ2PD xmm2, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000001BAA 62f1fe8d7ad0 VCVTUQQ2PD xmm2{k5}{z}, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001BB0 62f1fe8d7a13 VCVTUQQ2PD xmm2{k5}{z}, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001BB6 62f1fe9d7a13 VCVTUQQ2PD xmm2{k5}{z}, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000001BBC 62b1fe8d7a54db10 VCVTUQQ2PD xmm2{k5}{z}, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000001BC4 62b1fe8d7a54dbf0 VCVTUQQ2PD xmm2{k5}{z}, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000001BCC 62c1fe287ac7 VCVTUQQ2PD ymm16, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001BD2 62e1fe287a03 VCVTUQQ2PD ymm16, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000001BD8 62e1fe387a03 VCVTUQQ2PD ymm16, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000001BDE 62a1fe287a44db08 VCVTUQQ2PD ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001BE6 62a1fe287a44dbf8 VCVTUQQ2PD ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001BEE 62c1fe2d7ac7 VCVTUQQ2PD ymm16{k5}, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001BF4 62e1fe2d7a03 VCVTUQQ2PD ymm16{k5}, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000001BFA 62e1fe3d7a03 VCVTUQQ2PD ymm16{k5}, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000001C00 62a1fe2d7a44db08 VCVTUQQ2PD ymm16{k5}, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001C08 62a1fe2d7a44dbf8 VCVTUQQ2PD ymm16{k5}, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001C10 62c1fea87ac7 VCVTUQQ2PD ymm16, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001C16 62e1fea87a03 VCVTUQQ2PD ymm16, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000001C1C 62e1feb87a03 VCVTUQQ2PD ymm16, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000001C22 62a1fea87a44db08 VCVTUQQ2PD ymm16, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001C2A 62a1fea87a44dbf8 VCVTUQQ2PD ymm16, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001C32 62c1fead7ac7 VCVTUQQ2PD ymm16{k5}{z}, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001C38 62e1fead7a03 VCVTUQQ2PD ymm16{k5}{z}, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000001C3E 62e1febd7a03 VCVTUQQ2PD ymm16{k5}{z}, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000001C44 62a1fead7a44db08 VCVTUQQ2PD ymm16{k5}{z}, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001C4C 62a1fead7a44dbf8 VCVTUQQ2PD ymm16{k5}{z}, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001C54 6201fe487ac7 VCVTUQQ2PD zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001C5A 6201fe387ac7 VCVTUQQ2PD zmm24, zmm31, {rd-sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001C60 6261fe487a03 VCVTUQQ2PD zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001C66 6261fe587a03 VCVTUQQ2PD zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000001C6C 6221fe487a44db04 VCVTUQQ2PD zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001C74 6221fe487a44dbfc VCVTUQQ2PD zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001C7C 6201fe4d7ac7 VCVTUQQ2PD zmm24{k5}, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001C82 6201fe3d7ac7 VCVTUQQ2PD zmm24{k5}, zmm31, {rd-sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001C88 6261fe4d7a03 VCVTUQQ2PD zmm24{k5}, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001C8E 6261fe5d7a03 VCVTUQQ2PD zmm24{k5}, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000001C94 6221fe4d7a44db04 VCVTUQQ2PD zmm24{k5}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001C9C 6221fe4d7a44dbfc VCVTUQQ2PD zmm24{k5}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001CA4 6201fec87ac7 VCVTUQQ2PD zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001CAA 6201feb87ac7 VCVTUQQ2PD zmm24, zmm31, {rd-sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001CB0 6261fec87a03 VCVTUQQ2PD zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001CB6 6261fed87a03 VCVTUQQ2PD zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000001CBC 6221fec87a44db04 VCVTUQQ2PD zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001CC4 6221fec87a44dbfc VCVTUQQ2PD zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001CCC 6201fecd7ac7 VCVTUQQ2PD zmm24{k5}{z}, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001CD2 6201febd7ac7 VCVTUQQ2PD zmm24{k5}{z}, zmm31, {rd-sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001CD8 6261fecd7a03 VCVTUQQ2PD zmm24{k5}{z}, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001CDE 6261fedd7a03 VCVTUQQ2PD zmm24{k5}{z}, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000001CE4 6221fecd7a44db04 VCVTUQQ2PD zmm24{k5}{z}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001CEC 6221fecd7a44dbfc VCVTUQQ2PD zmm24{k5}{z}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001CF4 62f1ff087ad0 VCVTUQQ2PS xmm2, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001CFA 62d1ff287ad7 VCVTUQQ2PS xmm2, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001D00 62f1ff187a13 VCVTUQQ2PS xmm2, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000001D06 62f1ff387a13 VCVTUQQ2PS xmm2, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000001D0C 62f1ff0d7ad0 VCVTUQQ2PS xmm2{k5}, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001D12 62d1ff2d7ad7 VCVTUQQ2PS xmm2{k5}, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001D18 62f1ff1d7a13 VCVTUQQ2PS xmm2{k5}, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000001D1E 62f1ff3d7a13 VCVTUQQ2PS xmm2{k5}, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000001D24 62f1ff887ad0 VCVTUQQ2PS xmm2, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001D2A 62d1ffa87ad7 VCVTUQQ2PS xmm2, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001D30 62f1ff987a13 VCVTUQQ2PS xmm2, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000001D36 62f1ffb87a13 VCVTUQQ2PS xmm2, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000001D3C 62f1ff8d7ad0 VCVTUQQ2PS xmm2{k5}{z}, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001D42 62d1ffad7ad7 VCVTUQQ2PS xmm2{k5}{z}, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001D48 62f1ff9d7a13 VCVTUQQ2PS xmm2{k5}{z}, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000001D4E 62f1ffbd7a13 VCVTUQQ2PS xmm2{k5}{z}, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000001D54 6281ff487ac7 VCVTUQQ2PS ymm16, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001D5A 6281ff387ac7 VCVTUQQ2PS ymm16, zmm31, {rd-sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001D60 62e1ff487a03 VCVTUQQ2PS ymm16, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001D66 62e1ff587a03 VCVTUQQ2PS ymm16, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000001D6C 62a1ff487a44db04 VCVTUQQ2PS ymm16, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001D74 62a1ff487a44dbfc VCVTUQQ2PS ymm16, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001D7C 6281ff4d7ac7 VCVTUQQ2PS ymm16{k5}, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001D82 6281ff3d7ac7 VCVTUQQ2PS ymm16{k5}, zmm31, {rd-sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001D88 62e1ff4d7a03 VCVTUQQ2PS ymm16{k5}, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001D8E 62e1ff5d7a03 VCVTUQQ2PS ymm16{k5}, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000001D94 62a1ff4d7a44db04 VCVTUQQ2PS ymm16{k5}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001D9C 62a1ff4d7a44dbfc VCVTUQQ2PS ymm16{k5}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001DA4 6281ffc87ac7 VCVTUQQ2PS ymm16, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001DAA 6281ffb87ac7 VCVTUQQ2PS ymm16, zmm31, {rd-sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001DB0 62e1ffc87a03 VCVTUQQ2PS ymm16, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001DB6 62e1ffd87a03 VCVTUQQ2PS ymm16, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000001DBC 62a1ffc87a44db04 VCVTUQQ2PS ymm16, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001DC4 62a1ffc87a44dbfc VCVTUQQ2PS ymm16, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001DCC 6281ffcd7ac7 VCVTUQQ2PS ymm16{k5}{z}, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001DD2 6281ffbd7ac7 VCVTUQQ2PS ymm16{k5}{z}, zmm31, {rd-sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001DD8 62e1ffcd7a03 VCVTUQQ2PS ymm16{k5}{z}, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001DDE 62e1ffdd7a03 VCVTUQQ2PS ymm16{k5}{z}, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000001DE4 62a1ffcd7a44db04 VCVTUQQ2PS ymm16{k5}{z}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001DEC 62a1ffcd7a44dbfc VCVTUQQ2PS ymm16{k5}{z}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001DF4 62437d481bc70a VEXTRACTF32X8 ymm15, zmm24, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001DFB 62637d481b030a VEXTRACTF32X8 ymmword ptr [rbx], zmm24, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E02 62237d481b44db080a VEXTRACTF32X8 ymmword ptr [rbx+r11*8+0x100], zmm24, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E0B 62237d481b44dbf80a VEXTRACTF32X8 ymmword ptr [rbx+r11*8-0x100], zmm24, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E14 62e3fd2819c00a VEXTRACTF64X2 xmm0, ymm16, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E1B 6263fd4819c00a VEXTRACTF64X2 xmm0, zmm24, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E22 62e3fd2819030a VEXTRACTF64X2 xmmword ptr [rbx], ymm16, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E29 6263fd4819030a VEXTRACTF64X2 xmmword ptr [rbx], zmm24, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E30 62a3fd281944db100a VEXTRACTF64X2 xmmword ptr [rbx+r11*8+0x100], ymm16, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E39 6223fd481944db100a VEXTRACTF64X2 xmmword ptr [rbx+r11*8+0x100], zmm24, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E42 62a3fd281944dbf00a VEXTRACTF64X2 xmmword ptr [rbx+r11*8-0x100], ymm16, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E4B 6223fd481944dbf00a VEXTRACTF64X2 xmmword ptr [rbx+r11*8-0x100], zmm24, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E54 62437d483bc70a VEXTRACTI32X8 ymm15, zmm24, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E5B 62637d483b030a VEXTRACTI32X8 ymmword ptr [rbx], zmm24, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E62 62237d483b44db080a VEXTRACTI32X8 ymmword ptr [rbx+r11*8+0x100], zmm24, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E6B 62237d483b44dbf80a VEXTRACTI32X8 ymmword ptr [rbx+r11*8-0x100], zmm24, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E74 62e3fd2839c00a VEXTRACTI64X2 xmm0, ymm16, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E7B 6263fd4839c00a VEXTRACTI64X2 xmm0, zmm24, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E82 62e3fd2839030a VEXTRACTI64X2 xmmword ptr [rbx], ymm16, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E89 6263fd4839030a VEXTRACTI64X2 xmmword ptr [rbx], zmm24, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E90 62a3fd283944db100a VEXTRACTI64X2 xmmword ptr [rbx+r11*8+0x100], ymm16, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001E99 6223fd483944db100a VEXTRACTI64X2 xmmword ptr [rbx+r11*8+0x100], zmm24, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001EA2 62a3fd283944dbf00a VEXTRACTI64X2 xmmword ptr [rbx+r11*8-0x100], ymm16, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001EAB 6223fd483944dbf00a VEXTRACTI64X2 xmmword ptr [rbx+r11*8-0x100], zmm24, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001EB4 62f3fd0866d80a VFPCLASSPD k3, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001EBB 62d3fd2866df0a VFPCLASSPD k3, ymm15, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001EC2 6293fd4866df0a VFPCLASSPD k3, zmm31, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001EC9 62f3fd18661b0a VFPCLASSPD k3, qword ptr [rbx]{1to2}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001ED0 62f3fd38661b0a VFPCLASSPD k3, qword ptr [rbx]{1to4}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001ED7 62f3fd58661b0a VFPCLASSPD k3, qword ptr [rbx]{1to8}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001EDE 62f3fd0d66d80a VFPCLASSPD k3{k5}, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001EE5 62d3fd2d66df0a VFPCLASSPD k3{k5}, ymm15, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001EEC 6293fd4d66df0a VFPCLASSPD k3{k5}, zmm31, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001EF3 62f3fd1d661b0a VFPCLASSPD k3{k5}, qword ptr [rbx]{1to2}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001EFA 62f3fd3d661b0a VFPCLASSPD k3{k5}, qword ptr [rbx]{1to4}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F01 62f3fd5d661b0a VFPCLASSPD k3{k5}, qword ptr [rbx]{1to8}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F08 62f37d0866d80a VFPCLASSPS k3, xmm0, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F0F 62d37d2866df0a VFPCLASSPS k3, ymm15, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F16 62937d4866df0a VFPCLASSPS k3, zmm31, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F1D 62f37d18661b0a VFPCLASSPS k3, dword ptr [rbx]{1to4}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F24 62f37d38661b0a VFPCLASSPS k3, dword ptr [rbx]{1to8}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F2B 62f37d58661b0a VFPCLASSPS k3, dword ptr [rbx]{1to16}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F32 62f37d0d66d80a VFPCLASSPS k3{k5}, xmm0, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F39 62d37d2d66df0a VFPCLASSPS k3{k5}, ymm15, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F40 62937d4d66df0a VFPCLASSPS k3{k5}, zmm31, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F47 62f37d1d661b0a VFPCLASSPS k3{k5}, dword ptr [rbx]{1to4}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F4E 62f37d3d661b0a VFPCLASSPS k3{k5}, dword ptr [rbx]{1to8}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F55 62f37d5d661b0a VFPCLASSPS k3{k5}, dword ptr [rbx]{1to16}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F5C 62f3fd0867d80a VFPCLASSSD k3, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F63 62f3fd08671b0a VFPCLASSSD k3, qword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F6A 62b3fd08675cdb200a VFPCLASSSD k3, qword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F73 62b3fd08675cdbe00a VFPCLASSSD k3, qword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F7C 62f3fd0d67d80a VFPCLASSSD k3{k5}, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F83 62f3fd0d671b0a VFPCLASSSD k3{k5}, qword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F8A 62b3fd0d675cdb200a VFPCLASSSD k3{k5}, qword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F93 62b3fd0d675cdbe00a VFPCLASSSD k3{k5}, qword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001F9C 62f37d0867d80a VFPCLASSSS k3, xmm0, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001FA3 62f37d08671b0a VFPCLASSSS k3, dword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001FAA 62b37d08675cdb400a VFPCLASSSS k3, dword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000040, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001FB3 62b37d08675cdbc00a VFPCLASSSS k3, dword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffc0, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001FBC 62f37d0d67d80a VFPCLASSSS k3{k5}, xmm0, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001FC3 62f37d0d671b0a VFPCLASSSS k3{k5}, dword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001FCA 62b37d0d675cdb400a VFPCLASSSS k3{k5}, dword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000040, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001FD3 62b37d0d675cdbc00a VFPCLASSSS k3{k5}, dword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffc0, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001FDC 62433d401ac70a VINSERTF32X8 zmm24, zmm24, ymm15, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001FE3 62633d401a030a VINSERTF32X8 zmm24, zmm24, ymmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001FEA 62233d401a44db080a VINSERTF32X8 zmm24, zmm24, ymmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001FF3 62233d401a44dbf80a VINSERTF32X8 zmm24, zmm24, ymmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001FFC 62433d451ac70a VINSERTF32X8 zmm24{k5}, zmm24, ymm15, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002003 62633d451a030a VINSERTF32X8 zmm24{k5}, zmm24, ymmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000200A 62233d451a44db080a VINSERTF32X8 zmm24{k5}, zmm24, ymmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002013 62233d451a44dbf80a VINSERTF32X8 zmm24{k5}, zmm24, ymmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000201C 62433dc01ac70a VINSERTF32X8 zmm24, zmm24, ymm15, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002023 62633dc01a030a VINSERTF32X8 zmm24, zmm24, ymmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000202A 62233dc01a44db080a VINSERTF32X8 zmm24, zmm24, ymmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002033 62233dc01a44dbf80a VINSERTF32X8 zmm24, zmm24, ymmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000203C 62433dc51ac70a VINSERTF32X8 zmm24{k5}{z}, zmm24, ymm15, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002043 62633dc51a030a VINSERTF32X8 zmm24{k5}{z}, zmm24, ymmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000204A 62233dc51a44db080a VINSERTF32X8 zmm24{k5}{z}, zmm24, ymmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002053 62233dc51a44dbf80a VINSERTF32X8 zmm24{k5}{z}, zmm24, ymmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000205C 62e3952818c00a VINSERTF64X2 ymm16, ymm13, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002063 62e3952818030a VINSERTF64X2 ymm16, ymm13, xmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000206A 62a395281844db100a VINSERTF64X2 ymm16, ymm13, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002073 62a395281844dbf00a VINSERTF64X2 ymm16, ymm13, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000207C 62e3952d18c00a VINSERTF64X2 ymm16{k5}, ymm13, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002083 62e3952d18030a VINSERTF64X2 ymm16{k5}, ymm13, xmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000208A 62a3952d1844db100a VINSERTF64X2 ymm16{k5}, ymm13, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002093 62a3952d1844dbf00a VINSERTF64X2 ymm16{k5}, ymm13, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000209C 62e395a818c00a VINSERTF64X2 ymm16, ymm13, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000020A3 62e395a818030a VINSERTF64X2 ymm16, ymm13, xmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000020AA 62a395a81844db100a VINSERTF64X2 ymm16, ymm13, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000020B3 62a395a81844dbf00a VINSERTF64X2 ymm16, ymm13, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000020BC 62e395ad18c00a VINSERTF64X2 ymm16{k5}{z}, ymm13, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000020C3 62e395ad18030a VINSERTF64X2 ymm16{k5}{z}, ymm13, xmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000020CA 62a395ad1844db100a VINSERTF64X2 ymm16{k5}{z}, ymm13, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000020D3 62a395ad1844dbf00a VINSERTF64X2 ymm16{k5}{z}, ymm13, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000020DC 6263bd4018c00a VINSERTF64X2 zmm24, zmm24, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000020E3 6263bd4018030a VINSERTF64X2 zmm24, zmm24, xmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000020EA 6223bd401844db100a VINSERTF64X2 zmm24, zmm24, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000020F3 6223bd401844dbf00a VINSERTF64X2 zmm24, zmm24, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000020FC 6263bd4518c00a VINSERTF64X2 zmm24{k5}, zmm24, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002103 6263bd4518030a VINSERTF64X2 zmm24{k5}, zmm24, xmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000210A 6223bd451844db100a VINSERTF64X2 zmm24{k5}, zmm24, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002113 6223bd451844dbf00a VINSERTF64X2 zmm24{k5}, zmm24, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000211C 6263bdc018c00a VINSERTF64X2 zmm24, zmm24, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002123 6263bdc018030a VINSERTF64X2 zmm24, zmm24, xmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000212A 6223bdc01844db100a VINSERTF64X2 zmm24, zmm24, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002133 6223bdc01844dbf00a VINSERTF64X2 zmm24, zmm24, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000213C 6263bdc518c00a VINSERTF64X2 zmm24{k5}{z}, zmm24, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002143 6263bdc518030a VINSERTF64X2 zmm24{k5}{z}, zmm24, xmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000214A 6223bdc51844db100a VINSERTF64X2 zmm24{k5}{z}, zmm24, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002153 6223bdc51844dbf00a VINSERTF64X2 zmm24{k5}{z}, zmm24, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000215C 62433d403ac70a VINSERTI32X8 zmm24, zmm24, ymm15, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002163 62633d403a030a VINSERTI32X8 zmm24, zmm24, ymmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000216A 62233d403a44db080a VINSERTI32X8 zmm24, zmm24, ymmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002173 62233d403a44dbf80a VINSERTI32X8 zmm24, zmm24, ymmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000217C 62433d453ac70a VINSERTI32X8 zmm24{k5}, zmm24, ymm15, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002183 62633d453a030a VINSERTI32X8 zmm24{k5}, zmm24, ymmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000218A 62233d453a44db080a VINSERTI32X8 zmm24{k5}, zmm24, ymmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002193 62233d453a44dbf80a VINSERTI32X8 zmm24{k5}, zmm24, ymmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000219C 62433dc03ac70a VINSERTI32X8 zmm24, zmm24, ymm15, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000021A3 62633dc03a030a VINSERTI32X8 zmm24, zmm24, ymmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000021AA 62233dc03a44db080a VINSERTI32X8 zmm24, zmm24, ymmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000021B3 62233dc03a44dbf80a VINSERTI32X8 zmm24, zmm24, ymmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000021BC 62433dc53ac70a VINSERTI32X8 zmm24{k5}{z}, zmm24, ymm15, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000021C3 62633dc53a030a VINSERTI32X8 zmm24{k5}{z}, zmm24, ymmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000021CA 62233dc53a44db080a VINSERTI32X8 zmm24{k5}{z}, zmm24, ymmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000021D3 62233dc53a44dbf80a VINSERTI32X8 zmm24{k5}{z}, zmm24, ymmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 8 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000021DC 62e3952838c00a VINSERTI64X2 ymm16, ymm13, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000021E3 62e3952838030a VINSERTI64X2 ymm16, ymm13, xmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000021EA 62a395283844db100a VINSERTI64X2 ymm16, ymm13, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000021F3 62a395283844dbf00a VINSERTI64X2 ymm16, ymm13, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000021FC 62e3952d38c00a VINSERTI64X2 ymm16{k5}, ymm13, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002203 62e3952d38030a VINSERTI64X2 ymm16{k5}, ymm13, xmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000220A 62a3952d3844db100a VINSERTI64X2 ymm16{k5}, ymm13, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002213 62a3952d3844dbf00a VINSERTI64X2 ymm16{k5}, ymm13, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000221C 62e395a838c00a VINSERTI64X2 ymm16, ymm13, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002223 62e395a838030a VINSERTI64X2 ymm16, ymm13, xmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000222A 62a395a83844db100a VINSERTI64X2 ymm16, ymm13, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002233 62a395a83844dbf00a VINSERTI64X2 ymm16, ymm13, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000223C 62e395ad38c00a VINSERTI64X2 ymm16{k5}{z}, ymm13, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002243 62e395ad38030a VINSERTI64X2 ymm16{k5}{z}, ymm13, xmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000224A 62a395ad3844db100a VINSERTI64X2 ymm16{k5}{z}, ymm13, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002253 62a395ad3844dbf00a VINSERTI64X2 ymm16{k5}{z}, ymm13, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000225C 6263bd4038c00a VINSERTI64X2 zmm24, zmm24, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002263 6263bd4038030a VINSERTI64X2 zmm24, zmm24, xmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000226A 6223bd403844db100a VINSERTI64X2 zmm24, zmm24, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002273 6223bd403844dbf00a VINSERTI64X2 zmm24, zmm24, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000227C 6263bd4538c00a VINSERTI64X2 zmm24{k5}, zmm24, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002283 6263bd4538030a VINSERTI64X2 zmm24{k5}, zmm24, xmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000228A 6223bd453844db100a VINSERTI64X2 zmm24{k5}, zmm24, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002293 6223bd453844dbf00a VINSERTI64X2 zmm24{k5}, zmm24, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000229C 6263bdc038c00a VINSERTI64X2 zmm24, zmm24, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000022A3 6263bdc038030a VINSERTI64X2 zmm24, zmm24, xmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000022AA 6223bdc03844db100a VINSERTI64X2 zmm24, zmm24, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000022B3 6223bdc03844dbf00a VINSERTI64X2 zmm24, zmm24, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000022BC 6263bdc538c00a VINSERTI64X2 zmm24{k5}{z}, zmm24, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000022C3 6263bdc538030a VINSERTI64X2 zmm24{k5}{z}, zmm24, xmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000022CA 6223bdc53844db100a VINSERTI64X2 zmm24{k5}{z}, zmm24, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000022D3 6223bdc53844dbf00a VINSERTI64X2 zmm24{k5}{z}, zmm24, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 2 + Exception class: EVEX, exception type: E6NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000022DC c5c156d0 VORPD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000022E0 c5c15613 VORPD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000022E4 62f1c5185613 VORPD xmm2, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +00000000000022EA c4a1415694db00010000 VORPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000022F4 c4a1415694db00ffffff VORPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000022FE 62f1c50d56d0 VORPD xmm2{k5}, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002304 62f1c50d5613 VORPD xmm2{k5}, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000230A 62f1c51d5613 VORPD xmm2{k5}, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000002310 62b1c50d5654db10 VORPD xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000002318 62b1c50d5654dbf0 VORPD xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000002320 62f1c58856d0 VORPD xmm2, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002326 62f1c5885613 VORPD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000232C 62f1c5985613 VORPD xmm2, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000002332 62b1c5885654db10 VORPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000233A 62b1c5885654dbf0 VORPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000002342 62f1c58d56d0 VORPD xmm2{k5}{z}, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002348 62f1c58d5613 VORPD xmm2{k5}{z}, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000234E 62f1c59d5613 VORPD xmm2{k5}{z}, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000002354 62b1c58d5654db10 VORPD xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000235C 62b1c58d5654dbf0 VORPD xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000002364 62c1952856c7 VORPD ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000236A 62e195285603 VORPD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000002370 62e195385603 VORPD ymm16, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000002376 62a195285644db08 VORPD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000237E 62a195285644dbf8 VORPD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000002386 62c1952d56c7 VORPD ymm16{k5}, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000238C 62e1952d5603 VORPD ymm16{k5}, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000002392 62e1953d5603 VORPD ymm16{k5}, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000002398 62a1952d5644db08 VORPD ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000023A0 62a1952d5644dbf8 VORPD ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000023A8 62c195a856c7 VORPD ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000023AE 62e195a85603 VORPD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000023B4 62e195b85603 VORPD ymm16, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +00000000000023BA 62a195a85644db08 VORPD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000023C2 62a195a85644dbf8 VORPD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000023CA 62c195ad56c7 VORPD ymm16{k5}{z}, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000023D0 62e195ad5603 VORPD ymm16{k5}{z}, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000023D6 62e195bd5603 VORPD ymm16{k5}{z}, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +00000000000023DC 62a195ad5644db08 VORPD ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000023E4 62a195ad5644dbf8 VORPD ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000023EC 6201bd4056c7 VORPD zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000023F2 6261bd405603 VORPD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000023F8 6261bd505603 VORPD zmm24, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +00000000000023FE 6221bd405644db04 VORPD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000002406 6221bd405644dbfc VORPD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000240E 6201bd4556c7 VORPD zmm24{k5}, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000002414 6261bd455603 VORPD zmm24{k5}, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000241A 6261bd555603 VORPD zmm24{k5}, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000002420 6221bd455644db04 VORPD zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000002428 6221bd455644dbfc VORPD zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000002430 6201bdc056c7 VORPD zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000002436 6261bdc05603 VORPD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000243C 6261bdd05603 VORPD zmm24, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000002442 6221bdc05644db04 VORPD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000244A 6221bdc05644dbfc VORPD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000002452 6201bdc556c7 VORPD zmm24{k5}{z}, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000002458 6261bdc55603 VORPD zmm24{k5}{z}, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000245E 6261bdd55603 VORPD zmm24{k5}{z}, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000002464 6221bdc55644db04 VORPD zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000246C 6221bdc55644dbfc VORPD zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000002474 c5c056d0 VORPS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002478 c5c05613 VORPS xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000247C 62f144185613 VORPS xmm2, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000002482 c4a1405694db00010000 VORPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000248C c4a1405694db00ffffff VORPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000002496 62f1440d56d0 VORPS xmm2{k5}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000249C 62f1440d5613 VORPS xmm2{k5}, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000024A2 62f1441d5613 VORPS xmm2{k5}, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +00000000000024A8 62b1440d5654db10 VORPS xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000024B0 62b1440d5654dbf0 VORPS xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000024B8 62f1448856d0 VORPS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000024BE 62f144885613 VORPS xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000024C4 62f144985613 VORPS xmm2, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +00000000000024CA 62b144885654db10 VORPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000024D2 62b144885654dbf0 VORPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000024DA 62f1448d56d0 VORPS xmm2{k5}{z}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000024E0 62f1448d5613 VORPS xmm2{k5}{z}, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000024E6 62f1449d5613 VORPS xmm2{k5}{z}, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +00000000000024EC 62b1448d5654db10 VORPS xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000024F4 62b1448d5654dbf0 VORPS xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000024FC 62c1142856c7 VORPS ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000002502 62e114285603 VORPS ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000002508 62e114385603 VORPS ymm16, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +000000000000250E 62a114285644db08 VORPS ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000002516 62a114285644dbf8 VORPS ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000251E 62c1142d56c7 VORPS ymm16{k5}, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000002524 62e1142d5603 VORPS ymm16{k5}, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000252A 62e1143d5603 VORPS ymm16{k5}, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +0000000000002530 62a1142d5644db08 VORPS ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000002538 62a1142d5644dbf8 VORPS ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000002540 62c114a856c7 VORPS ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000002546 62e114a85603 VORPS ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000254C 62e114b85603 VORPS ymm16, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +0000000000002552 62a114a85644db08 VORPS ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000255A 62a114a85644dbf8 VORPS ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000002562 62c114ad56c7 VORPS ymm16{k5}{z}, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000002568 62e114ad5603 VORPS ymm16{k5}{z}, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000256E 62e114bd5603 VORPS ymm16{k5}{z}, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +0000000000002574 62a114ad5644db08 VORPS ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000257C 62a114ad5644dbf8 VORPS ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000002584 62013c4056c7 VORPS zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000258A 62613c405603 VORPS zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000002590 62613c505603 VORPS zmm24, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000002596 62213c405644db04 VORPS zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000259E 62213c405644dbfc VORPS zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000025A6 62013c4556c7 VORPS zmm24{k5}, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000025AC 62613c455603 VORPS zmm24{k5}, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000025B2 62613c555603 VORPS zmm24{k5}, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +00000000000025B8 62213c455644db04 VORPS zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000025C0 62213c455644dbfc VORPS zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000025C8 62013cc056c7 VORPS zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000025CE 62613cc05603 VORPS zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000025D4 62613cd05603 VORPS zmm24, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +00000000000025DA 62213cc05644db04 VORPS zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000025E2 62213cc05644dbfc VORPS zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000025EA 62013cc556c7 VORPS zmm24{k5}{z}, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000025F0 62613cc55603 VORPS zmm24{k5}{z}, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000025F6 62613cd55603 VORPS zmm24{k5}{z}, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +00000000000025FC 62213cc55644db04 VORPS zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000002604 62213cc55644dbfc VORPS zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000260C c4e37916d10a VPEXTRD ecx, xmm2, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002612 c4e37916d10a VPEXTRD ecx, xmm2, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002618 c4e37916130a VPEXTRD dword ptr [rbx], xmm2, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000261E c4e3791694f3000100000a VPEXTRD dword ptr [rbx+rsi*8+0x100], xmm2, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002629 c4e3f916d10a VPEXTRQ rcx, xmm2, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000262F c4e3f916130a VPEXTRQ qword ptr [rbx], xmm2, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002635 c4e3f91694f3000100000a VPEXTRQ qword ptr [rbx+rsi*8+0x100], xmm2, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002640 c4e34122d10a VPINSRD xmm2, xmm7, ecx, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002646 c4e34122130a VPINSRD xmm2, xmm7, dword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000264C c4e3412294f3000100000a VPINSRD xmm2, xmm7, dword ptr [rbx+rsi*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002657 c4e3c122d10a VPINSRQ xmm2, xmm7, rcx, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000265D c4e3c122130a VPINSRQ xmm2, xmm7, qword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002663 c4e3c12294f3000100000a VPINSRQ xmm2, xmm7, qword ptr [rbx+rsi*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: AVX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 8, Displacement: 0x0000000000000100, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000266E 62f27e0839d8 VPMOVD2M k3, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: None + Exception class: EVEX, exception type: E7NM + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002674 62d27e2839df VPMOVD2M k3, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: None + Exception class: EVEX, exception type: E7NM + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000267A 62927e4839df VPMOVD2M k3, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: None + Exception class: EVEX, exception type: E7NM + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000002680 62f27e0838d1 VPMOVM2D xmm2, k1 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: None + Exception class: EVEX, exception type: E7NM + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Mask, RegSize: 8, RegId: 1, RegCount: 1 + +0000000000002686 62e27e2838c1 VPMOVM2D ymm16, k1 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: None + Exception class: EVEX, exception type: E7NM + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Mask, RegSize: 8, RegId: 1, RegCount: 1 + +000000000000268C 62627e4838c1 VPMOVM2D zmm24, k1 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: None + Exception class: EVEX, exception type: E7NM + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Mask, RegSize: 8, RegId: 1, RegCount: 1 + +0000000000002692 62f2fe0838d1 VPMOVM2Q xmm2, k1 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: None + Exception class: EVEX, exception type: E7NM + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Mask, RegSize: 8, RegId: 1, RegCount: 1 + +0000000000002698 62e2fe2838c1 VPMOVM2Q ymm16, k1 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: None + Exception class: EVEX, exception type: E7NM + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Mask, RegSize: 8, RegId: 1, RegCount: 1 + +000000000000269E 6262fe4838c1 VPMOVM2Q zmm24, k1 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: None + Exception class: EVEX, exception type: E7NM + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Mask, RegSize: 8, RegId: 1, RegCount: 1 + +00000000000026A4 62f2fe0839d8 VPMOVQ2M k3, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: None + Exception class: EVEX, exception type: E7NM + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000026AA 62d2fe2839df VPMOVQ2M k3, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: None + Exception class: EVEX, exception type: E7NM + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000026B0 6292fe4839df VPMOVQ2M k3, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: None + Exception class: EVEX, exception type: E7NM + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000026B6 62f2c50840d0 VPMULLQ xmm2, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000026BC 62f2c5084013 VPMULLQ xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000026C2 62f2c5184013 VPMULLQ xmm2, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +00000000000026C8 62b2c5084054db10 VPMULLQ xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000026D0 62b2c5084054dbf0 VPMULLQ xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000026D8 62f2c50d40d0 VPMULLQ xmm2{k5}, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000026DE 62f2c50d4013 VPMULLQ xmm2{k5}, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000026E4 62f2c51d4013 VPMULLQ xmm2{k5}, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +00000000000026EA 62b2c50d4054db10 VPMULLQ xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000026F2 62b2c50d4054dbf0 VPMULLQ xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000026FA 62f2c58840d0 VPMULLQ xmm2, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002700 62f2c5884013 VPMULLQ xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002706 62f2c5984013 VPMULLQ xmm2, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +000000000000270C 62b2c5884054db10 VPMULLQ xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000002714 62b2c5884054dbf0 VPMULLQ xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000271C 62f2c58d40d0 VPMULLQ xmm2{k5}{z}, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000002722 62f2c58d4013 VPMULLQ xmm2{k5}{z}, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000002728 62f2c59d4013 VPMULLQ xmm2{k5}{z}, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +000000000000272E 62b2c58d4054db10 VPMULLQ xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000002736 62b2c58d4054dbf0 VPMULLQ xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000273E 62c2952840c7 VPMULLQ ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000002744 62e295284003 VPMULLQ ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000274A 62e295384003 VPMULLQ ymm16, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000002750 62a295284044db08 VPMULLQ ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000002758 62a295284044dbf8 VPMULLQ ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000002760 62c2952d40c7 VPMULLQ ymm16{k5}, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000002766 62e2952d4003 VPMULLQ ymm16{k5}, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000276C 62e2953d4003 VPMULLQ ymm16{k5}, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000002772 62a2952d4044db08 VPMULLQ ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000277A 62a2952d4044dbf8 VPMULLQ ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000002782 62c295a840c7 VPMULLQ ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000002788 62e295a84003 VPMULLQ ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000278E 62e295b84003 VPMULLQ ymm16, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000002794 62a295a84044db08 VPMULLQ ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000279C 62a295a84044dbf8 VPMULLQ ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000027A4 62c295ad40c7 VPMULLQ ymm16{k5}{z}, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000027AA 62e295ad4003 VPMULLQ ymm16{k5}{z}, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000027B0 62e295bd4003 VPMULLQ ymm16{k5}{z}, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +00000000000027B6 62a295ad4044db08 VPMULLQ ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000027BE 62a295ad4044dbf8 VPMULLQ ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000027C6 6202bd4040c7 VPMULLQ zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000027CC 6262bd404003 VPMULLQ zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000027D2 6262bd504003 VPMULLQ zmm24, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +00000000000027D8 6222bd404044db04 VPMULLQ zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000027E0 6222bd404044dbfc VPMULLQ zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000027E8 6202bd4540c7 VPMULLQ zmm24{k5}, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000027EE 6262bd454003 VPMULLQ zmm24{k5}, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000027F4 6262bd554003 VPMULLQ zmm24{k5}, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +00000000000027FA 6222bd454044db04 VPMULLQ zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000002802 6222bd454044dbfc VPMULLQ zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000280A 6202bdc040c7 VPMULLQ zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000002810 6262bdc04003 VPMULLQ zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000002816 6262bdd04003 VPMULLQ zmm24, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +000000000000281C 6222bdc04044db04 VPMULLQ zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000002824 6222bdc04044dbfc VPMULLQ zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000282C 6202bdc540c7 VPMULLQ zmm24{k5}{z}, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000002832 6262bdc54003 VPMULLQ zmm24{k5}{z}, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000002838 6262bdd54003 VPMULLQ zmm24{k5}{z}, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +000000000000283E 6222bdc54044db04 VPMULLQ zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000002846 6222bdc54044dbfc VPMULLQ zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000284E 62f3c50850d00a VRANGEPD xmm2, xmm7, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002855 62f3c50850130a VRANGEPD xmm2, xmm7, xmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000285C 62f3c51850130a VRANGEPD xmm2, xmm7, qword ptr [rbx]{1to2}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002863 62b3c5085054db100a VRANGEPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000286C 62b3c5085054dbf00a VRANGEPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002875 62f3c50d50d00a VRANGEPD xmm2{k5}, xmm7, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000287C 62f3c50d50130a VRANGEPD xmm2{k5}, xmm7, xmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002883 62f3c51d50130a VRANGEPD xmm2{k5}, xmm7, qword ptr [rbx]{1to2}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000288A 62b3c50d5054db100a VRANGEPD xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002893 62b3c50d5054dbf00a VRANGEPD xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000289C 62f3c58850d00a VRANGEPD xmm2, xmm7, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000028A3 62f3c58850130a VRANGEPD xmm2, xmm7, xmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000028AA 62f3c59850130a VRANGEPD xmm2, xmm7, qword ptr [rbx]{1to2}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000028B1 62b3c5885054db100a VRANGEPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000028BA 62b3c5885054dbf00a VRANGEPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000028C3 62f3c58d50d00a VRANGEPD xmm2{k5}{z}, xmm7, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000028CA 62f3c58d50130a VRANGEPD xmm2{k5}{z}, xmm7, xmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000028D1 62f3c59d50130a VRANGEPD xmm2{k5}{z}, xmm7, qword ptr [rbx]{1to2}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000028D8 62b3c58d5054db100a VRANGEPD xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000028E1 62b3c58d5054dbf00a VRANGEPD xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000028EA 62c3952850c70a VRANGEPD ymm16, ymm13, ymm15, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000028F1 62e3952850030a VRANGEPD ymm16, ymm13, ymmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000028F8 62e3953850030a VRANGEPD ymm16, ymm13, qword ptr [rbx]{1to4}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000028FF 62a395285044db080a VRANGEPD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002908 62a395285044dbf80a VRANGEPD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002911 62c3952d50c70a VRANGEPD ymm16{k5}, ymm13, ymm15, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002918 62e3952d50030a VRANGEPD ymm16{k5}, ymm13, ymmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000291F 62e3953d50030a VRANGEPD ymm16{k5}, ymm13, qword ptr [rbx]{1to4}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002926 62a3952d5044db080a VRANGEPD ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000292F 62a3952d5044dbf80a VRANGEPD ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002938 62c395a850c70a VRANGEPD ymm16, ymm13, ymm15, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000293F 62e395a850030a VRANGEPD ymm16, ymm13, ymmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002946 62e395b850030a VRANGEPD ymm16, ymm13, qword ptr [rbx]{1to4}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000294D 62a395a85044db080a VRANGEPD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002956 62a395a85044dbf80a VRANGEPD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000295F 62c395ad50c70a VRANGEPD ymm16{k5}{z}, ymm13, ymm15, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002966 62e395ad50030a VRANGEPD ymm16{k5}{z}, ymm13, ymmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000296D 62e395bd50030a VRANGEPD ymm16{k5}{z}, ymm13, qword ptr [rbx]{1to4}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002974 62a395ad5044db080a VRANGEPD ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000297D 62a395ad5044dbf80a VRANGEPD ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002986 6203bd4050c70a VRANGEPD zmm24, zmm24, zmm31, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000298D 6263bd4050030a VRANGEPD zmm24, zmm24, zmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002994 6263bd5050030a VRANGEPD zmm24, zmm24, qword ptr [rbx]{1to8}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000299B 6223bd405044db040a VRANGEPD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000029A4 6223bd405044dbfc0a VRANGEPD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000029AD 6203bd4550c70a VRANGEPD zmm24{k5}, zmm24, zmm31, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000029B4 6263bd4550030a VRANGEPD zmm24{k5}, zmm24, zmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000029BB 6263bd5550030a VRANGEPD zmm24{k5}, zmm24, qword ptr [rbx]{1to8}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000029C2 6223bd455044db040a VRANGEPD zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000029CB 6223bd455044dbfc0a VRANGEPD zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000029D4 6203bdc050c70a VRANGEPD zmm24, zmm24, zmm31, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000029DB 6263bdc050030a VRANGEPD zmm24, zmm24, zmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000029E2 6263bdd050030a VRANGEPD zmm24, zmm24, qword ptr [rbx]{1to8}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000029E9 6223bdc05044db040a VRANGEPD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000029F2 6223bdc05044dbfc0a VRANGEPD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000029FB 6203bdc550c70a VRANGEPD zmm24{k5}{z}, zmm24, zmm31, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002A02 6263bdc550030a VRANGEPD zmm24{k5}{z}, zmm24, zmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002A09 6263bdd550030a VRANGEPD zmm24{k5}{z}, zmm24, qword ptr [rbx]{1to8}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002A10 6223bdc55044db040a VRANGEPD zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002A19 6223bdc55044dbfc0a VRANGEPD zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002A22 62f3450850d00a VRANGEPS xmm2, xmm7, xmm0, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002A29 62f3450850130a VRANGEPS xmm2, xmm7, xmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002A30 62f3451850130a VRANGEPS xmm2, xmm7, dword ptr [rbx]{1to4}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002A37 62b345085054db100a VRANGEPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002A40 62b345085054dbf00a VRANGEPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002A49 62f3450d50d00a VRANGEPS xmm2{k5}, xmm7, xmm0, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002A50 62f3450d50130a VRANGEPS xmm2{k5}, xmm7, xmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002A57 62f3451d50130a VRANGEPS xmm2{k5}, xmm7, dword ptr [rbx]{1to4}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002A5E 62b3450d5054db100a VRANGEPS xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002A67 62b3450d5054dbf00a VRANGEPS xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002A70 62f3458850d00a VRANGEPS xmm2, xmm7, xmm0, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002A77 62f3458850130a VRANGEPS xmm2, xmm7, xmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002A7E 62f3459850130a VRANGEPS xmm2, xmm7, dword ptr [rbx]{1to4}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002A85 62b345885054db100a VRANGEPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002A8E 62b345885054dbf00a VRANGEPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002A97 62f3458d50d00a VRANGEPS xmm2{k5}{z}, xmm7, xmm0, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002A9E 62f3458d50130a VRANGEPS xmm2{k5}{z}, xmm7, xmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002AA5 62f3459d50130a VRANGEPS xmm2{k5}{z}, xmm7, dword ptr [rbx]{1to4}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002AAC 62b3458d5054db100a VRANGEPS xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002AB5 62b3458d5054dbf00a VRANGEPS xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002ABE 62c3152850c70a VRANGEPS ymm16, ymm13, ymm15, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002AC5 62e3152850030a VRANGEPS ymm16, ymm13, ymmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002ACC 62e3153850030a VRANGEPS ymm16, ymm13, dword ptr [rbx]{1to8}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002AD3 62a315285044db080a VRANGEPS ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002ADC 62a315285044dbf80a VRANGEPS ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002AE5 62c3152d50c70a VRANGEPS ymm16{k5}, ymm13, ymm15, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002AEC 62e3152d50030a VRANGEPS ymm16{k5}, ymm13, ymmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002AF3 62e3153d50030a VRANGEPS ymm16{k5}, ymm13, dword ptr [rbx]{1to8}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002AFA 62a3152d5044db080a VRANGEPS ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002B03 62a3152d5044dbf80a VRANGEPS ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002B0C 62c315a850c70a VRANGEPS ymm16, ymm13, ymm15, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002B13 62e315a850030a VRANGEPS ymm16, ymm13, ymmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002B1A 62e315b850030a VRANGEPS ymm16, ymm13, dword ptr [rbx]{1to8}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002B21 62a315a85044db080a VRANGEPS ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002B2A 62a315a85044dbf80a VRANGEPS ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002B33 62c315ad50c70a VRANGEPS ymm16{k5}{z}, ymm13, ymm15, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002B3A 62e315ad50030a VRANGEPS ymm16{k5}{z}, ymm13, ymmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002B41 62e315bd50030a VRANGEPS ymm16{k5}{z}, ymm13, dword ptr [rbx]{1to8}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002B48 62a315ad5044db080a VRANGEPS ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002B51 62a315ad5044dbf80a VRANGEPS ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002B5A 62033d4050c70a VRANGEPS zmm24, zmm24, zmm31, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002B61 62633d4050030a VRANGEPS zmm24, zmm24, zmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002B68 62633d5050030a VRANGEPS zmm24, zmm24, dword ptr [rbx]{1to16}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002B6F 62233d405044db040a VRANGEPS zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002B78 62233d405044dbfc0a VRANGEPS zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002B81 62033d4550c70a VRANGEPS zmm24{k5}, zmm24, zmm31, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002B88 62633d4550030a VRANGEPS zmm24{k5}, zmm24, zmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002B8F 62633d5550030a VRANGEPS zmm24{k5}, zmm24, dword ptr [rbx]{1to16}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002B96 62233d455044db040a VRANGEPS zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002B9F 62233d455044dbfc0a VRANGEPS zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002BA8 62033dc050c70a VRANGEPS zmm24, zmm24, zmm31, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002BAF 62633dc050030a VRANGEPS zmm24, zmm24, zmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002BB6 62633dd050030a VRANGEPS zmm24, zmm24, dword ptr [rbx]{1to16}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002BBD 62233dc05044db040a VRANGEPS zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002BC6 62233dc05044dbfc0a VRANGEPS zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002BCF 62033dc550c70a VRANGEPS zmm24{k5}{z}, zmm24, zmm31, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002BD6 62633dc550030a VRANGEPS zmm24{k5}{z}, zmm24, zmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002BDD 62633dd550030a VRANGEPS zmm24{k5}{z}, zmm24, dword ptr [rbx]{1to16}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002BE4 62233dc55044db040a VRANGEPS zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002BED 62233dc55044dbfc0a VRANGEPS zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002BF6 62f3c50851d00a VRANGESD xmm2, xmm7, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002BFD 62f3c50851130a VRANGESD xmm2, xmm7, qword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002C04 62b3c5085154db200a VRANGESD xmm2, xmm7, qword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002C0D 62b3c5085154dbe00a VRANGESD xmm2, xmm7, qword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002C16 62f3c50d51d00a VRANGESD xmm2{k5}, xmm7, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002C1D 62f3c50d51130a VRANGESD xmm2{k5}, xmm7, qword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002C24 62b3c50d5154db200a VRANGESD xmm2{k5}, xmm7, qword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002C2D 62b3c50d5154dbe00a VRANGESD xmm2{k5}, xmm7, qword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002C36 62f3c58851d00a VRANGESD xmm2, xmm7, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002C3D 62f3c58851130a VRANGESD xmm2, xmm7, qword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002C44 62b3c5885154db200a VRANGESD xmm2, xmm7, qword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002C4D 62b3c5885154dbe00a VRANGESD xmm2, xmm7, qword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002C56 62f3c58d51d00a VRANGESD xmm2{k5}{z}, xmm7, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002C5D 62f3c58d51130a VRANGESD xmm2{k5}{z}, xmm7, qword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002C64 62b3c58d5154db200a VRANGESD xmm2{k5}{z}, xmm7, qword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002C6D 62b3c58d5154dbe00a VRANGESD xmm2{k5}{z}, xmm7, qword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002C76 62f3450851d00a VRANGESS xmm2, xmm7, xmm0, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002C7D 62f3450851130a VRANGESS xmm2, xmm7, dword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002C84 62b345085154db400a VRANGESS xmm2, xmm7, dword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000040, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002C8D 62b345085154dbc00a VRANGESS xmm2, xmm7, dword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffc0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002C96 62f3450d51d00a VRANGESS xmm2{k5}, xmm7, xmm0, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002C9D 62f3450d51130a VRANGESS xmm2{k5}, xmm7, dword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002CA4 62b3450d5154db400a VRANGESS xmm2{k5}, xmm7, dword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000040, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002CAD 62b3450d5154dbc00a VRANGESS xmm2{k5}, xmm7, dword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffc0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002CB6 62f3458851d00a VRANGESS xmm2, xmm7, xmm0, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002CBD 62f3458851130a VRANGESS xmm2, xmm7, dword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002CC4 62b345885154db400a VRANGESS xmm2, xmm7, dword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000040, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002CCD 62b345885154dbc00a VRANGESS xmm2, xmm7, dword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffc0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002CD6 62f3458d51d00a VRANGESS xmm2{k5}{z}, xmm7, xmm0, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002CDD 62f3458d51130a VRANGESS xmm2{k5}{z}, xmm7, dword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002CE4 62b3458d5154db400a VRANGESS xmm2{k5}{z}, xmm7, dword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000040, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002CED 62b3458d5154dbc00a VRANGESS xmm2{k5}{z}, xmm7, dword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffc0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002CF6 62f3fd0856d00a VREDUCEPD xmm2, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002CFD 62f3fd0856130a VREDUCEPD xmm2, xmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D04 62f3fd1856130a VREDUCEPD xmm2, qword ptr [rbx]{1to2}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D0B 62b3fd085654db100a VREDUCEPD xmm2, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D14 62b3fd085654dbf00a VREDUCEPD xmm2, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D1D 62f3fd0d56d00a VREDUCEPD xmm2{k5}, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D24 62f3fd0d56130a VREDUCEPD xmm2{k5}, xmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D2B 62f3fd1d56130a VREDUCEPD xmm2{k5}, qword ptr [rbx]{1to2}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D32 62b3fd0d5654db100a VREDUCEPD xmm2{k5}, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D3B 62b3fd0d5654dbf00a VREDUCEPD xmm2{k5}, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D44 62f3fd8856d00a VREDUCEPD xmm2, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D4B 62f3fd8856130a VREDUCEPD xmm2, xmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D52 62f3fd9856130a VREDUCEPD xmm2, qword ptr [rbx]{1to2}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D59 62b3fd885654db100a VREDUCEPD xmm2, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D62 62b3fd885654dbf00a VREDUCEPD xmm2, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D6B 62f3fd8d56d00a VREDUCEPD xmm2{k5}{z}, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D72 62f3fd8d56130a VREDUCEPD xmm2{k5}{z}, xmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D79 62f3fd9d56130a VREDUCEPD xmm2{k5}{z}, qword ptr [rbx]{1to2}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D80 62b3fd8d5654db100a VREDUCEPD xmm2{k5}{z}, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D89 62b3fd8d5654dbf00a VREDUCEPD xmm2{k5}{z}, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D92 62c3fd2856c70a VREDUCEPD ymm16, ymm15, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002D99 62e3fd2856030a VREDUCEPD ymm16, ymmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002DA0 62e3fd3856030a VREDUCEPD ymm16, qword ptr [rbx]{1to4}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002DA7 62a3fd285644db080a VREDUCEPD ymm16, ymmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002DB0 62a3fd285644dbf80a VREDUCEPD ymm16, ymmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002DB9 62c3fd2d56c70a VREDUCEPD ymm16{k5}, ymm15, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002DC0 62e3fd2d56030a VREDUCEPD ymm16{k5}, ymmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002DC7 62e3fd3d56030a VREDUCEPD ymm16{k5}, qword ptr [rbx]{1to4}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002DCE 62a3fd2d5644db080a VREDUCEPD ymm16{k5}, ymmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002DD7 62a3fd2d5644dbf80a VREDUCEPD ymm16{k5}, ymmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002DE0 62c3fda856c70a VREDUCEPD ymm16, ymm15, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002DE7 62e3fda856030a VREDUCEPD ymm16, ymmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002DEE 62e3fdb856030a VREDUCEPD ymm16, qword ptr [rbx]{1to4}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002DF5 62a3fda85644db080a VREDUCEPD ymm16, ymmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002DFE 62a3fda85644dbf80a VREDUCEPD ymm16, ymmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002E07 62c3fdad56c70a VREDUCEPD ymm16{k5}{z}, ymm15, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002E0E 62e3fdad56030a VREDUCEPD ymm16{k5}{z}, ymmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002E15 62e3fdbd56030a VREDUCEPD ymm16{k5}{z}, qword ptr [rbx]{1to4}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002E1C 62a3fdad5644db080a VREDUCEPD ymm16{k5}{z}, ymmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002E25 62a3fdad5644dbf80a VREDUCEPD ymm16{k5}{z}, ymmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002E2E 6203fd4856c70a VREDUCEPD zmm24, zmm31, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002E35 6263fd4856030a VREDUCEPD zmm24, zmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002E3C 6263fd5856030a VREDUCEPD zmm24, qword ptr [rbx]{1to8}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002E43 6223fd485644db040a VREDUCEPD zmm24, zmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002E4C 6223fd485644dbfc0a VREDUCEPD zmm24, zmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002E55 6203fd4d56c70a VREDUCEPD zmm24{k5}, zmm31, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002E5C 6263fd4d56030a VREDUCEPD zmm24{k5}, zmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002E63 6263fd5d56030a VREDUCEPD zmm24{k5}, qword ptr [rbx]{1to8}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002E6A 6223fd4d5644db040a VREDUCEPD zmm24{k5}, zmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002E73 6223fd4d5644dbfc0a VREDUCEPD zmm24{k5}, zmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002E7C 6203fdc856c70a VREDUCEPD zmm24, zmm31, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002E83 6263fdc856030a VREDUCEPD zmm24, zmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002E8A 6263fdd856030a VREDUCEPD zmm24, qword ptr [rbx]{1to8}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002E91 6223fdc85644db040a VREDUCEPD zmm24, zmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002E9A 6223fdc85644dbfc0a VREDUCEPD zmm24, zmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002EA3 6203fdcd56c70a VREDUCEPD zmm24{k5}{z}, zmm31, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002EAA 6263fdcd56030a VREDUCEPD zmm24{k5}{z}, zmmword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002EB1 6263fddd56030a VREDUCEPD zmm24{k5}{z}, qword ptr [rbx]{1to8}, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002EB8 6223fdcd5644db040a VREDUCEPD zmm24{k5}{z}, zmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002EC1 6223fdcd5644dbfc0a VREDUCEPD zmm24{k5}{z}, zmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002ECA 62f37d0856d00a VREDUCEPS xmm2, xmm0, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002ED1 62f37d0856130a VREDUCEPS xmm2, xmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002ED8 62f37d1856130a VREDUCEPS xmm2, dword ptr [rbx]{1to4}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002EDF 62b37d085654db100a VREDUCEPS xmm2, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002EE8 62b37d085654dbf00a VREDUCEPS xmm2, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002EF1 62f37d0d56d00a VREDUCEPS xmm2{k5}, xmm0, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002EF8 62f37d0d56130a VREDUCEPS xmm2{k5}, xmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002EFF 62f37d1d56130a VREDUCEPS xmm2{k5}, dword ptr [rbx]{1to4}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002F06 62b37d0d5654db100a VREDUCEPS xmm2{k5}, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002F0F 62b37d0d5654dbf00a VREDUCEPS xmm2{k5}, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002F18 62f37d8856d00a VREDUCEPS xmm2, xmm0, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002F1F 62f37d8856130a VREDUCEPS xmm2, xmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002F26 62f37d9856130a VREDUCEPS xmm2, dword ptr [rbx]{1to4}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002F2D 62b37d885654db100a VREDUCEPS xmm2, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002F36 62b37d885654dbf00a VREDUCEPS xmm2, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002F3F 62f37d8d56d00a VREDUCEPS xmm2{k5}{z}, xmm0, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002F46 62f37d8d56130a VREDUCEPS xmm2{k5}{z}, xmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002F4D 62f37d9d56130a VREDUCEPS xmm2{k5}{z}, dword ptr [rbx]{1to4}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002F54 62b37d8d5654db100a VREDUCEPS xmm2{k5}{z}, xmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002F5D 62b37d8d5654dbf00a VREDUCEPS xmm2{k5}{z}, xmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002F66 62c37d2856c70a VREDUCEPS ymm16, ymm15, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002F6D 62e37d2856030a VREDUCEPS ymm16, ymmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002F74 62e37d3856030a VREDUCEPS ymm16, dword ptr [rbx]{1to8}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002F7B 62a37d285644db080a VREDUCEPS ymm16, ymmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002F84 62a37d285644dbf80a VREDUCEPS ymm16, ymmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002F8D 62c37d2d56c70a VREDUCEPS ymm16{k5}, ymm15, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002F94 62e37d2d56030a VREDUCEPS ymm16{k5}, ymmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002F9B 62e37d3d56030a VREDUCEPS ymm16{k5}, dword ptr [rbx]{1to8}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002FA2 62a37d2d5644db080a VREDUCEPS ymm16{k5}, ymmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002FAB 62a37d2d5644dbf80a VREDUCEPS ymm16{k5}, ymmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002FB4 62c37da856c70a VREDUCEPS ymm16, ymm15, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002FBB 62e37da856030a VREDUCEPS ymm16, ymmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002FC2 62e37db856030a VREDUCEPS ymm16, dword ptr [rbx]{1to8}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002FC9 62a37da85644db080a VREDUCEPS ymm16, ymmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002FD2 62a37da85644dbf80a VREDUCEPS ymm16, ymmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002FDB 62c37dad56c70a VREDUCEPS ymm16{k5}{z}, ymm15, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002FE2 62e37dad56030a VREDUCEPS ymm16{k5}{z}, ymmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002FE9 62e37dbd56030a VREDUCEPS ymm16{k5}{z}, dword ptr [rbx]{1to8}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002FF0 62a37dad5644db080a VREDUCEPS ymm16{k5}{z}, ymmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000002FF9 62a37dad5644dbf80a VREDUCEPS ymm16{k5}{z}, ymmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003002 62037d4856c70a VREDUCEPS zmm24, zmm31, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003009 62637d4856030a VREDUCEPS zmm24, zmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003010 62637d5856030a VREDUCEPS zmm24, dword ptr [rbx]{1to16}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003017 62237d485644db040a VREDUCEPS zmm24, zmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003020 62237d485644dbfc0a VREDUCEPS zmm24, zmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003029 62037d4d56c70a VREDUCEPS zmm24{k5}, zmm31, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003030 62637d4d56030a VREDUCEPS zmm24{k5}, zmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003037 62637d5d56030a VREDUCEPS zmm24{k5}, dword ptr [rbx]{1to16}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000303E 62237d4d5644db040a VREDUCEPS zmm24{k5}, zmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003047 62237d4d5644dbfc0a VREDUCEPS zmm24{k5}, zmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003050 62037dc856c70a VREDUCEPS zmm24, zmm31, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003057 62637dc856030a VREDUCEPS zmm24, zmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000305E 62637dd856030a VREDUCEPS zmm24, dword ptr [rbx]{1to16}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003065 62237dc85644db040a VREDUCEPS zmm24, zmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000306E 62237dc85644dbfc0a VREDUCEPS zmm24, zmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003077 62037dcd56c70a VREDUCEPS zmm24{k5}{z}, zmm31, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000307E 62637dcd56030a VREDUCEPS zmm24{k5}{z}, zmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003085 62637ddd56030a VREDUCEPS zmm24{k5}{z}, dword ptr [rbx]{1to16}, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000308C 62237dcd5644db040a VREDUCEPS zmm24{k5}{z}, zmmword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003095 62237dcd5644dbfc0a VREDUCEPS zmm24{k5}{z}, zmmword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000309E 62f3c50857d00a VREDUCESD xmm2, xmm7, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000030A5 62f3c50857130a VREDUCESD xmm2, xmm7, qword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000030AC 62b3c5085754db200a VREDUCESD xmm2, xmm7, qword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000030B5 62b3c5085754dbe00a VREDUCESD xmm2, xmm7, qword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000030BE 62f3c50d57d00a VREDUCESD xmm2{k5}, xmm7, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000030C5 62f3c50d57130a VREDUCESD xmm2{k5}, xmm7, qword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000030CC 62b3c50d5754db200a VREDUCESD xmm2{k5}, xmm7, qword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000030D5 62b3c50d5754dbe00a VREDUCESD xmm2{k5}, xmm7, qword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000030DE 62f3c58857d00a VREDUCESD xmm2, xmm7, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000030E5 62f3c58857130a VREDUCESD xmm2, xmm7, qword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000030EC 62b3c5885754db200a VREDUCESD xmm2, xmm7, qword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000030F5 62b3c5885754dbe00a VREDUCESD xmm2, xmm7, qword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000030FE 62f3c58d57d00a VREDUCESD xmm2{k5}{z}, xmm7, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003105 62f3c58d57130a VREDUCESD xmm2{k5}{z}, xmm7, qword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000310C 62b3c58d5754db200a VREDUCESD xmm2{k5}{z}, xmm7, qword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003115 62b3c58d5754dbe00a VREDUCESD xmm2{k5}{z}, xmm7, qword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000311E 62f3450857d00a VREDUCESS xmm2, xmm7, xmm0, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003125 62f3450857130a VREDUCESS xmm2, xmm7, dword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000312C 62b345085754db400a VREDUCESS xmm2, xmm7, dword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000040, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003135 62b345085754dbc00a VREDUCESS xmm2, xmm7, dword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffc0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000313E 62f3450d57d00a VREDUCESS xmm2{k5}, xmm7, xmm0, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003145 62f3450d57130a VREDUCESS xmm2{k5}, xmm7, dword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000314C 62b3450d5754db400a VREDUCESS xmm2{k5}, xmm7, dword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000040, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003155 62b3450d5754dbc00a VREDUCESS xmm2{k5}, xmm7, dword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffc0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000315E 62f3458857d00a VREDUCESS xmm2, xmm7, xmm0, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003165 62f3458857130a VREDUCESS xmm2, xmm7, dword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000316C 62b345885754db400a VREDUCESS xmm2, xmm7, dword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000040, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003175 62b345885754dbc00a VREDUCESS xmm2, xmm7, dword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffc0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000317E 62f3458d57d00a VREDUCESS xmm2{k5}{z}, xmm7, xmm0, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003185 62f3458d57130a VREDUCESS xmm2{k5}{z}, xmm7, dword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000318C 62b3458d5754db400a VREDUCESS xmm2{k5}{z}, xmm7, dword ptr [rbx+r11*8+0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000040, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000003195 62b3458d5754dbc00a VREDUCESS xmm2{k5}{z}, xmm7, dword ptr [rbx+r11*8-0x100], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: AVX512, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffc0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000319E c5c157d0 VXORPD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000031A2 c5c15713 VXORPD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000031A6 62f1c5185713 VXORPD xmm2, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +00000000000031AC c4a1415794db00010000 VXORPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +00000000000031B6 c4a1415794db00ffffff VXORPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +00000000000031C0 62f1c50d57d0 VXORPD xmm2{k5}, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000031C6 62f1c50d5713 VXORPD xmm2{k5}, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000031CC 62f1c51d5713 VXORPD xmm2{k5}, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +00000000000031D2 62b1c50d5754db10 VXORPD xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000031DA 62b1c50d5754dbf0 VXORPD xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000031E2 62f1c58857d0 VXORPD xmm2, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000031E8 62f1c5885713 VXORPD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000031EE 62f1c5985713 VXORPD xmm2, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +00000000000031F4 62b1c5885754db10 VXORPD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000031FC 62b1c5885754dbf0 VXORPD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000003204 62f1c58d57d0 VXORPD xmm2{k5}{z}, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000320A 62f1c58d5713 VXORPD xmm2{k5}{z}, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000003210 62f1c59d5713 VXORPD xmm2{k5}{z}, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000003216 62b1c58d5754db10 VXORPD xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000321E 62b1c58d5754dbf0 VXORPD xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000003226 62c1952857c7 VXORPD ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000322C 62e195285703 VXORPD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000003232 62e195385703 VXORPD ymm16, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000003238 62a195285744db08 VXORPD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000003240 62a195285744dbf8 VXORPD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000003248 62c1952d57c7 VXORPD ymm16{k5}, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000324E 62e1952d5703 VXORPD ymm16{k5}, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000003254 62e1953d5703 VXORPD ymm16{k5}, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +000000000000325A 62a1952d5744db08 VXORPD ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000003262 62a1952d5744dbf8 VXORPD ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000326A 62c195a857c7 VXORPD ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000003270 62e195a85703 VXORPD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000003276 62e195b85703 VXORPD ymm16, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +000000000000327C 62a195a85744db08 VXORPD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000003284 62a195a85744dbf8 VXORPD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000328C 62c195ad57c7 VXORPD ymm16{k5}{z}, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000003292 62e195ad5703 VXORPD ymm16{k5}{z}, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000003298 62e195bd5703 VXORPD ymm16{k5}{z}, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +000000000000329E 62a195ad5744db08 VXORPD ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000032A6 62a195ad5744dbf8 VXORPD ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000032AE 6201bd4057c7 VXORPD zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000032B4 6261bd405703 VXORPD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000032BA 6261bd505703 VXORPD zmm24, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +00000000000032C0 6221bd405744db04 VXORPD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000032C8 6221bd405744dbfc VXORPD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000032D0 6201bd4557c7 VXORPD zmm24{k5}, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000032D6 6261bd455703 VXORPD zmm24{k5}, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000032DC 6261bd555703 VXORPD zmm24{k5}, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +00000000000032E2 6221bd455744db04 VXORPD zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000032EA 6221bd455744dbfc VXORPD zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000032F2 6201bdc057c7 VXORPD zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000032F8 6261bdc05703 VXORPD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000032FE 6261bdd05703 VXORPD zmm24, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000003304 6221bdc05744db04 VXORPD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000330C 6221bdc05744dbfc VXORPD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000003314 6201bdc557c7 VXORPD zmm24{k5}{z}, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000331A 6261bdc55703 VXORPD zmm24{k5}{z}, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000003320 6261bdd55703 VXORPD zmm24{k5}{z}, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000003326 6221bdc55744db04 VXORPD zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000332E 6221bdc55744dbfc VXORPD zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000003336 c5c057d0 VXORPS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000333A c5c05713 VXORPS xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000333E 62f144185713 VXORPS xmm2, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000003344 c4a1405794db00010000 VXORPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000100, + +000000000000334E c4a1405794db00ffffff VXORPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 28 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffff00, + +0000000000003358 62f1440d57d0 VXORPS xmm2{k5}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000335E 62f1440d5713 VXORPS xmm2{k5}, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000003364 62f1441d5713 VXORPS xmm2{k5}, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +000000000000336A 62b1440d5754db10 VXORPS xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000003372 62b1440d5754dbf0 VXORPS xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000337A 62f1448857d0 VXORPS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000003380 62f144885713 VXORPS xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000003386 62f144985713 VXORPS xmm2, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +000000000000338C 62b144885754db10 VXORPS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000003394 62b144885754dbf0 VXORPS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000339C 62f1448d57d0 VXORPS xmm2{k5}{z}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000033A2 62f1448d5713 VXORPS xmm2{k5}{z}, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000033A8 62f1449d5713 VXORPS xmm2{k5}{z}, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +00000000000033AE 62b1448d5754db10 VXORPS xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000033B6 62b1448d5754dbf0 VXORPS xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000033BE 62c1142857c7 VXORPS ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000033C4 62e114285703 VXORPS ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000033CA 62e114385703 VXORPS ymm16, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +00000000000033D0 62a114285744db08 VXORPS ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000033D8 62a114285744dbf8 VXORPS ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000033E0 62c1142d57c7 VXORPS ymm16{k5}, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000033E6 62e1142d5703 VXORPS ymm16{k5}, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000033EC 62e1143d5703 VXORPS ymm16{k5}, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +00000000000033F2 62a1142d5744db08 VXORPS ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000033FA 62a1142d5744dbf8 VXORPS ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000003402 62c114a857c7 VXORPS ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000003408 62e114a85703 VXORPS ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000340E 62e114b85703 VXORPS ymm16, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +0000000000003414 62a114a85744db08 VXORPS ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000341C 62a114a85744dbf8 VXORPS ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000003424 62c114ad57c7 VXORPS ymm16{k5}{z}, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000342A 62e114ad5703 VXORPS ymm16{k5}{z}, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000003430 62e114bd5703 VXORPS ymm16{k5}{z}, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +0000000000003436 62a114ad5744db08 VXORPS ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000343E 62a114ad5744dbf8 VXORPS ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000003446 62013c4057c7 VXORPS zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000344C 62613c405703 VXORPS zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000003452 62613c505703 VXORPS zmm24, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000003458 62213c405744db04 VXORPS zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000003460 62213c405744dbfc VXORPS zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000003468 62013c4557c7 VXORPS zmm24{k5}, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000346E 62613c455703 VXORPS zmm24{k5}, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000003474 62613c555703 VXORPS zmm24{k5}, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +000000000000347A 62213c455744db04 VXORPS zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000003482 62213c455744dbfc VXORPS zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000348A 62013cc057c7 VXORPS zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000003490 62613cc05703 VXORPS zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000003496 62613cd05703 VXORPS zmm24, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +000000000000349C 62213cc05744db04 VXORPS zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000034A4 62213cc05744dbfc VXORPS zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000034AC 62013cc557c7 VXORPS zmm24{k5}{z}, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000034B2 62613cc55703 VXORPS zmm24{k5}{z}, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000034B8 62613cd55703 VXORPS zmm24{k5}{z}, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +00000000000034BE 62213cc55744db04 VXORPS zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000034C6 62213cc55744dbfc VXORPS zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512DQ, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + diff --git a/bddisasm_test/avx512/avx512er_64 b/bddisasm_test/avx512/avx512er_64 new file mode 100644 index 0000000..2098b09 --- /dev/null +++ b/bddisasm_test/avx512/avx512er_64 @@ -0,0 +1 @@ +bHbbbHbbXb"HDb"HDbMbbbMbb]b"MDb"MDbbbbbbb"Db"Dbbbbbbb"Db"Db}Hb}bb}Hbb}Xb"}HDb"}HDb}Mb}bb}Mbb}]b"}MDb"}MDb}b}bb}bb}b"}Db"}Db}b}bb}bb}b"}Db"}DbHbbbHbbXb"HDb"HDbMbbbMbb]b"MDb"MDbbbbbbb"Db"Dbbbbbbb"Db"Db}Hb}bb}Hbb}Xb"}HDb"}HDb}Mb}bb}Mbb}]b"}MDb"}MDb}b}bb}bb}b"}Db"}Db}b}bb}bb}b"}Db"}DbbbbT bTb bb b T b TbňbŘbňbňT bňTbōbŝbōbōT bōTbEbEbEbET@bETbE bEbE bE T@bE TbEbEbEbET@bETbEbEbEbET@bETbHbbbHbbXb"HDb"HDbMbbbMbb]b"MDb"MDbbbbbbb"Db"Dbbbbbbb"Db"Db}Hb}bb}Hbb}Xb"}HDb"}HDb}Mb}bb}Mbb}]b"}MDb"}MDb}b}bb}bb}b"}Db"}Db}b}bb}bb}b"}Db"}DbbbbT bTb bb b T b TbňbŘbňbňT bňTbōbŝbōbōT bōTbEbEbEbET@bETbE bEbE bE T@bE TbEbEbEbET@bETbEbEbEbET@bET \ No newline at end of file diff --git a/bddisasm_test/avx512/avx512er_64.asm b/bddisasm_test/avx512/avx512er_64.asm new file mode 100644 index 0000000..dc0773c --- /dev/null +++ b/bddisasm_test/avx512/avx512er_64.asm @@ -0,0 +1,226 @@ + bits 64 + + vexp2pd zmm24, zmm31 + vexp2pd zmm24, zmm31, {sae} + vexp2pd zmm24, [rbx] + vexp2pd zmm24, [rbx]{1to8} + vexp2pd zmm24, [rbx+r11*8+256] + vexp2pd zmm24, [rbx+r11*8-256] + vexp2pd zmm24{k5}, zmm31 + vexp2pd zmm24{k5}, zmm31, {sae} + vexp2pd zmm24{k5}, [rbx] + vexp2pd zmm24{k5}, [rbx]{1to8} + vexp2pd zmm24{k5}, [rbx+r11*8+256] + vexp2pd zmm24{k5}, [rbx+r11*8-256] + vexp2pd zmm24{z}, zmm31 + vexp2pd zmm24{z}, zmm31, {sae} + vexp2pd zmm24{z}, [rbx] + vexp2pd zmm24{z}, [rbx]{1to8} + vexp2pd zmm24{z}, [rbx+r11*8+256] + vexp2pd zmm24{z}, [rbx+r11*8-256] + vexp2pd zmm24{k5}{z}, zmm31 + vexp2pd zmm24{k5}{z}, zmm31, {sae} + vexp2pd zmm24{k5}{z}, [rbx] + vexp2pd zmm24{k5}{z}, [rbx]{1to8} + vexp2pd zmm24{k5}{z}, [rbx+r11*8+256] + vexp2pd zmm24{k5}{z}, [rbx+r11*8-256] + vexp2ps zmm24, zmm31 + vexp2ps zmm24, zmm31, {sae} + vexp2ps zmm24, [rbx] + vexp2ps zmm24, [rbx]{1to16} + vexp2ps zmm24, [rbx+r11*8+256] + vexp2ps zmm24, [rbx+r11*8-256] + vexp2ps zmm24{k5}, zmm31 + vexp2ps zmm24{k5}, zmm31, {sae} + vexp2ps zmm24{k5}, [rbx] + vexp2ps zmm24{k5}, [rbx]{1to16} + vexp2ps zmm24{k5}, [rbx+r11*8+256] + vexp2ps zmm24{k5}, [rbx+r11*8-256] + vexp2ps zmm24{z}, zmm31 + vexp2ps zmm24{z}, zmm31, {sae} + vexp2ps zmm24{z}, [rbx] + vexp2ps zmm24{z}, [rbx]{1to16} + vexp2ps zmm24{z}, [rbx+r11*8+256] + vexp2ps zmm24{z}, [rbx+r11*8-256] + vexp2ps zmm24{k5}{z}, zmm31 + vexp2ps zmm24{k5}{z}, zmm31, {sae} + vexp2ps zmm24{k5}{z}, [rbx] + vexp2ps zmm24{k5}{z}, [rbx]{1to16} + vexp2ps zmm24{k5}{z}, [rbx+r11*8+256] + vexp2ps zmm24{k5}{z}, [rbx+r11*8-256] + vrcp28pd zmm24, zmm31 + vrcp28pd zmm24, zmm31, {sae} + vrcp28pd zmm24, [rbx] + vrcp28pd zmm24, [rbx]{1to8} + vrcp28pd zmm24, [rbx+r11*8+256] + vrcp28pd zmm24, [rbx+r11*8-256] + vrcp28pd zmm24{k5}, zmm31 + vrcp28pd zmm24{k5}, zmm31, {sae} + vrcp28pd zmm24{k5}, [rbx] + vrcp28pd zmm24{k5}, [rbx]{1to8} + vrcp28pd zmm24{k5}, [rbx+r11*8+256] + vrcp28pd zmm24{k5}, [rbx+r11*8-256] + vrcp28pd zmm24{z}, zmm31 + vrcp28pd zmm24{z}, zmm31, {sae} + vrcp28pd zmm24{z}, [rbx] + vrcp28pd zmm24{z}, [rbx]{1to8} + vrcp28pd zmm24{z}, [rbx+r11*8+256] + vrcp28pd zmm24{z}, [rbx+r11*8-256] + vrcp28pd zmm24{k5}{z}, zmm31 + vrcp28pd zmm24{k5}{z}, zmm31, {sae} + vrcp28pd zmm24{k5}{z}, [rbx] + vrcp28pd zmm24{k5}{z}, [rbx]{1to8} + vrcp28pd zmm24{k5}{z}, [rbx+r11*8+256] + vrcp28pd zmm24{k5}{z}, [rbx+r11*8-256] + vrcp28ps zmm24, zmm31 + vrcp28ps zmm24, zmm31, {sae} + vrcp28ps zmm24, [rbx] + vrcp28ps zmm24, [rbx]{1to16} + vrcp28ps zmm24, [rbx+r11*8+256] + vrcp28ps zmm24, [rbx+r11*8-256] + vrcp28ps zmm24{k5}, zmm31 + vrcp28ps zmm24{k5}, zmm31, {sae} + vrcp28ps zmm24{k5}, [rbx] + vrcp28ps zmm24{k5}, [rbx]{1to16} + vrcp28ps zmm24{k5}, [rbx+r11*8+256] + vrcp28ps zmm24{k5}, [rbx+r11*8-256] + vrcp28ps zmm24{z}, zmm31 + vrcp28ps zmm24{z}, zmm31, {sae} + vrcp28ps zmm24{z}, [rbx] + vrcp28ps zmm24{z}, [rbx]{1to16} + vrcp28ps zmm24{z}, [rbx+r11*8+256] + vrcp28ps zmm24{z}, [rbx+r11*8-256] + vrcp28ps zmm24{k5}{z}, zmm31 + vrcp28ps zmm24{k5}{z}, zmm31, {sae} + vrcp28ps zmm24{k5}{z}, [rbx] + vrcp28ps zmm24{k5}{z}, [rbx]{1to16} + vrcp28ps zmm24{k5}{z}, [rbx+r11*8+256] + vrcp28ps zmm24{k5}{z}, [rbx+r11*8-256] + vrcp28sd xmm2, xmm7, xmm0 + vrcp28sd xmm2, xmm7, xmm0, {sae} + vrcp28sd xmm2, xmm7, [rbx] + vrcp28sd xmm2, xmm7, [rbx+r11*8+256] + vrcp28sd xmm2, xmm7, [rbx+r11*8-256] + vrcp28sd xmm2{k5}, xmm7, xmm0 + vrcp28sd xmm2{k5}, xmm7, xmm0, {sae} + vrcp28sd xmm2{k5}, xmm7, [rbx] + vrcp28sd xmm2{k5}, xmm7, [rbx+r11*8+256] + vrcp28sd xmm2{k5}, xmm7, [rbx+r11*8-256] + vrcp28sd xmm2{z}, xmm7, xmm0 + vrcp28sd xmm2{z}, xmm7, xmm0, {sae} + vrcp28sd xmm2{z}, xmm7, [rbx] + vrcp28sd xmm2{z}, xmm7, [rbx+r11*8+256] + vrcp28sd xmm2{z}, xmm7, [rbx+r11*8-256] + vrcp28sd xmm2{k5}{z}, xmm7, xmm0 + vrcp28sd xmm2{k5}{z}, xmm7, xmm0, {sae} + vrcp28sd xmm2{k5}{z}, xmm7, [rbx] + vrcp28sd xmm2{k5}{z}, xmm7, [rbx+r11*8+256] + vrcp28sd xmm2{k5}{z}, xmm7, [rbx+r11*8-256] + vrcp28ss xmm2, xmm7, xmm0 + vrcp28ss xmm2, xmm7, xmm0, {sae} + vrcp28ss xmm2, xmm7, [rbx] + vrcp28ss xmm2, xmm7, [rbx+r11*8+256] + vrcp28ss xmm2, xmm7, [rbx+r11*8-256] + vrcp28ss xmm2{k5}, xmm7, xmm0 + vrcp28ss xmm2{k5}, xmm7, xmm0, {sae} + vrcp28ss xmm2{k5}, xmm7, [rbx] + vrcp28ss xmm2{k5}, xmm7, [rbx+r11*8+256] + vrcp28ss xmm2{k5}, xmm7, [rbx+r11*8-256] + vrcp28ss xmm2{z}, xmm7, xmm0 + vrcp28ss xmm2{z}, xmm7, xmm0, {sae} + vrcp28ss xmm2{z}, xmm7, [rbx] + vrcp28ss xmm2{z}, xmm7, [rbx+r11*8+256] + vrcp28ss xmm2{z}, xmm7, [rbx+r11*8-256] + vrcp28ss xmm2{k5}{z}, xmm7, xmm0 + vrcp28ss xmm2{k5}{z}, xmm7, xmm0, {sae} + vrcp28ss xmm2{k5}{z}, xmm7, [rbx] + vrcp28ss xmm2{k5}{z}, xmm7, [rbx+r11*8+256] + vrcp28ss xmm2{k5}{z}, xmm7, [rbx+r11*8-256] + vrsqrt28pd zmm24, zmm31 + vrsqrt28pd zmm24, zmm31, {sae} + vrsqrt28pd zmm24, [rbx] + vrsqrt28pd zmm24, [rbx]{1to8} + vrsqrt28pd zmm24, [rbx+r11*8+256] + vrsqrt28pd zmm24, [rbx+r11*8-256] + vrsqrt28pd zmm24{k5}, zmm31 + vrsqrt28pd zmm24{k5}, zmm31, {sae} + vrsqrt28pd zmm24{k5}, [rbx] + vrsqrt28pd zmm24{k5}, [rbx]{1to8} + vrsqrt28pd zmm24{k5}, [rbx+r11*8+256] + vrsqrt28pd zmm24{k5}, [rbx+r11*8-256] + vrsqrt28pd zmm24{z}, zmm31 + vrsqrt28pd zmm24{z}, zmm31, {sae} + vrsqrt28pd zmm24{z}, [rbx] + vrsqrt28pd zmm24{z}, [rbx]{1to8} + vrsqrt28pd zmm24{z}, [rbx+r11*8+256] + vrsqrt28pd zmm24{z}, [rbx+r11*8-256] + vrsqrt28pd zmm24{k5}{z}, zmm31 + vrsqrt28pd zmm24{k5}{z}, zmm31, {sae} + vrsqrt28pd zmm24{k5}{z}, [rbx] + vrsqrt28pd zmm24{k5}{z}, [rbx]{1to8} + vrsqrt28pd zmm24{k5}{z}, [rbx+r11*8+256] + vrsqrt28pd zmm24{k5}{z}, [rbx+r11*8-256] + vrsqrt28ps zmm24, zmm31 + vrsqrt28ps zmm24, zmm31, {sae} + vrsqrt28ps zmm24, [rbx] + vrsqrt28ps zmm24, [rbx]{1to16} + vrsqrt28ps zmm24, [rbx+r11*8+256] + vrsqrt28ps zmm24, [rbx+r11*8-256] + vrsqrt28ps zmm24{k5}, zmm31 + vrsqrt28ps zmm24{k5}, zmm31, {sae} + vrsqrt28ps zmm24{k5}, [rbx] + vrsqrt28ps zmm24{k5}, [rbx]{1to16} + vrsqrt28ps zmm24{k5}, [rbx+r11*8+256] + vrsqrt28ps zmm24{k5}, [rbx+r11*8-256] + vrsqrt28ps zmm24{z}, zmm31 + vrsqrt28ps zmm24{z}, zmm31, {sae} + vrsqrt28ps zmm24{z}, [rbx] + vrsqrt28ps zmm24{z}, [rbx]{1to16} + vrsqrt28ps zmm24{z}, [rbx+r11*8+256] + vrsqrt28ps zmm24{z}, [rbx+r11*8-256] + vrsqrt28ps zmm24{k5}{z}, zmm31 + vrsqrt28ps zmm24{k5}{z}, zmm31, {sae} + vrsqrt28ps zmm24{k5}{z}, [rbx] + vrsqrt28ps zmm24{k5}{z}, [rbx]{1to16} + vrsqrt28ps zmm24{k5}{z}, [rbx+r11*8+256] + vrsqrt28ps zmm24{k5}{z}, [rbx+r11*8-256] + vrsqrt28sd xmm2, xmm7, xmm0 + vrsqrt28sd xmm2, xmm7, xmm0, {sae} + vrsqrt28sd xmm2, xmm7, [rbx] + vrsqrt28sd xmm2, xmm7, [rbx+r11*8+256] + vrsqrt28sd xmm2, xmm7, [rbx+r11*8-256] + vrsqrt28sd xmm2{k5}, xmm7, xmm0 + vrsqrt28sd xmm2{k5}, xmm7, xmm0, {sae} + vrsqrt28sd xmm2{k5}, xmm7, [rbx] + vrsqrt28sd xmm2{k5}, xmm7, [rbx+r11*8+256] + vrsqrt28sd xmm2{k5}, xmm7, [rbx+r11*8-256] + vrsqrt28sd xmm2{z}, xmm7, xmm0 + vrsqrt28sd xmm2{z}, xmm7, xmm0, {sae} + vrsqrt28sd xmm2{z}, xmm7, [rbx] + vrsqrt28sd xmm2{z}, xmm7, [rbx+r11*8+256] + vrsqrt28sd xmm2{z}, xmm7, [rbx+r11*8-256] + vrsqrt28sd xmm2{k5}{z}, xmm7, xmm0 + vrsqrt28sd xmm2{k5}{z}, xmm7, xmm0, {sae} + vrsqrt28sd xmm2{k5}{z}, xmm7, [rbx] + vrsqrt28sd xmm2{k5}{z}, xmm7, [rbx+r11*8+256] + vrsqrt28sd xmm2{k5}{z}, xmm7, [rbx+r11*8-256] + vrsqrt28ss xmm2, xmm7, xmm0 + vrsqrt28ss xmm2, xmm7, xmm0, {sae} + vrsqrt28ss xmm2, xmm7, [rbx] + vrsqrt28ss xmm2, xmm7, [rbx+r11*8+256] + vrsqrt28ss xmm2, xmm7, [rbx+r11*8-256] + vrsqrt28ss xmm2{k5}, xmm7, xmm0 + vrsqrt28ss xmm2{k5}, xmm7, xmm0, {sae} + vrsqrt28ss xmm2{k5}, xmm7, [rbx] + vrsqrt28ss xmm2{k5}, xmm7, [rbx+r11*8+256] + vrsqrt28ss xmm2{k5}, xmm7, [rbx+r11*8-256] + vrsqrt28ss xmm2{z}, xmm7, xmm0 + vrsqrt28ss xmm2{z}, xmm7, xmm0, {sae} + vrsqrt28ss xmm2{z}, xmm7, [rbx] + vrsqrt28ss xmm2{z}, xmm7, [rbx+r11*8+256] + vrsqrt28ss xmm2{z}, xmm7, [rbx+r11*8-256] + vrsqrt28ss xmm2{k5}{z}, xmm7, xmm0 + vrsqrt28ss xmm2{k5}{z}, xmm7, xmm0, {sae} + vrsqrt28ss xmm2{k5}{z}, xmm7, [rbx] + vrsqrt28ss xmm2{k5}{z}, xmm7, [rbx+r11*8+256] + vrsqrt28ss xmm2{k5}{z}, xmm7, [rbx+r11*8-256] diff --git a/bddisasm_test/avx512/avx512er_64.result b/bddisasm_test/avx512/avx512er_64.result new file mode 100644 index 0000000..e940691 --- /dev/null +++ b/bddisasm_test/avx512/avx512er_64.result @@ -0,0 +1,4504 @@ +0000000000000000 6202fd48c8c7 VEXP2PD zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000006 6202fd18c8c7 VEXP2PD zmm24, zmm31, {sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000000C 6262fd48c803 VEXP2PD zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000012 6262fd58c803 VEXP2PD zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000000018 6222fd48c844db04 VEXP2PD zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000020 6222fd48c844dbfc VEXP2PD zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000028 6202fd4dc8c7 VEXP2PD zmm24{k5}, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000002E 6202fd1dc8c7 VEXP2PD zmm24{k5}, zmm31, {sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000034 6262fd4dc803 VEXP2PD zmm24{k5}, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000003A 6262fd5dc803 VEXP2PD zmm24{k5}, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000000040 6222fd4dc844db04 VEXP2PD zmm24{k5}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000048 6222fd4dc844dbfc VEXP2PD zmm24{k5}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000050 6202fdc8c8c7 VEXP2PD zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000056 6202fd98c8c7 VEXP2PD zmm24, zmm31, {sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000005C 6262fdc8c803 VEXP2PD zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000062 6262fdd8c803 VEXP2PD zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000000068 6222fdc8c844db04 VEXP2PD zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000070 6222fdc8c844dbfc VEXP2PD zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000078 6202fdcdc8c7 VEXP2PD zmm24{k5}{z}, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000007E 6202fd9dc8c7 VEXP2PD zmm24{k5}{z}, zmm31, {sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000084 6262fdcdc803 VEXP2PD zmm24{k5}{z}, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000008A 6262fdddc803 VEXP2PD zmm24{k5}{z}, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000000090 6222fdcdc844db04 VEXP2PD zmm24{k5}{z}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000098 6222fdcdc844dbfc VEXP2PD zmm24{k5}{z}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000000A0 62027d48c8c7 VEXP2PS zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000000A6 62027d18c8c7 VEXP2PS zmm24, zmm31, {sae} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000000AC 62627d48c803 VEXP2PS zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000000B2 62627d58c803 VEXP2PS zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +00000000000000B8 62227d48c844db04 VEXP2PS zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000000C0 62227d48c844dbfc VEXP2PS zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000000C8 62027d4dc8c7 VEXP2PS zmm24{k5}, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000000CE 62027d1dc8c7 VEXP2PS zmm24{k5}, zmm31, {sae} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000000D4 62627d4dc803 VEXP2PS zmm24{k5}, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000000DA 62627d5dc803 VEXP2PS zmm24{k5}, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +00000000000000E0 62227d4dc844db04 VEXP2PS zmm24{k5}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000000E8 62227d4dc844dbfc VEXP2PS zmm24{k5}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000000F0 62027dc8c8c7 VEXP2PS zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000000F6 62027d98c8c7 VEXP2PS zmm24, zmm31, {sae} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000000FC 62627dc8c803 VEXP2PS zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000102 62627dd8c803 VEXP2PS zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000000108 62227dc8c844db04 VEXP2PS zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000110 62227dc8c844dbfc VEXP2PS zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000118 62027dcdc8c7 VEXP2PS zmm24{k5}{z}, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000011E 62027d9dc8c7 VEXP2PS zmm24{k5}{z}, zmm31, {sae} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000124 62627dcdc803 VEXP2PS zmm24{k5}{z}, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000012A 62627dddc803 VEXP2PS zmm24{k5}{z}, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000000130 62227dcdc844db04 VEXP2PS zmm24{k5}{z}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000138 62227dcdc844dbfc VEXP2PS zmm24{k5}{z}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000140 6202fd48cac7 VRCP28PD zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000146 6202fd18cac7 VRCP28PD zmm24, zmm31, {sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000014C 6262fd48ca03 VRCP28PD zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000152 6262fd58ca03 VRCP28PD zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000000158 6222fd48ca44db04 VRCP28PD zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000160 6222fd48ca44dbfc VRCP28PD zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000168 6202fd4dcac7 VRCP28PD zmm24{k5}, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000016E 6202fd1dcac7 VRCP28PD zmm24{k5}, zmm31, {sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000174 6262fd4dca03 VRCP28PD zmm24{k5}, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000017A 6262fd5dca03 VRCP28PD zmm24{k5}, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000000180 6222fd4dca44db04 VRCP28PD zmm24{k5}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000188 6222fd4dca44dbfc VRCP28PD zmm24{k5}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000190 6202fdc8cac7 VRCP28PD zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000196 6202fd98cac7 VRCP28PD zmm24, zmm31, {sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000019C 6262fdc8ca03 VRCP28PD zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000001A2 6262fdd8ca03 VRCP28PD zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +00000000000001A8 6222fdc8ca44db04 VRCP28PD zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000001B0 6222fdc8ca44dbfc VRCP28PD zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000001B8 6202fdcdcac7 VRCP28PD zmm24{k5}{z}, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000001BE 6202fd9dcac7 VRCP28PD zmm24{k5}{z}, zmm31, {sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000001C4 6262fdcdca03 VRCP28PD zmm24{k5}{z}, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000001CA 6262fdddca03 VRCP28PD zmm24{k5}{z}, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +00000000000001D0 6222fdcdca44db04 VRCP28PD zmm24{k5}{z}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000001D8 6222fdcdca44dbfc VRCP28PD zmm24{k5}{z}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000001E0 62027d48cac7 VRCP28PS zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000001E6 62027d18cac7 VRCP28PS zmm24, zmm31, {sae} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000001EC 62627d48ca03 VRCP28PS zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000001F2 62627d58ca03 VRCP28PS zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +00000000000001F8 62227d48ca44db04 VRCP28PS zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000200 62227d48ca44dbfc VRCP28PS zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000208 62027d4dcac7 VRCP28PS zmm24{k5}, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000020E 62027d1dcac7 VRCP28PS zmm24{k5}, zmm31, {sae} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000214 62627d4dca03 VRCP28PS zmm24{k5}, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000021A 62627d5dca03 VRCP28PS zmm24{k5}, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000000220 62227d4dca44db04 VRCP28PS zmm24{k5}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000228 62227d4dca44dbfc VRCP28PS zmm24{k5}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000230 62027dc8cac7 VRCP28PS zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000236 62027d98cac7 VRCP28PS zmm24, zmm31, {sae} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000023C 62627dc8ca03 VRCP28PS zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000242 62627dd8ca03 VRCP28PS zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000000248 62227dc8ca44db04 VRCP28PS zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000250 62227dc8ca44dbfc VRCP28PS zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000258 62027dcdcac7 VRCP28PS zmm24{k5}{z}, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000025E 62027d9dcac7 VRCP28PS zmm24{k5}{z}, zmm31, {sae} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000264 62627dcdca03 VRCP28PS zmm24{k5}{z}, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000026A 62627dddca03 VRCP28PS zmm24{k5}{z}, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000000270 62227dcdca44db04 VRCP28PS zmm24{k5}{z}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000278 62227dcdca44dbfc VRCP28PS zmm24{k5}{z}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000280 62f2c508cbd0 VRCP28SD xmm2, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000286 62f2c518cbd0 VRCP28SD xmm2, xmm7, xmm0, {sae} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000028C 62f2c508cb13 VRCP28SD xmm2, xmm7, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000292 62b2c508cb54db20 VRCP28SD xmm2, xmm7, qword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +000000000000029A 62b2c508cb54dbe0 VRCP28SD xmm2, xmm7, qword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +00000000000002A2 62f2c50dcbd0 VRCP28SD xmm2{k5}, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000002A8 62f2c51dcbd0 VRCP28SD xmm2{k5}, xmm7, xmm0, {sae} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000002AE 62f2c50dcb13 VRCP28SD xmm2{k5}, xmm7, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000002B4 62b2c50dcb54db20 VRCP28SD xmm2{k5}, xmm7, qword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +00000000000002BC 62b2c50dcb54dbe0 VRCP28SD xmm2{k5}, xmm7, qword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +00000000000002C4 62f2c588cbd0 VRCP28SD xmm2, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000002CA 62f2c598cbd0 VRCP28SD xmm2, xmm7, xmm0, {sae} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000002D0 62f2c588cb13 VRCP28SD xmm2, xmm7, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000002D6 62b2c588cb54db20 VRCP28SD xmm2, xmm7, qword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +00000000000002DE 62b2c588cb54dbe0 VRCP28SD xmm2, xmm7, qword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +00000000000002E6 62f2c58dcbd0 VRCP28SD xmm2{k5}{z}, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000002EC 62f2c59dcbd0 VRCP28SD xmm2{k5}{z}, xmm7, xmm0, {sae} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000002F2 62f2c58dcb13 VRCP28SD xmm2{k5}{z}, xmm7, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000002F8 62b2c58dcb54db20 VRCP28SD xmm2{k5}{z}, xmm7, qword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000000300 62b2c58dcb54dbe0 VRCP28SD xmm2{k5}{z}, xmm7, qword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +0000000000000308 62f24508cbd0 VRCP28SS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000030E 62f24518cbd0 VRCP28SS xmm2, xmm7, xmm0, {sae} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000314 62f24508cb13 VRCP28SS xmm2, xmm7, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +000000000000031A 62b24508cb54db40 VRCP28SS xmm2, xmm7, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000040, + +0000000000000322 62b24508cb54dbc0 VRCP28SS xmm2, xmm7, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffc0, + +000000000000032A 62f2450dcbd0 VRCP28SS xmm2{k5}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000330 62f2451dcbd0 VRCP28SS xmm2{k5}, xmm7, xmm0, {sae} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000336 62f2450dcb13 VRCP28SS xmm2{k5}, xmm7, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +000000000000033C 62b2450dcb54db40 VRCP28SS xmm2{k5}, xmm7, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000040, + +0000000000000344 62b2450dcb54dbc0 VRCP28SS xmm2{k5}, xmm7, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffc0, + +000000000000034C 62f24588cbd0 VRCP28SS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000352 62f24598cbd0 VRCP28SS xmm2, xmm7, xmm0, {sae} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000358 62f24588cb13 VRCP28SS xmm2, xmm7, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +000000000000035E 62b24588cb54db40 VRCP28SS xmm2, xmm7, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000040, + +0000000000000366 62b24588cb54dbc0 VRCP28SS xmm2, xmm7, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffc0, + +000000000000036E 62f2458dcbd0 VRCP28SS xmm2{k5}{z}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000374 62f2459dcbd0 VRCP28SS xmm2{k5}{z}, xmm7, xmm0, {sae} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000037A 62f2458dcb13 VRCP28SS xmm2{k5}{z}, xmm7, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +0000000000000380 62b2458dcb54db40 VRCP28SS xmm2{k5}{z}, xmm7, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000040, + +0000000000000388 62b2458dcb54dbc0 VRCP28SS xmm2{k5}{z}, xmm7, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffc0, + +0000000000000390 6202fd48ccc7 VRSQRT28PD zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000396 6202fd18ccc7 VRSQRT28PD zmm24, zmm31, {sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000039C 6262fd48cc03 VRSQRT28PD zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000003A2 6262fd58cc03 VRSQRT28PD zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +00000000000003A8 6222fd48cc44db04 VRSQRT28PD zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000003B0 6222fd48cc44dbfc VRSQRT28PD zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000003B8 6202fd4dccc7 VRSQRT28PD zmm24{k5}, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000003BE 6202fd1dccc7 VRSQRT28PD zmm24{k5}, zmm31, {sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000003C4 6262fd4dcc03 VRSQRT28PD zmm24{k5}, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000003CA 6262fd5dcc03 VRSQRT28PD zmm24{k5}, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +00000000000003D0 6222fd4dcc44db04 VRSQRT28PD zmm24{k5}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000003D8 6222fd4dcc44dbfc VRSQRT28PD zmm24{k5}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000003E0 6202fdc8ccc7 VRSQRT28PD zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000003E6 6202fd98ccc7 VRSQRT28PD zmm24, zmm31, {sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000003EC 6262fdc8cc03 VRSQRT28PD zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000003F2 6262fdd8cc03 VRSQRT28PD zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +00000000000003F8 6222fdc8cc44db04 VRSQRT28PD zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000400 6222fdc8cc44dbfc VRSQRT28PD zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000408 6202fdcdccc7 VRSQRT28PD zmm24{k5}{z}, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000040E 6202fd9dccc7 VRSQRT28PD zmm24{k5}{z}, zmm31, {sae} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000414 6262fdcdcc03 VRSQRT28PD zmm24{k5}{z}, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000041A 6262fdddcc03 VRSQRT28PD zmm24{k5}{z}, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000000420 6222fdcdcc44db04 VRSQRT28PD zmm24{k5}{z}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000428 6222fdcdcc44dbfc VRSQRT28PD zmm24{k5}{z}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000430 62027d48ccc7 VRSQRT28PS zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000436 62027d18ccc7 VRSQRT28PS zmm24, zmm31, {sae} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000043C 62627d48cc03 VRSQRT28PS zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000442 62627d58cc03 VRSQRT28PS zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000000448 62227d48cc44db04 VRSQRT28PS zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000450 62227d48cc44dbfc VRSQRT28PS zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000458 62027d4dccc7 VRSQRT28PS zmm24{k5}, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000045E 62027d1dccc7 VRSQRT28PS zmm24{k5}, zmm31, {sae} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000464 62627d4dcc03 VRSQRT28PS zmm24{k5}, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000046A 62627d5dcc03 VRSQRT28PS zmm24{k5}, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000000470 62227d4dcc44db04 VRSQRT28PS zmm24{k5}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000478 62227d4dcc44dbfc VRSQRT28PS zmm24{k5}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000480 62027dc8ccc7 VRSQRT28PS zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000486 62027d98ccc7 VRSQRT28PS zmm24, zmm31, {sae} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000048C 62627dc8cc03 VRSQRT28PS zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000492 62627dd8cc03 VRSQRT28PS zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000000498 62227dc8cc44db04 VRSQRT28PS zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000004A0 62227dc8cc44dbfc VRSQRT28PS zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000004A8 62027dcdccc7 VRSQRT28PS zmm24{k5}{z}, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000004AE 62027d9dccc7 VRSQRT28PS zmm24{k5}{z}, zmm31, {sae} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000004B4 62627dcdcc03 VRSQRT28PS zmm24{k5}{z}, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000004BA 62627dddcc03 VRSQRT28PS zmm24{k5}{z}, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +00000000000004C0 62227dcdcc44db04 VRSQRT28PS zmm24{k5}{z}, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000004C8 62227dcdcc44dbfc VRSQRT28PS zmm24{k5}{z}, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000004D0 62f2c508cdd0 VRSQRT28SD xmm2, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000004D6 62f2c518cdd0 VRSQRT28SD xmm2, xmm7, xmm0, {sae} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000004DC 62f2c508cd13 VRSQRT28SD xmm2, xmm7, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000004E2 62b2c508cd54db20 VRSQRT28SD xmm2, xmm7, qword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +00000000000004EA 62b2c508cd54dbe0 VRSQRT28SD xmm2, xmm7, qword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +00000000000004F2 62f2c50dcdd0 VRSQRT28SD xmm2{k5}, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000004F8 62f2c51dcdd0 VRSQRT28SD xmm2{k5}, xmm7, xmm0, {sae} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000004FE 62f2c50dcd13 VRSQRT28SD xmm2{k5}, xmm7, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000504 62b2c50dcd54db20 VRSQRT28SD xmm2{k5}, xmm7, qword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +000000000000050C 62b2c50dcd54dbe0 VRSQRT28SD xmm2{k5}, xmm7, qword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +0000000000000514 62f2c588cdd0 VRSQRT28SD xmm2, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000051A 62f2c598cdd0 VRSQRT28SD xmm2, xmm7, xmm0, {sae} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000520 62f2c588cd13 VRSQRT28SD xmm2, xmm7, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000526 62b2c588cd54db20 VRSQRT28SD xmm2, xmm7, qword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +000000000000052E 62b2c588cd54dbe0 VRSQRT28SD xmm2, xmm7, qword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +0000000000000536 62f2c58dcdd0 VRSQRT28SD xmm2{k5}{z}, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000053C 62f2c59dcdd0 VRSQRT28SD xmm2{k5}{z}, xmm7, xmm0, {sae} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000542 62f2c58dcd13 VRSQRT28SD xmm2{k5}{z}, xmm7, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000548 62b2c58dcd54db20 VRSQRT28SD xmm2{k5}{z}, xmm7, qword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + +0000000000000550 62b2c58dcd54dbe0 VRSQRT28SD xmm2{k5}{z}, xmm7, qword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + +0000000000000558 62f24508cdd0 VRSQRT28SS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000055E 62f24518cdd0 VRSQRT28SS xmm2, xmm7, xmm0, {sae} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000564 62f24508cd13 VRSQRT28SS xmm2, xmm7, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +000000000000056A 62b24508cd54db40 VRSQRT28SS xmm2, xmm7, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000040, + +0000000000000572 62b24508cd54dbc0 VRSQRT28SS xmm2, xmm7, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffc0, + +000000000000057A 62f2450dcdd0 VRSQRT28SS xmm2{k5}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000580 62f2451dcdd0 VRSQRT28SS xmm2{k5}, xmm7, xmm0, {sae} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000586 62f2450dcd13 VRSQRT28SS xmm2{k5}, xmm7, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +000000000000058C 62b2450dcd54db40 VRSQRT28SS xmm2{k5}, xmm7, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000040, + +0000000000000594 62b2450dcd54dbc0 VRSQRT28SS xmm2{k5}, xmm7, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffc0, + +000000000000059C 62f24588cdd0 VRSQRT28SS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000005A2 62f24598cdd0 VRSQRT28SS xmm2, xmm7, xmm0, {sae} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000005A8 62f24588cd13 VRSQRT28SS xmm2, xmm7, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +00000000000005AE 62b24588cd54db40 VRSQRT28SS xmm2, xmm7, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000040, + +00000000000005B6 62b24588cd54dbc0 VRSQRT28SS xmm2, xmm7, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffc0, + +00000000000005BE 62f2458dcdd0 VRSQRT28SS xmm2{k5}{z}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000005C4 62f2459dcdd0 VRSQRT28SS xmm2{k5}{z}, xmm7, xmm0, {sae} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000005CA 62f2458dcd13 VRSQRT28SS xmm2{k5}{z}, xmm7, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +00000000000005D0 62b2458dcd54db40 VRSQRT28SS xmm2{k5}{z}, xmm7, dword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000040, + +00000000000005D8 62b2458dcd54dbc0 VRSQRT28SS xmm2{k5}{z}, xmm7, dword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512ER, Ins cat: KNL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 27 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffc0, + diff --git a/bddisasm_test/avx512/avx512f_64 b/bddisasm_test/avx512/avx512f_64 new file mode 100644 index 0000000000000000000000000000000000000000..9d36e9c69020d07048a65d82b408ac3cffee434c GIT binary patch literal 94145 zcmeFa-H#midG8rnHbD5e0oi0LlNe)132-uwQ%H6JCUcT0U`Ar`5ZKdzE<6Awn>Iw} zzx3$O`j>Wo*5CPuckAD0U;nKK ze(Sd)xqtt@lC1ors{gpGI-&YsRsC=Odw=Jg^icb$e)iHY-}s+@_IAZT{n^|5{(sT7 z^ZNH6f7V~Sc%px&FaNql}V5n!+#T_=U=i zbNHob0>6|8k$#=SFGUmhr96oA>kNJ=%C9r{r5wLd&Gi}lQZ#{I%7aM1&fu4#3H(wX zMEZ3GzZ6a2m+~OeuPyxA!Y}3WYYV@W;}@#=-NLUe{8DZXzmx};er@5`7Jex=hhNHr zOTV`8YYV@Wo5L^V!G&Kh`n8Y68D*Od#yq^V$-G^;Un~mGd6Qb&uoG)i}r)$9cwao^dGGJ`_Lj%695h z|DSQ3XB^5+`1mHQCK$(g#-ZGVk8i>{z5IH0>cNw@Bd0BE4@$nRjXJrO$!!+~fel=L zy;=`!u*95z)q&N49R^k}F(+V6U`=30fi+9aiLe)k8xP)i`{iFs9<*#)zNl9^;g-oA zV?|&^U}a#%5_1C92G$0499X-=oPc$Kb%9L+>z0@kVGowu#y%?1pgvkYZutYf(#f_= z?i#BCs{-2%tXg7Dz@~vs13L+9y2PA-^?~()-3+W>Vorp;-iN0Wo7IP>dKI3M*o8hk zm4Jn(dX?DH(>^?vfQ6@emDtkLK0K9xg{OLz*wWL3@Kj|C*PNx^6;VM{5W5gn5>^vah$+Mg z#54)3i5{YdxCzlGVZD3#Un_i3lrI&&D90C6b6Vkxq6vIa9z^<5;ftaPd{G`m`cmPG zq6vIa9z^;w#1}>RGQ=0<_=0Lqhxnps0$-E|k-iM^MbQMlC=Vii8RCng34Bo=MEX+V zi=uof@kKelpqkSXUldK?i}E1Sml9tTP2h|2Akvo-UldK?i}E1CmtTxGeph2uJooxT zskfyCTZ`Ok_12cHZEm%CYsc0uw_0yszC6C5t&ZMrsJD*TI?An9Z=JDqmRqgfI%n%V zw_3GzapB$Cuj0AaPo>_Gj@UZNtyXWHv2~VPt=>9k>pZtw@A#cR$vixn^B`p&*jnUP zEAznCHn&=t2ex*()#`U~L0cVj9&+o5t)tv(Wggf%%dJ-Cfvxl0YGoci$UJ;7=RwLm zuyvGMt;_>kXSvnNJg{}1TdkUh#m4VUiRxI&&*^?H^p>_3)QaD6t;m|ywU$~-t<9R% zwT@axt;?GAmK{{hQJqQA#|w3BL~TTElr^hsGiozxv#eQNn^T)pn`g~>>!n{@Svzq! z{n8h%tmQLfWWJaD*YRNOgsAI=a^C@lPPMhBRJnoIn_znN zA>X7vPof)|f1GTCNsLV%2h*z$`F`i%!kolM`} zzwsw}>RYV+$%!&O^6kw9eV*n0=1fr?zOH+CrE2KDEVt zLu*|BhqZ^s_GxaPdQEEkw14wgC;F$)EB4oZrFZhoua@tXj3?av!LRgg6-})xKChgo zWK_@5`!z%jaR^Z-VKvb}G!RD+O%m2ymtWi8_|=rC&n)&gf2B{dwB?-coI`JGYXMQH z_S$|4Q6ynC(L%Hk#}I82RudgW2Qh)@lCa*syt9AdSNaS~QJ+ohUsQZVx$m7q?}!*d zj36#SjFPaLm_f`SUWS+@VKp&_m_xh@F;BvJr@!+-om(H&jPI>|&}Y~Om%fnU%iiFF zJ_`p>>x$1S_uXdbZPjXs8sZS5PQq%UfoLF(Aetns`h;APR^QqDaDOqJ?N7jv?A4tR^~$4q^h)C1KSkjC&VEJfIQC9p!Ro@1o)(%6&%} zs!y!;MsOwE2<{TxC^@US8Qd}44DMyPS#nl$bGQlI9PU-Pd2-gf{cnDC^3t`dzxrn- zGVQ(=lj5eA)Zea_6dBgt_mcX_{o+^uEXqsj*Y``J7t&Aew`})9`t|)|qLoa`(*vNjw6ed%cA=}WuH~KWK7Cp@TA`4qIgo1vRH>Li8b3>wjZ+PnAotrWBUCKe;O63%zTuPrXY>3-Ogr#f$TF@rmXo58&dr#oagtM@mDo50QCUWL;= zGo1DAf^TnRUVy975%&T4K3cMLa!dl_z)oYmYMZUQ%l zdlhb;ob|45e^2`!__XhVPv=<>na={<1E1y|_%!#xr+uB#J+Rc*znWT2t5intR~WzN+Z@DCHT8T0yPInw2LlYAv-kYgV4OsCCr3tXXegesp}{ z^bN%|#mmYc^wn0CQ>k}U8$ql?j37oySWV0z4k2a`vm~r0<`72^bBK8o);s+hx`w>r z&OYWEa%FW5A!E&rxrQj3;u@lyYY3_<#F%S{q6w}c%7e&j$e3%0q6w}c%7e&j$e3%0 zqRz!J*AV4gLs0eqG1m}96I?@-2VphAHAK+_*AV4FSWR#ZQ8d9dM0pTaT|>rPLo@y_lkAa&OZ;OgZ;rsP3co3Wx%tgea1*nrIbfICbvL!=PQJ6Z4(Cq()Sf%}BibIE z)to!|j%LOCb0>dl&z<}c<-u9axs&f`Zp^upKegvh{)qD6tao1e<(2gleL6ngSl2_v zW8(|!H}tjQE9?4T-P`;*v9>+<_LshRWj*?wz8s>0CQ@H}P)Yk*7G>_TsAsq+>M8Bl zd%jjUa#koluRQMYthZJ3Rm0JQuNpcdlCYZa^}~@f0-{dBYQk3%N6rX{CJ8Hdf$r*i z8}90Ro9^n$Jr|+AgDW5kh!Ubm!fK+0Xd#Xv+9a$dI*1Np0?{R5inZF@>NX9V0RIjcEe+aB2SwM}OPoUd&Spgv--7LP zv-iyEW{)gRJ#O~)x!K$2W=}a66I2(1eQx#?y&rD&ln0SFd;8q%DVpGBPk9h|v$xO9 zo}y-GpPN19Tq;nt`F(Eo6islmr#uL&32ycjO>ncPJP4}^ZuS&SaI>d82&*m?``qkl zHq^3}>k_cf&7N}mrH^x@YVG^n>}fvCakID2&7Sh$tme4c)2x`|W^bRHJ>|h!&2h7* zxiQDh-aa>b%7e4&F>uf4tD|OeZ%t8`_NVjGE|nX5K64#S_{`O%JqfD`pTmwOd=5Xa zJoaHV;j`J%gwN*Zl?P$v((W^BZ^LKS-loqi<;*1N%W?rxK$H+g5>^u}Lg?KIQ`AN586G82 zy_@|3!~kL)VvvN@L=90x975DdSWPq#4a5;dlZ2HIkDuYg<7eCrHWl@u@iY11vD6>@ z77ztQ2~i|rHPJ$}5XTU05>^u(L^v)h&jZo5c4FgcXXcOi=uqFiZ9Ap^{D#7ReVu2fiKE~ zu$sUZMHBdZUl_9wb!C;mV4^KAJaiv6_@ z>syXLteNiDKCIi|oewWRKqX^E_k#~>H7c4~SJby0e;7YdIo8(@HN+uAorKjy1JOVn zK{QEN<>|r3hvliFJU!S{)VCaenAt|<$3X#6K$H+g5>^u}L1b!(GBKE&Nh$4!@KKmws*G*A{*$H-}%!gA2c2 z^m%_{Q?9+}_4U}wFEaePfnPUDNV}$oZq2nGhf!UrZs6CAV+gyZhwdb-Ch+UV1j4TA zp*snyzUA1J^B%`_kK@tRILH{sdB$;`aVXb56!URcI`!i&dtn^PP5Ai!hGMG;#&Mo; zC^zBbo3QGeN*1STeGspx58@U5K120k`(i+CKy8pUt7|p2np&MTt7{FlhFX&~>n(q& zywWAzq!Xc^%p%nFN%E8BWs>d z*O*U5*F2B@e^%F+Pes=}kFHs#m#>eRPes1yp)v4H0aDkPPes1*Cu>F4n9niusTlvy z>i@@lD*FF*S+h8?{)qK=^s%cxVzu~HeBf%)r>wuT{FF74*b*PDYKxM`^i6#J)^LAEpFVN*xAgg2 zfg;gIuiE2(i2YmqD)w*D-u}aK|B=L&*uS>K{{J%e|Ch1_ed2*tf$auXEiorx z)4-;Iodh;rVot#N!1};$2G%bzC&Kje989moW>w*-UWKP5cA*MSC1ByHUM05lvtZ+dB7M|)=VoOiU@Kgd8p6XR% zOHa%2R00;B>Q!P(Py185Cti7{b~U|Ppu4(cE|Xg>45B`W`e0diLcNZ99rb!ycS601 zdK2|#S$E=k6~~wO_!3-Q%`q+`Pl z0>_3prY%9FW97Dpx0E=hT#l7ErX0smemVjU$4VS4aZGt|=~y|1!!hOFAC4&xE*&d- zI2==M4#$)SmyTWgl$X!ur@YcWx60$sZfEY=|NEFpIE`JNv4Q$0oDn_DQV^s{o zYJ!nej6}H!kHGt|PBjs&XQS1*)vvXllXf*H&T>v#Puu`%T~U3f&AubmS=`qUHN+uA zorKjy1JOVnK{QEN={qfbr={;Gs_(Sfcckta1w;W+LKI0@O|%d##4$vhgw;d`(Lqcg zx+JXh9TDm~it0Ne)OQrscT}hENa;IpXW=TiUAQVaD}4v3&3dfXZ-w8h|98;w4*bn8|cap%d3dbrOQ=WYX z;`(qyV^!bLDAjiqzo0z(j?`TR#}rNAnDQXfu_2Brn!qvTL8N0t98)xbW6Fa_$I5Nb zT!~}K={t(QuRPYjmA(UqV|M$9cstK8lq0ZO5dS2AvO?A5?1#e zmnufGQ!`9VvYWf{|2=L^1nL5)A|+sThf3_8k+Nh-1&jF@5LQ zb8@_z6K6Rm$DX(W)ViYj&T;k~>23ENh#KM$qE5nUqJd~2jv$&Otn{5@`p&V=uY*lR z^_^qRFOg=5OI?}Q%}jw#Z2?1%E~J4xVJg<}N|?+I~t?zP*M60 z1da`HY?zLrCRzv_8{(L@WZ#jR=pb-xh-2E4eFx$#<+cd*9mUJa={ue|<=Je{98>P&;+XQ_(y?pb^YYpJo>$uUyvDw_T4T;~ zjRBR!!S`5W-^;!urSDKXCe{#j5?1;SwF$9-Xp*qH@3>Skk{yp^XEhSCJa>Q?NySJM zv+qdhI}nVdVkC;$camrz7)ixQ6tnM`&_sN~v+)V~&L=!4pIFU_vz(Jpc;W_7>x$|- zpUA!=z3sjOQ9~R;)Ja%PG!PBM5k!-OmA>-{`pzflJBsQ%pUA!=b8=g`sA$cJ9ccx^H{Cfv7MD;WO?p*wksT~a7=mjo$#Z=F-7{0 z{ZO8LCkY&@aIC^H<=J;2)OR#i^&O2;eMeFKMq{M!NZm7VOwk06DGwqY8{(Lv2^>=% zL^?LaF+~$NraXvrtlaj@l{luHzN4tVBTkN?^c^@HD{-vEG3CLfW91YM$CP`2IHo+f zbgb;*a7;OUhvTMW+J>_aje8K z<-w(6*S_O5_8r#Pcf7{Fvsz=$a*ch5H3qe=s5SPTTw_w!7(@+m2vH|tWsN~J5JwPA z5?0pOcUWWJVT~zjjeRHAnAGc|fG8kJh$0EAi58-TIEHAGu$t%~I*18GmxPryCPHgW zQEN&FsYb^YzY6u*wa7U#xz!~F^y7d zOi^o0V`Pm z)66Bx8iObxN{Au}D{Bm*g*b+2ld!VJAUcQ%M3;n>H6}u9Oi^o0gw~j%)|l$7F)3>d z?krpdw+mM#XJw7SJqI_1JAs=fXJw7Sy#Uw4-Gu9tvwDr$u^rE2wPwe5R*sS78uM&d z11KC*o@*@psA>ott8h$Pa*ZX?K;T$~V^unavc@!4tuc*KYfMpVOk-q?Nm*kMI5xzw zVLFDIXd!THh-2E4Yb^KCLEzXB$A;+`%5_YH)|jHMW1hJZ$CSspZe@+Z;aG`dC5|Z% zE*&eUa5$!%HKzFc%7aVC${r5Kl(WX*(lKqrv1_04^4a{1SK4R1#y+!JW6pAo0hPqT zXINvO$!An4Uni8Vx>gq3GhY7=4u(IjE@Gpb7!BiZptc2*-H%X0^akyMOCF`rST zJflJ|l8TWi<}+#%4Fn^p7>Qy&qngk}eATn@Rr=0XJttpX&55&|ldpQ>22ksY>N{V} zz9YTuXH_P5YR!)AtQ;fDbH}q?;aG)Z%Cql;9~F)%dOtX( zJo`=(I9B0Ug=5NtNXLd78msz_MybA|sJ^2y(s!ipDmbQS0>_jGk&X> z`@pdwjty~4c@XJXx$T)NaZEXVM^V>yaa`M_^c^@HD{-vEG3D8JlAFTeSczjLjw#Q+ zlUxsnV zgq6NSZ9;4ynk205J1$j>WXB`fS&f7&&mAB}QZW+6>^oBW4g@2q7>Q!`og^9vMp7{n z#q2vKG!ftTYCEK-3V25Ooq(6AeTIaRkvMVWsbUlD_jv`i`Rd&L^|) zNZm6EhytR7D3Y+6XdzmNV~92htBDSxgP1^cNm%JSBGh*j)ptaw?p6v?9 zDjZXueJA{=a7>ZDV?UH<-$??;DjchDOnLSl2=yI}ReeXJRNqll-_aQ9J5qNQ98)xb zW6Fa_$A&njXadKSXWz+v;MfqyhB&4?h;*#n_RN(yrkuW`sQVpp-0w)~J8(Ew;#i4e z%7aVC$|)ReTw|W?Y5;{}%5#l{A5{&3 zV-=2RORljb8VDS#aI8wlP&qc-&{(y`G)k>8MXfQ7ku@e|jX~hp5XXk;7;2)0z_B5Y zX-lrL+(!q2V?!Jprei4Ab`e@*in_LY=1Lq>o@-3X8iT{J630p$Q=V%qxhWiul{i-7 znDXG#v9gE5G37okjwuf=9lQ2jud(m4#=h${_TAMQbCzrDyR0#&bw#bQ@8%klvc@24 zh(m}v2`g(1qJcPqXp*q9#=grM`z~utQETkGxyGbk9|c4KQ9=|+SWUDLEyOWIn}pRw z2hl-HAi5;1tT7QFujY(N!aA)BvxLvp^IV)=n?m4(A+zH$?IV)=n z?gh9W?j~HHoYia0j_r6Jt2H~evvQ0q*O+I!8bINg@?2x#M^!`MScPNSl4~r91_H+_ z9IMhXlr^TYYK>`>T4Rb@V;UoCOzIVcV~QqlOnDIL*bv7QP2iaFTw}Qp92?@;5XY1U zk&czyp1Bgol(WVZbsZDObxg_{gTt{B$4VSi9$Y$BPT_D&x%Y=-%7aVC${r5Kl(WV- zZaSuIICkx`USpqSjeXW@?6a#i<}BCPXIW!V>xx=qpUpKUWsO195Qh+T5?0n2L<4aI z(IjDIjeV9i_F2}LqSn}FnM;&422nti5JeJJ))+(!aSYKWVP%a$bPyAWE(t4ZOoY~$ zqSlxQtuaNdG1XaPQq~yUS-1*r7p_Xq${K@v4sHr}0yj<0${K@v0j`I;3D+lQ^%}Ed zJD$gC&5rG?93#s$=Gm?WP&lSM*I4*b)etyV;h47M8cU*qz_AL)s&ouxjcKe}V;ZH_ zn4;F0#>g6zvc@2AY=~pSbPP4oLg3gC$FwEaSni{Pz_B5Y4bw4{>zD|wF-2X+JaZ+E zDbF<~WsSk%SczjLjw#PImfRE$$4VS4aZGuxvE+I<94m3G#4+W;rDNBQynHr~ywZ-m z#*S8N%vr86pprN^VvQZ;GpdwlRBFe>8lq0Z$}=jp39*4_lCb(2)uoD&?06(QtC5i9 zxdX&VDn_E1&!|$KQ6U&f#YhzM88wLpf{|2=L@}RHO=u#%?%DV{edp_*ldrGl#97YC z*FA9qsC7m4ov&x#k>2(*Dnt!&2vH|tHPJvc5JwPA5?1=o*XcW7r|&4L?|eP`j?_J) zfG8kJh$0EAi58-TIEHAGu$t%~I*18GmxPtRBSL*gQGG{*`i`Rdj_ULsDSZd-EL;V* z3s)s)rSHH!2RDT~ftx00rSHJK0N2CagzJ;Dy6@Pr9nWL6X2*6`j*;cL}Q^3da<^9~@JjeJ2SVt8lEsG37y|W5W%NReeXJRNqll-_aQ9J5qNQ98)xbW6Fa_ z$A&njXadKSXWz+v;MfqyhB&4?h;*#n_RN(yrkuW`sB618uI*C#4jhh^I9B4A^5D|3 zateoI%Dq1vQyyG8R`zf>rraEkDGx3kyViO6Y<6C0o!3~mT4T;~jRBR!LB|^FvhPUg zJJgPeHAJ0+mA*r5LTn(KB&_Z`E>(J5u@%1S6>!iDLGh zBpL`tQZW+6>^mkj5kK^7{E)u$L(j<%S99Vl=j4Z;xB=9^upL<4aI(IjD|@BEOy^F#WMqWaDcIloZ)4nzS_LKI0@={pcD#4$vhgq6Mn(Lqcg zx+JXh9TDm~it0Ne)OQrscT}hENa;IpXW=TiUAQVaD}4vRP%47Xo={s;ZR^nKRW6Fa|$I2-jjwz?_DC&CS-KYZEV@&52jq#A|G_T4T;~jRBR!!Gtw7$-X0{?@&7?)(~|PR{9RL39*4_lCZk( zxKuHc9gk#ZH4?HscYqj4#Yhyh??~x85R9Z^B#PO0l4u|pNySJMv+tPDM10P(@j3d= z=R7B$Tg{2HoRiOa;s#Lbit0O`%f2JM?Y;w1LmWcXNmxxZ5Dml;M3aP-zVkWy&gbYm zit0O`%f2IZ&nO@Yh!Ubm!fK+0Xd#Xv+9a$dI*1Np0?{R5rSFJP-%(WG5uv`LsJ^2* zeMd^)fjbLV!R^9T$yw<;aL>U_;ZESD$yw<;a4*31a5v%l@n+cQjV@9gR|bM^Sx8W2Em$ z-BoZ*(FBeu4x0Bc<;^Fp`RqC}!VDqJdx}6(dp1zGFfY@eR+$H|RUx@SJ>OH7Cw;PQKxZ8$hiq zs_%Rw`;PRs`wm16aR^Z-VKvb}G!RD+O%hi6&Nt{g-=Oa(s_%S*^9!Z#Kok%qM3ID* zz5~%h97D88Sm`?u9mE8pOTtRu5uv`LsJ^tE{g=32J z9s8j?`%V%#R^eEMW6HDdK&bC%tm-=&rTUJd`i{m(-;vUHAaHDmW5aX|HPJ%g*bv9G zCHqe9ql3V)A&w2xF_ilq5$ZdNy5I54l{lt6`;L^p1BYWJj+Hp3Jo`>^Q#c$eaje8K z<=J)~*$#IX{`ln0lNUHhh&&*nG1(!S|6_RZBAbCzois3Z=)$r}4+_8lpGhuSf* zhNzRU(s!s$hz&%Ogw=h=rHYa4cqBWkk&xxN1H?!wMxvN~M@rv;U?deIQOv%RL<7M{ zDn_E1eaD0*;zyp1AJKPy_P5YR!)AtQ;fDbH}q?;aG)Z%Cql;9~F)%(s%5K^6WcF;8=xY6^<#-z5}7Y zqp_;*Xq4(Zit0NWBYj8eu7YEVCU8u75b4+u#}rNAnDXp9xepv0;@A+!ln0THmD`@V z633L&cNBHMBaZtWDSZbH$4VS4aZGt|=~y|1!!hOFAC4&xE*&d-I2==M4#$)SmyTWg zv6s*0kG;}<>^1h|)f#h_YYeC)4t~rU`*HRiDSe09F|mfIld#fvs7;6sM3aQoeaEGW zk?eRRJFAh9<+%gINGe96n0-e|-+^Ex6(dp1zLP`)!AL4bqL_Urh{dT#H55gie~UFm z{hG)}IlIu?+B$$3K&(RylCYYnA!>+2h&lg)kF)?LL5W1NmxyE5FNw>qD#W6uCurx;w_p9bsgn8mlhWl z^-CsI*Ex*p9A1pz*5O8Qm*7UpS4}vznX39l_1vUWJ<{XVu@r9^;py z{2Jqza{NLy*JJ!rG=X2rgGj%|_@!t9zmx}&evR=<(FA@e4wyiHm=mx%usX2A!0ILD1gr_H3G67aW{Eiw_TpmW-~0DrO7yD&f4SJSd{M7- z!Yvd3?!-kASP@tmSh2*MfVF|OfgK0dE-@!yU0_{clfb$q=0wIs9 zPsib@UWKP5c3~WzO2EQXy-IB9={P)=PPsib@UM1$lp7y8y@FYajtKWzDhw53& z-`e0diLcNZ99rb!ycS601dK2|#S$E=k6~~u&{}OePWioX=jxV9^!%}xb zJ&s?+@g-SzLOqUO#qlLsccS_)hx*IwA)53r>J`5-I1-)AzZ~kXuZK`CmUSo8^%vM( zZ`Y`|%eoWl`YY_NcTw+_btkHSwA^;xqW`a7k{b0$s8><1qFycQPN+|#K8^ZxS$9Ic zk9r^Vepz>-`eT#r-;LkD`@25AUUBY5qI37LNfq@f>eaIDg!(k<)2L6EbtlyOsP|Ft zmvtwqYyLNxpN&oCZ)0;g|4KAI&41L3s29t+6Y6c$+o-q8x)bVM)Vrv6%eoWQHSw-n zV*aD9`Crzns8><1mUSom|7p~xQJ*gBPN?@$@1x!?>rPbH{QpJF|6j!X|HX3tmBjo< zy^4CZtUHPMkNPy~(`DUB%zxDTsQ1gd6aRwiok#o&u6G_;{eo*!J(#fdwb}Kf&maS$ssl4qwsKx}yH1#YfbiQ}rhj`Wm8!IE1K^u$pKf z8i*r^CJ8Hl(&8ihNsEu@j~5(lD(X*Kd_=RA%Ad4=C?HCRA_*&h(gLD|IEHAGu<|D@ zAUcQ%M3;n>KWQQ2fyqOP`jZwS^d~J8^`|UU=TBNl`I8oKL%0fV7p_Xq%Ad4=`vaCuh~4w2)s@&*C}!+FtoZhF|CKOVJd5DaS8VZk)p}MHBd? zJc#t`9DXU9z%S)Nq+e$?G}6};{l_NoOF4d_{7DN4{5peQXVNd!L<@mmXYfl~Vjt<( znGOQK&fu4}1d)DiZHstd3%`{6PfOsJa{NO1lNNCJwS`|>_@z9!^lNJhhhNJ1lNRIU-rrc0YcG0zJ+|_T48LyR*Nt^ZyQV*7p}FQyT1fem z7Ss-jc1?fMA_*&h(t_F%(XQ!FS|nk;)n9kzyvK3f<9Kv64l>4Zo^hOK9Llv1MO{x* z`I8pxg>jr`9Ew3$`I8n9jN?4xPz=I4?XO)@zqzEds$aY0esgKnZ=7Ynxumi71E_UH z^_xrCZ=^bZ`x>H#IE1K^u$pKf8i*r^CJ8J3<`Vtp68%O|{pM2k8>xFm0Z~Ad5JeJJ z6D>pwaSYKWVKvb~bPyAWE(t6BMuhr}qWX;p^&3U?8`bGIQu+l}Wa!!PC8Zy>In+0aPUZ!|{r8^vdpXTOoUo8XtC3H(wXMEZ3GzZ6a2 zm+~OeuQT|iXac{K2a$elZF}Cf@Jl)UM)48l*>9xu8#w&h!mlm-Ql9-LxhWieZQ<7z zeksp>lUxsnUt9RKgv?T~2K z)Nhio(r>685$&4#O%hi18&}SI9M?ULM_1z@%YFmHIL6nrZ*1uAuWx7sS2mWNhKvy`1{)fsqQo)>3P!wOO;e)=}%Iby>5je=IJj_LQQ| zK}F65ROjGgL~TTElr^hsGiozxv#eQNn^T)pn`g~>S95v&^8cjw6GztHw}0PhzuWg| z9V{-q??KJ;`(mE`?%(HkuTe?gnibD`RPJO&e{)?P-LXecuRJ2dqdh!Qlt+qqgvy6K zJW_NmJwjc>BSqKJBUB#k;gO;|Qp6)vbG?U0imnw|v$}>yimtU;v$}>yimr88vudXH z@JLY}DdG{Tx!%JgMb}1Iv$}>yimuJFW_1mZ6kVHV&FcA-M|wYT#fVz?r*$HD@{=|u851M+_+y* zE2tG&v%1z&YpJzav%1z%>!@{EvuZByUr_BSMa{S(E~0Yd{)pO$+9+#Q*Jjja)Mi<; zx;Cdar#8=;^{(df-{$k*=F{h;o`H4F{{QU!y!`9&ssExit*AAvNM}aXea8c818Re; zSzW8C)zs>&SzT+WHPo7{S=F`28~;V?T~X^@k$FM2ZpQ_+f?AO^t7|Q_mRg%Nt7{## zj#`&BtJeGYf@)7GYP~D6-chaF@rc@p+9+#Q*Jjja)Mi<;x;Cdar#8=;Reyj~bEm$o zcNE9gpO77&x~k4S-ngo(>-d7A=J~4US?~X<-@nEseQR#No!iy5*{*#q@JLY}DaIX+ zRdc<-BSqKJBh)oKQgkgnLS4fnMc2|Jl)E3jKiv=L{pl*N_oZ_e)m$&|NYS+-YgX6r zNYS-6YgX6rNYS+}YgWzE0*@5sks=@+4YCaY52-RHgcz z(LFp;)O;%95vsYqhewL86ohDVC7wOO;ehDVC7by>4&p6=n1qUKW(k5J9^Jv>r$ zZIm^uYj~vS+AM2U*YHTuwRzU8F`x2C?vt&uw!@tnu|Aij^FAw%_{7dZ3jsIWHy?)BAU;5T4 z=znD4P8Re%Y*+s1v_t&A%nbfwyzxi=mWz!)@_s_^=o=j_Xse_4nyMT8_wyk4ejeoB zuVK7@IgG`|`x(aKf>gtBfniY4FevD;!+Y4<@E-OqXb*Q*d(cMqpv~R`1@=Hed!TUl zrPutF@unUs-pq#zZSiBqKWUEtDTbrciIJC{eP)08m_erfY5R4+Xc0PT9GxYYb~{wTAMYiYaO+YT9-8|EmyUt_AjWW_Ni_9 z5EFIV9#I=n8)ePv+Kk$a+AM2U*XGpb)aF^U-tFJivVYT$ozJWuJIQiB{rI@gW2a)y zr6du^Y`PQ{$hxIN$Ju~X4=U1ZJ5eDeQz z?A*`WdX)L3*75(k{C`&F(~pSzJa#JPd`g*5YCIhhY9#8bWP); zW|gmtjfc2(eMsIZ$5&MTEDCA`wIXX)*IH^VwKi*3*E(t)wJvK``MS8EntG>dk0|0R zDt{IuY9nf+tXW-~QJYblWzFi^oZ6h)JZo0<_lLM~eJGBs5ANPczketF{+<5d?wv8u ze)sS6yVt0s{@~6P&wEt3byYB!peAvSyMc2|J)HOU( zbS*tX<7JVG_sdw8ViT9GxYYj~vSTAMYiYj~vST9-AeW@-r$ZIm^uYj~vS+AM2U*YHTuwRzU8o=pZ^It#U9d+_uRPLLJkoYN zqJl?M+*!wZol?~oZ5L}xthpusvkU|RiS8VT~S|fdjh{udD7PqHN+uA zorKjy1JOVnK{QEN<=w%?6Ix%2`qIk5rlP*!_5=>1a^j$XC?HCRA_=RB7NUhXhG>(p zn&==phzUfOgjF*;*%tA@yxwUHdcO3J&Wh?YkTDv8GfC^FGW-Mr5wLdxp5A^6iwil z@*vW$bNHob0>6|8k$#=QFGYVT48N4)7pl2FgI|g!@Jo3R>DL+jQZ#{I%7aM1&fu4# z3H(wXMEbRbUt9R4Tz+lgmva0v59d2m+m55KnX zOSw7xQXX9R^`g)F8=G?NMX#^NR(_G;*A4u-Q9{}^eZft0%@^FHxAgz<>&7vJUDFrb zlCYYDaa{K}9$k%tjB%W29OoH_a_vJgzu+d-mHRy7IL|ng zoAB}dEdW*%jN?4xP;SDEk{6!Hg^K;TzlEqaTX6@}BHCk$EKg=JxmKo0Jv# z=61zzDfihI>TiFqA!>+2h&lg)kF)?LL5W1NmxyE5FNw>qD#WcH@Az>^OkD*wsyteSMGBtly7T?7(rZu z7$srl8`>de5HCZ_lCbiv>=1K^S0Uy}SoKZpi&O8_tSf5P7i)_8A(8ho>!{{*F@P9A ztV0Zvu$rhLYKTLKItinxIb9SG1w;u^ zBw;ntLbMRa5N#4x6CFecF@flku<}D9BJ|@Ss_Dl=6!l{vs_^3>QqAdN1TliR1Tjj& zYGMX4gLoNYmW0*B9AXafD#SbqtFF-ZbcMdBK3uKc^A-Bu>I&_Qm0Jz&X>}`_T338t zIo%pn$FFLL8sZS5PQq%UfoLF(AetnsxIz+Mi+D;=J-2*Z@e$?pTvWZetRO0gU5F|PtBEPZ z6ygM8nuOIv579&1gy@s7%9o$Ym!E3J`?a6im!GbDafUDb;HUCM(bT%4?wo##FQ{g{ zuOVuPLx?&FtBD4pfjEL_lCW~;^i%GfekxxMHWhW}^izC6HKzv!L;+Dk6iHZ3v=A-C zF+`h$)kFu;K};aJB&^&yiO@ZhYPx4q)IF0b+%rivr;`ezg4l(qlCYYXLQEk}Af`!J zP4o~w#7&4k39CLltWLe6SyyDuC_b+|R)bY@S`8ou5bF?wB&;TCh#KM$qE5nUqJd~2 zjv$&OtgM$;STC=zUKF)nUdi<$^|@X^6c8muk%ZMm3(-OxL$pa)O>__)!~~*C!peFP zq4lDg){COniz@O3^|@X_R1mumRT5ScQ-~?V3B)uBtBD?>hqwvRCt<~xpX1BV@kLR- z{5*Y;;tRw8VjW_TgcV;PYKTLKIteSjKr|3X5KR(ReEB)P{2X5t<;&007b(6#6c8mu zk%SdrAXB~V2fiDO6qAfwBF9#h2 zz8v6-wgi#BOtwX+k9o!>_@X@fm{fB*sUYxWf-l+*-@XeN1`mBl}oSA5-)`=wr&$ z7xr=OU_&cgzGzL$7e)D^6^$=ae1V{k9ni-PvX7xA=wpiB2YpO=`jY#gj~&p*4(Mab z(-(*bCfn{Xiuj_a>x(K}U!?c~K_8pY$0pgwP!seqMelOQ$zQ`8Sv{*`AeRQI^m0Ac{K4lzi=YNCdyAr2wxB&;SHhz8;aqDjK4 z`{d!qU-1h8{z~`B!%ao~LV&;WjD_kRcUV9a5G6#Bgw;d~(Lx+Uv`JV^bPyfH1fomA zs{7<}TZDcEiE8>4B#Qb~0IKk-0HnIdEh~r$Vi%%H!fIj)F@-pRm?mL0(L?kQHzE2Y zto#tJXRODU9$%E>3#vKo@kLS2_4uMZi1ek$7ey2JqCAN7rN(B@I`qL>B|AWD4M_*a1B^Yp6BUnygu;ex|<|k!Sjg=d@2f(@VXzpjKRTt;m|y zwU$~-t<9R%wT@axt;?Eq>SuS=9C>!9rf2u8ji`;Njk0F-|CmvmQJZDW>e`&zoZ38V zR=@XCdq44<5o=88)gJnqaO)$Oskbjo_+a&ri!2ecmgGr2) zkAvyehx}vZ-zM=-16PAM=m4x*2h+wps1pua#6b(NVF@-YmIrmhL8~}u1y=5Ym6fU- z)QJwN=d_Q#OnkTE+Q;7Qr-F~^h^en5s!Dt6zBFC3*XF)U3C z3srm+E52})%0#(qqO4T0`&NAUbA0)8&)Axx{P^?qMT#$fjxQz-HccFCsDdw2d@(WE zHZghJg!1%7iZ2{xV4`0)(GOIy`&NA6D20iG(!@cbijQK&7miYynCzOERI1p0>s|lI zK8sZ1wcJN%&?_BCYnjB0^dLHe#MnV}2EEeJgpqiWPNFkNj7_35=#>sBjD+745S^iq z&d^6^(5pP?vNIe+XOM8v=nQ(52VHiCNpuDY2aV34S9#Fv4C;aJi5~bKW7V2PJ@7qo zP?G3@?};7=HrxaoZU~DWs3dwISh)>WJ`Sc=aZr-zfpO3QShWsT4VDLW5iirKd{5Q{HJG@3fD1s#i--m2l7^4jS+DAl~W0@|}`!&?*iZ?{pIHbh3P> zBs!?>T>k#VUwQd^{raWx1x0T;?K_vh*ZrfmJgB?BQ-ANfK;5zZz3<#~CxyoLX>On9 zcHIpv*yn#4bdYgq3G2h$+Mg#54&j&sGpU#7&4k39EXWuF1L=ROFdgQO~*`Ljct z8i)qs2%<^CDqjvZ{zkqi`e}4iQNK>|Z{lgxsyRIlWh_DMUtxNnO9N2NKzH~f@)4D6+{KG3sEIuH8F*lLYzQMldziTA$o|L z5PcF>){AGX!j}qPl;?VhIj!(T(JKmHln0T%RQRH30$-E|k-k*;qG$qNln0T%4Dm&g z^`fZtq7m{Lk<{lpz9^c&7v({uFGGA$G=VS5gGgV7_@Zb6Uz7)tzLfZ)$a+!KdJ(~T zk@{T67ey2JqCAN7rNkFS6ZoP$i1ekz7ey2JqCAN7rKgW6vR>R_lrv)}>%~2&r;qjY zG37yIAM5F3irxo(OnDI5$9nphq6zw#@*uL09c*Z2YrSYqYrQCHy=X5n^sxi_*g^I&l=T8ZA3LCr9b_LvSuY~AUff|O^fBek7|MEqppQ-HW0UM- zDC-4+J~p9`O|p-ntQQFS*n~bd$v%eO)vwAN=#z+@0j>=Et1<`6&m+kAJfa^Aa0Y5! zQTNq@bVh3LYKR)*5TZ`PYNCN?AdVoKB&>9@0nQ9?Mp2Fo(ithvKok%qM3ICQXCPXL zV~92hE6zZ45EFQJ|M<2x%AsYV`^ncA zbzpVu@i4G@i8%pl0&4<03anXTPK4=~`MoWEncv&=3zYQB{4Dxqes7au%S3ml`elBB z6@it36-&$sSQ}Uy*l}R(5_1C91=a;N39MUUPK4=~`5DtM^K)Il%+I3V;isx@{v**X zv3{9fV57h;1vXk@PQYe?%>sKlu-OuG0yYn99@wja&6k*yyKmQ0dxzKCJG9=awRd>E zy<@fBoUz`j!8^3x6iuxweoHy)4b^I@YKR)*5TZ`PYNCN?AdVoKB&^)gy@NZtclg?| zsi-T|JL1}5)mj-A5CudDQ6ynC(L%Hk#}I82RudgW2Qh)@lCW||Cqj30s_BkSQCBEc zxI#&_R>}&Zg4l(qlCYYXLQEk}Af`!JP4o~w#7&4k39HxJTUl>!^&%RtNwnVH`hTxC zr?K9~1Ce3|fv#J=tyi($NW757bzpU1hk?~g%n4W%SQFS$V9gS9;`KJ(c&pc&#OrOm zY5AgF#d;(03KMKG8Q9@9zs-kcC}ut8 zL)Wnf;yU(#*VSUvqU+cL%j=jDuY^SrSP@tmSh2*MfVF|OfgK0dE-@!yU0_{clfb$q z=EUo2alx3bW3KBuX3^zK)wqr+@k&^X0viQ(DX`HJa{@LCY!=wdfz6hf6R>$;^T1vW zY`(;tcwG%ySBg60hntGJdT3^OzLC1~v#u0Pu&$H`k?U&6x>7X3x>6oQuB##IO3?)C zN_h~uuF7qn@rqnM6m|6w!PP_R&d<71G{L%39)#5d>q^lC>q>bLxvomqm7)pOmGU6s zJo>l!_tGsl=i9QKe_ zUFyK>B`zTiUX4_ju%gZWkeAe!K&3@mA$2o{J#e50kQM_a?fX987scg!zs&Ec$jI-F z|NkSSvZA<-x6JE!DDy4^*YTEI$6MxgJd}A?gyvnnisoHK&AZwU=3S}h%o>90cmvn* z^h^+W9d8&RxQ;h)9Z$~$k=OBt0>O2>f$MmBCWyF>r+MaYVxIY%m}e}SXZ}VlnUa`i z0;>X>2Ubm(lbB}$>jFCoteY?=G0z0n2Q~!OPneUKXN+l{ab5F_Me~fRG0!N8c_y$$ zU@r!?m@p?X&jhv#?8CrT6Xqo5nZVY8eH7Sw!kh@xm7F_17v8wT8MC6Uf8L36VXMz{ zXAm=p9f(;HR?e0o8i*r^CJ8HN%MdNZF+`h$m9ynLI$F1O?|3GR<3`(DPPLQn_M|i)b*S<@dZ^+%M4-$u>&zn!fK*{XdsRt znk1|yT8I|n7@|$W%2k6mJ&WwV$vmT|^Sd{5o{@Tvs30ncIYgC&)kFu;L7YHzNmxzv z5Iw{I(I;VLo)MvWMm5bdikfFsVV;pP&p^}=2M~1>jA>SG;W6iwiZ@*vWeEqqZlfiKE~NME+_MbQMlC=ViineV$}ii{UU zjTaG&7paf+8UkPD_@ZZmNMGjoqUdeli}E1SmpQ&Dn!p$3L8LE*c}$V<;u%JHj+dB& z3iFtv3Fa~7LF7DE8qZRSCYZ;R2a)qwX(5=$3iFtr2_omQ<*r7y#*45z z)>G@L^;xry{#~zX`u(nI`h707P}dgJ7StA5v%0pTwxYJmn$@*6wKcVM)~x(a*zf(E zek#Uy(5(0LEd5keuN9+ab&Y;1y5>ImJ8xFk=%=DZfAeZ6pgalO!4UN4+`&YwZ;DC&CQoKcTHP_2PzAdVoK zB&;S{h!)})qD{ie8PJ>=eeSvTx}s+EdCav|jry$$qJo%1R7qG(bPyfH2}GBK)kF`` zLktjo5?0QDL}*4=O=m!gn$cBZMwc?9L(~ul5Ooq(6C=b3aSAaeVKq@83d9*iNy5q* zkULg3+_55WJfla)Q1!ITAn>K&i=N3Dot|nghrpMDFM1|t^d#`5;7h?5*$c!%i(q}*r__D+oJrhLwvcwlfZv$VH2a&!k@kP-Dz9(lmjPe&Oc3eIfG>*P2EHf{B7GU~MbQMlC=UW(G+3VYheQ)I*_YQ%_O#7G%25co3S%aFdHCPoN+8Sq8V ze<$HMU9vz=^4t1fv6zn5LFUZMhrv;aRSjLVP(WX z^bi9?pM;eWBSIraHH{cWjTluJF;XAxHAD?@08uAlH8Dbr5T_7h5>^uhqClKMlq9T- z7V2|dI)@3;>$99LHX1mLLVpP+JQPhZ0g%KlV#6Z*# z2M~13ce`%Rq#c55b4WuS9_`vqkYtfQPhah9x`I29uN4UXaZl92a&!k@kP-D zz9`QTliR?TCB7{2MR^eE%dqc`DKcUdwZ@2Gjgc~9An;|tmmz&YO^guuGT@7z$q|#= zC=mEE;LDJ{pz`I;#!pUfeSBy4C;F?PJI^Zm8GTn+&uGu|jJ_+ZXZZfHp5wEVp4Go4 z%jfm|W1iP{g?V11-)z%{~(|L(pz|(Z9dL^D*73=`8eBD)XzR1!`(mrIA4{%^Q=@KOI7;y|M};9USE~w zd3}VvvvG~hUSn6Uv8&hE>@_y4sGq%-yLv5mRm!gFd3IHg*;OgK`UKm2f?ZYAt31Ir zpJ1Dc+U674(kHT|Qd+9#NAIT|(^4rdy~H*zu}wv7^Ag*<#5NVR%}cq>OSw%c+tl-H zQ;*rElx<#So0oa-mwE4(+2&=osikD^hnyI$JivrrYmgr3cGrRUA@9)udrD~ZT3p;>XqD8DZ8rY z*;PGeSEcOgqipk0c2!Zk`Y79clx-?%n~!EoAI+9ZX{ny4rFu+Dr4RI{gO{}a{Na*T zohFX&~t7|Q_mRg%Ns}HPQ4PZw)$}m+&8J6lOwTfDmHR}U+lv+ov%bL}- zo?1_>&zkkYt)Cx0tEoaARZSh$a~r8&sQEDq{tE^e+ zD77`Ub=Iuz=%eoFqweUV7aet$9n}=Bj%wOgCm;1x9Xk3LrPfeuvSxLyrPfkwvu352 zS_;%rP55z)>G@L^;xregg&d9BOTRqf9uXlnNX=M zs4cQ)WkRL4qPEJKl?j#Fn%X*R)(2kXesJp3yC3LP?>wvMXIS=h+f+ZpviE~r_H?t< zzxUaalx0uPv+U{dy?mZ+KFl^B9(}_1Fw679Z1Z8Zsi>v&;ar{{<~@qbD>Q?TmlrsrE&#vk*yDDW@H`(SUyQ-*H*<_oWY*SI&+{~74 zW=o~CRL|2=J*K772Ri0|;sgIDKJb5Xao{`417BzDI`DO-t^=O4^H9C^VMDE<)@04< zT1%~^)@IGhA+NLlj}Lv`|F4SP%TOP{6}5_5l{Kqt9kq^Hmo=+vJ++=%pEc_}AM&a> za^UMZ4tyyGKD7n4Mb@kw_|#U^R#~%h;8R;uTW8Jcjy~>=KJJb_e$i29*-?GIP)GHd zLY+*2G|wa`H~#5K3} znp=DAqP5Plwfc;u*6MSWTFYmtPz}e!hFU|d$(q%*mRd`#&6@R|dwI=0*wyDVb@G}I zp3nz+wxU*1tFmTwt)tda>#}Bbt*6#g>$7HM-P317byPKVRL`;QNm=)(EvPNBW@X)@ zwxYJmnw52r+M3!rYgVs&SKZO8?&#HvjylVZ>I1eqst?ub&j5L#@f0m5x$t zskK?N(oua}S4XeX(W}`}DIKL&QLD0MrK8k3YF*Z>bd*|8t>`;o}w=5=|4MiQBTT6JqZ7oN?p{0sFJXn z@c*jR9}_^FKy*o1P53`n>W>K^28cchE0@7V=%Su#x(u$Ui+Za3*HkX*LDUcj5Ooq( zF6u#y5T_7h5>^uhqClKMlq9U*$dr9Mv#);D+xvEAe>&pHaHgK^%Na#eJBqptzK=8L z13lY7G!RD+O%hfUEkp}(4ACZGl`~tr`|6pZ`o48tQJ2B@aRyaaw{?u2+={D zKy*o1P4o~w!~oGJVdWONB6JHw)pTn~Mcu+s6>ecDxz8tb9aT^38N>`?2V$0l)kFi)Kpa6dNmxy^ z5G}+pM4N<_Td{t^tyn*iFI(3Ybt~3S@C8**w(BXbnQTHXiC=UXFDfy%j2G3Tcu^9+=nyX|F*d}D>QTHXiC$D++13RE zM^;lseQ|rs$401E!5PF1Vh3WDgq4*PqJcPqXp*q9l0vi)#}I82R#wt2R?;n2Qbnz# zTRt{ISxF%(h&e=+gq4*PqJubr=#sFql0x(l14N&Mm6cS4R#Mfpk}7HiRfUyQ%1R1R zLmWWVNmyA)Ax4N(h%pH(D=9>QID;rjSowvrJ67kT5;L8$U^h^-x z%d&&OmnFXFnIO`aWeQaX&jgXa3?l@- z4EUmFf=FM60)a0BzUY}C!WXTfua6o}68*K3X9kHU1brNtlAIazw@scIjA>>trbl{D zQ<5`-vH3ojW(H$=q?eqMoEiM0ngYBv%?!r$C|;B#X9jOgQ-Cqe494^*UX&zf24k86 zjA>>trbqFjBr!8=>IkfTsZZzGikcBNIW|y_>KVigVh3WDgw;d?(LfwQG)Y)Zv=A-C zF+`h$^?}c^H<=kWnHdx{BW!YPpv(*q6~r8(O2W#_0MS95Ky*o1nHeB@hykKc!ph7b zLNkMEni&)|GpNGMAZ2ENs38s@>Ljep3=kv4Da4qBm6-veK%7C8B&^H~?pVQ>f-lNr z%v#mcf-j294DPA&AkvqDFN!AcMR^eEOTiaK6ZoP$i1cNNFN(|zikca;hs+F8W(K{N zkC*te#24j3q%X@30$-N+qGy6gUzR-tzAW)Y&jgXa4EyewA~S1m6-toUj}>` z(ihak2!SsHzUZ0QM*1=o2z(jvMb89*FXgYlJN=%5Zp!eVhuaeUpS<72$Db+H=N}hm z0uj(1|HRvRQoWrLjb;5;^uU_f;!$ADggF6g18W024y>IpC&KO??*2|g{=P(G{r=%~ z%UgP+Mox)l2L0Rgz^cIJfmIXc1gs0J3+yDYZo-^^^?~()4T1F&=0w;-htC?*f30ikfyOks8`D&8Opo4} zrusK{#n1E!`ZIra{_Ntjvok(B*R#*`X+hDS-)5hAG=}=KS3|9#)@04G@VW_{q#T&g+pnTwh} zdu6SrR#U69X7$gF)JAG!)~v1-YK2mu-s{&fkZFBslncTeIAS zT3(0Jqi~Q!2dd7f!6e?;@GCGq3I|Di%zQ2fKevOQUpVM2uYPePYqDmQgQca`QfsqjRkxSBpUXi-KDB+0gL>r7++SAIDr!~Mtgdy`I%-|ktgiLc zdTM>vtm^i#ubLyD&Zy~ATGnc6HMKfxR{z{cZKO74&FWgAR;ZP%S$!S$8DH&thO>}o ze6{bH>}zE1tIkB8(VD1eYDe);%H7>ipJy}>4a5;dlZ4eo3(-OxL$pa)ITLw?Gm&RF z6H(Ne$TO@(C}$!N6~r8(O2W#S2t)^Q0?{R5^u<#0YT;F(zR(Q6LJ$8AM6Ks_U?K?aW>Gt8CkuyBE%o;Y`69 zMN>GV9A{9Ut>BEJ37kIaXHXLz1kNmRM$g1H(wSusfip{-(KA7$GsC_Jor}0<1I{RqvjnTpG;l`I1kNZA zBAppt-O~)EmFlu(+v0WWCwy6y7lt3ZW+@`WlZaqF+F;DTDM+i-TGLw-p8KxKE9asoaMUpv1Yw`_A%?$$97KZ zmegxgL#?6KWXKT6n4<&B9KJvNk zdK4a#Xl3)oAiE@&zK&Ci6lBJ(u=y`id=|{hU*b#lo>Tl zRE~+LcNP;B{c~v|>KZ00x|SxQYWNZp6ALBq>!zlydi$oA zuA3K2m$O{DZnAVi?I>!=y2<2*vUEW-5JwPA5>}Qjh!)})qD{ie(sh%i>n2N=qL!|k zOkJp#oeH9Ym_t-aSWR>g9mEMlmxR?s579#m5PcHXFSV%bi_p@gnwBm_EnTXxbVW3zzngg-hyX311XV;EVDg z(w8N^D4M_*knJDEnc|PvMGrVT>o3;tz9TBT&DEs*VDrF>uKRK zrlrao)52v;kA6KZT)$@FdS46I`(C)-zgW1O<-+y8=EHjSJ`30Tc1{bIRP$QhP;00) zS+lywV2n%5&k8x>ixEs8w0By4F$asC8Mhy4F+csr6a2dXd>z z%~A7{qF*o6wVGN@tD_OJp1D74tCo4ByAGq9fJqia&;sckh z(I+cY`oLvMkHSHc{J>>QpRA1O1D7#93I|F2f$IY~_<`>Hv5h1sVT>RL^$rdDUo>e@(cq&8;F>RO>zsFkc)y=v87wQ5$a+N)Nb zeT^(vty=SEJ%id&)T&jxyP=vL>jt8MID%-Bu$pKgT8LwaHVG@MR?VtaYu?(ruBcV3 zX5KlYI$#pBY(L>^VqdZm=E9({n&I~v+q%)|A5dvohoY6D6 zZsj%#1kMaNGo&-9zWDN$=Af_ma>ZAkiN3m+iJawH@|9+ydIq(lsFma^_cT; z5JwPA5>^u}LZ@_-`H;@!hSpdmF2P?$-*ho2l?;J>%i*3 z4g#wu%n8^S*cjMpVB>^20V{!(z|I0I6Xryi{!-!DQ;D$O4&kXDg{LHTVF*tpVBx7AB{q3Fgr^d)@Klcy zn>-!DQwdmjsz-^Xr~38(k3Q6y+QyIc|LN*&MSTh2NBWOpsrnyxTf0Bf|H)Gnv31>q za{Y(0RQ->;`MwE75%XV}P_BPYma0$V^^8}UnW%S6=$UvGt6!z!RVou(a}#Tc$IuFH}OSL#7*9da$W`1 zd-);0D2n(Y??pMUg6h5el=q@2;-|b9<-7{2_i~f>qUcxQy(o`Y$@lU@-ixANh4-R7 zUM1hlPkAqjeihz}@_3beFYoeR6h*wtdr{7-pn5NV}0_#^K{Ij@51z5JQ?qA23e zycgxX3aa<=F7HLrufls#9Gw9S)K>JqVtV<2DPK8^S@U#Tczr3qHZ7>h$Dz539E?~qJ=nyXp^vV z9{399fv<2LsHpS5S2XXW`W&u;s37JLRT5Sc9YhCl0?{R5HPJ)#5CcS?gq8C^5jqc4 zP3M7%IuBHZ^FXQ3;cAE);sByf!fIlK7$Hs}#w4sJ3Pgc8gD6Q@bsqSde0h!Yz}M`{ zYZtya%k#k3T|dXqJo%1R7qG(bPyfH2}GBK)kF``Lktjo5?0OwMd&O4>t&I6@B zhpQoKhy#c^39E?_VuUz_7?ZG?C=dnW45B1ql`psC%Pq#sE&Foo!WU;bUT(>kdIq(l zsPS?u$BR^5uN#O4;s~Ni!fK+0Xd#Xv+9a%ums^aNTZ|V)jh9^vEL=Q1Q^hsD5FCsKvRMU7-)Ob;a@gnuHUPIIn2M~1Zm zSWUDLEyOWIn}n6|@+#xyRmO{=#>=ZYUZg(OD~JkW4pAjxHPJzI5GN2_5>^vEL=Q1Q z^hsD5FCsKvRMU7-)Ob;a@gnuHUPIIn2M~1^u(LF~M1z!|Bs_;d5 zju(2W@xnInrQnO62_k(d_@d}-;EVDg(wF6~_Vm6Y<3&;9MSI8}a!7rwC3S1jwv!;6g6H%FkYlS*6~Hr1imN_B7GU~MbQMl zC=Vii8Sq8X1imN_B7D&up`X*$P(@wIJl|H-e*k{Y9Shaf(DNC@3}OdjmW0(r1JOVn zK{QENO|%d##4$vhgjH9v&v&2G^-@J$FFn7msJli#=Z=NyYUp_dQ9;ZhswAu?I*1P9 z1fomAYNCheAqI#(39GJ`o+|!C@A?v;#FvZCw=Mrek91H>iLX(e&jOnT zwiDQF!kmCLfi;001=dWM6R8KpiGIc zQJq(TRe{X|t0v3|SQl6q*hygBggF801M34D0_!KtiLmdSKWj|?tH*WyuO5s3SC6W` z?nvTmROgGp7Js1@>WJs|j-gwhn9^*hhh_C(Mbk&kr{?PDAYJ;r50- z)sx{ViCs9H1vYd2^TVCMW)tQFtO=|M>?p8i!kmD$fwh4h2i8uQ6Jh%Qi5vD*VowjR zTlD`EH^NgAyKqteP+Nm=my7V5`7B3~V)FPQccItpocgu=RvFv8QF@`==o` zQ;#$gO^LqSsEf!^pM9VDY^pn<-bB5LdNb9XP;aB&M!lWtPF$}yzUSAMc>5B~B2zND zFpK&u>a(ftgnAS8ChE;pcS605dK>k2syk6#XDq+eJglgd>wH^L=PSQt_E(tu$pKf8i*r^CJC#F7NUhXhG>(pa^CVw&Rc$|mFxVvqRv--$;yTLoTGxMAm$KN z5>^u(L$VdcEV9XrIALwr#lXB1ZT^blVZId5@Kl?Rc&9O8>2=PeNF zi=K;Z;L9Pt9O8@e*hcztxT`(Y%~!OKI&V?bEm*XNI-f*+&VetACh$dh5LOfTqG$qN zlm}rofiH?C@I`qLR?b`8u|s@0#24jpMq%|i2fiqB-lF)3@*u1x@I{gH7Kl|6RulN5 z$axFIIteT1E&nKA%Emvc-->zOBGoxYnNgcjn`O=FT0^a&)@04dYrdNM?K5yDZ1v@;k+elyk5=gDMroepX2ou{d0aD&Re2ZHXh^sJ*H!(Y%A(r zKE@G&>bNU2h#ABV#4HJ`i3Xy9ID%-Bu$pKgT8LwaHVLcdgXQjHeDC8i9TCgxiu&Hi zV;m8vj+tczQ9;ZhswAu?I*1P91fomAYNCheAqI#(39F8~VPC|58U8_0-~JGxZ+|F0 zqMTz3)sZvQaM$2!xC6L4Ijgx5?%&`>xKp?>Ijgw>_wR58?hLLZXVvjoDLy1Dax-c{8ElzsCvDHUy3I1 zOL-9K*A{*$n!qpRL8M<>_@!t9zmx}&e$DY~j$g{<*Brl;;}@#_&hcxGU&_tlm-67! zuQ`6r@k_Zm{8AoV`ZdR|IesZOhhNHrOTWrSb*kh4I&q_7d{sG%NIe_OsLhEph*=U= z6AiT!Vgu16VKvcG8;C7Ln}k(F&3@GEhjPyZ8>%q7NJkOuN6mgHH{sW3j!A<3sM(L2 z{ZP!ACJFYVW|Qvd>#3K5yN+ZqaujeD~5R@tNjU6_{?qYHS`@HDOM` zy1=@?P6F#D%n4W@m~PGLtqpvHMZ5(Pj*u#_DzJHA)r2_# z>jLWnI|;0tFehMrV0~aiVEu$S5vJqKn2tBsb-Y=0yr~+;n-Y$YIHKqC;my0uj2jLWnI|;0tFehMrV0~aiVEu$S5%$oqZ%h~VUDt2IEV{I>syvNE zp6cR$V0B;zfz=b{1Z)g!4D2+pal)K{mB311XMvRobE3Zk813muYj1?7``>y>8lK(= zPbK#BMtG`6;VFsDx)GjAz`|2KN^J75#kZBK`>FbE=6M6rKpa6dNmxy^5G}+pM4N^vEL=Q1Q^hsFt`_A)cMLeWE&~Mk2>-S#g zzfruTT%AkRZ`aNjaC5i?+>3CF<;Rd)h+(&ThvHWKkFQ@` z_(g_a@8Q>bb4a`Pwx01PqtJW$dHj0s1j4Spt!IL;n!vC31_-ez6~9?8i;^<0ku|T-#9eXO_@WKhJ*LWIvRf@avnfnqWU}vLDJ#`1MU#$8z@t zeedN39aUxf1%L15g=xMaV?WC51?{V%sU1a~54^y!hwAt(4MYQR1kog6HPJ$}5XTU0 z5>~$V@&dode?dpq^17nd{TDd0P#t^A3ZjCTLsUsvO>__)#0f-~gw;e3(L)RneG*o_ z_afq<;U5&W=!?*ruc(z?b$**K)$umeaM$2!xC6L4Ijgx5?%&`>xKp?>Ijgw>_wR58 z?hLLZXZ@y(@@sS#Z{XMdg{&FYnpG8url9J8;EvI^Gy;~%{Q*x z^nU!s`|VG-v51keai$MEq=P+6Ec#g|yj5fvb zTSbO4XNk~kB|@{6qGl^@;uy+o1>svo>bpk}ajVEn+%l4R3c|OF)OU{{;#QHDxMd_W z6ohXTsqY>^#H}JPamz@}P4Z=Qw{GCe{)I1O_;SOy@cd6jQ~07h=ce%G2EHhoz!&8? zHzk2DH}K^Kz9`SR3F7XiZ{exAN&Bd|N%1Y^F>6?vn;`II)3@+^Ycp=)8EV3}@Vu|+ zZQzUYoSSkRzJ=%gO?=t(Ej-^+o^un#Lwml3=Szy}*dD$p&sj;ztOS8Cd-$@KzMv+2 z3(uDny$yU(o--C z#+Di{n>k*j9u2;MqNBIt8z^d=BoQ}I)JTEw4HPwAAmRp!8ZT_)E;mrT&kYncUUcI^ zjThZgkntk*v0mw>gZH_CqQ(nE+(1#|B?;d^@xE@F$asN>8z^eLB;gw<-q%eN87~lV z14WG&h=;g=qQ;AA8ZU|(C#tZzOMR@@+Qv(YCVT@$jgus-CVT_MmlRF-28tRdNyH5l zwW34#28tRl5OD)VjTdjDjPhl4w{GCe{)I1OIbPh;8~AbqUzF!~314pDi=wxKFUoVg zB!MqC@Z|=+D9`Z%q4DC5DKcIZHD0ub@&#qQK={U%TFW8Qm(BEL6JHcf_{NrRDbMjD z^)~QD(S&bosqvCT`m*O6TWY+hrtzY9NqLSJDdPnKU-s~2FMUB7FA(^$hcA2S3u*#i P6#XjrqCCfoU*-P;F1jJp%%sjs)aH^YS$ptu0g1U XF@b8KOpw|w2(?=fYGF*ES_l&W2(w2y literal 0 HcmV?d00001 diff --git a/bddisasm_test/avx512/avx512pf_64.asm b/bddisasm_test/avx512/avx512pf_64.asm new file mode 100644 index 0000000..315b52b --- /dev/null +++ b/bddisasm_test/avx512/avx512pf_64.asm @@ -0,0 +1,18 @@ + bits 64 + + vgatherpf0dpd [rbx+ymm17*8+0x1000]{k5} + vgatherpf0dps [rbx+zmm27*8+0x1000]{k5} + vgatherpf0qpd [rbx+zmm27*8+0x1000]{k5} + vgatherpf0qps [rbx+zmm27*8+0x1000]{k5} + vgatherpf1dpd [rbx+ymm17*8+0x1000]{k5} + vgatherpf1dps [rbx+zmm27*8+0x1000]{k5} + vgatherpf1qpd [rbx+zmm27*8+0x1000]{k5} + vgatherpf1qps [rbx+zmm27*8+0x1000]{k5} + vscatterpf0dpd [rbx+ymm17*8+0x1000]{k5} + vscatterpf0dps [rbx+zmm27*8+0x1000]{k5} + vscatterpf0qpd [rbx+zmm27*8+0x1000]{k5} + vscatterpf0qps [rbx+zmm27*8+0x1000]{k5} + vscatterpf1dpd [rbx+ymm17*8+0x1000]{k5} + vscatterpf1dps [rbx+zmm27*8+0x1000]{k5} + vscatterpf1qpd [rbx+zmm27*8+0x1000]{k5} + vscatterpf1qps [rbx+zmm27*8+0x1000]{k5} diff --git a/bddisasm_test/avx512/avx512pf_64.result b/bddisasm_test/avx512/avx512pf_64.result new file mode 100644 index 0000000..bcf562e --- /dev/null +++ b/bddisasm_test/avx512/avx512pf_64.result @@ -0,0 +1,320 @@ +0000000000000000 62f2fd45c68ccb00100000 VGATHERPF0DPD zmmword ptr [rbx+ymm17*8+0x1000]{k5} + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: AVX512PF, Ins cat: GATHER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E12NP + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, VSIB Addressing: yes, + Segment: 3, Base: 3, Index: 17 * 8, Displacement: 0x0000000000001000, + VSIB index size: 4, VSIB element size: 8, VSIB element count: 8 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + +000000000000000B 62b27d45c68cdb00100000 VGATHERPF0DPS zmmword ptr [rbx+zmm27*8+0x1000]{k5} + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512PF, Ins cat: GATHER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E12NP + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, VSIB Addressing: yes, + Segment: 3, Base: 3, Index: 27 * 8, Displacement: 0x0000000000001000, + VSIB index size: 4, VSIB element size: 4, VSIB element count: 16 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + +0000000000000016 62b2fd45c78cdb00100000 VGATHERPF0QPD zmmword ptr [rbx+zmm27*8+0x1000]{k5} + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: AVX512PF, Ins cat: GATHER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E12NP + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, VSIB Addressing: yes, + Segment: 3, Base: 3, Index: 27 * 8, Displacement: 0x0000000000001000, + VSIB index size: 8, VSIB element size: 8, VSIB element count: 8 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + +0000000000000021 62b27d45c78cdb00100000 VGATHERPF0QPS ymmword ptr [rbx+zmm27*8+0x1000]{k5} + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512PF, Ins cat: GATHER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E12NP + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, VSIB Addressing: yes, + Segment: 3, Base: 3, Index: 27 * 8, Displacement: 0x0000000000001000, + VSIB index size: 8, VSIB element size: 4, VSIB element count: 8 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + +000000000000002C 62f2fd45c694cb00100000 VGATHERPF1DPD zmmword ptr [rbx+ymm17*8+0x1000]{k5} + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: AVX512PF, Ins cat: GATHER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E12NP + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, VSIB Addressing: yes, + Segment: 3, Base: 3, Index: 17 * 8, Displacement: 0x0000000000001000, + VSIB index size: 4, VSIB element size: 8, VSIB element count: 8 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + +0000000000000037 62b27d45c694db00100000 VGATHERPF1DPS zmmword ptr [rbx+zmm27*8+0x1000]{k5} + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512PF, Ins cat: GATHER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E12NP + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, VSIB Addressing: yes, + Segment: 3, Base: 3, Index: 27 * 8, Displacement: 0x0000000000001000, + VSIB index size: 4, VSIB element size: 4, VSIB element count: 16 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + +0000000000000042 62b2fd45c794db00100000 VGATHERPF1QPD zmmword ptr [rbx+zmm27*8+0x1000]{k5} + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: AVX512PF, Ins cat: GATHER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E12NP + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, VSIB Addressing: yes, + Segment: 3, Base: 3, Index: 27 * 8, Displacement: 0x0000000000001000, + VSIB index size: 8, VSIB element size: 8, VSIB element count: 8 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + +000000000000004D 62b27d45c794db00100000 VGATHERPF1QPS ymmword ptr [rbx+zmm27*8+0x1000]{k5} + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512PF, Ins cat: GATHER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E12NP + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, VSIB Addressing: yes, + Segment: 3, Base: 3, Index: 27 * 8, Displacement: 0x0000000000001000, + VSIB index size: 8, VSIB element size: 4, VSIB element count: 8 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + +0000000000000058 62f2fd45c6accb00100000 VSCATTERPF0DPD zmmword ptr [rbx+ymm17*8+0x1000]{k5} + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: AVX512PF, Ins cat: SCATTER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E12NP + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, VSIB Addressing: yes, + Segment: 3, Base: 3, Index: 17 * 8, Displacement: 0x0000000000001000, + VSIB index size: 4, VSIB element size: 8, VSIB element count: 8 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + +0000000000000063 62b27d45c6acdb00100000 VSCATTERPF0DPS zmmword ptr [rbx+zmm27*8+0x1000]{k5} + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512PF, Ins cat: SCATTER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E12NP + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, VSIB Addressing: yes, + Segment: 3, Base: 3, Index: 27 * 8, Displacement: 0x0000000000001000, + VSIB index size: 4, VSIB element size: 4, VSIB element count: 16 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + +000000000000006E 62b2fd45c7acdb00100000 VSCATTERPF0QPD zmmword ptr [rbx+zmm27*8+0x1000]{k5} + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: AVX512PF, Ins cat: SCATTER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E12NP + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, VSIB Addressing: yes, + Segment: 3, Base: 3, Index: 27 * 8, Displacement: 0x0000000000001000, + VSIB index size: 8, VSIB element size: 8, VSIB element count: 8 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + +0000000000000079 62b27d45c7acdb00100000 VSCATTERPF0QPS ymmword ptr [rbx+zmm27*8+0x1000]{k5} + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512PF, Ins cat: SCATTER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E12NP + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, VSIB Addressing: yes, + Segment: 3, Base: 3, Index: 27 * 8, Displacement: 0x0000000000001000, + VSIB index size: 8, VSIB element size: 4, VSIB element count: 8 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + +0000000000000084 62f2fd45c6b4cb00100000 VSCATTERPF1DPD zmmword ptr [rbx+ymm17*8+0x1000]{k5} + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: AVX512PF, Ins cat: SCATTER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E12NP + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, VSIB Addressing: yes, + Segment: 3, Base: 3, Index: 17 * 8, Displacement: 0x0000000000001000, + VSIB index size: 4, VSIB element size: 8, VSIB element count: 8 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + +000000000000008F 62b27d45c6b4db00100000 VSCATTERPF1DPS zmmword ptr [rbx+zmm27*8+0x1000]{k5} + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512PF, Ins cat: SCATTER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E12NP + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, VSIB Addressing: yes, + Segment: 3, Base: 3, Index: 27 * 8, Displacement: 0x0000000000001000, + VSIB index size: 4, VSIB element size: 4, VSIB element count: 16 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + +000000000000009A 62b2fd45c7b4db00100000 VSCATTERPF1QPD zmmword ptr [rbx+zmm27*8+0x1000]{k5} + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: AVX512PF, Ins cat: SCATTER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E12NP + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, VSIB Addressing: yes, + Segment: 3, Base: 3, Index: 27 * 8, Displacement: 0x0000000000001000, + VSIB index size: 8, VSIB element size: 8, VSIB element count: 8 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + +00000000000000A5 62b27d45c7b4db00100000 VSCATTERPF1QPS ymmword ptr [rbx+zmm27*8+0x1000]{k5} + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AVX512PF, Ins cat: SCATTER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E12NP + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, VSIB Addressing: yes, + Segment: 3, Base: 3, Index: 27 * 8, Displacement: 0x0000000000001000, + VSIB index size: 8, VSIB element size: 4, VSIB element count: 8 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + diff --git a/bddisasm_test/avx512/avx512vbmi_64 b/bddisasm_test/avx512/avx512vbmi_64 new file mode 100644 index 0000000..ead1987 --- /dev/null +++ b/bddisasm_test/avx512/avx512vbmi_64 @@ -0,0 +1 @@ +b}cb}(cb}Hcb}cb}(cbb}Hcb}cT@b}(cD@b"}HcD@b}cTb}(cDb"}HcDbcb(cbHcbcb(cbbHcbcT b(cD b"HcD bcTb(cDb"HcDbEbEbETbETbE bE bE TbE TbEbEbETbETbEbEbETbETb(b(b(Db(Db-b-b-Db-DbbbDbDbbbDbDb=@bb=@b"=@Db"=@Db=Ebb=Eb"=EDb"=EDb=bb=b"=Db"=Db=ōbb=ōb"=ōDb"=ōDbEubEubEuTbEuTbE ubE ubE uTbE uTbEubEubEuTbEuTbEubEubEuTbEuTb(ub(ub(uDb(uDb-ub-ub-uDb-uDbububuDbuDbububuDbuDb=@ubb=@ub"=@uDb"=@uDb=Eubb=Eub"=EuDb"=EuDb=ubb=ub"=uDb"=uDb=ubb=ub"=uDb"=uDbE}bE}bE}TbE}TbE }bE }bE }TbE }TbE}bE}bE}TbE}TbE}bE}bE}TbE}Tb(}b(}b(}Db(}Db-}b-}b-}Db-}Db}b}b}Db}Db}b}b}Db}Db=@}bb=@}b"=@}Db"=@}Db=E}bb=E}b"=E}Db"=E}Db=}bb=}b"=}Db"=}Db=}bb=}b"=}Db"=}Db}bb} bb}bb}bb2}(bb2}-bb2}bb2}bb}Hbb}Mbb}bb}bbbb bbbbbb2(bb2-bb2bb2bbHbbMbbbbbbbbbTbTb b bb Tb TbňbňbŘbňTbňTbōbōbŝbōTbōTb•(b(b8b(Db(Db•-b-b=b-Db-Db•b╨b╸bDbDb•b╭b╽bDbDb@bb@bbPb"@Db"@DbEbbEbbUb"EDb"EDbbbbbЃb"Db"DbŃbbŃbbՃb"ŃDb"ŃDbEqАbEqbEqbEqTbEqTbE qАbE qbEqbE qTbE qTbEqАbEqbEqbEqTbEqTbEqАbEqbEqbEqTbEqTb(qǐb(qb8qb(qDb(qDb-qǐb-qb=qb-qDb-qDbqǐbqbqbqDbqDbqǐbqbqbqDbqDb=@qǐbc=@qbc=Pqb#=@qDb#=@qDb=Eqǐbc=Eqbc=Uqb#=EqDb#=EqDb=qǐbc=qbc=qb#=qDb#=qDb=qǐbc=qbc=qb#=qDb#=qDbqАbqbqbqTbqTb qАb qbqb qTb qTbňqАbňqbŘqbňqTbňqTbōqАbōqbŝqbōqTbōqTbÕ(qǐb(qb8qb(qDb(qDbÕ-qǐb-qb=qb-qDb-qDbÕqǐb㕨qb㕸qbqDbqDbÕqǐb㕭qb㕽qbqDbqDb@qǐbc@qbcPqb#@qDb#@qDbEqǐbcEqbcUqb#EqDb#EqDbqǐbcqbcqb#qDb#qDbqǐbcqbcqb#qDb#qDbEqАbEqbEqbEqTbEqTbE qАbE qbEqbE qTbE qTbEqАbEqbEqbEqTbEqTbEqАbEqbEqbEqTbEqTb(qǐb(qb8qb(qDb(qDb-qǐb-qb=qb-qDb-qDbqǐbqbqbqDbqDbqǐbqbqbqDbqDb=@qǐbb=@qbb=Pqb"=@qDb"=@qDb=Eqǐbb=Eqbb=Uqb"=EqDb"=EqDb=qǐbb=qbb=qb"=qDb"=qDb=qǐbb=qbb=qb"=qDb"=qDbqАbqbqbqTbqTb qАb qbqb qTb qTbňqАbňqbŘqbňqTbňqTbōqАbōqbŝqbōqTbōqTb•(qǐb(qb8qb(qDb(qDb•-qǐb-qb=qb-qDb-qDb•qǐb╨qb╸qbqDbqDb•qǐb╭qb╽qbqDbqDb@qǐbb@qbbPqb"@qDb"@qDbEqǐbbEqbbUqb"EqDb"EqDbqǐbbqbbqb"qDb"qDbqǐbbqbbqb"qDb"qDbpАbpbpTbpTb pАb pb pTb pTbňpАbňpbňpTbňpTbōpАbōpbōpTbōpTb•(pǐb(pb(pDb(pDb•-pǐb-pb-pDb-pDb•pǐb╨pbpDbpDb•pǐb╭pbpDbpDb@pǐbb@pb"@pDb"@pDbEpǐbbEpb"EpDb"EpDbpǐbbpb"pDb"pDbpǐbbpb"pDb"pDbpАbpbpTbpTb pАb pb pTb pTbňpАbňpbňpTbňpTbōpАbōpbōpTbōpTbÕ(pǐb(pb(pDb(pDbÕ-pǐb-pb-pDb-pDbÕpǐb㕨pbpDbpDbÕpǐb㕭pbpDbpDb@pǐbc@pb#@pDb#@pDbEpǐbcEpb#EpDb#EpDbpǐbcpb#pDb#pDbpǐbcpb#pDb#pDbEsАbEsbEsbEsTbEsTbE sАbE sbEsbE sTbE sTbEsАbEsbEsbEsTbEsTbEsАbEsbEsbEsTbEsTb(sǐb(sb8sb(sDb(sDb-sǐb-sb=sb-sDb-sDbsǐbsbsbsDbsDbsǐbsbsbsDbsDb=@sǐbc=@sbc=Psb#=@sDb#=@sDb=Esǐbc=Esbc=Usb#=EsDb#=EsDb=sǐbc=sbc=sb#=sDb#=sDb=sǐbc=sbc=sb#=sDb#=sDbsАbsbsbsTbsTb sАb sbsb sTb sTbňsАbňsbŘsbňsTbňsTbōsАbōsbŝsbōsTbōsTbÕ(sǐb(sb8sb(sDb(sDbÕ-sǐb-sb=sb-sDb-sDbÕsǐb㕨sb㕸sbsDbsDbÕsǐb㕭sb㕽sbsDbsDb@sǐbc@sbcPsb#@sDb#@sDbEsǐbcEsbcUsb#EsDb#EsDbsǐbcsbcsb#sDb#sDbsǐbcsbcsb#sDb#sDbEsАbEsbEsbEsTbEsTbE sАbE sbEsbE sTbE sTbEsАbEsbEsbEsTbEsTbEsАbEsbEsbEsTbEsTb(sǐb(sb8sb(sDb(sDb-sǐb-sb=sb-sDb-sDbsǐbsbsbsDbsDbsǐbsbsbsDbsDb=@sǐbb=@sbb=Psb"=@sDb"=@sDb=Esǐbb=Esbb=Usb"=EsDb"=EsDb=sǐbb=sbb=sb"=sDb"=sDb=sǐbb=sbb=sb"=sDb"=sDbsАbsbsbsTbsTb sАb sbsb sTb sTbňsАbňsbŘsbňsTbňsTbōsАbōsbŝsbōsTbōsTb•(sǐb(sb8sb(sDb(sDb•-sǐb-sb=sb-sDb-sDb•sǐb╨sb╸sbsDbsDb•sǐb╭sb╽sbsDbsDb@sǐbb@sbbPsb"@sDb"@sDbEsǐbbEsbbUsb"EsDb"EsDbsǐbbsbbsb"sDb"sDbsǐbbsbbsb"sDb"sDbrАbrbrTbrTb rАb rb rTb rTbňrАbňrbňrTbňrTbōrАbōrbōrTbōrTb•(rǐb(rb(rDb(rDb•-rǐb-rb-rDb-rDb•rǐb╨rbrDbrDb•rǐb╭rbrDbrDb@rǐbb@rb"@rDb"@rDbErǐbbErb"ErDb"ErDbrǐbbrb"rDb"rDbrǐbbrb"rDb"rDbrАbrbrTbrTb rАb rb rTb rTbňrАbňrbňrTbňrTbōrАbōrbōrTbōrTbÕ(rǐb(rb(rDb(rDbÕ-rǐb-rb-rDb-rDbÕrǐb㕨rbrDbrDbÕrǐb㕭rbrDbrDb@rǐbc@rb#@rDb#@rDbErǐbcErb#ErDb#ErDbrǐbcrb#rDb#rDbrǐbcrb#rDb#rD \ No newline at end of file diff --git a/bddisasm_test/avx512/avx512vbmi_64.asm b/bddisasm_test/avx512/avx512vbmi_64.asm new file mode 100644 index 0000000..2fc865f --- /dev/null +++ b/bddisasm_test/avx512/avx512vbmi_64.asm @@ -0,0 +1,926 @@ + bits 64 + + vpcompressb xmm0, xmm2 + vpcompressb ymm15, ymm16 + vpcompressb zmm31, zmm24 + vpcompressb [rbx], xmm2 + vpcompressb [rbx], ymm16 + vpcompressb [rbx], zmm24 + vpcompressb [rbx+r11*8+256], xmm2 + vpcompressb [rbx+r11*8+256], ymm16 + vpcompressb [rbx+r11*8+256], zmm24 + vpcompressb [rbx+r11*8-256], xmm2 + vpcompressb [rbx+r11*8-256], ymm16 + vpcompressb [rbx+r11*8-256], zmm24 + vpcompressw xmm0, xmm2 + vpcompressw ymm15, ymm16 + vpcompressw zmm31, zmm24 + vpcompressw [rbx], xmm2 + vpcompressw [rbx], ymm16 + vpcompressw [rbx], zmm24 + vpcompressw [rbx+r11*8+256], xmm2 + vpcompressw [rbx+r11*8+256], ymm16 + vpcompressw [rbx+r11*8+256], zmm24 + vpcompressw [rbx+r11*8-256], xmm2 + vpcompressw [rbx+r11*8-256], ymm16 + vpcompressw [rbx+r11*8-256], zmm24 + vpermb xmm2, xmm7, xmm0 + vpermb xmm2, xmm7, [rbx] + vpermb xmm2, xmm7, [rbx+r11*8+256] + vpermb xmm2, xmm7, [rbx+r11*8-256] + vpermb xmm2{k5}, xmm7, xmm0 + vpermb xmm2{k5}, xmm7, [rbx] + vpermb xmm2{k5}, xmm7, [rbx+r11*8+256] + vpermb xmm2{k5}, xmm7, [rbx+r11*8-256] + vpermb xmm2{z}, xmm7, xmm0 + vpermb xmm2{z}, xmm7, [rbx] + vpermb xmm2{z}, xmm7, [rbx+r11*8+256] + vpermb xmm2{z}, xmm7, [rbx+r11*8-256] + vpermb xmm2{k5}{z}, xmm7, xmm0 + vpermb xmm2{k5}{z}, xmm7, [rbx] + vpermb xmm2{k5}{z}, xmm7, [rbx+r11*8+256] + vpermb xmm2{k5}{z}, xmm7, [rbx+r11*8-256] + vpermb ymm16, ymm13, ymm15 + vpermb ymm16, ymm13, [rbx] + vpermb ymm16, ymm13, [rbx+r11*8+256] + vpermb ymm16, ymm13, [rbx+r11*8-256] + vpermb ymm16{k5}, ymm13, ymm15 + vpermb ymm16{k5}, ymm13, [rbx] + vpermb ymm16{k5}, ymm13, [rbx+r11*8+256] + vpermb ymm16{k5}, ymm13, [rbx+r11*8-256] + vpermb ymm16{z}, ymm13, ymm15 + vpermb ymm16{z}, ymm13, [rbx] + vpermb ymm16{z}, ymm13, [rbx+r11*8+256] + vpermb ymm16{z}, ymm13, [rbx+r11*8-256] + vpermb ymm16{k5}{z}, ymm13, ymm15 + vpermb ymm16{k5}{z}, ymm13, [rbx] + vpermb ymm16{k5}{z}, ymm13, [rbx+r11*8+256] + vpermb ymm16{k5}{z}, ymm13, [rbx+r11*8-256] + vpermb zmm24, zmm24, zmm31 + vpermb zmm24, zmm24, [rbx] + vpermb zmm24, zmm24, [rbx+r11*8+256] + vpermb zmm24, zmm24, [rbx+r11*8-256] + vpermb zmm24{k5}, zmm24, zmm31 + vpermb zmm24{k5}, zmm24, [rbx] + vpermb zmm24{k5}, zmm24, [rbx+r11*8+256] + vpermb zmm24{k5}, zmm24, [rbx+r11*8-256] + vpermb zmm24{z}, zmm24, zmm31 + vpermb zmm24{z}, zmm24, [rbx] + vpermb zmm24{z}, zmm24, [rbx+r11*8+256] + vpermb zmm24{z}, zmm24, [rbx+r11*8-256] + vpermb zmm24{k5}{z}, zmm24, zmm31 + vpermb zmm24{k5}{z}, zmm24, [rbx] + vpermb zmm24{k5}{z}, zmm24, [rbx+r11*8+256] + vpermb zmm24{k5}{z}, zmm24, [rbx+r11*8-256] + vpermi2b xmm2, xmm7, xmm0 + vpermi2b xmm2, xmm7, [rbx] + vpermi2b xmm2, xmm7, [rbx+r11*8+256] + vpermi2b xmm2, xmm7, [rbx+r11*8-256] + vpermi2b xmm2{k5}, xmm7, xmm0 + vpermi2b xmm2{k5}, xmm7, [rbx] + vpermi2b xmm2{k5}, xmm7, [rbx+r11*8+256] + vpermi2b xmm2{k5}, xmm7, [rbx+r11*8-256] + vpermi2b xmm2{z}, xmm7, xmm0 + vpermi2b xmm2{z}, xmm7, [rbx] + vpermi2b xmm2{z}, xmm7, [rbx+r11*8+256] + vpermi2b xmm2{z}, xmm7, [rbx+r11*8-256] + vpermi2b xmm2{k5}{z}, xmm7, xmm0 + vpermi2b xmm2{k5}{z}, xmm7, [rbx] + vpermi2b xmm2{k5}{z}, xmm7, [rbx+r11*8+256] + vpermi2b xmm2{k5}{z}, xmm7, [rbx+r11*8-256] + vpermi2b ymm16, ymm13, ymm15 + vpermi2b ymm16, ymm13, [rbx] + vpermi2b ymm16, ymm13, [rbx+r11*8+256] + vpermi2b ymm16, ymm13, [rbx+r11*8-256] + vpermi2b ymm16{k5}, ymm13, ymm15 + vpermi2b ymm16{k5}, ymm13, [rbx] + vpermi2b ymm16{k5}, ymm13, [rbx+r11*8+256] + vpermi2b ymm16{k5}, ymm13, [rbx+r11*8-256] + vpermi2b ymm16{z}, ymm13, ymm15 + vpermi2b ymm16{z}, ymm13, [rbx] + vpermi2b ymm16{z}, ymm13, [rbx+r11*8+256] + vpermi2b ymm16{z}, ymm13, [rbx+r11*8-256] + vpermi2b ymm16{k5}{z}, ymm13, ymm15 + vpermi2b ymm16{k5}{z}, ymm13, [rbx] + vpermi2b ymm16{k5}{z}, ymm13, [rbx+r11*8+256] + vpermi2b ymm16{k5}{z}, ymm13, [rbx+r11*8-256] + vpermi2b zmm24, zmm24, zmm31 + vpermi2b zmm24, zmm24, [rbx] + vpermi2b zmm24, zmm24, [rbx+r11*8+256] + vpermi2b zmm24, zmm24, [rbx+r11*8-256] + vpermi2b zmm24{k5}, zmm24, zmm31 + vpermi2b zmm24{k5}, zmm24, [rbx] + vpermi2b zmm24{k5}, zmm24, [rbx+r11*8+256] + vpermi2b zmm24{k5}, zmm24, [rbx+r11*8-256] + vpermi2b zmm24{z}, zmm24, zmm31 + vpermi2b zmm24{z}, zmm24, [rbx] + vpermi2b zmm24{z}, zmm24, [rbx+r11*8+256] + vpermi2b zmm24{z}, zmm24, [rbx+r11*8-256] + vpermi2b zmm24{k5}{z}, zmm24, zmm31 + vpermi2b zmm24{k5}{z}, zmm24, [rbx] + vpermi2b zmm24{k5}{z}, zmm24, [rbx+r11*8+256] + vpermi2b zmm24{k5}{z}, zmm24, [rbx+r11*8-256] + vpermt2b xmm2, xmm7, xmm0 + vpermt2b xmm2, xmm7, [rbx] + vpermt2b xmm2, xmm7, [rbx+r11*8+256] + vpermt2b xmm2, xmm7, [rbx+r11*8-256] + vpermt2b xmm2{k5}, xmm7, xmm0 + vpermt2b xmm2{k5}, xmm7, [rbx] + vpermt2b xmm2{k5}, xmm7, [rbx+r11*8+256] + vpermt2b xmm2{k5}, xmm7, [rbx+r11*8-256] + vpermt2b xmm2{z}, xmm7, xmm0 + vpermt2b xmm2{z}, xmm7, [rbx] + vpermt2b xmm2{z}, xmm7, [rbx+r11*8+256] + vpermt2b xmm2{z}, xmm7, [rbx+r11*8-256] + vpermt2b xmm2{k5}{z}, xmm7, xmm0 + vpermt2b xmm2{k5}{z}, xmm7, [rbx] + vpermt2b xmm2{k5}{z}, xmm7, [rbx+r11*8+256] + vpermt2b xmm2{k5}{z}, xmm7, [rbx+r11*8-256] + vpermt2b ymm16, ymm13, ymm15 + vpermt2b ymm16, ymm13, [rbx] + vpermt2b ymm16, ymm13, [rbx+r11*8+256] + vpermt2b ymm16, ymm13, [rbx+r11*8-256] + vpermt2b ymm16{k5}, ymm13, ymm15 + vpermt2b ymm16{k5}, ymm13, [rbx] + vpermt2b ymm16{k5}, ymm13, [rbx+r11*8+256] + vpermt2b ymm16{k5}, ymm13, [rbx+r11*8-256] + vpermt2b ymm16{z}, ymm13, ymm15 + vpermt2b ymm16{z}, ymm13, [rbx] + vpermt2b ymm16{z}, ymm13, [rbx+r11*8+256] + vpermt2b ymm16{z}, ymm13, [rbx+r11*8-256] + vpermt2b ymm16{k5}{z}, ymm13, ymm15 + vpermt2b ymm16{k5}{z}, ymm13, [rbx] + vpermt2b ymm16{k5}{z}, ymm13, [rbx+r11*8+256] + vpermt2b ymm16{k5}{z}, ymm13, [rbx+r11*8-256] + vpermt2b zmm24, zmm24, zmm31 + vpermt2b zmm24, zmm24, [rbx] + vpermt2b zmm24, zmm24, [rbx+r11*8+256] + vpermt2b zmm24, zmm24, [rbx+r11*8-256] + vpermt2b zmm24{k5}, zmm24, zmm31 + vpermt2b zmm24{k5}, zmm24, [rbx] + vpermt2b zmm24{k5}, zmm24, [rbx+r11*8+256] + vpermt2b zmm24{k5}, zmm24, [rbx+r11*8-256] + vpermt2b zmm24{z}, zmm24, zmm31 + vpermt2b zmm24{z}, zmm24, [rbx] + vpermt2b zmm24{z}, zmm24, [rbx+r11*8+256] + vpermt2b zmm24{z}, zmm24, [rbx+r11*8-256] + vpermt2b zmm24{k5}{z}, zmm24, zmm31 + vpermt2b zmm24{k5}{z}, zmm24, [rbx] + vpermt2b zmm24{k5}{z}, zmm24, [rbx+r11*8+256] + vpermt2b zmm24{k5}{z}, zmm24, [rbx+r11*8-256] + vpexpandb xmm2, xmm0 + vpexpandb xmm2{k5}, xmm0 + vpexpandb xmm2{z}, xmm0 + vpexpandb xmm2{k5}{z}, xmm0 + vpexpandb ymm16, ymm15 + vpexpandb ymm16{k5}, ymm15 + vpexpandb ymm16{z}, ymm15 + vpexpandb ymm16{k5}{z}, ymm15 + vpexpandb zmm24, zmm31 + vpexpandb zmm24{k5}, zmm31 + vpexpandb zmm24{z}, zmm31 + vpexpandb zmm24{k5}{z}, zmm31 + vpexpandw xmm2, xmm0 + vpexpandw xmm2{k5}, xmm0 + vpexpandw xmm2{z}, xmm0 + vpexpandw xmm2{k5}{z}, xmm0 + vpexpandw ymm16, ymm15 + vpexpandw ymm16{k5}, ymm15 + vpexpandw ymm16{z}, ymm15 + vpexpandw ymm16{k5}{z}, ymm15 + vpexpandw zmm24, zmm31 + vpexpandw zmm24{k5}, zmm31 + vpexpandw zmm24{z}, zmm31 + vpexpandw zmm24{k5}{z}, zmm31 + vpmultishiftqb xmm2, xmm7, xmm0 + vpmultishiftqb xmm2, xmm7, [rbx] + vpmultishiftqb xmm2, xmm7, [rbx]{1to2} + vpmultishiftqb xmm2, xmm7, [rbx+r11*8+256] + vpmultishiftqb xmm2, xmm7, [rbx+r11*8-256] + vpmultishiftqb xmm2{k5}, xmm7, xmm0 + vpmultishiftqb xmm2{k5}, xmm7, [rbx] + vpmultishiftqb xmm2{k5}, xmm7, [rbx]{1to2} + vpmultishiftqb xmm2{k5}, xmm7, [rbx+r11*8+256] + vpmultishiftqb xmm2{k5}, xmm7, [rbx+r11*8-256] + vpmultishiftqb xmm2{z}, xmm7, xmm0 + vpmultishiftqb xmm2{z}, xmm7, [rbx] + vpmultishiftqb xmm2{z}, xmm7, [rbx]{1to2} + vpmultishiftqb xmm2{z}, xmm7, [rbx+r11*8+256] + vpmultishiftqb xmm2{z}, xmm7, [rbx+r11*8-256] + vpmultishiftqb xmm2{k5}{z}, xmm7, xmm0 + vpmultishiftqb xmm2{k5}{z}, xmm7, [rbx] + vpmultishiftqb xmm2{k5}{z}, xmm7, [rbx]{1to2} + vpmultishiftqb xmm2{k5}{z}, xmm7, [rbx+r11*8+256] + vpmultishiftqb xmm2{k5}{z}, xmm7, [rbx+r11*8-256] + vpmultishiftqb ymm16, ymm13, ymm15 + vpmultishiftqb ymm16, ymm13, [rbx] + vpmultishiftqb ymm16, ymm13, [rbx]{1to4} + vpmultishiftqb ymm16, ymm13, [rbx+r11*8+256] + vpmultishiftqb ymm16, ymm13, [rbx+r11*8-256] + vpmultishiftqb ymm16{k5}, ymm13, ymm15 + vpmultishiftqb ymm16{k5}, ymm13, [rbx] + vpmultishiftqb ymm16{k5}, ymm13, [rbx]{1to4} + vpmultishiftqb ymm16{k5}, ymm13, [rbx+r11*8+256] + vpmultishiftqb ymm16{k5}, ymm13, [rbx+r11*8-256] + vpmultishiftqb ymm16{z}, ymm13, ymm15 + vpmultishiftqb ymm16{z}, ymm13, [rbx] + vpmultishiftqb ymm16{z}, ymm13, [rbx]{1to4} + vpmultishiftqb ymm16{z}, ymm13, [rbx+r11*8+256] + vpmultishiftqb ymm16{z}, ymm13, [rbx+r11*8-256] + vpmultishiftqb ymm16{k5}{z}, ymm13, ymm15 + vpmultishiftqb ymm16{k5}{z}, ymm13, [rbx] + vpmultishiftqb ymm16{k5}{z}, ymm13, [rbx]{1to4} + vpmultishiftqb ymm16{k5}{z}, ymm13, [rbx+r11*8+256] + vpmultishiftqb ymm16{k5}{z}, ymm13, [rbx+r11*8-256] + vpmultishiftqb zmm24, zmm24, zmm31 + vpmultishiftqb zmm24, zmm24, [rbx] + vpmultishiftqb zmm24, zmm24, [rbx]{1to8} + vpmultishiftqb zmm24, zmm24, [rbx+r11*8+256] + vpmultishiftqb zmm24, zmm24, [rbx+r11*8-256] + vpmultishiftqb zmm24{k5}, zmm24, zmm31 + vpmultishiftqb zmm24{k5}, zmm24, [rbx] + vpmultishiftqb zmm24{k5}, zmm24, [rbx]{1to8} + vpmultishiftqb zmm24{k5}, zmm24, [rbx+r11*8+256] + vpmultishiftqb zmm24{k5}, zmm24, [rbx+r11*8-256] + vpmultishiftqb zmm24{z}, zmm24, zmm31 + vpmultishiftqb zmm24{z}, zmm24, [rbx] + vpmultishiftqb zmm24{z}, zmm24, [rbx]{1to8} + vpmultishiftqb zmm24{z}, zmm24, [rbx+r11*8+256] + vpmultishiftqb zmm24{z}, zmm24, [rbx+r11*8-256] + vpmultishiftqb zmm24{k5}{z}, zmm24, zmm31 + vpmultishiftqb zmm24{k5}{z}, zmm24, [rbx] + vpmultishiftqb zmm24{k5}{z}, zmm24, [rbx]{1to8} + vpmultishiftqb zmm24{k5}{z}, zmm24, [rbx+r11*8+256] + vpmultishiftqb zmm24{k5}{z}, zmm24, [rbx+r11*8-256] + vpshldd xmm2, xmm7, xmm0, 0x90 + vpshldd xmm2, xmm7, [rbx], 0x90 + vpshldd xmm2, xmm7, [rbx]{1to4}, 0x90 + vpshldd xmm2, xmm7, [rbx+r11*8+256], 0x90 + vpshldd xmm2, xmm7, [rbx+r11*8-256], 0x90 + vpshldd xmm2{k5}, xmm7, xmm0, 0x90 + vpshldd xmm2{k5}, xmm7, [rbx], 0x90 + vpshldd xmm2{k5}, xmm7, [rbx]{1to4}, 0x90 + vpshldd xmm2{k5}, xmm7, [rbx+r11*8+256], 0x90 + vpshldd xmm2{k5}, xmm7, [rbx+r11*8-256], 0x90 + vpshldd xmm2{z}, xmm7, xmm0, 0x90 + vpshldd xmm2{z}, xmm7, [rbx], 0x90 + vpshldd xmm2{z}, xmm7, [rbx]{1to4}, 0x90 + vpshldd xmm2{z}, xmm7, [rbx+r11*8+256], 0x90 + vpshldd xmm2{z}, xmm7, [rbx+r11*8-256], 0x90 + vpshldd xmm2{k5}{z}, xmm7, xmm0, 0x90 + vpshldd xmm2{k5}{z}, xmm7, [rbx], 0x90 + vpshldd xmm2{k5}{z}, xmm7, [rbx]{1to4}, 0x90 + vpshldd xmm2{k5}{z}, xmm7, [rbx+r11*8+256], 0x90 + vpshldd xmm2{k5}{z}, xmm7, [rbx+r11*8-256], 0x90 + vpshldd ymm16, ymm13, ymm15, 0x90 + vpshldd ymm16, ymm13, [rbx], 0x90 + vpshldd ymm16, ymm13, [rbx]{1to8}, 0x90 + vpshldd ymm16, ymm13, [rbx+r11*8+256], 0x90 + vpshldd ymm16, ymm13, [rbx+r11*8-256], 0x90 + vpshldd ymm16{k5}, ymm13, ymm15, 0x90 + vpshldd ymm16{k5}, ymm13, [rbx], 0x90 + vpshldd ymm16{k5}, ymm13, [rbx]{1to8}, 0x90 + vpshldd ymm16{k5}, ymm13, [rbx+r11*8+256], 0x90 + vpshldd ymm16{k5}, ymm13, [rbx+r11*8-256], 0x90 + vpshldd ymm16{z}, ymm13, ymm15, 0x90 + vpshldd ymm16{z}, ymm13, [rbx], 0x90 + vpshldd ymm16{z}, ymm13, [rbx]{1to8}, 0x90 + vpshldd ymm16{z}, ymm13, [rbx+r11*8+256], 0x90 + vpshldd ymm16{z}, ymm13, [rbx+r11*8-256], 0x90 + vpshldd ymm16{k5}{z}, ymm13, ymm15, 0x90 + vpshldd ymm16{k5}{z}, ymm13, [rbx], 0x90 + vpshldd ymm16{k5}{z}, ymm13, [rbx]{1to8}, 0x90 + vpshldd ymm16{k5}{z}, ymm13, [rbx+r11*8+256], 0x90 + vpshldd ymm16{k5}{z}, ymm13, [rbx+r11*8-256], 0x90 + vpshldd zmm24, zmm24, zmm31, 0x90 + vpshldd zmm24, zmm24, [rbx], 0x90 + vpshldd zmm24, zmm24, [rbx]{1to16}, 0x90 + vpshldd zmm24, zmm24, [rbx+r11*8+256], 0x90 + vpshldd zmm24, zmm24, [rbx+r11*8-256], 0x90 + vpshldd zmm24{k5}, zmm24, zmm31, 0x90 + vpshldd zmm24{k5}, zmm24, [rbx], 0x90 + vpshldd zmm24{k5}, zmm24, [rbx]{1to16}, 0x90 + vpshldd zmm24{k5}, zmm24, [rbx+r11*8+256], 0x90 + vpshldd zmm24{k5}, zmm24, [rbx+r11*8-256], 0x90 + vpshldd zmm24{z}, zmm24, zmm31, 0x90 + vpshldd zmm24{z}, zmm24, [rbx], 0x90 + vpshldd zmm24{z}, zmm24, [rbx]{1to16}, 0x90 + vpshldd zmm24{z}, zmm24, [rbx+r11*8+256], 0x90 + vpshldd zmm24{z}, zmm24, [rbx+r11*8-256], 0x90 + vpshldd zmm24{k5}{z}, zmm24, zmm31, 0x90 + vpshldd zmm24{k5}{z}, zmm24, [rbx], 0x90 + vpshldd zmm24{k5}{z}, zmm24, [rbx]{1to16}, 0x90 + vpshldd zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 0x90 + vpshldd zmm24{k5}{z}, zmm24, [rbx+r11*8-256], 0x90 + vpshldq xmm2, xmm7, xmm0, 0x90 + vpshldq xmm2, xmm7, [rbx], 0x90 + vpshldq xmm2, xmm7, [rbx]{1to2}, 0x90 + vpshldq xmm2, xmm7, [rbx+r11*8+256], 0x90 + vpshldq xmm2, xmm7, [rbx+r11*8-256], 0x90 + vpshldq xmm2{k5}, xmm7, xmm0, 0x90 + vpshldq xmm2{k5}, xmm7, [rbx], 0x90 + vpshldq xmm2{k5}, xmm7, [rbx]{1to2}, 0x90 + vpshldq xmm2{k5}, xmm7, [rbx+r11*8+256], 0x90 + vpshldq xmm2{k5}, xmm7, [rbx+r11*8-256], 0x90 + vpshldq xmm2{z}, xmm7, xmm0, 0x90 + vpshldq xmm2{z}, xmm7, [rbx], 0x90 + vpshldq xmm2{z}, xmm7, [rbx]{1to2}, 0x90 + vpshldq xmm2{z}, xmm7, [rbx+r11*8+256], 0x90 + vpshldq xmm2{z}, xmm7, [rbx+r11*8-256], 0x90 + vpshldq xmm2{k5}{z}, xmm7, xmm0, 0x90 + vpshldq xmm2{k5}{z}, xmm7, [rbx], 0x90 + vpshldq xmm2{k5}{z}, xmm7, [rbx]{1to2}, 0x90 + vpshldq xmm2{k5}{z}, xmm7, [rbx+r11*8+256], 0x90 + vpshldq xmm2{k5}{z}, xmm7, [rbx+r11*8-256], 0x90 + vpshldq ymm16, ymm13, ymm15, 0x90 + vpshldq ymm16, ymm13, [rbx], 0x90 + vpshldq ymm16, ymm13, [rbx]{1to4}, 0x90 + vpshldq ymm16, ymm13, [rbx+r11*8+256], 0x90 + vpshldq ymm16, ymm13, [rbx+r11*8-256], 0x90 + vpshldq ymm16{k5}, ymm13, ymm15, 0x90 + vpshldq ymm16{k5}, ymm13, [rbx], 0x90 + vpshldq ymm16{k5}, ymm13, [rbx]{1to4}, 0x90 + vpshldq ymm16{k5}, ymm13, [rbx+r11*8+256], 0x90 + vpshldq ymm16{k5}, ymm13, [rbx+r11*8-256], 0x90 + vpshldq ymm16{z}, ymm13, ymm15, 0x90 + vpshldq ymm16{z}, ymm13, [rbx], 0x90 + vpshldq ymm16{z}, ymm13, [rbx]{1to4}, 0x90 + vpshldq ymm16{z}, ymm13, [rbx+r11*8+256], 0x90 + vpshldq ymm16{z}, ymm13, [rbx+r11*8-256], 0x90 + vpshldq ymm16{k5}{z}, ymm13, ymm15, 0x90 + vpshldq ymm16{k5}{z}, ymm13, [rbx], 0x90 + vpshldq ymm16{k5}{z}, ymm13, [rbx]{1to4}, 0x90 + vpshldq ymm16{k5}{z}, ymm13, [rbx+r11*8+256], 0x90 + vpshldq ymm16{k5}{z}, ymm13, [rbx+r11*8-256], 0x90 + vpshldq zmm24, zmm24, zmm31, 0x90 + vpshldq zmm24, zmm24, [rbx], 0x90 + vpshldq zmm24, zmm24, [rbx]{1to8}, 0x90 + vpshldq zmm24, zmm24, [rbx+r11*8+256], 0x90 + vpshldq zmm24, zmm24, [rbx+r11*8-256], 0x90 + vpshldq zmm24{k5}, zmm24, zmm31, 0x90 + vpshldq zmm24{k5}, zmm24, [rbx], 0x90 + vpshldq zmm24{k5}, zmm24, [rbx]{1to8}, 0x90 + vpshldq zmm24{k5}, zmm24, [rbx+r11*8+256], 0x90 + vpshldq zmm24{k5}, zmm24, [rbx+r11*8-256], 0x90 + vpshldq zmm24{z}, zmm24, zmm31, 0x90 + vpshldq zmm24{z}, zmm24, [rbx], 0x90 + vpshldq zmm24{z}, zmm24, [rbx]{1to8}, 0x90 + vpshldq zmm24{z}, zmm24, [rbx+r11*8+256], 0x90 + vpshldq zmm24{z}, zmm24, [rbx+r11*8-256], 0x90 + vpshldq zmm24{k5}{z}, zmm24, zmm31, 0x90 + vpshldq zmm24{k5}{z}, zmm24, [rbx], 0x90 + vpshldq zmm24{k5}{z}, zmm24, [rbx]{1to8}, 0x90 + vpshldq zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 0x90 + vpshldq zmm24{k5}{z}, zmm24, [rbx+r11*8-256], 0x90 + vpshldvd xmm2, xmm7, xmm0 + vpshldvd xmm2, xmm7, [rbx] + vpshldvd xmm2, xmm7, [rbx]{1to4} + vpshldvd xmm2, xmm7, [rbx+r11*8+256] + vpshldvd xmm2, xmm7, [rbx+r11*8-256] + vpshldvd xmm2{k5}, xmm7, xmm0 + vpshldvd xmm2{k5}, xmm7, [rbx] + vpshldvd xmm2{k5}, xmm7, [rbx]{1to4} + vpshldvd xmm2{k5}, xmm7, [rbx+r11*8+256] + vpshldvd xmm2{k5}, xmm7, [rbx+r11*8-256] + vpshldvd xmm2{z}, xmm7, xmm0 + vpshldvd xmm2{z}, xmm7, [rbx] + vpshldvd xmm2{z}, xmm7, [rbx]{1to4} + vpshldvd xmm2{z}, xmm7, [rbx+r11*8+256] + vpshldvd xmm2{z}, xmm7, [rbx+r11*8-256] + vpshldvd xmm2{k5}{z}, xmm7, xmm0 + vpshldvd xmm2{k5}{z}, xmm7, [rbx] + vpshldvd xmm2{k5}{z}, xmm7, [rbx]{1to4} + vpshldvd xmm2{k5}{z}, xmm7, [rbx+r11*8+256] + vpshldvd xmm2{k5}{z}, xmm7, [rbx+r11*8-256] + vpshldvd ymm16, ymm13, ymm15 + vpshldvd ymm16, ymm13, [rbx] + vpshldvd ymm16, ymm13, [rbx]{1to8} + vpshldvd ymm16, ymm13, [rbx+r11*8+256] + vpshldvd ymm16, ymm13, [rbx+r11*8-256] + vpshldvd ymm16{k5}, ymm13, ymm15 + vpshldvd ymm16{k5}, ymm13, [rbx] + vpshldvd ymm16{k5}, ymm13, [rbx]{1to8} + vpshldvd ymm16{k5}, ymm13, [rbx+r11*8+256] + vpshldvd ymm16{k5}, ymm13, [rbx+r11*8-256] + vpshldvd ymm16{z}, ymm13, ymm15 + vpshldvd ymm16{z}, ymm13, [rbx] + vpshldvd ymm16{z}, ymm13, [rbx]{1to8} + vpshldvd ymm16{z}, ymm13, [rbx+r11*8+256] + vpshldvd ymm16{z}, ymm13, [rbx+r11*8-256] + vpshldvd ymm16{k5}{z}, ymm13, ymm15 + vpshldvd ymm16{k5}{z}, ymm13, [rbx] + vpshldvd ymm16{k5}{z}, ymm13, [rbx]{1to8} + vpshldvd ymm16{k5}{z}, ymm13, [rbx+r11*8+256] + vpshldvd ymm16{k5}{z}, ymm13, [rbx+r11*8-256] + vpshldvd zmm24, zmm24, zmm31 + vpshldvd zmm24, zmm24, [rbx] + vpshldvd zmm24, zmm24, [rbx]{1to16} + vpshldvd zmm24, zmm24, [rbx+r11*8+256] + vpshldvd zmm24, zmm24, [rbx+r11*8-256] + vpshldvd zmm24{k5}, zmm24, zmm31 + vpshldvd zmm24{k5}, zmm24, [rbx] + vpshldvd zmm24{k5}, zmm24, [rbx]{1to16} + vpshldvd zmm24{k5}, zmm24, [rbx+r11*8+256] + vpshldvd zmm24{k5}, zmm24, [rbx+r11*8-256] + vpshldvd zmm24{z}, zmm24, zmm31 + vpshldvd zmm24{z}, zmm24, [rbx] + vpshldvd zmm24{z}, zmm24, [rbx]{1to16} + vpshldvd zmm24{z}, zmm24, [rbx+r11*8+256] + vpshldvd zmm24{z}, zmm24, [rbx+r11*8-256] + vpshldvd zmm24{k5}{z}, zmm24, zmm31 + vpshldvd zmm24{k5}{z}, zmm24, [rbx] + vpshldvd zmm24{k5}{z}, zmm24, [rbx]{1to16} + vpshldvd zmm24{k5}{z}, zmm24, [rbx+r11*8+256] + vpshldvd zmm24{k5}{z}, zmm24, [rbx+r11*8-256] + vpshldvq xmm2, xmm7, xmm0 + vpshldvq xmm2, xmm7, [rbx] + vpshldvq xmm2, xmm7, [rbx]{1to2} + vpshldvq xmm2, xmm7, [rbx+r11*8+256] + vpshldvq xmm2, xmm7, [rbx+r11*8-256] + vpshldvq xmm2{k5}, xmm7, xmm0 + vpshldvq xmm2{k5}, xmm7, [rbx] + vpshldvq xmm2{k5}, xmm7, [rbx]{1to2} + vpshldvq xmm2{k5}, xmm7, [rbx+r11*8+256] + vpshldvq xmm2{k5}, xmm7, [rbx+r11*8-256] + vpshldvq xmm2{z}, xmm7, xmm0 + vpshldvq xmm2{z}, xmm7, [rbx] + vpshldvq xmm2{z}, xmm7, [rbx]{1to2} + vpshldvq xmm2{z}, xmm7, [rbx+r11*8+256] + vpshldvq xmm2{z}, xmm7, [rbx+r11*8-256] + vpshldvq xmm2{k5}{z}, xmm7, xmm0 + vpshldvq xmm2{k5}{z}, xmm7, [rbx] + vpshldvq xmm2{k5}{z}, xmm7, [rbx]{1to2} + vpshldvq xmm2{k5}{z}, xmm7, [rbx+r11*8+256] + vpshldvq xmm2{k5}{z}, xmm7, [rbx+r11*8-256] + vpshldvq ymm16, ymm13, ymm15 + vpshldvq ymm16, ymm13, [rbx] + vpshldvq ymm16, ymm13, [rbx]{1to4} + vpshldvq ymm16, ymm13, [rbx+r11*8+256] + vpshldvq ymm16, ymm13, [rbx+r11*8-256] + vpshldvq ymm16{k5}, ymm13, ymm15 + vpshldvq ymm16{k5}, ymm13, [rbx] + vpshldvq ymm16{k5}, ymm13, [rbx]{1to4} + vpshldvq ymm16{k5}, ymm13, [rbx+r11*8+256] + vpshldvq ymm16{k5}, ymm13, [rbx+r11*8-256] + vpshldvq ymm16{z}, ymm13, ymm15 + vpshldvq ymm16{z}, ymm13, [rbx] + vpshldvq ymm16{z}, ymm13, [rbx]{1to4} + vpshldvq ymm16{z}, ymm13, [rbx+r11*8+256] + vpshldvq ymm16{z}, ymm13, [rbx+r11*8-256] + vpshldvq ymm16{k5}{z}, ymm13, ymm15 + vpshldvq ymm16{k5}{z}, ymm13, [rbx] + vpshldvq ymm16{k5}{z}, ymm13, [rbx]{1to4} + vpshldvq ymm16{k5}{z}, ymm13, [rbx+r11*8+256] + vpshldvq ymm16{k5}{z}, ymm13, [rbx+r11*8-256] + vpshldvq zmm24, zmm24, zmm31 + vpshldvq zmm24, zmm24, [rbx] + vpshldvq zmm24, zmm24, [rbx]{1to8} + vpshldvq zmm24, zmm24, [rbx+r11*8+256] + vpshldvq zmm24, zmm24, [rbx+r11*8-256] + vpshldvq zmm24{k5}, zmm24, zmm31 + vpshldvq zmm24{k5}, zmm24, [rbx] + vpshldvq zmm24{k5}, zmm24, [rbx]{1to8} + vpshldvq zmm24{k5}, zmm24, [rbx+r11*8+256] + vpshldvq zmm24{k5}, zmm24, [rbx+r11*8-256] + vpshldvq zmm24{z}, zmm24, zmm31 + vpshldvq zmm24{z}, zmm24, [rbx] + vpshldvq zmm24{z}, zmm24, [rbx]{1to8} + vpshldvq zmm24{z}, zmm24, [rbx+r11*8+256] + vpshldvq zmm24{z}, zmm24, [rbx+r11*8-256] + vpshldvq zmm24{k5}{z}, zmm24, zmm31 + vpshldvq zmm24{k5}{z}, zmm24, [rbx] + vpshldvq zmm24{k5}{z}, zmm24, [rbx]{1to8} + vpshldvq zmm24{k5}{z}, zmm24, [rbx+r11*8+256] + vpshldvq zmm24{k5}{z}, zmm24, [rbx+r11*8-256] + vpshldvw xmm2, xmm7, xmm0 + vpshldvw xmm2, xmm7, [rbx] + vpshldvw xmm2, xmm7, [rbx+r11*8+256] + vpshldvw xmm2, xmm7, [rbx+r11*8-256] + vpshldvw xmm2{k5}, xmm7, xmm0 + vpshldvw xmm2{k5}, xmm7, [rbx] + vpshldvw xmm2{k5}, xmm7, [rbx+r11*8+256] + vpshldvw xmm2{k5}, xmm7, [rbx+r11*8-256] + vpshldvw xmm2{z}, xmm7, xmm0 + vpshldvw xmm2{z}, xmm7, [rbx] + vpshldvw xmm2{z}, xmm7, [rbx+r11*8+256] + vpshldvw xmm2{z}, xmm7, [rbx+r11*8-256] + vpshldvw xmm2{k5}{z}, xmm7, xmm0 + vpshldvw xmm2{k5}{z}, xmm7, [rbx] + vpshldvw xmm2{k5}{z}, xmm7, [rbx+r11*8+256] + vpshldvw xmm2{k5}{z}, xmm7, [rbx+r11*8-256] + vpshldvw ymm16, ymm13, ymm15 + vpshldvw ymm16, ymm13, [rbx] + vpshldvw ymm16, ymm13, [rbx+r11*8+256] + vpshldvw ymm16, ymm13, [rbx+r11*8-256] + vpshldvw ymm16{k5}, ymm13, ymm15 + vpshldvw ymm16{k5}, ymm13, [rbx] + vpshldvw ymm16{k5}, ymm13, [rbx+r11*8+256] + vpshldvw ymm16{k5}, ymm13, [rbx+r11*8-256] + vpshldvw ymm16{z}, ymm13, ymm15 + vpshldvw ymm16{z}, ymm13, [rbx] + vpshldvw ymm16{z}, ymm13, [rbx+r11*8+256] + vpshldvw ymm16{z}, ymm13, [rbx+r11*8-256] + vpshldvw ymm16{k5}{z}, ymm13, ymm15 + vpshldvw ymm16{k5}{z}, ymm13, [rbx] + vpshldvw ymm16{k5}{z}, ymm13, [rbx+r11*8+256] + vpshldvw ymm16{k5}{z}, ymm13, [rbx+r11*8-256] + vpshldvw zmm24, zmm24, zmm31 + vpshldvw zmm24, zmm24, [rbx] + vpshldvw zmm24, zmm24, [rbx+r11*8+256] + vpshldvw zmm24, zmm24, [rbx+r11*8-256] + vpshldvw zmm24{k5}, zmm24, zmm31 + vpshldvw zmm24{k5}, zmm24, [rbx] + vpshldvw zmm24{k5}, zmm24, [rbx+r11*8+256] + vpshldvw zmm24{k5}, zmm24, [rbx+r11*8-256] + vpshldvw zmm24{z}, zmm24, zmm31 + vpshldvw zmm24{z}, zmm24, [rbx] + vpshldvw zmm24{z}, zmm24, [rbx+r11*8+256] + vpshldvw zmm24{z}, zmm24, [rbx+r11*8-256] + vpshldvw zmm24{k5}{z}, zmm24, zmm31 + vpshldvw zmm24{k5}{z}, zmm24, [rbx] + vpshldvw zmm24{k5}{z}, zmm24, [rbx+r11*8+256] + vpshldvw zmm24{k5}{z}, zmm24, [rbx+r11*8-256] + vpshldw xmm2, xmm7, xmm0, 0x90 + vpshldw xmm2, xmm7, [rbx], 0x90 + vpshldw xmm2, xmm7, [rbx+r11*8+256], 0x90 + vpshldw xmm2, xmm7, [rbx+r11*8-256], 0x90 + vpshldw xmm2{k5}, xmm7, xmm0, 0x90 + vpshldw xmm2{k5}, xmm7, [rbx], 0x90 + vpshldw xmm2{k5}, xmm7, [rbx+r11*8+256], 0x90 + vpshldw xmm2{k5}, xmm7, [rbx+r11*8-256], 0x90 + vpshldw xmm2{z}, xmm7, xmm0, 0x90 + vpshldw xmm2{z}, xmm7, [rbx], 0x90 + vpshldw xmm2{z}, xmm7, [rbx+r11*8+256], 0x90 + vpshldw xmm2{z}, xmm7, [rbx+r11*8-256], 0x90 + vpshldw xmm2{k5}{z}, xmm7, xmm0, 0x90 + vpshldw xmm2{k5}{z}, xmm7, [rbx], 0x90 + vpshldw xmm2{k5}{z}, xmm7, [rbx+r11*8+256], 0x90 + vpshldw xmm2{k5}{z}, xmm7, [rbx+r11*8-256], 0x90 + vpshldw ymm16, ymm13, ymm15, 0x90 + vpshldw ymm16, ymm13, [rbx], 0x90 + vpshldw ymm16, ymm13, [rbx+r11*8+256], 0x90 + vpshldw ymm16, ymm13, [rbx+r11*8-256], 0x90 + vpshldw ymm16{k5}, ymm13, ymm15, 0x90 + vpshldw ymm16{k5}, ymm13, [rbx], 0x90 + vpshldw ymm16{k5}, ymm13, [rbx+r11*8+256], 0x90 + vpshldw ymm16{k5}, ymm13, [rbx+r11*8-256], 0x90 + vpshldw ymm16{z}, ymm13, ymm15, 0x90 + vpshldw ymm16{z}, ymm13, [rbx], 0x90 + vpshldw ymm16{z}, ymm13, [rbx+r11*8+256], 0x90 + vpshldw ymm16{z}, ymm13, [rbx+r11*8-256], 0x90 + vpshldw ymm16{k5}{z}, ymm13, ymm15, 0x90 + vpshldw ymm16{k5}{z}, ymm13, [rbx], 0x90 + vpshldw ymm16{k5}{z}, ymm13, [rbx+r11*8+256], 0x90 + vpshldw ymm16{k5}{z}, ymm13, [rbx+r11*8-256], 0x90 + vpshldw zmm24, zmm24, zmm31, 0x90 + vpshldw zmm24, zmm24, [rbx], 0x90 + vpshldw zmm24, zmm24, [rbx+r11*8+256], 0x90 + vpshldw zmm24, zmm24, [rbx+r11*8-256], 0x90 + vpshldw zmm24{k5}, zmm24, zmm31, 0x90 + vpshldw zmm24{k5}, zmm24, [rbx], 0x90 + vpshldw zmm24{k5}, zmm24, [rbx+r11*8+256], 0x90 + vpshldw zmm24{k5}, zmm24, [rbx+r11*8-256], 0x90 + vpshldw zmm24{z}, zmm24, zmm31, 0x90 + vpshldw zmm24{z}, zmm24, [rbx], 0x90 + vpshldw zmm24{z}, zmm24, [rbx+r11*8+256], 0x90 + vpshldw zmm24{z}, zmm24, [rbx+r11*8-256], 0x90 + vpshldw zmm24{k5}{z}, zmm24, zmm31, 0x90 + vpshldw zmm24{k5}{z}, zmm24, [rbx], 0x90 + vpshldw zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 0x90 + vpshldw zmm24{k5}{z}, zmm24, [rbx+r11*8-256], 0x90 + vpshrdd xmm2, xmm7, xmm0, 0x90 + vpshrdd xmm2, xmm7, [rbx], 0x90 + vpshrdd xmm2, xmm7, [rbx]{1to4}, 0x90 + vpshrdd xmm2, xmm7, [rbx+r11*8+256], 0x90 + vpshrdd xmm2, xmm7, [rbx+r11*8-256], 0x90 + vpshrdd xmm2{k5}, xmm7, xmm0, 0x90 + vpshrdd xmm2{k5}, xmm7, [rbx], 0x90 + vpshrdd xmm2{k5}, xmm7, [rbx]{1to4}, 0x90 + vpshrdd xmm2{k5}, xmm7, [rbx+r11*8+256], 0x90 + vpshrdd xmm2{k5}, xmm7, [rbx+r11*8-256], 0x90 + vpshrdd xmm2{z}, xmm7, xmm0, 0x90 + vpshrdd xmm2{z}, xmm7, [rbx], 0x90 + vpshrdd xmm2{z}, xmm7, [rbx]{1to4}, 0x90 + vpshrdd xmm2{z}, xmm7, [rbx+r11*8+256], 0x90 + vpshrdd xmm2{z}, xmm7, [rbx+r11*8-256], 0x90 + vpshrdd xmm2{k5}{z}, xmm7, xmm0, 0x90 + vpshrdd xmm2{k5}{z}, xmm7, [rbx], 0x90 + vpshrdd xmm2{k5}{z}, xmm7, [rbx]{1to4}, 0x90 + vpshrdd xmm2{k5}{z}, xmm7, [rbx+r11*8+256], 0x90 + vpshrdd xmm2{k5}{z}, xmm7, [rbx+r11*8-256], 0x90 + vpshrdd ymm16, ymm13, ymm15, 0x90 + vpshrdd ymm16, ymm13, [rbx], 0x90 + vpshrdd ymm16, ymm13, [rbx]{1to8}, 0x90 + vpshrdd ymm16, ymm13, [rbx+r11*8+256], 0x90 + vpshrdd ymm16, ymm13, [rbx+r11*8-256], 0x90 + vpshrdd ymm16{k5}, ymm13, ymm15, 0x90 + vpshrdd ymm16{k5}, ymm13, [rbx], 0x90 + vpshrdd ymm16{k5}, ymm13, [rbx]{1to8}, 0x90 + vpshrdd ymm16{k5}, ymm13, [rbx+r11*8+256], 0x90 + vpshrdd ymm16{k5}, ymm13, [rbx+r11*8-256], 0x90 + vpshrdd ymm16{z}, ymm13, ymm15, 0x90 + vpshrdd ymm16{z}, ymm13, [rbx], 0x90 + vpshrdd ymm16{z}, ymm13, [rbx]{1to8}, 0x90 + vpshrdd ymm16{z}, ymm13, [rbx+r11*8+256], 0x90 + vpshrdd ymm16{z}, ymm13, [rbx+r11*8-256], 0x90 + vpshrdd ymm16{k5}{z}, ymm13, ymm15, 0x90 + vpshrdd ymm16{k5}{z}, ymm13, [rbx], 0x90 + vpshrdd ymm16{k5}{z}, ymm13, [rbx]{1to8}, 0x90 + vpshrdd ymm16{k5}{z}, ymm13, [rbx+r11*8+256], 0x90 + vpshrdd ymm16{k5}{z}, ymm13, [rbx+r11*8-256], 0x90 + vpshrdd zmm24, zmm24, zmm31, 0x90 + vpshrdd zmm24, zmm24, [rbx], 0x90 + vpshrdd zmm24, zmm24, [rbx]{1to16}, 0x90 + vpshrdd zmm24, zmm24, [rbx+r11*8+256], 0x90 + vpshrdd zmm24, zmm24, [rbx+r11*8-256], 0x90 + vpshrdd zmm24{k5}, zmm24, zmm31, 0x90 + vpshrdd zmm24{k5}, zmm24, [rbx], 0x90 + vpshrdd zmm24{k5}, zmm24, [rbx]{1to16}, 0x90 + vpshrdd zmm24{k5}, zmm24, [rbx+r11*8+256], 0x90 + vpshrdd zmm24{k5}, zmm24, [rbx+r11*8-256], 0x90 + vpshrdd zmm24{z}, zmm24, zmm31, 0x90 + vpshrdd zmm24{z}, zmm24, [rbx], 0x90 + vpshrdd zmm24{z}, zmm24, [rbx]{1to16}, 0x90 + vpshrdd zmm24{z}, zmm24, [rbx+r11*8+256], 0x90 + vpshrdd zmm24{z}, zmm24, [rbx+r11*8-256], 0x90 + vpshrdd zmm24{k5}{z}, zmm24, zmm31, 0x90 + vpshrdd zmm24{k5}{z}, zmm24, [rbx], 0x90 + vpshrdd zmm24{k5}{z}, zmm24, [rbx]{1to16}, 0x90 + vpshrdd zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 0x90 + vpshrdd zmm24{k5}{z}, zmm24, [rbx+r11*8-256], 0x90 + vpshrdq xmm2, xmm7, xmm0, 0x90 + vpshrdq xmm2, xmm7, [rbx], 0x90 + vpshrdq xmm2, xmm7, [rbx]{1to2}, 0x90 + vpshrdq xmm2, xmm7, [rbx+r11*8+256], 0x90 + vpshrdq xmm2, xmm7, [rbx+r11*8-256], 0x90 + vpshrdq xmm2{k5}, xmm7, xmm0, 0x90 + vpshrdq xmm2{k5}, xmm7, [rbx], 0x90 + vpshrdq xmm2{k5}, xmm7, [rbx]{1to2}, 0x90 + vpshrdq xmm2{k5}, xmm7, [rbx+r11*8+256], 0x90 + vpshrdq xmm2{k5}, xmm7, [rbx+r11*8-256], 0x90 + vpshrdq xmm2{z}, xmm7, xmm0, 0x90 + vpshrdq xmm2{z}, xmm7, [rbx], 0x90 + vpshrdq xmm2{z}, xmm7, [rbx]{1to2}, 0x90 + vpshrdq xmm2{z}, xmm7, [rbx+r11*8+256], 0x90 + vpshrdq xmm2{z}, xmm7, [rbx+r11*8-256], 0x90 + vpshrdq xmm2{k5}{z}, xmm7, xmm0, 0x90 + vpshrdq xmm2{k5}{z}, xmm7, [rbx], 0x90 + vpshrdq xmm2{k5}{z}, xmm7, [rbx]{1to2}, 0x90 + vpshrdq xmm2{k5}{z}, xmm7, [rbx+r11*8+256], 0x90 + vpshrdq xmm2{k5}{z}, xmm7, [rbx+r11*8-256], 0x90 + vpshrdq ymm16, ymm13, ymm15, 0x90 + vpshrdq ymm16, ymm13, [rbx], 0x90 + vpshrdq ymm16, ymm13, [rbx]{1to4}, 0x90 + vpshrdq ymm16, ymm13, [rbx+r11*8+256], 0x90 + vpshrdq ymm16, ymm13, [rbx+r11*8-256], 0x90 + vpshrdq ymm16{k5}, ymm13, ymm15, 0x90 + vpshrdq ymm16{k5}, ymm13, [rbx], 0x90 + vpshrdq ymm16{k5}, ymm13, [rbx]{1to4}, 0x90 + vpshrdq ymm16{k5}, ymm13, [rbx+r11*8+256], 0x90 + vpshrdq ymm16{k5}, ymm13, [rbx+r11*8-256], 0x90 + vpshrdq ymm16{z}, ymm13, ymm15, 0x90 + vpshrdq ymm16{z}, ymm13, [rbx], 0x90 + vpshrdq ymm16{z}, ymm13, [rbx]{1to4}, 0x90 + vpshrdq ymm16{z}, ymm13, [rbx+r11*8+256], 0x90 + vpshrdq ymm16{z}, ymm13, [rbx+r11*8-256], 0x90 + vpshrdq ymm16{k5}{z}, ymm13, ymm15, 0x90 + vpshrdq ymm16{k5}{z}, ymm13, [rbx], 0x90 + vpshrdq ymm16{k5}{z}, ymm13, [rbx]{1to4}, 0x90 + vpshrdq ymm16{k5}{z}, ymm13, [rbx+r11*8+256], 0x90 + vpshrdq ymm16{k5}{z}, ymm13, [rbx+r11*8-256], 0x90 + vpshrdq zmm24, zmm24, zmm31, 0x90 + vpshrdq zmm24, zmm24, [rbx], 0x90 + vpshrdq zmm24, zmm24, [rbx]{1to8}, 0x90 + vpshrdq zmm24, zmm24, [rbx+r11*8+256], 0x90 + vpshrdq zmm24, zmm24, [rbx+r11*8-256], 0x90 + vpshrdq zmm24{k5}, zmm24, zmm31, 0x90 + vpshrdq zmm24{k5}, zmm24, [rbx], 0x90 + vpshrdq zmm24{k5}, zmm24, [rbx]{1to8}, 0x90 + vpshrdq zmm24{k5}, zmm24, [rbx+r11*8+256], 0x90 + vpshrdq zmm24{k5}, zmm24, [rbx+r11*8-256], 0x90 + vpshrdq zmm24{z}, zmm24, zmm31, 0x90 + vpshrdq zmm24{z}, zmm24, [rbx], 0x90 + vpshrdq zmm24{z}, zmm24, [rbx]{1to8}, 0x90 + vpshrdq zmm24{z}, zmm24, [rbx+r11*8+256], 0x90 + vpshrdq zmm24{z}, zmm24, [rbx+r11*8-256], 0x90 + vpshrdq zmm24{k5}{z}, zmm24, zmm31, 0x90 + vpshrdq zmm24{k5}{z}, zmm24, [rbx], 0x90 + vpshrdq zmm24{k5}{z}, zmm24, [rbx]{1to8}, 0x90 + vpshrdq zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 0x90 + vpshrdq zmm24{k5}{z}, zmm24, [rbx+r11*8-256], 0x90 + vpshrdvd xmm2, xmm7, xmm0 + vpshrdvd xmm2, xmm7, [rbx] + vpshrdvd xmm2, xmm7, [rbx]{1to4} + vpshrdvd xmm2, xmm7, [rbx+r11*8+256] + vpshrdvd xmm2, xmm7, [rbx+r11*8-256] + vpshrdvd xmm2{k5}, xmm7, xmm0 + vpshrdvd xmm2{k5}, xmm7, [rbx] + vpshrdvd xmm2{k5}, xmm7, [rbx]{1to4} + vpshrdvd xmm2{k5}, xmm7, [rbx+r11*8+256] + vpshrdvd xmm2{k5}, xmm7, [rbx+r11*8-256] + vpshrdvd xmm2{z}, xmm7, xmm0 + vpshrdvd xmm2{z}, xmm7, [rbx] + vpshrdvd xmm2{z}, xmm7, [rbx]{1to4} + vpshrdvd xmm2{z}, xmm7, [rbx+r11*8+256] + vpshrdvd xmm2{z}, xmm7, [rbx+r11*8-256] + vpshrdvd xmm2{k5}{z}, xmm7, xmm0 + vpshrdvd xmm2{k5}{z}, xmm7, [rbx] + vpshrdvd xmm2{k5}{z}, xmm7, [rbx]{1to4} + vpshrdvd xmm2{k5}{z}, xmm7, [rbx+r11*8+256] + vpshrdvd xmm2{k5}{z}, xmm7, [rbx+r11*8-256] + vpshrdvd ymm16, ymm13, ymm15 + vpshrdvd ymm16, ymm13, [rbx] + vpshrdvd ymm16, ymm13, [rbx]{1to8} + vpshrdvd ymm16, ymm13, [rbx+r11*8+256] + vpshrdvd ymm16, ymm13, [rbx+r11*8-256] + vpshrdvd ymm16{k5}, ymm13, ymm15 + vpshrdvd ymm16{k5}, ymm13, [rbx] + vpshrdvd ymm16{k5}, ymm13, [rbx]{1to8} + vpshrdvd ymm16{k5}, ymm13, [rbx+r11*8+256] + vpshrdvd ymm16{k5}, ymm13, [rbx+r11*8-256] + vpshrdvd ymm16{z}, ymm13, ymm15 + vpshrdvd ymm16{z}, ymm13, [rbx] + vpshrdvd ymm16{z}, ymm13, [rbx]{1to8} + vpshrdvd ymm16{z}, ymm13, [rbx+r11*8+256] + vpshrdvd ymm16{z}, ymm13, [rbx+r11*8-256] + vpshrdvd ymm16{k5}{z}, ymm13, ymm15 + vpshrdvd ymm16{k5}{z}, ymm13, [rbx] + vpshrdvd ymm16{k5}{z}, ymm13, [rbx]{1to8} + vpshrdvd ymm16{k5}{z}, ymm13, [rbx+r11*8+256] + vpshrdvd ymm16{k5}{z}, ymm13, [rbx+r11*8-256] + vpshrdvd zmm24, zmm24, zmm31 + vpshrdvd zmm24, zmm24, [rbx] + vpshrdvd zmm24, zmm24, [rbx]{1to16} + vpshrdvd zmm24, zmm24, [rbx+r11*8+256] + vpshrdvd zmm24, zmm24, [rbx+r11*8-256] + vpshrdvd zmm24{k5}, zmm24, zmm31 + vpshrdvd zmm24{k5}, zmm24, [rbx] + vpshrdvd zmm24{k5}, zmm24, [rbx]{1to16} + vpshrdvd zmm24{k5}, zmm24, [rbx+r11*8+256] + vpshrdvd zmm24{k5}, zmm24, [rbx+r11*8-256] + vpshrdvd zmm24{z}, zmm24, zmm31 + vpshrdvd zmm24{z}, zmm24, [rbx] + vpshrdvd zmm24{z}, zmm24, [rbx]{1to16} + vpshrdvd zmm24{z}, zmm24, [rbx+r11*8+256] + vpshrdvd zmm24{z}, zmm24, [rbx+r11*8-256] + vpshrdvd zmm24{k5}{z}, zmm24, zmm31 + vpshrdvd zmm24{k5}{z}, zmm24, [rbx] + vpshrdvd zmm24{k5}{z}, zmm24, [rbx]{1to16} + vpshrdvd zmm24{k5}{z}, zmm24, [rbx+r11*8+256] + vpshrdvd zmm24{k5}{z}, zmm24, [rbx+r11*8-256] + vpshrdvq xmm2, xmm7, xmm0 + vpshrdvq xmm2, xmm7, [rbx] + vpshrdvq xmm2, xmm7, [rbx]{1to2} + vpshrdvq xmm2, xmm7, [rbx+r11*8+256] + vpshrdvq xmm2, xmm7, [rbx+r11*8-256] + vpshrdvq xmm2{k5}, xmm7, xmm0 + vpshrdvq xmm2{k5}, xmm7, [rbx] + vpshrdvq xmm2{k5}, xmm7, [rbx]{1to2} + vpshrdvq xmm2{k5}, xmm7, [rbx+r11*8+256] + vpshrdvq xmm2{k5}, xmm7, [rbx+r11*8-256] + vpshrdvq xmm2{z}, xmm7, xmm0 + vpshrdvq xmm2{z}, xmm7, [rbx] + vpshrdvq xmm2{z}, xmm7, [rbx]{1to2} + vpshrdvq xmm2{z}, xmm7, [rbx+r11*8+256] + vpshrdvq xmm2{z}, xmm7, [rbx+r11*8-256] + vpshrdvq xmm2{k5}{z}, xmm7, xmm0 + vpshrdvq xmm2{k5}{z}, xmm7, [rbx] + vpshrdvq xmm2{k5}{z}, xmm7, [rbx]{1to2} + vpshrdvq xmm2{k5}{z}, xmm7, [rbx+r11*8+256] + vpshrdvq xmm2{k5}{z}, xmm7, [rbx+r11*8-256] + vpshrdvq ymm16, ymm13, ymm15 + vpshrdvq ymm16, ymm13, [rbx] + vpshrdvq ymm16, ymm13, [rbx]{1to4} + vpshrdvq ymm16, ymm13, [rbx+r11*8+256] + vpshrdvq ymm16, ymm13, [rbx+r11*8-256] + vpshrdvq ymm16{k5}, ymm13, ymm15 + vpshrdvq ymm16{k5}, ymm13, [rbx] + vpshrdvq ymm16{k5}, ymm13, [rbx]{1to4} + vpshrdvq ymm16{k5}, ymm13, [rbx+r11*8+256] + vpshrdvq ymm16{k5}, ymm13, [rbx+r11*8-256] + vpshrdvq ymm16{z}, ymm13, ymm15 + vpshrdvq ymm16{z}, ymm13, [rbx] + vpshrdvq ymm16{z}, ymm13, [rbx]{1to4} + vpshrdvq ymm16{z}, ymm13, [rbx+r11*8+256] + vpshrdvq ymm16{z}, ymm13, [rbx+r11*8-256] + vpshrdvq ymm16{k5}{z}, ymm13, ymm15 + vpshrdvq ymm16{k5}{z}, ymm13, [rbx] + vpshrdvq ymm16{k5}{z}, ymm13, [rbx]{1to4} + vpshrdvq ymm16{k5}{z}, ymm13, [rbx+r11*8+256] + vpshrdvq ymm16{k5}{z}, ymm13, [rbx+r11*8-256] + vpshrdvq zmm24, zmm24, zmm31 + vpshrdvq zmm24, zmm24, [rbx] + vpshrdvq zmm24, zmm24, [rbx]{1to8} + vpshrdvq zmm24, zmm24, [rbx+r11*8+256] + vpshrdvq zmm24, zmm24, [rbx+r11*8-256] + vpshrdvq zmm24{k5}, zmm24, zmm31 + vpshrdvq zmm24{k5}, zmm24, [rbx] + vpshrdvq zmm24{k5}, zmm24, [rbx]{1to8} + vpshrdvq zmm24{k5}, zmm24, [rbx+r11*8+256] + vpshrdvq zmm24{k5}, zmm24, [rbx+r11*8-256] + vpshrdvq zmm24{z}, zmm24, zmm31 + vpshrdvq zmm24{z}, zmm24, [rbx] + vpshrdvq zmm24{z}, zmm24, [rbx]{1to8} + vpshrdvq zmm24{z}, zmm24, [rbx+r11*8+256] + vpshrdvq zmm24{z}, zmm24, [rbx+r11*8-256] + vpshrdvq zmm24{k5}{z}, zmm24, zmm31 + vpshrdvq zmm24{k5}{z}, zmm24, [rbx] + vpshrdvq zmm24{k5}{z}, zmm24, [rbx]{1to8} + vpshrdvq zmm24{k5}{z}, zmm24, [rbx+r11*8+256] + vpshrdvq zmm24{k5}{z}, zmm24, [rbx+r11*8-256] + vpshrdvw xmm2, xmm7, xmm0 + vpshrdvw xmm2, xmm7, [rbx] + vpshrdvw xmm2, xmm7, [rbx+r11*8+256] + vpshrdvw xmm2, xmm7, [rbx+r11*8-256] + vpshrdvw xmm2{k5}, xmm7, xmm0 + vpshrdvw xmm2{k5}, xmm7, [rbx] + vpshrdvw xmm2{k5}, xmm7, [rbx+r11*8+256] + vpshrdvw xmm2{k5}, xmm7, [rbx+r11*8-256] + vpshrdvw xmm2{z}, xmm7, xmm0 + vpshrdvw xmm2{z}, xmm7, [rbx] + vpshrdvw xmm2{z}, xmm7, [rbx+r11*8+256] + vpshrdvw xmm2{z}, xmm7, [rbx+r11*8-256] + vpshrdvw xmm2{k5}{z}, xmm7, xmm0 + vpshrdvw xmm2{k5}{z}, xmm7, [rbx] + vpshrdvw xmm2{k5}{z}, xmm7, [rbx+r11*8+256] + vpshrdvw xmm2{k5}{z}, xmm7, [rbx+r11*8-256] + vpshrdvw ymm16, ymm13, ymm15 + vpshrdvw ymm16, ymm13, [rbx] + vpshrdvw ymm16, ymm13, [rbx+r11*8+256] + vpshrdvw ymm16, ymm13, [rbx+r11*8-256] + vpshrdvw ymm16{k5}, ymm13, ymm15 + vpshrdvw ymm16{k5}, ymm13, [rbx] + vpshrdvw ymm16{k5}, ymm13, [rbx+r11*8+256] + vpshrdvw ymm16{k5}, ymm13, [rbx+r11*8-256] + vpshrdvw ymm16{z}, ymm13, ymm15 + vpshrdvw ymm16{z}, ymm13, [rbx] + vpshrdvw ymm16{z}, ymm13, [rbx+r11*8+256] + vpshrdvw ymm16{z}, ymm13, [rbx+r11*8-256] + vpshrdvw ymm16{k5}{z}, ymm13, ymm15 + vpshrdvw ymm16{k5}{z}, ymm13, [rbx] + vpshrdvw ymm16{k5}{z}, ymm13, [rbx+r11*8+256] + vpshrdvw ymm16{k5}{z}, ymm13, [rbx+r11*8-256] + vpshrdvw zmm24, zmm24, zmm31 + vpshrdvw zmm24, zmm24, [rbx] + vpshrdvw zmm24, zmm24, [rbx+r11*8+256] + vpshrdvw zmm24, zmm24, [rbx+r11*8-256] + vpshrdvw zmm24{k5}, zmm24, zmm31 + vpshrdvw zmm24{k5}, zmm24, [rbx] + vpshrdvw zmm24{k5}, zmm24, [rbx+r11*8+256] + vpshrdvw zmm24{k5}, zmm24, [rbx+r11*8-256] + vpshrdvw zmm24{z}, zmm24, zmm31 + vpshrdvw zmm24{z}, zmm24, [rbx] + vpshrdvw zmm24{z}, zmm24, [rbx+r11*8+256] + vpshrdvw zmm24{z}, zmm24, [rbx+r11*8-256] + vpshrdvw zmm24{k5}{z}, zmm24, zmm31 + vpshrdvw zmm24{k5}{z}, zmm24, [rbx] + vpshrdvw zmm24{k5}{z}, zmm24, [rbx+r11*8+256] + vpshrdvw zmm24{k5}{z}, zmm24, [rbx+r11*8-256] + vpshrdw xmm2, xmm7, xmm0, 0x90 + vpshrdw xmm2, xmm7, [rbx], 0x90 + vpshrdw xmm2, xmm7, [rbx+r11*8+256], 0x90 + vpshrdw xmm2, xmm7, [rbx+r11*8-256], 0x90 + vpshrdw xmm2{k5}, xmm7, xmm0, 0x90 + vpshrdw xmm2{k5}, xmm7, [rbx], 0x90 + vpshrdw xmm2{k5}, xmm7, [rbx+r11*8+256], 0x90 + vpshrdw xmm2{k5}, xmm7, [rbx+r11*8-256], 0x90 + vpshrdw xmm2{z}, xmm7, xmm0, 0x90 + vpshrdw xmm2{z}, xmm7, [rbx], 0x90 + vpshrdw xmm2{z}, xmm7, [rbx+r11*8+256], 0x90 + vpshrdw xmm2{z}, xmm7, [rbx+r11*8-256], 0x90 + vpshrdw xmm2{k5}{z}, xmm7, xmm0, 0x90 + vpshrdw xmm2{k5}{z}, xmm7, [rbx], 0x90 + vpshrdw xmm2{k5}{z}, xmm7, [rbx+r11*8+256], 0x90 + vpshrdw xmm2{k5}{z}, xmm7, [rbx+r11*8-256], 0x90 + vpshrdw ymm16, ymm13, ymm15, 0x90 + vpshrdw ymm16, ymm13, [rbx], 0x90 + vpshrdw ymm16, ymm13, [rbx+r11*8+256], 0x90 + vpshrdw ymm16, ymm13, [rbx+r11*8-256], 0x90 + vpshrdw ymm16{k5}, ymm13, ymm15, 0x90 + vpshrdw ymm16{k5}, ymm13, [rbx], 0x90 + vpshrdw ymm16{k5}, ymm13, [rbx+r11*8+256], 0x90 + vpshrdw ymm16{k5}, ymm13, [rbx+r11*8-256], 0x90 + vpshrdw ymm16{z}, ymm13, ymm15, 0x90 + vpshrdw ymm16{z}, ymm13, [rbx], 0x90 + vpshrdw ymm16{z}, ymm13, [rbx+r11*8+256], 0x90 + vpshrdw ymm16{z}, ymm13, [rbx+r11*8-256], 0x90 + vpshrdw ymm16{k5}{z}, ymm13, ymm15, 0x90 + vpshrdw ymm16{k5}{z}, ymm13, [rbx], 0x90 + vpshrdw ymm16{k5}{z}, ymm13, [rbx+r11*8+256], 0x90 + vpshrdw ymm16{k5}{z}, ymm13, [rbx+r11*8-256], 0x90 + vpshrdw zmm24, zmm24, zmm31, 0x90 + vpshrdw zmm24, zmm24, [rbx], 0x90 + vpshrdw zmm24, zmm24, [rbx+r11*8+256], 0x90 + vpshrdw zmm24, zmm24, [rbx+r11*8-256], 0x90 + vpshrdw zmm24{k5}, zmm24, zmm31, 0x90 + vpshrdw zmm24{k5}, zmm24, [rbx], 0x90 + vpshrdw zmm24{k5}, zmm24, [rbx+r11*8+256], 0x90 + vpshrdw zmm24{k5}, zmm24, [rbx+r11*8-256], 0x90 + vpshrdw zmm24{z}, zmm24, zmm31, 0x90 + vpshrdw zmm24{z}, zmm24, [rbx], 0x90 + vpshrdw zmm24{z}, zmm24, [rbx+r11*8+256], 0x90 + vpshrdw zmm24{z}, zmm24, [rbx+r11*8-256], 0x90 + vpshrdw zmm24{k5}{z}, zmm24, zmm31, 0x90 + vpshrdw zmm24{k5}{z}, zmm24, [rbx], 0x90 + vpshrdw zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 0x90 + vpshrdw zmm24{k5}{z}, zmm24, [rbx+r11*8-256], 0x90 diff --git a/bddisasm_test/avx512/avx512vbmi_64.result b/bddisasm_test/avx512/avx512vbmi_64.result new file mode 100644 index 0000000..bcd5263 --- /dev/null +++ b/bddisasm_test/avx512/avx512vbmi_64.result @@ -0,0 +1,23586 @@ +0000000000000000 62f27d0863d0 VPCOMPRESSB xmm0, xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000006 62c27d2863c7 VPCOMPRESSB ymm15, ymm16 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +000000000000000C 62027d4863c7 VPCOMPRESSB zmm31, zmm24 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +0000000000000012 62f27d086313 VPCOMPRESSB xmmword ptr [rbx], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000018 62e27d286303 VPCOMPRESSB ymmword ptr [rbx], ymm16 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +000000000000001E 62627d486303 VPCOMPRESSB zmmword ptr [rbx], zmm24 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +0000000000000024 62b27d086354db40 VPCOMPRESSB xmmword ptr [rbx+r11*8+0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000040, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +000000000000002C 62a27d286344db40 VPCOMPRESSB ymmword ptr [rbx+r11*8+0x100], ymm16 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000040, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +0000000000000034 62227d486344db40 VPCOMPRESSB zmmword ptr [rbx+r11*8+0x100], zmm24 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000040, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +000000000000003C 62b27d086354dbc0 VPCOMPRESSB xmmword ptr [rbx+r11*8-0x100], xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffc0, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000044 62a27d286344dbc0 VPCOMPRESSB ymmword ptr [rbx+r11*8-0x100], ymm16 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffc0, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +000000000000004C 62227d486344dbc0 VPCOMPRESSB zmmword ptr [rbx+r11*8-0x100], zmm24 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffc0, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +0000000000000054 62f2fd0863d0 VPCOMPRESSW xmm0, xmm2 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +000000000000005A 62c2fd2863c7 VPCOMPRESSW ymm15, ymm16 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +0000000000000060 6202fd4863c7 VPCOMPRESSW zmm31, zmm24 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +0000000000000066 62f2fd086313 VPCOMPRESSW xmmword ptr [rbx], xmm2 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +000000000000006C 62e2fd286303 VPCOMPRESSW ymmword ptr [rbx], ymm16 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +0000000000000072 6262fd486303 VPCOMPRESSW zmmword ptr [rbx], zmm24 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +0000000000000078 62b2fd086354db20 VPCOMPRESSW xmmword ptr [rbx+r11*8+0x100], xmm2 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000080 62a2fd286344db20 VPCOMPRESSW ymmword ptr [rbx+r11*8+0x100], ymm16 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +0000000000000088 6222fd486344db20 VPCOMPRESSW zmmword ptr [rbx+r11*8+0x100], zmm24 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000020, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +0000000000000090 62b2fd086354dbe0 VPCOMPRESSW xmmword ptr [rbx+r11*8-0x100], xmm2 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +0000000000000098 62a2fd286344dbe0 VPCOMPRESSW ymmword ptr [rbx+r11*8-0x100], ymm16 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +00000000000000A0 6222fd486344dbe0 VPCOMPRESSW zmmword ptr [rbx+r11*8-0x100], zmm24 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xffffffffffffffe0, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +00000000000000A8 62f245088dd0 VPERMB xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000000AE 62f245088d13 VPERMB xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000000B4 62b245088d54db10 VPERMB xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000000BC 62b245088d54dbf0 VPERMB xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000000C4 62f2450d8dd0 VPERMB xmm2{k5}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000000CA 62f2450d8d13 VPERMB xmm2{k5}, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000000D0 62b2450d8d54db10 VPERMB xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000000D8 62b2450d8d54dbf0 VPERMB xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000000E0 62f245888dd0 VPERMB xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000000E6 62f245888d13 VPERMB xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000000EC 62b245888d54db10 VPERMB xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000000F4 62b245888d54dbf0 VPERMB xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000000FC 62f2458d8dd0 VPERMB xmm2{k5}{z}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000102 62f2458d8d13 VPERMB xmm2{k5}{z}, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000108 62b2458d8d54db10 VPERMB xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000110 62b2458d8d54dbf0 VPERMB xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000118 62c215288dc7 VPERMB ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000011E 62e215288d03 VPERMB ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000124 62a215288d44db08 VPERMB ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000012C 62a215288d44dbf8 VPERMB ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000134 62c2152d8dc7 VPERMB ymm16{k5}, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000013A 62e2152d8d03 VPERMB ymm16{k5}, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000140 62a2152d8d44db08 VPERMB ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000148 62a2152d8d44dbf8 VPERMB ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000150 62c215a88dc7 VPERMB ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000156 62e215a88d03 VPERMB ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000015C 62a215a88d44db08 VPERMB ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000164 62a215a88d44dbf8 VPERMB ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000016C 62c215ad8dc7 VPERMB ymm16{k5}{z}, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000172 62e215ad8d03 VPERMB ymm16{k5}{z}, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000178 62a215ad8d44db08 VPERMB ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000180 62a215ad8d44dbf8 VPERMB ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000188 62023d408dc7 VPERMB zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000018E 62623d408d03 VPERMB zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000194 62223d408d44db04 VPERMB zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000019C 62223d408d44dbfc VPERMB zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000001A4 62023d458dc7 VPERMB zmm24{k5}, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000001AA 62623d458d03 VPERMB zmm24{k5}, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000001B0 62223d458d44db04 VPERMB zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000001B8 62223d458d44dbfc VPERMB zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000001C0 62023dc08dc7 VPERMB zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000001C6 62623dc08d03 VPERMB zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000001CC 62223dc08d44db04 VPERMB zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000001D4 62223dc08d44dbfc VPERMB zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000001DC 62023dc58dc7 VPERMB zmm24{k5}{z}, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000001E2 62623dc58d03 VPERMB zmm24{k5}{z}, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000001E8 62223dc58d44db04 VPERMB zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000001F0 62223dc58d44dbfc VPERMB zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000001F8 62f2450875d0 VPERMI2B xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000001FE 62f245087513 VPERMI2B xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000204 62b245087554db10 VPERMI2B xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000020C 62b245087554dbf0 VPERMI2B xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000214 62f2450d75d0 VPERMI2B xmm2{k5}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000021A 62f2450d7513 VPERMI2B xmm2{k5}, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000220 62b2450d7554db10 VPERMI2B xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000228 62b2450d7554dbf0 VPERMI2B xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000230 62f2458875d0 VPERMI2B xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000236 62f245887513 VPERMI2B xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000023C 62b245887554db10 VPERMI2B xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000244 62b245887554dbf0 VPERMI2B xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000024C 62f2458d75d0 VPERMI2B xmm2{k5}{z}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000252 62f2458d7513 VPERMI2B xmm2{k5}{z}, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000258 62b2458d7554db10 VPERMI2B xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000260 62b2458d7554dbf0 VPERMI2B xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000268 62c2152875c7 VPERMI2B ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000026E 62e215287503 VPERMI2B ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000274 62a215287544db08 VPERMI2B ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000027C 62a215287544dbf8 VPERMI2B ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000284 62c2152d75c7 VPERMI2B ymm16{k5}, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000028A 62e2152d7503 VPERMI2B ymm16{k5}, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000290 62a2152d7544db08 VPERMI2B ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000298 62a2152d7544dbf8 VPERMI2B ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000002A0 62c215a875c7 VPERMI2B ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000002A6 62e215a87503 VPERMI2B ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000002AC 62a215a87544db08 VPERMI2B ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000002B4 62a215a87544dbf8 VPERMI2B ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000002BC 62c215ad75c7 VPERMI2B ymm16{k5}{z}, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000002C2 62e215ad7503 VPERMI2B ymm16{k5}{z}, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000002C8 62a215ad7544db08 VPERMI2B ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000002D0 62a215ad7544dbf8 VPERMI2B ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000002D8 62023d4075c7 VPERMI2B zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000002DE 62623d407503 VPERMI2B zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000002E4 62223d407544db04 VPERMI2B zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000002EC 62223d407544dbfc VPERMI2B zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000002F4 62023d4575c7 VPERMI2B zmm24{k5}, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000002FA 62623d457503 VPERMI2B zmm24{k5}, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000300 62223d457544db04 VPERMI2B zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000308 62223d457544dbfc VPERMI2B zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000310 62023dc075c7 VPERMI2B zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000316 62623dc07503 VPERMI2B zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000031C 62223dc07544db04 VPERMI2B zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000324 62223dc07544dbfc VPERMI2B zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000032C 62023dc575c7 VPERMI2B zmm24{k5}{z}, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000332 62623dc57503 VPERMI2B zmm24{k5}{z}, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000338 62223dc57544db04 VPERMI2B zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000340 62223dc57544dbfc VPERMI2B zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000348 62f245087dd0 VPERMT2B xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000034E 62f245087d13 VPERMT2B xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000354 62b245087d54db10 VPERMT2B xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000035C 62b245087d54dbf0 VPERMT2B xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000364 62f2450d7dd0 VPERMT2B xmm2{k5}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000036A 62f2450d7d13 VPERMT2B xmm2{k5}, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000370 62b2450d7d54db10 VPERMT2B xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000378 62b2450d7d54dbf0 VPERMT2B xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000380 62f245887dd0 VPERMT2B xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000386 62f245887d13 VPERMT2B xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000038C 62b245887d54db10 VPERMT2B xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000394 62b245887d54dbf0 VPERMT2B xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000039C 62f2458d7dd0 VPERMT2B xmm2{k5}{z}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000003A2 62f2458d7d13 VPERMT2B xmm2{k5}{z}, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000003A8 62b2458d7d54db10 VPERMT2B xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000003B0 62b2458d7d54dbf0 VPERMT2B xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000003B8 62c215287dc7 VPERMT2B ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000003BE 62e215287d03 VPERMT2B ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000003C4 62a215287d44db08 VPERMT2B ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000003CC 62a215287d44dbf8 VPERMT2B ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000003D4 62c2152d7dc7 VPERMT2B ymm16{k5}, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000003DA 62e2152d7d03 VPERMT2B ymm16{k5}, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000003E0 62a2152d7d44db08 VPERMT2B ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000003E8 62a2152d7d44dbf8 VPERMT2B ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000003F0 62c215a87dc7 VPERMT2B ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000003F6 62e215a87d03 VPERMT2B ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000003FC 62a215a87d44db08 VPERMT2B ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000404 62a215a87d44dbf8 VPERMT2B ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000040C 62c215ad7dc7 VPERMT2B ymm16{k5}{z}, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000412 62e215ad7d03 VPERMT2B ymm16{k5}{z}, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000418 62a215ad7d44db08 VPERMT2B ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000420 62a215ad7d44dbf8 VPERMT2B ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000428 62023d407dc7 VPERMT2B zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000042E 62623d407d03 VPERMT2B zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000434 62223d407d44db04 VPERMT2B zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000043C 62223d407d44dbfc VPERMT2B zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000444 62023d457dc7 VPERMT2B zmm24{k5}, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000044A 62623d457d03 VPERMT2B zmm24{k5}, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000450 62223d457d44db04 VPERMT2B zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000458 62223d457d44dbfc VPERMT2B zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000460 62023dc07dc7 VPERMT2B zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000466 62623dc07d03 VPERMT2B zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000046C 62223dc07d44db04 VPERMT2B zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000474 62223dc07d44dbfc VPERMT2B zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000047C 62023dc57dc7 VPERMT2B zmm24{k5}{z}, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000482 62623dc57d03 VPERMT2B zmm24{k5}{z}, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000488 62223dc57d44db04 VPERMT2B zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000490 62223dc57d44dbfc VPERMT2B zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF.nb + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000498 62f27d0862c2 VPEXPANDB xmm0, xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +000000000000049E 62f27d0d62c2 VPEXPANDB xmm0{k5}, xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +00000000000004A4 62f27d8862c2 VPEXPANDB xmm0, xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +00000000000004AA 62f27d8d62c2 VPEXPANDB xmm0{k5}{z}, xmm2 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +00000000000004B0 62327d2862f8 VPEXPANDB ymm15, ymm16 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +00000000000004B6 62327d2d62f8 VPEXPANDB ymm15{k5}, ymm16 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +00000000000004BC 62327da862f8 VPEXPANDB ymm15, ymm16 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +00000000000004C2 62327dad62f8 VPEXPANDB ymm15{k5}{z}, ymm16 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +00000000000004C8 62027d4862f8 VPEXPANDB zmm31, zmm24 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +00000000000004CE 62027d4d62f8 VPEXPANDB zmm31{k5}, zmm24 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +00000000000004D4 62027dc862f8 VPEXPANDB zmm31, zmm24 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +00000000000004DA 62027dcd62f8 VPEXPANDB zmm31{k5}{z}, zmm24 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +00000000000004E0 62f2fd0862c2 VPEXPANDW xmm0, xmm2 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +00000000000004E6 62f2fd0d62c2 VPEXPANDW xmm0{k5}, xmm2 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +00000000000004EC 62f2fd8862c2 VPEXPANDW xmm0, xmm2 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +00000000000004F2 62f2fd8d62c2 VPEXPANDW xmm0{k5}{z}, xmm2 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + +00000000000004F8 6232fd2862f8 VPEXPANDW ymm15, ymm16 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +00000000000004FE 6232fd2d62f8 VPEXPANDW ymm15{k5}, ymm16 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +0000000000000504 6232fda862f8 VPEXPANDW ymm15, ymm16 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +000000000000050A 6232fdad62f8 VPEXPANDW ymm15{k5}{z}, ymm16 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + +0000000000000510 6202fd4862f8 VPEXPANDW zmm31, zmm24 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +0000000000000516 6202fd4d62f8 VPEXPANDW zmm31{k5}, zmm24 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +000000000000051C 6202fdc862f8 VPEXPANDW zmm31, zmm24 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +0000000000000522 6202fdcd62f8 VPEXPANDW zmm31{k5}{z}, zmm24 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Tuple 1 Scalar + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + +0000000000000528 62f2c50883d0 VPMULTISHIFTQB xmm2, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000052E 62f2c5088313 VPMULTISHIFTQB xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000534 62f2c5188313 VPMULTISHIFTQB xmm2, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +000000000000053A 62b2c5088354db10 VPMULTISHIFTQB xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000542 62b2c5088354dbf0 VPMULTISHIFTQB xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000054A 62f2c50d83d0 VPMULTISHIFTQB xmm2{k5}, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000550 62f2c50d8313 VPMULTISHIFTQB xmm2{k5}, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000556 62f2c51d8313 VPMULTISHIFTQB xmm2{k5}, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +000000000000055C 62b2c50d8354db10 VPMULTISHIFTQB xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000564 62b2c50d8354dbf0 VPMULTISHIFTQB xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000056C 62f2c58883d0 VPMULTISHIFTQB xmm2, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000572 62f2c5888313 VPMULTISHIFTQB xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000578 62f2c5988313 VPMULTISHIFTQB xmm2, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +000000000000057E 62b2c5888354db10 VPMULTISHIFTQB xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000586 62b2c5888354dbf0 VPMULTISHIFTQB xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000058E 62f2c58d83d0 VPMULTISHIFTQB xmm2{k5}{z}, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000594 62f2c58d8313 VPMULTISHIFTQB xmm2{k5}{z}, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000059A 62f2c59d8313 VPMULTISHIFTQB xmm2{k5}{z}, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +00000000000005A0 62b2c58d8354db10 VPMULTISHIFTQB xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000005A8 62b2c58d8354dbf0 VPMULTISHIFTQB xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000005B0 62c2952883c7 VPMULTISHIFTQB ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000005B6 62e295288303 VPMULTISHIFTQB ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000005BC 62e295388303 VPMULTISHIFTQB ymm16, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +00000000000005C2 62a295288344db08 VPMULTISHIFTQB ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000005CA 62a295288344dbf8 VPMULTISHIFTQB ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000005D2 62c2952d83c7 VPMULTISHIFTQB ymm16{k5}, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000005D8 62e2952d8303 VPMULTISHIFTQB ymm16{k5}, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000005DE 62e2953d8303 VPMULTISHIFTQB ymm16{k5}, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +00000000000005E4 62a2952d8344db08 VPMULTISHIFTQB ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000005EC 62a2952d8344dbf8 VPMULTISHIFTQB ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000005F4 62c295a883c7 VPMULTISHIFTQB ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000005FA 62e295a88303 VPMULTISHIFTQB ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000600 62e295b88303 VPMULTISHIFTQB ymm16, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000000606 62a295a88344db08 VPMULTISHIFTQB ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000060E 62a295a88344dbf8 VPMULTISHIFTQB ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000616 62c295ad83c7 VPMULTISHIFTQB ymm16{k5}{z}, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000061C 62e295ad8303 VPMULTISHIFTQB ymm16{k5}{z}, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000622 62e295bd8303 VPMULTISHIFTQB ymm16{k5}{z}, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000000628 62a295ad8344db08 VPMULTISHIFTQB ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000630 62a295ad8344dbf8 VPMULTISHIFTQB ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000638 6202bd4083c7 VPMULTISHIFTQB zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000063E 6262bd408303 VPMULTISHIFTQB zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000644 6262bd508303 VPMULTISHIFTQB zmm24, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +000000000000064A 6222bd408344db04 VPMULTISHIFTQB zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000652 6222bd408344dbfc VPMULTISHIFTQB zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000065A 6202bd4583c7 VPMULTISHIFTQB zmm24{k5}, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000660 6262bd458303 VPMULTISHIFTQB zmm24{k5}, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000666 6262bd558303 VPMULTISHIFTQB zmm24{k5}, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +000000000000066C 6222bd458344db04 VPMULTISHIFTQB zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000674 6222bd458344dbfc VPMULTISHIFTQB zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000067C 6202bdc083c7 VPMULTISHIFTQB zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000682 6262bdc08303 VPMULTISHIFTQB zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000688 6262bdd08303 VPMULTISHIFTQB zmm24, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +000000000000068E 6222bdc08344db04 VPMULTISHIFTQB zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000696 6222bdc08344dbfc VPMULTISHIFTQB zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000069E 6202bdc583c7 VPMULTISHIFTQB zmm24{k5}{z}, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000006A4 6262bdc58303 VPMULTISHIFTQB zmm24{k5}{z}, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000006AA 6262bdd58303 VPMULTISHIFTQB zmm24{k5}{z}, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +00000000000006B0 6222bdc58344db04 VPMULTISHIFTQB zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000006B8 6222bdc58344dbfc VPMULTISHIFTQB zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 1 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000006C0 62f3450871d090 VPSHLDD xmm2, xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000006C7 62f34508711390 VPSHLDD xmm2, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000006CE 62f34518711390 VPSHLDD xmm2, xmm7, dword ptr [rbx]{1to4}, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000006D5 62b345087154db1090 VPSHLDD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000006DE 62b345087154dbf090 VPSHLDD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000006E7 62f3450d71d090 VPSHLDD xmm2{k5}, xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000006EE 62f3450d711390 VPSHLDD xmm2{k5}, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000006F5 62f3451d711390 VPSHLDD xmm2{k5}, xmm7, dword ptr [rbx]{1to4}, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000006FC 62b3450d7154db1090 VPSHLDD xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000705 62b3450d7154dbf090 VPSHLDD xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000070E 62f3458871d090 VPSHLDD xmm2, xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000715 62f34588711390 VPSHLDD xmm2, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000071C 62f34598711390 VPSHLDD xmm2, xmm7, dword ptr [rbx]{1to4}, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000723 62b345887154db1090 VPSHLDD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000072C 62b345887154dbf090 VPSHLDD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000735 62f3458d71d090 VPSHLDD xmm2{k5}{z}, xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000073C 62f3458d711390 VPSHLDD xmm2{k5}{z}, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000743 62f3459d711390 VPSHLDD xmm2{k5}{z}, xmm7, dword ptr [rbx]{1to4}, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000074A 62b3458d7154db1090 VPSHLDD xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000753 62b3458d7154dbf090 VPSHLDD xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000075C 62c3152871c790 VPSHLDD ymm16, ymm13, ymm15, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000763 62e31528710390 VPSHLDD ymm16, ymm13, ymmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000076A 62e31538710390 VPSHLDD ymm16, ymm13, dword ptr [rbx]{1to8}, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000771 62a315287144db0890 VPSHLDD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000077A 62a315287144dbf890 VPSHLDD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000783 62c3152d71c790 VPSHLDD ymm16{k5}, ymm13, ymm15, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000078A 62e3152d710390 VPSHLDD ymm16{k5}, ymm13, ymmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000791 62e3153d710390 VPSHLDD ymm16{k5}, ymm13, dword ptr [rbx]{1to8}, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000798 62a3152d7144db0890 VPSHLDD ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000007A1 62a3152d7144dbf890 VPSHLDD ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000007AA 62c315a871c790 VPSHLDD ymm16, ymm13, ymm15, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000007B1 62e315a8710390 VPSHLDD ymm16, ymm13, ymmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000007B8 62e315b8710390 VPSHLDD ymm16, ymm13, dword ptr [rbx]{1to8}, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000007BF 62a315a87144db0890 VPSHLDD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000007C8 62a315a87144dbf890 VPSHLDD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000007D1 62c315ad71c790 VPSHLDD ymm16{k5}{z}, ymm13, ymm15, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000007D8 62e315ad710390 VPSHLDD ymm16{k5}{z}, ymm13, ymmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000007DF 62e315bd710390 VPSHLDD ymm16{k5}{z}, ymm13, dword ptr [rbx]{1to8}, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000007E6 62a315ad7144db0890 VPSHLDD ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000007EF 62a315ad7144dbf890 VPSHLDD ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000007F8 62033d4071c790 VPSHLDD zmm24, zmm24, zmm31, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000007FF 62633d40710390 VPSHLDD zmm24, zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000806 62633d50710390 VPSHLDD zmm24, zmm24, dword ptr [rbx]{1to16}, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000080D 62233d407144db0490 VPSHLDD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000816 62233d407144dbfc90 VPSHLDD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000081F 62033d4571c790 VPSHLDD zmm24{k5}, zmm24, zmm31, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000826 62633d45710390 VPSHLDD zmm24{k5}, zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000082D 62633d55710390 VPSHLDD zmm24{k5}, zmm24, dword ptr [rbx]{1to16}, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000834 62233d457144db0490 VPSHLDD zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000083D 62233d457144dbfc90 VPSHLDD zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000846 62033dc071c790 VPSHLDD zmm24, zmm24, zmm31, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000084D 62633dc0710390 VPSHLDD zmm24, zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000854 62633dd0710390 VPSHLDD zmm24, zmm24, dword ptr [rbx]{1to16}, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000085B 62233dc07144db0490 VPSHLDD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000864 62233dc07144dbfc90 VPSHLDD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000086D 62033dc571c790 VPSHLDD zmm24{k5}{z}, zmm24, zmm31, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000874 62633dc5710390 VPSHLDD zmm24{k5}{z}, zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000087B 62633dd5710390 VPSHLDD zmm24{k5}{z}, zmm24, dword ptr [rbx]{1to16}, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000882 62233dc57144db0490 VPSHLDD zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000088B 62233dc57144dbfc90 VPSHLDD zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000894 62f3c50871d090 VPSHLDQ xmm2, xmm7, xmm0, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000089B 62f3c508711390 VPSHLDQ xmm2, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000008A2 62f3c518711390 VPSHLDQ xmm2, xmm7, qword ptr [rbx]{1to2}, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000008A9 62b3c5087154db1090 VPSHLDQ xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000008B2 62b3c5087154dbf090 VPSHLDQ xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000008BB 62f3c50d71d090 VPSHLDQ xmm2{k5}, xmm7, xmm0, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000008C2 62f3c50d711390 VPSHLDQ xmm2{k5}, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000008C9 62f3c51d711390 VPSHLDQ xmm2{k5}, xmm7, qword ptr [rbx]{1to2}, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000008D0 62b3c50d7154db1090 VPSHLDQ xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000008D9 62b3c50d7154dbf090 VPSHLDQ xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000008E2 62f3c58871d090 VPSHLDQ xmm2, xmm7, xmm0, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000008E9 62f3c588711390 VPSHLDQ xmm2, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000008F0 62f3c598711390 VPSHLDQ xmm2, xmm7, qword ptr [rbx]{1to2}, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000008F7 62b3c5887154db1090 VPSHLDQ xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000900 62b3c5887154dbf090 VPSHLDQ xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000909 62f3c58d71d090 VPSHLDQ xmm2{k5}{z}, xmm7, xmm0, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000910 62f3c58d711390 VPSHLDQ xmm2{k5}{z}, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000917 62f3c59d711390 VPSHLDQ xmm2{k5}{z}, xmm7, qword ptr [rbx]{1to2}, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000091E 62b3c58d7154db1090 VPSHLDQ xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000927 62b3c58d7154dbf090 VPSHLDQ xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000930 62c3952871c790 VPSHLDQ ymm16, ymm13, ymm15, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000937 62e39528710390 VPSHLDQ ymm16, ymm13, ymmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000093E 62e39538710390 VPSHLDQ ymm16, ymm13, qword ptr [rbx]{1to4}, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000945 62a395287144db0890 VPSHLDQ ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000094E 62a395287144dbf890 VPSHLDQ ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000957 62c3952d71c790 VPSHLDQ ymm16{k5}, ymm13, ymm15, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000095E 62e3952d710390 VPSHLDQ ymm16{k5}, ymm13, ymmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000965 62e3953d710390 VPSHLDQ ymm16{k5}, ymm13, qword ptr [rbx]{1to4}, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000096C 62a3952d7144db0890 VPSHLDQ ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000975 62a3952d7144dbf890 VPSHLDQ ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000097E 62c395a871c790 VPSHLDQ ymm16, ymm13, ymm15, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000985 62e395a8710390 VPSHLDQ ymm16, ymm13, ymmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000098C 62e395b8710390 VPSHLDQ ymm16, ymm13, qword ptr [rbx]{1to4}, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000993 62a395a87144db0890 VPSHLDQ ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000099C 62a395a87144dbf890 VPSHLDQ ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000009A5 62c395ad71c790 VPSHLDQ ymm16{k5}{z}, ymm13, ymm15, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000009AC 62e395ad710390 VPSHLDQ ymm16{k5}{z}, ymm13, ymmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000009B3 62e395bd710390 VPSHLDQ ymm16{k5}{z}, ymm13, qword ptr [rbx]{1to4}, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000009BA 62a395ad7144db0890 VPSHLDQ ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000009C3 62a395ad7144dbf890 VPSHLDQ ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000009CC 6203bd4071c790 VPSHLDQ zmm24, zmm24, zmm31, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000009D3 6263bd40710390 VPSHLDQ zmm24, zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000009DA 6263bd50710390 VPSHLDQ zmm24, zmm24, qword ptr [rbx]{1to8}, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000009E1 6223bd407144db0490 VPSHLDQ zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000009EA 6223bd407144dbfc90 VPSHLDQ zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000009F3 6203bd4571c790 VPSHLDQ zmm24{k5}, zmm24, zmm31, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000009FA 6263bd45710390 VPSHLDQ zmm24{k5}, zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000A01 6263bd55710390 VPSHLDQ zmm24{k5}, zmm24, qword ptr [rbx]{1to8}, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000A08 6223bd457144db0490 VPSHLDQ zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000A11 6223bd457144dbfc90 VPSHLDQ zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000A1A 6203bdc071c790 VPSHLDQ zmm24, zmm24, zmm31, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000A21 6263bdc0710390 VPSHLDQ zmm24, zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000A28 6263bdd0710390 VPSHLDQ zmm24, zmm24, qword ptr [rbx]{1to8}, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000A2F 6223bdc07144db0490 VPSHLDQ zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000A38 6223bdc07144dbfc90 VPSHLDQ zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000A41 6203bdc571c790 VPSHLDQ zmm24{k5}{z}, zmm24, zmm31, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000A48 6263bdc5710390 VPSHLDQ zmm24{k5}{z}, zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000A4F 6263bdd5710390 VPSHLDQ zmm24{k5}{z}, zmm24, qword ptr [rbx]{1to8}, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000A56 6223bdc57144db0490 VPSHLDQ zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000A5F 6223bdc57144dbfc90 VPSHLDQ zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000A68 62f2450871d0 VPSHLDVD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000A6E 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000A6F 62f245087113 VPSHLDVD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000A75 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000A76 62f245187113 VPSHLDVD xmm2, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000000A7C 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000A7D 62b245087154db10 VPSHLDVD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000A85 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000A86 62b245087154dbf0 VPSHLDVD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000A8E 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000A8F 62f2450d71d0 VPSHLDVD xmm2{k5}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000A95 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000A96 62f2450d7113 VPSHLDVD xmm2{k5}, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000A9C 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000A9D 62f2451d7113 VPSHLDVD xmm2{k5}, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000000AA3 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000AA4 62b2450d7154db10 VPSHLDVD xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000AAC 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000AAD 62b2450d7154dbf0 VPSHLDVD xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000AB5 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000AB6 62f2458871d0 VPSHLDVD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000ABC 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000ABD 62f245887113 VPSHLDVD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000AC3 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000AC4 62f245987113 VPSHLDVD xmm2, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000000ACA 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000ACB 62b245887154db10 VPSHLDVD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000AD3 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000AD4 62b245887154dbf0 VPSHLDVD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000ADC 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000ADD 62f2458d71d0 VPSHLDVD xmm2{k5}{z}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000AE3 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000AE4 62f2458d7113 VPSHLDVD xmm2{k5}{z}, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000AEA 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000AEB 62f2459d7113 VPSHLDVD xmm2{k5}{z}, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000000AF1 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000AF2 62b2458d7154db10 VPSHLDVD xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000AFA 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000AFB 62b2458d7154dbf0 VPSHLDVD xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000B03 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000B04 62c2152871c7 VPSHLDVD ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000B0A 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000B0B 62e215287103 VPSHLDVD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000B11 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000B12 62e215387103 VPSHLDVD ymm16, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +0000000000000B18 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000B19 62a215287144db08 VPSHLDVD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000B21 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000B22 62a215287144dbf8 VPSHLDVD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000B2A 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000B2B 62c2152d71c7 VPSHLDVD ymm16{k5}, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000B31 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000B32 62e2152d7103 VPSHLDVD ymm16{k5}, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000B38 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000B39 62e2153d7103 VPSHLDVD ymm16{k5}, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +0000000000000B3F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000B40 62a2152d7144db08 VPSHLDVD ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000B48 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000B49 62a2152d7144dbf8 VPSHLDVD ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000B51 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000B52 62c215a871c7 VPSHLDVD ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000B58 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000B59 62e215a87103 VPSHLDVD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000B5F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000B60 62e215b87103 VPSHLDVD ymm16, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +0000000000000B66 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000B67 62a215a87144db08 VPSHLDVD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000B6F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000B70 62a215a87144dbf8 VPSHLDVD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000B78 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000B79 62c215ad71c7 VPSHLDVD ymm16{k5}{z}, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000B7F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000B80 62e215ad7103 VPSHLDVD ymm16{k5}{z}, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000B86 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000B87 62e215bd7103 VPSHLDVD ymm16{k5}{z}, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +0000000000000B8D 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000B8E 62a215ad7144db08 VPSHLDVD ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000B96 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000B97 62a215ad7144dbf8 VPSHLDVD ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000B9F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000BA0 62023d4071c7 VPSHLDVD zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000BA6 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000BA7 62623d407103 VPSHLDVD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000BAD 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000BAE 62623d507103 VPSHLDVD zmm24, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000000BB4 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000BB5 62223d407144db04 VPSHLDVD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000BBD 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000BBE 62223d407144dbfc VPSHLDVD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000BC6 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000BC7 62023d4571c7 VPSHLDVD zmm24{k5}, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000BCD 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000BCE 62623d457103 VPSHLDVD zmm24{k5}, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000BD4 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000BD5 62623d557103 VPSHLDVD zmm24{k5}, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000000BDB 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000BDC 62223d457144db04 VPSHLDVD zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000BE4 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000BE5 62223d457144dbfc VPSHLDVD zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000BED 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000BEE 62023dc071c7 VPSHLDVD zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000BF4 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000BF5 62623dc07103 VPSHLDVD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000BFB 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000BFC 62623dd07103 VPSHLDVD zmm24, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000000C02 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000C03 62223dc07144db04 VPSHLDVD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000C0B 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000C0C 62223dc07144dbfc VPSHLDVD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000C14 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000C15 62023dc571c7 VPSHLDVD zmm24{k5}{z}, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000C1B 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000C1C 62623dc57103 VPSHLDVD zmm24{k5}{z}, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000C22 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000C23 62623dd57103 VPSHLDVD zmm24{k5}{z}, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000000C29 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000C2A 62223dc57144db04 VPSHLDVD zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000C32 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000C33 62223dc57144dbfc VPSHLDVD zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000C3B 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000C3C 62f2c50871d0 VPSHLDVQ xmm2, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000C42 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000C43 62f2c5087113 VPSHLDVQ xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000C49 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000C4A 62f2c5187113 VPSHLDVQ xmm2, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000000C50 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000C51 62b2c5087154db10 VPSHLDVQ xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000C59 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000C5A 62b2c5087154dbf0 VPSHLDVQ xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000C62 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000C63 62f2c50d71d0 VPSHLDVQ xmm2{k5}, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000C69 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000C6A 62f2c50d7113 VPSHLDVQ xmm2{k5}, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000C70 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000C71 62f2c51d7113 VPSHLDVQ xmm2{k5}, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000000C77 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000C78 62b2c50d7154db10 VPSHLDVQ xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000C80 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000C81 62b2c50d7154dbf0 VPSHLDVQ xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000C89 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000C8A 62f2c58871d0 VPSHLDVQ xmm2, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000C90 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000C91 62f2c5887113 VPSHLDVQ xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000C97 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000C98 62f2c5987113 VPSHLDVQ xmm2, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000000C9E 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000C9F 62b2c5887154db10 VPSHLDVQ xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000CA7 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000CA8 62b2c5887154dbf0 VPSHLDVQ xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000CB0 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000CB1 62f2c58d71d0 VPSHLDVQ xmm2{k5}{z}, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000CB7 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000CB8 62f2c58d7113 VPSHLDVQ xmm2{k5}{z}, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000CBE 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000CBF 62f2c59d7113 VPSHLDVQ xmm2{k5}{z}, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000000CC5 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000CC6 62b2c58d7154db10 VPSHLDVQ xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000CCE 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000CCF 62b2c58d7154dbf0 VPSHLDVQ xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000CD7 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000CD8 62c2952871c7 VPSHLDVQ ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000CDE 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000CDF 62e295287103 VPSHLDVQ ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000CE5 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000CE6 62e295387103 VPSHLDVQ ymm16, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000000CEC 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000CED 62a295287144db08 VPSHLDVQ ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000CF5 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000CF6 62a295287144dbf8 VPSHLDVQ ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000CFE 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000CFF 62c2952d71c7 VPSHLDVQ ymm16{k5}, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000D05 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000D06 62e2952d7103 VPSHLDVQ ymm16{k5}, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000D0C 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000D0D 62e2953d7103 VPSHLDVQ ymm16{k5}, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000000D13 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000D14 62a2952d7144db08 VPSHLDVQ ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000D1C 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000D1D 62a2952d7144dbf8 VPSHLDVQ ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000D25 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000D26 62c295a871c7 VPSHLDVQ ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000D2C 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000D2D 62e295a87103 VPSHLDVQ ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000D33 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000D34 62e295b87103 VPSHLDVQ ymm16, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000000D3A 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000D3B 62a295a87144db08 VPSHLDVQ ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000D43 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000D44 62a295a87144dbf8 VPSHLDVQ ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000D4C 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000D4D 62c295ad71c7 VPSHLDVQ ymm16{k5}{z}, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000D53 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000D54 62e295ad7103 VPSHLDVQ ymm16{k5}{z}, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000D5A 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000D5B 62e295bd7103 VPSHLDVQ ymm16{k5}{z}, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000000D61 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000D62 62a295ad7144db08 VPSHLDVQ ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000D6A 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000D6B 62a295ad7144dbf8 VPSHLDVQ ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000D73 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000D74 6202bd4071c7 VPSHLDVQ zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000D7A 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000D7B 6262bd407103 VPSHLDVQ zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000D81 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000D82 6262bd507103 VPSHLDVQ zmm24, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000000D88 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000D89 6222bd407144db04 VPSHLDVQ zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000D91 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000D92 6222bd407144dbfc VPSHLDVQ zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000D9A 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000D9B 6202bd4571c7 VPSHLDVQ zmm24{k5}, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000DA1 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000DA2 6262bd457103 VPSHLDVQ zmm24{k5}, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000DA8 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000DA9 6262bd557103 VPSHLDVQ zmm24{k5}, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000000DAF 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000DB0 6222bd457144db04 VPSHLDVQ zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000DB8 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000DB9 6222bd457144dbfc VPSHLDVQ zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000DC1 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000DC2 6202bdc071c7 VPSHLDVQ zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000DC8 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000DC9 6262bdc07103 VPSHLDVQ zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000DCF 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000DD0 6262bdd07103 VPSHLDVQ zmm24, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000000DD6 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000DD7 6222bdc07144db04 VPSHLDVQ zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000DDF 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000DE0 6222bdc07144dbfc VPSHLDVQ zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000DE8 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000DE9 6202bdc571c7 VPSHLDVQ zmm24{k5}{z}, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000DEF 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000DF0 6262bdc57103 VPSHLDVQ zmm24{k5}{z}, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000DF6 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000DF7 6262bdd57103 VPSHLDVQ zmm24{k5}{z}, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000000DFD 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000DFE 6222bdc57144db04 VPSHLDVQ zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000E06 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000E07 6222bdc57144dbfc VPSHLDVQ zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000E0F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000E10 62f2c50870d0 VPSHLDVW xmm2, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000E16 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000E17 62f2c5087013 VPSHLDVW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000E1D 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000E1E 62b2c5087054db10 VPSHLDVW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000E26 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000E27 62b2c5087054dbf0 VPSHLDVW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000E2F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000E30 62f2c50d70d0 VPSHLDVW xmm2{k5}, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000E36 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000E37 62f2c50d7013 VPSHLDVW xmm2{k5}, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000E3D 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000E3E 62b2c50d7054db10 VPSHLDVW xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000E46 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000E47 62b2c50d7054dbf0 VPSHLDVW xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000E4F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000E50 62f2c58870d0 VPSHLDVW xmm2, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000E56 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000E57 62f2c5887013 VPSHLDVW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000E5D 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000E5E 62b2c5887054db10 VPSHLDVW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000E66 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000E67 62b2c5887054dbf0 VPSHLDVW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000E6F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000E70 62f2c58d70d0 VPSHLDVW xmm2{k5}{z}, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000E76 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000E77 62f2c58d7013 VPSHLDVW xmm2{k5}{z}, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000E7D 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000E7E 62b2c58d7054db10 VPSHLDVW xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000E86 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000E87 62b2c58d7054dbf0 VPSHLDVW xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000E8F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000E90 62c2952870c7 VPSHLDVW ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000E96 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000E97 62e295287003 VPSHLDVW ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000E9D 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000E9E 62a295287044db08 VPSHLDVW ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000EA6 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000EA7 62a295287044dbf8 VPSHLDVW ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000EAF 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000EB0 62c2952d70c7 VPSHLDVW ymm16{k5}, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000EB6 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000EB7 62e2952d7003 VPSHLDVW ymm16{k5}, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000EBD 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000EBE 62a2952d7044db08 VPSHLDVW ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000EC6 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000EC7 62a2952d7044dbf8 VPSHLDVW ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000ECF 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000ED0 62c295a870c7 VPSHLDVW ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000ED6 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000ED7 62e295a87003 VPSHLDVW ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000EDD 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000EDE 62a295a87044db08 VPSHLDVW ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000EE6 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000EE7 62a295a87044dbf8 VPSHLDVW ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000EEF 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000EF0 62c295ad70c7 VPSHLDVW ymm16{k5}{z}, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000EF6 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000EF7 62e295ad7003 VPSHLDVW ymm16{k5}{z}, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000EFD 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000EFE 62a295ad7044db08 VPSHLDVW ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000F06 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000F07 62a295ad7044dbf8 VPSHLDVW ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000F0F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000F10 6202bd4070c7 VPSHLDVW zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000F16 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000F17 6262bd407003 VPSHLDVW zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000F1D 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000F1E 6222bd407044db04 VPSHLDVW zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000F26 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000F27 6222bd407044dbfc VPSHLDVW zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000F2F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000F30 6202bd4570c7 VPSHLDVW zmm24{k5}, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000F36 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000F37 6262bd457003 VPSHLDVW zmm24{k5}, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000F3D 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000F3E 6222bd457044db04 VPSHLDVW zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000F46 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000F47 6222bd457044dbfc VPSHLDVW zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000F4F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000F50 6202bdc070c7 VPSHLDVW zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000F56 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000F57 6262bdc07003 VPSHLDVW zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000F5D 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000F5E 6222bdc07044db04 VPSHLDVW zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000F66 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000F67 6222bdc07044dbfc VPSHLDVW zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000F6F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000F70 6202bdc570c7 VPSHLDVW zmm24{k5}{z}, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000F76 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000F77 6262bdc57003 VPSHLDVW zmm24{k5}{z}, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000F7D 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000F7E 6222bdc57044db04 VPSHLDVW zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000F86 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000F87 6222bdc57044dbfc VPSHLDVW zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000F8F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000F90 62f3c50870d090 VPSHLDW xmm2, xmm7, xmm0, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000F97 62f3c508701390 VPSHLDW xmm2, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000F9E 62b3c5087054db1090 VPSHLDW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000FA7 62b3c5087054dbf090 VPSHLDW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000FB0 62f3c50d70d090 VPSHLDW xmm2{k5}, xmm7, xmm0, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000FB7 62f3c50d701390 VPSHLDW xmm2{k5}, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000FBE 62b3c50d7054db1090 VPSHLDW xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000FC7 62b3c50d7054dbf090 VPSHLDW xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000FD0 62f3c58870d090 VPSHLDW xmm2, xmm7, xmm0, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000FD7 62f3c588701390 VPSHLDW xmm2, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000FDE 62b3c5887054db1090 VPSHLDW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000FE7 62b3c5887054dbf090 VPSHLDW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000FF0 62f3c58d70d090 VPSHLDW xmm2{k5}{z}, xmm7, xmm0, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000FF7 62f3c58d701390 VPSHLDW xmm2{k5}{z}, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000FFE 62b3c58d7054db1090 VPSHLDW xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001007 62b3c58d7054dbf090 VPSHLDW xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001010 62c3952870c790 VPSHLDW ymm16, ymm13, ymm15, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001017 62e39528700390 VPSHLDW ymm16, ymm13, ymmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000101E 62a395287044db0890 VPSHLDW ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001027 62a395287044dbf890 VPSHLDW ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001030 62c3952d70c790 VPSHLDW ymm16{k5}, ymm13, ymm15, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001037 62e3952d700390 VPSHLDW ymm16{k5}, ymm13, ymmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000103E 62a3952d7044db0890 VPSHLDW ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001047 62a3952d7044dbf890 VPSHLDW ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001050 62c395a870c790 VPSHLDW ymm16, ymm13, ymm15, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001057 62e395a8700390 VPSHLDW ymm16, ymm13, ymmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000105E 62a395a87044db0890 VPSHLDW ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001067 62a395a87044dbf890 VPSHLDW ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001070 62c395ad70c790 VPSHLDW ymm16{k5}{z}, ymm13, ymm15, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001077 62e395ad700390 VPSHLDW ymm16{k5}{z}, ymm13, ymmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000107E 62a395ad7044db0890 VPSHLDW ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001087 62a395ad7044dbf890 VPSHLDW ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001090 6203bd4070c790 VPSHLDW zmm24, zmm24, zmm31, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001097 6263bd40700390 VPSHLDW zmm24, zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000109E 6223bd407044db0490 VPSHLDW zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000010A7 6223bd407044dbfc90 VPSHLDW zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000010B0 6203bd4570c790 VPSHLDW zmm24{k5}, zmm24, zmm31, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000010B7 6263bd45700390 VPSHLDW zmm24{k5}, zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000010BE 6223bd457044db0490 VPSHLDW zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000010C7 6223bd457044dbfc90 VPSHLDW zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000010D0 6203bdc070c790 VPSHLDW zmm24, zmm24, zmm31, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000010D7 6263bdc0700390 VPSHLDW zmm24, zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000010DE 6223bdc07044db0490 VPSHLDW zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000010E7 6223bdc07044dbfc90 VPSHLDW zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000010F0 6203bdc570c790 VPSHLDW zmm24{k5}{z}, zmm24, zmm31, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000010F7 6263bdc5700390 VPSHLDW zmm24{k5}{z}, zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000010FE 6223bdc57044db0490 VPSHLDW zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001107 6223bdc57044dbfc90 VPSHLDW zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001110 62f3450873d090 VPSHRDD xmm2, xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001117 62f34508731390 VPSHRDD xmm2, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000111E 62f34518731390 VPSHRDD xmm2, xmm7, dword ptr [rbx]{1to4}, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001125 62b345087354db1090 VPSHRDD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000112E 62b345087354dbf090 VPSHRDD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001137 62f3450d73d090 VPSHRDD xmm2{k5}, xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000113E 62f3450d731390 VPSHRDD xmm2{k5}, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001145 62f3451d731390 VPSHRDD xmm2{k5}, xmm7, dword ptr [rbx]{1to4}, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000114C 62b3450d7354db1090 VPSHRDD xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001155 62b3450d7354dbf090 VPSHRDD xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000115E 62f3458873d090 VPSHRDD xmm2, xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001165 62f34588731390 VPSHRDD xmm2, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000116C 62f34598731390 VPSHRDD xmm2, xmm7, dword ptr [rbx]{1to4}, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001173 62b345887354db1090 VPSHRDD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000117C 62b345887354dbf090 VPSHRDD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001185 62f3458d73d090 VPSHRDD xmm2{k5}{z}, xmm7, xmm0, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000118C 62f3458d731390 VPSHRDD xmm2{k5}{z}, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001193 62f3459d731390 VPSHRDD xmm2{k5}{z}, xmm7, dword ptr [rbx]{1to4}, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000119A 62b3458d7354db1090 VPSHRDD xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000011A3 62b3458d7354dbf090 VPSHRDD xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000011AC 62c3152873c790 VPSHRDD ymm16, ymm13, ymm15, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000011B3 62e31528730390 VPSHRDD ymm16, ymm13, ymmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000011BA 62e31538730390 VPSHRDD ymm16, ymm13, dword ptr [rbx]{1to8}, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000011C1 62a315287344db0890 VPSHRDD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000011CA 62a315287344dbf890 VPSHRDD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000011D3 62c3152d73c790 VPSHRDD ymm16{k5}, ymm13, ymm15, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000011DA 62e3152d730390 VPSHRDD ymm16{k5}, ymm13, ymmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000011E1 62e3153d730390 VPSHRDD ymm16{k5}, ymm13, dword ptr [rbx]{1to8}, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000011E8 62a3152d7344db0890 VPSHRDD ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000011F1 62a3152d7344dbf890 VPSHRDD ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000011FA 62c315a873c790 VPSHRDD ymm16, ymm13, ymm15, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001201 62e315a8730390 VPSHRDD ymm16, ymm13, ymmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001208 62e315b8730390 VPSHRDD ymm16, ymm13, dword ptr [rbx]{1to8}, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000120F 62a315a87344db0890 VPSHRDD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001218 62a315a87344dbf890 VPSHRDD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001221 62c315ad73c790 VPSHRDD ymm16{k5}{z}, ymm13, ymm15, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001228 62e315ad730390 VPSHRDD ymm16{k5}{z}, ymm13, ymmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000122F 62e315bd730390 VPSHRDD ymm16{k5}{z}, ymm13, dword ptr [rbx]{1to8}, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001236 62a315ad7344db0890 VPSHRDD ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000123F 62a315ad7344dbf890 VPSHRDD ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001248 62033d4073c790 VPSHRDD zmm24, zmm24, zmm31, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000124F 62633d40730390 VPSHRDD zmm24, zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001256 62633d50730390 VPSHRDD zmm24, zmm24, dword ptr [rbx]{1to16}, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000125D 62233d407344db0490 VPSHRDD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001266 62233d407344dbfc90 VPSHRDD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000126F 62033d4573c790 VPSHRDD zmm24{k5}, zmm24, zmm31, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001276 62633d45730390 VPSHRDD zmm24{k5}, zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000127D 62633d55730390 VPSHRDD zmm24{k5}, zmm24, dword ptr [rbx]{1to16}, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001284 62233d457344db0490 VPSHRDD zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000128D 62233d457344dbfc90 VPSHRDD zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001296 62033dc073c790 VPSHRDD zmm24, zmm24, zmm31, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000129D 62633dc0730390 VPSHRDD zmm24, zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000012A4 62633dd0730390 VPSHRDD zmm24, zmm24, dword ptr [rbx]{1to16}, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000012AB 62233dc07344db0490 VPSHRDD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000012B4 62233dc07344dbfc90 VPSHRDD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000012BD 62033dc573c790 VPSHRDD zmm24{k5}{z}, zmm24, zmm31, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000012C4 62633dc5730390 VPSHRDD zmm24{k5}{z}, zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000012CB 62633dd5730390 VPSHRDD zmm24{k5}{z}, zmm24, dword ptr [rbx]{1to16}, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000012D2 62233dc57344db0490 VPSHRDD zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000012DB 62233dc57344dbfc90 VPSHRDD zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000012E4 62f3c50873d090 VPSHRDQ xmm2, xmm7, xmm0, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000012EB 62f3c508731390 VPSHRDQ xmm2, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000012F2 62f3c518731390 VPSHRDQ xmm2, xmm7, qword ptr [rbx]{1to2}, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000012F9 62b3c5087354db1090 VPSHRDQ xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001302 62b3c5087354dbf090 VPSHRDQ xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000130B 62f3c50d73d090 VPSHRDQ xmm2{k5}, xmm7, xmm0, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001312 62f3c50d731390 VPSHRDQ xmm2{k5}, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001319 62f3c51d731390 VPSHRDQ xmm2{k5}, xmm7, qword ptr [rbx]{1to2}, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001320 62b3c50d7354db1090 VPSHRDQ xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001329 62b3c50d7354dbf090 VPSHRDQ xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001332 62f3c58873d090 VPSHRDQ xmm2, xmm7, xmm0, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001339 62f3c588731390 VPSHRDQ xmm2, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001340 62f3c598731390 VPSHRDQ xmm2, xmm7, qword ptr [rbx]{1to2}, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001347 62b3c5887354db1090 VPSHRDQ xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001350 62b3c5887354dbf090 VPSHRDQ xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001359 62f3c58d73d090 VPSHRDQ xmm2{k5}{z}, xmm7, xmm0, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001360 62f3c58d731390 VPSHRDQ xmm2{k5}{z}, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001367 62f3c59d731390 VPSHRDQ xmm2{k5}{z}, xmm7, qword ptr [rbx]{1to2}, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000136E 62b3c58d7354db1090 VPSHRDQ xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001377 62b3c58d7354dbf090 VPSHRDQ xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001380 62c3952873c790 VPSHRDQ ymm16, ymm13, ymm15, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001387 62e39528730390 VPSHRDQ ymm16, ymm13, ymmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000138E 62e39538730390 VPSHRDQ ymm16, ymm13, qword ptr [rbx]{1to4}, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001395 62a395287344db0890 VPSHRDQ ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000139E 62a395287344dbf890 VPSHRDQ ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000013A7 62c3952d73c790 VPSHRDQ ymm16{k5}, ymm13, ymm15, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000013AE 62e3952d730390 VPSHRDQ ymm16{k5}, ymm13, ymmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000013B5 62e3953d730390 VPSHRDQ ymm16{k5}, ymm13, qword ptr [rbx]{1to4}, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000013BC 62a3952d7344db0890 VPSHRDQ ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000013C5 62a3952d7344dbf890 VPSHRDQ ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000013CE 62c395a873c790 VPSHRDQ ymm16, ymm13, ymm15, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000013D5 62e395a8730390 VPSHRDQ ymm16, ymm13, ymmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000013DC 62e395b8730390 VPSHRDQ ymm16, ymm13, qword ptr [rbx]{1to4}, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000013E3 62a395a87344db0890 VPSHRDQ ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000013EC 62a395a87344dbf890 VPSHRDQ ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000013F5 62c395ad73c790 VPSHRDQ ymm16{k5}{z}, ymm13, ymm15, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000013FC 62e395ad730390 VPSHRDQ ymm16{k5}{z}, ymm13, ymmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001403 62e395bd730390 VPSHRDQ ymm16{k5}{z}, ymm13, qword ptr [rbx]{1to4}, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000140A 62a395ad7344db0890 VPSHRDQ ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001413 62a395ad7344dbf890 VPSHRDQ ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000141C 6203bd4073c790 VPSHRDQ zmm24, zmm24, zmm31, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001423 6263bd40730390 VPSHRDQ zmm24, zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000142A 6263bd50730390 VPSHRDQ zmm24, zmm24, qword ptr [rbx]{1to8}, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001431 6223bd407344db0490 VPSHRDQ zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000143A 6223bd407344dbfc90 VPSHRDQ zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001443 6203bd4573c790 VPSHRDQ zmm24{k5}, zmm24, zmm31, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000144A 6263bd45730390 VPSHRDQ zmm24{k5}, zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001451 6263bd55730390 VPSHRDQ zmm24{k5}, zmm24, qword ptr [rbx]{1to8}, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001458 6223bd457344db0490 VPSHRDQ zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001461 6223bd457344dbfc90 VPSHRDQ zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000146A 6203bdc073c790 VPSHRDQ zmm24, zmm24, zmm31, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001471 6263bdc0730390 VPSHRDQ zmm24, zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001478 6263bdd0730390 VPSHRDQ zmm24, zmm24, qword ptr [rbx]{1to8}, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000147F 6223bdc07344db0490 VPSHRDQ zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001488 6223bdc07344dbfc90 VPSHRDQ zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001491 6203bdc573c790 VPSHRDQ zmm24{k5}{z}, zmm24, zmm31, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001498 6263bdc5730390 VPSHRDQ zmm24{k5}{z}, zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000149F 6263bdd5730390 VPSHRDQ zmm24{k5}{z}, zmm24, qword ptr [rbx]{1to8}, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000014A6 6223bdc57344db0490 VPSHRDQ zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000014AF 6223bdc57344dbfc90 VPSHRDQ zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000014B8 62f2450873d0 VPSHRDVD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000014BE 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000014BF 62f245087313 VPSHRDVD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000014C5 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000014C6 62f245187313 VPSHRDVD xmm2, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +00000000000014CC 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000014CD 62b245087354db10 VPSHRDVD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000014D5 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000014D6 62b245087354dbf0 VPSHRDVD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000014DE 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000014DF 62f2450d73d0 VPSHRDVD xmm2{k5}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000014E5 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000014E6 62f2450d7313 VPSHRDVD xmm2{k5}, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000014EC 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000014ED 62f2451d7313 VPSHRDVD xmm2{k5}, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +00000000000014F3 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000014F4 62b2450d7354db10 VPSHRDVD xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000014FC 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000014FD 62b2450d7354dbf0 VPSHRDVD xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000001505 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001506 62f2458873d0 VPSHRDVD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000150C 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000150D 62f245887313 VPSHRDVD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001513 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001514 62f245987313 VPSHRDVD xmm2, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +000000000000151A 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000151B 62b245887354db10 VPSHRDVD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000001523 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001524 62b245887354dbf0 VPSHRDVD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000152C 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000152D 62f2458d73d0 VPSHRDVD xmm2{k5}{z}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001533 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001534 62f2458d7313 VPSHRDVD xmm2{k5}{z}, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000153A 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000153B 62f2459d7313 VPSHRDVD xmm2{k5}{z}, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000001541 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001542 62b2458d7354db10 VPSHRDVD xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000154A 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000154B 62b2458d7354dbf0 VPSHRDVD xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000001553 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001554 62c2152873c7 VPSHRDVD ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000155A 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000155B 62e215287303 VPSHRDVD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000001561 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001562 62e215387303 VPSHRDVD ymm16, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +0000000000001568 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001569 62a215287344db08 VPSHRDVD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001571 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001572 62a215287344dbf8 VPSHRDVD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000157A 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000157B 62c2152d73c7 VPSHRDVD ymm16{k5}, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001581 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001582 62e2152d7303 VPSHRDVD ymm16{k5}, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000001588 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001589 62e2153d7303 VPSHRDVD ymm16{k5}, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +000000000000158F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001590 62a2152d7344db08 VPSHRDVD ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001598 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001599 62a2152d7344dbf8 VPSHRDVD ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000015A1 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000015A2 62c215a873c7 VPSHRDVD ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000015A8 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000015A9 62e215a87303 VPSHRDVD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000015AF 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000015B0 62e215b87303 VPSHRDVD ymm16, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +00000000000015B6 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000015B7 62a215a87344db08 VPSHRDVD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000015BF 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000015C0 62a215a87344dbf8 VPSHRDVD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000015C8 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000015C9 62c215ad73c7 VPSHRDVD ymm16{k5}{z}, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000015CF 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000015D0 62e215ad7303 VPSHRDVD ymm16{k5}{z}, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000015D6 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000015D7 62e215bd7303 VPSHRDVD ymm16{k5}{z}, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +00000000000015DD 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000015DE 62a215ad7344db08 VPSHRDVD ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000015E6 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000015E7 62a215ad7344dbf8 VPSHRDVD ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000015EF 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000015F0 62023d4073c7 VPSHRDVD zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000015F6 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000015F7 62623d407303 VPSHRDVD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000015FD 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000015FE 62623d507303 VPSHRDVD zmm24, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000001604 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001605 62223d407344db04 VPSHRDVD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000160D 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000160E 62223d407344dbfc VPSHRDVD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001616 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001617 62023d4573c7 VPSHRDVD zmm24{k5}, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000161D 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000161E 62623d457303 VPSHRDVD zmm24{k5}, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001624 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001625 62623d557303 VPSHRDVD zmm24{k5}, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +000000000000162B 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000162C 62223d457344db04 VPSHRDVD zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001634 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001635 62223d457344dbfc VPSHRDVD zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000163D 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000163E 62023dc073c7 VPSHRDVD zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001644 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001645 62623dc07303 VPSHRDVD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000164B 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000164C 62623dd07303 VPSHRDVD zmm24, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000001652 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001653 62223dc07344db04 VPSHRDVD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000165B 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000165C 62223dc07344dbfc VPSHRDVD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001664 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001665 62023dc573c7 VPSHRDVD zmm24{k5}{z}, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000166B 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000166C 62623dc57303 VPSHRDVD zmm24{k5}{z}, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001672 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001673 62623dd57303 VPSHRDVD zmm24{k5}{z}, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000001679 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000167A 62223dc57344db04 VPSHRDVD zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001682 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001683 62223dc57344dbfc VPSHRDVD zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000168B 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000168C 62f2c50873d0 VPSHRDVQ xmm2, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001692 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001693 62f2c5087313 VPSHRDVQ xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000001699 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000169A 62f2c5187313 VPSHRDVQ xmm2, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +00000000000016A0 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000016A1 62b2c5087354db10 VPSHRDVQ xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000016A9 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000016AA 62b2c5087354dbf0 VPSHRDVQ xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000016B2 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000016B3 62f2c50d73d0 VPSHRDVQ xmm2{k5}, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000016B9 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000016BA 62f2c50d7313 VPSHRDVQ xmm2{k5}, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000016C0 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000016C1 62f2c51d7313 VPSHRDVQ xmm2{k5}, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +00000000000016C7 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000016C8 62b2c50d7354db10 VPSHRDVQ xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000016D0 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000016D1 62b2c50d7354dbf0 VPSHRDVQ xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000016D9 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000016DA 62f2c58873d0 VPSHRDVQ xmm2, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000016E0 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000016E1 62f2c5887313 VPSHRDVQ xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000016E7 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000016E8 62f2c5987313 VPSHRDVQ xmm2, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +00000000000016EE 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000016EF 62b2c5887354db10 VPSHRDVQ xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000016F7 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000016F8 62b2c5887354dbf0 VPSHRDVQ xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000001700 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001701 62f2c58d73d0 VPSHRDVQ xmm2{k5}{z}, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001707 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001708 62f2c58d7313 VPSHRDVQ xmm2{k5}{z}, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000170E 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000170F 62f2c59d7313 VPSHRDVQ xmm2{k5}{z}, xmm7, qword ptr [rbx]{1to2} + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 2 times + +0000000000001715 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001716 62b2c58d7354db10 VPSHRDVQ xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000171E 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000171F 62b2c58d7354dbf0 VPSHRDVQ xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000001727 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001728 62c2952873c7 VPSHRDVQ ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000172E 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000172F 62e295287303 VPSHRDVQ ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000001735 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001736 62e295387303 VPSHRDVQ ymm16, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +000000000000173C 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000173D 62a295287344db08 VPSHRDVQ ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001745 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001746 62a295287344dbf8 VPSHRDVQ ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000174E 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000174F 62c2952d73c7 VPSHRDVQ ymm16{k5}, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001755 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001756 62e2952d7303 VPSHRDVQ ymm16{k5}, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000175C 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000175D 62e2953d7303 VPSHRDVQ ymm16{k5}, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +0000000000001763 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001764 62a2952d7344db08 VPSHRDVQ ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000176C 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000176D 62a2952d7344dbf8 VPSHRDVQ ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000001775 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001776 62c295a873c7 VPSHRDVQ ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000177C 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000177D 62e295a87303 VPSHRDVQ ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000001783 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001784 62e295b87303 VPSHRDVQ ymm16, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +000000000000178A 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000178B 62a295a87344db08 VPSHRDVQ ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001793 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001794 62a295a87344dbf8 VPSHRDVQ ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000179C 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000179D 62c295ad73c7 VPSHRDVQ ymm16{k5}{z}, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000017A3 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000017A4 62e295ad7303 VPSHRDVQ ymm16{k5}{z}, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000017AA 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000017AB 62e295bd7303 VPSHRDVQ ymm16{k5}{z}, ymm13, qword ptr [rbx]{1to4} + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 4 times + +00000000000017B1 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000017B2 62a295ad7344db08 VPSHRDVQ ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000017BA 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000017BB 62a295ad7344dbf8 VPSHRDVQ ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000017C3 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000017C4 6202bd4073c7 VPSHRDVQ zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000017CA 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000017CB 6262bd407303 VPSHRDVQ zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000017D1 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000017D2 6262bd507303 VPSHRDVQ zmm24, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +00000000000017D8 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000017D9 6222bd407344db04 VPSHRDVQ zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000017E1 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000017E2 6222bd407344dbfc VPSHRDVQ zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000017EA 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000017EB 6202bd4573c7 VPSHRDVQ zmm24{k5}, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000017F1 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000017F2 6262bd457303 VPSHRDVQ zmm24{k5}, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000017F8 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000017F9 6262bd557303 VPSHRDVQ zmm24{k5}, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +00000000000017FF 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001800 6222bd457344db04 VPSHRDVQ zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001808 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001809 6222bd457344dbfc VPSHRDVQ zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001811 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001812 6202bdc073c7 VPSHRDVQ zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001818 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001819 6262bdc07303 VPSHRDVQ zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000181F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001820 6262bdd07303 VPSHRDVQ zmm24, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +0000000000001826 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001827 6222bdc07344db04 VPSHRDVQ zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000182F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001830 6222bdc07344dbfc VPSHRDVQ zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000001838 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001839 6202bdc573c7 VPSHRDVQ zmm24{k5}{z}, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000183F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001840 6262bdc57303 VPSHRDVQ zmm24{k5}{z}, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000001846 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001847 6262bdd57303 VPSHRDVQ zmm24{k5}{z}, zmm24, qword ptr [rbx]{1to8} + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 8 bytes element 8 times + +000000000000184D 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000184E 6222bdc57344db04 VPSHRDVQ zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001856 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001857 6222bdc57344dbfc VPSHRDVQ zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000185F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001860 62f2c50872d0 VPSHRDVW xmm2, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001866 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001867 62f2c5087213 VPSHRDVW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000186D 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000186E 62b2c5087254db10 VPSHRDVW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000001876 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001877 62b2c5087254dbf0 VPSHRDVW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000187F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001880 62f2c50d72d0 VPSHRDVW xmm2{k5}, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000001886 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001887 62f2c50d7213 VPSHRDVW xmm2{k5}, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000188D 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000188E 62b2c50d7254db10 VPSHRDVW xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000001896 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001897 62b2c50d7254dbf0 VPSHRDVW xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000189F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000018A0 62f2c58872d0 VPSHRDVW xmm2, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000018A6 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000018A7 62f2c5887213 VPSHRDVW xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000018AD 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000018AE 62b2c5887254db10 VPSHRDVW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000018B6 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000018B7 62b2c5887254dbf0 VPSHRDVW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000018BF 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000018C0 62f2c58d72d0 VPSHRDVW xmm2{k5}{z}, xmm7, xmm0 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000018C6 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000018C7 62f2c58d7213 VPSHRDVW xmm2{k5}{z}, xmm7, xmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000018CD 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000018CE 62b2c58d7254db10 VPSHRDVW xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000018D6 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000018D7 62b2c58d7254dbf0 VPSHRDVW xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000018DF 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000018E0 62c2952872c7 VPSHRDVW ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000018E6 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000018E7 62e295287203 VPSHRDVW ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000018ED 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000018EE 62a295287244db08 VPSHRDVW ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000018F6 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000018F7 62a295287244dbf8 VPSHRDVW ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000018FF 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001900 62c2952d72c7 VPSHRDVW ymm16{k5}, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001906 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001907 62e2952d7203 VPSHRDVW ymm16{k5}, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000190D 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000190E 62a2952d7244db08 VPSHRDVW ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001916 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001917 62a2952d7244dbf8 VPSHRDVW ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000191F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001920 62c295a872c7 VPSHRDVW ymm16, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001926 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001927 62e295a87203 VPSHRDVW ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000192D 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000192E 62a295a87244db08 VPSHRDVW ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001936 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001937 62a295a87244dbf8 VPSHRDVW ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000193F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001940 62c295ad72c7 VPSHRDVW ymm16{k5}{z}, ymm13, ymm15 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000001946 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001947 62e295ad7203 VPSHRDVW ymm16{k5}{z}, ymm13, ymmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000194D 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000194E 62a295ad7244db08 VPSHRDVW ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000001956 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001957 62a295ad7244dbf8 VPSHRDVW ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000195F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001960 6202bd4072c7 VPSHRDVW zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001966 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001967 6262bd407203 VPSHRDVW zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000196D 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000196E 6222bd407244db04 VPSHRDVW zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001976 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001977 6222bd407244dbfc VPSHRDVW zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000197F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001980 6202bd4572c7 VPSHRDVW zmm24{k5}, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000001986 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001987 6262bd457203 VPSHRDVW zmm24{k5}, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000198D 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000198E 6222bd457244db04 VPSHRDVW zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000001996 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000001997 6222bd457244dbfc VPSHRDVW zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000199F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000019A0 6202bdc072c7 VPSHRDVW zmm24, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000019A6 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000019A7 6262bdc07203 VPSHRDVW zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000019AD 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000019AE 6222bdc07244db04 VPSHRDVW zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000019B6 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000019B7 6222bdc07244dbfc VPSHRDVW zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000019BF 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000019C0 6202bdc572c7 VPSHRDVW zmm24{k5}{z}, zmm24, zmm31 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000019C6 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000019C7 6262bdc57203 VPSHRDVW zmm24{k5}{z}, zmm24, zmmword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000019CD 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000019CE 6222bdc57244db04 VPSHRDVW zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000019D6 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000019D7 6222bdc57244dbfc VPSHRDVW zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000019DF 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000019E0 62f3c50872d090 VPSHRDW xmm2, xmm7, xmm0, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000019E7 62f3c508721390 VPSHRDW xmm2, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000019EE 62b3c5087254db1090 VPSHRDW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000019F7 62b3c5087254dbf090 VPSHRDW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001A00 62f3c50d72d090 VPSHRDW xmm2{k5}, xmm7, xmm0, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001A07 62f3c50d721390 VPSHRDW xmm2{k5}, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001A0E 62b3c50d7254db1090 VPSHRDW xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001A17 62b3c50d7254dbf090 VPSHRDW xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001A20 62f3c58872d090 VPSHRDW xmm2, xmm7, xmm0, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001A27 62f3c588721390 VPSHRDW xmm2, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001A2E 62b3c5887254db1090 VPSHRDW xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001A37 62b3c5887254dbf090 VPSHRDW xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001A40 62f3c58d72d090 VPSHRDW xmm2{k5}{z}, xmm7, xmm0, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001A47 62f3c58d721390 VPSHRDW xmm2{k5}{z}, xmm7, xmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001A4E 62b3c58d7254db1090 VPSHRDW xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001A57 62b3c58d7254dbf090 VPSHRDW xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001A60 62c3952872c790 VPSHRDW ymm16, ymm13, ymm15, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001A67 62e39528720390 VPSHRDW ymm16, ymm13, ymmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001A6E 62a395287244db0890 VPSHRDW ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001A77 62a395287244dbf890 VPSHRDW ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001A80 62c3952d72c790 VPSHRDW ymm16{k5}, ymm13, ymm15, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001A87 62e3952d720390 VPSHRDW ymm16{k5}, ymm13, ymmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001A8E 62a3952d7244db0890 VPSHRDW ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001A97 62a3952d7244dbf890 VPSHRDW ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001AA0 62c395a872c790 VPSHRDW ymm16, ymm13, ymm15, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001AA7 62e395a8720390 VPSHRDW ymm16, ymm13, ymmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001AAE 62a395a87244db0890 VPSHRDW ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001AB7 62a395a87244dbf890 VPSHRDW ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001AC0 62c395ad72c790 VPSHRDW ymm16{k5}{z}, ymm13, ymm15, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001AC7 62e395ad720390 VPSHRDW ymm16{k5}{z}, ymm13, ymmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001ACE 62a395ad7244db0890 VPSHRDW ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001AD7 62a395ad7244dbf890 VPSHRDW ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001AE0 6203bd4072c790 VPSHRDW zmm24, zmm24, zmm31, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001AE7 6263bd40720390 VPSHRDW zmm24, zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001AEE 6223bd407244db0490 VPSHRDW zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001AF7 6223bd407244dbfc90 VPSHRDW zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001B00 6203bd4572c790 VPSHRDW zmm24{k5}, zmm24, zmm31, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001B07 6263bd45720390 VPSHRDW zmm24{k5}, zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001B0E 6223bd457244db0490 VPSHRDW zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001B17 6223bd457244dbfc90 VPSHRDW zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001B20 6203bdc072c790 VPSHRDW zmm24, zmm24, zmm31, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001B27 6263bdc0720390 VPSHRDW zmm24, zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001B2E 6223bdc07244db0490 VPSHRDW zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001B37 6223bdc07244dbfc90 VPSHRDW zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001B40 6203bdc572c790 VPSHRDW zmm24{k5}{z}, zmm24, zmm31, 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001B47 6263bdc5720390 VPSHRDW zmm24{k5}{z}, zmm24, zmmword ptr [rbx], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001B4E 6223bdc57244db0490 VPSHRDW zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000001B57 6223bdc57244dbfc90 VPSHRDW zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + Operand: 4, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + diff --git a/bddisasm_test/avx512/avx512vnni_64 b/bddisasm_test/avx512/avx512vnni_64 new file mode 100644 index 0000000..4152e2c --- /dev/null +++ b/bddisasm_test/avx512/avx512vnni_64 @@ -0,0 +1 @@ +bEPbEPbEPbEPTbEPTbE PbE PbEPbE PTbE PTbEPbEPbEPbEPTbEPTbEPbEPbEPbEPTbEPTb(Pb(Pb8Pb(PDb(PDb-Pb-Pb=Pb-PDb-PDbPbPbPbPDbPDbPbPbPbPDbPDb=@Pbb=@Pbb=PPb"=@PDb"=@PDb=EPbb=EPbb=UPb"=EPDb"=EPDb=Pbb=Pbb=Pb"=PDb"=PDb=Pbb=Pbb=Pb"=PDb"=PDbEQbEQbEQbEQTbEQTbE QbE QbEQbE QTbE QTbEQbEQbEQbEQTbEQTbEQbEQbEQbEQTbEQTb(Qb(Qb8Qb(QDb(QDb-Qb-Qb=Qb-QDb-QDbQbQbQbQDbQDbQbQbQbQDbQDb=@Qbb=@Qbb=PQb"=@QDb"=@QDb=EQbb=EQbb=UQb"=EQDb"=EQDb=Qbb=Qbb=Qb"=QDb"=QDb=Qbb=Qbb=Qb"=QDb"=QDbERbERbERbERTbERTbE RbE RbERbE RTbE RTbERbERbERbERTbERTbERbERbERbERTbERTb(Rb(Rb8Rb(RDb(RDb-Rb-Rb=Rb-RDb-RDbRbRbRbRDbRDbRbRbRbRDbRDb=@Rbb=@Rbb=PRb"=@RDb"=@RDb=ERbb=ERbb=URb"=ERDb"=ERDb=Rbb=Rbb=Rb"=RDb"=RDb=Rbb=Rbb=Rb"=RDb"=RDbESbESbESbESTbESTbE SbE SbESbE STbE STbESbESbESbESTbESTbESbESbESbESTbESTb(Sb(Sb8Sb(SDb(SDb-Sb-Sb=Sb-SDb-SDbSbSbSbSDbSDbSbSbSbSDbSDb=@Sbb=@Sbb=PSb"=@SDb"=@SDb=ESbb=ESbb=USb"=ESDb"=ESDb=Sbb=Sbb=Sb"=SDb"=SDb=Sbb=Sbb=Sb"=SDb"=SD \ No newline at end of file diff --git a/bddisasm_test/avx512/avx512vnni_64.asm b/bddisasm_test/avx512/avx512vnni_64.asm new file mode 100644 index 0000000..892cd63 --- /dev/null +++ b/bddisasm_test/avx512/avx512vnni_64.asm @@ -0,0 +1,242 @@ + bits 64 + + vpdpbusd xmm2, xmm7, xmm0 + vpdpbusd xmm2, xmm7, [rbx] + vpdpbusd xmm2, xmm7, [rbx]{1to4} + vpdpbusd xmm2, xmm7, [rbx+r11*8+256] + vpdpbusd xmm2, xmm7, [rbx+r11*8-256] + vpdpbusd xmm2{k5}, xmm7, xmm0 + vpdpbusd xmm2{k5}, xmm7, [rbx] + vpdpbusd xmm2{k5}, xmm7, [rbx]{1to4} + vpdpbusd xmm2{k5}, xmm7, [rbx+r11*8+256] + vpdpbusd xmm2{k5}, xmm7, [rbx+r11*8-256] + vpdpbusd xmm2{z}, xmm7, xmm0 + vpdpbusd xmm2{z}, xmm7, [rbx] + vpdpbusd xmm2{z}, xmm7, [rbx]{1to4} + vpdpbusd xmm2{z}, xmm7, [rbx+r11*8+256] + vpdpbusd xmm2{z}, xmm7, [rbx+r11*8-256] + vpdpbusd xmm2{k5}{z}, xmm7, xmm0 + vpdpbusd xmm2{k5}{z}, xmm7, [rbx] + vpdpbusd xmm2{k5}{z}, xmm7, [rbx]{1to4} + vpdpbusd xmm2{k5}{z}, xmm7, [rbx+r11*8+256] + vpdpbusd xmm2{k5}{z}, xmm7, [rbx+r11*8-256] + vpdpbusd ymm16, ymm13, ymm15 + vpdpbusd ymm16, ymm13, [rbx] + vpdpbusd ymm16, ymm13, [rbx]{1to8} + vpdpbusd ymm16, ymm13, [rbx+r11*8+256] + vpdpbusd ymm16, ymm13, [rbx+r11*8-256] + vpdpbusd ymm16{k5}, ymm13, ymm15 + vpdpbusd ymm16{k5}, ymm13, [rbx] + vpdpbusd ymm16{k5}, ymm13, [rbx]{1to8} + vpdpbusd ymm16{k5}, ymm13, [rbx+r11*8+256] + vpdpbusd ymm16{k5}, ymm13, [rbx+r11*8-256] + vpdpbusd ymm16{z}, ymm13, ymm15 + vpdpbusd ymm16{z}, ymm13, [rbx] + vpdpbusd ymm16{z}, ymm13, [rbx]{1to8} + vpdpbusd ymm16{z}, ymm13, [rbx+r11*8+256] + vpdpbusd ymm16{z}, ymm13, [rbx+r11*8-256] + vpdpbusd ymm16{k5}{z}, ymm13, ymm15 + vpdpbusd ymm16{k5}{z}, ymm13, [rbx] + vpdpbusd ymm16{k5}{z}, ymm13, [rbx]{1to8} + vpdpbusd ymm16{k5}{z}, ymm13, [rbx+r11*8+256] + vpdpbusd ymm16{k5}{z}, ymm13, [rbx+r11*8-256] + vpdpbusd zmm24, zmm24, zmm31 + vpdpbusd zmm24, zmm24, [rbx] + vpdpbusd zmm24, zmm24, [rbx]{1to16} + vpdpbusd zmm24, zmm24, [rbx+r11*8+256] + vpdpbusd zmm24, zmm24, [rbx+r11*8-256] + vpdpbusd zmm24{k5}, zmm24, zmm31 + vpdpbusd zmm24{k5}, zmm24, [rbx] + vpdpbusd zmm24{k5}, zmm24, [rbx]{1to16} + vpdpbusd zmm24{k5}, zmm24, [rbx+r11*8+256] + vpdpbusd zmm24{k5}, zmm24, [rbx+r11*8-256] + vpdpbusd zmm24{z}, zmm24, zmm31 + vpdpbusd zmm24{z}, zmm24, [rbx] + vpdpbusd zmm24{z}, zmm24, [rbx]{1to16} + vpdpbusd zmm24{z}, zmm24, [rbx+r11*8+256] + vpdpbusd zmm24{z}, zmm24, [rbx+r11*8-256] + vpdpbusd zmm24{k5}{z}, zmm24, zmm31 + vpdpbusd zmm24{k5}{z}, zmm24, [rbx] + vpdpbusd zmm24{k5}{z}, zmm24, [rbx]{1to16} + vpdpbusd zmm24{k5}{z}, zmm24, [rbx+r11*8+256] + vpdpbusd zmm24{k5}{z}, zmm24, [rbx+r11*8-256] + vpdpbusds xmm2, xmm7, xmm0 + vpdpbusds xmm2, xmm7, [rbx] + vpdpbusds xmm2, xmm7, [rbx]{1to4} + vpdpbusds xmm2, xmm7, [rbx+r11*8+256] + vpdpbusds xmm2, xmm7, [rbx+r11*8-256] + vpdpbusds xmm2{k5}, xmm7, xmm0 + vpdpbusds xmm2{k5}, xmm7, [rbx] + vpdpbusds xmm2{k5}, xmm7, [rbx]{1to4} + vpdpbusds xmm2{k5}, xmm7, [rbx+r11*8+256] + vpdpbusds xmm2{k5}, xmm7, [rbx+r11*8-256] + vpdpbusds xmm2{z}, xmm7, xmm0 + vpdpbusds xmm2{z}, xmm7, [rbx] + vpdpbusds xmm2{z}, xmm7, [rbx]{1to4} + vpdpbusds xmm2{z}, xmm7, [rbx+r11*8+256] + vpdpbusds xmm2{z}, xmm7, [rbx+r11*8-256] + vpdpbusds xmm2{k5}{z}, xmm7, xmm0 + vpdpbusds xmm2{k5}{z}, xmm7, [rbx] + vpdpbusds xmm2{k5}{z}, xmm7, [rbx]{1to4} + vpdpbusds xmm2{k5}{z}, xmm7, [rbx+r11*8+256] + vpdpbusds xmm2{k5}{z}, xmm7, [rbx+r11*8-256] + vpdpbusds ymm16, ymm13, ymm15 + vpdpbusds ymm16, ymm13, [rbx] + vpdpbusds ymm16, ymm13, [rbx]{1to8} + vpdpbusds ymm16, ymm13, [rbx+r11*8+256] + vpdpbusds ymm16, ymm13, [rbx+r11*8-256] + vpdpbusds ymm16{k5}, ymm13, ymm15 + vpdpbusds ymm16{k5}, ymm13, [rbx] + vpdpbusds ymm16{k5}, ymm13, [rbx]{1to8} + vpdpbusds ymm16{k5}, ymm13, [rbx+r11*8+256] + vpdpbusds ymm16{k5}, ymm13, [rbx+r11*8-256] + vpdpbusds ymm16{z}, ymm13, ymm15 + vpdpbusds ymm16{z}, ymm13, [rbx] + vpdpbusds ymm16{z}, ymm13, [rbx]{1to8} + vpdpbusds ymm16{z}, ymm13, [rbx+r11*8+256] + vpdpbusds ymm16{z}, ymm13, [rbx+r11*8-256] + vpdpbusds ymm16{k5}{z}, ymm13, ymm15 + vpdpbusds ymm16{k5}{z}, ymm13, [rbx] + vpdpbusds ymm16{k5}{z}, ymm13, [rbx]{1to8} + vpdpbusds ymm16{k5}{z}, ymm13, [rbx+r11*8+256] + vpdpbusds ymm16{k5}{z}, ymm13, [rbx+r11*8-256] + vpdpbusds zmm24, zmm24, zmm31 + vpdpbusds zmm24, zmm24, [rbx] + vpdpbusds zmm24, zmm24, [rbx]{1to16} + vpdpbusds zmm24, zmm24, [rbx+r11*8+256] + vpdpbusds zmm24, zmm24, [rbx+r11*8-256] + vpdpbusds zmm24{k5}, zmm24, zmm31 + vpdpbusds zmm24{k5}, zmm24, [rbx] + vpdpbusds zmm24{k5}, zmm24, [rbx]{1to16} + vpdpbusds zmm24{k5}, zmm24, [rbx+r11*8+256] + vpdpbusds zmm24{k5}, zmm24, [rbx+r11*8-256] + vpdpbusds zmm24{z}, zmm24, zmm31 + vpdpbusds zmm24{z}, zmm24, [rbx] + vpdpbusds zmm24{z}, zmm24, [rbx]{1to16} + vpdpbusds zmm24{z}, zmm24, [rbx+r11*8+256] + vpdpbusds zmm24{z}, zmm24, [rbx+r11*8-256] + vpdpbusds zmm24{k5}{z}, zmm24, zmm31 + vpdpbusds zmm24{k5}{z}, zmm24, [rbx] + vpdpbusds zmm24{k5}{z}, zmm24, [rbx]{1to16} + vpdpbusds zmm24{k5}{z}, zmm24, [rbx+r11*8+256] + vpdpbusds zmm24{k5}{z}, zmm24, [rbx+r11*8-256] + vpdpwssd xmm2, xmm7, xmm0 + vpdpwssd xmm2, xmm7, [rbx] + vpdpwssd xmm2, xmm7, [rbx]{1to4} + vpdpwssd xmm2, xmm7, [rbx+r11*8+256] + vpdpwssd xmm2, xmm7, [rbx+r11*8-256] + vpdpwssd xmm2{k5}, xmm7, xmm0 + vpdpwssd xmm2{k5}, xmm7, [rbx] + vpdpwssd xmm2{k5}, xmm7, [rbx]{1to4} + vpdpwssd xmm2{k5}, xmm7, [rbx+r11*8+256] + vpdpwssd xmm2{k5}, xmm7, [rbx+r11*8-256] + vpdpwssd xmm2{z}, xmm7, xmm0 + vpdpwssd xmm2{z}, xmm7, [rbx] + vpdpwssd xmm2{z}, xmm7, [rbx]{1to4} + vpdpwssd xmm2{z}, xmm7, [rbx+r11*8+256] + vpdpwssd xmm2{z}, xmm7, [rbx+r11*8-256] + vpdpwssd xmm2{k5}{z}, xmm7, xmm0 + vpdpwssd xmm2{k5}{z}, xmm7, [rbx] + vpdpwssd xmm2{k5}{z}, xmm7, [rbx]{1to4} + vpdpwssd xmm2{k5}{z}, xmm7, [rbx+r11*8+256] + vpdpwssd xmm2{k5}{z}, xmm7, [rbx+r11*8-256] + vpdpwssd ymm16, ymm13, ymm15 + vpdpwssd ymm16, ymm13, [rbx] + vpdpwssd ymm16, ymm13, [rbx]{1to8} + vpdpwssd ymm16, ymm13, [rbx+r11*8+256] + vpdpwssd ymm16, ymm13, [rbx+r11*8-256] + vpdpwssd ymm16{k5}, ymm13, ymm15 + vpdpwssd ymm16{k5}, ymm13, [rbx] + vpdpwssd ymm16{k5}, ymm13, [rbx]{1to8} + vpdpwssd ymm16{k5}, ymm13, [rbx+r11*8+256] + vpdpwssd ymm16{k5}, ymm13, [rbx+r11*8-256] + vpdpwssd ymm16{z}, ymm13, ymm15 + vpdpwssd ymm16{z}, ymm13, [rbx] + vpdpwssd ymm16{z}, ymm13, [rbx]{1to8} + vpdpwssd ymm16{z}, ymm13, [rbx+r11*8+256] + vpdpwssd ymm16{z}, ymm13, [rbx+r11*8-256] + vpdpwssd ymm16{k5}{z}, ymm13, ymm15 + vpdpwssd ymm16{k5}{z}, ymm13, [rbx] + vpdpwssd ymm16{k5}{z}, ymm13, [rbx]{1to8} + vpdpwssd ymm16{k5}{z}, ymm13, [rbx+r11*8+256] + vpdpwssd ymm16{k5}{z}, ymm13, [rbx+r11*8-256] + vpdpwssd zmm24, zmm24, zmm31 + vpdpwssd zmm24, zmm24, [rbx] + vpdpwssd zmm24, zmm24, [rbx]{1to16} + vpdpwssd zmm24, zmm24, [rbx+r11*8+256] + vpdpwssd zmm24, zmm24, [rbx+r11*8-256] + vpdpwssd zmm24{k5}, zmm24, zmm31 + vpdpwssd zmm24{k5}, zmm24, [rbx] + vpdpwssd zmm24{k5}, zmm24, [rbx]{1to16} + vpdpwssd zmm24{k5}, zmm24, [rbx+r11*8+256] + vpdpwssd zmm24{k5}, zmm24, [rbx+r11*8-256] + vpdpwssd zmm24{z}, zmm24, zmm31 + vpdpwssd zmm24{z}, zmm24, [rbx] + vpdpwssd zmm24{z}, zmm24, [rbx]{1to16} + vpdpwssd zmm24{z}, zmm24, [rbx+r11*8+256] + vpdpwssd zmm24{z}, zmm24, [rbx+r11*8-256] + vpdpwssd zmm24{k5}{z}, zmm24, zmm31 + vpdpwssd zmm24{k5}{z}, zmm24, [rbx] + vpdpwssd zmm24{k5}{z}, zmm24, [rbx]{1to16} + vpdpwssd zmm24{k5}{z}, zmm24, [rbx+r11*8+256] + vpdpwssd zmm24{k5}{z}, zmm24, [rbx+r11*8-256] + vpdpwssds xmm2, xmm7, xmm0 + vpdpwssds xmm2, xmm7, [rbx] + vpdpwssds xmm2, xmm7, [rbx]{1to4} + vpdpwssds xmm2, xmm7, [rbx+r11*8+256] + vpdpwssds xmm2, xmm7, [rbx+r11*8-256] + vpdpwssds xmm2{k5}, xmm7, xmm0 + vpdpwssds xmm2{k5}, xmm7, [rbx] + vpdpwssds xmm2{k5}, xmm7, [rbx]{1to4} + vpdpwssds xmm2{k5}, xmm7, [rbx+r11*8+256] + vpdpwssds xmm2{k5}, xmm7, [rbx+r11*8-256] + vpdpwssds xmm2{z}, xmm7, xmm0 + vpdpwssds xmm2{z}, xmm7, [rbx] + vpdpwssds xmm2{z}, xmm7, [rbx]{1to4} + vpdpwssds xmm2{z}, xmm7, [rbx+r11*8+256] + vpdpwssds xmm2{z}, xmm7, [rbx+r11*8-256] + vpdpwssds xmm2{k5}{z}, xmm7, xmm0 + vpdpwssds xmm2{k5}{z}, xmm7, [rbx] + vpdpwssds xmm2{k5}{z}, xmm7, [rbx]{1to4} + vpdpwssds xmm2{k5}{z}, xmm7, [rbx+r11*8+256] + vpdpwssds xmm2{k5}{z}, xmm7, [rbx+r11*8-256] + vpdpwssds ymm16, ymm13, ymm15 + vpdpwssds ymm16, ymm13, [rbx] + vpdpwssds ymm16, ymm13, [rbx]{1to8} + vpdpwssds ymm16, ymm13, [rbx+r11*8+256] + vpdpwssds ymm16, ymm13, [rbx+r11*8-256] + vpdpwssds ymm16{k5}, ymm13, ymm15 + vpdpwssds ymm16{k5}, ymm13, [rbx] + vpdpwssds ymm16{k5}, ymm13, [rbx]{1to8} + vpdpwssds ymm16{k5}, ymm13, [rbx+r11*8+256] + vpdpwssds ymm16{k5}, ymm13, [rbx+r11*8-256] + vpdpwssds ymm16{z}, ymm13, ymm15 + vpdpwssds ymm16{z}, ymm13, [rbx] + vpdpwssds ymm16{z}, ymm13, [rbx]{1to8} + vpdpwssds ymm16{z}, ymm13, [rbx+r11*8+256] + vpdpwssds ymm16{z}, ymm13, [rbx+r11*8-256] + vpdpwssds ymm16{k5}{z}, ymm13, ymm15 + vpdpwssds ymm16{k5}{z}, ymm13, [rbx] + vpdpwssds ymm16{k5}{z}, ymm13, [rbx]{1to8} + vpdpwssds ymm16{k5}{z}, ymm13, [rbx+r11*8+256] + vpdpwssds ymm16{k5}{z}, ymm13, [rbx+r11*8-256] + vpdpwssds zmm24, zmm24, zmm31 + vpdpwssds zmm24, zmm24, [rbx] + vpdpwssds zmm24, zmm24, [rbx]{1to16} + vpdpwssds zmm24, zmm24, [rbx+r11*8+256] + vpdpwssds zmm24, zmm24, [rbx+r11*8-256] + vpdpwssds zmm24{k5}, zmm24, zmm31 + vpdpwssds zmm24{k5}, zmm24, [rbx] + vpdpwssds zmm24{k5}, zmm24, [rbx]{1to16} + vpdpwssds zmm24{k5}, zmm24, [rbx+r11*8+256] + vpdpwssds zmm24{k5}, zmm24, [rbx+r11*8-256] + vpdpwssds zmm24{z}, zmm24, zmm31 + vpdpwssds zmm24{z}, zmm24, [rbx] + vpdpwssds zmm24{z}, zmm24, [rbx]{1to16} + vpdpwssds zmm24{z}, zmm24, [rbx+r11*8+256] + vpdpwssds zmm24{z}, zmm24, [rbx+r11*8-256] + vpdpwssds zmm24{k5}{z}, zmm24, zmm31 + vpdpwssds zmm24{k5}{z}, zmm24, [rbx] + vpdpwssds zmm24{k5}{z}, zmm24, [rbx]{1to16} + vpdpwssds zmm24{k5}{z}, zmm24, [rbx+r11*8+256] + vpdpwssds zmm24{k5}{z}, zmm24, [rbx+r11*8-256] diff --git a/bddisasm_test/avx512/avx512vnni_64.result b/bddisasm_test/avx512/avx512vnni_64.result new file mode 100644 index 0000000..3029215 --- /dev/null +++ b/bddisasm_test/avx512/avx512vnni_64.result @@ -0,0 +1,5040 @@ +0000000000000000 62f2450850d0 VPDPBUSD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000006 62f245085013 VPDPBUSD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000000C 62f245185013 VPDPBUSD xmm2, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000000012 62b245085054db10 VPDPBUSD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000001A 62b245085054dbf0 VPDPBUSD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000022 62f2450d50d0 VPDPBUSD xmm2{k5}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000028 62f2450d5013 VPDPBUSD xmm2{k5}, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000002E 62f2451d5013 VPDPBUSD xmm2{k5}, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000000034 62b2450d5054db10 VPDPBUSD xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000003C 62b2450d5054dbf0 VPDPBUSD xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000044 62f2458850d0 VPDPBUSD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000004A 62f245885013 VPDPBUSD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000050 62f245985013 VPDPBUSD xmm2, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000000056 62b245885054db10 VPDPBUSD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000005E 62b245885054dbf0 VPDPBUSD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000066 62f2458d50d0 VPDPBUSD xmm2{k5}{z}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000006C 62f2458d5013 VPDPBUSD xmm2{k5}{z}, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000072 62f2459d5013 VPDPBUSD xmm2{k5}{z}, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000000078 62b2458d5054db10 VPDPBUSD xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000080 62b2458d5054dbf0 VPDPBUSD xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000088 62c2152850c7 VPDPBUSD ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000008E 62e215285003 VPDPBUSD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000094 62e215385003 VPDPBUSD ymm16, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +000000000000009A 62a215285044db08 VPDPBUSD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000000A2 62a215285044dbf8 VPDPBUSD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000000AA 62c2152d50c7 VPDPBUSD ymm16{k5}, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000000B0 62e2152d5003 VPDPBUSD ymm16{k5}, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000000B6 62e2153d5003 VPDPBUSD ymm16{k5}, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +00000000000000BC 62a2152d5044db08 VPDPBUSD ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000000C4 62a2152d5044dbf8 VPDPBUSD ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000000CC 62c215a850c7 VPDPBUSD ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000000D2 62e215a85003 VPDPBUSD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000000D8 62e215b85003 VPDPBUSD ymm16, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +00000000000000DE 62a215a85044db08 VPDPBUSD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000000E6 62a215a85044dbf8 VPDPBUSD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000000EE 62c215ad50c7 VPDPBUSD ymm16{k5}{z}, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000000F4 62e215ad5003 VPDPBUSD ymm16{k5}{z}, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000000FA 62e215bd5003 VPDPBUSD ymm16{k5}{z}, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +0000000000000100 62a215ad5044db08 VPDPBUSD ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000108 62a215ad5044dbf8 VPDPBUSD ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000110 62023d4050c7 VPDPBUSD zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000116 62623d405003 VPDPBUSD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000011C 62623d505003 VPDPBUSD zmm24, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000000122 62223d405044db04 VPDPBUSD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000012A 62223d405044dbfc VPDPBUSD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000132 62023d4550c7 VPDPBUSD zmm24{k5}, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000138 62623d455003 VPDPBUSD zmm24{k5}, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000013E 62623d555003 VPDPBUSD zmm24{k5}, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000000144 62223d455044db04 VPDPBUSD zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000014C 62223d455044dbfc VPDPBUSD zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000154 62023dc050c7 VPDPBUSD zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000015A 62623dc05003 VPDPBUSD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000160 62623dd05003 VPDPBUSD zmm24, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000000166 62223dc05044db04 VPDPBUSD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000016E 62223dc05044dbfc VPDPBUSD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000176 62023dc550c7 VPDPBUSD zmm24{k5}{z}, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000017C 62623dc55003 VPDPBUSD zmm24{k5}{z}, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000182 62623dd55003 VPDPBUSD zmm24{k5}{z}, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000000188 62223dc55044db04 VPDPBUSD zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000190 62223dc55044dbfc VPDPBUSD zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000198 62f2450851d0 VPDPBUSDS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000019E 62f245085113 VPDPBUSDS xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000001A4 62f245185113 VPDPBUSDS xmm2, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +00000000000001AA 62b245085154db10 VPDPBUSDS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000001B2 62b245085154dbf0 VPDPBUSDS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000001BA 62f2450d51d0 VPDPBUSDS xmm2{k5}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000001C0 62f2450d5113 VPDPBUSDS xmm2{k5}, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000001C6 62f2451d5113 VPDPBUSDS xmm2{k5}, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +00000000000001CC 62b2450d5154db10 VPDPBUSDS xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000001D4 62b2450d5154dbf0 VPDPBUSDS xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000001DC 62f2458851d0 VPDPBUSDS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000001E2 62f245885113 VPDPBUSDS xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000001E8 62f245985113 VPDPBUSDS xmm2, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +00000000000001EE 62b245885154db10 VPDPBUSDS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000001F6 62b245885154dbf0 VPDPBUSDS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000001FE 62f2458d51d0 VPDPBUSDS xmm2{k5}{z}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000204 62f2458d5113 VPDPBUSDS xmm2{k5}{z}, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000020A 62f2459d5113 VPDPBUSDS xmm2{k5}{z}, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000000210 62b2458d5154db10 VPDPBUSDS xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000218 62b2458d5154dbf0 VPDPBUSDS xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000220 62c2152851c7 VPDPBUSDS ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000226 62e215285103 VPDPBUSDS ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000022C 62e215385103 VPDPBUSDS ymm16, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +0000000000000232 62a215285144db08 VPDPBUSDS ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000023A 62a215285144dbf8 VPDPBUSDS ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000242 62c2152d51c7 VPDPBUSDS ymm16{k5}, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000248 62e2152d5103 VPDPBUSDS ymm16{k5}, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000024E 62e2153d5103 VPDPBUSDS ymm16{k5}, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +0000000000000254 62a2152d5144db08 VPDPBUSDS ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000025C 62a2152d5144dbf8 VPDPBUSDS ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000264 62c215a851c7 VPDPBUSDS ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000026A 62e215a85103 VPDPBUSDS ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000270 62e215b85103 VPDPBUSDS ymm16, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +0000000000000276 62a215a85144db08 VPDPBUSDS ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000027E 62a215a85144dbf8 VPDPBUSDS ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000286 62c215ad51c7 VPDPBUSDS ymm16{k5}{z}, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000028C 62e215ad5103 VPDPBUSDS ymm16{k5}{z}, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000292 62e215bd5103 VPDPBUSDS ymm16{k5}{z}, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +0000000000000298 62a215ad5144db08 VPDPBUSDS ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000002A0 62a215ad5144dbf8 VPDPBUSDS ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000002A8 62023d4051c7 VPDPBUSDS zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000002AE 62623d405103 VPDPBUSDS zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000002B4 62623d505103 VPDPBUSDS zmm24, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +00000000000002BA 62223d405144db04 VPDPBUSDS zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000002C2 62223d405144dbfc VPDPBUSDS zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000002CA 62023d4551c7 VPDPBUSDS zmm24{k5}, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000002D0 62623d455103 VPDPBUSDS zmm24{k5}, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000002D6 62623d555103 VPDPBUSDS zmm24{k5}, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +00000000000002DC 62223d455144db04 VPDPBUSDS zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000002E4 62223d455144dbfc VPDPBUSDS zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000002EC 62023dc051c7 VPDPBUSDS zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000002F2 62623dc05103 VPDPBUSDS zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000002F8 62623dd05103 VPDPBUSDS zmm24, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +00000000000002FE 62223dc05144db04 VPDPBUSDS zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000306 62223dc05144dbfc VPDPBUSDS zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000030E 62023dc551c7 VPDPBUSDS zmm24{k5}{z}, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000314 62623dc55103 VPDPBUSDS zmm24{k5}{z}, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000031A 62623dd55103 VPDPBUSDS zmm24{k5}{z}, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000000320 62223dc55144db04 VPDPBUSDS zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000328 62223dc55144dbfc VPDPBUSDS zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000330 62f2450852d0 VPDPWSSD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000336 62f245085213 VPDPWSSD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000033C 62f245185213 VPDPWSSD xmm2, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000000342 62b245085254db10 VPDPWSSD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000034A 62b245085254dbf0 VPDPWSSD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000352 62f2450d52d0 VPDPWSSD xmm2{k5}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000358 62f2450d5213 VPDPWSSD xmm2{k5}, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000035E 62f2451d5213 VPDPWSSD xmm2{k5}, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000000364 62b2450d5254db10 VPDPWSSD xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000036C 62b2450d5254dbf0 VPDPWSSD xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000374 62f2458852d0 VPDPWSSD xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000037A 62f245885213 VPDPWSSD xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000380 62f245985213 VPDPWSSD xmm2, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000000386 62b245885254db10 VPDPWSSD xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +000000000000038E 62b245885254dbf0 VPDPWSSD xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000396 62f2458d52d0 VPDPWSSD xmm2{k5}{z}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000039C 62f2458d5213 VPDPWSSD xmm2{k5}{z}, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000003A2 62f2459d5213 VPDPWSSD xmm2{k5}{z}, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +00000000000003A8 62b2458d5254db10 VPDPWSSD xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000003B0 62b2458d5254dbf0 VPDPWSSD xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000003B8 62c2152852c7 VPDPWSSD ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000003BE 62e215285203 VPDPWSSD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000003C4 62e215385203 VPDPWSSD ymm16, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +00000000000003CA 62a215285244db08 VPDPWSSD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000003D2 62a215285244dbf8 VPDPWSSD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000003DA 62c2152d52c7 VPDPWSSD ymm16{k5}, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000003E0 62e2152d5203 VPDPWSSD ymm16{k5}, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000003E6 62e2153d5203 VPDPWSSD ymm16{k5}, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +00000000000003EC 62a2152d5244db08 VPDPWSSD ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000003F4 62a2152d5244dbf8 VPDPWSSD ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000003FC 62c215a852c7 VPDPWSSD ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000402 62e215a85203 VPDPWSSD ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000408 62e215b85203 VPDPWSSD ymm16, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +000000000000040E 62a215a85244db08 VPDPWSSD ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000416 62a215a85244dbf8 VPDPWSSD ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +000000000000041E 62c215ad52c7 VPDPWSSD ymm16{k5}{z}, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000424 62e215ad5203 VPDPWSSD ymm16{k5}{z}, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000042A 62e215bd5203 VPDPWSSD ymm16{k5}{z}, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +0000000000000430 62a215ad5244db08 VPDPWSSD ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +0000000000000438 62a215ad5244dbf8 VPDPWSSD ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000440 62023d4052c7 VPDPWSSD zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000446 62623d405203 VPDPWSSD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000044C 62623d505203 VPDPWSSD zmm24, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000000452 62223d405244db04 VPDPWSSD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000045A 62223d405244dbfc VPDPWSSD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000462 62023d4552c7 VPDPWSSD zmm24{k5}, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000468 62623d455203 VPDPWSSD zmm24{k5}, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000046E 62623d555203 VPDPWSSD zmm24{k5}, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000000474 62223d455244db04 VPDPWSSD zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000047C 62223d455244dbfc VPDPWSSD zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +0000000000000484 62023dc052c7 VPDPWSSD zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +000000000000048A 62623dc05203 VPDPWSSD zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000490 62623dd05203 VPDPWSSD zmm24, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000000496 62223dc05244db04 VPDPWSSD zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +000000000000049E 62223dc05244dbfc VPDPWSSD zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000004A6 62023dc552c7 VPDPWSSD zmm24{k5}{z}, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000004AC 62623dc55203 VPDPWSSD zmm24{k5}{z}, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000004B2 62623dd55203 VPDPWSSD zmm24{k5}{z}, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +00000000000004B8 62223dc55244db04 VPDPWSSD zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000004C0 62223dc55244dbfc VPDPWSSD zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000004C8 62f2450853d0 VPDPWSSDS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000004CE 62f245085313 VPDPWSSDS xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000004D4 62f245185313 VPDPWSSDS xmm2, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +00000000000004DA 62b245085354db10 VPDPWSSDS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +00000000000004E2 62b245085354dbf0 VPDPWSSDS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +00000000000004EA 62f2450d53d0 VPDPWSSDS xmm2{k5}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000004F0 62f2450d5313 VPDPWSSDS xmm2{k5}, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000004F6 62f2451d5313 VPDPWSSDS xmm2{k5}, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +00000000000004FC 62b2450d5354db10 VPDPWSSDS xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000504 62b2450d5354dbf0 VPDPWSSDS xmm2{k5}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000050C 62f2458853d0 VPDPWSSDS xmm2, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000512 62f245885313 VPDPWSSDS xmm2, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000518 62f245985313 VPDPWSSDS xmm2, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +000000000000051E 62b245885354db10 VPDPWSSDS xmm2, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000526 62b245885354dbf0 VPDPWSSDS xmm2, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +000000000000052E 62f2458d53d0 VPDPWSSDS xmm2{k5}{z}, xmm7, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000534 62f2458d5313 VPDPWSSDS xmm2{k5}{z}, xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000053A 62f2459d5313 VPDPWSSDS xmm2{k5}{z}, xmm7, dword ptr [rbx]{1to4} + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 4 times + +0000000000000540 62b2458d5354db10 VPDPWSSDS xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, + +0000000000000548 62b2458d5354dbf0 VPDPWSSDS xmm2{k5}{z}, xmm7, xmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff0, + +0000000000000550 62c2152853c7 VPDPWSSDS ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000556 62e215285303 VPDPWSSDS ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000055C 62e215385303 VPDPWSSDS ymm16, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +0000000000000562 62a215285344db08 VPDPWSSDS ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000056A 62a215285344dbf8 VPDPWSSDS ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000572 62c2152d53c7 VPDPWSSDS ymm16{k5}, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +0000000000000578 62e2152d5303 VPDPWSSDS ymm16{k5}, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000057E 62e2153d5303 VPDPWSSDS ymm16{k5}, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +0000000000000584 62a2152d5344db08 VPDPWSSDS ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +000000000000058C 62a2152d5344dbf8 VPDPWSSDS ymm16{k5}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +0000000000000594 62c215a853c7 VPDPWSSDS ymm16, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +000000000000059A 62e215a85303 VPDPWSSDS ymm16, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000005A0 62e215b85303 VPDPWSSDS ymm16, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +00000000000005A6 62a215a85344db08 VPDPWSSDS ymm16, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000005AE 62a215a85344dbf8 VPDPWSSDS ymm16, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000005B6 62c215ad53c7 VPDPWSSDS ymm16{k5}{z}, ymm13, ymm15 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + +00000000000005BC 62e215ad5303 VPDPWSSDS ymm16{k5}{z}, ymm13, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000005C2 62e215bd5303 VPDPWSSDS ymm16{k5}{z}, ymm13, dword ptr [rbx]{1to8} + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 8 times + +00000000000005C8 62a215ad5344db08 VPDPWSSDS ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, + +00000000000005D0 62a215ad5344dbf8 VPDPWSSDS ymm16{k5}{z}, ymm13, ymmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 16, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffff8, + +00000000000005D8 62023d4053c7 VPDPWSSDS zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +00000000000005DE 62623d405303 VPDPWSSDS zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000005E4 62623d505303 VPDPWSSDS zmm24, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +00000000000005EA 62223d405344db04 VPDPWSSDS zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +00000000000005F2 62223d405344dbfc VPDPWSSDS zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +00000000000005FA 62023d4553c7 VPDPWSSDS zmm24{k5}, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000600 62623d455303 VPDPWSSDS zmm24{k5}, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000606 62623d555303 VPDPWSSDS zmm24{k5}, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +000000000000060C 62223d455344db04 VPDPWSSDS zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000614 62223d455344dbfc VPDPWSSDS zmm24{k5}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000061C 62023dc053c7 VPDPWSSDS zmm24, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000622 62623dc05303 VPDPWSSDS zmm24, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +0000000000000628 62623dd05303 VPDPWSSDS zmm24, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +000000000000062E 62223dc05344db04 VPDPWSSDS zmm24, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000636 62223dc05344dbfc VPDPWSSDS zmm24, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + +000000000000063E 62023dc553c7 VPDPWSSDS zmm24{k5}{z}, zmm24, zmm31 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + +0000000000000644 62623dc55303 VPDPWSSDS zmm24{k5}{z}, zmm24, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +000000000000064A 62623dd55303 VPDPWSSDS zmm24{k5}{z}, zmm24, dword ptr [rbx]{1to16} + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Broadcast: yes, + Segment: 3, Base: 3, + Decorator: Broadcast 4 bytes element 16 times + +0000000000000650 62223dc55344db04 VPDPWSSDS zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8+0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, + +0000000000000658 62223dc55344dbfc VPDPWSSDS zmm24{k5}{z}, zmm24, zmmword ptr [rbx+r11*8-0x100] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: AVX512VNNI, Ins cat: VNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 11 + EVEX Tuple Type: Full + Exception class: EVEX, exception type: E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Decorator: Mask k5 + Decorator: Zero (no merging) + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 24, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, + Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, + diff --git a/bddisasm_test/basic/address_16 b/bddisasm_test/basic/address_16 new file mode 100644 index 0000000000000000000000000000000000000000..b7f1d68fc634cee6481cefe90c6a57878dd582a9 GIT binary patch literal 71 zcmeBnV_5jVzT3UNyB$a|cQd7TGp2X5SOW3R^lq1(_37O$KmY&#U%&AG|CEIW3@Jc) SAZD=y5tTrqrIJB_fdK%hU>^$r literal 0 HcmV?d00001 diff --git a/bddisasm_test/basic/address_16.asm b/bddisasm_test/basic/address_16.asm new file mode 100644 index 0000000..245d7fe --- /dev/null +++ b/bddisasm_test/basic/address_16.asm @@ -0,0 +1,31 @@ + bits 16 + + ; + ; 16 bit addressing + ; + mov ax, word [bp] + mov ax, word [0x7FFF] + mov ax, word [bx + 0x7F] + mov ax, word [bx + 0x7FFF] + mov ax, word [bp + di] + mov ax, word [bp + si] + + ; + ; 32 bit addressing + ; + mov ax, word [ecx] + mov ax, word [ecx + edi] + mov ax, word [ecx + edi * 4] + mov ax, word [ecx + edi * 4 + 0x7f] + mov ax, word [ecx + edi * 8 + 0x7fffffff] + mov ax, word [0x7fffffff] + + + ; + ; Segment prefix. + ; + mov ax, word [fs:0x30] + mov ax, word [fs:ecx] + mov ax, word [fs:ecx + edi] + mov ax, word [fs:ecx + edi * 2] + mov ax, word [fs:ecx + edi * 2 + 0x1000] \ No newline at end of file diff --git a/bddisasm_test/basic/address_16.result b/bddisasm_test/basic/address_16.result new file mode 100644 index 0000000..115c79c --- /dev/null +++ b/bddisasm_test/basic/address_16.result @@ -0,0 +1,255 @@ +0000000000000000 8b4600 MOV ax, word ptr [bp+0x0] + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 2, Base: 5, Displacement: 0x0000000000000000, + +0000000000000003 a1ff7f MOV ax, word ptr [0x7fff] + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: D, + Segment: 3, Displacement: 0x0000000000007fff, + +0000000000000006 8b477f MOV ax, word ptr [bx+0x7f] + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, Displacement: 0x000000000000007f, + +0000000000000009 8b87ff7f MOV ax, word ptr [bx+0x7fff] + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, Displacement: 0x0000000000007fff, + +000000000000000D 8b03 MOV ax, word ptr [bp+di] + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 2, Base: 5, Index: 7 * 1, + +000000000000000F 8b02 MOV ax, word ptr [bp+si] + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 2, Base: 5, Index: 6 * 1, + +0000000000000011 678b01 MOV ax, word ptr [ecx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 1, + +0000000000000014 678b0439 MOV ax, word ptr [ecx+edi] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 1, Index: 7 * 1, + +0000000000000018 678b04b9 MOV ax, word ptr [ecx+edi*4] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 1, Index: 7 * 4, + +000000000000001C 678b44b97f MOV ax, word ptr [ecx+edi*4+0x7f] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 1, Index: 7 * 4, Displacement: 0x000000000000007f, + +0000000000000021 678b84f9ffffff7f MOV ax, word ptr [ecx+edi*8+0x7fffffff] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 1, Index: 7 * 8, Displacement: 0x000000007fffffff, + +0000000000000029 a1ffff MOV ax, word ptr [0xffff] + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: D, + Segment: 3, Displacement: 0x000000000000ffff, + +000000000000002C 64a13000 MOV ax, word ptr fs:[0x30] + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: D, + Segment: 4, Displacement: 0x0000000000000030, + +0000000000000030 64678b01 MOV ax, word ptr fs:[ecx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 4, Base: 1, + +0000000000000034 64678b0439 MOV ax, word ptr fs:[ecx+edi] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 4, Base: 1, Index: 7 * 1, + +0000000000000039 64678b0479 MOV ax, word ptr fs:[ecx+edi*2] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 4, Base: 1, Index: 7 * 2, + +000000000000003E 64678b847900100000 MOV ax, word ptr fs:[ecx+edi*2+0x1000] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 4, Base: 1, Index: 7 * 2, Displacement: 0x0000000000001000, + diff --git a/bddisasm_test/basic/address_32 b/bddisasm_test/basic/address_32 new file mode 100644 index 0000000000000000000000000000000000000000..8a73acd7ba27270139043e861c52438b1b8ba214 GIT binary patch literal 73 zcmeBX>}Ij-X4%>8va`Os<>&wZ|LYfmi1cnZhK2v@85q*L-GQ8TkO*^nH&e<&0|o|$ Vly1fppgth3OzCc^WDsCr000~^9_;`C literal 0 HcmV?d00001 diff --git a/bddisasm_test/basic/address_32.asm b/bddisasm_test/basic/address_32.asm new file mode 100644 index 0000000..2ad6e29 --- /dev/null +++ b/bddisasm_test/basic/address_32.asm @@ -0,0 +1,32 @@ + bits 32 + + ; + ; 32 bit addressing + ; + mov eax, dword [ecx] + mov eax, dword [ecx + edi] + mov eax, dword [ecx + edi * 4] + mov eax, dword [ecx + edi * 4 + 0x7f] + mov eax, dword [ecx + edi * 8 + 0x7fffffff] + mov eax, dword [0x7fffffff] + + + ; + ; 16 bit addressing + ; + mov eax, dword [bp] + mov eax, dword [0x7FFF] + mov eax, dword [bx + 0x7F] + mov eax, dword [bx + 0x7FFF] + mov eax, dword [bp + di] + mov eax, dword [bp + si] + + + ; + ; Segment prefix. + ; + mov eax, dword [fs:0x30] + mov eax, dword [fs:ecx] + mov eax, dword [fs:ecx + edi] + mov eax, dword [fs:ecx + edi * 2] + mov eax, dword [fs:ecx + edi * 2 + 0x1000] \ No newline at end of file diff --git a/bddisasm_test/basic/address_32.result b/bddisasm_test/basic/address_32.result new file mode 100644 index 0000000..9a1e862 --- /dev/null +++ b/bddisasm_test/basic/address_32.result @@ -0,0 +1,255 @@ +0000000000000000 8b01 MOV eax, dword ptr [ecx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 1, + +0000000000000002 8b0439 MOV eax, dword ptr [ecx+edi] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 1, Index: 7 * 1, + +0000000000000005 8b04b9 MOV eax, dword ptr [ecx+edi*4] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 1, Index: 7 * 4, + +0000000000000008 8b44b97f MOV eax, dword ptr [ecx+edi*4+0x7f] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 1, Index: 7 * 4, Displacement: 0x000000000000007f, + +000000000000000C 8b84f9ffffff7f MOV eax, dword ptr [ecx+edi*8+0x7fffffff] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 1, Index: 7 * 8, Displacement: 0x000000007fffffff, + +0000000000000013 a1ffffff7f MOV eax, dword ptr [0x7fffffff] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: D, + Segment: 3, Displacement: 0x000000007fffffff, + +0000000000000018 678b4600 MOV eax, dword ptr [bp+0x0] + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 2, Base: 5, Displacement: 0x0000000000000000, + +000000000000001C a1ff7f0000 MOV eax, dword ptr [0x7fff] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: D, + Segment: 3, Displacement: 0x0000000000007fff, + +0000000000000021 678b477f MOV eax, dword ptr [bx+0x7f] + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Displacement: 0x000000000000007f, + +0000000000000025 678b87ff7f MOV eax, dword ptr [bx+0x7fff] + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Displacement: 0x0000000000007fff, + +000000000000002A 678b03 MOV eax, dword ptr [bp+di] + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 2, Base: 5, Index: 7 * 1, + +000000000000002D 678b02 MOV eax, dword ptr [bp+si] + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 2, Base: 5, Index: 6 * 1, + +0000000000000030 64a130000000 MOV eax, dword ptr fs:[0x30] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: D, + Segment: 4, Displacement: 0x0000000000000030, + +0000000000000036 648b01 MOV eax, dword ptr fs:[ecx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 4, Base: 1, + +0000000000000039 648b0439 MOV eax, dword ptr fs:[ecx+edi] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 4, Base: 1, Index: 7 * 1, + +000000000000003D 648b0479 MOV eax, dword ptr fs:[ecx+edi*2] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 4, Base: 1, Index: 7 * 2, + +0000000000000041 648b847900100000 MOV eax, dword ptr fs:[ecx+edi*2+0x1000] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 4, Base: 1, Index: 7 * 2, Displacement: 0x0000000000001000, + diff --git a/bddisasm_test/basic/address_64 b/bddisasm_test/basic/address_64 new file mode 100644 index 0000000000000000000000000000000000000000..077f77772f024fe0541dcf7dfbc40638a4062823 GIT binary patch literal 195 zcmXwyF%H5&3q&_K literal 0 HcmV?d00001 diff --git a/bddisasm_test/basic/address_64.asm b/bddisasm_test/basic/address_64.asm new file mode 100644 index 0000000..147db54 --- /dev/null +++ b/bddisasm_test/basic/address_64.asm @@ -0,0 +1,81 @@ + bits 64 + + ; + ; 64 bit addressing + ; + + ; Basic indirect addressing, using register. + mov eax, dword [rcx] + mov rax, qword [r15] + + ; Base + offset 1B + mov eax, dword [rcx + 0x7F] + mov rax, qword [r15 - 0x7F] + + ; Base + offset 4B + mov eax, dword [rcx + 0x7FFFFFFF] + mov rax, qword [r15 - 0x7FFFFFFF] + + ; Base + index + mov eax, dword [rcx + r8] + mov rax, qword [r15 + rdi] + + ; Base + index * scale + mov eax, dword [rcx + r8 * 4] + mov rax, qword [r15 + rdi * 8] + + ; Base + index * scale + displacement + mov eax, dword [rcx + r8 * 4 + 0x1000] + mov rax, qword [r15 + rdi * 8 - 0x1000] + + ; RIP-relative + mov eax, dword [rel $] + mov rax, qword [rel $] + + ; RSP only + mov eax, dword [rsp] + mov rax, qword [rsp + 0x1000] + + + + ; + ; 32 bit addressing + ; + + ; Basic indirect addressing, using register. + mov eax, dword [ecx] + mov rax, qword [r15d] + + ; Base + offset 1B + mov eax, dword [ecx + 0x7F] + mov rax, qword [r15d - 0x7F] + + ; Base + offset 4B + mov eax, dword [ecx + 0x7FFFFFFF] + mov rax, qword [r15d - 0x7FFFFFFF] + + ; Base + index + mov eax, dword [ecx + r8d] + mov rax, qword [r15d + edi] + + ; Base + index * scale + mov eax, dword [ecx + r8d * 4] + mov rax, qword [r15d + edi * 8] + + ; Base + index * scale + displacement + mov eax, dword [ecx + r8d * 4 + 0x1000] + mov rax, qword [r15d + edi * 8 - 0x1000] + + ; ESP only + mov eax, dword [esp] + mov rax, qword [esp + 0x1000] + + + ; + ; Segment prefix. + ; + mov rax, qword [gs:0x30] + mov rax, qword [gs:rcx] + mov rax, qword [gs:rcx + r15] + mov rax, qword [gs:rcx + r15 * 2] + mov rax, qword [gs:rcx + r15 * 2 + 0x1000] \ No newline at end of file diff --git a/bddisasm_test/basic/address_64.result b/bddisasm_test/basic/address_64.result new file mode 100644 index 0000000..93b135e --- /dev/null +++ b/bddisasm_test/basic/address_64.result @@ -0,0 +1,525 @@ +0000000000000000 8b01 MOV eax, dword ptr [rcx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 1, + +0000000000000002 498b07 MOV rax, qword ptr [r15] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 15, + +0000000000000005 8b417f MOV eax, dword ptr [rcx+0x7f] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 1, Displacement: 0x000000000000007f, + +0000000000000008 498b4781 MOV rax, qword ptr [r15-0x7f] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 15, Displacement: 0xffffffffffffff81, + +000000000000000C 8b81ffffff7f MOV eax, dword ptr [rcx+0x7fffffff] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 1, Displacement: 0x000000007fffffff, + +0000000000000012 498b8701000080 MOV rax, qword ptr [r15-0x7fffffff] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 15, Displacement: 0xffffffff80000001, + +0000000000000019 428b0401 MOV eax, dword ptr [rcx+r8] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 1, Index: 8 * 1, + +000000000000001D 498b043f MOV rax, qword ptr [r15+rdi] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 15, Index: 7 * 1, + +0000000000000021 428b0481 MOV eax, dword ptr [rcx+r8*4] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 1, Index: 8 * 4, + +0000000000000025 498b04ff MOV rax, qword ptr [r15+rdi*8] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 15, Index: 7 * 8, + +0000000000000029 428b848100100000 MOV eax, dword ptr [rcx+r8*4+0x1000] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 1, Index: 8 * 4, Displacement: 0x0000000000001000, + +0000000000000031 498b84ff00f0ffff MOV rax, qword ptr [r15+rdi*8-0x1000] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 15, Index: 7 * 8, Displacement: 0xfffffffffffff000, + +0000000000000039 8b05faffffff MOV eax, dword ptr [rel 0x39] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, RIP relative: yes, + Segment: 3, Displacement: 0xfffffffffffffffa, + +000000000000003F 488b05f9ffffff MOV rax, qword ptr [rel 0x3f] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, RIP relative: yes, + Segment: 3, Displacement: 0xfffffffffffffff9, + +0000000000000046 8b0424 MOV eax, dword ptr [rsp] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 2, Base: 4, + +0000000000000049 488b842400100000 MOV rax, qword ptr [rsp+0x1000] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 2, Base: 4, Displacement: 0x0000000000001000, + +0000000000000051 678b01 MOV eax, dword ptr [ecx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 1, + +0000000000000054 67498b07 MOV rax, qword ptr [r15d] + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 15, + +0000000000000058 678b417f MOV eax, dword ptr [ecx+0x7f] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 1, Displacement: 0x000000000000007f, + +000000000000005C 67498b4781 MOV rax, qword ptr [r15d-0x7f] + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 15, Displacement: 0xffffffffffffff81, + +0000000000000061 678b81ffffff7f MOV eax, dword ptr [ecx+0x7fffffff] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 1, Displacement: 0x000000007fffffff, + +0000000000000068 67498b8701000080 MOV rax, qword ptr [r15d-0x7fffffff] + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 15, Displacement: 0xffffffff80000001, + +0000000000000070 67428b0401 MOV eax, dword ptr [ecx+r8d] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 1, Index: 8 * 1, + +0000000000000075 67498b043f MOV rax, qword ptr [r15d+edi] + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 15, Index: 7 * 1, + +000000000000007A 67428b0481 MOV eax, dword ptr [ecx+r8d*4] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 1, Index: 8 * 4, + +000000000000007F 67498b04ff MOV rax, qword ptr [r15d+edi*8] + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 15, Index: 7 * 8, + +0000000000000084 67428b848100100000 MOV eax, dword ptr [ecx+r8d*4+0x1000] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 1, Index: 8 * 4, Displacement: 0x0000000000001000, + +000000000000008D 67498b84ff00f0ffff MOV rax, qword ptr [r15d+edi*8-0x1000] + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 15, Index: 7 * 8, Displacement: 0xfffffffffffff000, + +0000000000000096 678b0424 MOV eax, dword ptr [esp] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 2, Base: 4, + +000000000000009A 67488b842400100000 MOV rax, qword ptr [esp+0x1000] + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 2, Base: 4, Displacement: 0x0000000000001000, + +00000000000000A3 65488b042530000000 MOV rax, qword ptr gs:[0x30] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 5, Displacement: 0x0000000000000030, + +00000000000000AC 65488b01 MOV rax, qword ptr gs:[rcx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 5, Base: 1, + +00000000000000B0 654a8b0439 MOV rax, qword ptr gs:[rcx+r15] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 5, Base: 1, Index: 15 * 1, + +00000000000000B5 654a8b0479 MOV rax, qword ptr gs:[rcx+r15*2] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 5, Base: 1, Index: 15 * 2, + +00000000000000BA 654a8b847900100000 MOV rax, qword ptr gs:[rcx+r15*2+0x1000] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 5, Base: 1, Index: 15 * 2, Displacement: 0x0000000000001000, + diff --git a/bddisasm_test/basic/aes_64 b/bddisasm_test/basic/aes_64 new file mode 100644 index 0000000..621bb0d --- /dev/null +++ b/bddisasm_test/basic/aes_64 @@ -0,0 +1,5 @@ +fA8fA8fA8fA8fA8fA: +f8;f8;f8;f8;f8;f:; +yy +y;;;;;y; +;;;;b@b@b@b@b@;b@;b@;b@; \ No newline at end of file diff --git a/bddisasm_test/basic/aes_64.asm b/bddisasm_test/basic/aes_64.asm new file mode 100644 index 0000000..d45e8b1 --- /dev/null +++ b/bddisasm_test/basic/aes_64.asm @@ -0,0 +1,57 @@ + bits 64 + + ; legacy, reg - reg + aesimc xmm7, xmm13 + aesenc xmm7, xmm13 + aesenclast xmm7, xmm13 + aesdec xmm7, xmm13 + aesdeclast xmm7, xmm13 + aeskeygenassist xmm7, xmm13, 10 + + ; legacy, reg - mem + aesimc xmm7, [rbx] + aesenc xmm7, [rbx] + aesenclast xmm7, [rbx] + aesdec xmm7, [rbx] + aesdeclast xmm7, [rbx] + aeskeygenassist xmm7, [rbx], 10 + + ; VEX, reg - reg - reg, 128 bit + vaesimc xmm7, xmm13 + vaesenc xmm7, xmm15, xmm13 + vaesenclast xmm7, xmm15, xmm13 + vaesdec xmm7, xmm15, xmm13 + vaesdeclast xmm7, xmm15, xmm13 + vaeskeygenassist xmm7, xmm13, 10 + + ; VEX, reg - reg - mem, 128 bit + vaesimc xmm7, [rbx] + vaesenc xmm7, xmm15, [rbx] + vaesenclast xmm7, xmm15, [rbx] + vaesdec xmm7, xmm15, [rbx] + vaesdeclast xmm7, xmm15, [rbx] + vaeskeygenassist xmm7, [rbx], 10 + + ; VEX, reg - reg - reg, 256 bit + vaesenc ymm7, ymm15, ymm13 + vaesenclast ymm7, ymm15, ymm13 + vaesdec ymm7, ymm15, ymm13 + vaesdeclast ymm7, ymm15, ymm13 + + ; VEX reg - reg - mem, 256 bit + vaesenc ymm7, ymm15, [rbx] + vaesenclast ymm7, ymm15, [rbx] + vaesdec ymm7, ymm15, [rbx] + vaesdeclast ymm7, ymm15, [rbx] + + ; EVEX, reg - reg - reg, 512 bit + vaesenc zmm7, zmm31, zmm13 + vaesenclast zmm7, zmm31, zmm13 + vaesdec zmm7, zmm31, zmm13 + vaesdeclast zmm7, zmm31, zmm13 + + ; EVEX reg - reg - mem, 512 bit + vaesenc zmm7, zmm31, [rbx] + vaesenclast zmm7, zmm31, [rbx] + vaesdec zmm7, zmm31, [rbx] + vaesdeclast zmm7, zmm31, [rbx] \ No newline at end of file diff --git a/bddisasm_test/basic/aes_64.result b/bddisasm_test/basic/aes_64.result new file mode 100644 index 0000000..89100ff --- /dev/null +++ b/bddisasm_test/basic/aes_64.result @@ -0,0 +1,696 @@ +0000000000000000 66410f38dbfd AESIMC xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000006 66410f38dcfd AESENC xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000000C 66410f38ddfd AESENCLAST xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000012 66410f38defd AESDEC xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000018 66410f38dffd AESDECLAST xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000001E 66410f3adffd0a AESKEYGENASSIST xmm7, xmm13, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000025 660f38db3b AESIMC xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000002A 660f38dc3b AESENC xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000002F 660f38dd3b AESENCLAST xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000034 660f38de3b AESDEC xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000039 660f38df3b AESDECLAST xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000003E 660f3adf3b0a AESKEYGENASSIST xmm7, xmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000044 c4c279dbfd VAESIMC xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000049 c4c201dcfd VAESENC xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000004E c4c201ddfd VAESENCLAST xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000053 c4c201defd VAESDEC xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000058 c4c201dffd VAESDECLAST xmm7, xmm15, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000005D c4c379dffd0a VAESKEYGENASSIST xmm7, xmm13, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000063 c4e279db3b VAESIMC xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000068 c4e201dc3b VAESENC xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000006D c4e201dd3b VAESENCLAST xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000072 c4e201de3b VAESDEC xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000077 c4e201df3b VAESDECLAST xmm7, xmm15, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000007C c4e379df3b0a VAESKEYGENASSIST xmm7, xmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000082 c4c205dcfd VAESENC ymm7, ymm15, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +0000000000000087 c4c205ddfd VAESENCLAST ymm7, ymm15, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +000000000000008C c4c205defd VAESDEC ymm7, ymm15, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +0000000000000091 c4c205dffd VAESDECLAST ymm7, ymm15, ymm13 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 13, RegCount: 1 + +0000000000000096 c4e205dc3b VAESENC ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000009B c4e205dd3b VAESENCLAST ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000000A0 c4e205de3b VAESDEC ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000000A5 c4e205df3b VAESDECLAST ymm7, ymm15, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AES, Ins cat: AES, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +00000000000000AA 62d20540dcfd VAESENC zmm7, zmm31, zmm13 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: VAES, Ins cat: VAES, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 9 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 13, RegCount: 1 + +00000000000000B0 62d20540ddfd VAESENCLAST zmm7, zmm31, zmm13 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: VAES, Ins cat: VAES, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 9 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 13, RegCount: 1 + +00000000000000B6 62d20540defd VAESDEC zmm7, zmm31, zmm13 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: VAES, Ins cat: VAES, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 9 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 13, RegCount: 1 + +00000000000000BC 62d20540dffd VAESDECLAST zmm7, zmm31, zmm13 + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: VAES, Ins cat: VAES, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 9 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 13, RegCount: 1 + +00000000000000C2 62f20540dc3b VAESENC zmm7, zmm31, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: VAES, Ins cat: VAES, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 9 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000000C8 62f20540dd3b VAESENCLAST zmm7, zmm31, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: VAES, Ins cat: VAES, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 9 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000000CE 62f20540de3b VAESDEC zmm7, zmm31, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: VAES, Ins cat: VAES, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 9 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + +00000000000000D4 62f20540df3b VAESDECLAST zmm7, zmm31, zmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 512 + ISA Set: VAES, Ins cat: VAES, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 9 + EVEX Tuple Type: Full Mem + Exception class: EVEX, exception type: E4NF + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 31, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 3, + diff --git a/bddisasm_test/basic/basic1_64 b/bddisasm_test/basic/basic1_64 new file mode 100644 index 0000000000000000000000000000000000000000..62ac2512a4e1232d0fc51554aa67c87bca4a4ef1 GIT binary patch literal 1600 zcmX|*Pj4Gl6vfBARB9M1y)aZt7%DXkl^TXh4W?4VP|23MxR(4etUHTR`XNdP+kON7 zr4da_ShBG+v#NKUH?zpw)e9hA02wvXJg+>Qyt=V`&+qu0rz3l&=hYV|^(b}vj*^a% zdpIIVJGdn;da7fP6Lkm~s*9fIDejnI$1o8i22zk+bHns*)Sps%gHorTDcQs_F2?F6 zZpoXT+BC>x+9YJCZo1`7Gu$*B6C(yvkX@rpPu1^Jswj2(fs$1$;{vR%;+DMPsa1nK zpjASK>WW)lHN#cI0Wo4A1=%%grngpqNa-4-PCrtzj%8ek)pgvGS3R|EkcYHR$WUE% z%j;&iZa5@H45T2t=9=kUt3Rgn8l_G@QL=$$T!hsP+>+NlwPBD)v_Z&FU3beHX1HNE zB1R0PAiL(0>0PSdrSuY|PTy0qf@PeK)fL>5mp!#&ko&Yk$WUE&%PVHMV%R4}45T2t z=9cN*sz0an7Nt(VP_l((ToC+d zs3Vp--r1pfgKtT8Xoq-*ejm#p<1xPDF*`kTKb*paGMR<7YmY>TH=-#lm6nRv=cmd*-jwbP6qAE zg)gn&`rP_W(Ql5#7Sgvzwt%oL2KJ~4#0EBC8#Jchyb^2h;FUEHwq{^oHKEwhhHS&8 z?l)F!jR)4&5VrNe+NLYEYrAZ_&9vVfi=E=Zv7JKLP6zh5iNr=WVjDH{e$$Gb<3VfZ z5VrGyZJR`FViUGWGwU}eVrO`8VrLMxvw=NnVzIG}*~UedWur1Hs3g&u0$*7zZe(8&zNIt=hYoDB4JF@XCk|B@f|39fDQJI%F8G!eW|DN9DAL z%1HE7@+n?TMMsiHaFLF{DqWm2dM5b{uV$iS$z!-!$6yt+jv0ol zxR_`2Q8_P?G7&wOe2!Oh(TU^e=QFld?ODZ{;A|I^^g4fw~}M^pPbbEXxCGo*Lht(@;ayZ b`E23UZF}Lg_x;{kar*T1*=spG<^BHwhBuRB literal 0 HcmV?d00001 diff --git a/bddisasm_test/basic/basic1_64.asm b/bddisasm_test/basic/basic1_64.asm new file mode 100644 index 0000000..215b097 --- /dev/null +++ b/bddisasm_test/basic/basic1_64.asm @@ -0,0 +1,562 @@ + bits 64 + + ; Arithemtic. + add al, bl + add al, sil + add al, [rbx] + add [ebx], al + add al, [ebx] + add [ebx], al + add al, 0x10 + add ax, bx + add ax, r11w + add ax, [rbx] + add [ebx], ax + add ax, [ebx] + add [ebx], ax + add ax, 0x1000 + add eax, ebx + add eax, r11d + add eax, [rbx] + add [rbx], eax + add eax, [ebx] + add [ebx], eax + add eax, 0x10000000 + add rax, rbx + add rax, r11 + add rax, [rbx] + add [rbx], rax + add rax, [ebx] + add [ebx], rax + add rax, 0x10000000 + + sub al, bl + sub al, sil + sub al, [rbx] + sub [ebx], al + sub al, [ebx] + sub [ebx], al + sub al, 0x10 + sub ax, bx + sub ax, r11w + sub ax, [rbx] + sub [ebx], ax + sub ax, [ebx] + sub [ebx], ax + sub ax, 0x1000 + sub eax, ebx + sub eax, r11d + sub eax, [rbx] + sub [rbx], eax + sub eax, [ebx] + sub [ebx], eax + sub eax, 0x10000000 + sub rax, rbx + sub rax, r11 + sub rax, [rbx] + sub [rbx], rax + sub rax, [ebx] + sub [ebx], rax + sub rax, 0x10000000 + + adc al, bl + adc al, sil + adc al, [rbx] + adc [ebx], al + adc al, [ebx] + adc [ebx], al + adc al, 0x10 + adc ax, bx + adc ax, r11w + adc ax, [rbx] + adc [ebx], ax + adc ax, [ebx] + adc [ebx], ax + adc ax, 0x1000 + adc eax, ebx + adc eax, r11d + adc eax, [rbx] + adc [rbx], eax + adc eax, [ebx] + adc [ebx], eax + adc eax, 0x10000000 + adc rax, rbx + adc rax, r11 + adc rax, [rbx] + adc [rbx], rax + adc rax, [ebx] + adc [ebx], rax + adc rax, 0x10000000 + + sbb al, bl + sbb al, sil + sbb al, [rbx] + sbb [ebx], al + sbb al, [ebx] + sbb [ebx], al + sbb al, 0x10 + sbb ax, bx + sbb ax, r11w + sbb ax, [rbx] + sbb [ebx], ax + sbb ax, [ebx] + sbb [ebx], ax + sbb ax, 0x1000 + sbb eax, ebx + sbb eax, r11d + sbb eax, [rbx] + sbb [rbx], eax + sbb eax, [ebx] + sbb [ebx], eax + sbb eax, 0x10000000 + sbb rax, rbx + sbb rax, r11 + sbb rax, [rbx] + sbb [rbx], rax + sbb rax, [ebx] + sbb [ebx], rax + sbb rax, 0x10000000 + + and al, bl + and al, sil + and al, [rbx] + and [ebx], al + and al, [ebx] + and [ebx], al + and al, 0x10 + and ax, bx + and ax, r11w + and ax, [rbx] + and [ebx], ax + and ax, [ebx] + and [ebx], ax + and ax, 0x1000 + and eax, ebx + and eax, r11d + and eax, [rbx] + and [rbx], eax + and eax, [ebx] + and [ebx], eax + and eax, 0x10000000 + and rax, rbx + and rax, r11 + and rax, [rbx] + and [rbx], rax + and rax, [ebx] + and [ebx], rax + and rax, 0x10000000 + + or al, bl + or al, sil + or al, [rbx] + or [ebx], al + or al, [ebx] + or [ebx], al + or al, 0x10 + or ax, bx + or ax, r11w + or ax, [rbx] + or [ebx], ax + or ax, [ebx] + or [ebx], ax + or ax, 0x1000 + or eax, ebx + or eax, r11d + or eax, [rbx] + or [rbx], eax + or eax, [ebx] + or [ebx], eax + or eax, 0x10000000 + or rax, rbx + or rax, r11 + or rax, [rbx] + or [rbx], rax + or rax, [ebx] + or [ebx], rax + or rax, 0x10000000 + + xor al, bl + xor al, sil + xor al, [rbx] + xor [ebx], al + xor al, [ebx] + xor [ebx], al + xor al, 0x10 + xor ax, bx + xor ax, r11w + xor ax, [rbx] + xor [ebx], ax + xor ax, [ebx] + xor [ebx], ax + xor ax, 0x1000 + xor eax, ebx + xor eax, r11d + xor eax, [rbx] + xor [rbx], eax + xor eax, [ebx] + xor [ebx], eax + xor eax, 0x10000000 + xor rax, rbx + xor rax, r11 + xor rax, [rbx] + xor [rbx], rax + xor rax, [ebx] + xor [ebx], rax + xor rax, 0x10000000 + + cmp al, bl + cmp al, sil + cmp al, [rbx] + cmp [ebx], al + cmp al, [ebx] + cmp [ebx], al + cmp al, 0x10 + cmp ax, bx + cmp ax, r11w + cmp ax, [rbx] + cmp [ebx], ax + cmp ax, [ebx] + cmp [ebx], ax + cmp ax, 0x1000 + cmp eax, ebx + cmp eax, r11d + cmp eax, [rbx] + cmp [rbx], eax + cmp eax, [ebx] + cmp [ebx], eax + cmp eax, 0x10000000 + cmp rax, rbx + cmp rax, r11 + cmp rax, [rbx] + cmp [rbx], rax + cmp rax, [ebx] + cmp [ebx], rax + cmp rax, 0x10000000 + + test eax, 1 + test rax, 1 + test eax, r14d + test rax, r14 + test byte [rbx], 1 + test word [rbx], 1 + test dword [rbx], 1 + test qword [rbx], 1 + test byte [rbx], al + test word [rbx], ax + test dword [rbx], eax + test qword [rbx], rax + + + ; Data transfer. + mov al, byte 0xBD + mov ax, word 0xBDBD + mov eax, dword 0xBDBDBDBD + mov rax, qword 0xBDBDBDBDBDBDBDBD + mov al, [qword 0xBDBDBDBDBDBDBDBD] + mov ax, [qword 0xBDBDBDBDBDBDBDBD] + mov eax, [qword 0xBDBDBDBDBDBDBDBD] + mov rax, [qword 0xBDBDBDBDBDBDBDBD] + mov [qword 0xBDBDBDBDBDBDBDBD], al + mov [qword 0xBDBDBDBDBDBDBDBD], ax + mov [qword 0xBDBDBDBDBDBDBDBD], eax + mov [qword 0xBDBDBDBDBDBDBDBD], rax + + xlatb + xchg al, cl + xchg ax, cx + xchg eax, ecx + xchg rax, rcx + xchg rax, [rbx] + xchg rax, [ebx] + + ; Unary opcodes. + inc al + inc r15b + inc ax + inc r15w + inc eax + inc r15d + inc rax + inc r15 + inc byte [rbx] + inc word [rbx] + inc dword [rbx] + inc qword [rbx] + + dec al + dec r15b + dec ax + dec r15w + dec eax + dec r15d + dec rax + dec r15 + dec byte [rbx] + dec word [rbx] + dec dword [rbx] + dec qword [rbx] + + not al + not r15b + not ax + not r15w + not eax + not r15d + not rax + not r15 + not byte [rbx] + not word [rbx] + not dword [rbx] + not qword [rbx] + + neg al + neg r15b + neg ax + neg r15w + neg eax + neg r15d + neg rax + neg r15 + neg byte [rbx] + neg word [rbx] + neg dword [rbx] + neg qword [rbx] + + div al + div r15b + div ax + div r15w + div eax + div r15d + div rax + div r15 + div byte [rbx] + div word [rbx] + div dword [rbx] + div qword [rbx] + + mul al + mul r15b + mul ax + mul r15w + mul eax + mul r15d + mul rax + mul r15 + mul byte [rbx] + mul word [rbx] + mul dword [rbx] + mul qword [rbx] + + idiv al + idiv r15b + idiv ax + idiv r15w + idiv eax + idiv r15d + idiv rax + idiv r15 + idiv byte [rbx] + idiv word [rbx] + idiv dword [rbx] + idiv qword [rbx] + + imul al + imul r15b + imul ax + imul r15w + imul eax + imul r15d + imul rax + imul r15 + imul byte [rbx] + imul word [rbx] + imul dword [rbx] + imul qword [rbx] + + ; Shift/rotate + rol al, 1 + rol al, 100 + rol al, cl + rol byte [rbx], 1 + rol byte [rbx], cl + rol ax, 1 + rol ax, 100 + rol ax, cl + rol word [rbx], 1 + rol word [rbx], 100 + rol word [rbx], cl + rol dword [rbx], 1 + rol dword [rbx], 100 + rol dword [rbx], cl + rol qword [rbx], 1 + rol qword [rbx], 100 + rol qword [rbx], cl + + ror al, 1 + ror al, 100 + ror al, cl + ror byte [rbx], 1 + ror byte [rbx], cl + ror ax, 1 + ror ax, 100 + ror ax, cl + ror word [rbx], 1 + ror word [rbx], 100 + ror word [rbx], cl + ror dword [rbx], 1 + ror dword [rbx], 100 + ror dword [rbx], cl + ror qword [rbx], 1 + ror qword [rbx], 100 + ror qword [rbx], cl + + rcl al, 1 + rcl al, 100 + rcl al, cl + rcl byte [rbx], 1 + rcl byte [rbx], cl + rcl ax, 1 + rcl ax, 100 + rcl ax, cl + rcl word [rbx], 1 + rcl word [rbx], 100 + rcl word [rbx], cl + rcl dword [rbx], 1 + rcl dword [rbx], 100 + rcl dword [rbx], cl + rcl qword [rbx], 1 + rcl qword [rbx], 100 + rcl qword [rbx], cl + + rcr al, 1 + rcr al, 100 + rcr al, cl + rcr byte [rbx], 1 + rcr byte [rbx], cl + rcr ax, 1 + rcr ax, 100 + rcr ax, cl + rcr word [rbx], 1 + rcr word [rbx], 100 + rcr word [rbx], cl + rcr dword [rbx], 1 + rcr dword [rbx], 100 + rcr dword [rbx], cl + rcr qword [rbx], 1 + rcr qword [rbx], 100 + rcr qword [rbx], cl + + shl al, 1 + shl al, 100 + shl al, cl + shl byte [rbx], 1 + shl byte [rbx], cl + shl ax, 1 + shl ax, 100 + shl ax, cl + shl word [rbx], 1 + shl word [rbx], 100 + shl word [rbx], cl + shl dword [rbx], 1 + shl dword [rbx], 100 + shl dword [rbx], cl + shl qword [rbx], 1 + shl qword [rbx], 100 + shl qword [rbx], cl + + shr al, 1 + shr al, 100 + shr al, cl + shr byte [rbx], 1 + shr byte [rbx], cl + shr ax, 1 + shr ax, 100 + shr ax, cl + shr word [rbx], 1 + shr word [rbx], 100 + shr word [rbx], cl + shr dword [rbx], 1 + shr dword [rbx], 100 + shr dword [rbx], cl + shr qword [rbx], 1 + shr qword [rbx], 100 + shr qword [rbx], cl + + sar al, 1 + sar al, 100 + sar al, cl + sar byte [rbx], 1 + sar byte [rbx], cl + sar ax, 1 + sar ax, 100 + sar ax, cl + sar word [rbx], 1 + sar word [rbx], 100 + sar word [rbx], cl + sar dword [rbx], 1 + sar dword [rbx], 100 + sar dword [rbx], cl + sar qword [rbx], 1 + sar qword [rbx], 100 + sar qword [rbx], cl + + ; imul with 3 operands + imul ax, cx, 100 + imul ax, [rbx], 100 + imul eax, ecx, 100 + imul eax, [rbx], 100 + imul rax, rcx, 100 + imul rax, [rbx], 100 + + ; String + movsb + movsw + movsd + movsq + stosb + stosw + stosd + stosq + lodsb + lodsw + lodsd + lodsq + scasb + scasw + scasd + scasq + cmpsb + cmpsb + cmpsw + cmpsd + cmpsq + + ; I/O + insb + insw + insd + outsb + outsw + outsd + + in al, 0x10 + in ax, 0x10 + in al, dx + in ax, dx + out 0x10, al + out 0x10, ax + out dx, al + out dx, ax + + + ; Prefixes. + lock add qword [rdi + 0x1000], 1 + lock xacquire add dword [rax], 1 + lock xrelease sub qword [rsi + rdi * 8 - 0x1000], 2 + xrelease mov byte [rbp + 0x1000], spl + + rep stosb + rep lodsb + repnz scasw + repz cmpsq \ No newline at end of file diff --git a/bddisasm_test/basic/basic1_64.result b/bddisasm_test/basic/basic1_64.result new file mode 100644 index 0000000..367f572 --- /dev/null +++ b/bddisasm_test/basic/basic1_64.result @@ -0,0 +1,9088 @@ +0000000000000000 00d8 ADD al, bl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 3, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000002 4000f0 ADD al, sil + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 6, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000005 0203 ADD al, byte ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000007 670003 ADD byte ptr [ebx], al + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000000A 670203 ADD al, byte ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000000D 670003 ADD byte ptr [ebx], al + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000010 0410 ADD al, 0x10 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000012 6601d8 ADD ax, bx + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 3, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000015 664401d8 ADD ax, r11w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 11, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000019 660303 ADD ax, word ptr [rbx] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000001C 66670103 ADD word ptr [ebx], ax + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000020 66670303 ADD ax, word ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000024 66670103 ADD word ptr [ebx], ax + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000028 66050010 ADD ax, 0x1000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000002C 01d8 ADD eax, ebx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000002E 4401d8 ADD eax, r11d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 11, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000031 0303 ADD eax, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000033 0103 ADD dword ptr [rbx], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000035 670303 ADD eax, dword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000038 670103 ADD dword ptr [ebx], eax + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000003B 0500000010 ADD eax, 0x10000000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000040 4801d8 ADD rax, rbx + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000043 4c01d8 ADD rax, r11 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 11, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000046 480303 ADD rax, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000049 480103 ADD qword ptr [rbx], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000004C 67480303 ADD rax, qword ptr [ebx] + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000050 67480103 ADD qword ptr [ebx], rax + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000054 480500000010 ADD rax, 0x10000000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 8, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000005A 28d8 SUB al, bl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 3, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000005C 4028f0 SUB al, sil + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 6, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000005F 2a03 SUB al, byte ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000061 672803 SUB byte ptr [ebx], al + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000064 672a03 SUB al, byte ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000067 672803 SUB byte ptr [ebx], al + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000006A 2c10 SUB al, 0x10 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000006C 6629d8 SUB ax, bx + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 3, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000006F 664429d8 SUB ax, r11w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 11, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000073 662b03 SUB ax, word ptr [rbx] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000076 66672903 SUB word ptr [ebx], ax + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000007A 66672b03 SUB ax, word ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000007E 66672903 SUB word ptr [ebx], ax + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000082 662d0010 SUB ax, 0x1000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000086 29d8 SUB eax, ebx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000088 4429d8 SUB eax, r11d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 11, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000008B 2b03 SUB eax, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000008D 2903 SUB dword ptr [rbx], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000008F 672b03 SUB eax, dword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000092 672903 SUB dword ptr [ebx], eax + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000095 2d00000010 SUB eax, 0x10000000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000009A 4829d8 SUB rax, rbx + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000009D 4c29d8 SUB rax, r11 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 11, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000A0 482b03 SUB rax, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000A3 482903 SUB qword ptr [rbx], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000A6 67482b03 SUB rax, qword ptr [ebx] + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000AA 67482903 SUB qword ptr [ebx], rax + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000AE 482d00000010 SUB rax, 0x10000000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 8, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000B4 10d8 ADC al, bl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 3, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000B6 4010f0 ADC al, sil + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 6, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000B9 1203 ADC al, byte ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000BB 671003 ADC byte ptr [ebx], al + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000BE 671203 ADC al, byte ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000C1 671003 ADC byte ptr [ebx], al + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000C4 1410 ADC al, 0x10 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000C6 6611d8 ADC ax, bx + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 3, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000000C9 664411d8 ADC ax, r11w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 11, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000000CD 661303 ADC ax, word ptr [rbx] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000000D0 66671103 ADC word ptr [ebx], ax + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000000D4 66671303 ADC ax, word ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000000D8 66671103 ADC word ptr [ebx], ax + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000000DC 66150010 ADC ax, 0x1000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000000E0 11d8 ADC eax, ebx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000E2 4411d8 ADC eax, r11d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 11, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000E5 1303 ADC eax, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000E7 1103 ADC dword ptr [rbx], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000E9 671303 ADC eax, dword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000EC 671103 ADC dword ptr [ebx], eax + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000EF 1500000010 ADC eax, 0x10000000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000F4 4811d8 ADC rax, rbx + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000F7 4c11d8 ADC rax, r11 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 11, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000FA 481303 ADC rax, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000FD 481103 ADC qword ptr [rbx], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000100 67481303 ADC rax, qword ptr [ebx] + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000104 67481103 ADC qword ptr [ebx], rax + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000108 481500000010 ADC rax, 0x10000000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 8, RawSize: 4, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000010E 18d8 SBB al, bl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 3, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000110 4018f0 SBB al, sil + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 6, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000113 1a03 SBB al, byte ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000115 671803 SBB byte ptr [ebx], al + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000118 671a03 SBB al, byte ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000011B 671803 SBB byte ptr [ebx], al + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000011E 1c10 SBB al, 0x10 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000120 6619d8 SBB ax, bx + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 3, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000123 664419d8 SBB ax, r11w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 11, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000127 661b03 SBB ax, word ptr [rbx] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000012A 66671903 SBB word ptr [ebx], ax + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000012E 66671b03 SBB ax, word ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000132 66671903 SBB word ptr [ebx], ax + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000136 661d0010 SBB ax, 0x1000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000013A 19d8 SBB eax, ebx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000013C 4419d8 SBB eax, r11d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 11, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000013F 1b03 SBB eax, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000141 1903 SBB dword ptr [rbx], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000143 671b03 SBB eax, dword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000146 671903 SBB dword ptr [ebx], eax + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000149 1d00000010 SBB eax, 0x10000000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000014E 4819d8 SBB rax, rbx + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000151 4c19d8 SBB rax, r11 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 11, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000154 481b03 SBB rax, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000157 481903 SBB qword ptr [rbx], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000015A 67481b03 SBB rax, qword ptr [ebx] + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000015E 67481903 SBB qword ptr [ebx], rax + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000162 481d00000010 SBB rax, 0x10000000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 8, RawSize: 4, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000168 20d8 AND al, bl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 3, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000016A 4020f0 AND al, sil + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 6, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000016D 2203 AND al, byte ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000016F 672003 AND byte ptr [ebx], al + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000172 672203 AND al, byte ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000175 672003 AND byte ptr [ebx], al + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000178 2410 AND al, 0x10 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000017A 6621d8 AND ax, bx + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 3, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000017D 664421d8 AND ax, r11w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 11, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000181 662303 AND ax, word ptr [rbx] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000184 66672103 AND word ptr [ebx], ax + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000188 66672303 AND ax, word ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000018C 66672103 AND word ptr [ebx], ax + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000190 66250010 AND ax, 0x1000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000194 21d8 AND eax, ebx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000196 4421d8 AND eax, r11d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 11, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000199 2303 AND eax, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000019B 2103 AND dword ptr [rbx], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000019D 672303 AND eax, dword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000001A0 672103 AND dword ptr [ebx], eax + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000001A3 2500000010 AND eax, 0x10000000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000001A8 4821d8 AND rax, rbx + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000001AB 4c21d8 AND rax, r11 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 11, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000001AE 482303 AND rax, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000001B1 482103 AND qword ptr [rbx], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000001B4 67482303 AND rax, qword ptr [ebx] + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000001B8 67482103 AND qword ptr [ebx], rax + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000001BC 482500000010 AND rax, 0x10000000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 8, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000001C2 08d8 OR al, bl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 3, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000001C4 4008f0 OR al, sil + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 6, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000001C7 0a03 OR al, byte ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000001C9 670803 OR byte ptr [ebx], al + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000001CC 670a03 OR al, byte ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000001CF 670803 OR byte ptr [ebx], al + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000001D2 0c10 OR al, 0x10 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000001D4 6609d8 OR ax, bx + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 3, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000001D7 664409d8 OR ax, r11w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 11, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000001DB 660b03 OR ax, word ptr [rbx] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000001DE 66670903 OR word ptr [ebx], ax + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000001E2 66670b03 OR ax, word ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000001E6 66670903 OR word ptr [ebx], ax + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000001EA 660d0010 OR ax, 0x1000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000001EE 09d8 OR eax, ebx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000001F0 4409d8 OR eax, r11d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 11, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000001F3 0b03 OR eax, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000001F5 0903 OR dword ptr [rbx], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000001F7 670b03 OR eax, dword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000001FA 670903 OR dword ptr [ebx], eax + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000001FD 0d00000010 OR eax, 0x10000000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000202 4809d8 OR rax, rbx + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000205 4c09d8 OR rax, r11 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 11, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000208 480b03 OR rax, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000020B 480903 OR qword ptr [rbx], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000020E 67480b03 OR rax, qword ptr [ebx] + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000212 67480903 OR qword ptr [ebx], rax + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000216 480d00000010 OR rax, 0x10000000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 8, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000021C 30d8 XOR al, bl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 3, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000021E 4030f0 XOR al, sil + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 6, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000221 3203 XOR al, byte ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000223 673003 XOR byte ptr [ebx], al + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000226 673203 XOR al, byte ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000229 673003 XOR byte ptr [ebx], al + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000022C 3410 XOR al, 0x10 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000022E 6631d8 XOR ax, bx + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 3, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000231 664431d8 XOR ax, r11w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 11, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000235 663303 XOR ax, word ptr [rbx] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000238 66673103 XOR word ptr [ebx], ax + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000023C 66673303 XOR ax, word ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000240 66673103 XOR word ptr [ebx], ax + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000244 66350010 XOR ax, 0x1000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000248 31d8 XOR eax, ebx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000024A 4431d8 XOR eax, r11d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 11, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000024D 3303 XOR eax, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000024F 3103 XOR dword ptr [rbx], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000251 673303 XOR eax, dword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000254 673103 XOR dword ptr [ebx], eax + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000257 3500000010 XOR eax, 0x10000000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000025C 4831d8 XOR rax, rbx + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000025F 4c31d8 XOR rax, r11 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 11, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000262 483303 XOR rax, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000265 483103 XOR qword ptr [rbx], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000268 67483303 XOR rax, qword ptr [ebx] + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000026C 67483103 XOR qword ptr [ebx], rax + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000270 483500000010 XOR rax, 0x10000000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 8, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000276 38d8 CMP al, bl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 3, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000278 4038f0 CMP al, sil + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 6, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000027B 3a03 CMP al, byte ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000027D 673803 CMP byte ptr [ebx], al + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000280 673a03 CMP al, byte ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000283 673803 CMP byte ptr [ebx], al + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000286 3c10 CMP al, 0x10 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000288 6639d8 CMP ax, bx + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 3, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000028B 664439d8 CMP ax, r11w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 11, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000028F 663b03 CMP ax, word ptr [rbx] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000292 66673903 CMP word ptr [ebx], ax + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000296 66673b03 CMP ax, word ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000029A 66673903 CMP word ptr [ebx], ax + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000029E 663d0010 CMP ax, 0x1000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000002A2 39d8 CMP eax, ebx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000002A4 4439d8 CMP eax, r11d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 11, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000002A7 3b03 CMP eax, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000002A9 3903 CMP dword ptr [rbx], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000002AB 673b03 CMP eax, dword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000002AE 673903 CMP dword ptr [ebx], eax + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000002B1 3d00000010 CMP eax, 0x10000000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000002B6 4839d8 CMP rax, rbx + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000002B9 4c39d8 CMP rax, r11 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 11, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000002BC 483b03 CMP rax, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000002BF 483903 CMP qword ptr [rbx], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000002C2 67483b03 CMP rax, qword ptr [ebx] + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000002C6 67483903 CMP qword ptr [ebx], rax + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000002CA 483d00000010 CMP rax, 0x10000000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 8, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000002D0 a901000000 TEST eax, 0x00000001 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000002D5 48a901000000 TEST rax, 0x00000001 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 8, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000002DB 4485f0 TEST eax, r14d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 14, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000002DE 4c85f0 TEST rax, r14 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 14, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000002E1 f60301 TEST byte ptr [rbx], 0x01 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000002E4 66f7030100 TEST word ptr [rbx], 0x0001 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000002E9 f70301000000 TEST dword ptr [rbx], 0x00000001 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000002EF 48f70301000000 TEST qword ptr [rbx], 0x00000001 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 8, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000002F6 8403 TEST byte ptr [rbx], al + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000002F8 668503 TEST word ptr [rbx], ax + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000002FB 8503 TEST dword ptr [rbx], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000002FD 488503 TEST qword ptr [rbx], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000300 b0bd MOV al, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: O, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000302 66b8bdbd MOV ax, 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: O, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + +0000000000000306 b8bdbdbdbd MOV eax, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: O, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +000000000000030B 48b8bdbdbdbdbdbdbdbd MOV rax, 0xbdbdbdbdbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: O, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 8, RawSize: 8, Encoding: I + +0000000000000315 a0bdbdbdbdbdbdbdbd MOV al, byte ptr [0xbdbdbdbdbdbdbdbd] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: D, + Segment: 3, Displacement: 0xbdbdbdbdbdbdbdbd, + +000000000000031E 66a1bdbdbdbdbdbdbdbd MOV ax, word ptr [0xbdbdbdbdbdbdbdbd] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: D, + Segment: 3, Displacement: 0xbdbdbdbdbdbdbdbd, + +0000000000000328 a1bdbdbdbdbdbdbdbd MOV eax, dword ptr [0xbdbdbdbdbdbdbdbd] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: D, + Segment: 3, Displacement: 0xbdbdbdbdbdbdbdbd, + +0000000000000331 48a1bdbdbdbdbdbdbdbd MOV rax, qword ptr [0xbdbdbdbdbdbdbdbd] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: D, + Segment: 3, Displacement: 0xbdbdbdbdbdbdbdbd, + +000000000000033B a2bdbdbdbdbdbdbdbd MOV byte ptr [0xbdbdbdbdbdbdbdbd], al + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: D, + Segment: 3, Displacement: 0xbdbdbdbdbdbdbdbd, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + +0000000000000344 66a3bdbdbdbdbdbdbdbd MOV word ptr [0xbdbdbdbdbdbdbdbd], ax + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: D, + Segment: 3, Displacement: 0xbdbdbdbdbdbdbdbd, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000034E a3bdbdbdbdbdbdbdbd MOV dword ptr [0xbdbdbdbdbdbdbdbd], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: D, + Segment: 3, Displacement: 0xbdbdbdbdbdbdbdbd, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000357 48a3bdbdbdbdbdbdbdbd MOV qword ptr [0xbdbdbdbdbdbdbdbd], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: D, + Segment: 3, Displacement: 0xbdbdbdbdbdbdbdbd, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000361 d7 XLATB + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: MISC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: S, + Segment: 3, Base: 3, Index: 0 * 1, + +0000000000000362 86c1 XCHG cl, al + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + +0000000000000364 6691 XCHG ax, cx + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: O, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + +0000000000000366 91 XCHG eax, ecx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: O, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + +0000000000000367 4891 XCHG rax, rcx + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: O, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + +0000000000000369 488703 XCHG qword ptr [rbx], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000036C 67488703 XCHG qword ptr [ebx], rax + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000370 fec0 INC al + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000372 41fec7 INC r15b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 15, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000375 66ffc0 INC ax + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000378 6641ffc7 INC r15w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 15, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000037C ffc0 INC eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000037E 41ffc7 INC r15d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 15, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000381 48ffc0 INC rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000384 49ffc7 INC r15 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 15, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000387 fe03 INC byte ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000389 66ff03 INC word ptr [rbx] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000038C ff03 INC dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000038E 48ff03 INC qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000391 fec8 DEC al + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000393 41fecf DEC r15b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 15, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000396 66ffc8 DEC ax + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000399 6641ffcf DEC r15w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 15, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000039D ffc8 DEC eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000039F 41ffcf DEC r15d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 15, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000003A2 48ffc8 DEC rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000003A5 49ffcf DEC r15 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 15, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000003A8 fe0b DEC byte ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000003AA 66ff0b DEC word ptr [rbx] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000003AD ff0b DEC dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000003AF 48ff0b DEC qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000003B2 f6d0 NOT al + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + +00000000000003B4 41f6d7 NOT r15b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 15, RegCount: 1 + +00000000000003B7 66f7d0 NOT ax + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000003BA 6641f7d7 NOT r15w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 15, RegCount: 1 + +00000000000003BE f7d0 NOT eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000003C0 41f7d7 NOT r15d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 15, RegCount: 1 + +00000000000003C3 48f7d0 NOT rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000003C6 49f7d7 NOT r15 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 15, RegCount: 1 + +00000000000003C9 f613 NOT byte ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + +00000000000003CB 66f713 NOT word ptr [rbx] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + +00000000000003CE f713 NOT dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +00000000000003D0 48f713 NOT qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000003D3 f6d8 NEG al + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000003D5 41f6df NEG r15b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 15, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000003D8 66f7d8 NEG ax + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000003DB 6641f7df NEG r15w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 15, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000003DF f7d8 NEG eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000003E1 41f7df NEG r15d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 15, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000003E4 48f7d8 NEG rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000003E7 49f7df NEG r15 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 15, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000003EA f61b NEG byte ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000003EC 66f71b NEG word ptr [rbx] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000003EF f71b NEG dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000003F1 48f71b NEG qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000003F4 f6f0 DIV al + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000003F6 41f6f7 DIV r15b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 15, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000003F9 66f7f0 DIV ax + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000003FC 6641f7f7 DIV r15w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 15, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000400 f7f0 DIV eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000402 41f7f7 DIV r15d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 15, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000405 48f7f0 DIV rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000408 49f7f7 DIV r15 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 15, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000040B f633 DIV byte ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000040D 66f733 DIV word ptr [rbx] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000410 f733 DIV dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000412 48f733 DIV qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000415 f6e0 MUL al + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000417 41f6e7 MUL r15b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 15, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000041A 66f7e0 MUL ax + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000041D 6641f7e7 MUL r15w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 15, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000421 f7e0 MUL eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000423 41f7e7 MUL r15d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 15, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000426 48f7e0 MUL rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000429 49f7e7 MUL r15 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 15, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000042C f623 MUL byte ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000042E 66f723 MUL word ptr [rbx] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000431 f723 MUL dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000433 48f723 MUL qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000436 f6f8 IDIV al + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000438 41f6ff IDIV r15b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 15, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000043B 66f7f8 IDIV ax + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000043E 6641f7ff IDIV r15w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 15, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000442 f7f8 IDIV eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000444 41f7ff IDIV r15d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 15, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000447 48f7f8 IDIV rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000044A 49f7ff IDIV r15 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 15, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000044D f63b IDIV byte ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000044F 66f73b IDIV word ptr [rbx] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000452 f73b IDIV dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000454 48f73b IDIV qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000457 f6e8 IMUL al + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000459 41f6ef IMUL r15b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 15, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000045C 66f7e8 IMUL ax + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000045F 6641f7ef IMUL r15w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 15, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000463 f7e8 IMUL eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000465 41f7ef IMUL r15d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 15, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000468 48f7e8 IMUL rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000046B 49f7ef IMUL r15 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 15, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000046E f62b IMUL byte ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000470 66f72b IMUL word ptr [rbx] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000473 f72b IMUL dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000475 48f72b IMUL qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000478 d0c0 ROL al, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000047A c0c064 ROL al, 0x64 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000047D d2c0 ROL al, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000047F d003 ROL byte ptr [rbx], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000481 d203 ROL byte ptr [rbx], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000483 66d1c0 ROL ax, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000486 66c1c064 ROL ax, 0x64 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000048A 66d3c0 ROL ax, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000048D 66d103 ROL word ptr [rbx], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000490 66c10364 ROL word ptr [rbx], 0x64 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000494 66d303 ROL word ptr [rbx], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000497 d103 ROL dword ptr [rbx], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000499 c10364 ROL dword ptr [rbx], 0x64 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000049C d303 ROL dword ptr [rbx], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000049E 48d103 ROL qword ptr [rbx], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000004A1 48c10364 ROL qword ptr [rbx], 0x64 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000004A5 48d303 ROL qword ptr [rbx], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000004A8 d0c8 ROR al, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000004AA c0c864 ROR al, 0x64 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000004AD d2c8 ROR al, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000004AF d00b ROR byte ptr [rbx], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000004B1 d20b ROR byte ptr [rbx], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000004B3 66d1c8 ROR ax, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000004B6 66c1c864 ROR ax, 0x64 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000004BA 66d3c8 ROR ax, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000004BD 66d10b ROR word ptr [rbx], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000004C0 66c10b64 ROR word ptr [rbx], 0x64 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000004C4 66d30b ROR word ptr [rbx], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000004C7 d10b ROR dword ptr [rbx], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000004C9 c10b64 ROR dword ptr [rbx], 0x64 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000004CC d30b ROR dword ptr [rbx], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000004CE 48d10b ROR qword ptr [rbx], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000004D1 48c10b64 ROR qword ptr [rbx], 0x64 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000004D5 48d30b ROR qword ptr [rbx], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000004D8 d0d0 RCL al, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000004DA c0d064 RCL al, 0x64 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000004DD d2d0 RCL al, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000004DF d013 RCL byte ptr [rbx], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000004E1 d213 RCL byte ptr [rbx], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000004E3 66d1d0 RCL ax, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000004E6 66c1d064 RCL ax, 0x64 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000004EA 66d3d0 RCL ax, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000004ED 66d113 RCL word ptr [rbx], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000004F0 66c11364 RCL word ptr [rbx], 0x64 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000004F4 66d313 RCL word ptr [rbx], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000004F7 d113 RCL dword ptr [rbx], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000004F9 c11364 RCL dword ptr [rbx], 0x64 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000004FC d313 RCL dword ptr [rbx], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000004FE 48d113 RCL qword ptr [rbx], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000501 48c11364 RCL qword ptr [rbx], 0x64 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000505 48d313 RCL qword ptr [rbx], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000508 d0d8 RCR al, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000050A c0d864 RCR al, 0x64 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000050D d2d8 RCR al, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000050F d01b RCR byte ptr [rbx], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000511 d21b RCR byte ptr [rbx], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000513 66d1d8 RCR ax, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000516 66c1d864 RCR ax, 0x64 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000051A 66d3d8 RCR ax, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000051D 66d11b RCR word ptr [rbx], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000520 66c11b64 RCR word ptr [rbx], 0x64 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000524 66d31b RCR word ptr [rbx], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000527 d11b RCR dword ptr [rbx], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000529 c11b64 RCR dword ptr [rbx], 0x64 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000052C d31b RCR dword ptr [rbx], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000052E 48d11b RCR qword ptr [rbx], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000531 48c11b64 RCR qword ptr [rbx], 0x64 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000535 48d31b RCR qword ptr [rbx], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000538 d0e0 SHL al, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000053A c0e064 SHL al, 0x64 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000053D d2e0 SHL al, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000053F d023 SHL byte ptr [rbx], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000541 d223 SHL byte ptr [rbx], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000543 66d1e0 SHL ax, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000546 66c1e064 SHL ax, 0x64 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000054A 66d3e0 SHL ax, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000054D 66d123 SHL word ptr [rbx], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000550 66c12364 SHL word ptr [rbx], 0x64 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000554 66d323 SHL word ptr [rbx], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000557 d123 SHL dword ptr [rbx], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000559 c12364 SHL dword ptr [rbx], 0x64 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000055C d323 SHL dword ptr [rbx], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000055E 48d123 SHL qword ptr [rbx], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000561 48c12364 SHL qword ptr [rbx], 0x64 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000565 48d323 SHL qword ptr [rbx], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000568 d0e8 SHR al, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000056A c0e864 SHR al, 0x64 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000056D d2e8 SHR al, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000056F d02b SHR byte ptr [rbx], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000571 d22b SHR byte ptr [rbx], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000573 66d1e8 SHR ax, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000576 66c1e864 SHR ax, 0x64 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000057A 66d3e8 SHR ax, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000057D 66d12b SHR word ptr [rbx], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000580 66c12b64 SHR word ptr [rbx], 0x64 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000584 66d32b SHR word ptr [rbx], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000587 d12b SHR dword ptr [rbx], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000589 c12b64 SHR dword ptr [rbx], 0x64 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000058C d32b SHR dword ptr [rbx], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000058E 48d12b SHR qword ptr [rbx], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000591 48c12b64 SHR qword ptr [rbx], 0x64 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000595 48d32b SHR qword ptr [rbx], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000598 d0f8 SAR al, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000059A c0f864 SAR al, 0x64 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000059D d2f8 SAR al, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000059F d03b SAR byte ptr [rbx], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000005A1 d23b SAR byte ptr [rbx], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000005A3 66d1f8 SAR ax, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000005A6 66c1f864 SAR ax, 0x64 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000005AA 66d3f8 SAR ax, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000005AD 66d13b SAR word ptr [rbx], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000005B0 66c13b64 SAR word ptr [rbx], 0x64 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000005B4 66d33b SAR word ptr [rbx], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000005B7 d13b SAR dword ptr [rbx], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000005B9 c13b64 SAR dword ptr [rbx], 0x64 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000005BC d33b SAR dword ptr [rbx], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000005BE 48d13b SAR qword ptr [rbx], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000005C1 48c13b64 SAR qword ptr [rbx], 0x64 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000005C5 48d33b SAR qword ptr [rbx], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000005C8 666bc164 IMUL ax, cx, 0x64 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000005CC 666b0364 IMUL ax, word ptr [rbx], 0x64 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000005D0 6bc164 IMUL eax, ecx, 0x64 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000005D3 6b0364 IMUL eax, dword ptr [rbx], 0x64 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000005D6 486bc164 IMUL rax, rcx, 0x64 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 8, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000005DA 486b0364 IMUL rax, qword ptr [rbx], 0x64 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 8, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000005DE a4 MOVSB + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + DF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: yes, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: S, String: yes, + Segment: 3, Base: 6, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 6, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 4, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000005DF 66a5 MOVSW + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + DF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: yes, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: S, String: yes, + Segment: 3, Base: 6, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 6, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 4, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000005E1 a5 MOVSD + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + DF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: yes, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: S, String: yes, + Segment: 3, Base: 6, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 6, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 4, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000005E2 48a5 MOVSQ + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + DF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: yes, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: S, String: yes, + Segment: 3, Base: 6, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 6, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 4, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000005E4 aa STOSB + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + DF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: yes, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000005E5 66ab STOSW + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + DF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: yes, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000005E7 ab STOSD + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + DF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: yes, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000005E8 48ab STOSQ + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + DF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: yes, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000005EA ac LODSB + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + DF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: yes, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: S, String: yes, + Segment: 3, Base: 6, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 6, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000005EB 66ad LODSW + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + DF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: yes, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: S, String: yes, + Segment: 3, Base: 6, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 6, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000005ED ad LODSD + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + DF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: yes, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: S, String: yes, + Segment: 3, Base: 6, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 6, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000005EE 48ad LODSQ + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + DF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: yes, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: S, String: yes, + Segment: 3, Base: 6, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 6, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000005F0 ae SCASB + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, DF: t, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: yes, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000005F1 66af SCASW + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, DF: t, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: yes, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000005F3 af SCASD + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, DF: t, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: yes, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000005F4 48af SCASQ + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, DF: t, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: yes, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000005F6 a6 CMPSB + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, DF: t, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: yes, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: S, String: yes, + Segment: 3, Base: 6, + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 6, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 4, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000005F7 a6 CMPSB + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, DF: t, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: yes, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: S, String: yes, + Segment: 3, Base: 6, + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 6, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 4, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000005F8 66a7 CMPSW + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, DF: t, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: yes, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: S, String: yes, + Segment: 3, Base: 6, + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 6, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 4, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000005FA a7 CMPSD + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, DF: t, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: yes, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: S, String: yes, + Segment: 3, Base: 6, + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 6, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 4, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000005FB 48a7 CMPSQ + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, DF: t, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: yes, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: S, String: yes, + Segment: 3, Base: 6, + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 6, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 4, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000005FD 6c INSB + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: IOSTRINGOP, CET tracked: no + FLAGS access + DF: t, IOPL: t, VM: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: yes, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000005FE 666d INSW + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: IOSTRINGOP, CET tracked: no + FLAGS access + DF: t, IOPL: t, VM: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: yes, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000600 6d INSD + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: IOSTRINGOP, CET tracked: no + FLAGS access + DF: t, IOPL: t, VM: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: yes, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000601 6e OUTSB + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: IOSTRINGOP, CET tracked: no + FLAGS access + DF: t, IOPL: t, VM: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: yes, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: S, String: yes, + Segment: 3, Base: 6, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 6, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000602 666f OUTSW + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: IOSTRINGOP, CET tracked: no + FLAGS access + DF: t, IOPL: t, VM: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: yes, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: S, String: yes, + Segment: 3, Base: 6, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 6, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000604 6f OUTSD + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: IOSTRINGOP, CET tracked: no + FLAGS access + DF: t, IOPL: t, VM: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: yes, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: S, String: yes, + Segment: 3, Base: 6, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 6, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000605 e410 IN al, 0x10 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: IO, CET tracked: no + FLAGS access + IOPL: t, VM: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000607 66e510 IN ax, 0x10 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: IO, CET tracked: no + FLAGS access + IOPL: t, VM: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000060A ec IN al, dx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: IO, CET tracked: no + FLAGS access + IOPL: t, VM: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000060B 66ed IN ax, dx + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: IO, CET tracked: no + FLAGS access + IOPL: t, VM: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000060D e610 OUT 0x10, al + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: IO, CET tracked: no + FLAGS access + IOPL: t, VM: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000060F 66e710 OUT 0x10, ax + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: IO, CET tracked: no + FLAGS access + IOPL: t, VM: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000612 ee OUT dx, al + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: IO, CET tracked: no + FLAGS access + IOPL: t, VM: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000613 66ef OUT dx, ax + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: IO, CET tracked: no + FLAGS access + IOPL: t, VM: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000615 f04883870010000001 LOCK ADD qword ptr [rdi+0x1000], 0x01 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 7, Displacement: 0x0000000000001000, + Operand: 1, Acc: R-, Type: Immediate, Size: 8, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000061E f2f0830001 XACQUIRE LOCK ADD dword ptr [rax], 0x01 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000623 f3f04883acfe00f0ffff02 XRELEASE LOCK SUB qword ptr [rsi+rdi*8-0x1000], 0x02 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 6, Index: 7 * 8, Displacement: 0xfffffffffffff000, + Operand: 1, Acc: R-, Type: Immediate, Size: 8, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000062E f34088a500100000 XRELEASE MOV byte ptr [rbp+0x1000], spl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: yes + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 2, Base: 5, Displacement: 0x0000000000001000, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + +0000000000000636 f3aa REP STOSB + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + DF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: yes, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: --, Type: Memory, Size: 1, RawSize: 1, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 4, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000638 f3ac REP LODSB + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + DF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: yes, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: --, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: --, Type: Memory, Size: 1, RawSize: 1, Encoding: S, String: yes, + Segment: 3, Base: 6, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 6, RegCount: 1 + Operand: 4, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000063A f266af REPNZ SCASW + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: tm, SF: m, DF: t, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: yes, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: --, Type: Memory, Size: 2, RawSize: 2, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 4, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000063D f348a7 REPZ CMPSQ + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: tm, SF: m, DF: t, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: yes, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: --, Type: Memory, Size: 8, RawSize: 8, Encoding: S, String: yes, + Segment: 3, Base: 6, + Operand: 1, Acc: --, Type: Memory, Size: 8, RawSize: 8, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 6, RegCount: 1 + Operand: 4, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 5, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + diff --git a/bddisasm_test/basic/basic2_64 b/bddisasm_test/basic/basic2_64 new file mode 100644 index 0000000..867cf94 --- /dev/null +++ b/bddisasm_test/basic/basic2_64 @@ -0,0 +1,7 @@ +  fBBHBfgBfBgBBgHBB@@f + +H +fHf + +H +fHffHHfg#fg f#f g#g # gH#gH H#H ffHHfg+fg f+f g+g + gH+gH H+H ffHHfg3fg f3f g3g 3 gH3gH H3H ffHHfg;fg f;f g;g ; gH;gH H;H  (H#+ wgH PgH HgHAIfHfHfHfHfHfHfHfAAI \ No newline at end of file diff --git a/bddisasm_test/basic/basic2_64.asm b/bddisasm_test/basic/basic2_64.asm new file mode 100644 index 0000000..81834c8 --- /dev/null +++ b/bddisasm_test/basic/basic2_64.asm @@ -0,0 +1,171 @@ + bits 64 + + ud2 + sfence + lfence + mfence + + monitor + mwait + + prefetcht0 [rbx] + prefetcht1 [rbx] + prefetcht2 [rbx] + prefetchnta [rbx] + + cmovc ax, cx + cmovc eax, ecx + cmovc rax, rcx + cmovc ax, [ebx] + cmovc ax, [rbx] + cmovc eax, [ebx] + cmovc eax, [rbx] + cmovc rax, [ebx] + cmovc eax, [rbx] + + setnz al + setae cl + seto spl + setnae sil + + cpuid + + shrd ax, cx, 10 + shrd eax, ecx, 10 + shrd rax, rcx, 10 + shrd ax, cx, cl + shrd eax, ecx, cl + shrd rax, rcx, cl + + shld ax, cx, 10 + shld eax, ecx, 10 + shld rax, rcx, 10 + shld ax, cx, cl + shld eax, ecx, cl + shld rax, rcx, cl + + bt ax, 1 + bt ax, cx + bt eax, 1 + bt eax, ecx + bt rax, 1 + bt rax, rcx + bt word [ebx], 1 + bt word [ebx], cx + bt word [rbx], 1 + bt word [rbx], cx + bt dword [ebx], 1 + bt dword [ebx], ecx + bt dword [rbx], 1 + bt dword [rbx], ecx + bt qword [ebx], 1 + bt qword [ebx], rcx + bt qword [rbx], 1 + bt qword [rbx], rcx + + bts ax, 1 + bts ax, cx + bts eax, 1 + bts eax, ecx + bts rax, 1 + bts rax, rcx + bts word [ebx], 1 + bts word [ebx], cx + bts word [rbx], 1 + bts word [rbx], cx + bts dword [ebx], 1 + bts dword [ebx], ecx + bts dword [rbx], 1 + bts dword [rbx], ecx + bts qword [ebx], 1 + bts qword [ebx], rcx + bts qword [rbx], 1 + bts qword [rbx], rcx + + btr ax, 1 + btr ax, cx + btr eax, 1 + btr eax, ecx + btr rax, 1 + btr rax, rcx + btr word [ebx], 1 + btr word [ebx], cx + btr word [rbx], 1 + btr word [rbx], cx + btr dword [ebx], 1 + btr dword [ebx], ecx + btr dword [rbx], 1 + btr dword [rbx], ecx + btr qword [ebx], 1 + btr qword [ebx], rcx + btr qword [rbx], 1 + btr qword [rbx], rcx + + btc ax, 1 + btc ax, cx + btc eax, 1 + btc eax, ecx + btc rax, 1 + btc rax, rcx + btc word [ebx], 1 + btc word [ebx], cx + btc word [rbx], 1 + btc word [rbx], cx + btc dword [ebx], 1 + btc dword [ebx], ecx + btc dword [rbx], 1 + btc dword [rbx], ecx + btc qword [ebx], 1 + btc qword [ebx], rcx + btc qword [rbx], 1 + btc qword [rbx], rcx + + xsave [rax] + xrstor [rax] + xsavec64 [rbx] + xsaves [rbx] + + fxsave [rbx] + fxrstor [rbx] + emms + + cmpxchg [eax], edx + cmpxchg [rax], rdx + cmpxchg8b [rax + rdx * 2] + cmpxchg16b [esi + edi * 4] + + xadd [rax], rdx + xadd [ebx], eax + + bswap eax + bswap rax + bswap r15d + bswap r14 + + popcnt ax, cx + popcnt eax, ecx + popcnt rax, rcx + popcnt ax, [rbx] + popcnt eax, [rbx] + popcnt rax, [rbx] + + lzcnt ax, cx + lzcnt eax, ecx + lzcnt rax, rcx + lzcnt ax, [rbx] + lzcnt eax, [rbx] + lzcnt rax, [rbx] + + tzcnt ax, cx + tzcnt eax, ecx + tzcnt rax, rcx + tzcnt ax, [rbx] + tzcnt eax, [rbx] + tzcnt rax, [rbx] + + rdrand ax + rdrand eax + rdrand rax + rdseed r14w + rdseed r14d + rdseed r14 \ No newline at end of file diff --git a/bddisasm_test/basic/basic2_64.result b/bddisasm_test/basic/basic2_64.result new file mode 100644 index 0000000..ef83ce8 --- /dev/null +++ b/bddisasm_test/basic/basic2_64.result @@ -0,0 +1,2604 @@ +0000000000000000 0f0b UD2 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: PPRO, Ins cat: MISC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000002 0faef8 SFENCE + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSE2, Ins cat: MISC, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000005 0faee8 LFENCE + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSE2, Ins cat: MISC, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000008 0faef0 MFENCE + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSE2, Ins cat: MISC, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000000B 0f01c8 MONITOR + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSE3, Ins cat: MISC, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 3 + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + +000000000000000E 0f01c9 MWAIT + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSE3, Ins cat: MISC, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 3 + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + +0000000000000011 0f180b PREFETCHT0 [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSE, Ins cat: PREFETCH, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 25 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: -2, RawSize: -2, Encoding: M, + Segment: 3, Base: 3, + +0000000000000014 0f1813 PREFETCHT1 [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSE, Ins cat: PREFETCH, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 25 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: -2, RawSize: -2, Encoding: M, + Segment: 3, Base: 3, + +0000000000000017 0f181b PREFETCHT2 [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSE, Ins cat: PREFETCH, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 25 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: -2, RawSize: -2, Encoding: M, + Segment: 3, Base: 3, + +000000000000001A 0f1803 PREFETCHNTA [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSE, Ins cat: PREFETCH, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 25 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: -2, RawSize: -2, Encoding: M, + Segment: 3, Base: 3, + +000000000000001D 660f42c1 CMOVC ax, cx + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: PPRO, Ins cat: CMOV, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 15 + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: --, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000021 0f42c1 CMOVC eax, ecx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: PPRO, Ins cat: CMOV, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 15 + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: --, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000024 480f42c1 CMOVC rax, rcx + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: PPRO, Ins cat: CMOV, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 15 + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: --, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000028 66670f4203 CMOVC ax, word ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: PPRO, Ins cat: CMOV, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 15 + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: --, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000002D 660f4203 CMOVC ax, word ptr [rbx] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: PPRO, Ins cat: CMOV, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 15 + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: --, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000031 670f4203 CMOVC eax, dword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: PPRO, Ins cat: CMOV, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 15 + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: --, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000035 0f4203 CMOVC eax, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: PPRO, Ins cat: CMOV, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 15 + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: --, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000038 67480f4203 CMOVC rax, qword ptr [ebx] + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: PPRO, Ins cat: CMOV, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 15 + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: --, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000003D 0f4203 CMOVC eax, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: PPRO, Ins cat: CMOV, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 15 + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: --, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000040 0f95c0 SETNZ al + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000043 0f93c1 SETNC cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000046 400f90c4 SETO spl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000004A 400f92c6 SETC sil + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 6, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000004E 0fa2 CPUID + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I486REAL, Ins cat: MISC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: no, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + +0000000000000050 660facc80a SHRD ax, cx, 0x0a + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000055 0facc80a SHRD eax, ecx, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000059 480facc80a SHRD rax, rcx, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000005E 660fadc8 SHRD ax, cx, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000062 0fadc8 SHRD eax, ecx, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000065 480fadc8 SHRD rax, rcx, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000069 660fa4c80a SHLD ax, cx, 0x0a + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000006E 0fa4c80a SHLD eax, ecx, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000072 480fa4c80a SHLD rax, rcx, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000077 660fa5c8 SHLD ax, cx, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000007B 0fa5c8 SHLD eax, ecx, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000007E 480fa5c8 SHLD rax, rcx, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: SHIFT, CET tracked: no + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000082 660fbae001 BT ax, 0x01 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000087 660fa3c8 BT ax, cx + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000008B 0fbae001 BT eax, 0x01 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000008F 0fa3c8 BT eax, ecx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000092 480fbae001 BT rax, 0x01 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000097 480fa3c8 BT rax, rcx + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000009B 66670fba2301 BT word ptr [ebx], 0x01 + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000000A1 66670fa30b BT word ptr [ebx], cx + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, Bitbase Addressing: yes, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000000A6 660fba2301 BT word ptr [rbx], 0x01 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000000AB 660fa30b BT word ptr [rbx], cx + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, Bitbase Addressing: yes, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000000AF 670fba2301 BT dword ptr [ebx], 0x01 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000B4 670fa30b BT dword ptr [ebx], ecx + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Bitbase Addressing: yes, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000B8 0fba2301 BT dword ptr [rbx], 0x01 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000BC 0fa30b BT dword ptr [rbx], ecx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Bitbase Addressing: yes, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000BF 67480fba2301 BT qword ptr [ebx], 0x01 + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000C5 67480fa30b BT qword ptr [ebx], rcx + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Bitbase Addressing: yes, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000CA 480fba2301 BT qword ptr [rbx], 0x01 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000CF 480fa30b BT qword ptr [rbx], rcx + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Bitbase Addressing: yes, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000D3 660fbae801 BTS ax, 0x01 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000000D8 660fabc8 BTS ax, cx + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000000DC 0fbae801 BTS eax, 0x01 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000E0 0fabc8 BTS eax, ecx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000E3 480fbae801 BTS rax, 0x01 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000E8 480fabc8 BTS rax, rcx + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000EC 66670fba2b01 BTS word ptr [ebx], 0x01 + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000000F2 66670fab0b BTS word ptr [ebx], cx + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, Bitbase Addressing: yes, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000000F7 660fba2b01 BTS word ptr [rbx], 0x01 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000000FC 660fab0b BTS word ptr [rbx], cx + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, Bitbase Addressing: yes, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000100 670fba2b01 BTS dword ptr [ebx], 0x01 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000105 670fab0b BTS dword ptr [ebx], ecx + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Bitbase Addressing: yes, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000109 0fba2b01 BTS dword ptr [rbx], 0x01 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000010D 0fab0b BTS dword ptr [rbx], ecx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Bitbase Addressing: yes, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000110 67480fba2b01 BTS qword ptr [ebx], 0x01 + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000116 67480fab0b BTS qword ptr [ebx], rcx + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Bitbase Addressing: yes, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000011B 480fba2b01 BTS qword ptr [rbx], 0x01 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000120 480fab0b BTS qword ptr [rbx], rcx + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Bitbase Addressing: yes, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000124 660fbaf001 BTR ax, 0x01 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000129 660fb3c8 BTR ax, cx + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000012D 0fbaf001 BTR eax, 0x01 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000131 0fb3c8 BTR eax, ecx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000134 480fbaf001 BTR rax, 0x01 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000139 480fb3c8 BTR rax, rcx + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000013D 66670fba3301 BTR word ptr [ebx], 0x01 + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000143 66670fb30b BTR word ptr [ebx], cx + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, Bitbase Addressing: yes, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000148 660fba3301 BTR word ptr [rbx], 0x01 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000014D 660fb30b BTR word ptr [rbx], cx + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, Bitbase Addressing: yes, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000151 670fba3301 BTR dword ptr [ebx], 0x01 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000156 670fb30b BTR dword ptr [ebx], ecx + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Bitbase Addressing: yes, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000015A 0fba3301 BTR dword ptr [rbx], 0x01 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000015E 0fb30b BTR dword ptr [rbx], ecx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Bitbase Addressing: yes, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000161 67480fba3301 BTR qword ptr [ebx], 0x01 + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000167 67480fb30b BTR qword ptr [ebx], rcx + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Bitbase Addressing: yes, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000016C 480fba3301 BTR qword ptr [rbx], 0x01 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000171 480fb30b BTR qword ptr [rbx], rcx + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Bitbase Addressing: yes, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000175 660fbaf801 BTC ax, 0x01 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000017A 660fbbc8 BTC ax, cx + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: I386, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000017E 0fbaf801 BTC eax, 0x01 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000182 0fbbc8 BTC eax, ecx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: I386, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000185 480fbaf801 BTC rax, 0x01 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000018A 480fbbc8 BTC rax, rcx + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: I386, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000018E 66670fba3b01 BTC word ptr [ebx], 0x01 + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000194 66670fbb0b BTC word ptr [ebx], cx + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: I386, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, Bitbase Addressing: yes, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000199 660fba3b01 BTC word ptr [rbx], 0x01 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000019E 660fbb0b BTC word ptr [rbx], cx + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: I386, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, Bitbase Addressing: yes, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000001A2 670fba3b01 BTC dword ptr [ebx], 0x01 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000001A7 670fbb0b BTC dword ptr [ebx], ecx + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: I386, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Bitbase Addressing: yes, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000001AB 0fba3b01 BTC dword ptr [rbx], 0x01 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000001AF 0fbb0b BTC dword ptr [rbx], ecx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: I386, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Bitbase Addressing: yes, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000001B2 67480fba3b01 BTC qword ptr [ebx], 0x01 + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000001B8 67480fbb0b BTC qword ptr [ebx], rcx + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: I386, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Bitbase Addressing: yes, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000001BD 480fba3b01 BTC qword ptr [rbx], 0x01 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: BITBYTE, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000001C2 480fbb0b BTC qword ptr [rbx], rcx + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: I386, CET tracked: no + FLAGS access + CF: m, PF: u, AF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Bitbase Addressing: yes, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000001C6 0fae20 XSAVE [rax] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: XSAVE, Ins cat: XSAVE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 26 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: -1, RawSize: -1, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Extended Control, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Bank, Size: -1, RawSize: -1, Encoding: S + +00000000000001C9 0fae28 XRSTOR [rax] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: XSAVE, Ins cat: XSAVE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 26 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: -1, RawSize: -1, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Extended Control, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 4, Acc: -W, Type: Bank, Size: -1, RawSize: -1, Encoding: S + +00000000000001CC 480fc723 XSAVEC64 [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: XSAVEC, Ins cat: XSAVE, CET tracked: no + CPUID leaf: 0x0000000d, sub-leaf: 0x00000001, reg: eax, bit: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: -1, RawSize: -1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Extended Control, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Bank, Size: -1, RawSize: -1, Encoding: S + +00000000000001D0 0fc72b XSAVES [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: XSAVES, Ins cat: XSAVE, CET tracked: no + CPUID leaf: 0x0000000d, sub-leaf: 0x00000001, reg: eax, bit: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: -1, RawSize: -1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Extended Control, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Bank, Size: -1, RawSize: -1, Encoding: S + +00000000000001D3 0fae03 FXSAVE [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: FXSAVE, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 24 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 512, RawSize: 512, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Bank, Size: -1, RawSize: -1, Encoding: S + +00000000000001D6 0fae0b FXRSTOR [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: FXSAVE, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 24 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 512, RawSize: 512, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Bank, Size: -1, RawSize: -1, Encoding: S + +00000000000001D9 0f77 EMMS + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000001DB 670fb110 CMPXCHG dword ptr [eax], edx + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I486REAL, Ins cat: SEMAPHORE, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000001DF 480fb110 CMPXCHG qword ptr [rax], rdx + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I486REAL, Ins cat: SEMAPHORE, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000001E3 0fc70c50 CMPXCHG8B qword ptr [rax+rdx*2] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: PENTIUMREAL, Ins cat: SEMAPHORE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 8 + FLAGS access + ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 0, Index: 2 * 2, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 4, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 5, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000001E7 67480fc70cbe CMPXCHG16B xmmword ptr [esi+edi*4] + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: CMPXCHG16B, Ins cat: SEMAPHORE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 8 + FLAGS access + ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 6, Index: 7 * 4, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 4, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 5, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000001ED 480fc110 XADD qword ptr [rax], rdx + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I486REAL, Ins cat: SEMAPHORE, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000001F1 670fc103 XADD dword ptr [ebx], eax + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I486REAL, Ins cat: SEMAPHORE, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000001F5 0fc8 BSWAP eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I486REAL, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: O, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000001F7 480fc8 BSWAP rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I486REAL, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: O, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000001FA 410fcf BSWAP r15d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I486REAL, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: O, RegType: General Purpose, RegSize: 4, RegId: 15, RegCount: 1 + +00000000000001FD 490fce BSWAP r14 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I486REAL, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: O, RegType: General Purpose, RegSize: 8, RegId: 14, RegCount: 1 + +0000000000000200 66f30fb8c1 POPCNT ax, cx + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: POPCNT, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 23 + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000205 f30fb8c1 POPCNT eax, ecx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: POPCNT, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 23 + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000209 f3480fb8c1 POPCNT rax, rcx + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: POPCNT, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 23 + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000020E 66f30fb803 POPCNT ax, word ptr [rbx] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: POPCNT, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 23 + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000213 f30fb803 POPCNT eax, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: POPCNT, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 23 + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000217 f3480fb803 POPCNT rax, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: POPCNT, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 23 + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000021C 66f30fbdc1 LZCNT ax, cx + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: LZCNT, Ins cat: LZCNT, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 5 + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000221 f30fbdc1 LZCNT eax, ecx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: LZCNT, Ins cat: LZCNT, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 5 + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000225 f3480fbdc1 LZCNT rax, rcx + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: LZCNT, Ins cat: LZCNT, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 5 + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000022A 66f30fbd03 LZCNT ax, word ptr [rbx] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: LZCNT, Ins cat: LZCNT, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 5 + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000022F f30fbd03 LZCNT eax, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: LZCNT, Ins cat: LZCNT, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 5 + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000233 f3480fbd03 LZCNT rax, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: LZCNT, Ins cat: LZCNT, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 5 + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000238 66f30fbcc1 TZCNT ax, cx + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: BMI1, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 3 + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000023D f30fbcc1 TZCNT eax, ecx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: BMI1, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 3 + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000241 f3480fbcc1 TZCNT rax, rcx + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: BMI1, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 3 + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000246 66f30fbc03 TZCNT ax, word ptr [rbx] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: BMI1, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 3 + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000024B f30fbc03 TZCNT eax, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: BMI1, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 3 + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000024F f3480fbc03 TZCNT rax, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: BMI1, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 3 + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000254 660fc7f0 RDRAND ax + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: RDRAND, Ins cat: RDRAND, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 30 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: 0, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000258 0fc7f0 RDRAND eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: RDRAND, Ins cat: RDRAND, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 30 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: 0, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000025B 480fc7f0 RDRAND rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: RDRAND, Ins cat: RDRAND, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 30 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: 0, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000025F 66410fc7fe RDSEED r14w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: RDSEED, Ins cat: RDSEED, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 18 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: 0, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 14, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000264 410fc7fe RDSEED r14d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: RDSEED, Ins cat: RDSEED, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 18 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: 0, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 14, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000268 490fc7fe RDSEED r14 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: RDSEED, Ins cat: RDSEED, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 18 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: 0, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 14, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + diff --git a/bddisasm_test/basic/bmi_64 b/bddisasm_test/basic/bmi_64 new file mode 100644 index 0000000..f031193 --- /dev/null +++ b/bddisasm_test/basic/bmi_64 @@ -0,0 +1,4 @@ +@@@@@BCC@ABC{ +@ @ @@@ B C C @ A B C { + +  diff --git a/bddisasm_test/basic/bmi_64.asm b/bddisasm_test/basic/bmi_64.asm new file mode 100644 index 0000000..3d51e57 --- /dev/null +++ b/bddisasm_test/basic/bmi_64.asm @@ -0,0 +1,57 @@ + bits 64 + + andn ecx,edi,r14d + blsr edi,r14d + blsmsk edi,r14d + blsi edi,r14d + bzhi ecx,r14d,edi + pext ecx,edi,r14d + pdep ecx,edi,r14d + mulx ecx,edi,r14d + bextr ecx,r14d,edi + shlx ecx,r14d,edi + sarx ecx,r14d,edi + shrx ecx,r14d,edi + rorx ecx,r14d,10 + + andn ecx,edi,[rbx] + blsr edi,[rbx] + blsmsk edi,[rbx] + blsi edi,[rbx] + bzhi ecx,[rbx],edi + pext ecx,edi,[rbx] + pdep ecx,edi,[rbx] + mulx ecx,edi,[rbx] + bextr ecx,[rbx],edi + shlx ecx,[rbx],edi + sarx ecx,[rbx],edi + shrx ecx,[rbx],edi + rorx ecx,[rbx],10 + + andn rcx,rdi,r14 + blsr rdi,r14 + blsmsk rdi,r14 + blsi rdi,r14 + bzhi rcx,r14,rdi + pext rcx,rdi,r14 + pdep rcx,rdi,r14 + mulx rcx,rdi,r14 + bextr rcx,r14,rdi + shlx rcx,r14,rdi + sarx rcx,r14,rdi + shrx rcx,r14,rdi + rorx rcx,r14,10 + + andn rcx,rdi,[rbx] + blsr rdi,[rbx] + blsmsk rdi,[rbx] + blsi rdi,[rbx] + bzhi rcx,[rbx],rdi + pext rcx,rdi,[rbx] + pdep rcx,rdi,[rbx] + mulx rcx,rdi,[rbx] + bextr rcx,[rbx],rdi + shlx rcx,[rbx],rdi + sarx rcx,[rbx],rdi + shrx rcx,[rbx],rdi + rorx rcx,[rbx],10 \ No newline at end of file diff --git a/bddisasm_test/basic/bmi_64.result b/bddisasm_test/basic/bmi_64.result new file mode 100644 index 0000000..8eb6d54 --- /dev/null +++ b/bddisasm_test/basic/bmi_64.result @@ -0,0 +1,974 @@ +0000000000000000 c4c240f2ce ANDN ecx, edi, r14d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: BMI1, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 3 + Exception class: SSE/VEX, exception type: 13 + FLAGS access + CF: 0, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 14, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000005 c4c240f3ce BLSR edi, r14d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: BMI1, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 3 + Exception class: SSE/VEX, exception type: 13 + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 14, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000000A c4c240f3d6 BLSMSK edi, r14d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: BMI1, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 3 + Exception class: SSE/VEX, exception type: 13 + FLAGS access + CF: m, PF: u, AF: u, ZF: 0, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 14, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000000F c4c240f3de BLSI edi, r14d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: BMI1, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 3 + Exception class: SSE/VEX, exception type: 13 + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 14, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000014 c4c240f5ce BZHI ecx, r14d, edi + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 14, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000019 c4c242f5ce PEXT ecx, edi, r14d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 14, RegCount: 1 + +000000000000001E c4c243f5ce PDEP ecx, edi, r14d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 14, RegCount: 1 + +0000000000000023 c4c243f6ce MULX ecx, edi, r14d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 14, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + +0000000000000028 c4c240f7ce BEXTR ecx, r14d, edi + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: BMI1, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 3 + Exception class: SSE/VEX, exception type: 13 + FLAGS access + CF: 0, PF: u, AF: u, ZF: m, SF: u, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 14, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000002D c4c241f7ce SHLX ecx, r14d, edi + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 14, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + +0000000000000032 c4c242f7ce SARX ecx, r14d, edi + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 14, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + +0000000000000037 c4c243f7ce SHRX ecx, r14d, edi + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 14, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + +000000000000003C c4c37bf0ce0a RORX ecx, r14d, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 14, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000042 c4e240f20b ANDN ecx, edi, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: BMI1, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 3 + Exception class: SSE/VEX, exception type: 13 + FLAGS access + CF: 0, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000047 c4e240f30b BLSR edi, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: BMI1, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 3 + Exception class: SSE/VEX, exception type: 13 + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000004C c4e240f313 BLSMSK edi, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: BMI1, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 3 + Exception class: SSE/VEX, exception type: 13 + FLAGS access + CF: m, PF: u, AF: u, ZF: 0, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000051 c4e240f31b BLSI edi, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: BMI1, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 3 + Exception class: SSE/VEX, exception type: 13 + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000056 c4e240f50b BZHI ecx, dword ptr [rbx], edi + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000005B c4e242f50b PEXT ecx, edi, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +0000000000000060 c4e243f50b PDEP ecx, edi, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +0000000000000065 c4e243f60b MULX ecx, edi, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + +000000000000006A c4e240f70b BEXTR ecx, dword ptr [rbx], edi + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: BMI1, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 3 + Exception class: SSE/VEX, exception type: 13 + FLAGS access + CF: 0, PF: u, AF: u, ZF: m, SF: u, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000006F c4e241f70b SHLX ecx, dword ptr [rbx], edi + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + +0000000000000074 c4e242f70b SARX ecx, dword ptr [rbx], edi + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + +0000000000000079 c4e243f70b SHRX ecx, dword ptr [rbx], edi + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + +000000000000007E c4e37bf00b0a RORX ecx, dword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000084 c4c2c0f2ce ANDN rcx, rdi, r14 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: BMI1, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 3 + Exception class: SSE/VEX, exception type: 13 + FLAGS access + CF: 0, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 14, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000089 c4c2c0f3ce BLSR rdi, r14 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: BMI1, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 3 + Exception class: SSE/VEX, exception type: 13 + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 14, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000008E c4c2c0f3d6 BLSMSK rdi, r14 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: BMI1, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 3 + Exception class: SSE/VEX, exception type: 13 + FLAGS access + CF: m, PF: u, AF: u, ZF: 0, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 14, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000093 c4c2c0f3de BLSI rdi, r14 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: BMI1, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 3 + Exception class: SSE/VEX, exception type: 13 + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 14, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000098 c4c2c0f5ce BZHI rcx, r14, rdi + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 14, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000009D c4c2c2f5ce PEXT rcx, rdi, r14 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 14, RegCount: 1 + +00000000000000A2 c4c2c3f5ce PDEP rcx, rdi, r14 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 14, RegCount: 1 + +00000000000000A7 c4c2c3f6ce MULX rcx, rdi, r14 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 14, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + +00000000000000AC c4c2c0f7ce BEXTR rcx, r14, rdi + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: BMI1, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 3 + Exception class: SSE/VEX, exception type: 13 + FLAGS access + CF: 0, PF: u, AF: u, ZF: m, SF: u, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 14, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000B1 c4c2c1f7ce SHLX rcx, r14, rdi + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 14, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + +00000000000000B6 c4c2c2f7ce SARX rcx, r14, rdi + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 14, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + +00000000000000BB c4c2c3f7ce SHRX rcx, r14, rdi + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 14, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + +00000000000000C0 c4c3fbf0ce0a RORX rcx, r14, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 14, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000000C6 c4e2c0f20b ANDN rcx, rdi, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: BMI1, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 3 + Exception class: SSE/VEX, exception type: 13 + FLAGS access + CF: 0, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000CB c4e2c0f30b BLSR rdi, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: BMI1, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 3 + Exception class: SSE/VEX, exception type: 13 + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000D0 c4e2c0f313 BLSMSK rdi, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: BMI1, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 3 + Exception class: SSE/VEX, exception type: 13 + FLAGS access + CF: m, PF: u, AF: u, ZF: 0, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000D5 c4e2c0f31b BLSI rdi, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: BMI1, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 3 + Exception class: SSE/VEX, exception type: 13 + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000DA c4e2c0f50b BZHI rcx, qword ptr [rbx], rdi + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000DF c4e2c2f50b PEXT rcx, rdi, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000000E4 c4e2c3f50b PDEP rcx, rdi, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000000E9 c4e2c3f60b MULX rcx, rdi, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + +00000000000000EE c4e2c0f70b BEXTR rcx, qword ptr [rbx], rdi + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: BMI1, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 3 + Exception class: SSE/VEX, exception type: 13 + FLAGS access + CF: 0, PF: u, AF: u, ZF: m, SF: u, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000F3 c4e2c1f70b SHLX rcx, qword ptr [rbx], rdi + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + +00000000000000F8 c4e2c2f70b SARX rcx, qword ptr [rbx], rdi + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + +00000000000000FD c4e2c3f70b SHRX rcx, qword ptr [rbx], rdi + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + +0000000000000102 c4e3fbf00b0a RORX rcx, qword ptr [rbx], 0x0a + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: BMI2, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 8 + Exception class: SSE/VEX, exception type: 13 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + diff --git a/bddisasm_test/basic/branch_16 b/bddisasm_test/basic/branch_16 new file mode 100644 index 0000000000000000000000000000000000000000..f0be7cbb853a28bc00852ad4bee4d63cf43f5030 GIT binary patch literal 118 zcmYj{Jq|!n5QO`{wHi9(@ptKFX4yyMXM2}gLL5h@3;V|9{mGC!H)0anI}L=YQn zx)gyCPznmerovO?h&|Eg=f4P2WOhjznV>>#xnk6fwz_H1U1fjfe7f(xb2JW)7G7RH CqCH&z literal 0 HcmV?d00001 diff --git a/bddisasm_test/basic/branch_16.asm b/bddisasm_test/basic/branch_16.asm new file mode 100644 index 0000000..c781a3c --- /dev/null +++ b/bddisasm_test/basic/branch_16.asm @@ -0,0 +1,51 @@ + bits 16 + + call $ + call ax + call eax + call [bx] + call [ebx] + call word [ebx] + call dword [ebx] + + jmp $ + jmp ax + jmp eax + jmp [bx] + jmp [ebx] + jmp word [ebx] + jmp dword [ebx] + + call word 0x20:0x1000 + call dword 0x20:0x10000000 + jmp word 0x20:0x1000 + call dword 0x20:0x10000000 + + call far word [ebx] + call far word [bx] + call far dword [ebx] + call far dword [bx] + jmp far word [ebx] + jmp far word [bx] + jmp far dword [ebx] + jmp far dword [bx] + + jc $ + jnc $ + loop $ + loopnz $ + jcxz $ + jecxz $ + + int 0x21 + int3 + int1 + icebp + + ret + ret 0x20 + retf + retf 0x20 + + iretw + iretd \ No newline at end of file diff --git a/bddisasm_test/basic/branch_16.result b/bddisasm_test/basic/branch_16.result new file mode 100644 index 0000000..b014c57 --- /dev/null +++ b/bddisasm_test/basic/branch_16.result @@ -0,0 +1,744 @@ +0000000000000000 e8fdff CALL 0x0 + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 2, RawSize: 2, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 3, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Shadow Stack: yes, + + +0000000000000003 ffd0 CALL ax + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: yes + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 3, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Shadow Stack: yes, + + +0000000000000005 66ffd0 CALL eax + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: yes + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 3, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Shadow Stack: yes, + + +0000000000000008 ff17 CALL word ptr [bx] + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: yes + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 3, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Shadow Stack: yes, + + +000000000000000A 67ff13 CALL word ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: yes + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 3, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Shadow Stack: yes, + + +000000000000000D 67ff13 CALL word ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: yes + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 3, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Shadow Stack: yes, + + +0000000000000010 6667ff13 CALL dword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: yes + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 3, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Shadow Stack: yes, + + +0000000000000014 ebfe JMP 0x14 + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: UNCOND_BR, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 2, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000016 ffe0 JMP ax + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: UNCOND_BR, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: yes + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000018 66ffe0 JMP eax + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: UNCOND_BR, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: yes + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000001B ff27 JMP word ptr [bx] + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: UNCOND_BR, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: yes + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000001D 67ff23 JMP word ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: UNCOND_BR, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: yes + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000020 67ff23 JMP word ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: UNCOND_BR, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: yes + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000023 6667ff23 JMP dword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: UNCOND_BR, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: yes + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000027 9a00102000 CALLF 0x0020:0x1000 + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Address, Size: 4, RawSize: 4, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 4, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Shadow Stack: yes, + + +000000000000002C 669a000000102000 CALLF 0x0020:0x10000000 + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Address, Size: 6, RawSize: 6, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 4, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Shadow Stack: yes, + + +0000000000000034 ea00102000 JMPF 0x0020:0x1000 + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: UNCOND_BR, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Address, Size: 4, RawSize: 4, Encoding: D + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000039 669a000000102000 CALLF 0x0020:0x10000000 + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Address, Size: 6, RawSize: 6, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 4, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Shadow Stack: yes, + + +0000000000000041 67ff1b CALLF dword ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 4, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Shadow Stack: yes, + + +0000000000000044 ff1f CALLF dword ptr [bx] + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 4, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Shadow Stack: yes, + + +0000000000000046 6667ff1b CALLF fword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 6, RawSize: 6, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 4, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Shadow Stack: yes, + + +000000000000004A 66ff1f CALLF fword ptr [bx] + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 6, RawSize: 6, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 4, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Shadow Stack: yes, + + +000000000000004D 67ff2b JMPF dword ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: UNCOND_BR, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000050 ff2f JMPF dword ptr [bx] + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: UNCOND_BR, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000052 6667ff2b JMPF fword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: UNCOND_BR, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 6, RawSize: 6, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000056 66ff2f JMPF fword ptr [bx] + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: UNCOND_BR, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 6, RawSize: 6, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000059 72fe JC 0x59 + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: yes, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 2, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000005B 73fe JNC 0x5b + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: yes, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 2, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000005D e2fe LOOP 0x5d + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 2, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000005F e0fe LOOPNZ 0x5f + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 2, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000061 e3fe JCXZ 0x61 + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 2, RawSize: 1, Encoding: D + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000063 67e3fd JECXZ 0x63 + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 2, RawSize: 1, Encoding: D + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000066 cd21 INT 0x21 + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: INTERRUPT, CET tracked: no + FLAGS access + TF: m, IF: m, NT: m, RF: m, VM: tm, AC: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 3, Acc: RW, Type: Memory, Size: 6, RawSize: 6, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 4, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 5, Acc: -W, Type: Memory, Size: 6, RawSize: 6, Encoding: S, Shadow Stack: yes, + + +0000000000000068 cc INT3 + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: INTERRUPT, CET tracked: no + FLAGS access + TF: m, IF: m, NT: m, RF: m, VM: tm, AC: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Memory, Size: 6, RawSize: 6, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 4, Acc: -W, Type: Memory, Size: 6, RawSize: 6, Encoding: S, Shadow Stack: yes, + + +0000000000000069 f1 INT1 + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: INTERRUPT, CET tracked: no + FLAGS access + TF: m, IF: m, NT: m, RF: m, VM: tm, AC: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Memory, Size: 6, RawSize: 6, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000006A f1 INT1 + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: INTERRUPT, CET tracked: no + FLAGS access + TF: m, IF: m, NT: m, RF: m, VM: tm, AC: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Memory, Size: 6, RawSize: 6, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000006B c3 RETN + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: RET, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Shadow Stack: yes, + + +000000000000006C c22000 RETN 0x0020 + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: RET, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 4, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 4, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Shadow Stack: yes, + + +000000000000006F cb RETF + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: RET, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Shadow Stack: yes, + + +0000000000000070 ca2000 RETF 0x0020 + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: RET, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 4, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Shadow Stack: yes, + + +0000000000000073 cf IRETW + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: RET, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 6, RawSize: 6, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 4, Acc: RW, Type: Memory, Size: 6, RawSize: 6, Encoding: S, Shadow Stack: yes, + + +0000000000000074 66cf IRETD + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: RET, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 12, RawSize: 12, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 4, Acc: RW, Type: Memory, Size: 12, RawSize: 12, Encoding: S, Shadow Stack: yes, + + diff --git a/bddisasm_test/basic/branch_32 b/bddisasm_test/basic/branch_32 new file mode 100644 index 0000000000000000000000000000000000000000..1678697ec295adbe8c5a0d824134b0ba2888e1d7 GIT binary patch literal 120 zcmYkzF%E)I5QO2q0Vc1Ypb$bqL1Cj;+SluCIF5Fxfg`*~L$snc?9bZSd^1zb`~{Se zF_IIMK=_!FNRftGshv)CrF0^{(D(nK(8!*`QCjZ@TIXyRds(tLt&=^g$Fkh6rQCbJ J4?}j$P8&hLK12Wj literal 0 HcmV?d00001 diff --git a/bddisasm_test/basic/branch_32.asm b/bddisasm_test/basic/branch_32.asm new file mode 100644 index 0000000..051d23d --- /dev/null +++ b/bddisasm_test/basic/branch_32.asm @@ -0,0 +1,54 @@ + bits 32 + + call $ + call ax + call eax + call [bx] + call [ebx] + call word [ebx] + call dword [ebx] + + jmp $ + jmp ax + jmp eax + jmp [bx] + jmp [ebx] + jmp word [ebx] + jmp dword [ebx] + + call word 0x20:0x1000 + call dword 0x20:0x10000000 + jmp word 0x20:0x1000 + call dword 0x20:0x10000000 + + call far word [ebx] + call far word [bx] + call far dword [ebx] + call far dword [bx] + jmp far word [ebx] + jmp far word [bx] + jmp far dword [ebx] + jmp far dword [bx] + + jc $ + jnc $ + loop $ + loopnz $ + jcxz $ + jecxz $ + + int 0x21 + int3 + int1 + icebp + + ret + ret 0x20 + retf + retf 0x20 + + iretw + iretd + + sysenter + sysexit \ No newline at end of file diff --git a/bddisasm_test/basic/branch_32.result b/bddisasm_test/basic/branch_32.result new file mode 100644 index 0000000..5d823e9 --- /dev/null +++ b/bddisasm_test/basic/branch_32.result @@ -0,0 +1,784 @@ +0000000000000000 e8fbffffff CALL 0x0 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 4, RawSize: 4, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 3, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Shadow Stack: yes, + + +0000000000000005 66ffd0 CALL ax + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: yes + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 3, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Shadow Stack: yes, + + +0000000000000008 ffd0 CALL eax + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: yes + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 3, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Shadow Stack: yes, + + +000000000000000A 67ff17 CALL dword ptr [bx] + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: yes + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 3, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Shadow Stack: yes, + + +000000000000000D ff13 CALL dword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: yes + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 3, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Shadow Stack: yes, + + +000000000000000F 66ff13 CALL word ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: yes + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 3, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Shadow Stack: yes, + + +0000000000000012 ff13 CALL dword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: yes + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 3, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Shadow Stack: yes, + + +0000000000000014 ebfe JMP 0x14 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: UNCOND_BR, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 4, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000016 66ffe0 JMP ax + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: UNCOND_BR, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: yes + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000019 ffe0 JMP eax + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: UNCOND_BR, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: yes + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000001B 67ff27 JMP dword ptr [bx] + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: UNCOND_BR, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: yes + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000001E ff23 JMP dword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: UNCOND_BR, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: yes + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000020 66ff23 JMP word ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: UNCOND_BR, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: yes + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000023 ff23 JMP dword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: UNCOND_BR, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: yes + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000025 669a00102000 CALLF 0x0020:0x1000 + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Address, Size: 4, RawSize: 4, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 4, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Shadow Stack: yes, + + +000000000000002B 9a000000102000 CALLF 0x0020:0x10000000 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Address, Size: 6, RawSize: 6, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 4, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Shadow Stack: yes, + + +0000000000000032 66ea00102000 JMPF 0x0020:0x1000 + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: UNCOND_BR, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Address, Size: 4, RawSize: 4, Encoding: D + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000038 9a000000102000 CALLF 0x0020:0x10000000 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Address, Size: 6, RawSize: 6, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 4, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Shadow Stack: yes, + + +000000000000003F 66ff1b CALLF dword ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 4, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Shadow Stack: yes, + + +0000000000000042 6667ff1f CALLF dword ptr [bx] + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 4, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Shadow Stack: yes, + + +0000000000000046 ff1b CALLF fword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 6, RawSize: 6, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 4, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Shadow Stack: yes, + + +0000000000000048 67ff1f CALLF fword ptr [bx] + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 6, RawSize: 6, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 4, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Shadow Stack: yes, + + +000000000000004B 66ff2b JMPF dword ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: UNCOND_BR, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000004E 6667ff2f JMPF dword ptr [bx] + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: UNCOND_BR, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000052 ff2b JMPF fword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: UNCOND_BR, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 6, RawSize: 6, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000054 67ff2f JMPF fword ptr [bx] + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: UNCOND_BR, CET tracked: yes + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 6, RawSize: 6, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000057 72fe JC 0x57 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: yes, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 4, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000059 73fe JNC 0x59 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: yes, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 4, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000005B e2fe LOOP 0x5b + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 4, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000005D e0fe LOOPNZ 0x5d + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 4, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000005F 67e3fd JCXZ 0x5f + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 4, RawSize: 1, Encoding: D + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000062 e3fe JECXZ 0x62 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 4, RawSize: 1, Encoding: D + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000064 cd21 INT 0x21 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: INTERRUPT, CET tracked: no + FLAGS access + TF: m, IF: m, NT: m, RF: m, VM: tm, AC: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: RW, Type: Memory, Size: 12, RawSize: 12, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 5, Acc: -W, Type: Memory, Size: 12, RawSize: 12, Encoding: S, Shadow Stack: yes, + + +0000000000000066 cc INT3 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: INTERRUPT, CET tracked: no + FLAGS access + TF: m, IF: m, NT: m, RF: m, VM: tm, AC: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Memory, Size: 12, RawSize: 12, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 4, Acc: -W, Type: Memory, Size: 12, RawSize: 12, Encoding: S, Shadow Stack: yes, + + +0000000000000067 f1 INT1 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: INTERRUPT, CET tracked: no + FLAGS access + TF: m, IF: m, NT: m, RF: m, VM: tm, AC: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Memory, Size: 12, RawSize: 12, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000068 f1 INT1 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: INTERRUPT, CET tracked: no + FLAGS access + TF: m, IF: m, NT: m, RF: m, VM: tm, AC: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Memory, Size: 12, RawSize: 12, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000069 c3 RETN + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: RET, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Shadow Stack: yes, + + +000000000000006A c22000 RETN 0x0020 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: RET, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Immediate, Size: 4, RawSize: 2, Encoding: I + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 4, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 4, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Shadow Stack: yes, + + +000000000000006D cb RETF + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: RET, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Shadow Stack: yes, + + +000000000000006E ca2000 RETF 0x0020 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: RET, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Immediate, Size: 4, RawSize: 2, Encoding: I + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 4, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Shadow Stack: yes, + + +0000000000000071 66cf IRETW + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: RET, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: IP, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 6, RawSize: 6, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 4, Acc: RW, Type: Memory, Size: 6, RawSize: 6, Encoding: S, Shadow Stack: yes, + + +0000000000000073 cf IRETD + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: RET, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 12, RawSize: 12, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 4, Acc: RW, Type: Memory, Size: 12, RawSize: 12, Encoding: S, Shadow Stack: yes, + + +0000000000000074 0f34 SYSENTER + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: PPRO, Ins cat: SYSCALL, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 11 + FLAGS access + IF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: 372, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: 373, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: 374, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 4, RegCount: 1 + Operand: 5, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 6, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 7, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000076 0f35 SYSEXIT + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: PPRO, Ins cat: SYSRET, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 11 + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 4, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + diff --git a/bddisasm_test/basic/branch_64 b/bddisasm_test/basic/branch_64 new file mode 100644 index 0000000000000000000000000000000000000000..b2663d665451d3f374793253603a5513913b0920 GIT binary patch literal 70 zcmV-M0J;C@`~Uy{|Ilau6aN$I{{P@-|0Dk+X8#-i8%X~fX8$YyD@gwd0g*zKbrJF!#K@bhh5^4J&;F|1mpk|}f}tf#gvjn|~8~8viC{5Dlb&{4GHK79f8MJCFkMw*vWFf&8uP GKneg_q%So9 literal 0 HcmV?d00001 diff --git a/bddisasm_test/basic/misc_32.asm b/bddisasm_test/basic/misc_32.asm new file mode 100644 index 0000000..a792fc2 --- /dev/null +++ b/bddisasm_test/basic/misc_32.asm @@ -0,0 +1,65 @@ + bits 32 + + daa + das + aaa + aas + aam 100 + aad 100 + + bound ax, [ebx + esi] + bound eax, [ebx + esi] + arpl [bx], ax + arpl [ebx], ax + + nop + pause + clc + cmc + stc + cld + std + cli + sti + cbw + cwde + cwd + cdq + wait + + sahf + lahf + salc + + lea ax, [bx] + lea ax, [bx + si] + + les ax, [bx] + les ax, [ebx] + les eax, [bx] + les eax, [ebx] + + lds ax, [bx] + lds ax, [ebx] + lds eax, [bx] + lds eax, [ebx] + + lss ax, [bx] + lss ax, [ebx] + lss eax, [bx] + lss eax, [ebx] + + lfs ax, [bx] + lfs ax, [ebx] + lfs eax, [bx] + lfs eax, [ebx] + + lgs ax, [bx] + lgs ax, [ebx] + lgs eax, [bx] + lgs eax, [ebx] + + + + + \ No newline at end of file diff --git a/bddisasm_test/basic/misc_32.result b/bddisasm_test/basic/misc_32.result new file mode 100644 index 0000000..736f843 --- /dev/null +++ b/bddisasm_test/basic/misc_32.result @@ -0,0 +1,765 @@ +0000000000000000 27 DAA + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DECIMAL, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: tm, ZF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000001 2f DAS + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DECIMAL, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: tm, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000002 37 AAA + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DECIMAL, CET tracked: no + FLAGS access + CF: m, PF: u, AF: tm, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000003 3f AAS + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DECIMAL, CET tracked: no + FLAGS access + CF: m, PF: u, AF: tm, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000004 d464 AAM 0x64 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DECIMAL, CET tracked: no + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 1, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000006 d564 AAD 0x64 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DECIMAL, CET tracked: no + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 1, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000008 66620433 BOUND ax, dword ptr [ebx+esi] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I186, Ins cat: INTERRUPT, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 1, + +000000000000000C 620433 BOUND eax, qword ptr [ebx+esi] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I186, Ins cat: INTERRUPT, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, Index: 6 * 1, + +000000000000000F 676307 ARPL word ptr [bx], ax + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I286PROT, Ins cat: SYSTEM, CET tracked: no + FLAGS access + ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000012 6303 ARPL word ptr [ebx], ax + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I286PROT, Ins cat: SYSTEM, CET tracked: no + FLAGS access + ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000014 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000015 f390 PAUSE + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: PAUSE, Ins cat: MISC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: no, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000017 f8 CLC + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: FLAGOP, CET tracked: no + FLAGS access + CF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000018 f5 CMC + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: FLAGOP, CET tracked: no + FLAGS access + CF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000019 f9 STC + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: FLAGOP, CET tracked: no + FLAGS access + CF: 1, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000001A fc CLD + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: FLAGOP, CET tracked: no + FLAGS access + DF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000001B fd STD + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: FLAGOP, CET tracked: no + FLAGS access + DF: 1, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000001C fa CLI + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: FLAGOP, CET tracked: no + FLAGS access + IF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000001D fb STI + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: FLAGOP, CET tracked: no + FLAGS access + IF: 1, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000001E 6698 CBW + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: CONVERT, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + +0000000000000020 98 CWDE + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: CONVERT, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000021 6699 CWD + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: CONVERT, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000023 99 CDQ + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: CONVERT, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000024 9b WAIT + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: X87, Ins cat: X87_ALU, CET tracked: no + FPU flags access + C0: u, C1: u, C2: u, C3: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000025 9e SAHF + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: FLAGOP, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000026 9f LAHF + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: FLAGOP, CET tracked: no + FLAGS access + CF: t, PF: t, AF: t, ZF: t, SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000027 d6 SALC + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: FLAGOP, CET tracked: no + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000028 66678d07 LEA ax, [bx] + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: MISC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: --, Type: Memory, Size: 0, RawSize: 0, Encoding: M, Address Generator: yes, + Base: 3, + +000000000000002C 66678d00 LEA ax, [bx+si] + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: MISC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: --, Type: Memory, Size: 0, RawSize: 0, Encoding: M, Address Generator: yes, + Base: 3, Index: 6 * 1, + +0000000000000030 6667c407 LES ax, dword ptr [bx] + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000034 66c403 LES ax, dword ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000037 67c407 LES eax, fword ptr [bx] + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 6, RawSize: 6, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000003A c403 LES eax, fword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 6, RawSize: 6, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000003C 6667c507 LDS ax, dword ptr [bx] + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 3, RegCount: 1 + +0000000000000040 66c503 LDS ax, dword ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 3, RegCount: 1 + +0000000000000043 67c507 LDS eax, fword ptr [bx] + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 6, RawSize: 6, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 3, RegCount: 1 + +0000000000000046 c503 LDS eax, fword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 6, RawSize: 6, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 3, RegCount: 1 + +0000000000000048 66670fb207 LSS ax, dword ptr [bx] + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 2, RegCount: 1 + +000000000000004D 660fb203 LSS ax, dword ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 2, RegCount: 1 + +0000000000000051 670fb207 LSS eax, fword ptr [bx] + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 6, RawSize: 6, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 2, RegCount: 1 + +0000000000000055 0fb203 LSS eax, fword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 6, RawSize: 6, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 2, RegCount: 1 + +0000000000000058 66670fb407 LFS ax, dword ptr [bx] + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 4, RegCount: 1 + +000000000000005D 660fb403 LFS ax, dword ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 4, RegCount: 1 + +0000000000000061 670fb407 LFS eax, fword ptr [bx] + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 6, RawSize: 6, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 4, RegCount: 1 + +0000000000000065 0fb403 LFS eax, fword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 6, RawSize: 6, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 4, RegCount: 1 + +0000000000000068 66670fb507 LGS ax, dword ptr [bx] + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 5, RegCount: 1 + +000000000000006D 660fb503 LGS ax, dword ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 5, RegCount: 1 + +0000000000000071 670fb507 LGS eax, fword ptr [bx] + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 6, RawSize: 6, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 5, RegCount: 1 + +0000000000000075 0fb503 LGS eax, fword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 6, RawSize: 6, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 5, RegCount: 1 + diff --git a/bddisasm_test/basic/misc_64 b/bddisasm_test/basic/misc_64 new file mode 100644 index 0000000..7cce43b --- /dev/null +++ b/bddisasm_test/basic/misc_64 @@ -0,0 +1 @@ +fHfHfgggHfHfgfggHHfgfggHHfgfggHHHHHHf88H8f88H88H88H8f88H8fH8fH8H8H8 \ No newline at end of file diff --git a/bddisasm_test/basic/misc_64.asm b/bddisasm_test/basic/misc_64.asm new file mode 100644 index 0000000..7515388 --- /dev/null +++ b/bddisasm_test/basic/misc_64.asm @@ -0,0 +1,92 @@ + bits 64 + + nop + pause + clc + cmc + stc + cld + std + cli + sti + cbw + cwde + cdqe + cwd + cdq + cqo + wait + + sahf + lahf + salc + + lea ax, [ebx] + lea eax, [ebx] + lea rax, [ebx] + lea ax, [rbx] + lea eax, [rbx] + lea rax, [rbx] + + lss ax, [ebx] + lss ax, [rbx] + lss eax, [ebx] + lss eax, [rbx] + lss rax, [ebx] + lss rax, [rbx] + + lfs ax, [ebx] + lfs ax, [rbx] + lfs eax, [ebx] + lfs eax, [rbx] + lfs rax, [ebx] + lfs rax, [rbx] + + lgs ax, [ebx] + lgs ax, [rbx] + lgs eax, [ebx] + lgs eax, [rbx] + lgs rax, [ebx] + lgs rax, [rbx] + + rdfsbase eax + rdfsbase rax + rdgsbase eax + rdgsbase rax + wrfsbase eax + wrfsbase rax + wrgsbase eax + wrgsbase rax + + movbe ax, [rbx] + movbe eax, [rbx] + movbe rax, [rbx] + + movbe [rbx], ax + movbe [rbx], eax + movbe [rbx], rax + + crc32 eax, al + crc32 rax, al + crc32 eax, byte [rbx] + crc32 rax, byte [rbx] + + ;crc32 eax, ax + ;crc32 rax, ax + crc32 eax, word [rbx] + ;crc32 rax, word [rbx] + + ;crc32 eax, eax + ;crc32 rax, eax + crc32 eax, dword [rbx] + ;crc32 rax, dword [rbx] + + ;crc32 eax, eax + ;crc32 rax, eax + ;crc32 eax, qword [rbx] + crc32 rax, qword [rbx] + + adcx rax, rcx + adcx rax, [rbx] + adox rax, rcx + adox rax, [rbx] \ No newline at end of file diff --git a/bddisasm_test/basic/misc_64.result b/bddisasm_test/basic/misc_64.result new file mode 100644 index 0000000..8017585 --- /dev/null +++ b/bddisasm_test/basic/misc_64.result @@ -0,0 +1,1053 @@ +0000000000000000 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000001 f390 PAUSE + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: PAUSE, Ins cat: MISC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: no, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000003 f8 CLC + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: FLAGOP, CET tracked: no + FLAGS access + CF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000004 f5 CMC + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: FLAGOP, CET tracked: no + FLAGS access + CF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000005 f9 STC + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: FLAGOP, CET tracked: no + FLAGS access + CF: 1, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000006 fc CLD + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: FLAGOP, CET tracked: no + FLAGS access + DF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000007 fd STD + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: FLAGOP, CET tracked: no + FLAGS access + DF: 1, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000008 fa CLI + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: FLAGOP, CET tracked: no + FLAGS access + IF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000009 fb STI + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: FLAGOP, CET tracked: no + FLAGS access + IF: 1, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000000A 6698 CBW + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: CONVERT, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + +000000000000000C 98 CWDE + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: CONVERT, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000000D 4898 CDQE + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: CONVERT, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000000F 6699 CWD + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: CONVERT, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000011 99 CDQ + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: CONVERT, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000012 4899 CQO + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: CONVERT, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000014 9b WAIT + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: X87, Ins cat: X87_ALU, CET tracked: no + FPU flags access + C0: u, C1: u, C2: u, C3: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000015 9e SAHF + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: FLAGOP, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000016 9f LAHF + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: FLAGOP, CET tracked: no + FLAGS access + CF: t, PF: t, AF: t, ZF: t, SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000017 d6 SALC + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: FLAGOP, CET tracked: no + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000018 66678d03 LEA ax, [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: MISC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: --, Type: Memory, Size: 0, RawSize: 0, Encoding: M, Address Generator: yes, + Base: 3, + +000000000000001C 678d03 LEA eax, [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: MISC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: --, Type: Memory, Size: 0, RawSize: 0, Encoding: M, Address Generator: yes, + Base: 3, + +000000000000001F 67488d03 LEA rax, [ebx] + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: MISC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: --, Type: Memory, Size: 0, RawSize: 0, Encoding: M, Address Generator: yes, + Base: 3, + +0000000000000023 668d03 LEA ax, [rbx] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: MISC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: --, Type: Memory, Size: 0, RawSize: 0, Encoding: M, Address Generator: yes, + Base: 3, + +0000000000000026 8d03 LEA eax, [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: MISC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: --, Type: Memory, Size: 0, RawSize: 0, Encoding: M, Address Generator: yes, + Base: 3, + +0000000000000028 488d03 LEA rax, [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: MISC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: --, Type: Memory, Size: 0, RawSize: 0, Encoding: M, Address Generator: yes, + Base: 3, + +000000000000002B 66670fb203 LSS ax, dword ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 2, RegCount: 1 + +0000000000000030 660fb203 LSS ax, dword ptr [rbx] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 2, RegCount: 1 + +0000000000000034 670fb203 LSS eax, fword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 6, RawSize: 6, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 2, RegCount: 1 + +0000000000000038 0fb203 LSS eax, fword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 6, RawSize: 6, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 2, RegCount: 1 + +000000000000003B 67480fb203 LSS rax, tbyte ptr [ebx] + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 10, RawSize: 10, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Segment, RegSize: 8, RegId: 2, RegCount: 1 + +0000000000000040 480fb203 LSS rax, tbyte ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 10, RawSize: 10, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Segment, RegSize: 8, RegId: 2, RegCount: 1 + +0000000000000044 66670fb403 LFS ax, dword ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 4, RegCount: 1 + +0000000000000049 660fb403 LFS ax, dword ptr [rbx] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 4, RegCount: 1 + +000000000000004D 670fb403 LFS eax, fword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 6, RawSize: 6, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 4, RegCount: 1 + +0000000000000051 0fb403 LFS eax, fword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 6, RawSize: 6, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 4, RegCount: 1 + +0000000000000054 67480fb403 LFS rax, tbyte ptr [ebx] + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 10, RawSize: 10, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Segment, RegSize: 8, RegId: 4, RegCount: 1 + +0000000000000059 480fb403 LFS rax, tbyte ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 10, RawSize: 10, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Segment, RegSize: 8, RegId: 4, RegCount: 1 + +000000000000005D 66670fb503 LGS ax, dword ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 5, RegCount: 1 + +0000000000000062 660fb503 LGS ax, dword ptr [rbx] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 5, RegCount: 1 + +0000000000000066 670fb503 LGS eax, fword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 6, RawSize: 6, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 5, RegCount: 1 + +000000000000006A 0fb503 LGS eax, fword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 6, RawSize: 6, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 5, RegCount: 1 + +000000000000006D 67480fb503 LGS rax, tbyte ptr [ebx] + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 10, RawSize: 10, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Segment, RegSize: 8, RegId: 5, RegCount: 1 + +0000000000000072 480fb503 LGS rax, tbyte ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I386, Ins cat: SEGOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 10, RawSize: 10, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Segment, RegSize: 8, RegId: 5, RegCount: 1 + +0000000000000076 f30faec0 RDFSBASE eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: RDWRFSGS, Ins cat: RDWRFSGS, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 0 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: -1073741568, RegCount: 1 + +000000000000007A f3480faec0 RDFSBASE rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: RDWRFSGS, Ins cat: RDWRFSGS, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 0 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: -1073741568, RegCount: 1 + +000000000000007F f30faec8 RDGSBASE eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: RDWRFSGS, Ins cat: RDWRFSGS, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 0 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: -1073741567, RegCount: 1 + +0000000000000083 f3480faec8 RDGSBASE rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: RDWRFSGS, Ins cat: RDWRFSGS, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 0 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: -1073741567, RegCount: 1 + +0000000000000088 f30faed0 WRFSBASE eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: RDWRFSGS, Ins cat: RDWRFSGS, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 0 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: -1073741568, RegCount: 1 + +000000000000008C f3480faed0 WRFSBASE rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: RDWRFSGS, Ins cat: RDWRFSGS, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 0 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: -1073741568, RegCount: 1 + +0000000000000091 f30faed8 WRGSBASE eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: RDWRFSGS, Ins cat: RDWRFSGS, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 0 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: -1073741567, RegCount: 1 + +0000000000000095 f3480faed8 WRGSBASE rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: RDWRFSGS, Ins cat: RDWRFSGS, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 0 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: -1073741567, RegCount: 1 + +000000000000009A 660f38f003 MOVBE ax, word ptr [rbx] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: MOVBE, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 22 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + +000000000000009F 0f38f003 MOVBE eax, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MOVBE, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 22 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +00000000000000A3 480f38f003 MOVBE rax, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: MOVBE, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 22 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000000A8 660f38f103 MOVBE word ptr [rbx], ax + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: MOVBE, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 22 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000000AD 0f38f103 MOVBE dword ptr [rbx], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MOVBE, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 22 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000B1 480f38f103 MOVBE qword ptr [rbx], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: MOVBE, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 22 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000B6 f20f38f0c0 CRC32 eax, al + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSE42, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 20 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + +00000000000000BB f2480f38f0c0 CRC32 rax, al + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: SSE42, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 20 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + +00000000000000C1 f20f38f003 CRC32 eax, byte ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSE42, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 20 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + +00000000000000C6 f2480f38f003 CRC32 rax, byte ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: SSE42, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 20 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + +00000000000000CC 66f20f38f103 CRC32 eax, word ptr [rbx] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: SSE42, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 20 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + +00000000000000D2 f20f38f103 CRC32 eax, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSE42, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 20 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +00000000000000D7 f2480f38f103 CRC32 rax, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: SSE42, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 20 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000000DD 66480f38f6c1 ADCX rax, rcx + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: ADX, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 19 + FLAGS access + CF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000E3 66480f38f603 ADCX rax, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: ADX, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 19 + FLAGS access + CF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000E9 f3480f38f6c1 ADOX rax, rcx + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: ADX, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 19 + FLAGS access + OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000EF f3480f38f603 ADOX rax, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: ADX, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 19 + FLAGS access + OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + diff --git a/bddisasm_test/basic/mpx_64 b/bddisasm_test/basic/mpx_64 new file mode 100644 index 0000000..035bb0b --- /dev/null +++ b/bddisasm_test/basic/mpx_64 @@ -0,0 +1 @@ +3ff3ff \ No newline at end of file diff --git a/bddisasm_test/basic/mpx_64.asm b/bddisasm_test/basic/mpx_64.asm new file mode 100644 index 0000000..c6c371b --- /dev/null +++ b/bddisasm_test/basic/mpx_64.asm @@ -0,0 +1,15 @@ + bits 64 + + bndldx bnd0, [rbx + rsi] + bndmov bnd0, bnd3 + bndmov bnd0, [rbx] + bndcl bnd0, rax + bndcl bnd0, [rbx] + bndcu bnd0, rax + bndcu bnd0, [rbx] + bndstx [rbx + rsi], bnd0 + bndmov bnd0, bnd3 + bndmov [rbx], bnd0 + bndmk bnd0, [rbx] + bndcn bnd0, rax + bndcn bnd0, [rbx] \ No newline at end of file diff --git a/bddisasm_test/basic/mpx_64.result b/bddisasm_test/basic/mpx_64.result new file mode 100644 index 0000000..6781efa --- /dev/null +++ b/bddisasm_test/basic/mpx_64.result @@ -0,0 +1,203 @@ +0000000000000000 0f1a0433 BNDLDX bnd0, [rbx+rsi] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MPX, Ins cat: MPX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 14 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Bound, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 0, RawSize: 0, Encoding: M, Address Generator: yes, MIB Addressing: yes, + Base: 3, Index: 6 * 1, + +0000000000000004 660f1ac3 BNDMOV bnd0, bnd3 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MPX, Ins cat: MPX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 14 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Bound, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Bound, RegSize: 16, RegId: 3, RegCount: 1 + +0000000000000008 660f1a03 BNDMOV bnd0, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MPX, Ins cat: MPX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 14 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Bound, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000000C f30f1ac0 BNDCL bnd0, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: MPX, Ins cat: MPX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 14 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Bound, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000010 f30f1a03 BNDCL bnd0, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: MPX, Ins cat: MPX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 14 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Bound, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Address Generator: yes, + Base: 3, + +0000000000000014 f20f1ac0 BNDCU bnd0, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: MPX, Ins cat: MPX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 14 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Bound, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000018 f20f1a03 BNDCU bnd0, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: MPX, Ins cat: MPX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 14 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Bound, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Address Generator: yes, + Base: 3, + +000000000000001C 0f1b0433 BNDSTX [rbx+rsi], bnd0 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MPX, Ins cat: MPX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 14 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 0, RawSize: 0, Encoding: M, Address Generator: yes, MIB Addressing: yes, + Base: 3, Index: 6 * 1, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Bound, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000020 660f1ac3 BNDMOV bnd0, bnd3 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MPX, Ins cat: MPX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 14 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Bound, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Bound, RegSize: 16, RegId: 3, RegCount: 1 + +0000000000000024 660f1b03 BNDMOV xmmword ptr [rbx], bnd0 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MPX, Ins cat: MPX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 14 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Bound, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000028 f30f1b03 BNDMK bnd0, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: MPX, Ins cat: MPX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 14 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Bound, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000002C f20f1bc0 BNDCN bnd0, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: MPX, Ins cat: MPX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 14 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Bound, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000030 f20f1b03 BNDCN bnd0, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: MPX, Ins cat: MPX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 14 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Bound, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Address Generator: yes, + Base: 3, + diff --git a/bddisasm_test/basic/prefixes_64 b/bddisasm_test/basic/prefixes_64 new file mode 100644 index 0000000000000000000000000000000000000000..16be6f47ae2dbb1f05b26debc9a1ab67821f437e GIT binary patch literal 292 zcmYL^u?@mN3`M;GOhFmRvP2nCTFgOweKtZ$mEvabE@>!{y#W3Jg_Ga+zi$_J;wc{D zP29w_v{2Z}6CT{e@8V32$qFr+GCk>c+V1SQ+c&^ek5K=iZKNBus>POEW6d5tqeu4B z*$qGvKmtH4aJAfn#7@}075ly+Po`jcSJe}>dcaqd=$OJJ(hJkTbY&Wu9!yhdF_j%= K8fS_ZzVHD};A}Pk literal 0 HcmV?d00001 diff --git a/bddisasm_test/basic/prefixes_64.asm b/bddisasm_test/basic/prefixes_64.asm new file mode 100644 index 0000000..1324260 --- /dev/null +++ b/bddisasm_test/basic/prefixes_64.asm @@ -0,0 +1,91 @@ + bits 64 + + ; Rex, 0x66. + db 0x33, 0xC0 ; xor eax, eax + db 0xF3, 0x33, 0xC0 ; xor eax, eax + db 0xF2, 0x33, 0xC0 ; xor eax, eax + db 0x67, 0x33, 0xC0 ; xor eax, eax + db 0x66, 0x33, 0xC0 ; xor ax, ax + db 0x48, 0x33, 0xC0 ; xor rax, rax + db 0x66, 0x48, 0x33, 0xC0 ; xor rax, rax + db 0x48, 0x66, 0x33, 0xC0 ; xor ax, ax + db 0x48, 0xF3, 0x33, 0xC0 ; xor eax, eax + db 0xF3, 0x48, 0x33, 0xC0 ; xor rax, rax + db 0x48, 0x48, 0x33, 0xC0 ; xor rax, rax + db 0x48, 0x40, 0x33, 0xC0 ; xor eax, eax + db 0x4A, 0x33, 0xC0 ; xor rax, rax + + ; 0x67. + db 0x31, 0x00 ; xor [rax], eax + db 0x67, 0x31, 0x00 ; xor [eax], eax + db 0x66, 0x67, 0x31, 0x00 ; xor [eax], ax + db 0x48, 0x67, 0x31, 0x00 ; xor [eax], eax + db 0x67, 0x48, 0x31, 0x00 ; xor [eax], rax + + db 0xA1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ; mov eax, [0x0000000000000000] + db 0x67, 0xA1, 0x00, 0x00, 0x00, 0x00 ; mov eax, [0x00000000] + db 0x66, 0xA1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ; mov ax, [0x0000000000000000] + db 0x66, 0x67, 0xA1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ; mov ax, [0x00000000] + db 0x48, 0xA1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ; mov rax, [0x0000000000000000] + db 0x48, 0x67, 0xA1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ; mov rax, [0x00000000] + + db 0x66, 0xE3, 0x00 ; jrcxz $+3 + db 0x48, 0xE3, 0x00 ; jrcxz $+3 + db 0x67, 0xE3, 0x00 ; jecxz $+3 + + db 0x67, 0xA4 ; movsb + db 0x66, 0xA4 ; movsb + + ; Rep, repz, repnz. + db 0xF3, 0xAA ; rep stosb + db 0xF2, 0xAA ; repnz stosb + db 0xF3, 0xAE ; repz scasb + db 0xF2, 0xAE ; repnz scasb + db 0xF3, 0xF2, 0xAE ; repnz scasb + db 0xF2, 0xF3, 0xAE ; repz scasb + + ; Extension prefixes. + db 0x0F, 0x10, 0xC0 ; movups xmm0, xmm0 + db 0x66, 0x0F, 0x10, 0xC0 ; movupd xmm0, xmm0 + db 0x66, 0x66, 0x0F, 0x10, 0xC0 ; movupd xmm0, xmm0 + db 0xF3, 0x0F, 0x10, 0xC0 ; movss xmm0, xmm0 + db 0xF3, 0xF3, 0x0F, 0x10, 0xC0 ; movss xmm0, xmm0 + db 0xF2, 0x0F, 0x10, 0xC0 ; movsd xmm0, xmm0 + db 0xF2, 0xF2, 0x0F, 0x10, 0xC0 ; movsd xmm0, xmm0 + + db 0x66, 0xF2, 0xF3, 0x0F, 0x10, 0xC0 ; movss xmm0, xmm0 + db 0x66, 0xF3, 0xF2, 0x0F, 0x10, 0xC0 ; movsd xmm0, xmm0 + db 0xF2, 0xF3, 0x66, 0x0F, 0x10, 0xC0 ; movss xmm0, xmm0 + db 0xF2, 0x66, 0xF3, 0x0F, 0x10, 0xC0 ; movss xmm0, xmm0 + db 0xF3, 0xF2, 0x66, 0x0F, 0x10, 0xC0 ; movsd xmm0, xmm0 + db 0xF3, 0x66, 0xF2, 0x0F, 0x10, 0xC0 ; movsd xmm0, xmm0 + + ; Lock, xacquire, xrelease. + db 0xF3, 0x31, 0x00 ; xor [rax], eax + db 0xF2, 0x31, 0x00 ; xor [rax], eax + db 0xF0, 0x31, 0x00 ; lock xor [rax], eax + db 0xF0, 0x48, 0x31, 0x00 ; lock xor [rax], rax + db 0x48, 0xF0, 0x31, 0x00 ; lock xor [rax], eax + db 0xF2, 0xF0, 0x31, 0x00 ; lock xacquire xor [rax], eax + db 0xF0, 0xF2, 0x31, 0x00 ; lock xacquire xor [rax], eax + db 0xF3, 0xF0, 0x31, 0x00 ; lock xrelease xor [rax], eax + db 0xF0, 0xF3, 0x31, 0x00 ; lock xrelease xor [rax], eax + db 0xF2, 0xF3, 0xF0, 0x31, 0x00 ; lock xrelease xor [rax], eax + db 0xF3, 0xF2, 0xF0, 0x31, 0x00 ; lock xacquire xor [rax], eax + + ; Segment prefixes. + db 0x26, 0x31, 0x00 ; xor [rax], eax + db 0x2E, 0X31, 0x00 ; xor [rax], eax + db 0x36, 0X31, 0x00 ; xor [rax], eax + db 0x3E, 0X31, 0x00 ; xor [rax], eax + db 0x64, 0X31, 0x00 ; xor fs:[rax], eax + db 0x65, 0x31, 0x00 ; xor gs:[rax], eax + db 0x64, 0x65, 0x31, 0x00 ; xor gs:[rax], eax + db 0x65, 0x64, 0x31, 0x00 ; xor fs:[rax], eax + + ; Branch hints. + db 0x2E, 0x72, 0x00 ; bhnt jc $+3 + db 0x3E, 0x72, 0x00 ; bht jc $+3 + + ; Bound prefix. + db 0xF2, 0xE8, 0x00, 0x00, 0x00, 0x00 ; bnd call $+6 \ No newline at end of file diff --git a/bddisasm_test/basic/prefixes_64.result b/bddisasm_test/basic/prefixes_64.result new file mode 100644 index 0000000..ac4554a --- /dev/null +++ b/bddisasm_test/basic/prefixes_64.result @@ -0,0 +1,1282 @@ +0000000000000000 33c0 XOR eax, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000002 f333c0 XOR eax, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000005 f233c0 XOR eax, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000008 6733c0 XOR eax, eax + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000000B 6633c0 XOR ax, ax + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000000E 4833c0 XOR rax, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000011 664833c0 XOR rax, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000015 486633c0 XOR ax, ax + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000019 48f333c0 XOR eax, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000001D f34833c0 XOR rax, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000021 484833c0 XOR rax, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000025 484033c0 XOR eax, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000029 4a33c0 XOR rax, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000002C 3100 XOR dword ptr [rax], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000002E 673100 XOR dword ptr [eax], eax + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000031 66673100 XOR word ptr [eax], ax + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000035 48673100 XOR dword ptr [eax], eax + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000039 67483100 XOR qword ptr [eax], rax + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000003D a10000000000000000 MOV eax, dword ptr [0x0] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: D, + Segment: 3, Displacement: 0x0000000000000000, + +0000000000000046 67a100000000 MOV eax, dword ptr [0x0] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: D, + Segment: 3, Displacement: 0x0000000000000000, + +000000000000004C 66a10000000000000000 MOV ax, word ptr [0x0] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: D, + Segment: 3, Displacement: 0x0000000000000000, + +0000000000000056 6667a100000000 MOV ax, word ptr [0x0] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: D, + Segment: 3, Displacement: 0x0000000000000000, + +000000000000005D 0000 ADD byte ptr [rax], al + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000005F 0000 ADD byte ptr [rax], al + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000061 48a10000000000000000 MOV rax, qword ptr [0x0] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: D, + Segment: 3, Displacement: 0x0000000000000000, + +000000000000006B 4867a100000000 MOV eax, dword ptr [0x0] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: D, + Segment: 3, Displacement: 0x0000000000000000, + +0000000000000072 0000 ADD byte ptr [rax], al + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000074 0000 ADD byte ptr [rax], al + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000076 66e300 JRCXZ 0x79 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 8, RawSize: 1, Encoding: D + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: IP, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000079 48e300 JRCXZ 0x7c + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 8, RawSize: 1, Encoding: D + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: IP, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000007C 67e300 JECXZ 0x7f + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 8, RawSize: 1, Encoding: D + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: IP, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000007F 67a4 MOVSB + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + DF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: yes, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: S, String: yes, + Segment: 3, Base: 6, + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 6, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + Operand: 4, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000081 66a4 MOVSB + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + DF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: yes, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: S, String: yes, + Segment: 3, Base: 6, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 6, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 4, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000083 f3aa REP STOSB + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + DF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: yes, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: --, Type: Memory, Size: 1, RawSize: 1, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 4, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000085 f2aa REPNZ STOSB + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + DF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: yes, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: --, Type: Memory, Size: 1, RawSize: 1, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 4, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000087 f3ae REPZ SCASB + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: tm, SF: m, DF: t, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: yes, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: --, Type: Memory, Size: 1, RawSize: 1, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 4, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000089 f2ae REPNZ SCASB + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: tm, SF: m, DF: t, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: yes, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: --, Type: Memory, Size: 1, RawSize: 1, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 4, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000008B f3f2ae REPNZ SCASB + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: tm, SF: m, DF: t, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: yes, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: --, Type: Memory, Size: 1, RawSize: 1, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 4, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000008E f2f3ae REPZ SCASB + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: tm, SF: m, DF: t, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: yes, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: --, Type: Memory, Size: 1, RawSize: 1, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 4, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000091 0f10c0 MOVUPS xmm0, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 25 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000094 660f10c0 MOVUPD xmm0, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000098 66660f10c0 MOVUPD xmm0, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000009D f30f10c0 MOVSS xmm0, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 25 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000000A1 f3f30f10c0 MOVSS xmm0, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 25 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000000A6 f20f10c0 MOVSD xmm0, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000000AA f2f20f10c0 MOVSD xmm0, xmm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000000AF 66f2f30f10c0 MOVSS xmm0, xmm0 + DSIZE: 16, ASIZE: 64, VLEN: 128 + ISA Set: SSE, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 25 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000000B5 66f3f20f10c0 MOVSD xmm0, xmm0 + DSIZE: 16, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000000BB f2f3660f10c0 MOVSS xmm0, xmm0 + DSIZE: 16, ASIZE: 64, VLEN: 128 + ISA Set: SSE, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 25 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000000C1 f266f30f10c0 MOVSS xmm0, xmm0 + DSIZE: 16, ASIZE: 64, VLEN: 128 + ISA Set: SSE, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 25 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000000C7 f3f2660f10c0 MOVSD xmm0, xmm0 + DSIZE: 16, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000000CD f366f20f10c0 MOVSD xmm0, xmm0 + DSIZE: 16, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000000D3 f33100 XOR dword ptr [rax], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000D6 f23100 XOR dword ptr [rax], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000D9 f03100 LOCK XOR dword ptr [rax], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000DC f0483100 LOCK XOR qword ptr [rax], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000E0 48f03100 LOCK XOR dword ptr [rax], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000E4 f2f03100 XACQUIRE LOCK XOR dword ptr [rax], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000E8 f0f23100 XACQUIRE LOCK XOR dword ptr [rax], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000EC f3f03100 XRELEASE LOCK XOR dword ptr [rax], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000F0 f0f33100 XRELEASE LOCK XOR dword ptr [rax], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000F4 f2f3f03100 XRELEASE LOCK XOR dword ptr [rax], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000F9 f3f2f03100 XACQUIRE LOCK XOR dword ptr [rax], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000FE 263100 XOR dword ptr [rax], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000101 2e3100 XOR dword ptr [rax], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000104 363100 XOR dword ptr [rax], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000107 3e3100 XOR dword ptr [rax], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000010A 643100 XOR dword ptr fs:[rax], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 4, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000010D 653100 XOR dword ptr gs:[rax], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 5, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000110 64653100 XOR dword ptr gs:[rax], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 5, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000114 65643100 XOR dword ptr fs:[rax], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 4, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000118 2e7200 BHNT JC 0x11b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: yes, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 8, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: IP, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000011B 3e7200 BHT JC 0x11e + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: yes, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 8, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: IP, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000011E f2e800000000 BND CALL 0x124 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: yes, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 8, RawSize: 4, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: IP, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 3, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Shadow Stack: yes, + + diff --git a/bddisasm_test/basic/sha_64 b/bddisasm_test/basic/sha_64 new file mode 100644 index 0000000..056916b --- /dev/null +++ b/bddisasm_test/basic/sha_64 @@ -0,0 +1,2 @@ +A8A8A8A8A8A8A: +8;8;8;8;8;8;:; diff --git a/bddisasm_test/basic/sha_64.asm b/bddisasm_test/basic/sha_64.asm new file mode 100644 index 0000000..1b36576 --- /dev/null +++ b/bddisasm_test/basic/sha_64.asm @@ -0,0 +1,17 @@ + bits 64 + + sha1nexte xmm7,xmm13 + sha1msg1 xmm7,xmm13 + sha1msg2 xmm7,xmm13 + sha256rnds2 xmm7,xmm13 + sha256msg1 xmm7,xmm13 + sha256msg2 xmm7,xmm13 + sha1rnds4 xmm7,xmm13,10 + + sha1nexte xmm7,[rbx] + sha1msg1 xmm7,[rbx] + sha1msg2 xmm7,[rbx] + sha256rnds2 xmm7,[rbx] + sha256msg1 xmm7,[rbx] + sha256msg2 xmm7,[rbx] + sha1rnds4 xmm7,[rbx],10 \ No newline at end of file diff --git a/bddisasm_test/basic/sha_64.result b/bddisasm_test/basic/sha_64.result new file mode 100644 index 0000000..2cceb83 --- /dev/null +++ b/bddisasm_test/basic/sha_64.result @@ -0,0 +1,235 @@ +0000000000000000 410f38c8fd SHA1NEXTE xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SHA, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 29 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000005 410f38c9fd SHA1MSG1 xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SHA, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 29 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000000A 410f38cafd SHA1MSG2 xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SHA, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 29 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000000F 410f38cbfd SHA256RNDS2 xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SHA, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 29 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000014 410f38ccfd SHA256MSG1 xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SHA, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 29 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000019 410f38cdfd SHA256MSG2 xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SHA, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 29 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000001E 410f3accfd0a SHA1RNDS4 xmm7, xmm13, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SHA, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 29 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000024 0f38c83b SHA1NEXTE xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SHA, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 29 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000028 0f38c93b SHA1MSG1 xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SHA, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 29 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000002C 0f38ca3b SHA1MSG2 xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SHA, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 29 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000030 0f38cb3b SHA256RNDS2 xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SHA, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 29 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000034 0f38cc3b SHA256MSG1 xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SHA, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 29 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000038 0f38cd3b SHA256MSG2 xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SHA, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 29 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000003C 0f3acc3b0a SHA1RNDS4 xmm7, xmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SHA, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 29 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + diff --git a/bddisasm_test/basic/snp_64 b/bddisasm_test/basic/snp_64 new file mode 100644 index 0000000..a23eb11 --- /dev/null +++ b/bddisasm_test/basic/snp_64 @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/bddisasm_test/basic/snp_64.asm b/bddisasm_test/basic/snp_64.asm new file mode 100644 index 0000000..e2608e0 --- /dev/null +++ b/bddisasm_test/basic/snp_64.asm @@ -0,0 +1,6 @@ + bits 64 + + rmpadjust + rmpupdate + psmash + pvalidate \ No newline at end of file diff --git a/bddisasm_test/basic/snp_64.result b/bddisasm_test/basic/snp_64.result new file mode 100644 index 0000000..02c6870 --- /dev/null +++ b/bddisasm_test/basic/snp_64.result @@ -0,0 +1,73 @@ +0000000000000000 f30f01fe RMPADJUST + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SNP, Ins cat: SYSTEM, CET tracked: no + CPUID leaf: 0x8000001f, reg: eax, bit: 4 + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000004 f20f01fe RMPUPDATE + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SNP, Ins cat: SYSTEM, CET tracked: no + CPUID leaf: 0x8000001f, reg: eax, bit: 4 + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000008 f30f01ff PSMASH + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SNP, Ins cat: SYSTEM, CET tracked: no + CPUID leaf: 0x8000001f, reg: eax, bit: 4 + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000000C f20f01ff PVALIDATE + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SNP, Ins cat: SYSTEM, CET tracked: no + CPUID leaf: 0x8000001f, reg: eax, bit: 4 + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + diff --git a/bddisasm_test/basic/stack_16 b/bddisasm_test/basic/stack_16 new file mode 100644 index 0000000000000000000000000000000000000000..0eb3b93350cac5f98de256879bf8c7f1cf18bcdd GIT binary patch literal 65 zcmWHDNDD}d$f{4v_+QV!@ZY?jJ^jCNdOvg8fAh3{_B0?T4ahqoz@TuFja^P&Oq_oK T|3dy1{3{a@=gdu;lQtIsKR+0& literal 0 HcmV?d00001 diff --git a/bddisasm_test/basic/stack_16.asm b/bddisasm_test/basic/stack_16.asm new file mode 100644 index 0000000..660db66 --- /dev/null +++ b/bddisasm_test/basic/stack_16.asm @@ -0,0 +1,39 @@ + bits 16 + + push ax + pop ax + push eax + pop eax + + push word 0x7F + push dword 0x7FFF + + push word [bx] + pop word [bx] + push word [ebx] + pop word [ebx] + push dword [bx] + pop dword [bx] + push dword [ebx] + pop dword [ebx] + + enter 0x10, 0x20 + leave + + push es + pop es + push ds + pop ds + push ss + pop ss + push fs + pop fs + push gs + pop gs + + pusha + popa + pushfw + popfw + pushfd + popfd \ No newline at end of file diff --git a/bddisasm_test/basic/stack_16.result b/bddisasm_test/basic/stack_16.result new file mode 100644 index 0000000..c65fbae --- /dev/null +++ b/bddisasm_test/basic/stack_16.result @@ -0,0 +1,501 @@ +0000000000000000 50 PUSH ax + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: O, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000001 58 POP ax + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: O, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000002 6650 PUSH eax + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: O, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000004 6658 POP eax + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: O, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000006 6a7f PUSH 0x7f + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Immediate, Size: 2, RawSize: 1, Encoding: I + Operand: 1, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000008 6668ff7f0000 PUSH 0x00007fff + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 1, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +000000000000000E ff37 PUSH word ptr [bx] + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000010 8f07 POP word ptr [bx] + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000012 67ff33 PUSH word ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000015 678f03 POP word ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000018 66ff37 PUSH dword ptr [bx] + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +000000000000001B 668f07 POP dword ptr [bx] + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +000000000000001E 6667ff33 PUSH dword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000022 66678f03 POP dword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000026 c8100020 ENTER 0x0010, 0x20 + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I186, Ins cat: MISC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 5, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 4, RegCount: 1 + Operand: 4, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +000000000000002A c9 LEAVE + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I186, Ins cat: MISC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 5, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 5, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 4, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +000000000000002B 06 PUSH es + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +000000000000002C 07 POP es + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +000000000000002D 1e PUSH ds + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 3, RegCount: 1 + Operand: 1, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +000000000000002E 1f POP ds + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +000000000000002F 16 PUSH ss + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 1, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000030 17 POP ss + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000031 0fa0 PUSH fs + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 4, RegCount: 1 + Operand: 1, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000033 0fa1 POP fs + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 4, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000035 0fa8 PUSH gs + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 5, RegCount: 1 + Operand: 1, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000037 0fa9 POP gs + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Segment, RegSize: 2, RegId: 5, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000039 60 PUSHA + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I386, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +000000000000003A 61 POPA + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I386, Ins cat: POP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +000000000000003B 9c PUSHFW + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +000000000000003C 9d POPFW + DSIZE: 16, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +000000000000003D 669c PUSHFD + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +000000000000003F 669d POPFD + DSIZE: 32, ASIZE: 16, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + diff --git a/bddisasm_test/basic/stack_32 b/bddisasm_test/basic/stack_32 new file mode 100644 index 0000000000000000000000000000000000000000..d0217b34cca3e11b96d5b7afb30665e9df47a802 GIT binary patch literal 67 zcmYcbNQ(%FNXx3v_+QV!ke2@6JT1MSJ?+17T0b+817!aJy`TBNaX&MV31poRU{E;8zkq)s P{|f$-!%&Y24UX$~7l literal 0 HcmV?d00001 diff --git a/bddisasm_test/basic/stack_64.asm b/bddisasm_test/basic/stack_64.asm new file mode 100644 index 0000000..b7d9a6e --- /dev/null +++ b/bddisasm_test/basic/stack_64.asm @@ -0,0 +1,32 @@ + bits 64 + + push ax + pop ax + push rax + pop rax + + push word 0x7F + push dword 0x7FFF + push qword 0x7FFFFFFF + + push word [rbx] + pop word [rbx] + push word [ebx] + pop word [ebx] + push qword [rbx] + pop qword [rbx] + push qword [ebx] + pop qword [ebx] + + enter 0x10, 0x20 + leave + + push fs + pop fs + push gs + pop gs + + pushfw + popfw + pushfq + popfq \ No newline at end of file diff --git a/bddisasm_test/basic/stack_64.result b/bddisasm_test/basic/stack_64.result new file mode 100644 index 0000000..5a08930 --- /dev/null +++ b/bddisasm_test/basic/stack_64.result @@ -0,0 +1,396 @@ +0000000000000000 6650 PUSH ax + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: O, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000002 6658 POP ax + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: O, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000004 50 PUSH rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: O, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000005 58 POP rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: O, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000006 666a7f PUSH 0x7f + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Immediate, Size: 2, RawSize: 1, Encoding: I + Operand: 1, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000009 68ff7f0000 PUSH 0x00007fff + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Immediate, Size: 8, RawSize: 4, Encoding: I + Operand: 1, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +000000000000000E 68ffffff7f PUSH 0x7fffffff + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Immediate, Size: 8, RawSize: 4, Encoding: I + Operand: 1, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000013 66ff33 PUSH word ptr [rbx] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000016 668f03 POP word ptr [rbx] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000019 6667ff33 PUSH word ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +000000000000001D 66678f03 POP word ptr [ebx] + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000021 ff33 PUSH qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000023 8f03 POP qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000025 67ff33 PUSH qword ptr [ebx] + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000028 678f03 POP qword ptr [ebx] + DSIZE: 64, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +000000000000002B c8100020 ENTER 0x0010, 0x20 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I186, Ins cat: MISC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 5, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 4, RegCount: 1 + Operand: 4, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +000000000000002F c9 LEAVE + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I186, Ins cat: MISC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 4, RegCount: 1 + Operand: 3, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000030 0fa0 PUSH fs + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Segment, RegSize: 8, RegId: 4, RegCount: 1 + Operand: 1, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000032 0fa1 POP fs + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Segment, RegSize: 8, RegId: 4, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000034 0fa8 PUSH gs + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Segment, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 1, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000036 0fa9 POP gs + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Segment, RegSize: 8, RegId: 5, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000038 669c PUSHFW + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +000000000000003A 669d POPFW + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +000000000000003C 9c PUSHFQ + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +000000000000003D 9d POPFQ + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + diff --git a/bddisasm_test/basic/svm_64 b/bddisasm_test/basic/svm_64 new file mode 100644 index 0000000..efa0607 --- /dev/null +++ b/bddisasm_test/basic/svm_64 @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/bddisasm_test/basic/svm_64.asm b/bddisasm_test/basic/svm_64.asm new file mode 100644 index 0000000..705cbf2 --- /dev/null +++ b/bddisasm_test/basic/svm_64.asm @@ -0,0 +1,11 @@ + bits 64 + + vmrun + vmmcall + db 0xF3, 0x0F, 0x01, 0xD9 ; vmgexit + vmload + vmsave + stgi + clgi + skinit + invlpga \ No newline at end of file diff --git a/bddisasm_test/basic/svm_64.result b/bddisasm_test/basic/svm_64.result new file mode 100644 index 0000000..85ba5b4 --- /dev/null +++ b/bddisasm_test/basic/svm_64.result @@ -0,0 +1,122 @@ +0000000000000000 0f01d8 VMRUN + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SVM, Ins cat: SYSTEM, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 2 + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: no, V8086: no, Prot: yes, Compat: no, Long: yes + SMM: no, SGX: no, TSX: no, VMXRoot: yes, VMXNonRoot: no + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000003 0f01d9 VMMCALL + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SVM, Ins cat: SYSTEM, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000006 f30f01d9 VMGEXIT + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SVM, Ins cat: SYSTEM, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000000A 0f01da VMLOAD + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SVM, Ins cat: SYSTEM, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 2 + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: no, V8086: no, Prot: yes, Compat: no, Long: yes + SMM: no, SGX: no, TSX: no, VMXRoot: yes, VMXNonRoot: no + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000000D 0f01db VMSAVE + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SVM, Ins cat: SYSTEM, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 2 + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: no, V8086: no, Prot: yes, Compat: no, Long: yes + SMM: no, SGX: no, TSX: no, VMXRoot: yes, VMXNonRoot: no + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000010 0f01dc STGI + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SVM, Ins cat: SYSTEM, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 2 + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: no, V8086: no, Prot: yes, Compat: no, Long: yes + SMM: no, SGX: no, TSX: no, VMXRoot: yes, VMXNonRoot: no + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000013 0f01dd CLGI + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SVM, Ins cat: SYSTEM, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 2 + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: no, V8086: no, Prot: yes, Compat: no, Long: yes + SMM: no, SGX: no, TSX: no, VMXRoot: yes, VMXNonRoot: no + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000016 0f01de SKINIT + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SVM, Ins cat: SYSTEM, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 2 + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: no, V8086: no, Prot: yes, Compat: no, Long: yes + SMM: no, SGX: no, TSX: no, VMXRoot: yes, VMXNonRoot: no + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000019 0f01df INVLPGA + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SVM, Ins cat: SYSTEM, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 2 + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: no, V8086: no, Prot: yes, Compat: no, Long: yes + SMM: no, SGX: no, TSX: no, VMXRoot: yes, VMXNonRoot: no + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + diff --git a/bddisasm_test/basic/system_16 b/bddisasm_test/basic/system_16 new file mode 100644 index 0000000000000000000000000000000000000000..0ba83111750fdfcd83f16d59d3f948abefb65a5a GIT binary patch literal 115 zcmWN42hYd|a=-l3yQ(_El+>IJ+?4&uo&D+IcE00~{4N;dQGFej#VXKo8q zAtZbvWPB!6d_^}jq5(PV6S0hqnB&gEiYj(s1()bf^o!_=w#fE;7M7q0Z^_ydg_ B8?*ob literal 0 HcmV?d00001 diff --git a/bddisasm_test/basic/system_32.asm b/bddisasm_test/basic/system_32.asm new file mode 100644 index 0000000..cc558b7 --- /dev/null +++ b/bddisasm_test/basic/system_32.asm @@ -0,0 +1,51 @@ + bits 32 + + ; System instructions + mov cr0, eax + mov eax, cr0 + mov ecx, cr2 + mov cr2, ecx + mov cr4, esi + mov esi, cr4 + + mov dr0, eax + mov eax, dr0 + mov dr1, esi + mov esi, dr1 + mov dr7, ecx + mov ecx, dr7 + + lidt [ebx] + lgdt [ebx] + sidt [ebx] + sgdt [ebx] + ltr ax + str si + lldt [ebx] + sldt [ebx] + + rdmsr + wrmsr + rdtsc + rdtscp + + verw ax + verr si + + lsl eax, eax + lar esi, edi + + lmsw cx + smsw sp + + invlpg [eax] + invpcid eax, [ebp] + + clac + stac + + clts + invd + wbinvd + + db 0x0F, 0x01, 0xE8 ; serialize \ No newline at end of file diff --git a/bddisasm_test/basic/system_32.result b/bddisasm_test/basic/system_32.result new file mode 100644 index 0000000..3bb3f9d --- /dev/null +++ b/bddisasm_test/basic/system_32.result @@ -0,0 +1,559 @@ +0000000000000000 0f22c0 MOV cr0, eax + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Control, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000003 0f20c0 MOV eax, cr0 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Control, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000006 0f20d1 MOV ecx, cr2 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Control, RegSize: 4, RegId: 2, RegCount: 1 + +0000000000000009 0f22d1 MOV cr2, ecx + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Control, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + +000000000000000C 0f22e6 MOV cr4, esi + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Control, RegSize: 4, RegId: 4, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 6, RegCount: 1 + +000000000000000F 0f20e6 MOV esi, cr4 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 6, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Control, RegSize: 4, RegId: 4, RegCount: 1 + +0000000000000012 0f23c0 MOV dr0, eax + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Debug, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000015 0f21c0 MOV eax, dr0 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Debug, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000018 0f23ce MOV dr1, esi + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Debug, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 6, RegCount: 1 + +000000000000001B 0f21ce MOV esi, dr1 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 6, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Debug, RegSize: 4, RegId: 1, RegCount: 1 + +000000000000001E 0f23f9 MOV dr7, ecx + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Debug, RegSize: 4, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + +0000000000000021 0f21f9 MOV ecx, dr7 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Debug, RegSize: 4, RegId: 7, RegCount: 1 + +0000000000000024 0f011b LIDT fword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I286REAL, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 6, RawSize: 6, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 6, RawSize: 6, Encoding: S, RegType: System, RegSize: 6, RegId: 1, RegCount: 1 + +0000000000000027 0f0113 LGDT fword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I286REAL, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 6, RawSize: 6, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 6, RawSize: 6, Encoding: S, RegType: System, RegSize: 6, RegId: 0, RegCount: 1 + +000000000000002A 0f010b SIDT fword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I286REAL, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 6, RawSize: 6, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 6, RawSize: 6, Encoding: S, RegType: System, RegSize: 6, RegId: 1, RegCount: 1 + +000000000000002D 0f0103 SGDT fword ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I286REAL, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 6, RawSize: 6, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 6, RawSize: 6, Encoding: S, RegType: System, RegSize: 6, RegId: 0, RegCount: 1 + +0000000000000030 0f00d8 LTR ax + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I286PROT, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: System, RegSize: 2, RegId: 3, RegCount: 1 + +0000000000000033 660f00ce STR si + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I286PROT, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 6, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: System, RegSize: 2, RegId: 3, RegCount: 1 + +0000000000000037 0f0013 LLDT word ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I286PROT, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: System, RegSize: 2, RegId: 2, RegCount: 1 + +000000000000003A 0f0003 SLDT word ptr [ebx] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I286PROT, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: System, RegSize: 2, RegId: 2, RegCount: 1 + +000000000000003D 0f32 RDMSR + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: PENTIUMREAL, Ins cat: SYSTEM, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 5 + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: E, RegType: Model Specific, RegSize: 8, RegId: -1, RegCount: 1 + +000000000000003F 0f30 WRMSR + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: PENTIUMREAL, Ins cat: SYSTEM, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 5 + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: E, RegType: Model Specific, RegSize: 8, RegId: -1, RegCount: 1 + +0000000000000041 0f31 RDTSC + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: PENTIUMREAL, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: 16, RegCount: 1 + +0000000000000043 0f01f9 RDTSCP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: RDTSCP, Ins cat: SYSTEM, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 27 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: 16, RegCount: 1 + Operand: 4, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: -1073741565, RegCount: 1 + +0000000000000046 0f00e8 VERW ax + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I286PROT, Ins cat: SYSTEM, CET tracked: no + FLAGS access + ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000049 0f00e6 VERR si + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I286PROT, Ins cat: SYSTEM, CET tracked: no + FLAGS access + ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 6, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000004C 0f03c0 LSL eax, eax + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I286PROT, Ins cat: SYSTEM, CET tracked: no + FLAGS access + ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000004F 0f02f7 LAR esi, edi + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I286PROT, Ins cat: SYSTEM, CET tracked: no + FLAGS access + ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: --, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 6, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000052 0f01f1 LMSW cx + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I286REAL, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Control, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000055 660f01e4 SMSW sp + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I286REAL, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 4, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Control, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000059 0f0138 INVLPG byte ptr [eax] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I486REAL, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, Address Generator: yes, + Base: 0, + +000000000000005C 660f38824500 INVPCID eax, xmmword ptr [ebp+0x0] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: INVPCID, Ins cat: MISC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 10 + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 2, Base: 5, Displacement: 0x0000000000000000, + +0000000000000062 0f01ca CLAC + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: SMAP, Ins cat: SMAP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 20 + FLAGS access + AC: 0, + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000065 0f01cb STAC + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: SMAP, Ins cat: SMAP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 20 + FLAGS access + AC: 1, + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000068 0f06 CLTS + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I286REAL, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Control, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000006A 0f08 INVD + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I486REAL, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000006C 0f09 WBINVD + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I486REAL, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000006E 0f01e8 SERIALIZE + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: SERIALIZE, Ins cat: MISC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: edx, bit: 14 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + diff --git a/bddisasm_test/basic/system_64 b/bddisasm_test/basic/system_64 new file mode 100644 index 0000000000000000000000000000000000000000..cd6788eed273735264340be451d680d4fe3f36f8 GIT binary patch literal 135 zcmWm6Ar8VY07l{dG$9bg6O)*=y8xhOE1GbU9)y!sgJ|aPkZcNqK-5u^r#|uUnZ7mQ zr+}XW{T%T*{&mQ>92iQ#6^4qdXpcIyLl$#S0aGv?#&Y7o5mn66^nq=Y)fasddZIC% S886YG7kZ;By0K=%7A-%BIU+6q literal 0 HcmV?d00001 diff --git a/bddisasm_test/basic/system_64.asm b/bddisasm_test/basic/system_64.asm new file mode 100644 index 0000000..698b891 --- /dev/null +++ b/bddisasm_test/basic/system_64.asm @@ -0,0 +1,56 @@ + bits 64 + + ; System instructions + mov cr0, rax + mov rax, cr0 + mov rcx, cr2 + mov cr2, rcx + mov cr4, r15 + mov r15, cr4 + mov cr8, r8 + mov r8, cr8 + + mov dr0, rax + mov rax, dr0 + mov dr1, r15 + mov r15, dr1 + mov dr7, rcx + mov rcx, dr7 + + lidt [rbx] + lgdt [rbx] + sidt [rbx] + sgdt [rbx] + ltr ax + str r15w + lldt [rbx] + sldt [rbx] + + rdmsr + wrmsr + rdtsc + rdtscp + + verw ax + verr r11w + + lsl eax, eax + lar r14d, r13d + + lmsw cx + smsw sp + + invlpg [rax] + invpcid rax, [rbp] + + rdpkru + wrpkru + + clac + stac + + clts + invd + wbinvd + + db 0x0F, 0x01, 0xE8 ; serialize \ No newline at end of file diff --git a/bddisasm_test/basic/system_64.result b/bddisasm_test/basic/system_64.result new file mode 100644 index 0000000..d3dc6ee --- /dev/null +++ b/bddisasm_test/basic/system_64.result @@ -0,0 +1,621 @@ +0000000000000000 0f22c0 MOV cr0, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Control, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000003 0f20c0 MOV rax, cr0 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Control, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000006 0f20d1 MOV rcx, cr2 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Control, RegSize: 8, RegId: 2, RegCount: 1 + +0000000000000009 0f22d1 MOV cr2, rcx + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Control, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + +000000000000000C 410f22e7 MOV cr4, r15 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Control, RegSize: 8, RegId: 4, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 15, RegCount: 1 + +0000000000000010 410f20e7 MOV r15, cr4 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 15, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Control, RegSize: 8, RegId: 4, RegCount: 1 + +0000000000000014 450f22c0 MOV cr8, r8 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Control, RegSize: 8, RegId: 8, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 8, RegCount: 1 + +0000000000000018 450f20c0 MOV r8, cr8 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 8, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Control, RegSize: 8, RegId: 8, RegCount: 1 + +000000000000001C 0f23c0 MOV dr0, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Debug, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000001F 0f21c0 MOV rax, dr0 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Debug, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000022 410f23cf MOV dr1, r15 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Debug, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 15, RegCount: 1 + +0000000000000026 410f21cf MOV r15, dr1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 15, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Debug, RegSize: 8, RegId: 1, RegCount: 1 + +000000000000002A 0f23f9 MOV dr7, rcx + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Debug, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + +000000000000002D 0f21f9 MOV rcx, dr7 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Debug, RegSize: 8, RegId: 7, RegCount: 1 + +0000000000000030 0f011b LIDT tbyte ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I286REAL, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 10, RawSize: 10, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 10, RawSize: 10, Encoding: S, RegType: System, RegSize: 10, RegId: 1, RegCount: 1 + +0000000000000033 0f0113 LGDT tbyte ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I286REAL, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 10, RawSize: 10, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 10, RawSize: 10, Encoding: S, RegType: System, RegSize: 10, RegId: 0, RegCount: 1 + +0000000000000036 0f010b SIDT tbyte ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I286REAL, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 10, RawSize: 10, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 10, RawSize: 10, Encoding: S, RegType: System, RegSize: 10, RegId: 1, RegCount: 1 + +0000000000000039 0f0103 SGDT tbyte ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I286REAL, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 10, RawSize: 10, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 10, RawSize: 10, Encoding: S, RegType: System, RegSize: 10, RegId: 0, RegCount: 1 + +000000000000003C 0f00d8 LTR ax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I286PROT, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: System, RegSize: 2, RegId: 3, RegCount: 1 + +000000000000003F 66410f00cf STR r15w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I286PROT, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 15, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: System, RegSize: 2, RegId: 3, RegCount: 1 + +0000000000000044 0f0013 LLDT word ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I286PROT, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: System, RegSize: 2, RegId: 2, RegCount: 1 + +0000000000000047 0f0003 SLDT word ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I286PROT, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: System, RegSize: 2, RegId: 2, RegCount: 1 + +000000000000004A 0f32 RDMSR + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: PENTIUMREAL, Ins cat: SYSTEM, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 5 + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: E, RegType: Model Specific, RegSize: 8, RegId: -1, RegCount: 1 + +000000000000004C 0f30 WRMSR + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: PENTIUMREAL, Ins cat: SYSTEM, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 5 + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: E, RegType: Model Specific, RegSize: 8, RegId: -1, RegCount: 1 + +000000000000004E 0f31 RDTSC + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: PENTIUMREAL, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: 16, RegCount: 1 + +0000000000000050 0f01f9 RDTSCP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: RDTSCP, Ins cat: SYSTEM, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 27 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: 16, RegCount: 1 + Operand: 4, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: -1073741565, RegCount: 1 + +0000000000000053 0f00e8 VERW ax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I286PROT, Ins cat: SYSTEM, CET tracked: no + FLAGS access + ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000056 410f00e3 VERR r11w + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I286PROT, Ins cat: SYSTEM, CET tracked: no + FLAGS access + ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 11, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000005A 0f03c0 LSL eax, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I286PROT, Ins cat: SYSTEM, CET tracked: no + FLAGS access + ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000005D 450f02f5 LAR r14d, r13d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I286PROT, Ins cat: SYSTEM, CET tracked: no + FLAGS access + ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: --, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 14, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 13, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000061 0f01f1 LMSW cx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I286REAL, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Control, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000064 660f01e4 SMSW sp + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: I286REAL, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 4, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Control, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000068 0f0138 INVLPG byte ptr [rax] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I486REAL, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, Address Generator: yes, + Base: 0, + +000000000000006B 66480f38824500 INVPCID rax, xmmword ptr [rbp+0x0] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: INVPCID, Ins cat: MISC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 10 + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 2, Base: 5, Displacement: 0x0000000000000000, + +0000000000000072 0f01ee RDPKRU + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: PKU, Ins cat: MISC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: PKRU, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000075 0f01ef WRPKRU + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: PKU, Ins cat: MISC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: PKRU, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000078 0f01ca CLAC + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SMAP, Ins cat: SMAP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 20 + FLAGS access + AC: 0, + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000007B 0f01cb STAC + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SMAP, Ins cat: SMAP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 20 + FLAGS access + AC: 1, + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000007E 0f06 CLTS + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I286REAL, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Control, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000080 0f08 INVD + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I486REAL, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000082 0f09 WBINVD + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I486REAL, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000084 0f01e8 SERIALIZE + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SERIALIZE, Ins cat: MISC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: edx, bit: 14 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + diff --git a/bddisasm_test/basic/tsx_64 b/bddisasm_test/basic/tsx_64 new file mode 100644 index 0000000000000000000000000000000000000000..1abc707c7c546cfd4ac646c1134936b73d0a81c9 GIT binary patch literal 23 ecmX^9 literal 0 HcmV?d00001 diff --git a/bddisasm_test/basic/tsx_64.asm b/bddisasm_test/basic/tsx_64.asm new file mode 100644 index 0000000..6443cc3 --- /dev/null +++ b/bddisasm_test/basic/tsx_64.asm @@ -0,0 +1,8 @@ + bits 64 + + xbegin near $ + xtest + xabort 0 + xend + db 0xF2, 0x0F, 0x01, 0xE8 ; XSUSLDTRK + db 0xF2, 0x0F, 0x01, 0xE9 ; XRESLDTRK \ No newline at end of file diff --git a/bddisasm_test/basic/tsx_64.result b/bddisasm_test/basic/tsx_64.result new file mode 100644 index 0000000..c287a43 --- /dev/null +++ b/bddisasm_test/basic/tsx_64.result @@ -0,0 +1,86 @@ +0000000000000000 c7f8faffffff XBEGIN 0x0 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: TSX, Ins cat: COND_BR, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 11 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 4, RawSize: 4, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: --, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000006 0f01d6 XTEST + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: TSX, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 11 + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000009 c6f800 XABORT 0x00 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: TSX, Ins cat: UNCOND_BR, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 11 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: no, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000000C 0f01d5 XEND + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: TSX, Ins cat: COND_BR, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 11 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000000F f20f01e8 XSUSLDTRK + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: TSXLDTRK, Ins cat: MISC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: edx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000013 f20f01e9 XRESLDTRK + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: TSXLDTRK, Ins cat: MISC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: edx, bit: 16 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + diff --git a/bddisasm_test/basic/vmx_64 b/bddisasm_test/basic/vmx_64 new file mode 100644 index 0000000000000000000000000000000000000000..4510dea9c97a4b4a02569cbc61906800240765d6 GIT binary patch literal 59 zcmd;QJjl;@g`e>dKjUG3#v}X{C(`*V)%lNaQDIG0*ppoa z=Q{^3+`*#X75dFU&VU&)qh`#En+Y>%DrU+|n;A1}=FI%J;b6fmx?ssHn-veUnzv`F z-wUcL_-WS7hS@Y*uJg3rmVp3GZl$aJXVphzF zd9l!(#Y8NLWw9dG8dIj4;AWgy7aL+zY^h#u)`@MgBX&hi?1_DGAP&WmI2I@3RGg_< zC(gx%xD;37THJ_RaVP5HUOb3L@uX&*coDDSO}vW_@hJvdY7Bmf)=;!Xdvru+bVYX* oQHq}EjlO6Z%HL=WMO(B-M|4J4bVm`T=!xFw8{#WJimX!cAJi|%ng9R* literal 0 HcmV?d00001 diff --git a/bddisasm_test/simd/mmx_64.asm b/bddisasm_test/simd/mmx_64.asm new file mode 100644 index 0000000..239975b --- /dev/null +++ b/bddisasm_test/simd/mmx_64.asm @@ -0,0 +1,178 @@ + bits 64 + + cvttps2pi mm0,xmm7 + cvttpd2pi mm0,xmm7 + cvtps2pi mm0,xmm7 + cvtpd2pi mm0,xmm7 + punpcklbw mm0,mm7 + punpcklwd mm0,mm7 + punpckldq mm0,mm7 + packsswb mm0,mm7 + pcmpgtb mm0,mm7 + pcmpgtw mm0,mm7 + pcmpgtd mm0,mm7 + packuswb mm0,mm7 + punpckhbw mm0,mm7 + punpckhwd mm0,mm7 + punpckhdq mm0,mm7 + packssdw mm0,mm7 + movd mm0,edx + movq mm0,rdx + movq mm0,mm7 + pshufw mm0,mm7,10 + pcmpeqb mm0,mm7 + pcmpeqw mm0,mm7 + pcmpeqd mm0,mm7 + movq rdx,mm0 + movq mm7,mm0 + pinsrw mm0,esi,10 + pinsrw mm0,[rbx],10 + psrlw mm0,mm7 + psrld mm0,mm7 + psrlq mm0,mm7 + paddq mm0,mm7 + pmullw mm0,mm7 + movdq2q mm0,xmm7 + psubusb mm0,mm7 + psubusw mm0,mm7 + pminub mm0,mm7 + pand mm0,mm7 + paddusb mm0,mm7 + paddusw mm0,mm7 + pmaxub mm0,mm7 + pandn mm0,mm7 + pavgb mm0,mm7 + psraw mm0,mm7 + psrad mm0,mm7 + pavgw mm0,mm7 + pmulhuw mm0,mm7 + pmulhw mm0,mm7 + movntq [rbx],mm0 + psubsb mm0,mm7 + psubsw mm0,mm7 + pminsw mm0,mm7 + por mm0,mm7 + paddsb mm0,mm7 + paddsw mm0,mm7 + pmaxsw mm0,mm7 + pxor mm0,mm7 + psllw mm0,mm7 + pslld mm0,mm7 + psllq mm0,mm7 + pmuludq mm0,mm7 + pmaddwd mm0,mm7 + psadbw mm0,mm7 + maskmovq mm0,mm7 + psubb mm0,mm7 + psubw mm0,mm7 + psubd mm0,mm7 + psubq mm0,mm7 + paddb mm0,mm7 + paddw mm0,mm7 + paddd mm0,mm7 + + cvttps2pi mm0,xmm15 + cvttpd2pi mm0,xmm15 + cvtps2pi mm0,xmm15 + cvtpd2pi mm0,xmm15 + punpcklbw mm0,[rbx] + punpcklwd mm0,[rbx] + punpckldq mm0,[rbx] + packsswb mm0,[rbx] + pcmpgtb mm0,[rbx] + pcmpgtw mm0,[rbx] + pcmpgtd mm0,[rbx] + packuswb mm0,[rbx] + punpckhbw mm0,[rbx] + punpckhwd mm0,[rbx] + punpckhdq mm0,[rbx] + packssdw mm0,[rbx] + movd mm0,[rbx] + movq mm0,[rbx] + movq mm0,[rbx] + pshufw mm0,[rbx],10 + pcmpeqb mm0,[rbx] + pcmpeqw mm0,[rbx] + pcmpeqd mm0,[rbx] + movq [rbx],mm0 + movq [rbx],mm0 + pinsrw mm0,r15d,10 + pinsrw mm0,[rbx],10 + psrlw mm0,[rbx] + psrld mm0,[rbx] + psrlq mm0,[rbx] + paddq mm0,[rbx] + pmullw mm0,[rbx] + movdq2q mm0,xmm15 + psubusb mm0,[rbx] + psubusw mm0,[rbx] + pminub mm0,[rbx] + pand mm0,[rbx] + paddusb mm0,[rbx] + paddusw mm0,[rbx] + pmaxub mm0,[rbx] + pandn mm0,[rbx] + pavgb mm0,[rbx] + psraw mm0,[rbx] + psrad mm0,[rbx] + pavgw mm0,[rbx] + pmulhuw mm0,[rbx] + pmulhw mm0,[rbx] + movntq [rbx],mm0 + psubsb mm0,[rbx] + psubsw mm0,[rbx] + pminsw mm0,[rbx] + por mm0,[rbx] + paddsb mm0,[rbx] + paddsw mm0,[rbx] + pmaxsw mm0,[rbx] + pxor mm0,[rbx] + psllw mm0,[rbx] + pslld mm0,[rbx] + psllq mm0,[rbx] + pmuludq mm0,[rbx] + pmaddwd mm0,[rbx] + psadbw mm0,[rbx] + maskmovq mm0,mm7 + psubb mm0,[rbx] + psubw mm0,[rbx] + psubd mm0,[rbx] + psubq mm0,[rbx] + paddb mm0,[rbx] + paddw mm0,[rbx] + paddd mm0,[rbx] + + pshufb mm3,mm4 + phaddw mm3,mm4 + phaddd mm3,mm4 + phaddsw mm3,mm4 + pmaddubsw mm3,mm4 + phsubw mm3,mm4 + phsubd mm3,mm4 + phsubsw mm3,mm4 + psignb mm3,mm4 + psignw mm3,mm4 + psignd mm3,mm4 + pmulhrsw mm3,mm4 + pabsb mm3,mm4 + pabsw mm3,mm4 + pabsd mm3,mm4 + + pshufb mm7,[rbx] + phaddw mm7,[rbx] + phaddd mm7,[rbx] + phaddsw mm7,[rbx] + pmaddubsw mm7,[rbx] + phsubw mm7,[rbx] + phsubd mm7,[rbx] + phsubsw mm7,[rbx] + psignb mm7,[rbx] + psignw mm7,[rbx] + psignd mm7,[rbx] + pmulhrsw mm7,[rbx] + pabsb mm7,[rbx] + pabsw mm7,[rbx] + pabsd mm7,[rbx] + + palignr mm1,mm2,10 + palignr mm1,[rbx],10 \ No newline at end of file diff --git a/bddisasm_test/simd/mmx_64.result b/bddisasm_test/simd/mmx_64.result new file mode 100644 index 0000000..f259621 --- /dev/null +++ b/bddisasm_test/simd/mmx_64.result @@ -0,0 +1,2678 @@ +0000000000000000 0f2cc7 CVTTPS2PI mm0, xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 25 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +0000000000000003 660f2cc7 CVTTPD2PI mm0, xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +0000000000000007 0f2dc7 CVTPS2PI mm0, xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 25 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +000000000000000A 660f2dc7 CVTPD2PI mm0, xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +000000000000000E 0f60c7 PUNPCKLBW mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +0000000000000011 0f61c7 PUNPCKLWD mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +0000000000000014 0f62c7 PUNPCKLDQ mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +0000000000000017 0f63c7 PACKSSWB mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +000000000000001A 0f64c7 PCMPGTB mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +000000000000001D 0f65c7 PCMPGTW mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +0000000000000020 0f66c7 PCMPGTD mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +0000000000000023 0f67c7 PACKUSWB mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +0000000000000026 0f68c7 PUNPCKHBW mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +0000000000000029 0f69c7 PUNPCKHWD mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +000000000000002C 0f6ac7 PUNPCKHDQ mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +000000000000002F 0f6bc7 PACKSSDW mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +0000000000000032 0f6ec2 MOVD mm0, edx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + +0000000000000035 480f6ec2 MOVQ mm0, rdx + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + +0000000000000039 0f6fc7 MOVQ mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +000000000000003C 0f70c70a PSHUFW mm0, mm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000040 0f74c7 PCMPEQB mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +0000000000000043 0f75c7 PCMPEQW mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +0000000000000046 0f76c7 PCMPEQD mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +0000000000000049 480f7ec2 MOVQ rdx, mm0 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000004D 0f6ff8 MOVQ mm7, mm0 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000050 0fc4c60a PINSRW mm0, esi, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 6, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000054 0fc4030a PINSRW mm0, word ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000058 0fd1c7 PSRLW mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +000000000000005B 0fd2c7 PSRLD mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +000000000000005E 0fd3c7 PSRLQ mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +0000000000000061 0fd4c7 PADDQ mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSE2, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +0000000000000064 0fd5c7 PMULLW mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +0000000000000067 f20fd6c7 MOVDQ2Q mm0, xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +000000000000006B 0fd8c7 PSUBUSB mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +000000000000006E 0fd9c7 PSUBUSW mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +0000000000000071 0fdac7 PMINUB mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +0000000000000074 0fdbc7 PAND mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +0000000000000077 0fdcc7 PADDUSB mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +000000000000007A 0fddc7 PADDUSW mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +000000000000007D 0fdec7 PMAXUB mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +0000000000000080 0fdfc7 PANDN mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +0000000000000083 0fe0c7 PAVGB mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +0000000000000086 0fe1c7 PSRAW mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +0000000000000089 0fe2c7 PSRAD mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +000000000000008C 0fe3c7 PAVGW mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +000000000000008F 0fe4c7 PMULHUW mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +0000000000000092 0fe5c7 PMULHW mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +0000000000000095 0fe703 MOVNTQ qword ptr [rbx], mm0 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000098 0fe8c7 PSUBSB mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +000000000000009B 0fe9c7 PSUBSW mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +000000000000009E 0feac7 PMINSW mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +00000000000000A1 0febc7 POR mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +00000000000000A4 0fecc7 PADDSB mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +00000000000000A7 0fedc7 PADDSW mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +00000000000000AA 0feec7 PMAXSW mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +00000000000000AD 0fefc7 PXOR mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +00000000000000B0 0ff1c7 PSLLW mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +00000000000000B3 0ff2c7 PSLLD mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +00000000000000B6 0ff3c7 PSLLQ mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +00000000000000B9 0ff4c7 PMULUDQ mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSE2, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +00000000000000BC 0ff5c7 PMADDWD mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +00000000000000BF 0ff6c7 PSADBW mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +00000000000000C2 0ff7c7 MASKMOVQ mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 2, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, + Segment: 3, Base: 7, + +00000000000000C5 0ff8c7 PSUBB mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +00000000000000C8 0ff9c7 PSUBW mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +00000000000000CB 0ffac7 PSUBD mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +00000000000000CE 0ffbc7 PSUBQ mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +00000000000000D1 0ffcc7 PADDB mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +00000000000000D4 0ffdc7 PADDW mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +00000000000000D7 0ffec7 PADDD mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + +00000000000000DA 410f2cc7 CVTTPS2PI mm0, xmm15 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 25 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + +00000000000000DE 66410f2cc7 CVTTPD2PI mm0, xmm15 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + +00000000000000E3 410f2dc7 CVTPS2PI mm0, xmm15 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 25 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + +00000000000000E7 66410f2dc7 CVTPD2PI mm0, xmm15 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + +00000000000000EC 0f6003 PUNPCKLBW mm0, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +00000000000000EF 0f6103 PUNPCKLWD mm0, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +00000000000000F2 0f6203 PUNPCKLDQ mm0, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +00000000000000F5 0f6303 PACKSSWB mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000000F8 0f6403 PCMPGTB mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000000FB 0f6503 PCMPGTW mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000000FE 0f6603 PCMPGTD mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000101 0f6703 PACKUSWB mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000104 0f6803 PUNPCKHBW mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000107 0f6903 PUNPCKHWD mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000010A 0f6a03 PUNPCKHDQ mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000010D 0f6b03 PACKSSDW mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000110 0f6e03 MOVD mm0, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +0000000000000113 0f6f03 MOVQ mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000116 0f6f03 MOVQ mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000119 0f70030a PSHUFW mm0, qword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000011D 0f7403 PCMPEQB mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000120 0f7503 PCMPEQW mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000123 0f7603 PCMPEQD mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000126 0f7f03 MOVQ qword ptr [rbx], mm0 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000129 0f7f03 MOVQ qword ptr [rbx], mm0 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000012C 410fc4c70a PINSRW mm0, r15d, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 15, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000131 0fc4030a PINSRW mm0, word ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000135 0fd103 PSRLW mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000138 0fd203 PSRLD mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000013B 0fd303 PSRLQ mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000013E 0fd403 PADDQ mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSE2, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000141 0fd503 PMULLW mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000144 f2410fd6c7 MOVDQ2Q mm0, xmm15 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 15, RegCount: 1 + +0000000000000149 0fd803 PSUBUSB mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000014C 0fd903 PSUBUSW mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000014F 0fda03 PMINUB mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000152 0fdb03 PAND mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000155 0fdc03 PADDUSB mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000158 0fdd03 PADDUSW mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000015B 0fde03 PMAXUB mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000015E 0fdf03 PANDN mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000161 0fe003 PAVGB mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000164 0fe103 PSRAW mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000167 0fe203 PSRAD mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000016A 0fe303 PAVGW mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000016D 0fe403 PMULHUW mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000170 0fe503 PMULHW mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000173 0fe703 MOVNTQ qword ptr [rbx], mm0 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000176 0fe803 PSUBSB mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000179 0fe903 PSUBSW mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000017C 0fea03 PMINSW mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000017F 0feb03 POR mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000182 0fec03 PADDSB mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000185 0fed03 PADDSW mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000188 0fee03 PMAXSW mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000018B 0fef03 PXOR mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000018E 0ff103 PSLLW mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000191 0ff203 PSLLD mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000194 0ff303 PSLLQ mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000197 0ff403 PMULUDQ mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSE2, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000019A 0ff503 PMADDWD mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000019D 0ff603 PSADBW mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000001A0 0ff7c7 MASKMOVQ mm0, mm7 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 2, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, + Segment: 3, Base: 7, + +00000000000001A3 0ff803 PSUBB mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000001A6 0ff903 PSUBW mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000001A9 0ffa03 PSUBD mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000001AC 0ffb03 PSUBQ mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000001AF 0ffc03 PADDB mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000001B2 0ffd03 PADDW mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000001B5 0ffe03 PADDD mm0, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MMX, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 23 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000001B8 0f3800dc PSHUFB mm3, mm4 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 4, RegCount: 1 + +00000000000001BC 0f3801dc PHADDW mm3, mm4 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 4, RegCount: 1 + +00000000000001C0 0f3802dc PHADDD mm3, mm4 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 4, RegCount: 1 + +00000000000001C4 0f3803dc PHADDSW mm3, mm4 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 4, RegCount: 1 + +00000000000001C8 0f3804dc PMADDUBSW mm3, mm4 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 4, RegCount: 1 + +00000000000001CC 0f3805dc PHSUBW mm3, mm4 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 4, RegCount: 1 + +00000000000001D0 0f3806dc PHSUBD mm3, mm4 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 4, RegCount: 1 + +00000000000001D4 0f3807dc PHSUBSW mm3, mm4 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 4, RegCount: 1 + +00000000000001D8 0f3808dc PSIGNB mm3, mm4 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 4, RegCount: 1 + +00000000000001DC 0f3809dc PSIGNW mm3, mm4 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 4, RegCount: 1 + +00000000000001E0 0f380adc PSIGND mm3, mm4 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 4, RegCount: 1 + +00000000000001E4 0f380bdc PMULHRSW mm3, mm4 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 4, RegCount: 1 + +00000000000001E8 0f381cdc PABSB mm3, mm4 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 4, RegCount: 1 + +00000000000001EC 0f381ddc PABSW mm3, mm4 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 4, RegCount: 1 + +00000000000001F0 0f381edc PABSD mm3, mm4 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 4, RegCount: 1 + +00000000000001F4 0f38003b PSHUFB mm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000001F8 0f38013b PHADDW mm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000001FC 0f38023b PHADDD mm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000200 0f38033b PHADDSW mm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000204 0f38043b PMADDUBSW mm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000208 0f38053b PHSUBW mm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000020C 0f38063b PHSUBD mm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000210 0f38073b PHSUBSW mm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000214 0f38083b PSIGNB mm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000218 0f38093b PSIGNW mm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000021C 0f380a3b PSIGND mm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000220 0f380b3b PMULHRSW mm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000224 0f381c3b PABSB mm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000228 0f381d3b PABSW mm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000022C 0f381e3b PABSD mm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000230 0f3a0fca0a PALIGNR mm1, mm2, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000235 0f3a0f0b0a PALIGNR mm1, qword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSSE3, Ins cat: MMX, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: MMX, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + diff --git a/bddisasm_test/simd/sse2_64 b/bddisasm_test/simd/sse2_64 new file mode 100644 index 0000000..01b08c5 --- /dev/null +++ b/bddisasm_test/simd/sse2_64 @@ -0,0 +1,41 @@ +fAAfDDf;f;fAfAf;f;fA(fD(*H*f+;A,I,A-I-fA.fA/fPfAQAQfATfAUfAVfAWfAXAXfAYAYAZfAZAZAZA[fA[A[fA\A\fA]A]fA^A^fA_A_fA`fAafAbfAcfAdfAefAffAgfAhfAifAjfAkfAlfAmfnfHnfAoAofAp +Ap +Ap +fq +fq +fq +fr +fr +fr +fs +fs +fs +fs +fAtfAufAvf~fH~A~fDoDofA +A +f +f; +f +fH +fA +fAfAfAfAfAD~ffAfAfAfAfAfAfAfAfAfAfAfAfAfAfAAAf;fAfAfAfAfAfAfAfAfAfAfAfAfAfAffAfAfAfAfAfAfAf;;f;;f;f;f;f;f;f;f(;f);*H*f+;,H,-H-f.;f/;fPfQ;Q;fT;fU;fV;fW;fX;X;fY;Y;Z;fZ;Z;Z;[;f[;[;f\;\;f];];f^;^;f_;_;f`;fa;fb;fc;fd;fe;ff;fg;fh;fi;fj;fk;fl;fm;fnfHnfo;o;fp; +p; +p; +fq +fq +fq +fr +fr +fr +fs +fs +fs +fs +ft;fu;fv;f~fH~~;f;;f; +; +f +f; +f +fH +f; +f;f;f;f;f;f;ff;f;f;f;f;f;f;f;f;f;f;f;f;f;f;;;f;f;f;f;f;f;f;f;f;f;f;f;f;f;f;ff;f;f;f;f;f;f; \ No newline at end of file diff --git a/bddisasm_test/simd/sse2_64.asm b/bddisasm_test/simd/sse2_64.asm new file mode 100644 index 0000000..ab25a8c --- /dev/null +++ b/bddisasm_test/simd/sse2_64.asm @@ -0,0 +1,287 @@ + bits 64 + + movupd xmm7,xmm13 + movsd xmm7,xmm13 + movupd xmm13,xmm7 + movsd xmm13,xmm7 + movlpd xmm7,[rbx] + movlpd [rbx],xmm7 + unpcklpd xmm7,xmm13 + unpckhpd xmm7,xmm13 + movhpd xmm7,[rbx] + movhpd [rbx],xmm7 + movapd xmm7,xmm13 + movapd xmm13,xmm7 + cvtsi2sd xmm7,edx + cvtsi2sd xmm7,rdx + movntpd [rbx],xmm7 + cvttsd2si edx,xmm13 + cvttsd2si rdx,xmm13 + cvtsd2si edx,xmm13 + cvtsd2si rdx,xmm13 + ucomisd xmm7,xmm13 + comisd xmm7,xmm13 + movmskpd eax,xmm7 + sqrtpd xmm7,xmm13 + sqrtsd xmm7,xmm13 + andpd xmm7,xmm13 + andnpd xmm7,xmm13 + orpd xmm7,xmm13 + xorpd xmm7,xmm13 + addpd xmm7,xmm13 + addsd xmm7,xmm13 + mulpd xmm7,xmm13 + mulsd xmm7,xmm13 + cvtps2pd xmm7,xmm13 + cvtpd2ps xmm7,xmm13 + cvtss2sd xmm7,xmm13 + cvtsd2ss xmm7,xmm13 + cvtdq2ps xmm7,xmm13 + cvtps2dq xmm7,xmm13 + cvttps2dq xmm7,xmm13 + subpd xmm7,xmm13 + subsd xmm7,xmm13 + minpd xmm7,xmm13 + minsd xmm7,xmm13 + divpd xmm7,xmm13 + divsd xmm7,xmm13 + maxpd xmm7,xmm13 + maxsd xmm7,xmm13 + punpcklbw xmm7,xmm13 + punpcklwd xmm7,xmm13 + punpckldq xmm7,xmm13 + packsswb xmm7,xmm13 + pcmpgtb xmm7,xmm13 + pcmpgtw xmm7,xmm13 + pcmpgtd xmm7,xmm13 + packuswb xmm7,xmm13 + punpckhbw xmm7,xmm13 + punpckhwd xmm7,xmm13 + punpckhdq xmm7,xmm13 + packssdw xmm7,xmm13 + punpcklqdq xmm7,xmm13 + punpckhqdq xmm7,xmm13 + movd xmm7,edx + movq xmm7,rdx + movdqa xmm7,xmm13 + movdqu xmm7,xmm13 + pshufd xmm7,xmm13,10 + pshufhw xmm7,xmm13,10 + pshuflw xmm7,xmm13,10 + psrlw xmm7,10 + psraw xmm7,10 + psllw xmm7,10 + psrld xmm7,10 + psrad xmm7,10 + pslld xmm7,10 + psrlq xmm7,10 + psrldq xmm7,10 + psllq xmm7,10 + pslldq xmm7,10 + pcmpeqb xmm7,xmm13 + pcmpeqw xmm7,xmm13 + pcmpeqd xmm7,xmm13 + movd edx,xmm7 + movq rdx,xmm7 + movq xmm7,xmm13 + movdqa xmm13,xmm7 + movdqu xmm13,xmm7 + cmppd xmm7,xmm13,10 + cmpsd xmm7,xmm13,10 + movnti [rbx],edx + pinsrw xmm7,edx,10 + pinsrw xmm7,[rbx],10 + pextrw edx,xmm7,10 + pextrw rdx,xmm7,10 + shufpd xmm7,xmm13,10 + psrlw xmm7,xmm13 + psrld xmm7,xmm13 + psrlq xmm7,xmm13 + paddq xmm7,xmm13 + pmullw xmm7,xmm13 + movq xmm13,xmm7 + movq2dq xmm7,mm0 + pmovmskb edx,xmm7 + psubusb xmm7,xmm13 + psubusw xmm7,xmm13 + pminub xmm7,xmm13 + pand xmm7,xmm13 + paddusb xmm7,xmm13 + paddusw xmm7,xmm13 + pmaxub xmm7,xmm13 + pandn xmm7,xmm13 + pavgb xmm7,xmm13 + psraw xmm7,xmm13 + psrad xmm7,xmm13 + pavgw xmm7,xmm13 + pmulhuw xmm7,xmm13 + pmulhw xmm7,xmm13 + cvttpd2dq xmm7,xmm13 + cvtdq2pd xmm7,xmm13 + cvtpd2dq xmm7,xmm13 + movntdq [rbx],xmm7 + psubsb xmm7,xmm13 + psubsw xmm7,xmm13 + pminsw xmm7,xmm13 + por xmm7,xmm13 + paddsb xmm7,xmm13 + paddsw xmm7,xmm13 + pmaxsw xmm7,xmm13 + pxor xmm7,xmm13 + psllw xmm7,xmm13 + pslld xmm7,xmm13 + psllq xmm7,xmm13 + pmuludq xmm7,xmm13 + pmaddwd xmm7,xmm13 + psadbw xmm7,xmm13 + maskmovdqu xmm7,xmm7 + psubb xmm7,xmm13 + psubw xmm7,xmm13 + psubd xmm7,xmm13 + psubq xmm7,xmm13 + paddb xmm7,xmm13 + paddw xmm7,xmm13 + paddd xmm7,xmm13 + + movupd xmm7,[rbx] + movsd xmm7,[rbx] + movupd [rbx],xmm7 + movsd [rbx],xmm7 + movlpd xmm7,[rbx] + movlpd [rbx],xmm7 + unpcklpd xmm7,[rbx] + unpckhpd xmm7,[rbx] + movhpd xmm7,[rbx] + movhpd [rbx],xmm7 + movapd xmm7,[rbx] + movapd [rbx],xmm7 + cvtsi2sd xmm7,edx + cvtsi2sd xmm7,rdx + movntpd [rbx],xmm7 + cvttsd2si edx,[rbx] + cvttsd2si rdx,[rbx] + cvtsd2si edx,[rbx] + cvtsd2si rdx,[rbx] + ucomisd xmm7,[rbx] + comisd xmm7,[rbx] + movmskpd eax,xmm7 + sqrtpd xmm7,[rbx] + sqrtsd xmm7,[rbx] + andpd xmm7,[rbx] + andnpd xmm7,[rbx] + orpd xmm7,[rbx] + xorpd xmm7,[rbx] + addpd xmm7,[rbx] + addsd xmm7,[rbx] + mulpd xmm7,[rbx] + mulsd xmm7,[rbx] + cvtps2pd xmm7,[rbx] + cvtpd2ps xmm7,[rbx] + cvtss2sd xmm7,[rbx] + cvtsd2ss xmm7,[rbx] + cvtdq2ps xmm7,[rbx] + cvtps2dq xmm7,[rbx] + cvttps2dq xmm7,[rbx] + subpd xmm7,[rbx] + subsd xmm7,[rbx] + minpd xmm7,[rbx] + minsd xmm7,[rbx] + divpd xmm7,[rbx] + divsd xmm7,[rbx] + maxpd xmm7,[rbx] + maxsd xmm7,[rbx] + punpcklbw xmm7,[rbx] + punpcklwd xmm7,[rbx] + punpckldq xmm7,[rbx] + packsswb xmm7,[rbx] + pcmpgtb xmm7,[rbx] + pcmpgtw xmm7,[rbx] + pcmpgtd xmm7,[rbx] + packuswb xmm7,[rbx] + punpckhbw xmm7,[rbx] + punpckhwd xmm7,[rbx] + punpckhdq xmm7,[rbx] + packssdw xmm7,[rbx] + punpcklqdq xmm7,[rbx] + punpckhqdq xmm7,[rbx] + movd xmm7,edx + movq xmm7,rdx + movdqa xmm7,[rbx] + movdqu xmm7,[rbx] + pshufd xmm7,[rbx],10 + pshufhw xmm7,[rbx],10 + pshuflw xmm7,[rbx],10 + psrlw xmm7,10 + psraw xmm7,10 + psllw xmm7,10 + psrld xmm7,10 + psrad xmm7,10 + pslld xmm7,10 + psrlq xmm7,10 + psrldq xmm7,10 + psllq xmm7,10 + pslldq xmm7,10 + pcmpeqb xmm7,[rbx] + pcmpeqw xmm7,[rbx] + pcmpeqd xmm7,[rbx] + movd edx,xmm7 + movq rdx,xmm7 + movq xmm7,[rbx] + movdqa [rbx],xmm7 + movdqu [rbx],xmm7 + cmppd xmm7,[rbx],10 + cmpsd xmm7,[rbx],10 + movnti [rbx],edx + pinsrw xmm7,edx,10 + pinsrw xmm7,[rbx],10 + pextrw edx,xmm7,10 + pextrw rdx,xmm7,10 + shufpd xmm7,[rbx],10 + psrlw xmm7,[rbx] + psrld xmm7,[rbx] + psrlq xmm7,[rbx] + paddq xmm7,[rbx] + pmullw xmm7,[rbx] + movq [rbx],xmm7 + movq2dq xmm7,mm0 + pmovmskb edx,xmm7 + psubusb xmm7,[rbx] + psubusw xmm7,[rbx] + pminub xmm7,[rbx] + pand xmm7,[rbx] + paddusb xmm7,[rbx] + paddusw xmm7,[rbx] + pmaxub xmm7,[rbx] + pandn xmm7,[rbx] + pavgb xmm7,[rbx] + psraw xmm7,[rbx] + psrad xmm7,[rbx] + pavgw xmm7,[rbx] + pmulhuw xmm7,[rbx] + pmulhw xmm7,[rbx] + cvttpd2dq xmm7,[rbx] + cvtdq2pd xmm7,[rbx] + cvtpd2dq xmm7,[rbx] + movntdq [rbx],xmm7 + psubsb xmm7,[rbx] + psubsw xmm7,[rbx] + pminsw xmm7,[rbx] + por xmm7,[rbx] + paddsb xmm7,[rbx] + paddsw xmm7,[rbx] + pmaxsw xmm7,[rbx] + pxor xmm7,[rbx] + psllw xmm7,[rbx] + pslld xmm7,[rbx] + psllq xmm7,[rbx] + pmuludq xmm7,[rbx] + pmaddwd xmm7,[rbx] + psadbw xmm7,[rbx] + maskmovdqu xmm7,xmm7 + psubb xmm7,[rbx] + psubw xmm7,[rbx] + psubd xmm7,[rbx] + psubq xmm7,[rbx] + paddb xmm7,[rbx] + paddw xmm7,[rbx] + paddd xmm7,[rbx] \ No newline at end of file diff --git a/bddisasm_test/simd/sse2_64.result b/bddisasm_test/simd/sse2_64.result new file mode 100644 index 0000000..a6ebf14 --- /dev/null +++ b/bddisasm_test/simd/sse2_64.result @@ -0,0 +1,4703 @@ +0000000000000000 66410f10fd MOVUPD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000005 f2410f10fd MOVSD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000000A 66440f10ef MOVUPD xmm13, xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +000000000000000F f2440f10ef MOVSD xmm13, xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +0000000000000014 660f123b MOVLPD xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000018 660f133b MOVLPD qword ptr [rbx], xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +000000000000001C 66410f14fd UNPCKLPD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000021 66410f15fd UNPCKHPD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000026 660f163b MOVHPD xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000002A 660f173b MOVHPD qword ptr [rbx], xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +000000000000002E 66410f28fd MOVAPD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000033 66440f28ef MOVAPD xmm13, xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +0000000000000038 f20f2afa CVTSI2SD xmm7, edx + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + +000000000000003C f2480f2afa CVTSI2SD xmm7, rdx + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + +0000000000000041 660f2b3b MOVNTPD xmmword ptr [rbx], xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +0000000000000045 f2410f2cd5 CVTTSD2SI edx, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000004A f2490f2cd5 CVTTSD2SI rdx, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000004F f2410f2dd5 CVTSD2SI edx, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000054 f2490f2dd5 CVTSD2SI rdx, xmm13 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000059 66410f2efd UCOMISD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE2, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + FLAGS access + CF: m, PF: m, ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000005E 66410f2ffd COMISD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE2, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + FLAGS access + CF: m, PF: m, ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000063 660f50c7 MOVMSKPD eax, xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +0000000000000067 66410f51fd SQRTPD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000006C f2410f51fd SQRTSD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000071 66410f54fd ANDPD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000076 66410f55fd ANDNPD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000007B 66410f56fd ORPD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000080 66410f57fd XORPD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000085 66410f58fd ADDPD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000008A f2410f58fd ADDSD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000008F 66410f59fd MULPD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000094 f2410f59fd MULSD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000099 410f5afd CVTPS2PD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000009D 66410f5afd CVTPD2PS xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000A2 f3410f5afd CVTSS2SD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000A7 f2410f5afd CVTSD2SS xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000AC 410f5bfd CVTDQ2PS xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000B0 66410f5bfd CVTPS2DQ xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000B5 f3410f5bfd CVTTPS2DQ xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000BA 66410f5cfd SUBPD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000BF f2410f5cfd SUBSD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000C4 66410f5dfd MINPD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000C9 f2410f5dfd MINSD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000CE 66410f5efd DIVPD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000D3 f2410f5efd DIVSD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000D8 66410f5ffd MAXPD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000DD f2410f5ffd MAXSD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000E2 66410f60fd PUNPCKLBW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000E7 66410f61fd PUNPCKLWD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000EC 66410f62fd PUNPCKLDQ xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000F1 66410f63fd PACKSSWB xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000F6 66410f64fd PCMPGTB xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000FB 66410f65fd PCMPGTW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000100 66410f66fd PCMPGTD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000105 66410f67fd PACKUSWB xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000010A 66410f68fd PUNPCKHBW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000010F 66410f69fd PUNPCKHWD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000114 66410f6afd PUNPCKHDQ xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000119 66410f6bfd PACKSSDW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000011E 66410f6cfd PUNPCKLQDQ xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000123 66410f6dfd PUNPCKHQDQ xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000128 660f6efa MOVD xmm7, edx + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + +000000000000012C 66480f6efa MOVQ xmm7, rdx + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + +0000000000000131 66410f6ffd MOVDQA xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000136 f3410f6ffd MOVDQU xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000013B 66410f70fd0a PSHUFD xmm7, xmm13, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000141 f3410f70fd0a PSHUFHW xmm7, xmm13, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000147 f2410f70fd0a PSHUFLW xmm7, xmm13, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000014D 660f71d70a PSRLW xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000152 660f71e70a PSRAW xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000157 660f71f70a PSLLW xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000015C 660f72d70a PSRLD xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000161 660f72e70a PSRAD xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000166 660f72f70a PSLLD xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000016B 660f73d70a PSRLQ xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000170 660f73df0a PSRLDQ xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000175 660f73f70a PSLLQ xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000017A 660f73ff0a PSLLDQ xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000017F 66410f74fd PCMPEQB xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000184 66410f75fd PCMPEQW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000189 66410f76fd PCMPEQD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000018E 660f7efa MOVD edx, xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +0000000000000192 66480f7efa MOVQ rdx, xmm7 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +0000000000000197 f3410f7efd MOVQ xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000019C 66440f6fef MOVDQA xmm13, xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +00000000000001A1 f3440f6fef MOVDQU xmm13, xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +00000000000001A6 66410fc2fd0a CMPPD xmm7, xmm13, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000001AC f2410fc2fd0a CMPSD xmm7, xmm13, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000001B2 0fc313 MOVNTI dword ptr [rbx], edx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + +00000000000001B5 660fc4fa0a PINSRW xmm7, edx, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000001BA 660fc43b0a PINSRW xmm7, word ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000001BF 660fc5d70a PEXTRW edx, xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000001C4 66480fc5d70a PEXTRW rdx, xmm7, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000001CA 66410fc6fd0a SHUFPD xmm7, xmm13, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000001D0 66410fd1fd PSRLW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000001D5 66410fd2fd PSRLD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000001DA 66410fd3fd PSRLQ xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000001DF 66410fd4fd PADDQ xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000001E4 66410fd5fd PMULLW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000001E9 f3440f7eef MOVQ xmm13, xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +00000000000001EE f30fd6f8 MOVQ2DQ xmm7, mm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000001F2 660fd7d7 PMOVMSKB edx, xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +00000000000001F6 66410fd8fd PSUBUSB xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000001FB 66410fd9fd PSUBUSW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000200 66410fdafd PMINUB xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000205 66410fdbfd PAND xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000020A 66410fdcfd PADDUSB xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000020F 66410fddfd PADDUSW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000214 66410fdefd PMAXUB xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000219 66410fdffd PANDN xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000021E 66410fe0fd PAVGB xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000223 66410fe1fd PSRAW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000228 66410fe2fd PSRAD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000022D 66410fe3fd PAVGW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000232 66410fe4fd PMULHUW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000237 66410fe5fd PMULHW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000023C 66410fe6fd CVTTPD2DQ xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000241 f3410fe6fd CVTDQ2PD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000246 f2410fe6fd CVTPD2DQ xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000024B 660fe73b MOVNTDQ xmmword ptr [rbx], xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +000000000000024F 66410fe8fd PSUBSB xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000254 66410fe9fd PSUBSW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000259 66410feafd PMINSW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000025E 66410febfd POR xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000263 66410fecfd PADDSB xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000268 66410fedfd PADDSW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000026D 66410feefd PMAXSW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000272 66410feffd PXOR xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000277 66410ff1fd PSLLW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000027C 66410ff2fd PSLLD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000281 66410ff3fd PSLLQ xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000286 66410ff4fd PMULUDQ xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000028B 66410ff5fd PMADDWD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000290 66410ff6fd PSADBW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000295 660ff7ff MASKMOVDQU xmm7, xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: S, + Segment: 3, Base: 7, + +0000000000000299 66410ff8fd PSUBB xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000029E 66410ff9fd PSUBW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000002A3 66410ffafd PSUBD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000002A8 66410ffbfd PSUBQ xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000002AD 66410ffcfd PADDB xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000002B2 66410ffdfd PADDW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000002B7 66410ffefd PADDD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000002BC 660f103b MOVUPD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000002C0 f20f103b MOVSD xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000002C4 660f113b MOVUPD xmmword ptr [rbx], xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +00000000000002C8 f20f113b MOVSD qword ptr [rbx], xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +00000000000002CC 660f123b MOVLPD xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000002D0 660f133b MOVLPD qword ptr [rbx], xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +00000000000002D4 660f143b UNPCKLPD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000002D8 660f153b UNPCKHPD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000002DC 660f163b MOVHPD xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000002E0 660f173b MOVHPD qword ptr [rbx], xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +00000000000002E4 660f283b MOVAPD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000002E8 660f293b MOVAPD xmmword ptr [rbx], xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +00000000000002EC f20f2afa CVTSI2SD xmm7, edx + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + +00000000000002F0 f2480f2afa CVTSI2SD xmm7, rdx + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + +00000000000002F5 660f2b3b MOVNTPD xmmword ptr [rbx], xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +00000000000002F9 f20f2c13 CVTTSD2SI edx, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000002FD f2480f2c13 CVTTSD2SI rdx, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000302 f20f2d13 CVTSD2SI edx, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000306 f2480f2d13 CVTSD2SI rdx, qword ptr [rbx] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000030B 660f2e3b UCOMISD xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE2, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + FLAGS access + CF: m, PF: m, ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000030F 660f2f3b COMISD xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE2, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + FLAGS access + CF: m, PF: m, ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000313 660f50c7 MOVMSKPD eax, xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +0000000000000317 660f513b SQRTPD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000031B f20f513b SQRTSD xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000031F 660f543b ANDPD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000323 660f553b ANDNPD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000327 660f563b ORPD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000032B 660f573b XORPD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: LOGICAL_FP, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000032F 660f583b ADDPD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000333 f20f583b ADDSD xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000337 660f593b MULPD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000033B f20f593b MULSD xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000033F 0f5a3b CVTPS2PD xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000342 660f5a3b CVTPD2PS xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000346 f30f5a3b CVTSS2SD xmm7, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +000000000000034A f20f5a3b CVTSD2SS xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000034E 0f5b3b CVTDQ2PS xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000351 660f5b3b CVTPS2DQ xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000355 f30f5b3b CVTTPS2DQ xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000359 660f5c3b SUBPD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000035D f20f5c3b SUBSD xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000361 660f5d3b MINPD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000365 f20f5d3b MINSD xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000369 660f5e3b DIVPD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000036D f20f5e3b DIVSD xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000371 660f5f3b MAXPD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000375 f20f5f3b MAXSD xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000379 660f603b PUNPCKLBW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000037D 660f613b PUNPCKLWD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000381 660f623b PUNPCKLDQ xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000385 660f633b PACKSSWB xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000389 660f643b PCMPGTB xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000038D 660f653b PCMPGTW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000391 660f663b PCMPGTD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000395 660f673b PACKUSWB xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000399 660f683b PUNPCKHBW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000039D 660f693b PUNPCKHWD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000003A1 660f6a3b PUNPCKHDQ xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000003A5 660f6b3b PACKSSDW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000003A9 660f6c3b PUNPCKLQDQ xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000003AD 660f6d3b PUNPCKHQDQ xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000003B1 660f6efa MOVD xmm7, edx + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + +00000000000003B5 66480f6efa MOVQ xmm7, rdx + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + +00000000000003BA 660f6f3b MOVDQA xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000003BE f30f6f3b MOVDQU xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000003C2 660f703b0a PSHUFD xmm7, xmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000003C7 f30f703b0a PSHUFHW xmm7, xmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000003CC f20f703b0a PSHUFLW xmm7, xmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000003D1 660f71d70a PSRLW xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000003D6 660f71e70a PSRAW xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000003DB 660f71f70a PSLLW xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000003E0 660f72d70a PSRLD xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000003E5 660f72e70a PSRAD xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000003EA 660f72f70a PSLLD xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000003EF 660f73d70a PSRLQ xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000003F4 660f73df0a PSRLDQ xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000003F9 660f73f70a PSLLQ xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000003FE 660f73ff0a PSLLDQ xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000403 660f743b PCMPEQB xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000407 660f753b PCMPEQW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000040B 660f763b PCMPEQD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000040F 660f7efa MOVD edx, xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +0000000000000413 66480f7efa MOVQ rdx, xmm7 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +0000000000000418 f30f7e3b MOVQ xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000041C 660f7f3b MOVDQA xmmword ptr [rbx], xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +0000000000000420 f30f7f3b MOVDQU xmmword ptr [rbx], xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +0000000000000424 660fc23b0a CMPPD xmm7, xmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000429 f20fc23b0a CMPSD xmm7, qword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000042E 0fc313 MOVNTI dword ptr [rbx], edx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + +0000000000000431 660fc4fa0a PINSRW xmm7, edx, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000436 660fc43b0a PINSRW xmm7, word ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000043B 660fc5d70a PEXTRW edx, xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000440 66480fc5d70a PEXTRW rdx, xmm7, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000446 660fc63b0a SHUFPD xmm7, xmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000044B 660fd13b PSRLW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000044F 660fd23b PSRLD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000453 660fd33b PSRLQ xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000457 660fd43b PADDQ xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000045B 660fd53b PMULLW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000045F 660fd63b MOVQ qword ptr [rbx], xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +0000000000000463 f30fd6f8 MOVQ2DQ xmm7, mm0 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000467 660fd7d7 PMOVMSKB edx, xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 7 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +000000000000046B 660fd83b PSUBUSB xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000046F 660fd93b PSUBUSW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000473 660fda3b PMINUB xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000477 660fdb3b PAND xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000047B 660fdc3b PADDUSB xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000047F 660fdd3b PADDUSW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000483 660fde3b PMAXUB xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000487 660fdf3b PANDN xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000048B 660fe03b PAVGB xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000048F 660fe13b PSRAW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000493 660fe23b PSRAD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000497 660fe33b PAVGW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000049B 660fe43b PMULHUW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000049F 660fe53b PMULHW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000004A3 660fe63b CVTTPD2DQ xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000004A7 f30fe63b CVTDQ2PD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000004AB f20fe63b CVTPD2DQ xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000004AF 660fe73b MOVNTDQ xmmword ptr [rbx], xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +00000000000004B3 660fe83b PSUBSB xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000004B7 660fe93b PSUBSW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000004BB 660fea3b PMINSW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000004BF 660feb3b POR xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000004C3 660fec3b PADDSB xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000004C7 660fed3b PADDSW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000004CB 660fee3b PMAXSW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000004CF 660fef3b PXOR xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: LOGICAL, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000004D3 660ff13b PSLLW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000004D7 660ff23b PSLLD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000004DB 660ff33b PSLLQ xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000004DF 660ff43b PMULUDQ xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000004E3 660ff53b PMADDWD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000004E7 660ff63b PSADBW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000004EB 660ff7ff MASKMOVDQU xmm7, xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: S, + Segment: 3, Base: 7, + +00000000000004EF 660ff83b PSUBB xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000004F3 660ff93b PSUBW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000004F7 660ffa3b PSUBD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000004FB 660ffb3b PSUBQ xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000004FF 660ffc3b PADDB xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000503 660ffd3b PADDW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000507 660ffe3b PADDD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + diff --git a/bddisasm_test/simd/sse3_64 b/bddisasm_test/simd/sse3_64 new file mode 100644 index 0000000000000000000000000000000000000000..f32073c134e0651ea1cc367c8c456e89b99de379 GIT binary patch literal 267 zcmW;Gy$yvh3(1r;y{B2|`QieyJdL8OlK?ym56XIIX_mhzDtY%O=N$ThMh zw#4?Z0ed~R^T*p+$yzqDm7VP6AV)b#Cuh0IT^{tZ;<7FN!(?0iZ4o^p6EYzmBnOY+ b4^okuG^8aR>B&GwG7(2+vXPw};4<(2ZVFbI literal 0 HcmV?d00001 diff --git a/bddisasm_test/simd/sse3_64.asm b/bddisasm_test/simd/sse3_64.asm new file mode 100644 index 0000000..747748a --- /dev/null +++ b/bddisasm_test/simd/sse3_64.asm @@ -0,0 +1,55 @@ + bits 64 + + movsldup xmm7,xmm13 + movddup xmm7,xmm13 + movshdup xmm7,xmm13 + haddpd xmm7,xmm13 + haddps xmm7,xmm13 + hsubpd xmm7,xmm13 + hsubps xmm7,xmm13 + addsubpd xmm7,xmm13 + addsubps xmm7,xmm13 + lddqu xmm7,[rbx] + pshufb xmm7,xmm13 + phaddw xmm7,xmm13 + phaddd xmm7,xmm13 + phaddsw xmm7,xmm13 + pmaddubsw xmm7,xmm13 + phsubw xmm7,xmm13 + phsubd xmm7,xmm13 + phsubsw xmm7,xmm13 + psignb xmm7,xmm13 + psignw xmm7,xmm13 + psignd xmm7,xmm13 + pmulhrsw xmm7,xmm13 + pabsb xmm7,xmm13 + pabsw xmm7,xmm13 + pabsd xmm7,xmm13 + palignr xmm7,xmm13,10 + + movsldup xmm7,[rbx] + movddup xmm7,[rbx] + movshdup xmm7,[rbx] + haddpd xmm7,[rbx] + haddps xmm7,[rbx] + hsubpd xmm7,[rbx] + hsubps xmm7,[rbx] + addsubpd xmm7,[rbx] + addsubps xmm7,[rbx] + lddqu xmm7,[rbx] + pshufb xmm7,[rbx] + phaddw xmm7,[rbx] + phaddd xmm7,[rbx] + phaddsw xmm7,[rbx] + pmaddubsw xmm7,[rbx] + phsubw xmm7,[rbx] + phsubd xmm7,[rbx] + phsubsw xmm7,[rbx] + psignb xmm7,[rbx] + psignw xmm7,[rbx] + psignd xmm7,[rbx] + pmulhrsw xmm7,[rbx] + pabsb xmm7,[rbx] + pabsw xmm7,[rbx] + pabsd xmm7,[rbx] + palignr xmm7,[rbx],10 diff --git a/bddisasm_test/simd/sse3_64.result b/bddisasm_test/simd/sse3_64.result new file mode 100644 index 0000000..7c5a67f --- /dev/null +++ b/bddisasm_test/simd/sse3_64.result @@ -0,0 +1,861 @@ +0000000000000000 f3410f12fd MOVSLDUP xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE3, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 0 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000005 f2410f12fd MOVDDUP xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE3, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 0 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000000A f3410f16fd MOVSHDUP xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE3, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 0 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000000F 66410f7cfd HADDPD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 0 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000014 f2410f7cfd HADDPS xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 0 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000019 66410f7dfd HSUBPD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 0 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000001E f2410f7dfd HSUBPS xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 0 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000023 66410fd0fd ADDSUBPD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 0 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000028 f2410fd0fd ADDSUBPS xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 0 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000002D f20ff03b LDDQU xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 0 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000031 66410f3800fd PSHUFB xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000037 66410f3801fd PHADDW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000003D 66410f3802fd PHADDD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000043 66410f3803fd PHADDSW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000049 66410f3804fd PMADDUBSW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000004F 66410f3805fd PHSUBW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000055 66410f3806fd PHSUBD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000005B 66410f3807fd PHSUBSW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000061 66410f3808fd PSIGNB xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000067 66410f3809fd PSIGNW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000006D 66410f380afd PSIGND xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000073 66410f380bfd PMULHRSW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000079 66410f381cfd PABSB xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000007F 66410f381dfd PABSW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000085 66410f381efd PABSD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000008B 66410f3a0ffd0a PALIGNR xmm7, xmm13, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000092 f30f123b MOVSLDUP xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE3, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 0 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000096 f20f123b MOVDDUP xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE3, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 0 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +000000000000009A f30f163b MOVSHDUP xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE3, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 0 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000009E 660f7c3b HADDPD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 0 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000000A2 f20f7c3b HADDPS xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 0 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000000A6 660f7d3b HSUBPD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 0 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000000AA f20f7d3b HSUBPS xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 0 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000000AE 660fd03b ADDSUBPD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 0 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000000B2 f20fd03b ADDSUBPS xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 0 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000000B6 f20ff03b LDDQU xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 0 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000000BA 660f38003b PSHUFB xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000000BF 660f38013b PHADDW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000000C4 660f38023b PHADDD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000000C9 660f38033b PHADDSW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000000CE 660f38043b PMADDUBSW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000000D3 660f38053b PHSUBW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000000D8 660f38063b PHSUBD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000000DD 660f38073b PHSUBSW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000000E2 660f38083b PSIGNB xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000000E7 660f38093b PSIGNW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000000EC 660f380a3b PSIGND xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000000F1 660f380b3b PMULHRSW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000000F6 660f381c3b PABSB xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000000FB 660f381d3b PABSW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000100 660f381e3b PABSD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000105 660f3a0f3b0a PALIGNR xmm7, xmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSSE3, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 9 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + diff --git a/bddisasm_test/simd/sse4_64 b/bddisasm_test/simd/sse4_64 new file mode 100644 index 0000000..40e7f0a --- /dev/null +++ b/bddisasm_test/simd/sse4_64 @@ -0,0 +1,64 @@ ++;+;x + +fx + +fyyfA8fA8fA8fA8fA8 fA8!fA8"fA8#fA8$fA8%fA8(fA8)f8*;fA8+fA80fA81fA82fA83fA84fA85fA87fA88fA89fA8:fA8;fA8fA8?fA8@fA8AfA: +fA: +fA: + +fA: +fA: +fA: +fA: +f:; +f: +f:; +f +f: +fH: +fH: +f: ; +f: +f:!; +f:! +f:" +fH:" +fA:@ +fA:A +fA:B +fA:` +fA:a +fA:b +fA:c ++;+;x + +fx + +fyyf8;f8;f8;f8;f8 ;f8!;f8";f8#;f8$;f8%;f8(;f8);f8*;f8+;f80;f81;f82;f83;f84;f85;f87;f88;f89;f8:;f8;;f8<;f8=;f8>;f8?;f8@;f8A;f:; +f: ; +f: +; +f: ; +f: ; +f: ; +f:; +f:; +f: +f:; +f +f: +fH: +fH: +f: ; +f: +f:!; +f:! +f:" +fH:" +f:@; +f:A; +f:B; +f:`; +f:a; +f:b; +f:c; diff --git a/bddisasm_test/simd/sse4_64.asm b/bddisasm_test/simd/sse4_64.asm new file mode 100644 index 0000000..d46c876 --- /dev/null +++ b/bddisasm_test/simd/sse4_64.asm @@ -0,0 +1,131 @@ + bits 64 + + movntss [rbx],xmm7 + movntsd [rbx],xmm7 + insertq xmm7,xmm7,10,10 + extrq xmm7,10,10 + extrq xmm7,xmm7 + insertq xmm7,xmm7 + pblendvb xmm7,xmm13 + blendvps xmm7,xmm13 + blendvpd xmm7,xmm13 + ptest xmm7,xmm13 + pmovsxbw xmm7,xmm13 + pmovsxbd xmm7,xmm13 + pmovsxbq xmm7,xmm13 + pmovsxwd xmm7,xmm13 + pmovsxwq xmm7,xmm13 + pmovsxdq xmm7,xmm13 + pmuldq xmm7,xmm13 + pcmpeqq xmm7,xmm13 + movntdqa xmm7,[rbx] + packusdw xmm7,xmm13 + pmovzxbw xmm7,xmm13 + pmovzxbd xmm7,xmm13 + pmovzxbq xmm7,xmm13 + pmovzxwd xmm7,xmm13 + pmovzxwq xmm7,xmm13 + pmovzxdq xmm7,xmm13 + pcmpgtq xmm7,xmm13 + pminsb xmm7,xmm13 + pminsd xmm7,xmm13 + pminuw xmm7,xmm13 + pminud xmm7,xmm13 + pmaxsb xmm7,xmm13 + pmaxsd xmm7,xmm13 + pmaxuw xmm7,xmm13 + pmaxud xmm7,xmm13 + pmulld xmm7,xmm13 + phminposuw xmm7,xmm13 + roundps xmm7,xmm13,10 + roundpd xmm7,xmm13,10 + roundss xmm7,xmm13,10 + roundsd xmm7,xmm13,10 + blendps xmm7,xmm13,10 + blendpd xmm7,xmm13,10 + pblendw xmm7,xmm13,10 + pextrb [rbx],xmm7,10 + pextrb edx,xmm7,10 + pextrw [rbx],xmm7,10 + pextrw edx,xmm7,10 + pextrd edx,xmm7,10 + pextrq rdx,xmm7,10 + extractps rdx,xmm7,10 + pinsrb xmm7,[rbx],10 + pinsrb xmm7,edx,10 + insertps xmm7,[rbx],10 + insertps xmm7,xmm7,10 + pinsrd xmm7,edx,10 + pinsrq xmm7,rdx,10 + dpps xmm7,xmm13,10 + dppd xmm7,xmm13,10 + mpsadbw xmm7,xmm13,10 + pcmpestrm xmm7,xmm13,10 + pcmpestri xmm7,xmm13,10 + pcmpistrm xmm7,xmm13,10 + pcmpistri xmm7,xmm13,10 + + movntss [rbx],xmm7 + movntsd [rbx],xmm7 + insertq xmm7,xmm7,10,10 + extrq xmm7,10,10 + extrq xmm7,xmm7 + insertq xmm7,xmm7 + pblendvb xmm7,[rbx] + blendvps xmm7,[rbx] + blendvpd xmm7,[rbx] + ptest xmm7,[rbx] + pmovsxbw xmm7,[rbx] + pmovsxbd xmm7,[rbx] + pmovsxbq xmm7,[rbx] + pmovsxwd xmm7,[rbx] + pmovsxwq xmm7,[rbx] + pmovsxdq xmm7,[rbx] + pmuldq xmm7,[rbx] + pcmpeqq xmm7,[rbx] + movntdqa xmm7,[rbx] + packusdw xmm7,[rbx] + pmovzxbw xmm7,[rbx] + pmovzxbd xmm7,[rbx] + pmovzxbq xmm7,[rbx] + pmovzxwd xmm7,[rbx] + pmovzxwq xmm7,[rbx] + pmovzxdq xmm7,[rbx] + pcmpgtq xmm7,[rbx] + pminsb xmm7,[rbx] + pminsd xmm7,[rbx] + pminuw xmm7,[rbx] + pminud xmm7,[rbx] + pmaxsb xmm7,[rbx] + pmaxsd xmm7,[rbx] + pmaxuw xmm7,[rbx] + pmaxud xmm7,[rbx] + pmulld xmm7,[rbx] + phminposuw xmm7,[rbx] + roundps xmm7,[rbx],10 + roundpd xmm7,[rbx],10 + roundss xmm7,[rbx],10 + roundsd xmm7,[rbx],10 + blendps xmm7,[rbx],10 + blendpd xmm7,[rbx],10 + pblendw xmm7,[rbx],10 + pextrb [rbx],xmm7,10 + pextrb edx,xmm7,10 + pextrw [rbx],xmm7,10 + pextrw edx,xmm7,10 + pextrd edx,xmm7,10 + pextrq rdx,xmm7,10 + extractps rdx,xmm7,10 + pinsrb xmm7,[rbx],10 + pinsrb xmm7,edx,10 + insertps xmm7,[rbx],10 + insertps xmm7,xmm7,10 + pinsrd xmm7,edx,10 + pinsrq xmm7,rdx,10 + dpps xmm7,[rbx],10 + dppd xmm7,[rbx],10 + mpsadbw xmm7,[rbx],10 + pcmpestrm xmm7,[rbx],10 + pcmpestri xmm7,[rbx],10 + pcmpistrm xmm7,[rbx],10 + pcmpistri xmm7,[rbx],10 diff --git a/bddisasm_test/simd/sse4_64.result b/bddisasm_test/simd/sse4_64.result new file mode 100644 index 0000000..3fe68bb --- /dev/null +++ b/bddisasm_test/simd/sse4_64.result @@ -0,0 +1,2206 @@ +0000000000000000 f30f2b3b MOVNTSS dword ptr [rbx], xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4A, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +0000000000000004 f20f2b3b MOVNTSD qword ptr [rbx], xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4A, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +0000000000000008 f20f78ff0a0a INSERTQ xmm7, xmm7, 0x0a, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4A, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000000E 660f78c70a0a EXTRQ xmm7, 0x0a, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4A, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000014 660f79ff EXTRQ xmm7, xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4A, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +0000000000000018 f20f79ff INSERTQ xmm7, xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4A, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +000000000000001C 66410f3810fd PBLENDVB xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000022 66410f3814fd BLENDVPS xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000000028 66410f3815fd BLENDVPD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000002E 66410f3817fd PTEST xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000034 66410f3820fd PMOVSXBW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000003A 66410f3821fd PMOVSXBD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000040 66410f3822fd PMOVSXBQ xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000046 66410f3823fd PMOVSXWD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000004C 66410f3824fd PMOVSXWQ xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000052 66410f3825fd PMOVSXDQ xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000058 66410f3828fd PMULDQ xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000005E 66410f3829fd PCMPEQQ xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000064 660f382a3b MOVNTDQA xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000069 66410f382bfd PACKUSDW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000006F 66410f3830fd PMOVZXBW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000075 66410f3831fd PMOVZXBD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000007B 66410f3832fd PMOVZXBQ xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000081 66410f3833fd PMOVZXWD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000087 66410f3834fd PMOVZXWQ xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000008D 66410f3835fd PMOVZXDQ xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000093 66410f3837fd PCMPGTQ xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE42, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 20 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +0000000000000099 66410f3838fd PMINSB xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +000000000000009F 66410f3839fd PMINSD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000A5 66410f383afd PMINUW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000AB 66410f383bfd PMINUD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000B1 66410f383cfd PMAXSB xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000B7 66410f383dfd PMAXSD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000BD 66410f383efd PMAXUW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000C3 66410f383ffd PMAXUD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000C9 66410f3840fd PMULLD xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000CF 66410f3841fd PHMINPOSUW xmm7, xmm13 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + +00000000000000D5 66410f3a08fd0a ROUNDPS xmm7, xmm13, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000000DC 66410f3a09fd0a ROUNDPD xmm7, xmm13, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000000E3 66410f3a0afd0a ROUNDSS xmm7, xmm13, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000000EA 66410f3a0bfd0a ROUNDSD xmm7, xmm13, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000000F1 66410f3a0cfd0a BLENDPS xmm7, xmm13, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000000F8 66410f3a0dfd0a BLENDPD xmm7, xmm13, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000000FF 66410f3a0efd0a PBLENDW xmm7, xmm13, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000106 660f3a143b0a PEXTRB byte ptr [rbx], xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000010C 660f3a14fa0a PEXTRB edx, xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000112 660f3a153b0a PEXTRW word ptr [rbx], xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000118 660fc5d70a PEXTRW edx, xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000011D 660f3a16fa0a PEXTRD edx, xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000123 66480f3a16fa0a PEXTRQ rdx, xmm7, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000012A 66480f3a17fa0a EXTRACTPS edx, xmm7, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000131 660f3a203b0a PINSRB xmm7, byte ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000137 660f3a20fa0a PINSRB xmm7, edx, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000013D 660f3a213b0a INSERTPS xmm7, dword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000143 660f3a21ff0a INSERTPS xmm7, xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000149 660f3a22fa0a PINSRD xmm7, edx, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000014F 66480f3a22fa0a PINSRQ xmm7, rdx, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000156 66410f3a40fd0a DPPS xmm7, xmm13, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000015D 66410f3a41fd0a DPPD xmm7, xmm13, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000164 66410f3a42fd0a MPSADBW xmm7, xmm13, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000016B 66410f3a60fd0a PCMPESTRM xmm7, xmm13, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE42, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 20 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 5, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 6, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000172 66410f3a61fd0a PCMPESTRI xmm7, xmm13, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE42, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 20 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 5, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 6, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000179 66410f3a62fd0a PCMPISTRM xmm7, xmm13, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE42, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 20 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000180 66410f3a63fd0a PCMPISTRI xmm7, xmm13, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE42, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 20 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000187 f30f2b3b MOVNTSS dword ptr [rbx], xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4A, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +000000000000018B f20f2b3b MOVNTSD qword ptr [rbx], xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4A, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +000000000000018F f20f78ff0a0a INSERTQ xmm7, xmm7, 0x0a, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4A, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000195 660f78c70a0a EXTRQ xmm7, 0x0a, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4A, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000019B 660f79ff EXTRQ xmm7, xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4A, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +000000000000019F f20f79ff INSERTQ xmm7, xmm7 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4A, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 6 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + +00000000000001A3 660f38103b PBLENDVB xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000001A8 660f38143b BLENDVPS xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000001AD 660f38153b BLENDVPD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +00000000000001B2 660f38173b PTEST xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000001B7 660f38203b PMOVSXBW xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000001BC 660f38213b PMOVSXBD xmm7, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +00000000000001C1 660f38223b PMOVSXBQ xmm7, word ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + +00000000000001C6 660f38233b PMOVSXWD xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000001CB 660f38243b PMOVSXWQ xmm7, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +00000000000001D0 660f38253b PMOVSXDQ xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000001D5 660f38283b PMULDQ xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000001DA 660f38293b PCMPEQQ xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000001DF 660f382a3b MOVNTDQA xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000001E4 660f382b3b PACKUSDW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +00000000000001E9 660f38303b PMOVZXBW xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000001EE 660f38313b PMOVZXBD xmm7, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +00000000000001F3 660f38323b PMOVZXBQ xmm7, word ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + +00000000000001F8 660f38333b PMOVZXWD xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +00000000000001FD 660f38343b PMOVZXWQ xmm7, dword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + +0000000000000202 660f38353b PMOVZXDQ xmm7, qword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + +0000000000000207 660f38373b PCMPGTQ xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE42, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 20 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000020C 660f38383b PMINSB xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000211 660f38393b PMINSD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000216 660f383a3b PMINUW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000021B 660f383b3b PMINUD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000220 660f383c3b PMAXSB xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000225 660f383d3b PMAXSD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000022A 660f383e3b PMAXUW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000022F 660f383f3b PMAXUD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000234 660f38403b PMULLD xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000239 660f38413b PHMINPOSUW xmm7, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000023E 660f3a083b0a ROUNDPS xmm7, xmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000244 660f3a093b0a ROUNDPD xmm7, xmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000024A 660f3a0a3b0a ROUNDSS xmm7, dword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000250 660f3a0b3b0a ROUNDSD xmm7, qword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000256 660f3a0c3b0a BLENDPS xmm7, xmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000025C 660f3a0d3b0a BLENDPD xmm7, xmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000262 660f3a0e3b0a PBLENDW xmm7, xmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000268 660f3a143b0a PEXTRB byte ptr [rbx], xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000026E 660f3a14fa0a PEXTRB edx, xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000274 660f3a153b0a PEXTRW word ptr [rbx], xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 3, + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000027A 660fc5d70a PEXTRW edx, xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE2, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: edx, bit: 26 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000027F 660f3a16fa0a PEXTRD edx, xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000285 66480f3a16fa0a PEXTRQ rdx, xmm7, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000028C 66480f3a17fa0a EXTRACTPS edx, xmm7, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000293 660f3a203b0a PINSRB xmm7, byte ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000299 660f3a20fa0a PINSRB xmm7, edx, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000029F 660f3a213b0a INSERTPS xmm7, dword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000002A5 660f3a21ff0a INSERTPS xmm7, xmm7, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000002AB 660f3a22fa0a PINSRD xmm7, edx, 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000002B1 66480f3a22fa0a PINSRQ xmm7, rdx, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000002B8 660f3a403b0a DPPS xmm7, xmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000002BE 660f3a413b0a DPPD xmm7, xmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000002C4 660f3a423b0a MPSADBW xmm7, xmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE4, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 19 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000002CA 660f3a603b0a PCMPESTRM xmm7, xmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE42, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 20 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 5, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 6, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000002D0 660f3a613b0a PCMPESTRI xmm7, xmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE42, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 20 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 5, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 6, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000002D6 660f3a623b0a PCMPISTRM xmm7, xmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE42, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 20 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000002DC 660f3a633b0a PCMPISTRI xmm7, xmmword ptr [rbx], 0x0a + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: SSE42, Ins cat: SSE, CET tracked: no + CPUID leaf: 0x00000001, reg: ecx, bit: 20 + Exception class: SSE/VEX, exception type: 4 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + diff --git a/bddisasm_test/special/amx_64 b/bddisasm_test/special/amx_64 new file mode 100644 index 0000000000000000000000000000000000000000..4e20139e9f7884dcf8d8f096bdf3fc08828ec24b GIT binary patch literal 252 zcmX@|s3Pvb1SmKHGazKDkvUb!oB~fIWrZjlZx$q}ViaBx3a`++ ag#iQ*_7!7@6k&)IcpgB~fXev+lK}wb*MoNe literal 0 HcmV?d00001 diff --git a/bddisasm_test/special/amx_64.asm b/bddisasm_test/special/amx_64.asm new file mode 100644 index 0000000..4ec0052 --- /dev/null +++ b/bddisasm_test/special/amx_64.asm @@ -0,0 +1,46 @@ + bits 64 + + ; srcdest == src1, src1 == src2 or srcdest == src2 => #UD. + db 0xc4, 0xe2, 0x78, 0x5e, 0xC0 ; TDPBUUD tmm0, tmm0, tmm0 + db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 + db 0xc4, 0xe2, 0x78, 0x5e, 0xC1 ; TDPBUUD tmm0, tmm1, tmm0 + db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 + db 0xc4, 0xe2, 0x78, 0x5e, 0xC8 ; TDPBUUD tmm1, tmm0, tmm0 + db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 + db 0xc4, 0xe2, 0x70, 0x5e, 0xC0 ; TDPBUUD tmm0, tmm0, tmm1 + db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 + + ; tileload or tilestore without SIB => #UD. + db 0xc4, 0xe2, 0x79, 0x4b, 0x00 ; TILELOADDT1 tmm0, [rax] + db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 + db 0xc4, 0xe2, 0x7b, 0x4b, 0x00, ; TILELOADD tmm0, [rax] + db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 + db 0xc4, 0xe2, 0x7a, 0x4b, 0x00 ; TILESTORED tmm0, [rax+rax] + db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 + + ; using vex.vvvv != 0b1111 => #UD + db 0xc4, 0xe2, 0x70, 0x49, 0x00 ; LDTILECFG zmmword ptr [rax] + db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 + db 0xc4, 0xe2, 0x71, 0x49, 0x00 ; STTILECFG zmmword ptr [rax] + db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 + + db 0xc4, 0xe2, 0x71, 0x4b, 0x04, 0x00 ; TILELOADDT1 tmm0, [rax+rax] + db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 + db 0xc4, 0xe2, 0x73, 0x4b, 0x04, 0x00 ; TILELOADD tmm0, [rax+rax] + db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 + db 0xc4, 0xe2, 0x72, 0x4b, 0x04, 0x00 ; TILESTORED tmm0, [rax+rax] + db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 + + db 0xc4, 0xe2, 0x71, 0x4b, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 ; TILELOADDT1 tmm0, [rax+rax+0] + db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 + db 0xc4, 0xe2, 0x73, 0x4b, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 ; TILELOADD tmm0, [rax+rax+0] + db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 + db 0xc4, 0xe2, 0x72, 0x4b, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 ; TILESTORED tmm0, [rax+rax+0] + db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 + + db 0xc4, 0xe2, 0x70, 0x49, 0xC0 ; TILERELEASE + db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 + db 0xc4, 0xe2, 0x73, 0x49, 0xC0 ; TILEZERO tmm0 + db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 + db 0xc4, 0xe2, 0x73, 0x49, 0xf8 ; TILEZERO tmm7 + db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 diff --git a/bddisasm_test/special/amx_64.result b/bddisasm_test/special/amx_64.result new file mode 100644 index 0000000..bbd869d --- /dev/null +++ b/bddisasm_test/special/amx_64.result @@ -0,0 +1,1860 @@ +0000000000000000 c4 db 0xc4 (0x80000005) +0000000000000001 e278 LOOP 0x7b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 8, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: IP, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000003 5e POP rsi + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: O, RegType: General Purpose, RegSize: 8, RegId: 6, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000004 c0909090909090 RCL byte ptr [rax-0x6f6f6f70], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 0, Displacement: 0xffffffff90909090, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000000B 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000000C 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000000D c4 db 0xc4 (0x80000005) +000000000000000E e278 LOOP 0x88 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 8, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: IP, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000010 5e POP rsi + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: O, RegType: General Purpose, RegSize: 8, RegId: 6, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000011 c1909090909090 RCL dword ptr [rax-0x6f6f6f70], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, Displacement: 0xffffffff90909090, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000018 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000019 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000001A c4 db 0xc4 (0x80000005) +000000000000001B e278 LOOP 0x95 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 8, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: IP, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000001D 5e POP rsi + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: O, RegType: General Purpose, RegSize: 8, RegId: 6, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +000000000000001E c8909090 ENTER 0x9090, 0x90 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I186, Ins cat: MISC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 5, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 4, RegCount: 1 + Operand: 4, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000022 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000023 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000024 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000025 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000026 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000027 c4 db 0xc4 (0x80000005) +0000000000000028 e270 LOOP 0x9a + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 8, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: IP, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000002A 5e POP rsi + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: O, RegType: General Purpose, RegSize: 8, RegId: 6, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +000000000000002B c0909090909090 RCL byte ptr [rax-0x6f6f6f70], 0x90 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 0, Displacement: 0xffffffff90909090, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000032 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000033 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000034 c4 db 0xc4 (0x80000002) +0000000000000035 e279 LOOP 0xb0 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 8, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: IP, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000037 4b009090909090 ADD byte ptr [r8-0x6f6f6f70], dl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 8, Displacement: 0xffffffff90909090, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 2, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000003E 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000003F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000040 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000041 c4 db 0xc4 (0x80000002) +0000000000000042 e27b LOOP 0xbf + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 8, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: IP, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000044 4b009090909090 ADD byte ptr [r8-0x6f6f6f70], dl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 8, Displacement: 0xffffffff90909090, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 2, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000004B 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000004C 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000004D 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000004E c4 db 0xc4 (0x80000002) +000000000000004F e27a LOOP 0xcb + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 8, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: IP, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000051 4b009090909090 ADD byte ptr [r8-0x6f6f6f70], dl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 8, Displacement: 0xffffffff90909090, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 2, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000058 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000059 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000005A 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000005B c4 db 0xc4 (0x80000032) +000000000000005C e270 LOOP 0xce + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 8, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: IP, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000005E 49009090909090 ADD byte ptr [r8-0x6f6f6f70], dl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 8, Displacement: 0xffffffff90909090, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 2, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000065 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000066 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000067 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000068 c4 db 0xc4 (0x80000032) +0000000000000069 e271 LOOP 0xdc + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 8, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: IP, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000006B 49009090909090 ADD byte ptr [r8-0x6f6f6f70], dl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 8, Displacement: 0xffffffff90909090, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 2, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000072 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000073 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000074 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000075 c4 db 0xc4 (0x80000032) +0000000000000076 e271 LOOP 0xe9 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 8, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: IP, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000078 4b0400 ADD al, 0x00 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000007B 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000007C 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000007D 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000007E 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000007F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000080 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000081 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000082 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000083 c4 db 0xc4 (0x80000032) +0000000000000084 e273 LOOP 0xf9 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 8, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: IP, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000086 4b0400 ADD al, 0x00 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000089 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000008A 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000008B 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000008C 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000008D 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000008E 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000008F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000090 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000091 c4 db 0xc4 (0x80000032) +0000000000000092 e272 LOOP 0x106 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 8, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: IP, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000094 4b0400 ADD al, 0x00 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000097 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000098 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000099 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000009A 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000009B 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000009C 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000009D 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000009E 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000009F c4 db 0xc4 (0x80000032) +00000000000000A0 e271 LOOP 0x113 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 8, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: IP, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000A2 4b8400 TEST byte ptr [r8], al + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000A5 0000 ADD byte ptr [rax], al + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000A7 0000 ADD byte ptr [rax], al + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000A9 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000AA 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000AB 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000AC 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000AD 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000AE 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000AF 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000B0 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000B1 c4 db 0xc4 (0x80000032) +00000000000000B2 e273 LOOP 0x127 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 8, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: IP, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000B4 4b8400 TEST byte ptr [r8], al + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000B7 0000 ADD byte ptr [rax], al + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000B9 0000 ADD byte ptr [rax], al + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000BB 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000BC 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000BD 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000BE 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000BF 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000C0 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000C1 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000C2 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000C3 c4 db 0xc4 (0x80000032) +00000000000000C4 e272 LOOP 0x138 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 8, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: IP, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000C6 4b8400 TEST byte ptr [r8], al + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: LOGIC, CET tracked: no + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000C9 0000 ADD byte ptr [rax], al + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000CB 0000 ADD byte ptr [rax], al + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000CD 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000CE 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000CF 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000D0 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000D1 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000D2 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000D3 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000D4 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000D5 c4 db 0xc4 (0x80000032) +00000000000000D6 e270 LOOP 0x148 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 8, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: IP, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000D8 49c0909090909090 RCL byte ptr [r8-0x6f6f6f70], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 8, Displacement: 0xffffffff90909090, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000E0 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000E1 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000E2 c4 db 0xc4 (0x80000032) +00000000000000E3 e273 LOOP 0x158 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 8, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: IP, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000E5 49c0909090909090 RCL byte ptr [r8-0x6f6f6f70], 0x90 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 8, Displacement: 0xffffffff90909090, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000ED 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000EE 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000EF c4 db 0xc4 (0x80000032) +00000000000000F0 e273 LOOP 0x165 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 8, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: IP, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000F2 49f8 CLC + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: FLAGOP, CET tracked: no + FLAGS access + CF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000F4 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000F5 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000F6 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000F7 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000F8 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000F9 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000FA 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +00000000000000FB 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + diff --git a/bddisasm_test/special/avx2gather_1_64 b/bddisasm_test/special/avx2gather_1_64 new file mode 100644 index 0000000000000000000000000000000000000000..50ff4897ef8f08be2b910b4dc499a86ca11366b1 GIT binary patch literal 10 RcmX@|XyU{vml*^Y7yuvY1V8`) literal 0 HcmV?d00001 diff --git a/bddisasm_test/special/avx2gather_1_64.asm b/bddisasm_test/special/avx2gather_1_64.asm new file mode 100644 index 0000000..721b9c9 --- /dev/null +++ b/bddisasm_test/special/avx2gather_1_64.asm @@ -0,0 +1,3 @@ + bits 64 + + vpgatherqq xmm2, [rbx+xmm2*8+0x1000], xmm13 diff --git a/bddisasm_test/special/avx2gather_1_64.result b/bddisasm_test/special/avx2gather_1_64.result new file mode 100644 index 0000000..8775939 --- /dev/null +++ b/bddisasm_test/special/avx2gather_1_64.result @@ -0,0 +1,84 @@ +0000000000000000 c4 db 0xc4 (0x80000031) +0000000000000001 e291 LOOP 0xffffffffffffff94 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 8, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: IP, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000003 91 XCHG eax, ecx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: O, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + +0000000000000004 94 XCHG eax, esp + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: O, RegType: General Purpose, RegSize: 4, RegId: 4, RegCount: 1 + +0000000000000005 d300 ROL dword ptr [rax], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000007 1000 ADC byte ptr [rax], al + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000009 00 db 0x00 (0x80000001) diff --git a/bddisasm_test/special/avx2gather_2_64 b/bddisasm_test/special/avx2gather_2_64 new file mode 100644 index 0000000000000000000000000000000000000000..a5398fa12d8aceb14405bac2be0dc6a607723e80 GIT binary patch literal 10 RcmX@|=;g#IzZnD=7yu)31i%0Q literal 0 HcmV?d00001 diff --git a/bddisasm_test/special/avx2gather_2_64.asm b/bddisasm_test/special/avx2gather_2_64.asm new file mode 100644 index 0000000..b0dd9a3 --- /dev/null +++ b/bddisasm_test/special/avx2gather_2_64.asm @@ -0,0 +1,3 @@ + bits 64 + + vpgatherqq xmm2, [rbx+xmm7*8+0x1000], xmm2 diff --git a/bddisasm_test/special/avx2gather_2_64.result b/bddisasm_test/special/avx2gather_2_64.result new file mode 100644 index 0000000..2012f82 --- /dev/null +++ b/bddisasm_test/special/avx2gather_2_64.result @@ -0,0 +1,98 @@ +0000000000000000 c4 db 0xc4 (0x80000031) +0000000000000001 e2e9 LOOP 0xffffffffffffffec + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 8, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: IP, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000003 91 XCHG eax, ecx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: O, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + +0000000000000004 94 XCHG eax, esp + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: O, RegType: General Purpose, RegSize: 4, RegId: 4, RegCount: 1 + +0000000000000005 fb STI + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: FLAGOP, CET tracked: no + FLAGS access + IF: 1, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000006 0010 ADD byte ptr [rax], dl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 2, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000008 0000 ADD byte ptr [rax], al + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + diff --git a/bddisasm_test/special/avx2gather_3_64 b/bddisasm_test/special/avx2gather_3_64 new file mode 100644 index 0000000000000000000000000000000000000000..18aa08c2beb7be044b7a3f3327b60f60d7396b85 GIT binary patch literal 10 RcmX@|=-|XDzZnD=7yu$N1egE- literal 0 HcmV?d00001 diff --git a/bddisasm_test/special/avx2gather_3_64.asm b/bddisasm_test/special/avx2gather_3_64.asm new file mode 100644 index 0000000..9b592cc --- /dev/null +++ b/bddisasm_test/special/avx2gather_3_64.asm @@ -0,0 +1,3 @@ + bits 64 + + vpgatherqq xmm2, [rbx+xmm7*8+0x1000], xmm7 diff --git a/bddisasm_test/special/avx2gather_3_64.result b/bddisasm_test/special/avx2gather_3_64.result new file mode 100644 index 0000000..15244b3 --- /dev/null +++ b/bddisasm_test/special/avx2gather_3_64.result @@ -0,0 +1,98 @@ +0000000000000000 c4 db 0xc4 (0x80000031) +0000000000000001 e2c1 LOOP 0xffffffffffffffc4 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: COND_BR, CET tracked: no + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Offset, Size: 8, RawSize: 1, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: IP, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000003 91 XCHG eax, ecx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: O, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + +0000000000000004 94 XCHG eax, esp + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: O, RegType: General Purpose, RegSize: 4, RegId: 4, RegCount: 1 + +0000000000000005 fb STI + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: FLAGOP, CET tracked: no + FLAGS access + IF: 1, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000006 0010 ADD byte ptr [rax], dl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 2, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000008 0000 ADD byte ptr [rax], al + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + diff --git a/bddisasm_test/special/cr8_32 b/bddisasm_test/special/cr8_32 new file mode 100644 index 0000000..e9646b2 --- /dev/null +++ b/bddisasm_test/special/cr8_32 @@ -0,0 +1 @@ + " \ No newline at end of file diff --git a/bddisasm_test/special/cr8_32.asm b/bddisasm_test/special/cr8_32.asm new file mode 100644 index 0000000..82e2c68 --- /dev/null +++ b/bddisasm_test/special/cr8_32.asm @@ -0,0 +1,8 @@ + bits 32 + + ; These should operate on CR8, as per AMD hack to make CR8 accessible outside long mode. + db 0xF0 + mov eax, cr0 + db 0xF0 + mov cr0, eax + \ No newline at end of file diff --git a/bddisasm_test/special/cr8_32.result b/bddisasm_test/special/cr8_32.result new file mode 100644 index 0000000..ab121af --- /dev/null +++ b/bddisasm_test/special/cr8_32.result @@ -0,0 +1,28 @@ +0000000000000000 f00f20c0 MOV eax, cr8 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Control, RegSize: 4, RegId: 8, RegCount: 1 + +0000000000000004 f00f22c0 MOV cr8, eax + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Control, RegSize: 4, RegId: 8, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + diff --git a/bddisasm_test/special/invalid_32 b/bddisasm_test/special/invalid_32 new file mode 100644 index 0000000..cbaca0c --- /dev/null +++ b/bddisasm_test/special/invalid_32 @@ -0,0 +1 @@ +ȐАؐ \ No newline at end of file diff --git a/bddisasm_test/special/invalid_32.asm b/bddisasm_test/special/invalid_32.asm new file mode 100644 index 0000000..1505370 --- /dev/null +++ b/bddisasm_test/special/invalid_32.asm @@ -0,0 +1,19 @@ + bits 32 + + db 0x0F, 0x01, 0xF8 ; SWAPGS + db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 + db 0x0F, 0x05 ; SYSCALL + db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 + db 0x0F, 0x07 ; SYSRET + db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 + db 0xF3, 0x0F, 0xAE, 0xC0 ; RDFSBASE eax + db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 + db 0xF3, 0x0F, 0xAE, 0xC8 ; RDGSBASE eax + db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 + db 0xF3, 0x0F, 0xAE, 0xD0 ; WRFSBASE eax + db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 + db 0xF3, 0x0F, 0xAE, 0xD8 ; WRGSBASE eax + db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 + + + \ No newline at end of file diff --git a/bddisasm_test/special/invalid_32.result b/bddisasm_test/special/invalid_32.result new file mode 100644 index 0000000..63d09f7 --- /dev/null +++ b/bddisasm_test/special/invalid_32.result @@ -0,0 +1,644 @@ +0000000000000000 0f db 0x0f (0x80000009) +0000000000000001 01f8 ADD eax, edi + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000003 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000004 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000005 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000006 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000007 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000008 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000009 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000000A 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000000B 0f05 LOADALL + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I486REAL, Ins cat: UNDOC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Bank, Size: -1, RawSize: -1, Encoding: S + +000000000000000D 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000000E 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000000F 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000010 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000011 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000012 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000013 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000014 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000015 0f07 LOADALLD + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I486REAL, Ins cat: UNDOC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Bank, Size: -1, RawSize: -1, Encoding: S + +0000000000000017 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000018 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000019 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000001A 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000001B 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000001C 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000001D 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000001E 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000001F f3 db 0xf3 (0x80000002) +0000000000000020 0f db 0x0f (0x80000002) +0000000000000021 ae SCASB + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, DF: t, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: yes, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000022 c0909090909090 RCL byte ptr [eax-0x6f6f6f70], 0x90 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 0, Displacement: 0xffffffff90909090, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000029 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000002A 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000002B f3 db 0xf3 (0x80000002) +000000000000002C 0f db 0x0f (0x80000002) +000000000000002D ae SCASB + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, DF: t, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: yes, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000002E c8909090 ENTER 0x9090, 0x90 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I186, Ins cat: MISC, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 5, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 4, RegCount: 1 + Operand: 4, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000032 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000033 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000034 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000035 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000036 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000037 f3 db 0xf3 (0x80000002) +0000000000000038 0f db 0x0f (0x80000002) +0000000000000039 ae SCASB + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, DF: t, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: yes, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000003A d09090909090 RCL byte ptr [eax-0x6f6f6f70], 1 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: ROTATE, CET tracked: no + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 0, Displacement: 0xffffffff90909090, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000040 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000041 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000042 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000043 f3 db 0xf3 (0x80000002) +0000000000000044 0f db 0x0f (0x80000002) +0000000000000045 ae SCASB + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: STRINGOP, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, DF: t, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: yes, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: S, String: yes, + Segment: 0, Base: 7, + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 7, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000046 d89090909090 FCOM st0, dword ptr [eax-0x6f6f6f70] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: X87, Ins cat: X87_ALU, CET tracked: no + FPU flags access + C0: m, C1: 0, C2: m, C3: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 10, RawSize: 10, Encoding: S, RegType: FP, RegSize: 10, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, Displacement: 0xffffffff90909090, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: System, RegSize: 2, RegId: 2, RegCount: 1 + +000000000000004C 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000004D 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000004E 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + diff --git a/bddisasm_test/special/invalid_64 b/bddisasm_test/special/invalid_64 new file mode 100644 index 0000000..ff60012 --- /dev/null +++ b/bddisasm_test/special/invalid_64 @@ -0,0 +1 @@ +'/7?ԐՐ`aꐐ \ No newline at end of file diff --git a/bddisasm_test/special/invalid_64.asm b/bddisasm_test/special/invalid_64.asm new file mode 100644 index 0000000..d65a06b --- /dev/null +++ b/bddisasm_test/special/invalid_64.asm @@ -0,0 +1,19 @@ + bits 64 + + db 0x06 ; PUSH es + db 0x07 ; POP es + db 0x0E ; PUSH cs + db 0x16 ; PUSH ss + db 0x17 ; POP ss + db 0x1E ; PUSH ds + db 0x1F ; POP ds + db 0x27 ; DAA + db 0x2F ; DAS + db 0x37 ; AAA + db 0x3F ; AAS + db 0xD4, 0x90 ; AAM + db 0xD5, 0x90 ; AAD + db 0x60 ; PUSHA + db 0x61 ; POPA + db 0x9A, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 ; CALL far + db 0xEA, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 ; JMP far diff --git a/bddisasm_test/special/invalid_64.result b/bddisasm_test/special/invalid_64.result new file mode 100644 index 0000000..9354bb6 --- /dev/null +++ b/bddisasm_test/special/invalid_64.result @@ -0,0 +1,233 @@ +0000000000000000 06 db 0x06 (0x80000009) +0000000000000001 07 db 0x07 (0x80000009) +0000000000000002 0e db 0x0e (0x80000009) +0000000000000003 16 db 0x16 (0x80000009) +0000000000000004 17 db 0x17 (0x80000009) +0000000000000005 1e db 0x1e (0x80000009) +0000000000000006 1f db 0x1f (0x80000009) +0000000000000007 27 db 0x27 (0x80000009) +0000000000000008 2f db 0x2f (0x80000009) +0000000000000009 37 db 0x37 (0x80000009) +000000000000000A 3f db 0x3f (0x80000009) +000000000000000B d4 db 0xd4 (0x80000009) +000000000000000C 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000000D d5 db 0xd5 (0x80000009) +000000000000000E 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000000F 60 db 0x60 (0x80000009) +0000000000000010 61 db 0x61 (0x80000009) +0000000000000011 9a db 0x9a (0x80000009) +0000000000000012 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000013 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000014 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000015 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000016 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000017 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000018 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000019 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000001A ea db 0xea (0x80000009) +000000000000001B 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000001C 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000001D 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000001E 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000001F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000020 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000021 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000022 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + diff --git a/bddisasm_test/special/long_64 b/bddisasm_test/special/long_64 new file mode 100644 index 0000000..b0e5f66 --- /dev/null +++ b/bddisasm_test/special/long_64 @@ -0,0 +1 @@ +eKfeK \ No newline at end of file diff --git a/bddisasm_test/special/long_64.asm b/bddisasm_test/special/long_64.asm new file mode 100644 index 0000000..3dea4fa --- /dev/null +++ b/bddisasm_test/special/long_64.asm @@ -0,0 +1,9 @@ + bits 64 + + xacquire lock add qword [gs:r15 + r14 * 8 + 0x7FFFFFFF], 0xBDBDBDBD + db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 + + ; This is invalid, as its more than 15 bytes long. + db 0x66 + xacquire lock add qword [gs:r15 + r14 * 8 + 0x7FFFFFFF], 0xBDBDBDBD + db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 \ No newline at end of file diff --git a/bddisasm_test/special/long_64.result b/bddisasm_test/special/long_64.result new file mode 100644 index 0000000..6a442bb --- /dev/null +++ b/bddisasm_test/special/long_64.result @@ -0,0 +1,229 @@ +0000000000000000 f2f0654b8184f7ffffff7fbdbdbdbd XACQUIRE LOCK ADD qword ptr gs:[r15+r14*8+0x7fffffff], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 5, Base: 15, Index: 14 * 8, Displacement: 0x000000007fffffff, + Operand: 1, Acc: R-, Type: Immediate, Size: 8, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000000F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000010 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000011 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000012 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000013 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000014 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000015 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000016 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000017 66 db 0x66 (0x80000003) +0000000000000018 f2f0654b8184f7ffffff7fbdbdbdbd XACQUIRE LOCK ADD qword ptr gs:[r15+r14*8+0x7fffffff], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: ARITH, CET tracked: no + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: yes + HLE: yes, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 5, Base: 15, Index: 14 * 8, Displacement: 0x000000007fffffff, + Operand: 1, Acc: R-, Type: Immediate, Size: 8, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000027 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000028 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000029 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000002A 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000002B 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000002C 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000002D 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000002E 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + diff --git a/bddisasm_test/special/movcrdr_64 b/bddisasm_test/special/movcrdr_64 new file mode 100644 index 0000000000000000000000000000000000000000..f1c553f608dfc7d62188aa9b00d0d7d4f965aa65 GIT binary patch literal 68 zcmXBIK@k8j2m~=4tOX8?R9Yn<329|Yp1~V8{1kp`phku!v=L1hF%cWtq>&T(;{lJv B6iEO8 literal 0 HcmV?d00001 diff --git a/bddisasm_test/special/movcrdr_64.asm b/bddisasm_test/special/movcrdr_64.asm new file mode 100644 index 0000000..3db731a --- /dev/null +++ b/bddisasm_test/special/movcrdr_64.asm @@ -0,0 +1,19 @@ + bits 64 + + ; MOV cr/dr encoded with memory simply forces the r/m to register. No memory is interpreted. + db 0x0F, 0x20, 0xC0 ; MOV rax, cr0 + db 0x0F, 0x20, 0x00 ; MOV rax, cr0 + db 0x0F, 0x20, 0x40, 0x90 ; MOV rax, cr0 followed by NOP + db 0x0F, 0x20, 0x80, 0x90, 0x90, 0x90, 0x90 ; MOV rax, cr0 followed by 4 x NOP + db 0x0F, 0x21, 0xC0 + db 0x0F, 0x21, 0x00 + db 0x0F, 0x21, 0x40, 0x90 + db 0x0F, 0x21, 0x80, 0x90, 0x90, 0x90, 0x90 + db 0x0F, 0x22, 0xC0 + db 0x0F, 0x22, 0x00 + db 0x0F, 0x22, 0x40, 0x90 + db 0x0F, 0x22, 0x80, 0x90, 0x90, 0x90, 0x90 + db 0x0F, 0x23, 0xC0 + db 0x0F, 0x23, 0x00 + db 0x0F, 0x23, 0x40, 0x90 + db 0x0F, 0x23, 0x80, 0x90, 0x90, 0x90, 0x90 \ No newline at end of file diff --git a/bddisasm_test/special/movcrdr_64.result b/bddisasm_test/special/movcrdr_64.result new file mode 100644 index 0000000..1e59eff --- /dev/null +++ b/bddisasm_test/special/movcrdr_64.result @@ -0,0 +1,464 @@ +0000000000000000 0f20c0 MOV rax, cr0 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Control, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000003 0f2000 MOV rax, cr0 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Control, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000006 0f2040 MOV rax, cr0 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Control, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000009 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000000A 0f2080 MOV rax, cr0 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Control, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000000D 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000000E 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000000F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000010 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000011 0f21c0 MOV rax, dr0 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Debug, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000014 0f2100 MOV rax, dr0 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Debug, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000017 0f2140 MOV rax, dr0 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Debug, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000001A 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000001B 0f2180 MOV rax, dr0 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Debug, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000001E 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000001F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000020 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000021 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000022 0f22c0 MOV cr0, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Control, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000025 0f2200 MOV cr0, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Control, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000028 0f2240 MOV cr0, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Control, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000002B 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000002C 0f2280 MOV cr0, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Control, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000002F 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000030 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000031 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000032 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000033 0f23c0 MOV dr0, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Debug, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000036 0f2300 MOV dr0, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Debug, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000039 0f2340 MOV dr0, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Debug, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000003C 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000003D 0f2380 MOV dr0, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Debug, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000040 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000041 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000042 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000043 90 NOP + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + diff --git a/bddisasm_test/special/only_32 b/bddisasm_test/special/only_32 new file mode 100644 index 0000000..30eedc7 --- /dev/null +++ b/bddisasm_test/special/only_32 @@ -0,0 +1 @@ +cfc'/7?ԐՐ`aꐐ \ No newline at end of file diff --git a/bddisasm_test/special/only_32.asm b/bddisasm_test/special/only_32.asm new file mode 100644 index 0000000..481267d --- /dev/null +++ b/bddisasm_test/special/only_32.asm @@ -0,0 +1,21 @@ + bits 32 + + db 0x63, 0xC1 ; ARPL cx, ax + db 0x66, 0x63, 0xC1 ; ARPL cx, ax + db 0x06 ; PUSH es + db 0x07 ; POP es + db 0x0E ; PUSH cs + db 0x16 ; PUSH ss + db 0x17 ; POP ss + db 0x1E ; PUSH ds + db 0x1F ; POP ds + db 0x27 ; DAA + db 0x2F ; DAS + db 0x37 ; AAA + db 0x3F ; AAS + db 0xD4, 0x90 ; AAM + db 0xD5, 0x90 ; AAD + db 0x60 ; PUSHA + db 0x61 ; POPA + db 0x9A, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 ; CALL far + db 0xEA, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 ; JMP far diff --git a/bddisasm_test/special/only_32.result b/bddisasm_test/special/only_32.result new file mode 100644 index 0000000..a97233d --- /dev/null +++ b/bddisasm_test/special/only_32.result @@ -0,0 +1,353 @@ +0000000000000000 63c1 ARPL cx, ax + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I286PROT, Ins cat: SYSTEM, CET tracked: no + FLAGS access + ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000002 6663c1 ARPL cx, ax + DSIZE: 16, ASIZE: 32, VLEN: - + ISA Set: I286PROT, Ins cat: SYSTEM, CET tracked: no + FLAGS access + ZF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000005 06 PUSH es + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000006 07 POP es + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000007 0e PUSH cs + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000008 16 PUSH ss + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 1, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000009 17 POP ss + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +000000000000000A 1e PUSH ds + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +000000000000000B 1f POP ds + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: POP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +000000000000000C 27 DAA + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DECIMAL, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: tm, ZF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000000D 2f DAS + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DECIMAL, CET tracked: no + FLAGS access + CF: tm, PF: m, AF: tm, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000000E 37 AAA + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DECIMAL, CET tracked: no + FLAGS access + CF: m, PF: u, AF: tm, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000000F 3f AAS + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DECIMAL, CET tracked: no + FLAGS access + CF: m, PF: u, AF: tm, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000010 d490 AAM 0x90 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DECIMAL, CET tracked: no + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 1, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000012 d590 AAD 0x90 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: DECIMAL, CET tracked: no + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 1, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000014 60 PUSHA + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: PUSH, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Memory, Size: 32, RawSize: 32, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000015 61 POPA + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I386, Ins cat: POP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000000016 9a909090909090 CALLF 0x9090:0x90909090 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: CALL, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Address, Size: 6, RawSize: 6, Encoding: D + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 4, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Shadow Stack: yes, + + +000000000000001D 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000001E 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +000000000000001F ea909090909090 JMPF 0x9090:0x90909090 + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: UNCOND_BR, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no + SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Address, Size: 6, RawSize: 6, Encoding: D + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000026 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + +0000000000000027 90 NOP + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: I86, Ins cat: NOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + diff --git a/bddisasm_test/special/only_64 b/bddisasm_test/special/only_64 new file mode 100644 index 0000000..a8d1065 --- /dev/null +++ b/bddisasm_test/special/only_64 @@ -0,0 +1 @@ +cfcHc \ No newline at end of file diff --git a/bddisasm_test/special/only_64.asm b/bddisasm_test/special/only_64.asm new file mode 100644 index 0000000..b30ca7f --- /dev/null +++ b/bddisasm_test/special/only_64.asm @@ -0,0 +1,15 @@ + bits 64 + + db 0x63, 0xC1 ; MOVSXD eax, cx + db 0x66, 0x63, 0xC1 ; MOVSXD eax, ecx + db 0x48, 0x63, 0xC1 ; MOVSXD rax, ecx + db 0x0F, 0x01, 0xF8 ; SWAPGS + db 0x0F, 0x05 ; SYSCALL + db 0x0F, 0x07 ; SYSRET + db 0xF3, 0x0F, 0xAE, 0xC0 ; RDFSBASE eax + db 0xF3, 0x0F, 0xAE, 0xC8 ; RDGSBASE eax + db 0xF3, 0x0F, 0xAE, 0xD0 ; WRFSBASE eax + db 0xF3, 0x0F, 0xAE, 0xD8 ; WRGSBASE eax + + + \ No newline at end of file diff --git a/bddisasm_test/special/only_64.result b/bddisasm_test/special/only_64.result new file mode 100644 index 0000000..c9b0ec0 --- /dev/null +++ b/bddisasm_test/special/only_64.result @@ -0,0 +1,162 @@ +0000000000000000 63c1 MOVSXD eax, ecx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: LONGMODE, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + +0000000000000002 6663c1 MOVSXD ax, cx + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: LONGMODE, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 1, RegCount: 1 + +0000000000000005 4863c1 MOVSXD rax, ecx + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: LONGMODE, Ins cat: DATAXFER, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + +0000000000000008 0f01f8 SWAPGS + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: LONGMODE, Ins cat: SYSTEM, CET tracked: no + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: -1073741567, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: -1073741567, RegCount: 1 + +000000000000000B 0f05 SYSCALL + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMD, Ins cat: SYSCALL, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 11 + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: -1073741695, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: -1073741694, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: -1073741692, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 5, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 11, RegCount: 1 + Operand: 6, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 7, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 8, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000000D 0f07 SYSRET + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMD, Ins cat: SYSRET, CET tracked: no + CPUID leaf: 0x80000001, reg: ecx, bit: 11 + FLAGS access + Entire register + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: -1073741695, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 11, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 5, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 6, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000000F f30faec0 RDFSBASE eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: RDWRFSGS, Ins cat: RDWRFSGS, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 0 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: -1073741568, RegCount: 1 + +0000000000000013 f30faec8 RDGSBASE eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: RDWRFSGS, Ins cat: RDWRFSGS, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 0 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: -1073741567, RegCount: 1 + +0000000000000017 f30faed0 WRFSBASE eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: RDWRFSGS, Ins cat: RDWRFSGS, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 0 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: -1073741568, RegCount: 1 + +000000000000001B f30faed8 WRGSBASE eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: RDWRFSGS, Ins cat: RDWRFSGS, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 0 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM: no, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: -1073741567, RegCount: 1 + diff --git a/bddisasm_test/test_all.py b/bddisasm_test/test_all.py new file mode 100644 index 0000000..52893a1 --- /dev/null +++ b/bddisasm_test/test_all.py @@ -0,0 +1,126 @@ +# +# Copyright (c) 2020 Bitdefender +# SPDX-License-Identifier: Apache-2.0 +# +import os +import sys +import glob + +total_tests = 0 +failed_tests = 0 + +def get_dict(ins): + d = {} + prefix = "" + + # Remove lines that don't contain tokens. + lines = ins.split("\n") + + # Main disassembly. + d["disasm"] = lines[0] + + for line in lines[1:]: + tokens = line.split(",") + for t in tokens: + val = t.split(":") + if len(val) != 2: + continue + a = val[0].strip(" ") + b = val[1].strip(" ") + if a == "Operand": + prefix = "op%s_" % b + a = prefix + a + d[a] = b + return d + +def compare_instruction(i1, i2): + x1 = get_dict(i1) + x2 = get_dict(i2) + for t in x1: + if not t in x2: + print(" ! ERROR: Token '%s', value '%s' missing from output!" % (t, x1[t])) + return False + if x1[t] != x2[t]: + print(" ! ERROR: Token '%s' value mismatch: expected '%s', got '%s'!" % (t, x1[t], x2[t])) + return False + for t in x2: + if not t in x1: + print(" ! WARNING: Extra token in result: '%s', value '%s'!" % (t, x2[t])) + + return True + +def compare_results(data1, data2): + ins1 = data1.split("\n\n") + ins2 = data2.split("\n\n") + if len(ins1) != len(ins2): + print(" ! Different number of instructions in output: expected %d, got %d!" % (len(ins1), len(ins2))) + return False + for i in range(0, len(ins1)): + if not compare_instruction(ins1[i], ins2[i]): + print(" ! ERROR: Instruction mismatch at %d!" % (i)) + return False + return True + +def test_dir(dir): + global total_tests + global failed_tests + + for f in glob.glob('%s\\*' % dir): + if -1 == f.find('.'): + if 0 < f.find('_16'): + mod = '-b16' + elif 0 < f.find('_32'): + mod = '-b32' + else: + mod = '-b64' + if 0 < f.find('_r0'): + mod += ' -k' + + print(' * Running test case %s...' % f) + os.system('disasm -exi %s -f %s >%s.temp' % (mod, f, f)) + try: + res = open('%s.result' % f).read() + except: + print(' ! No result file provided for test %s!' % f) + + try: + tmp = open('%s.temp' % f).read() + except: + print(' ! No result produced by test %s!' % f) + + total_tests += 1 + if not compare_results(res, tmp): + print(' **** FAILED! ****') + failed_tests += 1 + else: + print(' * Passed.') + + for f in glob.glob('%s\\*_decoded.bin' % dir): + os.remove(f) + for f in glob.glob('%s\\*.temp' % dir): + os.remove(f) + +def regenerate(dir): + for f in glob.glob('%s\\*' % dir): + if -1 == f.find('.'): + if 0 < f.find('_16'): + mod = '-b16' + elif 0 < f.find('_32'): + mod = '-b32' + else: + mod = '-b64' + if 0 < f.find('_r0'): + mod += ' -k' + + print(' * Regenerating test case %s...' % f) + os.system('disasm -exi %s -f %s >%s.result' % (mod, f, f)) + + for f in glob.glob('%s\\*_decoded.bin' % dir): + os.remove(f) + +for dn in glob.glob("*"): + if not os.path.isdir(dn): + continue + print('Testing %s...' % dn) + test_dir(dn) +print("Ran %d tests, %d failed" % (total_tests, failed_tests)) \ No newline at end of file diff --git a/bdshemu/Makefile b/bdshemu/Makefile new file mode 100644 index 0000000..5fe016f --- /dev/null +++ b/bdshemu/Makefile @@ -0,0 +1,123 @@ +.PHONY: clean + +SRC_FILES := bdshemu.c + +OBJECTS := $(SRC_FILES:.c=.o) + +INCLUDES := -I. -I../inc -I../bddisasm/include -I../inc/bdshemu + +ifeq ($(PLATFORM),) + PLATFORM := x64 +endif + +ifeq ($(RELEASE),y) + CONFIGURATION := Release +else + CONFIGURATION := Debug +endif + +ifeq ($(PREFIX),) + PREFIX := /usr/local +endif + +DEFINES := -D_LIB -DAMD64 -DXEN + +INT_DIR := ../_intdir/bdshemu/$(PLATFORM)/$(CONFIGURATION) + +DEP_DIR := $(INT_DIR)/.d + +OUT_DIR := ../bin/$(PLATFORM)/$(CONFIGURATION) + +OBJECTS_PATH := $(addprefix $(INT_DIR)/, $(OBJECTS)) + +LIB_NAME := libbdshemu.a + +WARNINGS_ENABLE := -Wall -Wextra -Wshadow -Wstrict-overflow \ + -Wframe-larger-than=3072 -Wstack-usage=3072 + +WARNINGS_DISABLE := -Wno-missing-field-initializers \ + -Wno-missing-braces \ + -Wno-unused-function \ + -Wno-unused-variable \ + -Wno-unknown-pragmas \ + -Wno-format \ + -Wno-multichar + +# Some warnings are compiler-specific, some version-specific +ifeq (,$(findstring clang,$(CC))) + CC_VERSION_MAJOR = $(shell $(CC) -dumpversion | cut -d '.' -f1) + CC_VERSION_GT_4 = $(shell [ $(CC_VERSION_MAJOR) -gt 4 ] && echo true) + CC_VERSION_GT_5 = $(shell [ $(CC_VERSION_MAJOR) -gt 5 ] && echo true) + + ifeq (true,$(CC_VERSION_GT_4)) + WARNINGS_DISABLE += -Wno-incompatible-pointer-types + endif + + ifeq (true,$(CC_VERSION_GT_5)) + WARNINGS_ENABLE += -Wshift-overflow=2 \ + -Wnull-dereference \ + -Wduplicated-cond + endif +else + WARNINGS_DISABLE += -Wno-typedef-redefinition \ + -Wno-missing-braces \ + -Wno-incompatible-pointer-types \ + -Wno-missing-field-initializers +endif + +DEPFLAGS = -MT $@ -MMD -MP -MF $(DEP_DIR)/$*.Td + +CFLAGS = -pipe -std=c11 -fpic -fno-strict-aliasing \ + -D_REENTRANT -fstack-protector -ffunction-sections -fdata-sections \ + $(WARNINGS_ENABLE) $(WARNINGS_DISABLE) $(DEFINES) $(INCLUDES) + +ifeq ($(RELEASE),y) + CFLAGS += -Ofast -g3 -DNDEBUG -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=1 +else + CFLAGS += -O0 -g3 -D_DEBUG -DDEBUG +endif + +all: $(LIB_NAME) + +# Here it will link the objects created below in the final .a +$(LIB_NAME): $(OBJECTS_PATH) + @mkdir -p $(OUT_DIR) + @ar rcs $(OUT_DIR)/$(LIB_NAME) $(OBJECTS_PATH) + @echo Shemu library in $(OUT_DIR)/$(LIB_NAME) + +# We need to mkdir inside the rule, so each subfolder gets created, +# and avoiding conflicts: +# ./linux/example.c => $(INT_DIR)/linux/example.o +# ./example.c => $(INT_DIR)/example.o +$(INT_DIR)/%.o: %.c $(DEP_DIR)/%.d + @mkdir -p $(dir $@) + @mkdir -p $(dir $(DEP_DIR)/$<) >/dev/null + @echo $< + @$(CC) $(DEPFLAGS) $(CFLAGS) -c $< -o $@ + @mv -f $(DEP_DIR)/$*.Td $(DEP_DIR)/$*.d + +# So 'make' won't fail if the dependecy file doesn't exist +$(DEP_DIR)/%.d: ; + +# Don't delete the dependecy files +.PRECIOUS: $(DEP_DIR)/%.d + +# Include all the dependecy files (this will trigger a rebuild if a header is changed) +-include $(patsubst %,$(DEP_DIR)/%.d,$(basename $(SRC_FILES))) + +clean_lib_file: + @rm $(OUT_DIR)/$(LIB_NAME) 2>/dev/null ||: + +clean_int_dir: + @rm -r $(INT_DIR) 2>/dev/null ||: + +clean_dep_dir: + @rm -r $(DEP_DIR) 2>/dev/null ||: + +clean: clean_lib_file clean_int_dir clean_dep_dir + +install: all + install -d $(DESTDIR)$(PREFIX)/lib/ + install -m 644 $(OUT_DIR)/$(LIB_NAME) $(DESTDIR)$(PREFIX)/lib/ + install -d $(DESTDIR)$(PREFIX)/include/bddisasm/bdshemu/ + cp -r ../inc/bdshemu/* $(DESTDIR)$(PREFIX)/include/bddisasm/bdshemu/ \ No newline at end of file diff --git a/bdshemu/bdshemu.c b/bdshemu/bdshemu.c new file mode 100644 index 0000000..a39b16c --- /dev/null +++ b/bdshemu/bdshemu.c @@ -0,0 +1,2712 @@ +/* + * Copyright (c) 2020 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +// +// bdshemu.c +// + + +#include "nd_crt.h" +#include "bddisasm.h" +#include "bdshemu/bdshemu.h" + + +// +// A generic emulator value. +// +typedef struct _SHEMU_VALUE +{ + union + { + uint8_t Bytes[ND_MAX_REGISTER_SIZE]; + uint16_t Words[ND_MAX_REGISTER_SIZE / sizeof(uint16_t)]; + uint32_t Dwords[ND_MAX_REGISTER_SIZE / sizeof(uint32_t)]; + uint64_t Qwords[ND_MAX_REGISTER_SIZE / sizeof(uint64_t)]; + + struct + { + uint16_t FpuControlWord; + uint16_t FpuStatusWord; + uint16_t FpuTagWord; + uint16_t Rsvd; + uint32_t FpuDataPointer; + uint32_t FpuInstructionPointer; + uint32_t FpuLastInstructionOpcode; + } FpuEnvironment; + + struct + { + uint16_t FpuControlWord; + uint16_t FpuStatuwsWord; + uint16_t FpuTagWord; + uint16_t FpuOpcode; + uint64_t FpuRip; + uint64_t FpuDataPointer; + uint32_t Mxcsr; + uint32_t MxcsrMask; + } XsaveArea; + + struct + { + uint16_t Limit; + uint64_t Base; + } Descriptor; + + } Value; + + ND_OPERAND_SIZE Size; +} SHEMU_VALUE, *PSHEMU_VALUE; + + +enum +{ + FM_LOGIC, + FM_SHL, + FM_SHR, + FM_SAR, + FM_SUB, + FM_ADD, +} FLAGS_MODE; + + +#define GET_OP(ctx, op, val) { \ + SHEMU_STATUS status = ShemuGetOperandValue(ctx, op, val); \ + if (SHEMU_SUCCESS != status) \ + { \ + return status; \ + } \ +} + +#define SET_OP(ctx, op, val) { \ + SHEMU_STATUS status = ShemuSetOperandValue(ctx, op, val); \ + if (SHEMU_SUCCESS != status) \ + { \ + return status; \ + } \ +} + +#define GET_FLAG(ctx, flg) (!!((ctx)->Registers.RegFlags & (flg))) +#define SET_FLAG(ctx, flg, val) ((ctx)->Registers.RegFlags = (val) ? ((ctx)->Registers.RegFlags | flg) : \ + ((ctx)->Registers.RegFlags & ~(flg))) +#define SET_FLAGS(ctx, dst, src1, src2, fm) ShemuSetFlags(ctx, dst.Value.Qwords[0], src.Value.Qwords[0], \ + src2.Value.Qwords[0], dst.Size, fm) + +#define SHELLBMP(ctx) ((ctx)->Intbuf) +#define STACKBMP(ctx) ((ctx)->Intbuf + (ctx)->ShellcodeSize) +#define SHELLBMP_SIZE(ctx) ((ctx)->ShellcodeSize) +#define STACKBMP_SIZE(ctx) ((ctx)->StackSize) +#define MAX(a, b) ((a) < (b) ? (b) : (a)) +#define MIN(a, b) ((a) > (b) ? (b) : (a)) + + +// +// ShemuPrintf - simple version +// +static void +shemu_printf( + SHEMU_CONTEXT *Context, + char *formatstring, + ... + ) +{ + char buff[1024]; + va_list args; + + if (NULL == Context->Log) + { + return; + } + + nd_memzero(buff, sizeof(buff)); + va_start(args, formatstring); + + nd_vsnprintf_s(buff, sizeof(buff), sizeof(buff) - 1, formatstring, args); + + va_end(args); + + Context->Log(buff); +} + + +// +// shemu_memcpy +// +static void * +shemu_memcpy( + void *Dest, + const void *Source, + size_t Size + ) +{ + void *start = Dest; + uint32_t index = 0; + + if (NULL == Dest) + { + return NULL; + } + + if (NULL == Source) + { + return NULL; + } + + while (Size--) + { + *(char *)Dest = *((char *)Source + index); + Dest = (char *)Dest + 1; + index++; + } + + return start; +} + + +// +// ShemuBts +// +inline static uint8_t +ShemuBts( + uint8_t *BitMap, + uint64_t Position + ) +{ + uint8_t old; + + old = (BitMap[Position / 8] >> (Position % 8)) & 1; + + BitMap[Position / 8] |= 1 << (Position % 8); + + return old; +} + + +// +// ShemuBtr +// +inline static uint8_t +ShemuBtr( + uint8_t *BitMap, + uint64_t Position + ) +{ + uint8_t old; + + old = (BitMap[Position / 8] >> (Position % 8)) & 1; + + BitMap[Position / 8] &= ~(1 << (Position % 8)); + + return old; +} + + +// +// ShemuBt +// +inline static uint8_t +ShemuBt( + uint8_t *BitMap, + uint64_t Position + ) +{ + return (BitMap[Position / 8] >> (Position % 8)) & 1; +} + + +// +// ShemuSetBits +// +static void +ShemuSetBits( + uint8_t *Bitmap, + uint64_t Start, + uint64_t Size, + bool Val + ) +// +// No size validations here; the caller has to make sure the ranges are all good. +// +{ + uint64_t i; + + for (i = 0; i < Size; i++) + { + if (Val) + { + ShemuBts(Bitmap, (uint64_t)(Start + i)); + } + else + { + ShemuBtr(Bitmap, (uint64_t)(Start + i)); + } + } +} + + +// +// ShemuAllBitsSet +// +static bool +ShemuAllBitsSet( + uint8_t *Bitmap, + uint64_t Start, + uint32_t Size + ) +// +// No size validations here; the caller has to make sure the ranges are all good. +// +{ + uint32_t i; + + for (i = 0; i < Size; i++) + { + if (!ShemuBt(Bitmap, (uint64_t)(Start + i))) + { + return false; + } + } + + return true; +} + + +// +// ShemuAnyBitsSet +// +static bool +ShemuAnyBitsSet( + uint8_t *Bitmap, + uint64_t Start, + uint32_t Size + ) +// +// No size validations here; the caller has to make sure the ranges are all good. +// +{ + uint32_t i; + + for (i = 0; i < Size; i++) + { + if (ShemuBt(Bitmap, (uint64_t)(Start + i))) + { + return true; + } + } + + return false; +} + + +// +// ShemuSetFlags +// +static void +ShemuSetFlags( + SHEMU_CONTEXT *Context, + uint64_t Dst, + uint64_t Src1, + uint64_t Src2, + ND_OPERAND_SIZE Size, + uint8_t FlagsMode + ) +{ + uint8_t pfArr[16] = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 }; + + // Mask the operands with their respective size. + Dst = ND_TRIM(Size, Dst); + Src1 = ND_TRIM(Size, Src1); + Src2 = ND_TRIM(Size, Src2); + + // PF set if the first bytes has an even number of 1 bits. + if ((pfArr[Dst & 0xF] + pfArr[(Dst >> 4) & 0xF]) % 2 == 0) + { + Context->Registers.RegFlags |= REG_RFLAG_PF; + } + else + { + Context->Registers.RegFlags &= ~REG_RFLAG_PF; + } + + // ZF set if the result is zero. + if (Dst == 0) + { + Context->Registers.RegFlags |= REG_RFLAG_ZF; + } + else + { + Context->Registers.RegFlags &= ~REG_RFLAG_ZF; + } + + // SF is set if the sign flag is set. + if (ND_GET_SIGN(Size, Dst) != 0) + { + Context->Registers.RegFlags |= REG_RFLAG_SF; + } + else + { + Context->Registers.RegFlags &= ~REG_RFLAG_SF; + } + + // OF and CF are handled differently for some instructions. + if (FM_LOGIC == FlagsMode) + { + // OF and CF are cleared on logic instructions. + Context->Registers.RegFlags &= ~(REG_RFLAG_OF | REG_RFLAG_CF); + } + else if (FM_SHL == FlagsMode) + { + // CF is the last bit shifted out of the destination. + if (ND_GET_BIT(Src1, (Size * 8) - Src2)) + { + Context->Registers.RegFlags |= REG_RFLAG_CF; + } + else + { + Context->Registers.RegFlags &= ~REG_RFLAG_CF; + } + + if (Src2 == 1) + { + if (ND_GET_BIT(Size * 8 - 1, Dst) ^ ND_GET_BIT(Src1, (Size * 8) - Src2)) + { + Context->Registers.RegFlags |= REG_RFLAG_OF; + } + else + { + Context->Registers.RegFlags &= ~REG_RFLAG_OF; + } + } + } + else if (FM_SHR == FlagsMode) + { + // CF is the last bit shifted out of the destination. + if (ND_GET_BIT(Src1, Src2 - 1)) + { + Context->Registers.RegFlags |= REG_RFLAG_CF; + } + else + { + Context->Registers.RegFlags &= ~REG_RFLAG_CF; + } + + if (Src2 == 1) + { + if (ND_GET_BIT(Size * 8 - 1, Dst)) + { + Context->Registers.RegFlags |= REG_RFLAG_OF; + } + else + { + Context->Registers.RegFlags &= ~REG_RFLAG_OF; + } + } + } + else if (FM_SAR == FlagsMode) + { + // CF is the last bit shifted out of the destination. + if (ND_GET_BIT(Src1, Src2 - 1)) + { + Context->Registers.RegFlags |= REG_RFLAG_CF; + } + else + { + Context->Registers.RegFlags &= ~REG_RFLAG_CF; + } + + Context->Registers.RegFlags &= ~REG_RFLAG_OF; + } + else + { + // Set CF. + if ((FM_SUB == FlagsMode) && (Src1 < Src2)) + { + Context->Registers.RegFlags |= REG_RFLAG_CF; + } + else if ((FM_ADD == FlagsMode) && (Dst < Src1)) + { + Context->Registers.RegFlags |= REG_RFLAG_CF; + } + else + { + Context->Registers.RegFlags &= ~REG_RFLAG_CF; + } + + // Set OF. + if (FM_SUB == FlagsMode) + { + if ((ND_GET_SIGN(Size, Src1) && !ND_GET_SIGN(Size, Src2) && !ND_GET_SIGN(Size, Dst)) || + (!ND_GET_SIGN(Size, Src1) && ND_GET_SIGN(Size, Src2) && ND_GET_SIGN(Size, Dst))) + { + Context->Registers.RegFlags |= REG_RFLAG_OF; + } + else + { + Context->Registers.RegFlags &= ~REG_RFLAG_OF; + } + } + else if (FM_ADD == FlagsMode) + { + if (ND_GET_SIGN(Size, Src1) == ND_GET_SIGN(Size, Src2) && + ND_GET_SIGN(Size, Src1) != ND_GET_SIGN(Size, Dst)) + { + Context->Registers.RegFlags |= REG_RFLAG_OF; + } + else + { + Context->Registers.RegFlags &= ~REG_RFLAG_OF; + } + } + } +} + + +// +// ShemuEvalCondition +// +static bool +ShemuEvalCondition( + SHEMU_CONTEXT *Context, + uint8_t ConditionCode + ) +{ + switch (ConditionCode) + { + case ND_COND_OVERFLOW: // O + if (GET_FLAG(Context, REG_RFLAG_OF) == 1) + { + return true; + } + break; + case ND_COND_NOT(ND_COND_OVERFLOW): // NO + if (GET_FLAG(Context, REG_RFLAG_OF) == 0) + { + return true; + } + break; + case ND_COND_CARRY: // C/B/NAE + if (GET_FLAG(Context, REG_RFLAG_CF) == 1) + { + return true; + } + break; + case ND_COND_NOT(ND_COND_CARRY): // NC/NB/AE + if (GET_FLAG(Context, REG_RFLAG_CF) == 0) + { + return true; + } + break; + case ND_COND_ZERO: // E/Z + if (GET_FLAG(Context, REG_RFLAG_ZF) == 1) + { + return true; + } + break; + case ND_COND_NOT(ND_COND_ZERO): // NE/NZ + if (GET_FLAG(Context, REG_RFLAG_ZF) == 0) + { + return true; + } + break; + case ND_COND_BELOW_OR_EQUAL: // BE/NA + if ((GET_FLAG(Context, REG_RFLAG_CF) | (GET_FLAG(Context, REG_RFLAG_ZF))) == 1) + { + return true; + } + break; + case ND_COND_NOT(ND_COND_BELOW_OR_EQUAL): // A/NBE + if ((GET_FLAG(Context, REG_RFLAG_CF) | (GET_FLAG(Context, REG_RFLAG_ZF))) == 0) + { + return true; + } + break; + case ND_COND_SIGN: // S + if (GET_FLAG(Context, REG_RFLAG_SF) == 1) + { + return true; + } + break; + case ND_COND_NOT(ND_COND_SIGN): // NS + if (GET_FLAG(Context, REG_RFLAG_SF) == 0) + { + return true; + } + break; + case ND_COND_PARITY: // P + if (GET_FLAG(Context, REG_RFLAG_PF) == 1) + { + return true; + } + break; + case ND_COND_NOT(ND_COND_PARITY): // NP + if (GET_FLAG(Context, REG_RFLAG_PF) == 0) + { + return true; + } + break; + case ND_COND_LESS: // L/NGE + if ((GET_FLAG(Context, REG_RFLAG_SF) ^ GET_FLAG(Context, REG_RFLAG_OF)) == 1) + { + return true; + } + break; + case ND_COND_NOT(ND_COND_LESS): // NL/GE + if ((GET_FLAG(Context, REG_RFLAG_SF) ^ GET_FLAG(Context, REG_RFLAG_OF)) == 0) + { + return true; + } + break; + case ND_COND_LESS_OR_EQUAL: // LE/NG + if (((GET_FLAG(Context, REG_RFLAG_SF) ^ GET_FLAG(Context, REG_RFLAG_OF)) | + (GET_FLAG(Context, REG_RFLAG_ZF))) == 1) + { + return true; + } + break; + case ND_COND_NOT(ND_COND_LESS_OR_EQUAL): // NLE/G + if (((GET_FLAG(Context, REG_RFLAG_SF) ^ GET_FLAG(Context, REG_RFLAG_OF)) | + (GET_FLAG(Context, REG_RFLAG_ZF))) == 0) + { + return true; + } + break; + } + + return false; + +} + + +// +// ShemuIsShellcodePtr +// +inline static bool +ShemuIsShellcodePtr( + SHEMU_CONTEXT *Context, + uint64_t Gla, + uint32_t Size + ) +{ + return (Gla >= Context->ShellcodeBase && Gla < Context->ShellcodeBase + Context->ShellcodeSize && + Gla + Size > Context->ShellcodeBase && Gla + Size <= Context->ShellcodeBase + Context->ShellcodeSize); +} + + +// +// ShemuIsStackPtr +// +inline static bool +ShemuIsStackPtr( + SHEMU_CONTEXT *Context, + uint64_t Gla, + uint32_t Size +) +{ + return (Gla >= Context->StackBase && Gla < Context->StackBase + Context->StackSize && + Gla + Size > Context->StackBase && Gla + Size <= Context->StackBase + Context->StackSize); +} + + +// +// ShemuGetGprValue +// +static uint64_t +ShemuGetGprValue( + SHEMU_CONTEXT *Context, + uint32_t Reg, + uint32_t Size, + bool High8 + ) +{ + switch (Size) + { + case 1: + if (High8) + { + // AH, CH, DH or BH accessed. + return (*(&Context->Registers.RegRax + Reg - 4) >> 8) & 0xff; + } + else + { + return *(&Context->Registers.RegRax + Reg) & 0xff; + } + + case 2: + return *(&Context->Registers.RegRax + Reg) & 0xffff; + + case 4: + return *(&Context->Registers.RegRax + Reg) & 0xffffffff; + + default: + return *(&Context->Registers.RegRax + Reg); + } +} + + +// +// ShemuGetGprValue +// +static void +ShemuSetGprValue( + SHEMU_CONTEXT *Context, + uint32_t Reg, + uint32_t Size, + uint64_t Value, + bool High8 + ) +{ + switch (Size) + { + case 1: + if (High8) + { + // AH, CH, DH or BH accessed. + *((uint8_t *)(&Context->Registers.RegRax + Reg - 4) + 1) = Value & 0xFF; + } + else + { + *((uint8_t *)(&Context->Registers.RegRax + Reg)) = Value & 0xff; + } + break; + + case 2: + *((uint16_t *)(&Context->Registers.RegRax + Reg)) = Value & 0xffff; + break; + + case 4: + // Higher uint32_t is always set to zero. + *(&Context->Registers.RegRax + Reg) = Value & 0xffffffff; + break; + + default: + *(&Context->Registers.RegRax + Reg) = Value; + break; + } +} + + +// +// ShemuGetSegValue +// +static uint64_t +ShemuGetSegValue( + SHEMU_CONTEXT *Context, + uint32_t Reg + ) +{ + switch (Reg) + { + case REG_ES: + return Context->Segments.Es.Selector; + case REG_CS: + return Context->Segments.Cs.Selector; + case REG_SS: + return Context->Segments.Ss.Selector; + case REG_DS: + return Context->Segments.Ds.Selector; + case REG_FS: + return Context->Segments.Fs.Selector; + case REG_GS: + return Context->Segments.Gs.Selector; + } + + return 0; +} + + +// +// ShemuSetSegValue +// +static void +ShemuSetSegValue( + SHEMU_CONTEXT *Context, + uint32_t Reg, + uint16_t Value + ) +{ + switch (Reg) + { + case REG_ES: + Context->Segments.Es.Selector = Value; + break; + case REG_CS: + Context->Segments.Cs.Selector = Value; + break; + case REG_SS: + Context->Segments.Ss.Selector = Value; + break; + case REG_DS: + Context->Segments.Ds.Selector = Value; + break; + case REG_FS: + Context->Segments.Fs.Selector = Value; + break; + case REG_GS: + Context->Segments.Gs.Selector = Value; + break; + } +} + + +// +// ShemuGetSegBase +// +static uint64_t +ShemuGetSegBase( + SHEMU_CONTEXT *Context, + uint32_t Reg + ) +{ + switch (Reg) + { + case REG_ES: + return Context->Segments.Es.Base; + case REG_CS: + return Context->Segments.Cs.Base; + case REG_SS: + return Context->Segments.Ss.Base; + case REG_DS: + return Context->Segments.Ds.Base; + case REG_FS: + return Context->Segments.Fs.Base; + case REG_GS: + return Context->Segments.Gs.Base; + } + + return 0; +} + + +// +// ShemuComputeLinearAddress +// +static uint64_t +ShemuComputeLinearAddress( + SHEMU_CONTEXT *Context, + PND_OPERAND Operand + ) +{ + uint64_t gla = 0; + + // Memory operands usually have a segment. + if (Operand->Info.Memory.HasSeg) + { + gla += ShemuGetSegBase(Context, Operand->Info.Memory.Seg); + } + + if (Operand->Info.Memory.HasBase) + { + gla += ShemuGetGprValue(Context, Operand->Info.Memory.Base, Operand->Info.Memory.BaseSize, false); + } + + if (Operand->Info.Memory.HasIndex) + { + gla += ShemuGetGprValue(Context, Operand->Info.Memory.Index, Operand->Info.Memory.IndexSize, false) * + Operand->Info.Memory.Scale; + } + + // Note that this also handles the case where moffset (absolute addressing) is used, as HasDisp will be set when + // IsDirect is also set. + if (Operand->Info.Memory.HasDisp) + { + gla += Operand->Info.Memory.Disp; + } + + if (Operand->Info.Memory.IsRipRel) + { + gla += Context->Registers.RegRip; + } + + // Special handling for BT, BTR, BTS, BTC instructions with bitbase addressing. + if (Operand->Info.Memory.IsBitbase) + { + uint64_t bitbase, op1size, op2size, reg; + + op1size = Context->Instruction.Operands[0].Size; + op2size = Context->Instruction.Operands[1].Size; + + reg = ((uint64_t*)&Context->Registers.RegRax)[Context->Instruction.Operands[1].Info.Register.Reg]; + + // Note: only BT* with register source (NOT immediate) support bitbase addressing. + bitbase = ND_SIGN_EX(op2size, reg); + + if (bitbase & (1ULL << 63)) + { + gla -= ((~bitbase >> 3) & ~(op1size - 1)) + op1size; + } + else + { + gla += (bitbase >> 3) & ~(op1size - 1); + } + } + + // Special handling for stack operations: if we have a PUSH, we have to subtract the accessed size, as, in fact, + // [RSP - size] is accessed, not [RSP]. + if (Operand->Info.Memory.IsStack) + { + if (Operand->Access.Write || Operand->Access.CondWrite) + { + gla -= Operand->Size; + } + } + + return gla; +} + + +// +// ShemuGetMemValue +// +static SHEMU_STATUS +ShemuGetMemValue( + SHEMU_CONTEXT *Context, + uint64_t Gla, + uint32_t Size, + uint8_t *Value + ) +{ + uint8_t *addr; + uint32_t offset; + + if (ShemuIsShellcodePtr(Context, Gla, Size)) + { + addr = Context->Shellcode; + offset = (uint32_t)(Gla - Context->ShellcodeBase); + } + else if (ShemuIsStackPtr(Context, Gla, Size)) + { + addr = Context->Stack; + offset = (uint32_t)(Gla - Context->StackBase); + } + else + { + bool res = false; + + // We allow a maximum number of external memory accesses, due to performance reasons. + if (++Context->ExtMemAccess > Context->MemThreshold) + { + return SHEMU_ABORT_GLA_OUTSIDE; + } + + // NOTE: The accessed GLA may partially access an internal address (shellcode or stack) and an external address. + // Since the AccessMemory callback can be provided with the full SHEMU_CONTEXT, the integrator can choose how + // to handle those accesses; some options are: + // - Don't handle them at all, and return error (false); + // - Handle them by reading the actual memory value; this has the disadvantage that if the shellcode/stack + // portion has been modified due to emulation, the AccessMemory function would return the original memory + // value; + // - Handle them properly, by returning the emulated values for the internal addresses, and the external + // values for the external addresses. + // bdshemu does not care directly about this, and lets the integrator choose his own strategy. + if (NULL != Context->AccessMemory) + { + res = Context->AccessMemory(Context, Gla, Size, Value, false); + } + + if (res) + { + return SHEMU_SUCCESS; + } + + return SHEMU_ABORT_GLA_OUTSIDE; + } + + switch (Size) + { + case 1: + *Value = *(addr + offset); + break; + case 2: + *(uint16_t *)Value = *(uint16_t *)(addr + offset); + break; + case 4: + *(uint32_t *)Value = *(uint32_t *)(addr + offset); + break; + case 8: + *(uint64_t *)Value = *(uint64_t *)(addr + offset); + break; + default: + shemu_memcpy(Value, addr + offset, Size); + break; + } + + return SHEMU_SUCCESS; +} + + +// +// ShemuSetMemValue +// +static SHEMU_STATUS +ShemuSetMemValue( + SHEMU_CONTEXT *Context, + uint64_t Gla, + uint32_t Size, + uint8_t *Value + ) +{ + uint8_t *addr; + uint32_t offset; + + if (ShemuIsShellcodePtr(Context, Gla, Size)) + { + addr = Context->Shellcode; + offset = (uint32_t)(Gla - Context->ShellcodeBase); + } + else if (ShemuIsStackPtr(Context, Gla, Size)) + { + addr = Context->Stack; + offset = (uint32_t)(Gla - Context->StackBase); + } + else + { + bool res = false; + + // We allow a maximum number of external memory accesses, due to performance reasons. + if (++Context->ExtMemAccess > Context->MemThreshold) + { + return SHEMU_ABORT_GLA_OUTSIDE; + } + + // Handling external stores made by the shellcode can be done in a variety of ways by the integrator. Some + // of the solutions are: + // - Abort on external stores; this will cause the emulation to immediately stop; + // - Discard external stores; this is very simple, and it assumes that modified memory addresses will + // not be read later on by the shellcode; + // - Create a store-buffer like structure, where every external store is cached; when a load is issued on + // a previously written address, the value from the store-buffer can be returned; + // For obvious reasons, actually storing the value at the indicated address is a very, very bad idea. + if (NULL != Context->AccessMemory) + { + res = Context->AccessMemory(Context, Gla, Size, Value, true); + } + + if (res) + { + return SHEMU_SUCCESS; + } + + return SHEMU_ABORT_GLA_OUTSIDE; + } + + switch (Size) + { + case 1: + *(addr + offset) = *Value & 0xff; + break; + case 2: + *(uint16_t *)(addr + offset) = *(uint16_t *)Value & 0xffff; + break; + case 4: + *(uint32_t *)(addr + offset) = *(uint32_t *)Value & 0xffffffff; + break; + case 8: + *(uint64_t *)(addr + offset) = *(uint64_t *)Value; + break; + default: + shemu_memcpy(addr + offset, Value, Size); + break; + } + + return SHEMU_SUCCESS; +} + + +// +// IntWinShcSetOperandValue +// +static SHEMU_STATUS +ShemuGetOperandValue( + SHEMU_CONTEXT *Context, + uint32_t Operand, + SHEMU_VALUE *Value + ) +{ + SHEMU_STATUS status; + PND_OPERAND op = &Context->Instruction.Operands[Operand]; + + Value->Size = op->Size; + if (Value->Size > sizeof(Value->Value)) + { + return SHEMU_ABORT_OP_TOO_LARGE; + } + + if (op->Type == ND_OP_REG) + { + switch (op->Info.Register.Type) + { + case ND_REG_GPR: + Value->Value.Qwords[0] = ShemuGetGprValue(Context, op->Info.Register.Reg, op->Size, + op->Info.Register.IsHigh8); + break; + + case ND_REG_SEG: + Value->Value.Qwords[0] = ShemuGetSegValue(Context, op->Info.Register.Reg); + break; + + case ND_REG_MMX: + Value->Value.Qwords[0] = Context->MmxRegisters[op->Info.Register.Reg]; + break; + + case ND_REG_SSE: + shemu_memcpy(Value->Value.Bytes, + &Context->SseRegisters[op->Info.Register.Reg * ND_MAX_REGISTER_SIZE], + op->Size); + break; + + case ND_REG_RIP: + Value->Value.Qwords[0] = ND_TRIM(Value->Size, Context->Registers.RegRip); + break; + + case ND_REG_FLG: + Value->Value.Qwords[0] = Context->Registers.RegFlags; + break; + + case ND_REG_CR: + switch (op->Info.Register.Reg) + { + case REG_CR0: + Value->Value.Qwords[0] = Context->Registers.RegCr0; + break; + case REG_CR2: + Value->Value.Qwords[0] = Context->Registers.RegCr2; + break; + case REG_CR3: + Value->Value.Qwords[0] = Context->Registers.RegCr3; + break; + case REG_CR4: + Value->Value.Qwords[0] = Context->Registers.RegCr4; + break; + case REG_CR8: + Value->Value.Qwords[0] = Context->Registers.RegCr8; + break; + default: + return SHEMU_ABORT_REGISTER_NOT_SUPPORTED; + } + break; + + + default: + return SHEMU_ABORT_REGISTER_NOT_SUPPORTED; + } + } + else if (op->Type == ND_OP_MEM) + { + uint64_t gla = ShemuComputeLinearAddress(Context, op); + + if (op->Info.Memory.IsAG) + { + // Address generation instruction, the result is the linear address itself. + Value->Value.Qwords[0] = gla; + } + else + { + uint32_t offset; + uint8_t seg; + + if (Context->Ring == 3) + { + // User-mode TIB offset that contains the PEB address. + offset = Context->Mode == ND_CODE_32 ? 0x30 : 0x60; + seg = Context->Mode == ND_CODE_32 ? ND_PREFIX_G2_SEG_FS : ND_PREFIX_G2_SEG_GS; + } + else + { + // Kernel-mode KPCR offset that contains the current KTHREAD address. + offset = Context->Mode == ND_CODE_32 ? 0x124 : 0x188; + seg = Context->Mode == ND_CODE_32 ? ND_PREFIX_G2_SEG_FS : ND_PREFIX_G2_SEG_GS; + } + + // Check if this is a TIB/PCR access. Make sure the FS/GS register is used for the access, in order to avoid + // false positives where legitimate code accesses a linear TIB directly. + if (gla == Context->TibBase + offset && Context->Instruction.Seg == seg) + { + Context->Flags |= SHEMU_FLAG_TIB_ACCESS; + } + + // Check if we are reading a previously saved RIP. Ignore RET category, which naturally uses the saved RIP. + // Also, ignore RMW instruction which naturally read the current value - this could happen if the code + // modifies the return value, for example "ADD qword [rsp], r8". + if (Context->Instruction.Category != ND_CAT_RET && !(op->Access.Access & ND_ACCESS_ANY_WRITE) && + ShemuIsStackPtr(Context, gla, op->Size) && + ShemuAnyBitsSet(STACKBMP(Context), gla - Context->StackBase, op->Size)) + { + Context->Flags |= SHEMU_FLAG_LOAD_RIP; + } + + // Get the memory value. + status = ShemuGetMemValue(Context, gla, Value->Size, Value->Value.Bytes); + if (SHEMU_SUCCESS != status) + { + return status; + } + + // If this is a stack access, we need to update the stack pointer. + if (op->Info.Memory.IsStack) + { + uint64_t regval = ShemuGetGprValue(Context, REG_RSP, (2 << Context->Instruction.DefStack), false); + + regval += op->Size; + + ShemuSetGprValue(Context, REG_RSP, (2 << Context->Instruction.DefStack), regval, false); + } + + // If this is a string operation, make sure we update RSI/RDI. + if (op->Info.Memory.IsString) + { + uint64_t regval = ShemuGetGprValue(Context, op->Info.Memory.Base, op->Info.Memory.BaseSize, false); + + regval = GET_FLAG(Context, REG_RFLAG_DF) ? regval - op->Size : regval + op->Size; + + ShemuSetGprValue(Context, op->Info.Memory.Base, op->Info.Memory.BaseSize, regval, false); + } + } + } + else if (op->Type == ND_OP_IMM) + { + Value->Value.Qwords[0] = op->Info.Immediate.Imm; + } + else if (op->Type == ND_OP_CONST) + { + Value->Value.Qwords[0] = op->Info.Constant.Const; + } + else if (op->Type == ND_OP_OFFS) + { + Value->Value.Qwords[0] = op->Info.RelativeOffset.Rel; + } + else + { + return SHEMU_ABORT_UNSUPPORTED_INSTRUX; + } + + return SHEMU_SUCCESS; +} + + +// +// IntWinShcSetOperandValue +// +static SHEMU_STATUS +ShemuSetOperandValue( + SHEMU_CONTEXT *Context, + uint32_t Operand, + SHEMU_VALUE *Value + ) +{ + SHEMU_STATUS status; + PND_OPERAND op = &Context->Instruction.Operands[Operand]; + + if (op->Type == ND_OP_REG) + { + switch (op->Info.Register.Type) + { + case ND_REG_GPR: + ShemuSetGprValue(Context, op->Info.Register.Reg, op->Size, Value->Value.Qwords[0], + op->Info.Register.IsHigh8); + break; + + case ND_REG_SEG: + ShemuSetSegValue(Context, op->Info.Register.Reg, Value->Value.Words[0]); + break; + + case ND_REG_MMX: + Context->MmxRegisters[op->Info.Register.Reg] = Value->Value.Qwords[0]; + // Only log these when they're written. + shemu_printf(Context, " MM%d = 0x%016llx\n", op->Info.Register.Reg, Value->Value.Qwords[0]); + break; + + case ND_REG_SSE: + shemu_memcpy(&Context->SseRegisters[op->Info.Register.Reg * ND_MAX_REGISTER_SIZE], + Value->Value.Bytes, + op->Size); + // Only log these when they're written. + shemu_printf(Context, + " %cMM%d (HI_32) = 0x%016llx%016llx%016llx%016llx\n", + op->Size == 16 ? 'X' : op->Size == 32 ? 'Y' : 'Z', op->Info.Register.Reg, + Value->Value.Qwords[7], Value->Value.Qwords[6], Value->Value.Qwords[5], Value->Value.Qwords[4]); + shemu_printf(Context, + " %cMM%d (LO_32) = 0x%016llx%016llx%016llx%016llx\n", + op->Size == 16 ? 'X' : op->Size == 32 ? 'Y' : 'Z', op->Info.Register.Reg, + Value->Value.Qwords[3], Value->Value.Qwords[2], Value->Value.Qwords[1], Value->Value.Qwords[0]); + break; + + case ND_REG_RIP: + Context->Registers.RegRip = ND_TRIM(Value->Size, Value->Value.Qwords[0]); + break; + + case ND_REG_FLG: + Context->Registers.RegFlags = ND_TRIM(Value->Size, Value->Value.Qwords[0]); + break; + + case ND_REG_CR: + switch (op->Info.Register.Reg) + { + case REG_CR0: + Context->Registers.RegCr0 = Value->Value.Qwords[0]; + break; + case REG_CR2: + Context->Registers.RegCr2 = Value->Value.Qwords[0]; + break; + case REG_CR3: + Context->Registers.RegCr3 = Value->Value.Qwords[0]; + break; + case REG_CR4: + Context->Registers.RegCr4 = Value->Value.Qwords[0]; + break; + case REG_CR8: + Context->Registers.RegCr8 = Value->Value.Qwords[0]; + break; + default: + return SHEMU_ABORT_REGISTER_NOT_SUPPORTED; + } + break; + + default: + return SHEMU_ABORT_REGISTER_NOT_SUPPORTED; + } + } + else if (op->Type == ND_OP_MEM) + { + // Compute the GLA. + uint64_t gla = ShemuComputeLinearAddress(Context, op); + + // Handle self-write. We store a 1 for each written byte inside the shellcode space. Once the modified bytes + // are executed, we can trigger the self-write detection. + if (ShemuIsShellcodePtr(Context, gla, op->Size)) + { + ShemuSetBits(SHELLBMP(Context), gla - Context->ShellcodeBase, op->Size, 1); + } + + // Handle RIP save on the stack. + if (ShemuIsStackPtr(Context, gla, MAX(op->Size, Context->Instruction.WordLength))) + { + // Note: only Context->Instruction.WordLength bits are flagged as RIP, as that is the RIP size. + if (Context->Instruction.Instruction == ND_INS_CALLNR || + Context->Instruction.Instruction == ND_INS_CALLNI) + { + ShemuSetBits(STACKBMP(Context), gla - Context->StackBase, Context->Instruction.WordLength, 1); + } + else if (Context->Instruction.Instruction == ND_INS_FNSTENV) + { + // OK: op->Size will be the FPU state size. + ShemuSetBits(STACKBMP(Context), (gla + 0xC) - Context->StackBase, Context->Instruction.WordLength, 1); + } + else if (Context->Instruction.Instruction == ND_INS_FXSAVE) + { + // OK: op->Size will be the FXSAVE size. + ShemuSetBits(STACKBMP(Context), (gla + 0x8) - Context->StackBase, Context->Instruction.WordLength, 1); + } + else + { + // Something is written on a previously saved RIP; reset it. + ShemuSetBits(STACKBMP(Context), gla - Context->StackBase, op->Size, 0); + } + + // Check if a string is being saved on the stack. Typically used by shellcodes like this: + // PUSH str0 + // PUSH str1 + // ... + // PUSH strn + // Other variants may exist, but all we care about are stores on the stack, and all are checked. + for (uint32_t i = 0; i < Value->Size; i++) + { + unsigned char c = Value->Value.Bytes[i]; + + if ((c >= 'a' && c <= 'z') || (c >= 'A' && c <= 'Z') || (c >= '0' && c <= '9') || + c == '\\' || c == '/' || c == ':' || c == ' ') + { + Context->StrLength++; + + if (Context->StrLength >= Context->StrThreshold) + { + Context->Flags |= SHEMU_FLAG_STACK_STR; + break; + } + } + else + { + Context->StrLength = 0; + } + } + } + + // Set the value. + status = ShemuSetMemValue(Context, gla, MIN(op->Size, Value->Size), Value->Value.Bytes); + if (SHEMU_SUCCESS != status) + { + return status; + } + + // If this is a stack access, we need to update the stack pointer. + if (op->Info.Memory.IsStack) + { + uint64_t regval = ShemuGetGprValue(Context, REG_RSP, (2 << Context->Instruction.DefStack), false); + + regval -= op->Size; + + ShemuSetGprValue(Context, REG_RSP, (2 << Context->Instruction.DefStack), regval, false); + } + + // If this is a string operation, make sure we update RSI/RDI. + if (op->Info.Memory.IsString) + { + uint64_t regval = ShemuGetGprValue(Context, op->Info.Memory.Base, op->Info.Memory.BaseSize, false); + + regval = GET_FLAG(Context, REG_RFLAG_DF) ? regval - op->Size : regval + op->Size; + + ShemuSetGprValue(Context, op->Info.Memory.Base, op->Info.Memory.BaseSize, regval, false); + } + } + else + { + return SHEMU_ABORT_INVALID_INSTRUX; + } + + return SHEMU_SUCCESS; +} + + +// +// ShemuMultiply64Unsigned +// +static void +ShemuMultiply64Unsigned( + uint64_t Operand1, + uint64_t Operand2, + uint64_t *ResHigh, + uint64_t *ResLow + ) +{ + uint64_t xLow = (uint64_t)(uint32_t)Operand1; + uint64_t xHigh = Operand1 >> 32; + uint64_t yLow = (uint64_t)(uint32_t)Operand2; + uint64_t yHigh = Operand2 >> 32; + + uint64_t p0 = xLow * yLow; + uint64_t p1 = xLow * yHigh; + uint64_t p2 = xHigh * yLow; + uint64_t p3 = xHigh * yHigh; + + uint32_t cy = (uint32_t)(((p0 >> 32) + (uint32_t)p1 + (uint32_t)p2) >> 32); + + *ResLow = p0 + (p1 << 32) + (p2 << 32); + *ResHigh = p3 + (p1 >> 32) + (p2 >> 32) + cy; +} + + +// +// ShemuMultiply64Signed +// +static void +ShemuMultiply64Signed( + int64_t Operand1, + int64_t Operand2, + int64_t *ResHigh, + int64_t *ResLow + ) +{ + ShemuMultiply64Unsigned((uint64_t)Operand1, (uint64_t)Operand2, (uint64_t *)ResHigh, (uint64_t *)ResLow); + if (Operand1 < 0LL) *ResHigh -= Operand2; + if (Operand2 < 0LL) *ResHigh -= Operand1; +} + + +// +// ShemuPrintContext +// +static void +ShemuPrintContext( + SHEMU_CONTEXT *Context + ) +{ + char text[ND_MIN_BUF_SIZE] = { 0 }; + + NdToText(&Context->Instruction, Context->Registers.RegRip, ND_MIN_BUF_SIZE, text); + + shemu_printf(Context, " RAX = 0x%016llx RCX = 0x%016llx RDX = 0x%016llx RBX = 0x%016llx\n", + Context->Registers.RegRax, Context->Registers.RegRcx, Context->Registers.RegRdx, Context->Registers.RegRbx); + shemu_printf(Context, " RSP = 0x%016llx RBP = 0x%016llx RSI = 0x%016llx RDI = 0x%016llx\n", + Context->Registers.RegRsp, Context->Registers.RegRbp, Context->Registers.RegRsi, Context->Registers.RegRdi); + shemu_printf(Context, " R8 = 0x%016llx R9 = 0x%016llx R10 = 0x%016llx R11 = 0x%016llx\n", + Context->Registers.RegR8, Context->Registers.RegR9, Context->Registers.RegR10, Context->Registers.RegR11); + shemu_printf(Context, " R12 = 0x%016llx R13 = 0x%016llx R14 = 0x%016llx R15 = 0x%016llx\n", + Context->Registers.RegR12, Context->Registers.RegR13, Context->Registers.RegR14, Context->Registers.RegR15); + shemu_printf(Context, " RIP = 0x%016llx RFLAGS = 0x%016llx\n", + Context->Registers.RegRip, Context->Registers.RegFlags); + + shemu_printf(Context, "Emulating: 0x%016llx %s\n", Context->Registers.RegRip, text); +} + + +// +// ShemuEmulate +// +SHEMU_STATUS +ShemuEmulate( + SHEMU_CONTEXT *Context + ) +{ + NDSTATUS ndstatus; + SHEMU_VALUE res = { 0 }, dst = { 0 }, src = { 0 }, rcx = { 0 }, aux = { 0 }; + bool stop = false; + uint64_t rip = 0; + + if (NULL == Context) + { + return SHEMU_ABORT_INVALID_PARAMETER; + } + + if (NULL == Context->Shellcode) + { + return SHEMU_ABORT_INVALID_PARAMETER; + } + + if (NULL == Context->Stack) + { + return SHEMU_ABORT_INVALID_PARAMETER; + } + + if (NULL == Context->Intbuf) + { + return SHEMU_ABORT_INVALID_PARAMETER; + } + + if (SHEMU_INTERNAL_BUFFER_SIZE(Context) > Context->IntbufSize) + { + return SHEMU_ABORT_INVALID_PARAMETER; + } + + if (Context->NopThreshold == 0) + { + Context->NopThreshold = SHEMU_DEFAULT_NOP_THRESHOLD; + } + + if (Context->StrThreshold == 0) + { + Context->StrThreshold = SHEMU_DEFAULT_STR_THRESHOLD; + } + + while (Context->InstructionsCount++ < Context->MaxInstructionsCount) + { + // The stop flag has been set, this means we've reached a valid instruction, but that instruction cannot be + // emulated (for example, SYSCALL, INT, system instructions, etc). + if (stop) + { + return SHEMU_ABORT_CANT_EMULATE; + } + + // If we already have a detection and we wish to stop on detections, do so now. + if ((0 != Context->Flags) && (0 != (Context->Options & SHEMU_OPT_STOP_ON_EXPLOIT))) + { + return SHEMU_ABORT_SHELLCODE_DETECTED; + } + + // Make sure the RIP is pointing in the right area. We test only 1 byte - the decoder will make sure it can + // access as many bytes as needed and return error in case it can't. + if (!ShemuIsShellcodePtr(Context, Context->Registers.RegRip, 1)) + { + return SHEMU_ABORT_BRANCH_OUTSIDE; + } + + // Get the offset inside the shellcode buffer. + rip = Context->Registers.RegRip - Context->ShellcodeBase; + + // Decode the next instruction. + ndstatus = NdDecodeEx(&Context->Instruction, Context->Shellcode + rip, + Context->ShellcodeSize - (size_t)rip, Context->Mode, Context->Mode); + if (!ND_SUCCESS(ndstatus)) + { + if (ND_STATUS_BUFFER_TOO_SMALL == ndstatus) + { + return SHEMU_ABORT_BRANCH_OUTSIDE; + } + else + { + return SHEMU_ABORT_INVALID_INSTRUX; + } + } + + // Paranoid check... + if (!ShemuIsShellcodePtr(Context, Context->Registers.RegRip, Context->Instruction.Length)) + { + return SHEMU_ABORT_BRANCH_OUTSIDE; + } + + // Check if we just fetched an instruction from a previously written area, to raise self-write alert. + if (ShemuAnyBitsSet(SHELLBMP(Context), rip, Context->Instruction.Length)) + { + Context->Flags |= SHEMU_FLAG_WRITE_SELF; + } + + // Dump the context. + if (Context->Options & SHEMU_OPT_TRACE_EMULATION) + { + ShemuPrintContext(Context); + } + + // The RIP is incremented BEFORE actually emulating the instruction. This is what the CPU does as well. + Context->Registers.RegRip += Context->Instruction.Length; + + // FPU instructions are "pass-through", we just want to save the RIP, so we can emulate FNSTENV. + if ((Context->Instruction.IsaSet == ND_SET_X87) && (Context->Instruction.Instruction != ND_INS_FNSTENV)) + { + Context->Registers.FpuRip = Context->Registers.RegRip - Context->Instruction.Length; + continue; + } + + switch (Context->Instruction.Instruction) + { + case ND_INS_FNSTENV: + src.Size = Context->Instruction.Operands[0].Size; + src.Value.FpuEnvironment.FpuInstructionPointer = (uint32_t)Context->Registers.FpuRip; + SET_OP(Context, 0, &src); + break; + + case ND_INS_FXSAVE: + src.Size = MIN(Context->Instruction.Operands[0].Size, sizeof(src.Value.XsaveArea)); + src.Value.XsaveArea.FpuRip = Context->Registers.FpuRip; + SET_OP(Context, 0, &src); + break; + + case ND_INS_MOV_CR: + if (Context->Ring != 0) + { + return SHEMU_ABORT_NO_PRIVILEGE; + } + + // Fall through. + + case ND_INS_MOV: + case ND_INS_MOVZX: + GET_OP(Context, 1, &src); + SET_OP(Context, 0, &src); + break; + + case ND_INS_MOVSX: + case ND_INS_MOVSXD: + GET_OP(Context, 1, &src); + GET_OP(Context, 0, &dst); + dst.Value.Qwords[0] = ND_SIGN_EX(src.Size, src.Value.Qwords[0]); + SET_OP(Context, 0, &dst); + break; + + case ND_INS_CMOVcc: + if (ShemuEvalCondition(Context, Context->Instruction.Condition)) + { + GET_OP(Context, 1, &src); + SET_OP(Context, 0, &src); + } + break; + + case ND_INS_SETcc: + if (ShemuEvalCondition(Context, Context->Instruction.Condition)) + { + src.Size = Context->Instruction.Operands[0].Size; + src.Value.Qwords[0] = 1; + } + else + { + src.Size = Context->Instruction.Operands[0].Size; + src.Value.Qwords[0] = 0; + } + SET_OP(Context, 0, &src); + break; + + case ND_INS_XLATB: + GET_OP(Context, 1, &src); + SET_OP(Context, 0, &src); + break; + + case ND_INS_XCHG: + GET_OP(Context, 1, &src); + GET_OP(Context, 0, &dst); + SET_OP(Context, 1, &dst); + SET_OP(Context, 0, &src); + break; + + case ND_INS_XADD: + GET_OP(Context, 1, &src); + GET_OP(Context, 0, &dst); + res.Size = dst.Size; + res.Value.Qwords[0] = dst.Value.Qwords[0] + src.Value.Qwords[0]; + SET_FLAGS(Context, res, dst, src, FM_ADD); + SET_OP(Context, 1, &dst); + SET_OP(Context, 0, &res); + break; + + case ND_INS_CMPXCHG: + GET_OP(Context, 2, &src); + GET_OP(Context, 0, &dst); + if (src.Value.Qwords[0] == dst.Value.Qwords[0]) + { + GET_OP(Context, 1, &src); + SET_OP(Context, 0, &src); + SET_FLAG(Context, REG_RFLAG_ZF, 1); + } + else + { + SET_OP(Context, 2, &dst); + SET_FLAG(Context, REG_RFLAG_ZF, 0); + } + break; + + case ND_INS_ADD: + case ND_INS_ADC: + GET_OP(Context, 0, &dst); + GET_OP(Context, 1, &src); + + if (ND_INS_ADC == Context->Instruction.Instruction) + { + src.Value.Qwords[0] += GET_FLAG(Context, REG_RFLAG_CF); + } + + res.Size = src.Size; + res.Value.Qwords[0] = dst.Value.Qwords[0] + src.Value.Qwords[0]; + + SET_FLAGS(Context, res, dst, src, FM_ADD); + SET_OP(Context, 0, &res); + + break; + + case ND_INS_SUB: + case ND_INS_SBB: + case ND_INS_CMP: + GET_OP(Context, 0, &dst); + GET_OP(Context, 1, &src); + + if (ND_INS_SBB == Context->Instruction.Instruction) + { + src.Value.Qwords[0] += GET_FLAG(Context, REG_RFLAG_CF); + } + + res.Size = src.Size; + res.Value.Qwords[0] = dst.Value.Qwords[0] - src.Value.Qwords[0]; + + SET_FLAGS(Context, res, dst, src, FM_SUB); + + if (ND_INS_CMP != Context->Instruction.Instruction) + { + SET_OP(Context, 0, &res); + } + + break; + + case ND_INS_INC: + GET_OP(Context, 0, &dst); + src.Size = dst.Size; + src.Value.Qwords[0] = 1; + res.Size = src.Size; + res.Value.Qwords[0] = dst.Value.Qwords[0] + src.Value.Qwords[0]; + SET_FLAGS(Context, res, dst, src, FM_ADD); + SET_OP(Context, 0, &res); + break; + + case ND_INS_DEC: + GET_OP(Context, 0, &dst); + src.Size = dst.Size; + src.Value.Qwords[0] = 1; + res.Size = src.Size; + res.Value.Qwords[0] = dst.Value.Qwords[0] - src.Value.Qwords[0]; + SET_FLAGS(Context, res, dst, src, FM_SUB); + SET_OP(Context, 0, &res); + break; + + case ND_INS_PUSH: + case ND_INS_PUSHF: + GET_OP(Context, 0, &src); + SET_OP(Context, 1, &src); + break; + + case ND_INS_POP: + case ND_INS_POPF: + GET_OP(Context, 1, &src); + SET_OP(Context, 0, &src); + break; + + case ND_INS_PUSHA: + src.Size = 32; + src.Value.Dwords[7] = (uint32_t)Context->Registers.RegRax; + src.Value.Dwords[6] = (uint32_t)Context->Registers.RegRcx; + src.Value.Dwords[5] = (uint32_t)Context->Registers.RegRdx; + src.Value.Dwords[4] = (uint32_t)Context->Registers.RegRbx; + src.Value.Dwords[3] = (uint32_t)Context->Registers.RegRsp; + src.Value.Dwords[2] = (uint32_t)Context->Registers.RegRbp; + src.Value.Dwords[1] = (uint32_t)Context->Registers.RegRsi; + src.Value.Dwords[0] = (uint32_t)Context->Registers.RegRdi; + SET_OP(Context, 1, &src); + break; + + case ND_INS_POPA: + GET_OP(Context, 1, &src); + Context->Registers.RegRax = src.Value.Dwords[7]; + Context->Registers.RegRcx = src.Value.Dwords[6]; + Context->Registers.RegRdx = src.Value.Dwords[5]; + Context->Registers.RegRbx = src.Value.Dwords[4]; + Context->Registers.RegRsp = src.Value.Dwords[3]; + Context->Registers.RegRbp = src.Value.Dwords[2]; + Context->Registers.RegRsi = src.Value.Dwords[1]; + Context->Registers.RegRdi = src.Value.Dwords[0]; + break; + + case ND_INS_LEA: + GET_OP(Context, 1, &src); + SET_OP(Context, 0, &src); + break; + + case ND_INS_SHL: + case ND_INS_SAL: + case ND_INS_SHR: + case ND_INS_SAR: + GET_OP(Context, 0, &dst); + GET_OP(Context, 1, &src); + + if (dst.Size == 8) + { + src.Value.Qwords[0] &= 0x3f; + } + else + { + src.Value.Qwords[0] &= 0x1f; + } + + res.Size = dst.Size; + + if (ND_INS_SHL == Context->Instruction.Instruction || + ND_INS_SAL == Context->Instruction.Instruction) + { + res.Value.Qwords[0] = dst.Value.Qwords[0] << src.Value.Qwords[0]; + } + else if (ND_INS_SHR == Context->Instruction.Instruction) + { + res.Value.Qwords[0] = dst.Value.Qwords[0] >> src.Value.Qwords[0]; + } + else + { + int64_t val = ND_SIGN_EX(dst.Size, dst.Value.Qwords[0]); + val = val >> src.Value.Qwords[0]; + res.Value.Qwords[0] = (uint64_t)val; + } + + if (src.Value.Qwords[0] != 0) + { + // 0 bit shifts do not affect the flags. + if (ND_INS_SHL == Context->Instruction.Instruction || + ND_INS_SAL == Context->Instruction.Instruction) + { + SET_FLAGS(Context, res, dst, src, FM_SHL); + } + else if (ND_INS_SHR == Context->Instruction.Instruction) + { + SET_FLAGS(Context, res, dst, src, FM_SHR); + } + else + { + SET_FLAGS(Context, res, dst, src, FM_SAR); + } + } + + SET_OP(Context, 0, &res); + break; + + case ND_INS_RCL: + case ND_INS_RCR: + case ND_INS_ROL: + case ND_INS_ROR: + { + uint32_t cnt, tempcnt, cntmask; + uint8_t tempCF = 0; + + GET_OP(Context, 0, &dst); + GET_OP(Context, 1, &src); + + cnt = (uint32_t)src.Value.Qwords[0]; + tempcnt = 0; + cntmask = ((dst.Size == 8) ? 0x3F : 0x1F); + + if (ND_INS_RCL == Context->Instruction.Instruction || + ND_INS_RCR == Context->Instruction.Instruction) + { + switch (dst.Size) + { + case 1: tempcnt = (cnt & 0x1F) % 9; break; + case 2: tempcnt = (cnt & 0x1F) % 17; break; + case 4: tempcnt = (cnt & 0x1F); break; + case 8: tempcnt = (cnt & 0x3F); break; + default: break; + } + } + else + { + tempcnt = (cnt & cntmask) % (dst.Size * 8); + } + + if (ND_INS_RCL == Context->Instruction.Instruction) + { + while (tempcnt != 0) + { + tempCF = ND_MSB(dst.Size, dst.Value.Qwords[0]); + dst.Value.Qwords[0] = (dst.Value.Qwords[0] << 1) + GET_FLAG(Context, REG_RFLAG_CF); + SET_FLAG(Context, REG_RFLAG_CF, tempCF); + tempcnt--; + } + + if ((cnt & cntmask) == 1) + { + SET_FLAG(Context, REG_RFLAG_OF, ND_MSB(dst.Size, dst.Value.Qwords[0]) ^ + GET_FLAG(Context, REG_RFLAG_CF)); + } + } + else if (ND_INS_RCR == Context->Instruction.Instruction) + { + if ((cnt & cntmask) == 1) + { + SET_FLAG(Context, REG_RFLAG_OF, ND_MSB(dst.Size, dst.Value.Qwords[0]) ^ + GET_FLAG(Context, REG_RFLAG_CF)); + } + + while (tempcnt != 0) + { + tempCF = ND_LSB(dst.Size, dst.Value.Qwords[0]); + dst.Value.Qwords[0] = (dst.Value.Qwords[0] >> 1) + + ((uint64_t)GET_FLAG(Context, REG_RFLAG_CF) << (dst.Size * 8 - 1)); + SET_FLAG(Context, REG_RFLAG_CF, tempCF); + tempcnt--; + } + } + else if (ND_INS_ROL == Context->Instruction.Instruction) + { + while (tempcnt != 0) + { + tempCF = ND_MSB(dst.Size, dst.Value.Qwords[0]); + dst.Value.Qwords[0] = (dst.Value.Qwords[0] << 1) + tempCF; + tempcnt--; + } + + if ((cnt & cntmask) != 0) + { + SET_FLAG(Context, REG_RFLAG_CF, dst.Value.Qwords[0] & 1); + } + + if ((cnt & cntmask) == 1) + { + SET_FLAG(Context, REG_RFLAG_OF, ND_MSB(dst.Size, dst.Value.Qwords[0]) ^ + GET_FLAG(Context, REG_RFLAG_CF)); + } + } + else // ND_INS_ROR + { + while (tempcnt != 0) + { + tempCF = ND_LSB(dst.Size, dst.Value.Qwords[0]); + dst.Value.Qwords[0] = (dst.Value.Qwords[0] >> 1) + ((uint64_t)tempCF << (dst.Size * 8 - 1)); + tempcnt--; + } + + if ((cnt & cntmask) != 0) + { + SET_FLAG(Context, REG_RFLAG_CF, ND_MSB(dst.Size, dst.Value.Qwords[0])); + } + + if ((cnt & cntmask) == 1) + { + SET_FLAG(Context, REG_RFLAG_OF, ND_MSB(dst.Size, dst.Value.Qwords[0]) ^ tempCF); + } + } + + SET_OP(Context, 0, &dst); + } + break; + + case ND_INS_OR: + case ND_INS_XOR: + case ND_INS_AND: + case ND_INS_TEST: + GET_OP(Context, 0, &dst); + GET_OP(Context, 1, &src); + + res.Size = dst.Size; + + if (ND_INS_OR == Context->Instruction.Instruction) + { + res.Value.Qwords[0] = dst.Value.Qwords[0] | src.Value.Qwords[0]; + } + else if (ND_INS_XOR == Context->Instruction.Instruction) + { + res.Value.Qwords[0] = dst.Value.Qwords[0] ^ src.Value.Qwords[0]; + } + else + { + res.Value.Qwords[0] = dst.Value.Qwords[0] & src.Value.Qwords[0]; + } + + if (ND_INS_TEST != Context->Instruction.Instruction) + { + SET_OP(Context, 0, &res); + } + + SET_FLAGS(Context, res, dst, src, FM_LOGIC); + break; + + case ND_INS_NOT: + GET_OP(Context, 0, &dst); + dst.Value.Qwords[0] = ~dst.Value.Qwords[0]; + SET_OP(Context, 0, &dst); + break; + + case ND_INS_NEG: + GET_OP(Context, 0, &dst); + dst.Value.Qwords[0] = 0 - dst.Value.Qwords[0]; + SET_OP(Context, 0, &dst); + break; + + case ND_INS_BT: + case ND_INS_BTS: + case ND_INS_BTR: + case ND_INS_BTC: + GET_OP(Context, 0, &dst); + GET_OP(Context, 1, &src); + + src.Value.Qwords[0] %= dst.Size * 8; + + // Store the bit inside CF. + SET_FLAG(Context, REG_RFLAG_CF, (dst.Value.Qwords[0] >> src.Value.Qwords[0]) & 1); + + if (ND_INS_BTS == Context->Instruction.Instruction) + { + dst.Value.Qwords[0] |= (1ULL << src.Value.Qwords[0]); + } + else if (ND_INS_BTR == Context->Instruction.Instruction) + { + dst.Value.Qwords[0] &= ~(1ULL << src.Value.Qwords[0]); + } + else if (ND_INS_BTC == Context->Instruction.Instruction) + { + dst.Value.Qwords[0] ^= (1ULL << src.Value.Qwords[0]); + } + + if (ND_INS_BT != Context->Instruction.Instruction) + { + SET_OP(Context, 0, &dst); + } + + break; + + case ND_INS_Jcc: + if (ShemuEvalCondition(Context, Context->Instruction.Condition)) + { + // Modify the RIP if the branch is taken. + GET_OP(Context, 1, &aux); + aux.Value.Qwords[0] += Context->Instruction.Operands[0].Info.RelativeOffset.Rel; + SET_OP(Context, 1, &aux); + } + break; + + case ND_INS_JrCXZ: + // Fetch the rCX value. It could be CX, ECX or RCX, depending on address size. + GET_OP(Context, 1, &rcx); + if (rcx.Value.Qwords[0] == 0) + { + // Modify the RIP if the branch is taken. + GET_OP(Context, 2, &aux); + aux.Value.Qwords[0] += Context->Instruction.Operands[0].Info.RelativeOffset.Rel; + SET_OP(Context, 2, &aux); + } + break; + + case ND_INS_LOOP: + case ND_INS_LOOPNZ: + case ND_INS_LOOPZ: + // rCX is decremented first. Note that the size depends on address size. + GET_OP(Context, 1, &rcx); + rcx.Value.Qwords[0]--; + SET_OP(Context, 1, &rcx); + if (rcx.Value.Qwords[0] > 0) + { + if (((ND_INS_LOOPNZ == Context->Instruction.Instruction) && (0 == GET_FLAG(Context, REG_RFLAG_ZF))) || + ((ND_INS_LOOPZ == Context->Instruction.Instruction) && (0 != GET_FLAG(Context, REG_RFLAG_ZF))) || + (ND_INS_LOOP == Context->Instruction.Instruction)) + { + // Modify the RIP if the branch is taken. + GET_OP(Context, 2, &aux); + aux.Value.Qwords[0] += Context->Instruction.Operands[0].Info.RelativeOffset.Rel; + SET_OP(Context, 2, &aux); + } + } + break; + + case ND_INS_JMPNR: + GET_OP(Context, 1, &aux); + aux.Value.Qwords[0] += Context->Instruction.Operands[0].Info.RelativeOffset.Rel; + SET_OP(Context, 1, &aux); + break; + + case ND_INS_JMPNI: + GET_OP(Context, 0, &src); + SET_OP(Context, 1, &src); // Set the RIP to the new value. + break; + + case ND_INS_CALLNR: + // Save the EIP on the stack. + GET_OP(Context, 1, &aux); + SET_OP(Context, 2, &aux); + aux.Value.Qwords[0] += Context->Instruction.Operands[0].Info.RelativeOffset.Rel; + SET_OP(Context, 1, &aux); + break; + + case ND_INS_CALLNI: + GET_OP(Context, 0, &src); + GET_OP(Context, 1, &dst); // The RIP + SET_OP(Context, 2, &dst); // Save the RIP on the stack. + SET_OP(Context, 1, &src); // Set the RIP to the new value. + break; + + case ND_INS_RETN: + if (!Context->Instruction.HasImm1) + { + // The simple RET form, 0xC3 + GET_OP(Context, 1, &src); + SET_OP(Context, 0, &src); + } + else + { + // The RET Imm16 form, 0xC2 + GET_OP(Context, 3, &src); + SET_OP(Context, 1, &src); + + // Patch the RSP register. + GET_OP(Context, 2, &aux); + aux.Value.Qwords[0] += Context->Instruction.Operands[0].Info.Immediate.Imm; + SET_OP(Context, 2, &aux); + } + break; + + case ND_INS_LODS: + case ND_INS_STOS: + case ND_INS_MOVS: + // Fetch the rCX register, which is the third operand in case of repeated instructions. + while (Context->InstructionsCount < Context->MaxInstructionsCount) + { + GET_OP(Context, 2, &rcx); + + if (Context->Instruction.IsRepeated && (rcx.Value.Qwords[0] == 0)) + { + break; + } + + // Load the source into the destination. + GET_OP(Context, 1, &src); + SET_OP(Context, 0, &src); + + if (Context->Instruction.IsRepeated) + { + // Decrement RCX. + rcx.Value.Qwords[0]--; + SET_OP(Context, 2, &rcx); + } + else + { + break; + } + + Context->InstructionsCount++; + } + break; + + case ND_INS_SCAS: + case ND_INS_CMPS: + while (Context->InstructionsCount < Context->MaxInstructionsCount) + { + GET_OP(Context, 2, &rcx); + + if (Context->Instruction.IsRepeated && (rcx.Value.Qwords[0] == 0)) + { + break; + } + + GET_OP(Context, 0, &dst); + GET_OP(Context, 1, &src); + + res.Size = dst.Size; + res.Value.Qwords[0] = dst.Value.Qwords[0] - src.Value.Qwords[0]; + + ShemuSetFlags(Context, res.Value.Qwords[0], dst.Value.Qwords[0], src.Value.Qwords[0], res.Size, FM_SUB); + + if (Context->Instruction.IsRepeated) + { + // Decrement RCX. + rcx.Value.Qwords[0]--; + SET_OP(Context, 2, &rcx); + + if (Context->Instruction.HasRepRepzXrelease && !GET_FLAG(Context, REG_RFLAG_ZF)) + { + break; + } + + if (Context->Instruction.HasRepnzXacquireBnd && GET_FLAG(Context, REG_RFLAG_ZF)) + { + break; + } + } + else + { + break; + } + + Context->InstructionsCount++; + } + break; + + case ND_INS_MUL: + case ND_INS_IMUL: + if (Context->Instruction.ExpOperandsCount < 3) + { + // MUL or IMUL with a single explicit operand or IMUL with 2 explicit operands. + GET_OP(Context, 0, &dst); + GET_OP(Context, 1, &src); + } + else + { + // IMUL with 3 operands. The first operand is the write-only destination. + GET_OP(Context, 0, &res); + GET_OP(Context, 1, &dst); + GET_OP(Context, 2, &src); + } + + if (dst.Size == 1) + { + if (ND_INS_MUL == Context->Instruction.Instruction) + { + res.Value.Words[0] = dst.Value.Bytes[0] * src.Value.Bytes[0]; + } + else + { + res.Value.Words[0] = (int8_t)dst.Value.Bytes[0] * (int8_t)src.Value.Bytes[0]; + } + } + else if (dst.Size == 2) + { + if (ND_INS_MUL == Context->Instruction.Instruction) + { + res.Value.Dwords[0] = dst.Value.Words[0] * src.Value.Words[0]; + } + else + { + res.Value.Dwords[0] = (int16_t)dst.Value.Words[0] * (int16_t)src.Value.Words[0]; + } + } + else if (dst.Size == 4) + { + if (ND_INS_MUL == Context->Instruction.Instruction) + { + res.Value.Qwords[0] = dst.Value.Qwords[0] * src.Value.Qwords[0]; + } + else + { + res.Value.Qwords[0] = (int64_t)(int32_t)dst.Value.Dwords[0] * (int64_t)(int32_t)src.Value.Dwords[0]; + } + } + else + { + if (ND_INS_MUL == Context->Instruction.Instruction) + { + ShemuMultiply64Unsigned(dst.Value.Qwords[0], src.Value.Qwords[0], + &res.Value.Qwords[1], &res.Value.Qwords[0]); + } + else + { + ShemuMultiply64Signed(dst.Value.Qwords[0], src.Value.Qwords[0], + (int64_t*)&res.Value.Qwords[1], (int64_t*)&res.Value.Qwords[0]); + } + } + + if (Context->Instruction.ExpOperandsCount == 1) + { + // The result is stored in AX, DX:AX, EDX:EAX or RDX:RAX for the single-operand form. + switch (dst.Size) + { + case 1: + *((uint16_t*)&Context->Registers.RegRax) = res.Value.Words[0]; + break; + case 2: + *((uint16_t*)&Context->Registers.RegRdx) = res.Value.Words[1]; + *((uint16_t*)&Context->Registers.RegRax) = res.Value.Words[0]; + break; + case 4: + Context->Registers.RegRdx = res.Value.Dwords[1]; + Context->Registers.RegRax = res.Value.Dwords[0]; + break; + case 8: + Context->Registers.RegRdx = res.Value.Qwords[1]; + Context->Registers.RegRax = res.Value.Qwords[0]; + break; + } + } + else + { + // The result is truncated and stored in the destination operand for the 2 & 3 operands forms. + SET_OP(Context, 0, &res); + } + + if (ND_INS_MUL == Context->Instruction.Instruction) + { + uint8_t cfof = 0; + + // CF and OF are set to 0 if the high part of the result is 0, otherwise they are set to 1. + switch (dst.Size) + { + case 1: + cfof = (0 == res.Value.Bytes[1]) ? 0 : 1; + break; + case 2: + cfof = (0 == res.Value.Words[1]) ? 0 : 1; + break; + case 4: + cfof = (0 == res.Value.Dwords[1]) ? 0 : 1; + break; + case 8: + cfof = (0 == res.Value.Qwords[1]) ? 0 : 1; + break; + } + + SET_FLAG(Context, REG_RFLAG_CF, cfof); + SET_FLAG(Context, REG_RFLAG_OF, cfof); + } + else + { + // The CF and OF flags are set when the signed integer value of the intermediate product differs from + // the sign extended operand - size - truncated product, otherwise the CF and OF flags are cleared. + uint8_t cfof = 0, sign = 0; + + sign = ND_MSB(res.Size, res.Value.Qwords[0]); + + switch (dst.Size) + { + case 1: + cfof = (0 == res.Value.Bytes[1] && 0 == sign) || + ((uint8_t)-1 == res.Value.Bytes[1] && 1 == sign) ? 0 : 1; + break; + case 2: + cfof = (0 == res.Value.Words[1] && 0 == sign) || + ((uint16_t)-1 == res.Value.Words[1] && 1 == sign) ? 0 : 1; + break; + case 4: + cfof = (0 == res.Value.Dwords[1] && 0 == sign) || + ((uint32_t)-1 == res.Value.Dwords[1] && 1 == sign) ? 0 : 1; + break; + case 8: + cfof = (0 == res.Value.Qwords[1] && 0 == sign) || + ((uint64_t)-1 == res.Value.Qwords[1] && 1 == sign) ? 0 : 1; + break; + } + + SET_FLAG(Context, REG_RFLAG_CF, cfof); + SET_FLAG(Context, REG_RFLAG_OF, cfof); + } + + break; + + case ND_INS_DIV: + case ND_INS_IDIV: + // DIV and IDIV only exist with a single explicit operand encoding. All flags are undefined. + GET_OP(Context, 0, &src); + + if (src.Size == 1) + { + if (src.Value.Bytes[0] == 0) + { + // Division by zero, force emulation stop. + stop = true; + break; + } + + if (ND_INS_DIV == Context->Instruction.Instruction) + { + res.Value.Bytes[0] = (uint8_t)((uint16_t)Context->Registers.RegRax / (uint8_t)src.Value.Bytes[0]); + res.Value.Bytes[1] = (uint8_t)((uint16_t)Context->Registers.RegRax % (uint8_t)src.Value.Bytes[0]); + } + else + { + res.Value.Bytes[0] = (int8_t)((int16_t)Context->Registers.RegRax / (int8_t)src.Value.Bytes[0]); + res.Value.Bytes[1] = (int8_t)((int16_t)Context->Registers.RegRax % (int8_t)src.Value.Bytes[0]); + } + + // Result in AX (AL - quotient, AH - reminder). + *((uint16_t*)&Context->Registers.RegRax) = res.Value.Words[0]; + } + else if (src.Size == 2) + { + uint32_t divident; + + if (src.Value.Words[0] == 0) + { + // Division by zero, force emulation stop. + stop = true; + break; + } + + divident = ((uint32_t)(uint16_t)Context->Registers.RegRdx << 16) | + (uint32_t)(uint16_t)Context->Registers.RegRax; + + if (ND_INS_DIV == Context->Instruction.Instruction) + { + res.Value.Words[0] = (uint16_t)((uint32_t)divident / (uint16_t)src.Value.Words[0]); + res.Value.Words[1] = (uint16_t)((uint32_t)divident % (uint16_t)src.Value.Words[0]); + } + else + { + res.Value.Words[0] = (int16_t)((int32_t)divident / (int16_t)src.Value.Words[0]); + res.Value.Words[1] = (int16_t)((int32_t)divident % (int16_t)src.Value.Words[0]); + } + + *((uint16_t*)&Context->Registers.RegRdx) = res.Value.Words[1]; + *((uint16_t*)&Context->Registers.RegRax) = res.Value.Words[0]; + } + else if (src.Size == 4) + { + uint64_t divident; + + if (src.Value.Dwords[0] == 0) + { + // Division by zero, force emulation stop. + stop = true; + break; + } + + divident = ((uint64_t)(uint32_t)Context->Registers.RegRdx << 32) | + (uint64_t)(uint32_t)Context->Registers.RegRax; + + if (ND_INS_DIV == Context->Instruction.Instruction) + { + res.Value.Dwords[0] = (uint32_t)((uint64_t)divident / (uint32_t)src.Value.Dwords[0]); + res.Value.Dwords[1] = (uint32_t)((uint64_t)divident % (uint32_t)src.Value.Dwords[0]); + } + else + { + res.Value.Dwords[0] = (int32_t)((int64_t)divident / (int32_t)src.Value.Dwords[0]); + res.Value.Dwords[1] = (int32_t)((int64_t)divident % (int32_t)src.Value.Dwords[0]); + } + + Context->Registers.RegRdx = res.Value.Dwords[1]; + Context->Registers.RegRax = res.Value.Dwords[0]; + } + else if (src.Size == 8) + { + /// Not implemented! + } + + break; + + case ND_INS_CLD: + SET_FLAG(Context, REG_RFLAG_DF, 0); + break; + + case ND_INS_STD: + SET_FLAG(Context, REG_RFLAG_DF, 1); + break; + + case ND_INS_CLC: + SET_FLAG(Context, REG_RFLAG_CF, 0); + break; + + case ND_INS_STC: + SET_FLAG(Context, REG_RFLAG_CF, 1); + break; + + case ND_INS_CMC: + Context->Registers.RegFlags ^= REG_RFLAG_CF; + break; + + case ND_INS_STI: + if (Context->Ring != 0) + { + return SHEMU_ABORT_NO_PRIVILEGE; + } + + SET_FLAG(Context, REG_RFLAG_IF, 1); + break; + + case ND_INS_CLI: + if (Context->Ring != 0) + { + return SHEMU_ABORT_NO_PRIVILEGE; + } + + SET_FLAG(Context, REG_RFLAG_IF, 0); + break; + + case ND_INS_SAHF: + { + uint8_t ah = (Context->Registers.RegRax >> 8) & 0xFF; + // Handle reserved bits. + ah |= (1 << 1); + ah &= ~((1 << 3) | (1 << 5)); + ((uint8_t *)&Context->Registers.RegFlags)[0] = ah; + } + break; + + case ND_INS_LAHF: + { + uint8_t ah = ((uint8_t *)&Context->Registers.RegFlags)[0]; + ((uint8_t *)&Context->Registers.RegRax)[1] = ah; + } + break; + + case ND_INS_SALC: + if (GET_FLAG(Context, REG_RFLAG_CF)) + { + *((uint8_t *)&Context->Registers.RegRax) = 0xFF; + } + else + { + *((uint8_t *)&Context->Registers.RegRax) = 0x0; + } + break; + + case ND_INS_NOP: + Context->NopCount++; + break; + + case ND_INS_WAIT: + break; + + case ND_INS_CBW: + case ND_INS_CWDE: + case ND_INS_CDQE: + GET_OP(Context, 1, &src); + dst.Size = src.Size * 2; + dst.Value.Qwords[0] = ND_SIGN_EX(src.Size, src.Value.Qwords[0]); + SET_OP(Context, 0, &dst); + break; + + case ND_INS_CWD: + case ND_INS_CDQ: + case ND_INS_CQO: + GET_OP(Context, 1, &src); + dst.Size = src.Size; + if (ND_GET_SIGN(src.Size, src.Value.Qwords[0])) + { + dst.Value.Qwords[0] = 0xFFFFFFFFFFFFFFFF; + } + else + { + dst.Value.Qwords[0] = 0; + } + SET_OP(Context, 0, &dst); + break; + + case ND_INS_AAA: + case ND_INS_AAD: + case ND_INS_AAM: + case ND_INS_AAS: + case ND_INS_DAA: + case ND_INS_DAS: + // Ignore these for now. + break; + + case ND_INS_ENDBR: + // Acts as a NOP, it's just a hint to the decoder. + break; + + case ND_INS_LFENCE: + case ND_INS_SFENCE: + case ND_INS_MFENCE: + // Nothing can be done for them, really. + break; + + case ND_INS_CPUID: + // OK; EAX, EBX, ECX and EDX are modified, which also zeroes the high 32 bit. + Context->Registers.RegRax = 0; + Context->Registers.RegRbx = 0; + Context->Registers.RegRcx = 0; + Context->Registers.RegRdx = 0; + break; + + // Some basic MMX/SSE instructions supported. + case ND_INS_EMMS: + nd_memzero(Context->MmxRegisters, sizeof(Context->MmxRegisters)); + break; + + case ND_INS_MOVD: + case ND_INS_MOVQ: + case ND_INS_MOVDQU: + case ND_INS_MOVDQA: + // memzero the source; if the source size is less than the destination size, the upper bits will be zero. + // Note that we don't really care about #GP on unaligned MOVDQA accesses... + nd_memzero(src.Value.Bytes, sizeof(src.Value.Bytes)); + GET_OP(Context, 1, &src); + SET_OP(Context, 0, &src); + break; + + case ND_INS_PUNPCKLBW: + GET_OP(Context, 0, &dst); + GET_OP(Context, 1, &src); + if (dst.Size == 8) + { + // Operating on MMX register. + dst.Value.Bytes[7] = src.Value.Bytes[3]; + dst.Value.Bytes[6] = dst.Value.Bytes[3]; + dst.Value.Bytes[5] = src.Value.Bytes[2]; + dst.Value.Bytes[4] = dst.Value.Bytes[2]; + dst.Value.Bytes[3] = src.Value.Bytes[1]; + dst.Value.Bytes[2] = dst.Value.Bytes[1]; + dst.Value.Bytes[1] = src.Value.Bytes[0]; + } + else + { + // Operating on XMM register. + dst.Value.Bytes[15] = src.Value.Bytes[7]; + dst.Value.Bytes[14] = dst.Value.Bytes[7]; + dst.Value.Bytes[13] = src.Value.Bytes[6]; + dst.Value.Bytes[12] = dst.Value.Bytes[6]; + dst.Value.Bytes[11] = src.Value.Bytes[5]; + dst.Value.Bytes[10] = dst.Value.Bytes[5]; + dst.Value.Bytes[9] = src.Value.Bytes[4]; + dst.Value.Bytes[8] = src.Value.Bytes[4]; + dst.Value.Bytes[7] = src.Value.Bytes[3]; + dst.Value.Bytes[6] = dst.Value.Bytes[3]; + dst.Value.Bytes[5] = src.Value.Bytes[2]; + dst.Value.Bytes[4] = dst.Value.Bytes[2]; + dst.Value.Bytes[3] = src.Value.Bytes[1]; + dst.Value.Bytes[2] = dst.Value.Bytes[1]; + dst.Value.Bytes[1] = src.Value.Bytes[0]; + } + SET_OP(Context, 0, &dst); + break; + + case ND_INS_PXOR: + GET_OP(Context, 0, &dst); + GET_OP(Context, 1, &src); + for (uint32_t i = 0; i < dst.Size; i++) + { + dst.Value.Bytes[i] ^= src.Value.Bytes[i]; + } + SET_OP(Context, 0, &dst); + break; + + // Some basic AVX/AVX2 instructions support. + case ND_INS_VMOVD: + case ND_INS_VMOVQ: + case ND_INS_VMOVDQU: + case ND_INS_VMOVDQA: + // First clear out the entire register. If less than MAX_VL bits are written, the upper bits are set to 0. + nd_memzero(src.Value.Bytes, sizeof(src.Value.Bytes)); + nd_memzero(dst.Value.Bytes, sizeof(dst.Value.Bytes)); + dst.Size = ND_MAX_REGISTER_SIZE; + SET_OP(Context, 0, &dst); + // Fetch the source, and write the destination. + GET_OP(Context, 1, &src); + SET_OP(Context, 0, &src); + break; + + case ND_INS_VPBROADCASTB: + case ND_INS_VPBROADCASTW: + case ND_INS_VPBROADCASTD: + case ND_INS_VPBROADCASTQ: + GET_OP(Context, 1, &src); + dst.Size = Context->Instruction.Operands[0].Size; + for (uint32_t i = 0; i < dst.Size / src.Size; i++) + { + switch (src.Size) + { + case 1: + dst.Value.Bytes[i] = src.Value.Bytes[0]; + break; + case 2: + dst.Value.Words[i] = src.Value.Words[0]; + break; + case 4: + dst.Value.Dwords[i] = src.Value.Dwords[0]; + break; + default: + dst.Value.Qwords[i] = src.Value.Qwords[0]; + break; + } + } + SET_OP(Context, 0, &dst); + break; + + case ND_INS_VPXOR: + GET_OP(Context, 1, &dst); + GET_OP(Context, 2, &src); + for (uint32_t i = 0; i < dst.Size; i++) + { + dst.Value.Bytes[i] ^= src.Value.Bytes[i]; + } + SET_OP(Context, 0, &dst); + break; + + // Software interrupt/SYSCALL/SYSENTER. + case ND_INS_INT: + if (Context->Instruction.Immediate1 == 0x80 || + Context->Instruction.Immediate1 == 0x2E) + { + Context->Flags |= SHEMU_FLAG_SYSCALL; + } + + stop = true; + break; + + case ND_INS_SYSCALL: + case ND_INS_SYSENTER: + Context->Flags |= SHEMU_FLAG_SYSCALL; + stop = true; + break; + + // Some basic privileged instructions supported, specific to kernel-mode shellcodes. + case ND_INS_SWAPGS: + if (Context->Ring != 0) + { + return SHEMU_ABORT_NO_PRIVILEGE; + } + + Context->Flags |= SHEMU_FLAG_SWAPGS; + stop = true; + break; + + case ND_INS_RDMSR: + if (Context->Ring != 0) + { + return SHEMU_ABORT_NO_PRIVILEGE; + } + + if ((Context->Registers.RegRcx == 0xC0000082 && ND_CODE_64 == Context->Mode) || + (Context->Registers.RegRcx == 0x00000176 && ND_CODE_32 == Context->Mode)) + { + Context->Flags |= SHEMU_FLAG_SYSCALL_MSR_READ; + } + + stop = true; + break; + + case ND_INS_WRMSR: + if (Context->Ring != 0) + { + return SHEMU_ABORT_NO_PRIVILEGE; + } + + if ((Context->Registers.RegRcx == 0xC0000082 && ND_CODE_64 == Context->Mode) || + (Context->Registers.RegRcx == 0x00000176 && ND_CODE_32 == Context->Mode)) + { + Context->Flags |= SHEMU_FLAG_SYSCALL_MSR_WRITE; + } + + stop = true; + break; + + default: + return SHEMU_ABORT_UNSUPPORTED_INSTRUX; + } + } + + // Minimum percent of the instructions were NOPs => consider we have a NOP sled. Note that we get here only if + // the maximum number of instructions has been emulated successfully; if the emulation is aborted for any reason, + // this code will have no effect. + if ((Context->InstructionsCount >= Context->MaxInstructionsCount / 2) && + (Context->NopCount >= Context->InstructionsCount * Context->NopThreshold / 100)) + { + Context->Flags |= SHEMU_FLAG_NOP_SLED; + return SHEMU_ABORT_SHELLCODE_DETECTED; + } + + return SHEMU_SUCCESS; +} diff --git a/bdshemu/bdshemu.vcxproj b/bdshemu/bdshemu.vcxproj new file mode 100644 index 0000000..8b8e939 --- /dev/null +++ b/bdshemu/bdshemu.vcxproj @@ -0,0 +1,413 @@ + + + + + DebugKernel + Win32 + + + DebugKernel + x64 + + + Debug + Win32 + + + ReleaseKernel + Win32 + + + ReleaseKernel + x64 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA} + Win32Proj + bdshemu + 10.0.18362.0 + + + + StaticLibrary + true + v142 + Unicode + + + StaticLibrary + true + v142 + Unicode + + + StaticLibrary + false + v142 + false + Unicode + + + StaticLibrary + false + v142 + true + Unicode + + + StaticLibrary + true + v142 + Unicode + + + StaticLibrary + true + v142 + Unicode + + + StaticLibrary + false + v142 + false + Unicode + + + StaticLibrary + false + v142 + false + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + .lib + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + + + true + .lib + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + + + true + .lib + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + + + true + .lib + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + + + false + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + .lib + + + false + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + .lib + + + false + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + .lib + + + false + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + .lib + + + + NotUsing + Level4 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + + + ..\inc;..\bddisasm\include;%(AdditionalIncludeDirectories) + true + $(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb + + + Console + true + bddisasm.lib;%(AdditionalDependencies) + $(SolutionDir)bin\$(Platform)\$(Configuration);%(AdditionalLibraryDirectories) + + + + + NotUsing + Level4 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + + + ..\inc;..\bddisasm\include;%(AdditionalIncludeDirectories) + true + $(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb + + + Console + true + bddisasm.lib;%(AdditionalDependencies) + $(SolutionDir)bin\$(Platform)\$(Configuration);%(AdditionalLibraryDirectories) + + + + + NotUsing + Level4 + Disabled + WIN32;_DEBUG;_LIB;DEBUG;%(PreprocessorDefinitions) + + + ..\inc;..\bddisasm\include;%(AdditionalIncludeDirectories) + true + true + Speed + true + $(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb + MultiThreadedDebugDLL + false + Default + false + ProgramDatabase + /D "AMD64" %(AdditionalOptions) + + + Console + true + bddisasm.lib;%(AdditionalDependencies) + $(SolutionDir)bin\$(Platform)\$(Configuration);%(AdditionalLibraryDirectories) + + + true + + + + + NotUsing + Level4 + Disabled + WIN32;_DEBUG;_LIB;DEBUG;%(PreprocessorDefinitions) + + + ..\inc;..\bddisasm\include;%(AdditionalIncludeDirectories) + true + true + Speed + true + $(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb + MultiThreadedDebugDLL + false + Default + false + ProgramDatabase + /D "AMD64" %(AdditionalOptions) + + + Console + true + bddisasm.lib;%(AdditionalDependencies) + $(SolutionDir)bin\$(Platform)\$(Configuration);%(AdditionalLibraryDirectories) + + + true + + + + + Level4 + NotUsing + Disabled + + + true + WIN32;_DEBUG;_LIB;DEBUG;%(PreprocessorDefinitions) + + + ..\inc;..\bddisasm\include;%(AdditionalIncludeDirectories) + true + ProgramDatabase + Default + true + false + Speed + true + false + $(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb + + + Console + true + true + true + bddisasm.lib;%(AdditionalDependencies) + $(SolutionDir)bin\$(Platform)\$(Configuration);%(AdditionalLibraryDirectories) + + + + + Level4 + NotUsing + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + + + ..\inc;..\bddisasm\include;%(AdditionalIncludeDirectories) + true + $(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb + + + Console + true + true + true + bddisasm.lib;%(AdditionalDependencies) + $(SolutionDir)bin\$(Platform)\$(Configuration);%(AdditionalLibraryDirectories) + + + + + Level4 + NotUsing + Disabled + + + true + WIN32;_DEBUG;_LIB;DEBUG;%(PreprocessorDefinitions) + + + ..\inc;..\bddisasm\include;%(AdditionalIncludeDirectories) + true + false + MultiThreadedDLL + false + true + Default + Speed + false + $(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb + Sync + true + /D "AMD64" %(AdditionalOptions) + + + Console + true + true + true + bddisasm.lib;%(AdditionalDependencies) + $(SolutionDir)bin\$(Platform)\$(Configuration);%(AdditionalLibraryDirectories) + + + + true + + + + + Level4 + NotUsing + Disabled + + + true + WIN32;_DEBUG;_LIB;DEBUG;%(PreprocessorDefinitions) + + + ..\inc;..\bddisasm\include;%(AdditionalIncludeDirectories) + true + false + MultiThreadedDLL + false + true + Default + Speed + false + $(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb + Sync + true + /D "AMD64" %(AdditionalOptions) + + + Console + true + true + true + bddisasm.lib;%(AdditionalDependencies) + $(SolutionDir)bin\$(Platform)\$(Configuration);%(AdditionalLibraryDirectories) + + + + true + + + + + + + + + + + + \ No newline at end of file diff --git a/bdshemu/bdshemu.vcxproj.filters b/bdshemu/bdshemu.vcxproj.filters new file mode 100644 index 0000000..626a3f0 --- /dev/null +++ b/bdshemu/bdshemu.vcxproj.filters @@ -0,0 +1,30 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + {e9031566-ae16-49a2-807a-b33729f7b1d4} + + + + + Source Files + + + + + Header Files\public + + + \ No newline at end of file diff --git a/bdshemu_fuzz/Makefile b/bdshemu_fuzz/Makefile new file mode 100644 index 0000000..63eb772 --- /dev/null +++ b/bdshemu_fuzz/Makefile @@ -0,0 +1,73 @@ +# Look for afl-fuzz. If it is in path we assume that afl-gcc/afl-clang/afl-clang-fast is present as well. +ifeq (, $(shell which afl-fuzz)) + $(error "It looks like AFL is not in your path. AFL is available on GitHub: https://github.com/google/AFL") +endif + +# Try to figure out which compiler we should use, afl-clang-fast being the preferred choice. +ifeq (, $(AFL_COMPILER)) + # If AFL_COMPILER is not set, check if afl-clang-fast is available. + ifeq (, $(shell which afl-clang-fast)) + # If it is not, try to figure out if we should use afl-gcc or afl-clang. + ifeq "$(findstring clang, $(shell $(CC) --version 2>/dev/null))" "" + AFL_COMPILER = afl-gcc + else + AFL_COMPILER = afl-clang + endif + else + # If it is available, use it. + AFL_COMPILER = afl-clang-fast + endif +endif + +ROOT_DIR := $(realpath ..) +DISASM_SRC := $(ROOT_DIR)/bddisasm +DISASM_INC := $(DISASM_SRC)/include +SHEMU_SRC := $(ROOT_DIR)/bdshemu +PUBLIC_INC := $(ROOT_DIR)/inc +SHEMU_INC := $(PUBLIC_INC)/bdshemu +FUZZER_SRC := $(ROOT_DIR)/bdshemu_fuzz + +ALL_SRC := $(shell find $(DISASM_SRC)/*.c -type f) +ALL_SRC += $(shell find $(SHEMU_SRC)/*.c -type f) +ALL_SRC += $(shell find $(FUZZER_SRC)/*.c -type f) + +ALL_INC := $(shell find $(DISASM_INC)/*.h -type f) +ALL_INC += $(shell find $(PUBLIC_INC)/*.h -type f) +ALL_INC += $(shell find $(SHEMU_INC)/*.h -type f) + +# Enable qui ck and dirty mode, if needed. +ifeq ($(DIRTY),y) + AFL_ARGS := -d +endif + +ifdef AFL_MEMORY + AFL_ARGS := -m $(AFL_MEMORY) +endif + +CFLAGS := -std=c11 -fpic -fno-strict-aliasing \ + -D_REENTRANT -fstack-protector -ffunction-sections -fdata-sections \ + -DNDEBUG -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=1 -Ofast -g3 + +ifeq ($(LOG),y) + PREDEFS := -DENABLE_LOGGING +endif + +# Build shfuzz with AFL instrumentation. +shfuzz: $(ALL_SRC) $(ALL_INC) + @echo "Using $(AFL_COMPILER) as a compiler" + @$(AFL_COMPILER) $(PREDEFS) $(CFLAGS) -I$(DISASM_INC) -I$(PUBLIC_INC) -I$(SHEMU_INC) $(ALL_SRC) -o shfuzz + @echo "Done!" + +# Run the tests in 32-bit mode. +.PHONY: fuzz32 +fuzz32: shfuzz + @afl-fuzz -i ./in-32 -o ./out-32 $(AFL_ARGS) ./shfuzz @@ 32 + +# Run the tests in 64-bit mode. +.PHONY: fuzz64 +fuzz64: shfuzz + @afl-fuzz -i ./in-64 -o ./out-64 $(AFL_ARGS) ./shfuzz @@ 64 + +.PHONY: clean +clean: + @rm -f ./shfuzz diff --git a/bdshemu_fuzz/README.md b/bdshemu_fuzz/README.md new file mode 100644 index 0000000..66d0235 --- /dev/null +++ b/bdshemu_fuzz/README.md @@ -0,0 +1,49 @@ +# Bitdefender Shellocde Emulator Fuzzer + +This assumes that you have [AFL](https://github.com/google/AFL) in your path. + +It collects the `bddisasm` and `bdshemu` sources into a single executable, built with AFL instrumentation. + +## Getting started + +Build it with `make shfuzz`. + +Start fuzzing with `make fuzz32` (for 32-bit mode samples) or `make fuzz64` (for 64-bit mode samples). + +If you're in a hurry you can fuzz in the quick and dirty mode with `DIRTY=y`: `make fuzz32 DIRTY=y` or `make fuzz64 DIRTY=y`. + +Activate support for [address sanitizer](https://github.com/google/sanitizers/wiki/AddressSanitizer) with `AFL_USE_ASAN=1 make shfuzz`. This can uncover more bugs, but it is a lot slower and requires more memory. + +Input files are in the `in-32` and `in-64` directories, crashes will be in `out-32/crashes` or `out-64/crashes`, hangs will be in `out-32/hangs` or `out-64/hangs`. + +## Details + +If the `AFL_COMPILER` variable is not set, the build process looks for `afl-clang-fast` and if it is available, the tool is compiled with that. If not, it tries to choose between `afl-clang` and `afl-gcc`. +If you want to use a certain compiler simply set `AFL_COMPILER` before invoking make: `AFL_COMPILER=afl-gcc make`. +Note that `afl-clang-fast` is not compiled by default when compiling AFL. See [llvm mode](https://github.com/google/AFL/tree/master/llvm_mode) in the AFL repository. + +Run the fuzzer in 32-bit mode with `make fuzz32`, or in 64-bit mode with `make fuzz64`. + +If you want to take advantage of multiple cores see [parallel fuzzing](https://github.com/google/AFL/blob/master/docs/parallel_fuzzing.txt). + +If `afl-clang-fast` is used, we try to use AFL in persistent mode, which should provide better performance. + +Note that both `fuzz32` and `fuzz64` assume that the tool was compiled with `afl-clang-fast`, `afl-clang`, or `afl-gcc`. + +ASAN builds will have increased memory requirements. You may need to tweak the `-m` parameter (or set `AFL_MEMORY`) for `afl-fuzz` (see [notes for ASAN](https://github.com/google/AFL/blob/master/docs/notes_for_asan.txt)). + +By default, all logging is disabled, as it is already not visible while AFL is running. Compile with `LOG=y` in order to enable some minimal logging. + +## Using the tool + +The `shfuzz` tool is a simplified version of `disasmtool`. It takes 3 positional arguments: + +```bash +shfuzz file mode use_logging +``` + +- file - the path to a input file that contains instructions to be disassembled and emulated; +- mode - the mode in which to run: `32` for 32-bit instructions, `64` for 64-bit instruction; +- use_logging - if present, will actually log everything that `bdshemu` wants to log; even if absent, the `ShemuLog` implementation will still try to access every character in the string it should normally print, so if you want to find bugs related to logging you can still do, but it is a lot faster when the strings don't get printed. This is ignored if you compile `shfuzz` without `LOG=y`. + +Any errors encountered while parsing the arguments, trying to open the input file, or allocate memory are handled by calling `abort()`. This makes it easier to detect these problems. diff --git a/bdshemu_fuzz/bdshemu_fuzzer.c b/bdshemu_fuzz/bdshemu_fuzzer.c new file mode 100644 index 0000000..47a366c --- /dev/null +++ b/bdshemu_fuzz/bdshemu_fuzzer.c @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2020 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +#define _CRT_SECURE_NO_WARNINGS + +#include +#include +#include +#include +#include +#include +#include "bddisasm.h" +#include "bdshemu.h" + +#ifdef ENABLE_LOGGING +#define LOG(fmt, ...) printf(fmt, ##__VA_ARGS__) +#else +#define LOG(fmt, ...) +#endif // ENABLE_LOGGING + +#ifndef __AFL_LOOP +#warning "Persistent mode will not work (you are probably not using afl-clang-fast)" +#endif + +int nd_vsnprintf_s( + char *buffer, + size_t sizeOfBuffer, + size_t count, + const char *format, + va_list argptr +) +{ + return vsnprintf(buffer, sizeOfBuffer, format, argptr); +} + +void *nd_memset(void *s, int c, size_t n) +{ + return memset(s, c, n); +} + +uint8_t *read_file(const char *fpath, size_t *size) +{ + uint8_t *buffer; + FILE *fd = fopen(fpath, "rb"); + if (fd == NULL) + { + LOG("[-] Failed to open \"%s\"\n", fpath); + return NULL; + } + + fseek(fd, 0ull, SEEK_END); + *size = ftell(fd); + rewind(fd); + + buffer = malloc(*size); + if (buffer == NULL) + { + LOG("[-] Failed to allocate %zu bytes\n", *size); + } + else + { + fread(buffer, *size, 1, fd); + } + + fclose(fd); + return buffer; +} + +static bool gUseLog; + +void ShemuLog(char *data) +{ + if (gUseLog) + { + LOG("%s", data); + } +} + +void run_shemu(uint8_t *Data, size_t Size, uint8_t Def) +{ + // More or less copy pasted from disasmtool + + SHEMU_CONTEXT ctx = { 0 }; + SHEMU_STATUS shs; + + ctx.Shellcode = Data; + + ctx.Stack = calloc(1, 0x2000); + if (ctx.Stack == NULL) + { + LOG("[-] Failed to allocate Stack!\n"); + abort(); + } + + ctx.Intbuf = calloc(1, Size + 0x2000); + if (ctx.Stack == NULL) + { + LOG("[-] Failed to allocate Intbuf!\n"); + abort(); + } + + ctx.ShellcodeBase = 0x200000; + ctx.ShellcodeSize = (uint32_t)Size; + ctx.StackBase = 0x100000; + ctx.StackSize = 0x2000; + ctx.Registers.RegRsp = 0x101000; + ctx.IntbufSize = (uint32_t)Size + 0x2000; + + ctx.Registers.RegFlags = REG_RFLAG_IF | 2; + ctx.Registers.RegRip = ctx.ShellcodeBase; + + ctx.Segments.Cs.Selector = 0x10; + ctx.Segments.Ds.Selector = 0x28; + ctx.Segments.Es.Selector = 0x28; + ctx.Segments.Ss.Selector = 0x28; + ctx.Segments.Fs.Selector = 0x30; + ctx.Segments.Fs.Base = 0x7FFF0000; + ctx.Segments.Gs.Selector = 0x30; + ctx.Segments.Gs.Base = 0x7FFF0000; + + ctx.Mode = Def; + ctx.Ring = 3; + ctx.TibBase = ctx.Mode == ND_CODE_32 ? ctx.Segments.Fs.Base : ctx.Segments.Gs.Base; + ctx.MaxInstructionsCount = 4096; + ctx.Log = &ShemuLog; + ctx.Flags = 0; + ctx.Options = SHEMU_OPT_TRACE_EMULATION; + + shs = ShemuEmulate(&ctx); + LOG("[+] Shemu returned: 0x%08x\n", shs); + + free(ctx.Intbuf); + free(ctx.Stack); +} + +void run_test(uint8_t *Data, size_t Size, uint8_t Def) +{ + run_shemu(Data, Size, Def); +} + +int8_t arch_to_def_code(const char *arch) +{ + uint32_t a = strtoul(arch, NULL, 0); + + switch (a) + { + case 16: + return ND_CODE_16; + + case 32: + return ND_CODE_32; + + case 64: + return ND_CODE_64; + + default: + LOG("[-] Unknown arch: \"%s\"\n", arch); + return -1; + } +} + +int main(int argc, char **argv) +{ + size_t size = 0; + uint8_t *buffer; + int8_t defCode; + + if (argc < 3) + { + LOG("[-] Missing arguments: <16|32|64> [activate shemu print]\n"); + abort(); + } + + defCode = arch_to_def_code(argv[2]); + if (defCode == -1) + { + abort(); + } + + if (argc >= 4) + { + LOG("[+] Will activate ShemuLog\n"); + gUseLog = true; + } + else + { + gUseLog = false; + } + + LOG("[+] Using def code/data = %d\n", defCode); + +// __AFL_LOOP is defined only when compiling with afl-clang-fast and allows us to use +// AFL's persistent mode. We still want to be able to compile and run even if we are +// using afl-gcc or afl-clang, but there is no reason to actually have a loop here +// if we are not using persistent mode. +#ifdef __AFL_LOOP + while (__AFL_LOOP(1000)) +#endif // __AFL_LOOP + { + LOG("[+] Reading data from \"%s\"\n", argv[1]); + buffer = read_file(argv[1], &size); + if (buffer == NULL) + { + abort(); + } + + LOG("[+] Read %zu bytes at %p (range: [%p, %p))\n", size, buffer, buffer, buffer + size); + + run_test(buffer, size, (uint8_t)defCode); + + free(buffer); + } + + LOG("[+] Done!\n"); + + return 0; +} diff --git a/bdshemu_fuzz/in-32/test_32_str01 b/bdshemu_fuzz/in-32/test_32_str01 new file mode 100644 index 0000000..a496946 --- /dev/null +++ b/bdshemu_fuzz/in-32/test_32_str01 @@ -0,0 +1 @@ +AAAAP \ No newline at end of file diff --git a/bdshemu_fuzz/in-32/test_32_str02 b/bdshemu_fuzz/in-32/test_32_str02 new file mode 100644 index 0000000..f1921e6 --- /dev/null +++ b/bdshemu_fuzz/in-32/test_32_str02 @@ -0,0 +1 @@ +AAAAPP \ No newline at end of file diff --git a/bdshemu_fuzz/in-32/test_32_str03 b/bdshemu_fuzz/in-32/test_32_str03 new file mode 100644 index 0000000000000000000000000000000000000000..50339f7cea9230eacdb78078e48f0e206d2de565 GIT binary patch literal 13 Rcmdnt2m}E;fCNLpVE`b>1e*W= literal 0 HcmV?d00001 diff --git a/bdshemu_fuzz/in-32/test_32_str04 b/bdshemu_fuzz/in-32/test_32_str04 new file mode 100644 index 0000000..d82cac6 --- /dev/null +++ b/bdshemu_fuzz/in-32/test_32_str04 @@ -0,0 +1 @@ +AAAAPSPSPSPS \ No newline at end of file diff --git a/bdshemu_fuzz/in-32/test_32_sys01 b/bdshemu_fuzz/in-32/test_32_sys01 new file mode 100644 index 0000000..44fd652 --- /dev/null +++ b/bdshemu_fuzz/in-32/test_32_sys01 @@ -0,0 +1 @@ +4 \ No newline at end of file diff --git a/bdshemu_fuzz/in-32/test_64_basic01 b/bdshemu_fuzz/in-32/test_64_basic01 new file mode 100644 index 0000000000000000000000000000000000000000..8f5c11a35eff768769072d873c9c7d600e495702 GIT binary patch literal 12 PcmdmC00imB89)>O87Bj0 literal 0 HcmV?d00001 diff --git a/bdshemu_fuzz/in-32/test_64_basic04 b/bdshemu_fuzz/in-32/test_64_basic04 new file mode 100644 index 0000000..ca7ec3c --- /dev/null +++ b/bdshemu_fuzz/in-32/test_64_basic04 @@ -0,0 +1 @@ +H500000000 \ No newline at end of file diff --git a/bdshemu_fuzz/in-32/test_64_basic05 b/bdshemu_fuzz/in-32/test_64_basic05 new file mode 100644 index 0000000..f65f496 --- /dev/null +++ b/bdshemu_fuzz/in-32/test_64_basic05 @@ -0,0 +1 @@ +H-000H \ No newline at end of file diff --git a/bdshemu_fuzz/in-32/test_64_basic06 b/bdshemu_fuzz/in-32/test_64_basic06 new file mode 100644 index 0000000..d2f9396 --- /dev/null +++ b/bdshemu_fuzz/in-32/test_64_basic06 @@ -0,0 +1 @@ +000 \ No newline at end of file diff --git a/bdshemu_fuzz/in-32/test_64_basic07 b/bdshemu_fuzz/in-32/test_64_basic07 new file mode 100644 index 0000000..d50394e --- /dev/null +++ b/bdshemu_fuzz/in-32/test_64_basic07 @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/bdshemu_fuzz/in-32/test_64_basic08 b/bdshemu_fuzz/in-32/test_64_basic08 new file mode 100644 index 0000000..e276e00 --- /dev/null +++ b/bdshemu_fuzz/in-32/test_64_basic08 @@ -0,0 +1 @@ +00 \ No newline at end of file diff --git a/bdshemu_fuzz/in-32/test_64_basic09 b/bdshemu_fuzz/in-32/test_64_basic09 new file mode 100644 index 0000000..32897ec --- /dev/null +++ b/bdshemu_fuzz/in-32/test_64_basic09 @@ -0,0 +1 @@ +H000H0000 \ No newline at end of file diff --git a/bdshemu_fuzz/in-32/test_64_branch1 b/bdshemu_fuzz/in-32/test_64_branch1 new file mode 100644 index 0000000..d721910 --- /dev/null +++ b/bdshemu_fuzz/in-32/test_64_branch1 @@ -0,0 +1,2 @@ +r +0000000000 \ No newline at end of file diff --git a/bdshemu_fuzz/in-32/test_64_branch2 b/bdshemu_fuzz/in-32/test_64_branch2 new file mode 100644 index 0000000000000000000000000000000000000000..641d8ca7db98f1125f8a80be27893e6d47239f80 GIT binary patch literal 20 acmdn-9|)QcFcuql^qLwNFfbfrGXMa5M+pJ| literal 0 HcmV?d00001 diff --git a/bdshemu_fuzz/in-32/test_64_branch3 b/bdshemu_fuzz/in-32/test_64_branch3 new file mode 100644 index 0000000..248a450 --- /dev/null +++ b/bdshemu_fuzz/in-32/test_64_branch3 @@ -0,0 +1,2 @@ +1t +0000000000 \ No newline at end of file diff --git a/bdshemu_fuzz/in-32/test_64_branch4 b/bdshemu_fuzz/in-32/test_64_branch4 new file mode 100644 index 0000000000000000000000000000000000000000..808fc0fa220fdd6025c3d71065fe24dd858c5bf9 GIT binary patch literal 14 VcmXp!P-@`OYihv2z;KMs001FV1I+*c literal 0 HcmV?d00001 diff --git a/bdshemu_fuzz/in-32/test_64_div b/bdshemu_fuzz/in-32/test_64_div new file mode 100644 index 0000000..cf016d0 --- /dev/null +++ b/bdshemu_fuzz/in-32/test_64_div @@ -0,0 +1 @@ +H000000001f \ No newline at end of file diff --git a/bdshemu_fuzz/in-32/test_64_flags b/bdshemu_fuzz/in-32/test_64_flags new file mode 100644 index 0000000..b576f38 --- /dev/null +++ b/bdshemu_fuzz/in-32/test_64_flags @@ -0,0 +1 @@ +1100101000001000010000010000010000100000 \ No newline at end of file diff --git a/bdshemu_fuzz/in-32/test_64_loadrip01 b/bdshemu_fuzz/in-32/test_64_loadrip01 new file mode 100644 index 0000000000000000000000000000000000000000..a35c72c9ed6d95747c2fb4fb435b920ab8adca9f GIT binary patch literal 7 McmaFC00gmz0SDXy2><{9 literal 0 HcmV?d00001 diff --git a/bdshemu_fuzz/in-32/test_64_loadrip02 b/bdshemu_fuzz/in-32/test_64_loadrip02 new file mode 100644 index 0000000..7df5071 --- /dev/null +++ b/bdshemu_fuzz/in-32/test_64_loadrip02 @@ -0,0 +1 @@ +$HH$ \ No newline at end of file diff --git a/bdshemu_fuzz/in-32/test_64_loadrip03 b/bdshemu_fuzz/in-32/test_64_loadrip03 new file mode 100644 index 0000000000000000000000000000000000000000..967b50d78301dabe5a6dc0a9e1351b8308c3b093 GIT binary patch literal 12 ScmaFC00f3_J(zV=&Hw-u-2-j_ literal 0 HcmV?d00001 diff --git a/bdshemu_fuzz/in-32/test_64_mov b/bdshemu_fuzz/in-32/test_64_mov new file mode 100644 index 0000000..a56f773 --- /dev/null +++ b/bdshemu_fuzz/in-32/test_64_mov @@ -0,0 +1 @@ +00H0000fHf00ظ0000ͫ H$H$ \ No newline at end of file diff --git a/bdshemu_fuzz/in-32/test_64_nopsled01 b/bdshemu_fuzz/in-32/test_64_nopsled01 new file mode 100644 index 0000000..237ddeb --- /dev/null +++ b/bdshemu_fuzz/in-32/test_64_nopsled01 @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/bdshemu_fuzz/in-32/test_64_nopsled02 b/bdshemu_fuzz/in-32/test_64_nopsled02 new file mode 100644 index 0000000..f7b91e4 --- /dev/null +++ b/bdshemu_fuzz/in-32/test_64_nopsled02 @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/bdshemu_fuzz/in-32/test_64_selfwrite02 b/bdshemu_fuzz/in-32/test_64_selfwrite02 new file mode 100644 index 0000000000000000000000000000000000000000..2e80d43c3dc87ef49de842230ad9f9ccf3716b1a GIT binary patch literal 11 Scmeb1H8n6`VDRYtz6Jmirvu*r literal 0 HcmV?d00001 diff --git a/bdshemu_fuzz/in-32/test_64_selfwrite03 b/bdshemu_fuzz/in-32/test_64_selfwrite03 new file mode 100644 index 0000000000000000000000000000000000000000..6b0248036e92750230613b72a1f217f537dac38d GIT binary patch literal 18 Wcmeb1RW&eRVDQ*s00a|&AOHX^R|Ts8 literal 0 HcmV?d00001 diff --git a/bdshemu_fuzz/in-32/test_64_string b/bdshemu_fuzz/in-32/test_64_string new file mode 100644 index 0000000000000000000000000000000000000000..fc2d4fd2945c5cd8c350fe62a7d4104a22dd2745 GIT binary patch literal 15 Ucmeb1H8n6`VDRX*H2{Jo03FK%;Q#;t literal 0 HcmV?d00001 diff --git a/bdshemu_fuzz/in-32/test_64_sys01 b/bdshemu_fuzz/in-32/test_64_sys01 new file mode 100644 index 0000000..b688912 --- /dev/null +++ b/bdshemu_fuzz/in-32/test_64_sys01 @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/bdshemu_fuzz/in-32/test_64_sys02 b/bdshemu_fuzz/in-32/test_64_sys02 new file mode 100644 index 0000000..9fe1505 --- /dev/null +++ b/bdshemu_fuzz/in-32/test_64_sys02 @@ -0,0 +1 @@ +̀ \ No newline at end of file diff --git a/bdshemu_fuzz/in-32/test_64_sys03 b/bdshemu_fuzz/in-32/test_64_sys03 new file mode 100644 index 0000000..07271e9 --- /dev/null +++ b/bdshemu_fuzz/in-32/test_64_sys03 @@ -0,0 +1 @@ +0 \ No newline at end of file diff --git a/bdshemu_fuzz/in-64/test_32_str01 b/bdshemu_fuzz/in-64/test_32_str01 new file mode 100644 index 0000000..a496946 --- /dev/null +++ b/bdshemu_fuzz/in-64/test_32_str01 @@ -0,0 +1 @@ +AAAAP \ No newline at end of file diff --git a/bdshemu_fuzz/in-64/test_32_str02 b/bdshemu_fuzz/in-64/test_32_str02 new file mode 100644 index 0000000..f1921e6 --- /dev/null +++ b/bdshemu_fuzz/in-64/test_32_str02 @@ -0,0 +1 @@ +AAAAPP \ No newline at end of file diff --git a/bdshemu_fuzz/in-64/test_32_str04 b/bdshemu_fuzz/in-64/test_32_str04 new file mode 100644 index 0000000..d82cac6 --- /dev/null +++ b/bdshemu_fuzz/in-64/test_32_str04 @@ -0,0 +1 @@ +AAAAPSPSPSPS \ No newline at end of file diff --git a/bdshemu_fuzz/in-64/test_32_sys01 b/bdshemu_fuzz/in-64/test_32_sys01 new file mode 100644 index 0000000..44fd652 --- /dev/null +++ b/bdshemu_fuzz/in-64/test_32_sys01 @@ -0,0 +1 @@ +4 \ No newline at end of file diff --git a/bdshemu_fuzz/in-64/test_64_basic01 b/bdshemu_fuzz/in-64/test_64_basic01 new file mode 100644 index 0000000000000000000000000000000000000000..8f5c11a35eff768769072d873c9c7d600e495702 GIT binary patch literal 12 PcmdmC00imB89)>O87Bj0 literal 0 HcmV?d00001 diff --git a/bdshemu_fuzz/in-64/test_64_basic02 b/bdshemu_fuzz/in-64/test_64_basic02 new file mode 100644 index 0000000000000000000000000000000000000000..fdc40651404637e399ba57fe43f4e99eed118d5e GIT binary patch literal 13 Ucmeb1)&2SZ|Nm}RhHlrx05xj|TmS$7 literal 0 HcmV?d00001 diff --git a/bdshemu_fuzz/in-64/test_64_basic03 b/bdshemu_fuzz/in-64/test_64_basic03 new file mode 100644 index 0000000000000000000000000000000000000000..f525dcfdbe5e59d257af15003c1a53c7707b90e7 GIT binary patch literal 13 Scmeb1)ip3MVCZfIk_G@73j<>S literal 0 HcmV?d00001 diff --git a/bdshemu_fuzz/in-64/test_64_basic04 b/bdshemu_fuzz/in-64/test_64_basic04 new file mode 100644 index 0000000..fd8ccb9 --- /dev/null +++ b/bdshemu_fuzz/in-64/test_64_basic04 @@ -0,0 +1 @@ +H50000 \ No newline at end of file diff --git a/bdshemu_fuzz/in-64/test_64_basic05 b/bdshemu_fuzz/in-64/test_64_basic05 new file mode 100644 index 0000000..2c47392 --- /dev/null +++ b/bdshemu_fuzz/in-64/test_64_basic05 @@ -0,0 +1 @@ +H-00H \ No newline at end of file diff --git a/bdshemu_fuzz/in-64/test_64_basic06 b/bdshemu_fuzz/in-64/test_64_basic06 new file mode 100644 index 0000000..d2f9396 --- /dev/null +++ b/bdshemu_fuzz/in-64/test_64_basic06 @@ -0,0 +1 @@ +000 \ No newline at end of file diff --git a/bdshemu_fuzz/in-64/test_64_basic07 b/bdshemu_fuzz/in-64/test_64_basic07 new file mode 100644 index 0000000..d50394e --- /dev/null +++ b/bdshemu_fuzz/in-64/test_64_basic07 @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/bdshemu_fuzz/in-64/test_64_basic08 b/bdshemu_fuzz/in-64/test_64_basic08 new file mode 100644 index 0000000..e276e00 --- /dev/null +++ b/bdshemu_fuzz/in-64/test_64_basic08 @@ -0,0 +1 @@ +00 \ No newline at end of file diff --git a/bdshemu_fuzz/in-64/test_64_branch1 b/bdshemu_fuzz/in-64/test_64_branch1 new file mode 100644 index 0000000..d721910 --- /dev/null +++ b/bdshemu_fuzz/in-64/test_64_branch1 @@ -0,0 +1,2 @@ +r +0000000000 \ No newline at end of file diff --git a/bdshemu_fuzz/in-64/test_64_branch2 b/bdshemu_fuzz/in-64/test_64_branch2 new file mode 100644 index 0000000000000000000000000000000000000000..d0b8317e8f378b75a52c683fc9d3748e09b7b1c1 GIT binary patch literal 21 bcmdn-9|)QcFcuql^qMj=FfbfrJ7WLPz;KN1i~#^8AOvgx literal 0 HcmV?d00001 diff --git a/bdshemu_fuzz/in-64/test_64_div b/bdshemu_fuzz/in-64/test_64_div new file mode 100644 index 0000000..5546024 --- /dev/null +++ b/bdshemu_fuzz/in-64/test_64_div @@ -0,0 +1 @@ +H00000000f1f \ No newline at end of file diff --git a/bdshemu_fuzz/in-64/test_64_flags b/bdshemu_fuzz/in-64/test_64_flags new file mode 100644 index 0000000..b576f38 --- /dev/null +++ b/bdshemu_fuzz/in-64/test_64_flags @@ -0,0 +1 @@ +1100101000001000010000010000010000100000 \ No newline at end of file diff --git a/bdshemu_fuzz/in-64/test_64_loadrip01 b/bdshemu_fuzz/in-64/test_64_loadrip01 new file mode 100644 index 0000000000000000000000000000000000000000..a35c72c9ed6d95747c2fb4fb435b920ab8adca9f GIT binary patch literal 7 McmaFC00gmz0SDXy2><{9 literal 0 HcmV?d00001 diff --git a/bdshemu_fuzz/in-64/test_64_loadrip02 b/bdshemu_fuzz/in-64/test_64_loadrip02 new file mode 100644 index 0000000..7df5071 --- /dev/null +++ b/bdshemu_fuzz/in-64/test_64_loadrip02 @@ -0,0 +1 @@ +$HH$ \ No newline at end of file diff --git a/bdshemu_fuzz/in-64/test_64_loadrip03 b/bdshemu_fuzz/in-64/test_64_loadrip03 new file mode 100644 index 0000000000000000000000000000000000000000..967b50d78301dabe5a6dc0a9e1351b8308c3b093 GIT binary patch literal 12 ScmaFC00f3_J(zV=&Hw-u-2-j_ literal 0 HcmV?d00001 diff --git a/bdshemu_fuzz/in-64/test_64_mov b/bdshemu_fuzz/in-64/test_64_mov new file mode 100644 index 0000000..a56f773 --- /dev/null +++ b/bdshemu_fuzz/in-64/test_64_mov @@ -0,0 +1 @@ +00H0000fHf00ظ0000ͫ H$H$ \ No newline at end of file diff --git a/bdshemu_fuzz/in-64/test_64_nopsled01 b/bdshemu_fuzz/in-64/test_64_nopsled01 new file mode 100644 index 0000000..237ddeb --- /dev/null +++ b/bdshemu_fuzz/in-64/test_64_nopsled01 @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/bdshemu_fuzz/in-64/test_64_nopsled02 b/bdshemu_fuzz/in-64/test_64_nopsled02 new file mode 100644 index 0000000..f7b91e4 --- /dev/null +++ b/bdshemu_fuzz/in-64/test_64_nopsled02 @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/bdshemu_fuzz/in-64/test_64_selfwrite02 b/bdshemu_fuzz/in-64/test_64_selfwrite02 new file mode 100644 index 0000000000000000000000000000000000000000..e2eec5baa041aa64e08c4b7a5d0b2dd303c668d1 GIT binary patch literal 16 Xcmeb1HDzaDVDRYtzQ*9hstJbyDV_#< literal 0 HcmV?d00001 diff --git a/bdshemu_fuzz/in-64/test_64_selfwrite03 b/bdshemu_fuzz/in-64/test_64_selfwrite03 new file mode 100644 index 0000000000000000000000000000000000000000..e3a6490bead0ad138144db21deeed465991523e6 GIT binary patch literal 27 Xcmeb1RTXAnVDQ*60SW>Ppx`h7d=&{H literal 0 HcmV?d00001 diff --git a/bdshemu_fuzz/in-64/test_64_string b/bdshemu_fuzz/in-64/test_64_string new file mode 100644 index 0000000000000000000000000000000000000000..628c4c1e2181e5259f9da4513c8737075c6b419d GIT binary patch literal 172 zcmeb1HH~0kVDRX*Ed)|afMBUd^E(cY=Jy;sS%4y+J(ha(nwmnC_yH-ylb@GCWR~qT q0D%La)&X?~1Et{n9UyVd6aP;f1~C{w1lb_bAhF26AlIPCfB^tw1e*W= literal 0 HcmV?d00001 diff --git a/bdshemu_test/basic/test_32_str03.asm b/bdshemu_test/basic/test_32_str03.asm new file mode 100644 index 0000000..5f7432f --- /dev/null +++ b/bdshemu_test/basic/test_32_str03.asm @@ -0,0 +1,8 @@ + + bits 32 + + mov eax, 0x41414141 + push eax + mov eax, 0x00414141 + push eax + retn \ No newline at end of file diff --git a/bdshemu_test/basic/test_32_str03.result b/bdshemu_test/basic/test_32_str03.result new file mode 100644 index 0000000..bc3d37f --- /dev/null +++ b/bdshemu_test/basic/test_32_str03.result @@ -0,0 +1,31 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 MOV eax, 0x41414141 + RAX = 0x0000000041414141 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200005 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200005 PUSH eax + RAX = 0x0000000041414141 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000100ffc RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200006 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200006 MOV eax, 0x00414141 + RAX = 0x0000000000414141 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000100ffc RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000b PUSH eax + RAX = 0x0000000000414141 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000100ff8 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000c RETN +Emulation terminated with status 0x00000002, flags: 0x0, 0 NOPs diff --git a/bdshemu_test/basic/test_32_str04 b/bdshemu_test/basic/test_32_str04 new file mode 100644 index 0000000..d82cac6 --- /dev/null +++ b/bdshemu_test/basic/test_32_str04 @@ -0,0 +1 @@ +AAAAPSPSPSPS \ No newline at end of file diff --git a/bdshemu_test/basic/test_32_str04.asm b/bdshemu_test/basic/test_32_str04.asm new file mode 100644 index 0000000..4c0a4bb --- /dev/null +++ b/bdshemu_test/basic/test_32_str04.asm @@ -0,0 +1,13 @@ + bits 32 + + mov eax, 0x41414141 + mov ebx, 0xbdbdbdbd + push eax + push ebx + push eax + push ebx + push eax + push ebx + push eax + push ebx + retn diff --git a/bdshemu_test/basic/test_32_str04.result b/bdshemu_test/basic/test_32_str04.result new file mode 100644 index 0000000..fe99dd1 --- /dev/null +++ b/bdshemu_test/basic/test_32_str04.result @@ -0,0 +1,67 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 MOV eax, 0x41414141 + RAX = 0x0000000041414141 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200005 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200005 MOV ebx, 0xbdbdbdbd + RAX = 0x0000000041414141 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x00000000bdbdbdbd + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000a PUSH eax + RAX = 0x0000000041414141 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x00000000bdbdbdbd + RSP = 0x0000000000100ffc RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000b PUSH ebx + RAX = 0x0000000041414141 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x00000000bdbdbdbd + RSP = 0x0000000000100ff8 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000c PUSH eax + RAX = 0x0000000041414141 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x00000000bdbdbdbd + RSP = 0x0000000000100ff4 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000d PUSH ebx + RAX = 0x0000000041414141 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x00000000bdbdbdbd + RSP = 0x0000000000100ff0 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000e PUSH eax + RAX = 0x0000000041414141 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x00000000bdbdbdbd + RSP = 0x0000000000100fec RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000f PUSH ebx + RAX = 0x0000000041414141 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x00000000bdbdbdbd + RSP = 0x0000000000100fe8 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200010 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200010 PUSH eax + RAX = 0x0000000041414141 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x00000000bdbdbdbd + RSP = 0x0000000000100fe4 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200011 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200011 PUSH ebx + RAX = 0x0000000041414141 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x00000000bdbdbdbd + RSP = 0x0000000000100fe0 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200012 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200012 RETN +Emulation terminated with status 0x00000002, flags: 0x0, 0 NOPs diff --git a/bdshemu_test/basic/test_32_sys01 b/bdshemu_test/basic/test_32_sys01 new file mode 100644 index 0000000..44fd652 --- /dev/null +++ b/bdshemu_test/basic/test_32_sys01 @@ -0,0 +1 @@ +4 \ No newline at end of file diff --git a/bdshemu_test/basic/test_32_sys01.asm b/bdshemu_test/basic/test_32_sys01.asm new file mode 100644 index 0000000..6bf2ab4 --- /dev/null +++ b/bdshemu_test/basic/test_32_sys01.asm @@ -0,0 +1,4 @@ + + bits 32 + + sysenter \ No newline at end of file diff --git a/bdshemu_test/basic/test_32_sys01.result b/bdshemu_test/basic/test_32_sys01.result new file mode 100644 index 0000000..a01106b --- /dev/null +++ b/bdshemu_test/basic/test_32_sys01.result @@ -0,0 +1,8 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 SYSENTER +Emulation terminated with status 0x0000000a, flags: 0x10, 0 NOPs + SHEMU_FLAG_SYSCALL diff --git a/bdshemu_test/basic/test_64_basic01 b/bdshemu_test/basic/test_64_basic01 new file mode 100644 index 0000000000000000000000000000000000000000..e462c7337d0551df584cddc3636c35a822cc6c86 GIT binary patch literal 13 ScmdnN!0@*|{Wt>%90mX(Dg-6~ literal 0 HcmV?d00001 diff --git a/bdshemu_test/basic/test_64_basic01.asm b/bdshemu_test/basic/test_64_basic01.asm new file mode 100644 index 0000000..8b5e85f --- /dev/null +++ b/bdshemu_test/basic/test_64_basic01.asm @@ -0,0 +1,6 @@ + + bits 64 + + mov eax, 0x7FFD0000 + mov dword [eax], 0 + retn \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_basic01.result b/bdshemu_test/basic/test_64_basic01.result new file mode 100644 index 0000000..b459e8b --- /dev/null +++ b/bdshemu_test/basic/test_64_basic01.result @@ -0,0 +1,13 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 MOV eax, 0x7ffd0000 + RAX = 0x000000007ffd0000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200005 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200005 MOV dword ptr [eax], 0x00000000 +Emulation terminated with status 0x00000001, flags: 0x0, 0 NOPs diff --git a/bdshemu_test/basic/test_64_basic02 b/bdshemu_test/basic/test_64_basic02 new file mode 100644 index 0000000000000000000000000000000000000000..1aab11424a8cb9fcd79272006f746ee0394953d0 GIT binary patch literal 14 Vcmeb1)&2SZ|Nm}RhHlrthXFnQ2w4CC literal 0 HcmV?d00001 diff --git a/bdshemu_test/basic/test_64_basic02.asm b/bdshemu_test/basic/test_64_basic02.asm new file mode 100644 index 0000000..d1aee95 --- /dev/null +++ b/bdshemu_test/basic/test_64_basic02.asm @@ -0,0 +1,9 @@ + + bits 64 + +_xxx: + lea rbp, [rel _xxx] + mov eax, dword [rbp] + ; This must fail with SHEMU_ABORT_GLA_OUTSIDE + mov eax, dword [rbp - 3] + retn \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_basic02.result b/bdshemu_test/basic/test_64_basic02.result new file mode 100644 index 0000000..4da2a83 --- /dev/null +++ b/bdshemu_test/basic/test_64_basic02.result @@ -0,0 +1,19 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 LEA rbp, [rel 0x200000] + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000200000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200007 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200007 MOV eax, dword ptr [rbp+0x0] + RAX = 0x00000000f92d8d48 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000200000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000a MOV eax, dword ptr [rbp-0x3] +Emulation terminated with status 0x00000001, flags: 0x0, 0 NOPs diff --git a/bdshemu_test/basic/test_64_basic03 b/bdshemu_test/basic/test_64_basic03 new file mode 100644 index 0000000000000000000000000000000000000000..cf9ef600c758cd11cd9bb88abf6aac3c06f96a40 GIT binary patch literal 20 Wcmeb1)#YViVCZiB11A3h$-@9R@CEDu literal 0 HcmV?d00001 diff --git a/bdshemu_test/basic/test_64_basic03.asm b/bdshemu_test/basic/test_64_basic03.asm new file mode 100644 index 0000000..09d54c2 --- /dev/null +++ b/bdshemu_test/basic/test_64_basic03.asm @@ -0,0 +1,8 @@ + + bits 64 + + lea rbp, [rel _xxx] + mov eax, dword [rbp - 4 + 0x100] + mov eax, dword [rbp - 3 + 0x100] + retn +_xxx: \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_basic03.result b/bdshemu_test/basic/test_64_basic03.result new file mode 100644 index 0000000..f4a22ef --- /dev/null +++ b/bdshemu_test/basic/test_64_basic03.result @@ -0,0 +1,19 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 LEA rbp, [rel 0x200014] + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000200014 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200007 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200007 MOV eax, dword ptr [rbp+0xfc] + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000200014 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000d MOV eax, dword ptr [rbp+0xfd] +Emulation terminated with status 0x00000001, flags: 0x0, 0 NOPs diff --git a/bdshemu_test/basic/test_64_basic04 b/bdshemu_test/basic/test_64_basic04 new file mode 100644 index 0000000..ebf5800 --- /dev/null +++ b/bdshemu_test/basic/test_64_basic04 @@ -0,0 +1 @@ +H5 \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_basic04.asm b/bdshemu_test/basic/test_64_basic04.asm new file mode 100644 index 0000000..5a640d1 --- /dev/null +++ b/bdshemu_test/basic/test_64_basic04.asm @@ -0,0 +1,8 @@ + + bits 64 + +_xxx: + lea rsi, [rel _xxx] + mov rcx, 0xFFFFFFFF + rep lodsb + \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_basic04.result b/bdshemu_test/basic/test_64_basic04.result new file mode 100644 index 0000000..8397ec4 --- /dev/null +++ b/bdshemu_test/basic/test_64_basic04.result @@ -0,0 +1,19 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 LEA rsi, [rel 0x200000] + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000200000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200007 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200007 MOV ecx, 0xffffffff + RAX = 0x0000000000000000 RCX = 0x00000000ffffffff RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000200000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000c REP LODSB +Emulation terminated with status 0x00000001, flags: 0x0, 0 NOPs diff --git a/bdshemu_test/basic/test_64_basic05 b/bdshemu_test/basic/test_64_basic05 new file mode 100644 index 0000000..e1cb976 --- /dev/null +++ b/bdshemu_test/basic/test_64_basic05 @@ -0,0 +1 @@ +H-H \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_basic05.asm b/bdshemu_test/basic/test_64_basic05.asm new file mode 100644 index 0000000..5135b80 --- /dev/null +++ b/bdshemu_test/basic/test_64_basic05.asm @@ -0,0 +1,8 @@ + + bits 64 + +_xxx: + lea rbp, [rel _xxx] + sub rbp, 1 + jmp rbp + \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_basic05.result b/bdshemu_test/basic/test_64_basic05.result new file mode 100644 index 0000000..59151a4 --- /dev/null +++ b/bdshemu_test/basic/test_64_basic05.result @@ -0,0 +1,19 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 LEA rbp, [rel 0x200000] + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000200000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200007 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200007 SUB rbp, 0x01 + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x00000000001fffff RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000b RFLAGS = 0x0000000000000206 +Emulating: 0x000000000020000b JMP rbp +Emulation terminated with status 0x00000002, flags: 0x0, 0 NOPs diff --git a/bdshemu_test/basic/test_64_basic06 b/bdshemu_test/basic/test_64_basic06 new file mode 100644 index 0000000..dce5a43 --- /dev/null +++ b/bdshemu_test/basic/test_64_basic06 @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_basic06.asm b/bdshemu_test/basic/test_64_basic06.asm new file mode 100644 index 0000000..47af3f1 --- /dev/null +++ b/bdshemu_test/basic/test_64_basic06.asm @@ -0,0 +1,12 @@ + + bits 64 + +_xxx: + jmp _yyy + + nop + nop + nop + +_yyy: + jmp _xxx - 1 \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_basic06.result b/bdshemu_test/basic/test_64_basic06.result new file mode 100644 index 0000000..c9f6e2a --- /dev/null +++ b/bdshemu_test/basic/test_64_basic06.result @@ -0,0 +1,13 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 JMP 0x200005 + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200005 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200005 JMP 0x1fffff +Emulation terminated with status 0x00000002, flags: 0x0, 0 NOPs diff --git a/bdshemu_test/basic/test_64_basic07 b/bdshemu_test/basic/test_64_basic07 new file mode 100644 index 0000000..d50394e --- /dev/null +++ b/bdshemu_test/basic/test_64_basic07 @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_basic07.asm b/bdshemu_test/basic/test_64_basic07.asm new file mode 100644 index 0000000..9e47b34 --- /dev/null +++ b/bdshemu_test/basic/test_64_basic07.asm @@ -0,0 +1,4 @@ + + bits 64 + + int3 \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_basic07.result b/bdshemu_test/basic/test_64_basic07.result new file mode 100644 index 0000000..2c19d4d --- /dev/null +++ b/bdshemu_test/basic/test_64_basic07.result @@ -0,0 +1,7 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 INT3 +Emulation terminated with status 0x00000003, flags: 0x0, 0 NOPs diff --git a/bdshemu_test/basic/test_64_basic08 b/bdshemu_test/basic/test_64_basic08 new file mode 100644 index 0000000..65c9e7e --- /dev/null +++ b/bdshemu_test/basic/test_64_basic08 @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_basic08.asm b/bdshemu_test/basic/test_64_basic08.asm new file mode 100644 index 0000000..0d36923 --- /dev/null +++ b/bdshemu_test/basic/test_64_basic08.asm @@ -0,0 +1,6 @@ + + bits 64 + + nop + nop + db 0x0f, 0x0f, 0x0f, 0x0f \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_basic08.result b/bdshemu_test/basic/test_64_basic08.result new file mode 100644 index 0000000..b82b9e1 --- /dev/null +++ b/bdshemu_test/basic/test_64_basic08.result @@ -0,0 +1,13 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200001 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200001 NOP +Emulation terminated with status 0x00000004, flags: 0x0, 2 NOPs diff --git a/bdshemu_test/basic/test_64_basic09 b/bdshemu_test/basic/test_64_basic09 new file mode 100644 index 0000000..bcaa3a2 --- /dev/null +++ b/bdshemu_test/basic/test_64_basic09 @@ -0,0 +1 @@ +HH \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_basic09.asm b/bdshemu_test/basic/test_64_basic09.asm new file mode 100644 index 0000000..626a753 --- /dev/null +++ b/bdshemu_test/basic/test_64_basic09.asm @@ -0,0 +1,6 @@ + + bits 64 + + mov rax, 0xFFFFFFFFFFFFFFF0 + mov rax, qword [rax + 0x7FFFFFFF] + retn \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_basic09.result b/bdshemu_test/basic/test_64_basic09.result new file mode 100644 index 0000000..18ba9e1 --- /dev/null +++ b/bdshemu_test/basic/test_64_basic09.result @@ -0,0 +1,13 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 MOV rax, 0xfffffff0 + RAX = 0xfffffffffffffff0 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200007 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200007 MOV rax, qword ptr [rax+0x7fffffff] +Emulation terminated with status 0x00000001, flags: 0x0, 0 NOPs diff --git a/bdshemu_test/basic/test_64_branch1 b/bdshemu_test/basic/test_64_branch1 new file mode 100644 index 0000000000000000000000000000000000000000..4a88ed5a429d6e39e2b5468239bbbdc706639841 GIT binary patch literal 21 bcmdn-9|)QcFcxun^qMj=FfbfrJ98KSg0~6X literal 0 HcmV?d00001 diff --git a/bdshemu_test/basic/test_64_branch1.asm b/bdshemu_test/basic/test_64_branch1.asm new file mode 100644 index 0000000..818100a --- /dev/null +++ b/bdshemu_test/basic/test_64_branch1.asm @@ -0,0 +1,10 @@ + + bits 64 + + mov eax, 0xFFFFFFFF + add eax, 1 ; Will set CF + jc _skip + lea rsi, [rel _skip] + mov byte [rsi], 0xCC +_skip: + retn \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_branch1.result b/bdshemu_test/basic/test_64_branch1.result new file mode 100644 index 0000000..ec74268 --- /dev/null +++ b/bdshemu_test/basic/test_64_branch1.result @@ -0,0 +1,25 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 MOV eax, 0xffffffff + RAX = 0x00000000ffffffff RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200005 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200005 ADD eax, 0x01 + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200008 RFLAGS = 0x0000000000000247 +Emulating: 0x0000000000200008 JC 0x200014 + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200014 RFLAGS = 0x0000000000000247 +Emulating: 0x0000000000200014 RETN +Emulation terminated with status 0x00000002, flags: 0x0, 0 NOPs diff --git a/bdshemu_test/basic/test_64_branch2 b/bdshemu_test/basic/test_64_branch2 new file mode 100644 index 0000000000000000000000000000000000000000..7918322b24004ebc93c33ead0d47274b0da141ac GIT binary patch literal 21 bcmdn-9|)QcFcx!p^qMj=FfbfrJ98KSg2V~l literal 0 HcmV?d00001 diff --git a/bdshemu_test/basic/test_64_branch2.asm b/bdshemu_test/basic/test_64_branch2.asm new file mode 100644 index 0000000..0cf4c09 --- /dev/null +++ b/bdshemu_test/basic/test_64_branch2.asm @@ -0,0 +1,10 @@ + + bits 64 + + mov eax, 0xFFFFFFFF + add eax, 1 ; Will set CF + jnc _skip + lea rsi, [rel _skip] + mov byte [rsi], 0xCC +_skip: + retn \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_branch2.result b/bdshemu_test/basic/test_64_branch2.result new file mode 100644 index 0000000..a06d124 --- /dev/null +++ b/bdshemu_test/basic/test_64_branch2.result @@ -0,0 +1,38 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 MOV eax, 0xffffffff + RAX = 0x00000000ffffffff RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200005 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200005 ADD eax, 0x01 + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200008 RFLAGS = 0x0000000000000247 +Emulating: 0x0000000000200008 JNC 0x200014 + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000a RFLAGS = 0x0000000000000247 +Emulating: 0x000000000020000a LEA rsi, [rel 0x200014] + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000200014 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200011 RFLAGS = 0x0000000000000247 +Emulating: 0x0000000000200011 MOV byte ptr [rsi], 0xcc + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000200014 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200014 RFLAGS = 0x0000000000000247 +Emulating: 0x0000000000200014 INT3 +Emulation terminated with status 0x00000003, flags: 0x4, 0 NOPs + SHEMU_FLAG_WRITE_SELF diff --git a/bdshemu_test/basic/test_64_branch3 b/bdshemu_test/basic/test_64_branch3 new file mode 100644 index 0000000000000000000000000000000000000000..6f5f5bdb7e3c941d6565342af447853494ff88ff GIT binary patch literal 15 WcmXp!P{QTWYs$>Pz;KN1%wYf{-UQeH literal 0 HcmV?d00001 diff --git a/bdshemu_test/basic/test_64_branch3.asm b/bdshemu_test/basic/test_64_branch3.asm new file mode 100644 index 0000000..0b5ded3 --- /dev/null +++ b/bdshemu_test/basic/test_64_branch3.asm @@ -0,0 +1,9 @@ + + bits 64 + + xor eax, eax + jz _skip + lea rsi, [rel _skip] + mov byte [rsi], 0xCC +_skip: + retn \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_branch3.result b/bdshemu_test/basic/test_64_branch3.result new file mode 100644 index 0000000..cff8cc6 --- /dev/null +++ b/bdshemu_test/basic/test_64_branch3.result @@ -0,0 +1,19 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 XOR eax, eax + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200002 RFLAGS = 0x0000000000000246 +Emulating: 0x0000000000200002 JZ 0x20000e + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000e RFLAGS = 0x0000000000000246 +Emulating: 0x000000000020000e RETN +Emulation terminated with status 0x00000002, flags: 0x0, 0 NOPs diff --git a/bdshemu_test/basic/test_64_branch4 b/bdshemu_test/basic/test_64_branch4 new file mode 100644 index 0000000000000000000000000000000000000000..fc5af4d8f336fdf51c49e26ede3f6ade8cdd9405 GIT binary patch literal 15 WcmXp!P|D@eYs$>Pz;KN1%wYf{>jc>V literal 0 HcmV?d00001 diff --git a/bdshemu_test/basic/test_64_branch4.asm b/bdshemu_test/basic/test_64_branch4.asm new file mode 100644 index 0000000..b73c298 --- /dev/null +++ b/bdshemu_test/basic/test_64_branch4.asm @@ -0,0 +1,9 @@ + + bits 64 + + xor eax, eax + jnz _skip + lea rsi, [rel _skip] + mov byte [rsi], 0xCC +_skip: + retn \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_branch4.result b/bdshemu_test/basic/test_64_branch4.result new file mode 100644 index 0000000..fad5c15 --- /dev/null +++ b/bdshemu_test/basic/test_64_branch4.result @@ -0,0 +1,32 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 XOR eax, eax + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200002 RFLAGS = 0x0000000000000246 +Emulating: 0x0000000000200002 JNZ 0x20000e + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200004 RFLAGS = 0x0000000000000246 +Emulating: 0x0000000000200004 LEA rsi, [rel 0x20000e] + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x000000000020000e RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000b RFLAGS = 0x0000000000000246 +Emulating: 0x000000000020000b MOV byte ptr [rsi], 0xcc + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x000000000020000e RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000e RFLAGS = 0x0000000000000246 +Emulating: 0x000000000020000e INT3 +Emulation terminated with status 0x00000003, flags: 0x4, 0 NOPs + SHEMU_FLAG_WRITE_SELF diff --git a/bdshemu_test/basic/test_64_div b/bdshemu_test/basic/test_64_div new file mode 100644 index 0000000..4466ccf --- /dev/null +++ b/bdshemu_test/basic/test_64_div @@ -0,0 +1 @@ +Hf1f \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_div.asm b/bdshemu_test/basic/test_64_div.asm new file mode 100644 index 0000000..5110803 --- /dev/null +++ b/bdshemu_test/basic/test_64_div.asm @@ -0,0 +1,6 @@ + bits 64 + + mov rax, 0xBDBDBDBDBDBDBDBD + xor ax, ax + div ax + retn \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_div.result b/bdshemu_test/basic/test_64_div.result new file mode 100644 index 0000000..fd9901c --- /dev/null +++ b/bdshemu_test/basic/test_64_div.result @@ -0,0 +1,19 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 MOV rax, 0xbdbdbdbdbdbdbdbd + RAX = 0xbdbdbdbdbdbdbdbd RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000a XOR ax, ax + RAX = 0xbdbdbdbdbdbd0000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000d RFLAGS = 0x0000000000000246 +Emulating: 0x000000000020000d DIV ax +Emulation terminated with status 0x0000000a, flags: 0x0, 0 NOPs diff --git a/bdshemu_test/basic/test_64_eicar b/bdshemu_test/basic/test_64_eicar new file mode 100644 index 0000000000000000000000000000000000000000..f5714196369c0a3008c915fa21d95bd8cebb938a GIT binary patch literal 109 zcmX@i00j}I{)z#r4vqoQCNTj~5vC>@0dbn<&d!?VwJNTj&W=I4!6A-*E{;Jix{iJ! zo?)Irp~1Q#uE8O?Zk|4_iYgx39$GN7LNYRo6@VyF!6VF5p(M4qL?JCRCzSyJYw{Y7 literal 0 HcmV?d00001 diff --git a/bdshemu_test/basic/test_64_eicar.asm b/bdshemu_test/basic/test_64_eicar.asm new file mode 100644 index 0000000..7aa4c6f --- /dev/null +++ b/bdshemu_test/basic/test_64_eicar.asm @@ -0,0 +1,10 @@ + + bits 64 + + retn + +dq 0 +db "X5O!P%@AP[4\PZX54(P^)7CC)7}$EICAR-STANDARD-ANTIVIRUS-TEST-FILE!$H+H*" +dq 0 + +db "This is a HVI test file",0 \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_eicar.result b/bdshemu_test/basic/test_64_eicar.result new file mode 100644 index 0000000..7b07cc3 --- /dev/null +++ b/bdshemu_test/basic/test_64_eicar.result @@ -0,0 +1,7 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 RETN +Emulation terminated with status 0x00000002, flags: 0x0, 0 NOPs diff --git a/bdshemu_test/basic/test_64_flags b/bdshemu_test/basic/test_64_flags new file mode 100644 index 0000000000000000000000000000000000000000..3ba2da0ca9166d36ee854ecd8a164e8142b1c1bf GIT binary patch literal 92 zcmXp!u;V`vG#_9zgtMA2Fc=j9kgLgFw0 DX`DG# literal 0 HcmV?d00001 diff --git a/bdshemu_test/basic/test_64_flags.asm b/bdshemu_test/basic/test_64_flags.asm new file mode 100644 index 0000000..d20d022 --- /dev/null +++ b/bdshemu_test/basic/test_64_flags.asm @@ -0,0 +1,41 @@ + + bits 64 + + xor eax, eax + mov eax, 0xFFFFFFFF + add eax, 1 + + xor eax, eax + mov eax, 0xFFFFFFFF + add eax, 1 + adc eax, 0 + + xor eax, eax + sub eax, 1 + sbb eax, 0 + + xor eax, eax + mov eax, 0xBDBDBDBD + rol eax, 16 + + xor eax, eax + mov eax, 0xBDBDBDBD + ror eax, 24 + + xor eax, eax + mov eax, 0xBDBDBDBD + rcl eax, 24 + + xor eax, eax + mov eax, 0xBDBDBDBD + rcr eax, 24 + + xor eax, eax + mov eax, 0xBDBDBDBD + shl eax, 24 + + xor eax, eax + mov eax, 0xBDBDBDBD + shr eax, 24 + + retn \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_flags.result b/bdshemu_test/basic/test_64_flags.result new file mode 100644 index 0000000..c16ef81 --- /dev/null +++ b/bdshemu_test/basic/test_64_flags.result @@ -0,0 +1,175 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 XOR eax, eax + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200002 RFLAGS = 0x0000000000000246 +Emulating: 0x0000000000200002 MOV eax, 0xffffffff + RAX = 0x00000000ffffffff RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200007 RFLAGS = 0x0000000000000246 +Emulating: 0x0000000000200007 ADD eax, 0x01 + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000a RFLAGS = 0x0000000000000247 +Emulating: 0x000000000020000a XOR eax, eax + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000c RFLAGS = 0x0000000000000246 +Emulating: 0x000000000020000c MOV eax, 0xffffffff + RAX = 0x00000000ffffffff RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200011 RFLAGS = 0x0000000000000246 +Emulating: 0x0000000000200011 ADD eax, 0x01 + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200014 RFLAGS = 0x0000000000000247 +Emulating: 0x0000000000200014 ADC eax, 0x00 + RAX = 0x0000000000000001 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200017 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200017 XOR eax, eax + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200019 RFLAGS = 0x0000000000000246 +Emulating: 0x0000000000200019 SUB eax, 0x01 + RAX = 0x00000000ffffffff RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020001c RFLAGS = 0x0000000000000286 +Emulating: 0x000000000020001c SBB eax, 0x00 + RAX = 0x00000000ffffffff RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020001f RFLAGS = 0x0000000000000286 +Emulating: 0x000000000020001f XOR eax, eax + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200021 RFLAGS = 0x0000000000000246 +Emulating: 0x0000000000200021 MOV eax, 0xbdbdbdbd + RAX = 0x00000000bdbdbdbd RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200026 RFLAGS = 0x0000000000000246 +Emulating: 0x0000000000200026 ROL eax, 0x10 + RAX = 0x00000000bdbdbdbd RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200029 RFLAGS = 0x0000000000000247 +Emulating: 0x0000000000200029 XOR eax, eax + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020002b RFLAGS = 0x0000000000000246 +Emulating: 0x000000000020002b MOV eax, 0xbdbdbdbd + RAX = 0x00000000bdbdbdbd RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200030 RFLAGS = 0x0000000000000246 +Emulating: 0x0000000000200030 ROR eax, 0x18 + RAX = 0x00000000bdbdbdbd RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200033 RFLAGS = 0x0000000000000247 +Emulating: 0x0000000000200033 XOR eax, eax + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200035 RFLAGS = 0x0000000000000246 +Emulating: 0x0000000000200035 MOV eax, 0xbdbdbdbd + RAX = 0x00000000bdbdbdbd RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020003a RFLAGS = 0x0000000000000246 +Emulating: 0x000000000020003a RCL eax, 0x18 + RAX = 0x00000000bd5edede RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020003d RFLAGS = 0x0000000000000247 +Emulating: 0x000000000020003d XOR eax, eax + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020003f RFLAGS = 0x0000000000000246 +Emulating: 0x000000000020003f MOV eax, 0xbdbdbdbd + RAX = 0x00000000bdbdbdbd RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200044 RFLAGS = 0x0000000000000246 +Emulating: 0x0000000000200044 RCR eax, 0x18 + RAX = 0x000000007b7b7abd RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200047 RFLAGS = 0x0000000000000247 +Emulating: 0x0000000000200047 XOR eax, eax + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200049 RFLAGS = 0x0000000000000246 +Emulating: 0x0000000000200049 MOV eax, 0xbdbdbdbd + RAX = 0x00000000bdbdbdbd RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020004e RFLAGS = 0x0000000000000246 +Emulating: 0x000000000020004e SHL eax, 0x18 + RAX = 0x00000000bd000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200051 RFLAGS = 0x0000000000000286 +Emulating: 0x0000000000200051 XOR eax, eax + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200053 RFLAGS = 0x0000000000000246 +Emulating: 0x0000000000200053 MOV eax, 0xbdbdbdbd + RAX = 0x00000000bdbdbdbd RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200058 RFLAGS = 0x0000000000000246 +Emulating: 0x0000000000200058 SHR eax, 0x18 + RAX = 0x00000000000000bd RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020005b RFLAGS = 0x0000000000000206 +Emulating: 0x000000000020005b RETN +Emulation terminated with status 0x00000002, flags: 0x0, 0 NOPs diff --git a/bdshemu_test/basic/test_64_loadrip01 b/bdshemu_test/basic/test_64_loadrip01 new file mode 100644 index 0000000000000000000000000000000000000000..a35c72c9ed6d95747c2fb4fb435b920ab8adca9f GIT binary patch literal 7 McmaFC00gmz0SDXy2><{9 literal 0 HcmV?d00001 diff --git a/bdshemu_test/basic/test_64_loadrip01.asm b/bdshemu_test/basic/test_64_loadrip01.asm new file mode 100644 index 0000000..3f8c7c6 --- /dev/null +++ b/bdshemu_test/basic/test_64_loadrip01.asm @@ -0,0 +1,7 @@ + + bits 64 + + call _xxx +_xxx: + pop rbp + retn \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_loadrip01.result b/bdshemu_test/basic/test_64_loadrip01.result new file mode 100644 index 0000000..54c2d82 --- /dev/null +++ b/bdshemu_test/basic/test_64_loadrip01.result @@ -0,0 +1,20 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 CALL 0x200005 + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000100ff8 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200005 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200005 POP rbp + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000200005 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200006 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200006 RETN +Emulation terminated with status 0x00000002, flags: 0x2, 0 NOPs + SHEMU_FLAG_LOAD_RIP diff --git a/bdshemu_test/basic/test_64_loadrip02 b/bdshemu_test/basic/test_64_loadrip02 new file mode 100644 index 0000000..7df5071 --- /dev/null +++ b/bdshemu_test/basic/test_64_loadrip02 @@ -0,0 +1 @@ +$HH$ \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_loadrip02.asm b/bdshemu_test/basic/test_64_loadrip02.asm new file mode 100644 index 0000000..b91f4cb --- /dev/null +++ b/bdshemu_test/basic/test_64_loadrip02.asm @@ -0,0 +1,8 @@ + + bits 64 + + FFREE st3 + FXSAVE [rsp+0x0] + ADD rsp, 0x0000000000000008 + MOV rax, qword [rsp+0x0] + int3 \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_loadrip02.result b/bdshemu_test/basic/test_64_loadrip02.result new file mode 100644 index 0000000..a186a08 --- /dev/null +++ b/bdshemu_test/basic/test_64_loadrip02.result @@ -0,0 +1,32 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 FFREE st3 + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200002 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200002 FXSAVE [rsp] + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200006 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200006 ADD rsp, 0x08 + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101008 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000a MOV rax, qword ptr [rsp] + RAX = 0x0000000000200000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101008 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000e INT3 +Emulation terminated with status 0x00000003, flags: 0x2, 0 NOPs + SHEMU_FLAG_LOAD_RIP diff --git a/bdshemu_test/basic/test_64_loadrip03 b/bdshemu_test/basic/test_64_loadrip03 new file mode 100644 index 0000000000000000000000000000000000000000..967b50d78301dabe5a6dc0a9e1351b8308c3b093 GIT binary patch literal 12 ScmaFC00f3_J(zV=&Hw-u-2-j_ literal 0 HcmV?d00001 diff --git a/bdshemu_test/basic/test_64_loadrip03.asm b/bdshemu_test/basic/test_64_loadrip03.asm new file mode 100644 index 0000000..b9ebb0a --- /dev/null +++ b/bdshemu_test/basic/test_64_loadrip03.asm @@ -0,0 +1,8 @@ + + bits 64 + + call _test +_test: + xor ebp, ebp + add rbp, qword [rsp] + int3 \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_loadrip03.result b/bdshemu_test/basic/test_64_loadrip03.result new file mode 100644 index 0000000..0470ed1 --- /dev/null +++ b/bdshemu_test/basic/test_64_loadrip03.result @@ -0,0 +1,26 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 CALL 0x200005 + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000100ff8 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200005 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200005 XOR ebp, ebp + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000100ff8 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200007 RFLAGS = 0x0000000000000246 +Emulating: 0x0000000000200007 ADD rbp, qword ptr [rsp] + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000100ff8 RBP = 0x0000000000200005 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000b RFLAGS = 0x0000000000000206 +Emulating: 0x000000000020000b INT3 +Emulation terminated with status 0x00000003, flags: 0x2, 0 NOPs + SHEMU_FLAG_LOAD_RIP diff --git a/bdshemu_test/basic/test_64_moffset b/bdshemu_test/basic/test_64_moffset new file mode 100644 index 0000000..ccf25b3 --- /dev/null +++ b/bdshemu_test/basic/test_64_moffset @@ -0,0 +1 @@ +H \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_moffset.asm b/bdshemu_test/basic/test_64_moffset.asm new file mode 100644 index 0000000..5a992c3 --- /dev/null +++ b/bdshemu_test/basic/test_64_moffset.asm @@ -0,0 +1,5 @@ + + bits 64 + + mov rax, qword [qword 0xBDBDBDBDBDBDBDBD] + ret \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_moffset.result b/bdshemu_test/basic/test_64_moffset.result new file mode 100644 index 0000000..96812b6 --- /dev/null +++ b/bdshemu_test/basic/test_64_moffset.result @@ -0,0 +1,7 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 MOV rax, qword ptr [0xbdbdbdbdbdbdbdbd] +Emulation terminated with status 0x00000001, flags: 0x0, 0 NOPs diff --git a/bdshemu_test/basic/test_64_mov b/bdshemu_test/basic/test_64_mov new file mode 100644 index 0000000..d31f136 --- /dev/null +++ b/bdshemu_test/basic/test_64_mov @@ -0,0 +1 @@ +HfHfظxV4ͫ H$H$ \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_mov.asm b/bdshemu_test/basic/test_64_mov.asm new file mode 100644 index 0000000..3ab083a --- /dev/null +++ b/bdshemu_test/basic/test_64_mov.asm @@ -0,0 +1,22 @@ + + bits 64 + + mov ah, 0xBD + mov al, 0x12 + mov rcx, 0xFFFFFFFFFFFFFFFF + mov cx, ax + mov ecx, eax + mov rbx, rax + + mov ax, 0xFFFF + movzx ecx, ax + movsx ebx, ax + + mov eax, 0x12345678 + mov ebx, 0x09ABCDEF + xchg eax, ebx + + mov qword [rsp], -1 + xchg rax, qword [rsp] + + retn \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_mov.result b/bdshemu_test/basic/test_64_mov.result new file mode 100644 index 0000000..45b3489 --- /dev/null +++ b/bdshemu_test/basic/test_64_mov.result @@ -0,0 +1,91 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 MOV ah, 0xbd + RAX = 0x000000000000bd00 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200002 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200002 MOV al, 0x12 + RAX = 0x000000000000bd12 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200004 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200004 MOV rcx, 0xffffffff + RAX = 0x000000000000bd12 RCX = 0xffffffffffffffff RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000b MOV cx, ax + RAX = 0x000000000000bd12 RCX = 0xffffffffffffbd12 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000e MOV ecx, eax + RAX = 0x000000000000bd12 RCX = 0x000000000000bd12 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200010 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200010 MOV rbx, rax + RAX = 0x000000000000bd12 RCX = 0x000000000000bd12 RDX = 0x0000000000000000 RBX = 0x000000000000bd12 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200013 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200013 MOV ax, 0xffff + RAX = 0x000000000000ffff RCX = 0x000000000000bd12 RDX = 0x0000000000000000 RBX = 0x000000000000bd12 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200017 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200017 MOVZX ecx, ax + RAX = 0x000000000000ffff RCX = 0x000000000000ffff RDX = 0x0000000000000000 RBX = 0x000000000000bd12 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020001a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020001a MOVSX ebx, ax + RAX = 0x000000000000ffff RCX = 0x000000000000ffff RDX = 0x0000000000000000 RBX = 0x00000000ffffffff + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020001d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020001d MOV eax, 0x12345678 + RAX = 0x0000000012345678 RCX = 0x000000000000ffff RDX = 0x0000000000000000 RBX = 0x00000000ffffffff + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200022 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200022 MOV ebx, 0x09abcdef + RAX = 0x0000000012345678 RCX = 0x000000000000ffff RDX = 0x0000000000000000 RBX = 0x0000000009abcdef + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200027 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200027 XCHG eax, ebx + RAX = 0x0000000009abcdef RCX = 0x000000000000ffff RDX = 0x0000000000000000 RBX = 0x0000000012345678 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200028 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200028 MOV qword ptr [rsp], 0xffffffff + RAX = 0x0000000009abcdef RCX = 0x000000000000ffff RDX = 0x0000000000000000 RBX = 0x0000000012345678 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200030 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200030 XCHG qword ptr [rsp], rax + RAX = 0xffffffffffffffff RCX = 0x000000000000ffff RDX = 0x0000000000000000 RBX = 0x0000000012345678 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200034 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200034 RETN +Emulation terminated with status 0x00000002, flags: 0x0, 0 NOPs diff --git a/bdshemu_test/basic/test_64_nopsled01 b/bdshemu_test/basic/test_64_nopsled01 new file mode 100644 index 0000000..237ddeb --- /dev/null +++ b/bdshemu_test/basic/test_64_nopsled01 @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_nopsled01.asm b/bdshemu_test/basic/test_64_nopsled01.asm new file mode 100644 index 0000000..1cecf22 --- /dev/null +++ b/bdshemu_test/basic/test_64_nopsled01.asm @@ -0,0 +1,20 @@ + + bits 64 + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + retn \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_nopsled01.result b/bdshemu_test/basic/test_64_nopsled01.result new file mode 100644 index 0000000..1640d1e --- /dev/null +++ b/bdshemu_test/basic/test_64_nopsled01.result @@ -0,0 +1,103 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200001 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200001 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200002 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200002 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200003 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200003 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200004 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200004 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200005 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200005 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200006 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200006 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200007 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200007 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200008 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200008 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200009 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200009 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200010 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200010 RETN +Emulation terminated with status 0x00000002, flags: 0x0, 16 NOPs diff --git a/bdshemu_test/basic/test_64_nopsled02 b/bdshemu_test/basic/test_64_nopsled02 new file mode 100644 index 0000000..f7b91e4 --- /dev/null +++ b/bdshemu_test/basic/test_64_nopsled02 @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_nopsled02.asm b/bdshemu_test/basic/test_64_nopsled02.asm new file mode 100644 index 0000000..766f18c --- /dev/null +++ b/bdshemu_test/basic/test_64_nopsled02.asm @@ -0,0 +1,36 @@ + + bits 64 + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + retn \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_nopsled02.result b/bdshemu_test/basic/test_64_nopsled02.result new file mode 100644 index 0000000..a440ada --- /dev/null +++ b/bdshemu_test/basic/test_64_nopsled02.result @@ -0,0 +1,199 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200001 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200001 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200002 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200002 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200003 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200003 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200004 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200004 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200005 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200005 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200006 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200006 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200007 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200007 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200008 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200008 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200009 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200009 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200010 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200010 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200011 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200011 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200012 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200012 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200013 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200013 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200014 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200014 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200015 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200015 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200016 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200016 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200017 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200017 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200018 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200018 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200019 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200019 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020001a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020001a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020001b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020001b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020001c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020001c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020001d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020001d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020001e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020001e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020001f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020001f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200020 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200020 RETN +Emulation terminated with status 0x00000002, flags: 0x0, 32 NOPs diff --git a/bdshemu_test/basic/test_64_nopsled03 b/bdshemu_test/basic/test_64_nopsled03 new file mode 100644 index 0000000..e31d12c --- /dev/null +++ b/bdshemu_test/basic/test_64_nopsled03 @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_nopsled03.asm b/bdshemu_test/basic/test_64_nopsled03.asm new file mode 100644 index 0000000..74a3e57 --- /dev/null +++ b/bdshemu_test/basic/test_64_nopsled03.asm @@ -0,0 +1,4 @@ + + bits 64 + + times 4096 db 0x90 \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_nopsled03.result b/bdshemu_test/basic/test_64_nopsled03.result new file mode 100644 index 0000000..68daa0e --- /dev/null +++ b/bdshemu_test/basic/test_64_nopsled03.result @@ -0,0 +1,24578 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200001 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200001 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200002 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200002 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200003 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200003 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200004 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200004 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200005 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200005 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200006 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200006 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200007 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200007 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200008 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200008 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200009 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200009 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200010 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200010 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200011 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200011 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200012 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200012 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200013 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200013 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200014 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200014 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200015 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200015 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200016 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200016 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200017 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200017 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200018 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200018 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200019 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200019 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020001a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020001a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020001b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020001b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020001c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020001c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020001d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020001d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020001e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020001e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020001f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020001f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200020 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200020 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200021 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200021 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200022 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200022 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200023 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200023 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200024 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200024 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200025 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200025 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200026 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200026 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200027 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200027 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200028 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200028 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200029 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200029 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020002a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020002a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020002b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020002b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020002c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020002c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020002d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020002d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020002e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020002e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020002f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020002f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200030 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200030 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200031 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200031 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200032 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200032 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200033 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200033 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200034 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200034 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200035 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200035 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200036 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200036 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200037 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200037 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200038 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200038 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200039 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200039 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020003a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020003a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020003b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020003b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020003c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020003c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020003d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020003d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020003e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020003e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020003f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020003f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200040 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200040 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200041 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200041 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200042 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200042 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200043 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200043 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200044 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200044 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200045 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200045 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200046 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200046 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200047 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200047 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200048 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200048 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200049 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200049 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020004a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020004a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020004b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020004b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020004c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020004c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020004d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020004d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020004e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020004e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020004f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020004f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200050 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200050 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200051 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200051 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200052 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200052 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200053 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200053 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200054 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200054 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200055 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200055 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200056 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200056 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200057 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200057 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200058 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200058 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200059 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200059 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020005a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020005a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020005b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020005b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020005c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020005c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020005d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020005d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020005e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020005e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020005f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020005f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200060 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200060 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200061 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200061 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200062 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200062 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200063 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200063 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200064 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200064 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200065 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200065 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200066 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200066 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200067 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200067 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200068 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200068 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200069 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200069 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020006a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020006a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020006b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020006b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020006c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020006c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020006d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020006d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020006e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020006e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020006f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020006f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200070 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200070 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200071 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200071 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200072 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200072 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200073 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200073 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200074 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200074 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200075 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200075 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200076 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200076 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200077 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200077 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200078 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200078 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200079 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200079 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020007a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020007a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020007b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020007b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020007c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020007c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020007d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020007d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020007e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020007e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020007f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020007f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200080 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200080 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200081 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200081 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200082 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200082 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200083 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200083 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200084 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200084 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200085 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200085 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200086 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200086 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200087 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200087 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200088 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200088 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200089 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200089 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020008a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020008a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020008b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020008b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020008c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020008c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020008d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020008d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020008e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020008e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020008f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020008f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200090 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200090 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200091 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200091 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200092 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200092 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200093 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200093 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200094 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200094 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200095 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200095 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200096 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200096 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200097 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200097 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200098 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200098 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200099 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200099 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020009a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020009a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020009b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020009b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020009c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020009c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020009d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020009d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020009e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020009e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020009f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020009f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000a0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000a0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000a1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000a1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000a2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000a2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000a3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000a3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000a4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000a4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000a5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000a5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000a6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000a6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000a7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000a7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000a8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000a8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000a9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000a9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000aa RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000aa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000ab RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000ab NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000ac RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000ac NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000ad RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000ad NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000ae RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000ae NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000af RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000af NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000b0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000b0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000b1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000b1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000b2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000b2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000b3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000b3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000b4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000b4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000b5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000b5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000b6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000b6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000b7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000b7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000b8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000b8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000b9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000b9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000ba RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000ba NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000bb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000bb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000bc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000bc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000bd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000bd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000be RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000be NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000bf RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000bf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000c0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000c0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000c1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000c1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000c2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000c2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000c3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000c3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000c4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000c4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000c5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000c5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000c6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000c6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000c7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000c7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000c8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000c8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000c9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000c9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000ca RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000ca NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000cb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000cb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000cc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000cc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000cd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000cd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000ce RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000ce NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000cf RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000cf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000d0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000d0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000d1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000d1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000d2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000d2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000d3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000d3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000d4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000d4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000d5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000d5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000d6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000d6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000d7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000d7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000d8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000d8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000d9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000d9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000da RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000da NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000db RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000db NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000dc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000dc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000dd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000dd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000de RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000de NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000df RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000df NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000e0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000e0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000e1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000e1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000e2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000e2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000e3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000e3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000e4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000e4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000e5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000e5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000e6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000e6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000e7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000e7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000e8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000e8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000e9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000e9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000ea RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000ea NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000eb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000eb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000ec RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000ec NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000ed RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000ed NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000ee RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000ee NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000ef RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000ef NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000f0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000f0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000f1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000f1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000f2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000f2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000f3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000f3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000f4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000f4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000f5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000f5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000f6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000f6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000f7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000f7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000f8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000f8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000f9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000f9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000fa RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000fa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000fb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000fb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000fc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000fc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000fd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000fd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000fe RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000fe NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002000ff RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002000ff NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200100 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200100 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200101 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200101 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200102 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200102 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200103 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200103 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200104 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200104 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200105 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200105 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200106 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200106 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200107 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200107 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200108 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200108 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200109 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200109 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020010a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020010a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020010b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020010b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020010c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020010c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020010d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020010d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020010e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020010e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020010f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020010f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200110 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200110 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200111 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200111 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200112 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200112 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200113 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200113 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200114 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200114 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200115 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200115 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200116 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200116 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200117 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200117 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200118 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200118 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200119 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200119 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020011a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020011a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020011b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020011b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020011c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020011c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020011d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020011d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020011e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020011e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020011f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020011f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200120 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200120 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200121 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200121 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200122 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200122 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200123 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200123 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200124 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200124 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200125 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200125 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200126 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200126 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200127 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200127 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200128 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200128 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200129 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200129 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020012a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020012a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020012b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020012b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020012c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020012c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020012d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020012d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020012e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020012e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020012f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020012f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200130 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200130 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200131 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200131 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200132 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200132 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200133 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200133 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200134 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200134 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200135 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200135 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200136 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200136 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200137 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200137 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200138 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200138 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200139 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200139 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020013a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020013a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020013b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020013b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020013c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020013c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020013d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020013d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020013e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020013e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020013f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020013f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200140 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200140 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200141 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200141 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200142 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200142 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200143 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200143 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200144 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200144 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200145 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200145 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200146 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200146 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200147 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200147 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200148 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200148 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200149 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200149 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020014a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020014a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020014b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020014b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020014c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020014c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020014d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020014d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020014e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020014e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020014f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020014f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200150 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200150 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200151 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200151 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200152 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200152 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200153 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200153 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200154 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200154 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200155 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200155 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200156 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200156 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200157 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200157 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200158 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200158 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200159 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200159 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020015a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020015a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020015b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020015b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020015c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020015c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020015d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020015d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020015e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020015e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020015f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020015f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200160 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200160 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200161 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200161 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200162 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200162 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200163 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200163 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200164 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200164 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200165 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200165 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200166 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200166 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200167 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200167 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200168 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200168 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200169 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200169 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020016a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020016a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020016b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020016b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020016c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020016c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020016d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020016d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020016e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020016e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020016f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020016f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200170 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200170 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200171 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200171 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200172 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200172 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200173 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200173 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200174 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200174 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200175 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200175 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200176 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200176 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200177 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200177 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200178 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200178 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200179 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200179 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020017a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020017a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020017b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020017b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020017c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020017c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020017d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020017d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020017e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020017e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020017f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020017f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200180 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200180 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200181 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200181 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200182 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200182 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200183 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200183 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200184 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200184 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200185 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200185 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200186 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200186 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200187 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200187 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200188 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200188 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200189 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200189 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020018a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020018a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020018b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020018b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020018c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020018c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020018d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020018d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020018e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020018e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020018f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020018f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200190 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200190 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200191 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200191 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200192 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200192 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200193 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200193 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200194 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200194 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200195 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200195 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200196 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200196 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200197 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200197 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200198 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200198 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200199 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200199 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020019a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020019a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020019b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020019b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020019c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020019c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020019d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020019d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020019e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020019e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020019f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020019f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001a0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001a0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001a1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001a1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001a2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001a2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001a3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001a3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001a4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001a4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001a5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001a5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001a6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001a6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001a7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001a7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001a8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001a8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001a9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001a9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001aa RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001aa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001ab RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001ab NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001ac RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001ac NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001ad RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001ad NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001ae RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001ae NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001af RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001af NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001b0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001b0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001b1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001b1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001b2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001b2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001b3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001b3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001b4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001b4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001b5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001b5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001b6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001b6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001b7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001b7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001b8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001b8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001b9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001b9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001ba RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001ba NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001bb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001bb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001bc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001bc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001bd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001bd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001be RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001be NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001bf RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001bf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001c0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001c0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001c1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001c1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001c2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001c2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001c3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001c3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001c4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001c4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001c5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001c5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001c6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001c6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001c7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001c7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001c8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001c8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001c9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001c9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001ca RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001ca NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001cb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001cb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001cc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001cc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001cd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001cd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001ce RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001ce NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001cf RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001cf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001d0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001d0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001d1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001d1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001d2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001d2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001d3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001d3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001d4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001d4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001d5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001d5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001d6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001d6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001d7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001d7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001d8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001d8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001d9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001d9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001da RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001da NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001db RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001db NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001dc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001dc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001dd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001dd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001de RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001de NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001df RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001df NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001e0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001e0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001e1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001e1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001e2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001e2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001e3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001e3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001e4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001e4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001e5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001e5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001e6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001e6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001e7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001e7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001e8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001e8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001e9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001e9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001ea RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001ea NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001eb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001eb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001ec RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001ec NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001ed RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001ed NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001ee RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001ee NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001ef RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001ef NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001f0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001f0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001f1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001f1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001f2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001f2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001f3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001f3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001f4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001f4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001f5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001f5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001f6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001f6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001f7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001f7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001f8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001f8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001f9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001f9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001fa RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001fa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001fb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001fb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001fc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001fc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001fd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001fd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001fe RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001fe NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002001ff RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002001ff NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200200 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200200 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200201 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200201 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200202 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200202 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200203 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200203 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200204 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200204 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200205 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200205 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200206 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200206 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200207 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200207 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200208 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200208 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200209 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200209 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020020a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020020a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020020b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020020b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020020c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020020c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020020d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020020d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020020e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020020e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020020f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020020f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200210 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200210 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200211 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200211 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200212 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200212 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200213 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200213 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200214 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200214 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200215 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200215 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200216 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200216 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200217 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200217 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200218 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200218 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200219 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200219 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020021a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020021a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020021b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020021b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020021c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020021c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020021d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020021d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020021e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020021e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020021f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020021f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200220 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200220 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200221 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200221 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200222 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200222 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200223 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200223 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200224 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200224 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200225 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200225 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200226 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200226 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200227 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200227 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200228 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200228 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200229 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200229 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020022a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020022a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020022b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020022b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020022c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020022c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020022d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020022d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020022e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020022e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020022f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020022f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200230 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200230 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200231 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200231 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200232 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200232 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200233 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200233 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200234 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200234 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200235 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200235 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200236 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200236 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200237 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200237 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200238 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200238 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200239 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200239 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020023a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020023a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020023b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020023b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020023c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020023c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020023d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020023d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020023e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020023e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020023f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020023f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200240 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200240 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200241 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200241 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200242 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200242 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200243 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200243 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200244 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200244 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200245 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200245 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200246 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200246 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200247 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200247 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200248 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200248 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200249 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200249 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020024a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020024a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020024b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020024b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020024c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020024c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020024d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020024d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020024e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020024e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020024f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020024f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200250 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200250 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200251 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200251 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200252 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200252 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200253 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200253 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200254 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200254 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200255 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200255 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200256 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200256 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200257 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200257 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200258 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200258 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200259 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200259 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020025a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020025a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020025b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020025b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020025c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020025c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020025d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020025d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020025e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020025e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020025f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020025f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200260 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200260 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200261 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200261 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200262 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200262 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200263 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200263 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200264 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200264 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200265 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200265 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200266 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200266 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200267 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200267 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200268 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200268 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200269 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200269 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020026a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020026a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020026b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020026b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020026c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020026c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020026d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020026d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020026e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020026e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020026f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020026f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200270 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200270 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200271 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200271 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200272 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200272 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200273 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200273 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200274 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200274 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200275 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200275 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200276 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200276 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200277 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200277 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200278 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200278 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200279 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200279 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020027a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020027a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020027b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020027b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020027c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020027c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020027d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020027d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020027e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020027e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020027f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020027f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200280 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200280 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200281 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200281 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200282 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200282 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200283 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200283 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200284 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200284 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200285 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200285 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200286 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200286 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200287 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200287 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200288 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200288 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200289 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200289 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020028a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020028a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020028b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020028b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020028c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020028c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020028d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020028d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020028e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020028e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020028f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020028f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200290 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200290 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200291 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200291 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200292 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200292 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200293 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200293 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200294 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200294 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200295 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200295 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200296 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200296 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200297 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200297 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200298 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200298 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200299 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200299 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020029a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020029a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020029b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020029b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020029c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020029c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020029d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020029d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020029e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020029e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020029f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020029f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002a0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002a0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002a1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002a1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002a2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002a2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002a3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002a3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002a4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002a4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002a5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002a5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002a6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002a6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002a7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002a7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002a8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002a8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002a9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002a9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002aa RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002aa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002ab RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002ab NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002ac RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002ac NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002ad RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002ad NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002ae RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002ae NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002af RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002af NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002b0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002b0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002b1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002b1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002b2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002b2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002b3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002b3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002b4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002b4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002b5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002b5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002b6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002b6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002b7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002b7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002b8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002b8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002b9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002b9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002ba RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002ba NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002bb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002bb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002bc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002bc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002bd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002bd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002be RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002be NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002bf RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002bf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002c0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002c0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002c1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002c1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002c2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002c2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002c3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002c3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002c4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002c4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002c5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002c5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002c6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002c6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002c7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002c7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002c8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002c8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002c9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002c9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002ca RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002ca NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002cb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002cb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002cc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002cc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002cd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002cd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002ce RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002ce NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002cf RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002cf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002d0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002d0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002d1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002d1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002d2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002d2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002d3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002d3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002d4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002d4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002d5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002d5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002d6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002d6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002d7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002d7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002d8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002d8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002d9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002d9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002da RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002da NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002db RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002db NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002dc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002dc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002dd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002dd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002de RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002de NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002df RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002df NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002e0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002e0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002e1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002e1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002e2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002e2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002e3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002e3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002e4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002e4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002e5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002e5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002e6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002e6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002e7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002e7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002e8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002e8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002e9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002e9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002ea RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002ea NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002eb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002eb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002ec RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002ec NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002ed RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002ed NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002ee RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002ee NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002ef RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002ef NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002f0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002f0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002f1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002f1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002f2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002f2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002f3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002f3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002f4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002f4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002f5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002f5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002f6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002f6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002f7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002f7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002f8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002f8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002f9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002f9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002fa RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002fa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002fb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002fb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002fc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002fc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002fd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002fd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002fe RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002fe NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002002ff RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002002ff NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200300 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200300 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200301 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200301 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200302 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200302 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200303 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200303 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200304 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200304 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200305 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200305 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200306 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200306 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200307 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200307 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200308 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200308 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200309 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200309 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020030a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020030a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020030b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020030b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020030c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020030c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020030d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020030d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020030e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020030e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020030f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020030f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200310 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200310 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200311 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200311 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200312 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200312 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200313 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200313 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200314 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200314 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200315 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200315 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200316 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200316 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200317 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200317 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200318 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200318 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200319 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200319 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020031a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020031a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020031b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020031b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020031c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020031c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020031d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020031d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020031e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020031e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020031f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020031f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200320 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200320 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200321 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200321 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200322 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200322 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200323 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200323 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200324 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200324 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200325 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200325 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200326 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200326 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200327 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200327 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200328 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200328 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200329 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200329 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020032a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020032a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020032b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020032b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020032c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020032c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020032d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020032d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020032e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020032e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020032f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020032f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200330 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200330 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200331 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200331 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200332 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200332 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200333 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200333 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200334 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200334 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200335 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200335 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200336 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200336 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200337 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200337 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200338 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200338 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200339 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200339 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020033a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020033a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020033b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020033b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020033c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020033c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020033d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020033d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020033e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020033e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020033f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020033f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200340 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200340 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200341 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200341 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200342 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200342 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200343 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200343 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200344 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200344 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200345 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200345 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200346 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200346 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200347 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200347 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200348 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200348 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200349 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200349 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020034a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020034a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020034b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020034b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020034c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020034c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020034d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020034d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020034e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020034e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020034f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020034f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200350 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200350 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200351 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200351 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200352 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200352 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200353 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200353 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200354 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200354 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200355 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200355 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200356 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200356 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200357 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200357 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200358 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200358 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200359 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200359 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020035a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020035a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020035b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020035b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020035c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020035c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020035d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020035d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020035e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020035e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020035f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020035f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200360 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200360 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200361 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200361 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200362 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200362 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200363 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200363 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200364 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200364 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200365 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200365 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200366 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200366 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200367 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200367 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200368 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200368 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200369 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200369 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020036a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020036a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020036b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020036b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020036c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020036c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020036d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020036d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020036e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020036e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020036f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020036f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200370 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200370 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200371 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200371 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200372 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200372 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200373 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200373 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200374 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200374 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200375 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200375 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200376 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200376 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200377 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200377 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200378 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200378 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200379 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200379 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020037a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020037a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020037b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020037b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020037c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020037c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020037d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020037d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020037e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020037e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020037f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020037f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200380 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200380 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200381 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200381 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200382 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200382 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200383 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200383 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200384 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200384 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200385 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200385 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200386 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200386 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200387 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200387 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200388 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200388 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200389 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200389 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020038a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020038a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020038b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020038b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020038c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020038c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020038d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020038d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020038e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020038e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020038f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020038f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200390 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200390 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200391 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200391 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200392 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200392 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200393 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200393 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200394 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200394 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200395 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200395 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200396 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200396 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200397 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200397 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200398 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200398 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200399 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200399 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020039a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020039a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020039b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020039b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020039c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020039c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020039d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020039d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020039e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020039e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020039f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020039f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003a0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003a0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003a1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003a1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003a2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003a2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003a3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003a3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003a4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003a4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003a5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003a5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003a6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003a6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003a7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003a7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003a8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003a8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003a9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003a9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003aa RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003aa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003ab RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003ab NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003ac RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003ac NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003ad RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003ad NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003ae RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003ae NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003af RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003af NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003b0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003b0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003b1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003b1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003b2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003b2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003b3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003b3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003b4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003b4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003b5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003b5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003b6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003b6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003b7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003b7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003b8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003b8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003b9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003b9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003ba RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003ba NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003bb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003bb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003bc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003bc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003bd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003bd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003be RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003be NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003bf RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003bf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003c0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003c0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003c1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003c1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003c2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003c2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003c3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003c3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003c4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003c4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003c5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003c5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003c6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003c6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003c7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003c7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003c8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003c8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003c9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003c9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003ca RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003ca NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003cb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003cb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003cc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003cc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003cd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003cd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003ce RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003ce NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003cf RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003cf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003d0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003d0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003d1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003d1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003d2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003d2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003d3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003d3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003d4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003d4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003d5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003d5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003d6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003d6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003d7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003d7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003d8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003d8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003d9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003d9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003da RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003da NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003db RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003db NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003dc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003dc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003dd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003dd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003de RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003de NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003df RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003df NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003e0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003e0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003e1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003e1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003e2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003e2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003e3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003e3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003e4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003e4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003e5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003e5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003e6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003e6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003e7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003e7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003e8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003e8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003e9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003e9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003ea RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003ea NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003eb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003eb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003ec RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003ec NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003ed RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003ed NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003ee RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003ee NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003ef RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003ef NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003f0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003f0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003f1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003f1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003f2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003f2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003f3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003f3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003f4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003f4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003f5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003f5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003f6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003f6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003f7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003f7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003f8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003f8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003f9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003f9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003fa RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003fa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003fb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003fb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003fc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003fc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003fd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003fd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003fe RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003fe NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002003ff RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002003ff NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200400 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200400 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200401 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200401 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200402 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200402 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200403 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200403 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200404 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200404 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200405 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200405 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200406 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200406 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200407 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200407 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200408 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200408 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200409 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200409 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020040a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020040a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020040b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020040b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020040c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020040c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020040d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020040d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020040e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020040e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020040f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020040f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200410 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200410 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200411 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200411 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200412 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200412 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200413 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200413 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200414 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200414 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200415 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200415 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200416 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200416 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200417 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200417 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200418 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200418 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200419 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200419 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020041a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020041a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020041b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020041b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020041c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020041c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020041d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020041d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020041e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020041e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020041f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020041f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200420 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200420 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200421 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200421 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200422 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200422 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200423 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200423 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200424 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200424 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200425 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200425 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200426 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200426 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200427 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200427 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200428 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200428 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200429 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200429 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020042a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020042a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020042b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020042b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020042c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020042c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020042d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020042d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020042e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020042e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020042f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020042f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200430 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200430 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200431 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200431 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200432 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200432 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200433 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200433 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200434 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200434 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200435 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200435 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200436 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200436 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200437 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200437 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200438 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200438 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200439 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200439 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020043a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020043a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020043b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020043b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020043c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020043c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020043d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020043d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020043e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020043e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020043f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020043f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200440 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200440 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200441 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200441 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200442 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200442 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200443 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200443 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200444 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200444 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200445 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200445 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200446 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200446 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200447 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200447 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200448 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200448 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200449 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200449 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020044a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020044a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020044b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020044b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020044c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020044c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020044d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020044d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020044e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020044e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020044f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020044f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200450 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200450 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200451 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200451 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200452 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200452 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200453 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200453 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200454 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200454 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200455 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200455 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200456 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200456 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200457 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200457 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200458 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200458 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200459 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200459 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020045a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020045a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020045b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020045b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020045c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020045c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020045d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020045d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020045e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020045e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020045f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020045f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200460 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200460 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200461 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200461 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200462 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200462 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200463 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200463 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200464 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200464 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200465 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200465 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200466 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200466 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200467 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200467 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200468 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200468 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200469 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200469 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020046a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020046a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020046b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020046b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020046c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020046c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020046d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020046d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020046e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020046e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020046f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020046f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200470 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200470 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200471 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200471 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200472 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200472 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200473 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200473 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200474 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200474 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200475 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200475 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200476 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200476 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200477 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200477 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200478 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200478 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200479 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200479 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020047a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020047a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020047b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020047b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020047c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020047c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020047d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020047d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020047e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020047e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020047f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020047f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200480 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200480 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200481 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200481 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200482 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200482 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200483 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200483 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200484 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200484 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200485 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200485 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200486 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200486 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200487 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200487 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200488 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200488 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200489 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200489 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020048a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020048a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020048b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020048b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020048c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020048c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020048d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020048d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020048e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020048e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020048f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020048f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200490 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200490 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200491 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200491 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200492 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200492 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200493 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200493 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200494 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200494 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200495 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200495 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200496 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200496 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200497 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200497 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200498 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200498 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200499 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200499 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020049a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020049a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020049b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020049b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020049c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020049c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020049d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020049d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020049e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020049e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020049f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020049f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004a0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004a0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004a1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004a1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004a2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004a2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004a3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004a3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004a4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004a4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004a5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004a5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004a6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004a6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004a7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004a7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004a8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004a8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004a9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004a9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004aa RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004aa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004ab RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004ab NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004ac RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004ac NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004ad RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004ad NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004ae RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004ae NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004af RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004af NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004b0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004b0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004b1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004b1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004b2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004b2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004b3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004b3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004b4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004b4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004b5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004b5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004b6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004b6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004b7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004b7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004b8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004b8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004b9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004b9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004ba RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004ba NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004bb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004bb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004bc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004bc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004bd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004bd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004be RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004be NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004bf RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004bf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004c0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004c0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004c1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004c1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004c2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004c2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004c3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004c3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004c4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004c4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004c5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004c5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004c6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004c6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004c7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004c7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004c8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004c8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004c9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004c9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004ca RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004ca NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004cb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004cb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004cc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004cc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004cd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004cd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004ce RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004ce NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004cf RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004cf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004d0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004d0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004d1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004d1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004d2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004d2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004d3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004d3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004d4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004d4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004d5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004d5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004d6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004d6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004d7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004d7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004d8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004d8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004d9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004d9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004da RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004da NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004db RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004db NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004dc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004dc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004dd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004dd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004de RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004de NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004df RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004df NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004e0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004e0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004e1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004e1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004e2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004e2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004e3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004e3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004e4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004e4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004e5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004e5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004e6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004e6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004e7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004e7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004e8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004e8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004e9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004e9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004ea RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004ea NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004eb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004eb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004ec RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004ec NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004ed RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004ed NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004ee RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004ee NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004ef RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004ef NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004f0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004f0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004f1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004f1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004f2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004f2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004f3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004f3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004f4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004f4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004f5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004f5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004f6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004f6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004f7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004f7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004f8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004f8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004f9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004f9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004fa RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004fa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004fb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004fb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004fc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004fc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004fd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004fd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004fe RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004fe NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002004ff RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002004ff NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200500 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200500 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200501 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200501 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200502 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200502 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200503 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200503 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200504 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200504 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200505 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200505 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200506 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200506 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200507 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200507 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200508 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200508 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200509 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200509 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020050a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020050a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020050b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020050b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020050c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020050c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020050d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020050d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020050e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020050e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020050f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020050f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200510 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200510 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200511 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200511 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200512 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200512 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200513 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200513 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200514 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200514 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200515 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200515 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200516 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200516 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200517 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200517 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200518 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200518 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200519 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200519 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020051a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020051a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020051b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020051b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020051c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020051c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020051d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020051d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020051e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020051e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020051f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020051f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200520 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200520 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200521 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200521 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200522 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200522 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200523 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200523 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200524 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200524 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200525 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200525 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200526 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200526 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200527 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200527 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200528 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200528 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200529 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200529 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020052a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020052a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020052b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020052b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020052c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020052c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020052d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020052d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020052e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020052e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020052f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020052f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200530 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200530 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200531 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200531 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200532 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200532 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200533 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200533 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200534 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200534 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200535 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200535 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200536 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200536 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200537 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200537 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200538 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200538 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200539 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200539 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020053a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020053a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020053b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020053b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020053c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020053c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020053d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020053d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020053e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020053e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020053f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020053f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200540 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200540 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200541 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200541 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200542 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200542 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200543 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200543 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200544 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200544 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200545 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200545 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200546 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200546 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200547 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200547 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200548 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200548 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200549 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200549 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020054a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020054a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020054b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020054b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020054c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020054c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020054d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020054d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020054e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020054e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020054f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020054f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200550 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200550 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200551 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200551 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200552 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200552 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200553 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200553 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200554 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200554 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200555 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200555 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200556 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200556 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200557 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200557 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200558 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200558 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200559 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200559 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020055a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020055a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020055b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020055b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020055c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020055c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020055d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020055d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020055e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020055e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020055f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020055f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200560 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200560 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200561 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200561 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200562 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200562 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200563 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200563 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200564 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200564 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200565 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200565 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200566 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200566 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200567 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200567 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200568 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200568 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200569 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200569 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020056a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020056a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020056b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020056b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020056c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020056c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020056d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020056d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020056e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020056e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020056f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020056f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200570 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200570 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200571 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200571 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200572 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200572 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200573 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200573 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200574 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200574 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200575 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200575 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200576 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200576 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200577 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200577 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200578 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200578 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200579 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200579 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020057a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020057a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020057b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020057b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020057c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020057c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020057d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020057d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020057e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020057e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020057f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020057f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200580 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200580 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200581 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200581 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200582 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200582 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200583 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200583 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200584 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200584 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200585 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200585 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200586 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200586 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200587 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200587 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200588 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200588 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200589 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200589 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020058a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020058a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020058b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020058b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020058c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020058c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020058d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020058d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020058e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020058e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020058f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020058f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200590 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200590 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200591 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200591 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200592 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200592 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200593 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200593 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200594 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200594 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200595 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200595 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200596 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200596 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200597 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200597 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200598 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200598 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200599 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200599 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020059a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020059a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020059b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020059b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020059c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020059c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020059d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020059d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020059e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020059e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020059f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020059f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005a0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005a0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005a1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005a1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005a2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005a2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005a3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005a3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005a4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005a4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005a5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005a5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005a6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005a6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005a7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005a7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005a8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005a8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005a9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005a9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005aa RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005aa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005ab RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005ab NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005ac RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005ac NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005ad RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005ad NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005ae RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005ae NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005af RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005af NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005b0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005b0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005b1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005b1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005b2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005b2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005b3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005b3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005b4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005b4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005b5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005b5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005b6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005b6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005b7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005b7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005b8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005b8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005b9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005b9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005ba RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005ba NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005bb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005bb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005bc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005bc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005bd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005bd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005be RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005be NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005bf RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005bf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005c0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005c0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005c1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005c1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005c2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005c2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005c3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005c3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005c4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005c4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005c5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005c5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005c6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005c6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005c7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005c7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005c8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005c8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005c9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005c9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005ca RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005ca NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005cb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005cb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005cc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005cc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005cd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005cd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005ce RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005ce NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005cf RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005cf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005d0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005d0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005d1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005d1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005d2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005d2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005d3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005d3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005d4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005d4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005d5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005d5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005d6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005d6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005d7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005d7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005d8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005d8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005d9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005d9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005da RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005da NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005db RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005db NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005dc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005dc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005dd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005dd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005de RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005de NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005df RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005df NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005e0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005e0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005e1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005e1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005e2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005e2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005e3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005e3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005e4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005e4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005e5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005e5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005e6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005e6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005e7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005e7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005e8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005e8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005e9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005e9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005ea RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005ea NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005eb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005eb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005ec RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005ec NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005ed RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005ed NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005ee RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005ee NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005ef RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005ef NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005f0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005f0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005f1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005f1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005f2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005f2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005f3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005f3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005f4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005f4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005f5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005f5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005f6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005f6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005f7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005f7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005f8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005f8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005f9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005f9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005fa RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005fa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005fb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005fb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005fc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005fc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005fd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005fd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005fe RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005fe NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002005ff RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002005ff NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200600 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200600 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200601 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200601 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200602 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200602 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200603 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200603 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200604 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200604 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200605 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200605 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200606 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200606 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200607 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200607 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200608 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200608 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200609 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200609 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020060a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020060a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020060b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020060b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020060c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020060c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020060d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020060d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020060e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020060e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020060f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020060f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200610 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200610 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200611 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200611 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200612 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200612 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200613 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200613 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200614 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200614 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200615 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200615 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200616 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200616 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200617 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200617 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200618 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200618 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200619 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200619 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020061a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020061a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020061b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020061b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020061c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020061c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020061d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020061d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020061e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020061e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020061f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020061f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200620 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200620 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200621 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200621 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200622 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200622 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200623 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200623 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200624 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200624 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200625 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200625 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200626 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200626 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200627 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200627 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200628 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200628 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200629 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200629 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020062a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020062a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020062b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020062b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020062c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020062c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020062d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020062d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020062e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020062e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020062f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020062f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200630 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200630 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200631 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200631 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200632 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200632 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200633 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200633 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200634 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200634 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200635 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200635 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200636 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200636 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200637 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200637 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200638 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200638 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200639 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200639 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020063a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020063a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020063b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020063b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020063c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020063c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020063d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020063d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020063e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020063e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020063f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020063f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200640 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200640 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200641 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200641 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200642 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200642 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200643 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200643 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200644 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200644 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200645 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200645 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200646 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200646 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200647 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200647 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200648 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200648 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200649 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200649 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020064a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020064a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020064b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020064b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020064c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020064c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020064d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020064d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020064e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020064e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020064f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020064f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200650 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200650 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200651 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200651 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200652 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200652 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200653 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200653 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200654 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200654 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200655 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200655 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200656 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200656 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200657 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200657 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200658 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200658 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200659 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200659 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020065a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020065a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020065b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020065b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020065c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020065c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020065d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020065d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020065e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020065e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020065f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020065f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200660 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200660 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200661 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200661 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200662 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200662 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200663 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200663 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200664 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200664 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200665 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200665 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200666 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200666 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200667 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200667 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200668 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200668 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200669 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200669 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020066a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020066a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020066b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020066b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020066c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020066c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020066d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020066d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020066e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020066e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020066f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020066f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200670 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200670 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200671 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200671 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200672 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200672 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200673 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200673 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200674 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200674 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200675 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200675 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200676 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200676 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200677 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200677 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200678 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200678 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200679 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200679 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020067a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020067a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020067b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020067b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020067c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020067c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020067d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020067d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020067e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020067e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020067f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020067f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200680 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200680 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200681 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200681 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200682 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200682 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200683 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200683 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200684 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200684 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200685 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200685 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200686 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200686 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200687 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200687 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200688 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200688 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200689 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200689 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020068a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020068a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020068b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020068b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020068c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020068c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020068d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020068d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020068e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020068e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020068f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020068f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200690 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200690 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200691 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200691 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200692 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200692 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200693 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200693 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200694 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200694 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200695 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200695 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200696 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200696 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200697 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200697 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200698 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200698 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200699 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200699 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020069a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020069a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020069b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020069b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020069c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020069c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020069d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020069d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020069e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020069e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020069f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020069f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006a0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006a0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006a1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006a1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006a2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006a2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006a3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006a3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006a4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006a4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006a5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006a5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006a6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006a6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006a7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006a7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006a8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006a8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006a9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006a9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006aa RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006aa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006ab RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006ab NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006ac RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006ac NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006ad RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006ad NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006ae RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006ae NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006af RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006af NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006b0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006b0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006b1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006b1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006b2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006b2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006b3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006b3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006b4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006b4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006b5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006b5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006b6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006b6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006b7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006b7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006b8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006b8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006b9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006b9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006ba RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006ba NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006bb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006bb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006bc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006bc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006bd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006bd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006be RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006be NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006bf RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006bf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006c0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006c0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006c1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006c1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006c2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006c2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006c3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006c3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006c4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006c4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006c5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006c5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006c6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006c6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006c7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006c7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006c8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006c8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006c9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006c9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006ca RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006ca NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006cb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006cb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006cc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006cc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006cd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006cd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006ce RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006ce NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006cf RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006cf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006d0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006d0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006d1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006d1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006d2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006d2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006d3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006d3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006d4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006d4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006d5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006d5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006d6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006d6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006d7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006d7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006d8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006d8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006d9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006d9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006da RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006da NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006db RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006db NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006dc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006dc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006dd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006dd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006de RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006de NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006df RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006df NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006e0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006e0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006e1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006e1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006e2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006e2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006e3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006e3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006e4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006e4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006e5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006e5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006e6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006e6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006e7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006e7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006e8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006e8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006e9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006e9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006ea RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006ea NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006eb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006eb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006ec RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006ec NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006ed RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006ed NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006ee RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006ee NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006ef RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006ef NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006f0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006f0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006f1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006f1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006f2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006f2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006f3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006f3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006f4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006f4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006f5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006f5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006f6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006f6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006f7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006f7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006f8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006f8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006f9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006f9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006fa RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006fa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006fb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006fb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006fc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006fc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006fd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006fd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006fe RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006fe NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002006ff RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002006ff NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200700 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200700 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200701 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200701 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200702 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200702 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200703 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200703 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200704 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200704 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200705 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200705 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200706 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200706 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200707 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200707 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200708 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200708 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200709 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200709 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020070a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020070a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020070b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020070b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020070c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020070c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020070d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020070d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020070e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020070e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020070f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020070f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200710 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200710 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200711 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200711 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200712 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200712 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200713 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200713 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200714 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200714 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200715 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200715 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200716 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200716 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200717 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200717 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200718 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200718 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200719 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200719 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020071a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020071a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020071b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020071b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020071c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020071c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020071d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020071d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020071e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020071e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020071f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020071f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200720 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200720 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200721 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200721 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200722 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200722 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200723 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200723 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200724 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200724 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200725 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200725 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200726 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200726 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200727 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200727 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200728 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200728 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200729 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200729 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020072a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020072a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020072b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020072b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020072c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020072c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020072d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020072d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020072e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020072e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020072f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020072f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200730 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200730 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200731 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200731 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200732 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200732 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200733 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200733 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200734 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200734 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200735 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200735 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200736 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200736 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200737 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200737 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200738 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200738 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200739 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200739 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020073a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020073a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020073b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020073b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020073c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020073c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020073d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020073d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020073e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020073e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020073f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020073f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200740 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200740 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200741 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200741 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200742 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200742 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200743 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200743 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200744 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200744 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200745 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200745 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200746 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200746 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200747 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200747 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200748 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200748 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200749 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200749 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020074a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020074a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020074b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020074b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020074c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020074c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020074d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020074d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020074e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020074e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020074f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020074f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200750 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200750 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200751 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200751 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200752 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200752 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200753 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200753 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200754 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200754 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200755 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200755 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200756 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200756 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200757 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200757 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200758 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200758 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200759 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200759 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020075a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020075a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020075b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020075b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020075c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020075c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020075d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020075d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020075e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020075e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020075f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020075f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200760 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200760 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200761 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200761 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200762 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200762 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200763 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200763 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200764 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200764 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200765 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200765 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200766 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200766 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200767 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200767 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200768 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200768 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200769 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200769 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020076a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020076a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020076b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020076b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020076c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020076c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020076d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020076d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020076e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020076e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020076f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020076f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200770 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200770 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200771 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200771 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200772 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200772 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200773 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200773 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200774 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200774 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200775 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200775 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200776 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200776 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200777 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200777 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200778 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200778 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200779 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200779 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020077a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020077a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020077b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020077b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020077c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020077c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020077d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020077d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020077e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020077e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020077f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020077f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200780 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200780 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200781 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200781 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200782 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200782 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200783 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200783 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200784 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200784 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200785 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200785 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200786 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200786 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200787 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200787 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200788 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200788 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200789 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200789 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020078a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020078a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020078b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020078b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020078c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020078c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020078d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020078d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020078e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020078e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020078f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020078f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200790 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200790 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200791 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200791 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200792 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200792 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200793 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200793 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200794 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200794 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200795 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200795 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200796 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200796 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200797 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200797 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200798 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200798 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200799 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200799 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020079a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020079a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020079b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020079b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020079c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020079c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020079d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020079d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020079e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020079e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020079f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020079f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007a0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007a0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007a1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007a1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007a2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007a2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007a3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007a3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007a4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007a4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007a5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007a5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007a6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007a6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007a7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007a7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007a8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007a8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007a9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007a9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007aa RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007aa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007ab RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007ab NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007ac RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007ac NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007ad RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007ad NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007ae RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007ae NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007af RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007af NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007b0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007b0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007b1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007b1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007b2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007b2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007b3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007b3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007b4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007b4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007b5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007b5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007b6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007b6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007b7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007b7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007b8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007b8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007b9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007b9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007ba RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007ba NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007bb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007bb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007bc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007bc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007bd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007bd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007be RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007be NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007bf RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007bf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007c0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007c0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007c1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007c1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007c2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007c2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007c3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007c3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007c4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007c4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007c5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007c5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007c6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007c6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007c7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007c7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007c8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007c8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007c9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007c9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007ca RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007ca NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007cb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007cb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007cc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007cc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007cd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007cd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007ce RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007ce NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007cf RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007cf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007d0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007d0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007d1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007d1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007d2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007d2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007d3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007d3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007d4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007d4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007d5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007d5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007d6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007d6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007d7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007d7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007d8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007d8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007d9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007d9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007da RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007da NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007db RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007db NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007dc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007dc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007dd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007dd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007de RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007de NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007df RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007df NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007e0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007e0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007e1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007e1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007e2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007e2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007e3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007e3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007e4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007e4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007e5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007e5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007e6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007e6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007e7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007e7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007e8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007e8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007e9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007e9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007ea RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007ea NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007eb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007eb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007ec RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007ec NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007ed RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007ed NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007ee RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007ee NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007ef RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007ef NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007f0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007f0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007f1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007f1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007f2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007f2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007f3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007f3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007f4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007f4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007f5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007f5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007f6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007f6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007f7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007f7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007f8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007f8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007f9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007f9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007fa RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007fa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007fb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007fb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007fc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007fc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007fd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007fd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007fe RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007fe NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002007ff RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002007ff NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200800 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200800 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200801 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200801 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200802 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200802 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200803 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200803 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200804 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200804 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200805 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200805 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200806 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200806 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200807 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200807 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200808 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200808 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200809 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200809 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020080a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020080a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020080b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020080b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020080c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020080c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020080d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020080d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020080e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020080e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020080f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020080f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200810 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200810 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200811 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200811 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200812 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200812 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200813 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200813 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200814 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200814 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200815 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200815 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200816 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200816 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200817 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200817 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200818 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200818 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200819 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200819 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020081a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020081a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020081b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020081b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020081c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020081c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020081d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020081d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020081e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020081e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020081f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020081f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200820 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200820 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200821 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200821 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200822 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200822 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200823 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200823 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200824 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200824 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200825 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200825 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200826 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200826 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200827 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200827 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200828 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200828 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200829 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200829 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020082a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020082a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020082b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020082b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020082c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020082c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020082d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020082d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020082e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020082e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020082f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020082f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200830 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200830 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200831 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200831 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200832 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200832 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200833 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200833 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200834 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200834 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200835 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200835 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200836 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200836 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200837 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200837 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200838 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200838 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200839 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200839 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020083a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020083a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020083b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020083b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020083c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020083c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020083d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020083d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020083e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020083e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020083f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020083f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200840 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200840 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200841 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200841 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200842 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200842 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200843 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200843 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200844 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200844 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200845 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200845 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200846 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200846 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200847 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200847 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200848 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200848 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200849 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200849 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020084a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020084a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020084b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020084b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020084c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020084c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020084d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020084d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020084e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020084e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020084f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020084f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200850 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200850 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200851 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200851 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200852 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200852 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200853 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200853 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200854 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200854 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200855 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200855 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200856 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200856 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200857 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200857 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200858 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200858 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200859 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200859 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020085a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020085a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020085b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020085b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020085c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020085c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020085d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020085d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020085e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020085e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020085f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020085f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200860 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200860 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200861 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200861 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200862 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200862 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200863 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200863 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200864 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200864 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200865 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200865 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200866 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200866 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200867 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200867 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200868 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200868 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200869 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200869 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020086a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020086a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020086b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020086b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020086c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020086c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020086d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020086d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020086e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020086e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020086f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020086f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200870 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200870 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200871 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200871 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200872 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200872 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200873 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200873 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200874 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200874 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200875 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200875 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200876 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200876 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200877 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200877 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200878 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200878 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200879 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200879 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020087a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020087a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020087b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020087b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020087c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020087c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020087d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020087d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020087e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020087e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020087f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020087f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200880 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200880 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200881 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200881 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200882 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200882 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200883 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200883 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200884 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200884 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200885 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200885 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200886 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200886 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200887 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200887 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200888 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200888 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200889 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200889 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020088a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020088a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020088b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020088b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020088c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020088c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020088d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020088d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020088e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020088e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020088f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020088f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200890 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200890 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200891 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200891 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200892 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200892 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200893 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200893 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200894 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200894 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200895 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200895 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200896 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200896 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200897 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200897 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200898 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200898 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200899 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200899 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020089a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020089a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020089b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020089b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020089c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020089c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020089d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020089d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020089e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020089e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020089f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020089f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008a0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008a0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008a1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008a1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008a2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008a2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008a3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008a3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008a4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008a4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008a5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008a5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008a6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008a6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008a7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008a7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008a8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008a8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008a9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008a9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008aa RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008aa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008ab RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008ab NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008ac RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008ac NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008ad RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008ad NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008ae RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008ae NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008af RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008af NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008b0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008b0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008b1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008b1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008b2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008b2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008b3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008b3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008b4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008b4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008b5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008b5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008b6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008b6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008b7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008b7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008b8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008b8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008b9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008b9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008ba RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008ba NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008bb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008bb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008bc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008bc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008bd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008bd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008be RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008be NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008bf RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008bf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008c0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008c0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008c1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008c1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008c2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008c2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008c3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008c3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008c4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008c4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008c5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008c5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008c6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008c6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008c7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008c7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008c8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008c8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008c9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008c9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008ca RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008ca NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008cb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008cb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008cc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008cc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008cd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008cd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008ce RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008ce NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008cf RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008cf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008d0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008d0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008d1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008d1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008d2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008d2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008d3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008d3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008d4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008d4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008d5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008d5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008d6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008d6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008d7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008d7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008d8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008d8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008d9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008d9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008da RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008da NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008db RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008db NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008dc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008dc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008dd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008dd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008de RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008de NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008df RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008df NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008e0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008e0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008e1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008e1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008e2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008e2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008e3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008e3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008e4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008e4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008e5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008e5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008e6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008e6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008e7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008e7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008e8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008e8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008e9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008e9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008ea RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008ea NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008eb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008eb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008ec RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008ec NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008ed RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008ed NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008ee RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008ee NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008ef RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008ef NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008f0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008f0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008f1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008f1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008f2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008f2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008f3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008f3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008f4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008f4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008f5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008f5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008f6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008f6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008f7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008f7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008f8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008f8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008f9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008f9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008fa RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008fa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008fb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008fb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008fc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008fc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008fd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008fd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008fe RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008fe NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002008ff RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002008ff NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200900 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200900 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200901 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200901 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200902 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200902 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200903 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200903 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200904 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200904 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200905 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200905 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200906 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200906 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200907 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200907 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200908 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200908 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200909 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200909 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020090a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020090a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020090b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020090b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020090c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020090c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020090d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020090d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020090e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020090e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020090f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020090f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200910 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200910 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200911 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200911 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200912 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200912 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200913 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200913 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200914 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200914 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200915 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200915 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200916 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200916 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200917 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200917 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200918 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200918 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200919 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200919 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020091a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020091a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020091b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020091b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020091c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020091c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020091d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020091d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020091e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020091e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020091f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020091f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200920 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200920 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200921 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200921 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200922 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200922 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200923 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200923 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200924 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200924 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200925 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200925 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200926 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200926 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200927 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200927 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200928 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200928 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200929 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200929 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020092a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020092a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020092b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020092b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020092c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020092c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020092d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020092d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020092e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020092e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020092f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020092f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200930 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200930 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200931 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200931 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200932 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200932 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200933 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200933 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200934 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200934 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200935 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200935 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200936 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200936 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200937 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200937 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200938 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200938 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200939 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200939 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020093a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020093a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020093b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020093b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020093c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020093c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020093d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020093d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020093e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020093e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020093f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020093f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200940 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200940 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200941 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200941 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200942 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200942 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200943 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200943 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200944 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200944 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200945 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200945 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200946 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200946 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200947 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200947 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200948 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200948 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200949 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200949 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020094a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020094a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020094b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020094b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020094c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020094c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020094d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020094d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020094e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020094e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020094f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020094f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200950 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200950 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200951 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200951 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200952 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200952 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200953 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200953 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200954 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200954 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200955 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200955 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200956 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200956 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200957 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200957 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200958 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200958 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200959 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200959 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020095a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020095a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020095b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020095b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020095c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020095c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020095d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020095d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020095e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020095e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020095f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020095f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200960 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200960 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200961 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200961 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200962 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200962 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200963 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200963 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200964 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200964 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200965 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200965 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200966 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200966 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200967 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200967 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200968 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200968 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200969 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200969 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020096a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020096a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020096b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020096b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020096c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020096c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020096d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020096d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020096e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020096e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020096f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020096f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200970 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200970 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200971 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200971 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200972 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200972 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200973 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200973 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200974 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200974 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200975 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200975 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200976 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200976 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200977 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200977 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200978 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200978 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200979 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200979 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020097a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020097a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020097b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020097b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020097c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020097c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020097d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020097d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020097e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020097e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020097f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020097f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200980 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200980 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200981 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200981 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200982 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200982 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200983 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200983 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200984 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200984 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200985 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200985 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200986 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200986 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200987 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200987 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200988 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200988 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200989 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200989 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020098a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020098a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020098b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020098b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020098c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020098c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020098d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020098d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020098e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020098e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020098f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020098f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200990 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200990 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200991 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200991 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200992 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200992 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200993 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200993 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200994 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200994 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200995 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200995 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200996 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200996 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200997 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200997 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200998 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200998 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200999 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200999 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020099a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020099a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020099b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020099b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020099c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020099c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020099d RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020099d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020099e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020099e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020099f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020099f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009a0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009a0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009a1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009a1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009a2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009a2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009a3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009a3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009a4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009a4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009a5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009a5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009a6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009a6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009a7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009a7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009a8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009a8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009a9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009a9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009aa RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009aa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009ab RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009ab NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009ac RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009ac NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009ad RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009ad NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009ae RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009ae NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009af RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009af NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009b0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009b0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009b1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009b1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009b2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009b2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009b3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009b3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009b4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009b4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009b5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009b5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009b6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009b6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009b7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009b7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009b8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009b8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009b9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009b9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009ba RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009ba NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009bb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009bb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009bc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009bc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009bd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009bd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009be RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009be NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009bf RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009bf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009c0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009c0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009c1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009c1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009c2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009c2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009c3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009c3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009c4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009c4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009c5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009c5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009c6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009c6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009c7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009c7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009c8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009c8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009c9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009c9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009ca RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009ca NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009cb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009cb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009cc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009cc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009cd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009cd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009ce RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009ce NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009cf RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009cf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009d0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009d0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009d1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009d1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009d2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009d2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009d3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009d3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009d4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009d4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009d5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009d5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009d6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009d6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009d7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009d7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009d8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009d8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009d9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009d9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009da RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009da NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009db RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009db NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009dc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009dc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009dd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009dd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009de RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009de NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009df RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009df NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009e0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009e0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009e1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009e1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009e2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009e2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009e3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009e3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009e4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009e4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009e5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009e5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009e6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009e6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009e7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009e7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009e8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009e8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009e9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009e9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009ea RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009ea NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009eb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009eb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009ec RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009ec NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009ed RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009ed NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009ee RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009ee NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009ef RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009ef NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009f0 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009f0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009f1 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009f1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009f2 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009f2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009f3 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009f3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009f4 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009f4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009f5 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009f5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009f6 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009f6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009f7 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009f7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009f8 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009f8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009f9 RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009f9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009fa RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009fa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009fb RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009fb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009fc RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009fc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009fd RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009fd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009fe RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009fe NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x00000000002009ff RFLAGS = 0x0000000000000202 +Emulating: 0x00000000002009ff NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a00 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a00 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a01 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a01 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a02 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a02 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a03 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a03 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a04 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a04 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a05 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a05 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a06 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a06 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a07 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a07 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a08 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a08 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a09 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a09 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a0a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a0a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a0b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a0b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a0c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a0c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a0d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a0d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a0e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a0e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a0f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a0f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a10 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a10 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a11 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a11 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a12 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a12 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a13 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a13 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a14 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a14 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a15 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a15 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a16 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a16 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a17 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a17 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a18 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a18 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a19 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a19 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a1a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a1a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a1b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a1b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a1c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a1c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a1d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a1d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a1e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a1e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a1f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a1f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a20 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a20 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a21 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a21 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a22 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a22 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a23 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a23 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a24 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a24 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a25 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a25 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a26 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a26 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a27 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a27 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a28 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a28 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a29 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a29 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a2a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a2a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a2b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a2b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a2c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a2c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a2d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a2d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a2e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a2e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a2f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a2f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a30 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a30 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a31 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a31 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a32 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a32 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a33 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a33 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a34 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a34 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a35 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a35 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a36 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a36 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a37 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a37 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a38 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a38 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a39 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a39 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a3a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a3a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a3b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a3b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a3c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a3c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a3d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a3d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a3e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a3e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a3f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a3f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a40 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a40 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a41 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a41 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a42 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a42 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a43 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a43 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a44 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a44 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a45 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a45 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a46 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a46 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a47 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a47 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a48 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a48 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a49 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a49 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a4a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a4a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a4b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a4b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a4c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a4c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a4d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a4d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a4e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a4e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a4f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a4f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a50 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a50 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a51 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a51 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a52 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a52 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a53 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a53 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a54 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a54 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a55 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a55 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a56 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a56 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a57 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a57 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a58 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a58 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a59 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a59 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a5a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a5a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a5b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a5b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a5c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a5c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a5d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a5d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a5e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a5e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a5f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a5f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a60 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a60 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a61 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a61 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a62 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a62 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a63 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a63 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a64 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a64 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a65 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a65 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a66 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a66 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a67 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a67 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a68 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a68 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a69 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a69 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a6a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a6a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a6b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a6b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a6c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a6c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a6d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a6d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a6e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a6e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a6f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a6f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a70 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a70 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a71 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a71 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a72 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a72 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a73 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a73 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a74 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a74 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a75 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a75 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a76 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a76 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a77 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a77 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a78 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a78 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a79 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a79 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a7a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a7a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a7b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a7b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a7c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a7c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a7d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a7d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a7e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a7e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a7f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a7f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a80 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a80 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a81 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a81 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a82 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a82 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a83 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a83 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a84 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a84 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a85 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a85 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a86 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a86 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a87 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a87 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a88 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a88 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a89 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a89 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a8a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a8a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a8b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a8b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a8c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a8c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a8d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a8d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a8e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a8e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a8f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a8f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a90 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a90 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a91 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a91 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a92 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a92 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a93 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a93 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a94 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a94 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a95 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a95 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a96 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a96 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a97 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a97 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a98 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a98 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a99 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a99 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a9a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a9a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a9b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a9b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a9c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a9c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a9d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a9d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a9e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a9e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200a9f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200a9f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200aa0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200aa0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200aa1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200aa1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200aa2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200aa2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200aa3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200aa3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200aa4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200aa4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200aa5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200aa5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200aa6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200aa6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200aa7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200aa7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200aa8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200aa8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200aa9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200aa9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200aaa RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200aaa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200aab RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200aab NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200aac RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200aac NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200aad RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200aad NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200aae RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200aae NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200aaf RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200aaf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ab0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ab0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ab1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ab1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ab2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ab2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ab3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ab3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ab4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ab4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ab5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ab5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ab6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ab6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ab7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ab7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ab8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ab8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ab9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ab9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200aba RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200aba NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200abb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200abb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200abc RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200abc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200abd RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200abd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200abe RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200abe NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200abf RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200abf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ac0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ac0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ac1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ac1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ac2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ac2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ac3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ac3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ac4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ac4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ac5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ac5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ac6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ac6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ac7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ac7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ac8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ac8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ac9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ac9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200aca RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200aca NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200acb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200acb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200acc RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200acc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200acd RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200acd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ace RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ace NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200acf RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200acf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ad0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ad0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ad1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ad1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ad2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ad2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ad3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ad3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ad4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ad4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ad5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ad5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ad6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ad6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ad7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ad7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ad8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ad8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ad9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ad9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ada RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ada NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200adb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200adb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200adc RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200adc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200add RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200add NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ade RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ade NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200adf RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200adf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ae0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ae0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ae1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ae1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ae2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ae2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ae3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ae3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ae4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ae4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ae5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ae5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ae6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ae6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ae7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ae7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ae8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ae8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ae9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ae9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200aea RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200aea NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200aeb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200aeb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200aec RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200aec NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200aed RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200aed NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200aee RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200aee NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200aef RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200aef NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200af0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200af0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200af1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200af1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200af2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200af2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200af3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200af3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200af4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200af4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200af5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200af5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200af6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200af6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200af7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200af7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200af8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200af8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200af9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200af9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200afa RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200afa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200afb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200afb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200afc RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200afc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200afd RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200afd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200afe RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200afe NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200aff RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200aff NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b00 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b00 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b01 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b01 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b02 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b02 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b03 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b03 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b04 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b04 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b05 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b05 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b06 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b06 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b07 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b07 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b08 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b08 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b09 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b09 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b0a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b0a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b0b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b0b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b0c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b0c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b0d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b0d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b0e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b0e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b0f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b0f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b10 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b10 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b11 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b11 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b12 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b12 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b13 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b13 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b14 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b14 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b15 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b15 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b16 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b16 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b17 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b17 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b18 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b18 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b19 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b19 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b1a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b1a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b1b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b1b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b1c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b1c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b1d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b1d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b1e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b1e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b1f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b1f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b20 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b20 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b21 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b21 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b22 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b22 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b23 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b23 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b24 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b24 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b25 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b25 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b26 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b26 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b27 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b27 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b28 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b28 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b29 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b29 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b2a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b2a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b2b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b2b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b2c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b2c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b2d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b2d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b2e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b2e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b2f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b2f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b30 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b30 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b31 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b31 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b32 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b32 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b33 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b33 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b34 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b34 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b35 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b35 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b36 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b36 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b37 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b37 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b38 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b38 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b39 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b39 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b3a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b3a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b3b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b3b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b3c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b3c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b3d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b3d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b3e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b3e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b3f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b3f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b40 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b40 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b41 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b41 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b42 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b42 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b43 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b43 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b44 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b44 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b45 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b45 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b46 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b46 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b47 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b47 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b48 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b48 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b49 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b49 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b4a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b4a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b4b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b4b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b4c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b4c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b4d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b4d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b4e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b4e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b4f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b4f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b50 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b50 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b51 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b51 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b52 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b52 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b53 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b53 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b54 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b54 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b55 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b55 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b56 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b56 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b57 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b57 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b58 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b58 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b59 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b59 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b5a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b5a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b5b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b5b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b5c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b5c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b5d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b5d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b5e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b5e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b5f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b5f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b60 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b60 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b61 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b61 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b62 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b62 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b63 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b63 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b64 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b64 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b65 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b65 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b66 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b66 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b67 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b67 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b68 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b68 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b69 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b69 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b6a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b6a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b6b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b6b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b6c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b6c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b6d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b6d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b6e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b6e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b6f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b6f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b70 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b70 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b71 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b71 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b72 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b72 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b73 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b73 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b74 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b74 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b75 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b75 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b76 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b76 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b77 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b77 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b78 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b78 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b79 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b79 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b7a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b7a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b7b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b7b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b7c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b7c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b7d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b7d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b7e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b7e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b7f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b7f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b80 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b80 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b81 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b81 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b82 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b82 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b83 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b83 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b84 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b84 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b85 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b85 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b86 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b86 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b87 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b87 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b88 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b88 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b89 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b89 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b8a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b8a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b8b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b8b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b8c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b8c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b8d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b8d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b8e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b8e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b8f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b8f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b90 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b90 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b91 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b91 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b92 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b92 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b93 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b93 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b94 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b94 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b95 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b95 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b96 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b96 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b97 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b97 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b98 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b98 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b99 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b99 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b9a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b9a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b9b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b9b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b9c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b9c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b9d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b9d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b9e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b9e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200b9f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200b9f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ba0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ba0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ba1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ba1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ba2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ba2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ba3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ba3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ba4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ba4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ba5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ba5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ba6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ba6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ba7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ba7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ba8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ba8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ba9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ba9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200baa RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200baa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bab RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bab NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bac RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bac NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bad RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bad NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bae RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bae NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200baf RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200baf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bb0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bb0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bb1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bb1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bb2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bb2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bb3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bb3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bb4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bb4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bb5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bb5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bb6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bb6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bb7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bb7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bb8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bb8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bb9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bb9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bba RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bba NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bbb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bbb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bbc RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bbc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bbd RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bbd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bbe RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bbe NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bbf RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bbf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bc0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bc0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bc1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bc1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bc2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bc2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bc3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bc3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bc4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bc4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bc5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bc5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bc6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bc6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bc7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bc7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bc8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bc8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bc9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bc9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bca RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bca NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bcb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bcb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bcc RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bcc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bcd RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bcd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bce RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bce NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bcf RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bcf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bd0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bd0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bd1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bd1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bd2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bd2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bd3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bd3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bd4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bd4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bd5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bd5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bd6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bd6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bd7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bd7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bd8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bd8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bd9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bd9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bda RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bda NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bdb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bdb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bdc RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bdc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bdd RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bdd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bde RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bde NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bdf RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bdf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200be0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200be0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200be1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200be1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200be2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200be2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200be3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200be3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200be4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200be4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200be5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200be5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200be6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200be6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200be7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200be7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200be8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200be8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200be9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200be9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bea RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bea NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200beb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200beb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bec RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bec NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bed RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bed NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bee RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bee NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bef RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bef NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bf0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bf0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bf1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bf1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bf2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bf2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bf3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bf3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bf4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bf4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bf5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bf5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bf6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bf6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bf7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bf7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bf8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bf8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bf9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bf9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bfa RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bfa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bfb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bfb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bfc RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bfc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bfd RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bfd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bfe RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bfe NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200bff RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200bff NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c00 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c00 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c01 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c01 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c02 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c02 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c03 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c03 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c04 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c04 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c05 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c05 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c06 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c06 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c07 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c07 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c08 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c08 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c09 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c09 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c0a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c0a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c0b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c0b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c0c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c0c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c0d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c0d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c0e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c0e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c0f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c0f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c10 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c10 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c11 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c11 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c12 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c12 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c13 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c13 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c14 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c14 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c15 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c15 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c16 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c16 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c17 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c17 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c18 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c18 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c19 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c19 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c1a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c1a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c1b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c1b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c1c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c1c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c1d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c1d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c1e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c1e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c1f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c1f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c20 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c20 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c21 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c21 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c22 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c22 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c23 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c23 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c24 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c24 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c25 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c25 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c26 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c26 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c27 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c27 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c28 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c28 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c29 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c29 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c2a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c2a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c2b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c2b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c2c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c2c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c2d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c2d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c2e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c2e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c2f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c2f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c30 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c30 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c31 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c31 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c32 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c32 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c33 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c33 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c34 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c34 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c35 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c35 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c36 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c36 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c37 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c37 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c38 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c38 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c39 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c39 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c3a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c3a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c3b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c3b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c3c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c3c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c3d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c3d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c3e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c3e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c3f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c3f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c40 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c40 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c41 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c41 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c42 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c42 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c43 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c43 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c44 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c44 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c45 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c45 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c46 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c46 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c47 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c47 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c48 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c48 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c49 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c49 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c4a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c4a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c4b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c4b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c4c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c4c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c4d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c4d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c4e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c4e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c4f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c4f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c50 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c50 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c51 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c51 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c52 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c52 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c53 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c53 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c54 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c54 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c55 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c55 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c56 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c56 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c57 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c57 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c58 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c58 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c59 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c59 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c5a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c5a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c5b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c5b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c5c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c5c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c5d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c5d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c5e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c5e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c5f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c5f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c60 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c60 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c61 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c61 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c62 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c62 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c63 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c63 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c64 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c64 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c65 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c65 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c66 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c66 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c67 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c67 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c68 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c68 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c69 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c69 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c6a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c6a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c6b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c6b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c6c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c6c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c6d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c6d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c6e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c6e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c6f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c6f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c70 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c70 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c71 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c71 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c72 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c72 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c73 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c73 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c74 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c74 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c75 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c75 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c76 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c76 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c77 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c77 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c78 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c78 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c79 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c79 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c7a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c7a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c7b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c7b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c7c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c7c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c7d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c7d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c7e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c7e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c7f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c7f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c80 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c80 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c81 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c81 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c82 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c82 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c83 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c83 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c84 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c84 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c85 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c85 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c86 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c86 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c87 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c87 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c88 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c88 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c89 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c89 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c8a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c8a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c8b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c8b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c8c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c8c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c8d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c8d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c8e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c8e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c8f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c8f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c90 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c90 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c91 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c91 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c92 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c92 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c93 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c93 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c94 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c94 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c95 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c95 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c96 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c96 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c97 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c97 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c98 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c98 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c99 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c99 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c9a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c9a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c9b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c9b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c9c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c9c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c9d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c9d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c9e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c9e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200c9f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200c9f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ca0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ca0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ca1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ca1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ca2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ca2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ca3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ca3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ca4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ca4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ca5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ca5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ca6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ca6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ca7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ca7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ca8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ca8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ca9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ca9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200caa RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200caa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cab RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cab NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cac RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cac NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cad RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cad NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cae RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cae NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200caf RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200caf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cb0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cb0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cb1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cb1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cb2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cb2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cb3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cb3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cb4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cb4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cb5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cb5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cb6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cb6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cb7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cb7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cb8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cb8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cb9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cb9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cba RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cba NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cbb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cbb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cbc RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cbc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cbd RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cbd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cbe RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cbe NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cbf RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cbf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cc0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cc0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cc1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cc1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cc2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cc2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cc3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cc3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cc4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cc4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cc5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cc5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cc6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cc6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cc7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cc7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cc8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cc8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cc9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cc9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cca RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cca NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ccb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ccb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ccc RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ccc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ccd RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ccd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cce RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cce NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ccf RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ccf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cd0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cd0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cd1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cd1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cd2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cd2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cd3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cd3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cd4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cd4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cd5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cd5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cd6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cd6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cd7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cd7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cd8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cd8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cd9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cd9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cda RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cda NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cdb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cdb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cdc RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cdc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cdd RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cdd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cde RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cde NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cdf RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cdf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ce0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ce0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ce1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ce1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ce2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ce2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ce3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ce3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ce4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ce4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ce5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ce5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ce6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ce6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ce7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ce7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ce8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ce8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ce9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ce9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cea RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cea NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ceb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ceb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cec RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cec NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ced RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ced NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cee RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cee NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cef RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cef NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cf0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cf0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cf1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cf1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cf2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cf2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cf3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cf3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cf4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cf4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cf5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cf5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cf6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cf6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cf7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cf7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cf8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cf8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cf9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cf9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cfa RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cfa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cfb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cfb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cfc RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cfc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cfd RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cfd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cfe RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cfe NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200cff RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200cff NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d00 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d00 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d01 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d01 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d02 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d02 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d03 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d03 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d04 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d04 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d05 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d05 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d06 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d06 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d07 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d07 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d08 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d08 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d09 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d09 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d0a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d0a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d0b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d0b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d0c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d0c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d0d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d0d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d0e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d0e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d0f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d0f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d10 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d10 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d11 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d11 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d12 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d12 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d13 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d13 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d14 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d14 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d15 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d15 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d16 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d16 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d17 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d17 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d18 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d18 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d19 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d19 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d1a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d1a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d1b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d1b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d1c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d1c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d1d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d1d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d1e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d1e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d1f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d1f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d20 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d20 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d21 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d21 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d22 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d22 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d23 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d23 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d24 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d24 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d25 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d25 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d26 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d26 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d27 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d27 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d28 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d28 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d29 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d29 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d2a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d2a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d2b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d2b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d2c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d2c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d2d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d2d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d2e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d2e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d2f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d2f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d30 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d30 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d31 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d31 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d32 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d32 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d33 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d33 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d34 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d34 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d35 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d35 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d36 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d36 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d37 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d37 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d38 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d38 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d39 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d39 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d3a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d3a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d3b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d3b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d3c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d3c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d3d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d3d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d3e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d3e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d3f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d3f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d40 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d40 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d41 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d41 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d42 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d42 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d43 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d43 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d44 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d44 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d45 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d45 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d46 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d46 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d47 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d47 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d48 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d48 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d49 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d49 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d4a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d4a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d4b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d4b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d4c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d4c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d4d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d4d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d4e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d4e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d4f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d4f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d50 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d50 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d51 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d51 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d52 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d52 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d53 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d53 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d54 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d54 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d55 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d55 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d56 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d56 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d57 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d57 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d58 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d58 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d59 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d59 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d5a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d5a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d5b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d5b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d5c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d5c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d5d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d5d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d5e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d5e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d5f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d5f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d60 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d60 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d61 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d61 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d62 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d62 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d63 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d63 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d64 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d64 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d65 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d65 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d66 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d66 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d67 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d67 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d68 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d68 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d69 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d69 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d6a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d6a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d6b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d6b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d6c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d6c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d6d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d6d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d6e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d6e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d6f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d6f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d70 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d70 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d71 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d71 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d72 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d72 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d73 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d73 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d74 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d74 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d75 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d75 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d76 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d76 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d77 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d77 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d78 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d78 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d79 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d79 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d7a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d7a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d7b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d7b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d7c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d7c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d7d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d7d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d7e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d7e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d7f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d7f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d80 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d80 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d81 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d81 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d82 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d82 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d83 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d83 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d84 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d84 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d85 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d85 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d86 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d86 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d87 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d87 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d88 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d88 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d89 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d89 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d8a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d8a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d8b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d8b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d8c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d8c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d8d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d8d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d8e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d8e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d8f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d8f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d90 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d90 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d91 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d91 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d92 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d92 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d93 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d93 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d94 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d94 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d95 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d95 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d96 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d96 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d97 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d97 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d98 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d98 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d99 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d99 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d9a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d9a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d9b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d9b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d9c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d9c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d9d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d9d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d9e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d9e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200d9f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200d9f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200da0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200da0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200da1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200da1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200da2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200da2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200da3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200da3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200da4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200da4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200da5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200da5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200da6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200da6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200da7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200da7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200da8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200da8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200da9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200da9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200daa RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200daa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dab RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dab NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dac RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dac NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dad RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dad NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dae RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dae NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200daf RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200daf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200db0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200db0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200db1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200db1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200db2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200db2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200db3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200db3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200db4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200db4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200db5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200db5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200db6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200db6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200db7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200db7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200db8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200db8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200db9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200db9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dba RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dba NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dbb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dbb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dbc RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dbc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dbd RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dbd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dbe RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dbe NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dbf RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dbf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dc0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dc0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dc1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dc1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dc2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dc2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dc3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dc3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dc4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dc4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dc5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dc5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dc6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dc6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dc7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dc7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dc8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dc8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dc9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dc9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dca RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dca NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dcb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dcb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dcc RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dcc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dcd RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dcd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dce RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dce NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dcf RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dcf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dd0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dd0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dd1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dd1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dd2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dd2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dd3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dd3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dd4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dd4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dd5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dd5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dd6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dd6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dd7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dd7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dd8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dd8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dd9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dd9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dda RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dda NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ddb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ddb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ddc RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ddc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ddd RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ddd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dde RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dde NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ddf RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ddf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200de0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200de0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200de1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200de1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200de2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200de2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200de3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200de3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200de4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200de4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200de5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200de5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200de6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200de6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200de7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200de7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200de8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200de8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200de9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200de9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dea RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dea NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200deb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200deb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dec RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dec NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ded RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ded NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dee RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dee NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200def RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200def NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200df0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200df0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200df1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200df1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200df2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200df2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200df3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200df3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200df4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200df4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200df5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200df5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200df6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200df6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200df7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200df7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200df8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200df8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200df9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200df9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dfa RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dfa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dfb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dfb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dfc RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dfc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dfd RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dfd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dfe RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dfe NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200dff RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200dff NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e00 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e00 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e01 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e01 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e02 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e02 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e03 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e03 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e04 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e04 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e05 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e05 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e06 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e06 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e07 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e07 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e08 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e08 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e09 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e09 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e0a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e0a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e0b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e0b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e0c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e0c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e0d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e0d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e0e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e0e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e0f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e0f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e10 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e10 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e11 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e11 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e12 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e12 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e13 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e13 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e14 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e14 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e15 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e15 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e16 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e16 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e17 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e17 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e18 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e18 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e19 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e19 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e1a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e1a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e1b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e1b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e1c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e1c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e1d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e1d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e1e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e1e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e1f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e1f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e20 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e20 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e21 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e21 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e22 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e22 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e23 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e23 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e24 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e24 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e25 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e25 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e26 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e26 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e27 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e27 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e28 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e28 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e29 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e29 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e2a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e2a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e2b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e2b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e2c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e2c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e2d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e2d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e2e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e2e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e2f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e2f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e30 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e30 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e31 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e31 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e32 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e32 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e33 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e33 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e34 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e34 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e35 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e35 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e36 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e36 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e37 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e37 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e38 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e38 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e39 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e39 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e3a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e3a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e3b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e3b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e3c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e3c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e3d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e3d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e3e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e3e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e3f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e3f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e40 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e40 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e41 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e41 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e42 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e42 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e43 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e43 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e44 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e44 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e45 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e45 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e46 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e46 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e47 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e47 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e48 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e48 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e49 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e49 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e4a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e4a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e4b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e4b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e4c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e4c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e4d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e4d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e4e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e4e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e4f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e4f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e50 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e50 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e51 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e51 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e52 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e52 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e53 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e53 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e54 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e54 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e55 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e55 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e56 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e56 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e57 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e57 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e58 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e58 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e59 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e59 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e5a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e5a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e5b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e5b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e5c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e5c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e5d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e5d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e5e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e5e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e5f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e5f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e60 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e60 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e61 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e61 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e62 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e62 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e63 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e63 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e64 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e64 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e65 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e65 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e66 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e66 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e67 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e67 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e68 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e68 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e69 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e69 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e6a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e6a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e6b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e6b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e6c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e6c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e6d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e6d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e6e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e6e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e6f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e6f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e70 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e70 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e71 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e71 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e72 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e72 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e73 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e73 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e74 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e74 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e75 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e75 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e76 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e76 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e77 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e77 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e78 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e78 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e79 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e79 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e7a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e7a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e7b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e7b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e7c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e7c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e7d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e7d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e7e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e7e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e7f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e7f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e80 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e80 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e81 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e81 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e82 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e82 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e83 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e83 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e84 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e84 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e85 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e85 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e86 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e86 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e87 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e87 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e88 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e88 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e89 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e89 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e8a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e8a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e8b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e8b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e8c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e8c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e8d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e8d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e8e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e8e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e8f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e8f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e90 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e90 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e91 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e91 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e92 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e92 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e93 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e93 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e94 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e94 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e95 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e95 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e96 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e96 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e97 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e97 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e98 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e98 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e99 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e99 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e9a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e9a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e9b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e9b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e9c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e9c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e9d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e9d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e9e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e9e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200e9f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200e9f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ea0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ea0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ea1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ea1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ea2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ea2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ea3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ea3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ea4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ea4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ea5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ea5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ea6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ea6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ea7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ea7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ea8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ea8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ea9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ea9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200eaa RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200eaa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200eab RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200eab NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200eac RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200eac NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ead RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ead NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200eae RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200eae NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200eaf RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200eaf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200eb0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200eb0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200eb1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200eb1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200eb2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200eb2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200eb3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200eb3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200eb4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200eb4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200eb5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200eb5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200eb6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200eb6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200eb7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200eb7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200eb8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200eb8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200eb9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200eb9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200eba RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200eba NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ebb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ebb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ebc RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ebc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ebd RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ebd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ebe RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ebe NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ebf RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ebf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ec0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ec0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ec1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ec1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ec2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ec2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ec3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ec3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ec4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ec4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ec5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ec5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ec6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ec6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ec7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ec7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ec8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ec8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ec9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ec9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200eca RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200eca NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ecb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ecb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ecc RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ecc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ecd RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ecd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ece RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ece NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ecf RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ecf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ed0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ed0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ed1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ed1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ed2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ed2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ed3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ed3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ed4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ed4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ed5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ed5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ed6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ed6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ed7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ed7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ed8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ed8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ed9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ed9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200eda RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200eda NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200edb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200edb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200edc RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200edc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200edd RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200edd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ede RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ede NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200edf RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200edf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ee0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ee0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ee1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ee1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ee2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ee2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ee3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ee3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ee4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ee4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ee5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ee5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ee6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ee6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ee7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ee7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ee8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ee8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ee9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ee9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200eea RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200eea NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200eeb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200eeb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200eec RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200eec NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200eed RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200eed NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200eee RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200eee NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200eef RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200eef NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ef0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ef0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ef1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ef1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ef2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ef2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ef3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ef3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ef4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ef4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ef5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ef5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ef6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ef6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ef7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ef7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ef8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ef8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ef9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ef9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200efa RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200efa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200efb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200efb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200efc RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200efc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200efd RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200efd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200efe RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200efe NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200eff RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200eff NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f00 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f00 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f01 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f01 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f02 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f02 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f03 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f03 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f04 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f04 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f05 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f05 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f06 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f06 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f07 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f07 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f08 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f08 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f09 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f09 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f0a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f0a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f0b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f0b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f0c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f0c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f0d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f0d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f0e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f0e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f0f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f0f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f10 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f10 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f11 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f11 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f12 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f12 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f13 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f13 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f14 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f14 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f15 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f15 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f16 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f16 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f17 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f17 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f18 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f18 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f19 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f19 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f1a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f1a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f1b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f1b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f1c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f1c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f1d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f1d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f1e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f1e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f1f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f1f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f20 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f20 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f21 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f21 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f22 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f22 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f23 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f23 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f24 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f24 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f25 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f25 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f26 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f26 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f27 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f27 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f28 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f28 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f29 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f29 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f2a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f2a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f2b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f2b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f2c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f2c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f2d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f2d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f2e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f2e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f2f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f2f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f30 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f30 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f31 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f31 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f32 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f32 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f33 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f33 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f34 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f34 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f35 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f35 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f36 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f36 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f37 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f37 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f38 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f38 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f39 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f39 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f3a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f3a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f3b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f3b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f3c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f3c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f3d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f3d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f3e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f3e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f3f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f3f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f40 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f40 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f41 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f41 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f42 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f42 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f43 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f43 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f44 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f44 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f45 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f45 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f46 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f46 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f47 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f47 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f48 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f48 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f49 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f49 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f4a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f4a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f4b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f4b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f4c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f4c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f4d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f4d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f4e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f4e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f4f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f4f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f50 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f50 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f51 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f51 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f52 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f52 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f53 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f53 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f54 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f54 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f55 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f55 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f56 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f56 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f57 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f57 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f58 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f58 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f59 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f59 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f5a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f5a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f5b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f5b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f5c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f5c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f5d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f5d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f5e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f5e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f5f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f5f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f60 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f60 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f61 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f61 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f62 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f62 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f63 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f63 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f64 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f64 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f65 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f65 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f66 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f66 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f67 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f67 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f68 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f68 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f69 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f69 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f6a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f6a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f6b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f6b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f6c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f6c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f6d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f6d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f6e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f6e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f6f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f6f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f70 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f70 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f71 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f71 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f72 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f72 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f73 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f73 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f74 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f74 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f75 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f75 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f76 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f76 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f77 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f77 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f78 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f78 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f79 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f79 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f7a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f7a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f7b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f7b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f7c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f7c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f7d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f7d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f7e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f7e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f7f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f7f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f80 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f80 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f81 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f81 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f82 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f82 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f83 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f83 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f84 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f84 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f85 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f85 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f86 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f86 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f87 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f87 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f88 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f88 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f89 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f89 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f8a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f8a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f8b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f8b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f8c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f8c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f8d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f8d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f8e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f8e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f8f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f8f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f90 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f90 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f91 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f91 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f92 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f92 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f93 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f93 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f94 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f94 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f95 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f95 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f96 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f96 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f97 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f97 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f98 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f98 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f99 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f99 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f9a RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f9a NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f9b RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f9b NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f9c RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f9c NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f9d RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f9d NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f9e RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f9e NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200f9f RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200f9f NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fa0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fa0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fa1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fa1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fa2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fa2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fa3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fa3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fa4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fa4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fa5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fa5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fa6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fa6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fa7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fa7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fa8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fa8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fa9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fa9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200faa RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200faa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fab RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fab NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fac RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fac NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fad RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fad NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fae RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fae NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200faf RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200faf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fb0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fb0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fb1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fb1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fb2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fb2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fb3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fb3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fb4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fb4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fb5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fb5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fb6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fb6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fb7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fb7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fb8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fb8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fb9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fb9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fba RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fba NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fbb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fbb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fbc RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fbc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fbd RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fbd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fbe RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fbe NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fbf RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fbf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fc0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fc0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fc1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fc1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fc2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fc2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fc3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fc3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fc4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fc4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fc5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fc5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fc6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fc6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fc7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fc7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fc8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fc8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fc9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fc9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fca RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fca NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fcb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fcb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fcc RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fcc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fcd RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fcd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fce RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fce NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fcf RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fcf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fd0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fd0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fd1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fd1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fd2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fd2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fd3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fd3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fd4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fd4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fd5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fd5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fd6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fd6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fd7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fd7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fd8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fd8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fd9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fd9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fda RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fda NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fdb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fdb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fdc RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fdc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fdd RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fdd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fde RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fde NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fdf RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fdf NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fe0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fe0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fe1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fe1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fe2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fe2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fe3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fe3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fe4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fe4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fe5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fe5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fe6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fe6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fe7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fe7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fe8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fe8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fe9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fe9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fea RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fea NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200feb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200feb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fec RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fec NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fed RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fed NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fee RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fee NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fef RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fef NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ff0 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ff0 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ff1 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ff1 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ff2 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ff2 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ff3 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ff3 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ff4 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ff4 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ff5 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ff5 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ff6 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ff6 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ff7 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ff7 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ff8 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ff8 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ff9 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ff9 NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ffa RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ffa NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ffb RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ffb NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ffc RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ffc NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ffd RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ffd NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200ffe RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200ffe NOP + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200fff RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200fff NOP +Emulation terminated with status 0xffffffff, flags: 0x1, 4096 NOPs + SHEMU_FLAG_NOP_SLED diff --git a/bdshemu_test/basic/test_64_selfwrite01 b/bdshemu_test/basic/test_64_selfwrite01 new file mode 100644 index 0000000000000000000000000000000000000000..ba8e4f97978fa5b5e4d24be8876dec058a4c9def GIT binary patch literal 16 Xcmeb1HRWJnVDRYtzQ*9hs>2fiDc%Nr literal 0 HcmV?d00001 diff --git a/bdshemu_test/basic/test_64_selfwrite01.asm b/bdshemu_test/basic/test_64_selfwrite01.asm new file mode 100644 index 0000000..e4e9755 --- /dev/null +++ b/bdshemu_test/basic/test_64_selfwrite01.asm @@ -0,0 +1,12 @@ + + bits 64 + + lea rsi, [rel _xxx] + mov rdi, rsi + lodsb + xor al, cl + stosb + retn + +_xxx: + nop \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_selfwrite01.result b/bdshemu_test/basic/test_64_selfwrite01.result new file mode 100644 index 0000000..afe9669 --- /dev/null +++ b/bdshemu_test/basic/test_64_selfwrite01.result @@ -0,0 +1,37 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 LEA rsi, [rel 0x20000f] + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x000000000020000f RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200007 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200007 MOV rdi, rsi + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x000000000020000f RDI = 0x000000000020000f + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000a LODSB + RAX = 0x0000000000000090 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000200010 RDI = 0x000000000020000f + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000b XOR al, cl + RAX = 0x0000000000000090 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000200010 RDI = 0x000000000020000f + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000d RFLAGS = 0x0000000000000286 +Emulating: 0x000000000020000d STOSB + RAX = 0x0000000000000090 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000200010 RDI = 0x0000000000200010 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000e RFLAGS = 0x0000000000000286 +Emulating: 0x000000000020000e RETN +Emulation terminated with status 0x00000002, flags: 0x0, 0 NOPs diff --git a/bdshemu_test/basic/test_64_selfwrite02 b/bdshemu_test/basic/test_64_selfwrite02 new file mode 100644 index 0000000000000000000000000000000000000000..e2eec5baa041aa64e08c4b7a5d0b2dd303c668d1 GIT binary patch literal 16 Xcmeb1HDzaDVDRYtzQ*9hstJbyDV_#< literal 0 HcmV?d00001 diff --git a/bdshemu_test/basic/test_64_selfwrite02.asm b/bdshemu_test/basic/test_64_selfwrite02.asm new file mode 100644 index 0000000..bff96f7 --- /dev/null +++ b/bdshemu_test/basic/test_64_selfwrite02.asm @@ -0,0 +1,12 @@ + + bits 64 + + lea rsi, [rel _xxx] + mov rdi, rsi + lodsb + xor al, cl + stosb + +_xxx: + nop + retn \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_selfwrite02.result b/bdshemu_test/basic/test_64_selfwrite02.result new file mode 100644 index 0000000..5e57f79 --- /dev/null +++ b/bdshemu_test/basic/test_64_selfwrite02.result @@ -0,0 +1,44 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 LEA rsi, [rel 0x20000e] + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x000000000020000e RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200007 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200007 MOV rdi, rsi + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x000000000020000e RDI = 0x000000000020000e + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000a LODSB + RAX = 0x0000000000000090 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x000000000020000f RDI = 0x000000000020000e + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000b XOR al, cl + RAX = 0x0000000000000090 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x000000000020000f RDI = 0x000000000020000e + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000d RFLAGS = 0x0000000000000286 +Emulating: 0x000000000020000d STOSB + RAX = 0x0000000000000090 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x000000000020000f RDI = 0x000000000020000f + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000e RFLAGS = 0x0000000000000286 +Emulating: 0x000000000020000e NOP + RAX = 0x0000000000000090 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x000000000020000f RDI = 0x000000000020000f + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000f RFLAGS = 0x0000000000000286 +Emulating: 0x000000000020000f RETN +Emulation terminated with status 0x00000002, flags: 0x4, 1 NOPs + SHEMU_FLAG_WRITE_SELF diff --git a/bdshemu_test/basic/test_64_selfwrite03 b/bdshemu_test/basic/test_64_selfwrite03 new file mode 100644 index 0000000000000000000000000000000000000000..6c13d5fe74451b52e62c68b0cb49b10158341206 GIT binary patch literal 27 Ycmeb1RTXAnVDQ*60SW?uJTN#60CUv`p#T5? literal 0 HcmV?d00001 diff --git a/bdshemu_test/basic/test_64_selfwrite03.asm b/bdshemu_test/basic/test_64_selfwrite03.asm new file mode 100644 index 0000000..5082060 --- /dev/null +++ b/bdshemu_test/basic/test_64_selfwrite03.asm @@ -0,0 +1,10 @@ + + bits 64 + + lea rsp, [rel _xxx + 8] + mov rax, 0x9090909090909090 + push rax + +_xxx: + dq 0 + retn \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_selfwrite03.result b/bdshemu_test/basic/test_64_selfwrite03.result new file mode 100644 index 0000000..2229b67 --- /dev/null +++ b/bdshemu_test/basic/test_64_selfwrite03.result @@ -0,0 +1,74 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 LEA rsp, [rel 0x20001a] + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x000000000020001a RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200007 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200007 MOV rax, 0x9090909090909090 + RAX = 0x9090909090909090 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x000000000020001a RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200011 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200011 PUSH rax + RAX = 0x9090909090909090 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000200012 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200012 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200012 NOP + RAX = 0x9090909090909090 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000200012 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200013 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200013 NOP + RAX = 0x9090909090909090 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000200012 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200014 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200014 NOP + RAX = 0x9090909090909090 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000200012 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200015 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200015 NOP + RAX = 0x9090909090909090 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000200012 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200016 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200016 NOP + RAX = 0x9090909090909090 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000200012 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200017 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200017 NOP + RAX = 0x9090909090909090 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000200012 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200018 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200018 NOP + RAX = 0x9090909090909090 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000200012 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200019 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200019 NOP + RAX = 0x9090909090909090 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000200012 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020001a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020001a RETN +Emulation terminated with status 0x00000002, flags: 0x4, 8 NOPs + SHEMU_FLAG_WRITE_SELF diff --git a/bdshemu_test/basic/test_64_string b/bdshemu_test/basic/test_64_string new file mode 100644 index 0000000000000000000000000000000000000000..b1cb77a524a44cf54ca7f7c581187b2658e45de9 GIT binary patch literal 172 zcmeb1HH~0kVDRX*Ed)|afMBUd^E(cY=Jy;sS%4y+J(ha(nwmnC_yH-ylb@GCWFVBm zflupzx`TmII~f=m7(o0TAcp3N|0fOuX)s`d(#%jAWHbn{LMR3{D9sL~IiPf6UZO%` MQK~|2YEdc!0EXctXaE2J literal 0 HcmV?d00001 diff --git a/bdshemu_test/basic/test_64_string.asm b/bdshemu_test/basic/test_64_string.asm new file mode 100644 index 0000000..580f919 --- /dev/null +++ b/bdshemu_test/basic/test_64_string.asm @@ -0,0 +1,44 @@ + + bits 64 + + lea rsi, [rel _xxx] + lea rdi, [rel _yyy] + + movsb + movsb + movsb + movsb + movsd + + sub rsi, 8 + sub rdi, 8 + mov ecx, 4 + rep movsq + + lea rsi, [rel _xxx] + lea rdi, [rel _yyy] + xor ecx, ecx + repz cmpsb + + mov ecx, 4 + repz cmpsb + + mov ecx, 4 + xor al, al + repnz scasb + + lea rdi, [rel _zzz] + mov ecx, 0x100 + xor al, al + repnz scasb + mov eax, 0x100 + sub eax, ecx + dec eax + + retn +_xxx: + dq 1, 2, 3, 4 +_yyy: + dq 5, 6, 7, 8 +_zzz: + db 'ana are mere',0 \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_string.result b/bdshemu_test/basic/test_64_string.result new file mode 100644 index 0000000..bb4eec0 --- /dev/null +++ b/bdshemu_test/basic/test_64_string.result @@ -0,0 +1,169 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 LEA rsi, [rel 0x20005f] + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x000000000020005f RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200007 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200007 LEA rdi, [rel 0x20007f] + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x000000000020005f RDI = 0x000000000020007f + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000e RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000e MOVSB + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000200060 RDI = 0x0000000000200080 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000f RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020000f MOVSB + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000200061 RDI = 0x0000000000200081 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200010 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200010 MOVSB + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000200062 RDI = 0x0000000000200082 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200011 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200011 MOVSB + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000200063 RDI = 0x0000000000200083 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200012 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200012 MOVSD + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000200067 RDI = 0x0000000000200087 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200013 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200013 SUB rsi, 0x08 + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x000000000020005f RDI = 0x0000000000200087 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200017 RFLAGS = 0x0000000000000206 +Emulating: 0x0000000000200017 SUB rdi, 0x08 + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x000000000020005f RDI = 0x000000000020007f + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020001b RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020001b MOV ecx, 0x00000004 + RAX = 0x0000000000000000 RCX = 0x0000000000000004 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x000000000020005f RDI = 0x000000000020007f + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200020 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200020 REP MOVSQ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x000000000020007f RDI = 0x000000000020009f + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200023 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200023 LEA rsi, [rel 0x20005f] + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x000000000020005f RDI = 0x000000000020009f + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020002a RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020002a LEA rdi, [rel 0x20007f] + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x000000000020005f RDI = 0x000000000020007f + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200031 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200031 XOR ecx, ecx + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x000000000020005f RDI = 0x000000000020007f + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200033 RFLAGS = 0x0000000000000246 +Emulating: 0x0000000000200033 REPZ CMPSB + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x000000000020005f RDI = 0x000000000020007f + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200035 RFLAGS = 0x0000000000000246 +Emulating: 0x0000000000200035 MOV ecx, 0x00000004 + RAX = 0x0000000000000000 RCX = 0x0000000000000004 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x000000000020005f RDI = 0x000000000020007f + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020003a RFLAGS = 0x0000000000000246 +Emulating: 0x000000000020003a REPZ CMPSB + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000200063 RDI = 0x0000000000200083 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020003c RFLAGS = 0x0000000000000246 +Emulating: 0x000000000020003c MOV ecx, 0x00000004 + RAX = 0x0000000000000000 RCX = 0x0000000000000004 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000200063 RDI = 0x0000000000200083 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200041 RFLAGS = 0x0000000000000246 +Emulating: 0x0000000000200041 XOR al, al + RAX = 0x0000000000000000 RCX = 0x0000000000000004 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000200063 RDI = 0x0000000000200083 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200043 RFLAGS = 0x0000000000000246 +Emulating: 0x0000000000200043 REPNZ SCASB + RAX = 0x0000000000000000 RCX = 0x0000000000000003 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000200063 RDI = 0x0000000000200084 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200045 RFLAGS = 0x0000000000000246 +Emulating: 0x0000000000200045 LEA rdi, [rel 0x20009f] + RAX = 0x0000000000000000 RCX = 0x0000000000000003 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000200063 RDI = 0x000000000020009f + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020004c RFLAGS = 0x0000000000000246 +Emulating: 0x000000000020004c MOV ecx, 0x00000100 + RAX = 0x0000000000000000 RCX = 0x0000000000000100 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000200063 RDI = 0x000000000020009f + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200051 RFLAGS = 0x0000000000000246 +Emulating: 0x0000000000200051 XOR al, al + RAX = 0x0000000000000000 RCX = 0x0000000000000100 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000200063 RDI = 0x000000000020009f + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200053 RFLAGS = 0x0000000000000246 +Emulating: 0x0000000000200053 REPNZ SCASB + RAX = 0x0000000000000000 RCX = 0x00000000000000f3 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000200063 RDI = 0x00000000002000ac + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200055 RFLAGS = 0x0000000000000246 +Emulating: 0x0000000000200055 MOV eax, 0x00000100 + RAX = 0x0000000000000100 RCX = 0x00000000000000f3 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000200063 RDI = 0x00000000002000ac + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020005a RFLAGS = 0x0000000000000246 +Emulating: 0x000000000020005a SUB eax, ecx + RAX = 0x000000000000000d RCX = 0x00000000000000f3 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000200063 RDI = 0x00000000002000ac + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020005c RFLAGS = 0x0000000000000202 +Emulating: 0x000000000020005c DEC eax + RAX = 0x000000000000000c RCX = 0x00000000000000f3 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000200063 RDI = 0x00000000002000ac + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020005e RFLAGS = 0x0000000000000206 +Emulating: 0x000000000020005e RETN +Emulation terminated with status 0x00000002, flags: 0x0, 0 NOPs diff --git a/bdshemu_test/basic/test_64_sys01 b/bdshemu_test/basic/test_64_sys01 new file mode 100644 index 0000000..b688912 --- /dev/null +++ b/bdshemu_test/basic/test_64_sys01 @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_sys01.asm b/bdshemu_test/basic/test_64_sys01.asm new file mode 100644 index 0000000..c92e97e --- /dev/null +++ b/bdshemu_test/basic/test_64_sys01.asm @@ -0,0 +1,4 @@ + + bits 64 + + syscall \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_sys01.result b/bdshemu_test/basic/test_64_sys01.result new file mode 100644 index 0000000..bd359a2 --- /dev/null +++ b/bdshemu_test/basic/test_64_sys01.result @@ -0,0 +1,8 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 SYSCALL +Emulation terminated with status 0x0000000a, flags: 0x10, 0 NOPs + SHEMU_FLAG_SYSCALL diff --git a/bdshemu_test/basic/test_64_sys02 b/bdshemu_test/basic/test_64_sys02 new file mode 100644 index 0000000..9fe1505 --- /dev/null +++ b/bdshemu_test/basic/test_64_sys02 @@ -0,0 +1 @@ +̀ \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_sys02.asm b/bdshemu_test/basic/test_64_sys02.asm new file mode 100644 index 0000000..a93f1bd --- /dev/null +++ b/bdshemu_test/basic/test_64_sys02.asm @@ -0,0 +1,4 @@ + + bits 64 + + int 0x80 \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_sys02.result b/bdshemu_test/basic/test_64_sys02.result new file mode 100644 index 0000000..2550bc2 --- /dev/null +++ b/bdshemu_test/basic/test_64_sys02.result @@ -0,0 +1,8 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 INT 0x80 +Emulation terminated with status 0x0000000a, flags: 0x10, 0 NOPs + SHEMU_FLAG_SYSCALL diff --git a/bdshemu_test/basic/test_64_sys03 b/bdshemu_test/basic/test_64_sys03 new file mode 100644 index 0000000..741d907 --- /dev/null +++ b/bdshemu_test/basic/test_64_sys03 @@ -0,0 +1 @@ +3 \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_sys03.asm b/bdshemu_test/basic/test_64_sys03.asm new file mode 100644 index 0000000..5d53f66 --- /dev/null +++ b/bdshemu_test/basic/test_64_sys03.asm @@ -0,0 +1,4 @@ + + bits 64 + + int 0x33 \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_sys03.result b/bdshemu_test/basic/test_64_sys03.result new file mode 100644 index 0000000..8642484 --- /dev/null +++ b/bdshemu_test/basic/test_64_sys03.result @@ -0,0 +1,7 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 INT 0x33 +Emulation terminated with status 0x0000000a, flags: 0x0, 0 NOPs diff --git a/bdshemu_test/test_all.py b/bdshemu_test/test_all.py new file mode 100644 index 0000000..adc7482 --- /dev/null +++ b/bdshemu_test/test_all.py @@ -0,0 +1,56 @@ +# +# Copyright (c) 2020 Bitdefender +# SPDX-License-Identifier: Apache-2.0 +# +import os +import sys +import glob + +total_tests = 0 +failed_tests = 0 + +def test_dir(dir): + global total_tests + global failed_tests + + for f in glob.glob('%s\\*' % dir): + if -1 == f.find('.'): + if 0 < f.find('_16'): + mod = '-b16' + elif 0 < f.find('_32'): + mod = '-b32' + else: + mod = '-b64' + if 0 < f.find('_r0'): + mod += ' -k' + + print(' * Running test case %s...' % f) + os.system('disasm -shemu %s -f %s >%s.temp' % (mod, f, f)) + try: + res = open('%s.result' % f).read() + except: + print(' ! No result file provided for test %s!' % f) + + try: + tmp = open('%s.temp' % f).read() + except: + print(' ! No result produced by test %s!' % f) + + total_tests += 1 + if res != tmp: + print(' **** FAILED! ****') + failed_tests += 1 + else: + print(' * Passed.') + + for f in glob.glob('%s\\*_decoded.bin' % dir): + os.remove(f) + for f in glob.glob('%s\\*.temp' % dir): + os.remove(f) + +for dn in glob.glob("*"): + if not os.path.isdir(dn): + continue + print('Testing %s...' % dn) + test_dir(dn) +print("Ran %d tests, %d failed" % (total_tests, failed_tests)) \ No newline at end of file diff --git a/disasmtool/disasmtool.c b/disasmtool/disasmtool.c new file mode 100644 index 0000000..85a4132 --- /dev/null +++ b/disasmtool/disasmtool.c @@ -0,0 +1,1922 @@ +/* + * Copyright (c) 2020 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include +#include + +typedef uint64_t QWORD, *PQWORD; + +// Main disasm header file. +#include "bdshemu\bdshemu.h" +#include "bddisasm.h" + + +#define PAGE_SIZE 0x1000 +#define PAGE_MASK 0xFFFFFFFFFFFFF000 + +typedef struct _DISASM_OPTIONS +{ + uint8_t *Buffer; // The buffer containing the instructions. + size_t Size; // Buffer size. + size_t Offset; // Offset inside the buffer. + size_t Rip; // Virtual RIP. + char *Target; // If in search mode, this indicates the instruction to be searched for. + BOOLEAN Highlight; // Highlight instruction components, if true. + BOOLEAN ExtendedInfo; // Display extended instruction info, if true. + BOOLEAN Stats; // Display disassembly stats (clocks / instruction, instructions / second), if true. + BOOLEAN Search; // Search for the Target instruction in the provided buffer. + BOOLEAN Print; // Print instruction disassembly, if true. + uint8_t Mode; // Mode - 16, 32 or 64 bit mode. + uint8_t Ring; // Ring - 0, 1, 2 or 3. + uint8_t Vendor; // Proffered vendor. + char *FileName; // Input file, if any. + size_t ShemuRegs[REG_R15 + 1]; + BOOLEAN UseShemuRegs; +} DISASM_OPTIONS, *PDISASM_OPTIONS; + +char *gSpaces[16] = +{ + "", + " ", + " ", + " ", + " ", + " ", + " ", + " ", + " ", + " ", + " ", + " ", + " ", + " ", + " ", + " ", +}; + + +// +// nd_vsnprintf +// +int nd_vsnprintf_s( + char *buffer, + size_t sizeOfBuffer, + size_t count, + const char *format, + va_list argptr + ) +{ + return _vsnprintf_s(buffer, sizeOfBuffer, count, format, argptr); +} + +void* nd_memset(void *s, int c, size_t n) +{ + return memset(s, c, n); +} + + +// +// set_to_string +// +const char* set_to_string( + __in ND_INS_SET Set + ) +{ + switch (Set) + { + case ND_SET_3DNOW: return "3DNOW"; + case ND_SET_ADX: return "ADX"; + case ND_SET_AES: return "AES"; + case ND_SET_AMD: return "AMD"; + case ND_SET_AMXBF16: return "AMX-BF16"; + case ND_SET_AMXINT8: return "AMX-INT8"; + case ND_SET_AMXTILE: return "AMX-TILE"; + case ND_SET_AVX: return "AVX"; + case ND_SET_AVX2: return "AVX2"; + case ND_SET_AVX2GATHER: return "AVX2GATHER"; + case ND_SET_AVX5124FMAPS: return "AVX5124FMAPS"; + case ND_SET_AVX5124VNNIW: return "AVX5124VNNIW"; + case ND_SET_AVX512BF16: return "AVX512BF16"; + case ND_SET_AVX512BITALG: return "AVX512BITALG"; + case ND_SET_AVX512BW: return "AVX512BW"; + case ND_SET_AVX512CD: return "AVX512CD"; + case ND_SET_AVX512DQ: return "AVX512DQ"; + case ND_SET_AVX512ER: return "AVX512ER"; + case ND_SET_AVX512F: return "AVX512F"; + case ND_SET_AVX512IFMA: return "AVX512IFMA"; + case ND_SET_AVX512PF: return "AVX512PF"; + case ND_SET_AVX512VBMI: return "AVX512VBMI"; + case ND_SET_AVX512VBMI2: return "AVX512VBMI2"; + case ND_SET_AVX512VNNI: return "AVX512VNNI"; + case ND_SET_AVX512VP2INTERSECT: return "AVX512VP2INTERSECT"; + case ND_SET_AVX512VPOPCNTDQ: return "AVX512VPOPCNTDQ"; + case ND_SET_BMI1: return "BMI1"; + case ND_SET_BMI2: return "BMI2"; + case ND_SET_CET: return "CET"; + case ND_SET_CLDEMOTE: return "CLDEMOTE"; + case ND_SET_CLFSH: return "CLFSH"; + case ND_SET_CLFSHOPT: return "CLFSHOPT"; + case ND_SET_CLWB: return "CLWB"; + case ND_SET_CLZERO: return "CLZERO"; + case ND_SET_CMPXCHG16B: return "CMPXCHG16B"; + case ND_SET_CYRIX: return "CYRIX"; + case ND_SET_CYRIX_SMM: return "CYRIX_SMM"; + case ND_SET_ENQCMD: return "ENQCMD"; + case ND_SET_F16C: return "F16C"; + case ND_SET_FMA: return "FMA"; + case ND_SET_FMA4: return "FMA4"; + case ND_SET_FXSAVE: return "FXSAVE"; + case ND_SET_GFNI: return "GFNI"; + case ND_SET_I186: return "I186"; + case ND_SET_I286PROT: return "I286PROT"; + case ND_SET_I286REAL: return "I286REAL"; + case ND_SET_I386: return "I386"; + case ND_SET_I486: return "I486"; + case ND_SET_I486REAL: return "I486REAL"; + case ND_SET_I64: return "I64"; + case ND_SET_I86: return "I86"; + case ND_SET_INVPCID: return "INVPCID"; + case ND_SET_INVLPGB: return "INVLPGB"; + case ND_SET_LONGMODE: return "LONGMODE"; + case ND_SET_LWP: return "LWP"; + case ND_SET_LZCNT: return "LZCNT"; + case ND_SET_MCOMMIT: return "MCOMMIT"; + case ND_SET_MMX: return "MMX"; + case ND_SET_MOVBE: return "MOVBE"; + case ND_SET_MOVDIR64B: return "MOVDIR64B"; + case ND_SET_MOVDIRI: return "MOVDIRI"; + case ND_SET_MPX: return "MPX"; + case ND_SET_MWAITT: return "MWAITT"; + case ND_SET_PAUSE: return "PAUSE"; + case ND_SET_PCLMULQDQ: return "PCLMULQDQ"; + case ND_SET_PCOMMIT: return "PCOMMIT"; + case ND_SET_PCONFIG: return "PCONFIG"; + case ND_SET_PENTIUMREAL: return "PENTIUMREAL"; + case ND_SET_PKU: return "PKU"; + case ND_SET_POPCNT: return "POPCNT"; + case ND_SET_PPRO: return "PPRO"; + case ND_SET_PREFETCH_NOP: return "PREFETCH_NOP"; + case ND_SET_PTWRITE: return "PTWRITE"; + case ND_SET_RDPID: return "RDPID"; + case ND_SET_RDPMC: return "RDPMC"; + case ND_SET_RDPRU: return "RDPRU"; + case ND_SET_RDRAND: return "RDRAND"; + case ND_SET_RDSEED: return "RDSEED"; + case ND_SET_RDTSCP: return "RDTSCP"; + case ND_SET_RDWRFSGS: return "RDWRFSGS"; + case ND_SET_SCC: return "SCC"; + case ND_SET_SERIALIZE: return "SERIALIZE"; + case ND_SET_SGX: return "SGX"; + case ND_SET_SHA: return "SHA"; + case ND_SET_SMAP: return "SMAP"; + case ND_SET_SMX: return "SMX"; + case ND_SET_SNP: return "SNP"; + case ND_SET_SSE: return "SSE"; + case ND_SET_SSE2: return "SSE2"; + case ND_SET_SSE3: return "SSE3"; + case ND_SET_SSE4: return "SSE4"; + case ND_SET_SSE42: return "SSE42"; + case ND_SET_SSE4A: return "SSE4A"; + case ND_SET_SSSE3: return "SSSE3"; + case ND_SET_SVM: return "SVM"; + case ND_SET_TBM: return "TBM"; + case ND_SET_TSX: return "TSX"; + case ND_SET_TSXLDTRK: return "TSXLDTRK"; + case ND_SET_UD: return "UD"; + case ND_SET_UNKNOWN: return "UNKNOWN"; + case ND_SET_VAES: return "VAES"; + case ND_SET_VPCLMULQDQ: return "VPCLMULQDQ"; + case ND_SET_VTX: return "VTX"; + case ND_SET_WAITPKG: return "WAITPKG"; + case ND_SET_WBNOINVD: return "WBNOINVD"; + case ND_SET_X87: return "X87"; + case ND_SET_XOP: return "XOP"; + case ND_SET_XSAVE: return "XSAVE"; + case ND_SET_XSAVEC: return "XSAVEC"; + case ND_SET_XSAVES: return "XSAVES"; + default: return "???"; + } +} + + +// +// category_to_string +// +const char* category_to_string( + __in ND_INS_CATEGORY Category + ) +{ + switch (Category) + { + case ND_CAT_3DNOW: return "3DNOW"; + case ND_CAT_AES: return "AES"; + case ND_CAT_ARITH: return "ARITH"; + case ND_CAT_AMX: return "AMX"; + case ND_CAT_AVX: return "AVX"; + case ND_CAT_AVX2: return "AVX2"; + case ND_CAT_AVX2GATHER: return "AVX2GATHER"; + case ND_CAT_AVX512: return "AVX512"; + case ND_CAT_AVX512BF16: return "AVX512BF16"; + case ND_CAT_AVX512VBMI: return "AVX512VBMI"; + case ND_CAT_AVX512VP2INTERSECT: return "AVX512VP2INTERSECT"; + case ND_CAT_BITBYTE: return "BITBYTE"; + case ND_CAT_BLEND: return "BLEND"; + case ND_CAT_BMI1: return "BMI1"; + case ND_CAT_BMI2: return "BMI2"; + case ND_CAT_BROADCAST: return "BROADCAST"; + case ND_CAT_CALL: return "CALL"; + case ND_CAT_CET: return "CET"; + case ND_CAT_CLDEMOTE: return "CLDEMOTE"; + case ND_CAT_CMOV: return "CMOV"; + case ND_CAT_COMPRESS: return "COMPRESS"; + case ND_CAT_COND_BR: return "COND_BR"; + case ND_CAT_CONFLICT: return "CONFLICT"; + case ND_CAT_CONVERT: return "CONVERT"; + case ND_CAT_DATAXFER: return "DATAXFER"; + case ND_CAT_DECIMAL: return "DECIMAL"; + case ND_CAT_ENQCMD: return "ENQCMD"; + case ND_CAT_EXPAND: return "EXPAND"; + case ND_CAT_FLAGOP: return "FLAGOP"; + case ND_CAT_FMA4: return "FMA4"; + case ND_CAT_GATHER: return "GATHER"; + case ND_CAT_GFNI: return "GFNI"; + case ND_CAT_I386: return "I386"; + case ND_CAT_IFMA: return "IFMA"; + case ND_CAT_INTERRUPT: return "INTERRUPT"; + case ND_CAT_IO: return "IO"; + case ND_CAT_IOSTRINGOP: return "IOSTRINGOP"; + case ND_CAT_KMASK: return "KMASK"; + case ND_CAT_KNL: return "KNL"; + case ND_CAT_LOGIC: return "LOGIC"; + case ND_CAT_LOGICAL: return "LOGICAL"; + case ND_CAT_LOGICAL_FP: return "LOGICAL_FP"; + case ND_CAT_LWP: return "LWP"; + case ND_CAT_LZCNT: return "LZCNT"; + case ND_CAT_MISC: return "MISC"; + case ND_CAT_MMX: return "MMX"; + case ND_CAT_MOVDIR64B: return "MOVDIR64B"; + case ND_CAT_MOVDIRI: return "MOVDIRI"; + case ND_CAT_MPX: return "MPX"; + case ND_CAT_NOP: return "NOP"; + case ND_CAT_PADLOCK: return "PADLOCK"; + case ND_CAT_PCLMULQDQ: return "PCLMULQDQ"; + case ND_CAT_PCONFIG: return "PCONFIG"; + case ND_CAT_POP: return "POP"; + case ND_CAT_PREFETCH: return "PREFETCH"; + case ND_CAT_PTWRITE: return "PTWRITE"; + case ND_CAT_PUSH: return "PUSH"; + case ND_CAT_RDPID: return "RDPID"; + case ND_CAT_RDRAND: return "RDRAND"; + case ND_CAT_RDSEED: return "RDSEED"; + case ND_CAT_RDWRFSGS: return "RDWRFSGS"; + case ND_CAT_RET: return "RET"; + case ND_CAT_ROTATE: return "ROTATE"; + case ND_CAT_SCATTER: return "SCATTER"; + case ND_CAT_SEGOP: return "SEGOP"; + case ND_CAT_SEMAPHORE: return "SEMAPHORE"; + case ND_CAT_SGX: return "SGX"; + case ND_CAT_SHA: return "SHA"; + case ND_CAT_SHIFT: return "SHIFT"; + case ND_CAT_SMAP: return "SMAP"; + case ND_CAT_SSE: return "SSE"; + case ND_CAT_SSE2: return "SSE2"; + case ND_CAT_STRINGOP: return "STRINGOP"; + case ND_CAT_STTNI: return "STTNI"; + case ND_CAT_SYSCALL: return "SYSCALL"; + case ND_CAT_SYSRET: return "SYSRET"; + case ND_CAT_SYSTEM: return "SYSTEM"; + case ND_CAT_UD: return "UD"; + case ND_CAT_UNCOND_BR: return "UNCOND_BR"; + case ND_CAT_UNDOC: return "UNDOC"; + case ND_CAT_UNKNOWN: return "UNKNOWN"; + case ND_CAT_VAES: return "VAES"; + case ND_CAT_VFMA: return "VFMA"; + case ND_CAT_VFMAPS: return "VFMAPS"; + case ND_CAT_VNNI: return "VNNI"; + case ND_CAT_VNNIW: return "VNNIW"; + case ND_CAT_VPCLMULQDQ: return "VPCLMULQDQ"; + case ND_CAT_VPOPCNT: return "VPOPCNT"; + case ND_CAT_VTX: return "VTX"; + case ND_CAT_WAITPKG: return "WAITPKG"; + case ND_CAT_WBNOINVD: return "WBNOINVD"; + case ND_CAT_WIDENOP: return "WIDENOP"; + case ND_CAT_X87_ALU: return "X87_ALU"; + case ND_CAT_XOP: return "XOP"; + case ND_CAT_XSAVE: return "XSAVE"; + default: return "???"; + } +} + + +// +// optype_to_string +// +const char* optype_to_string( + __in ND_OPERAND_TYPE OpType + ) +{ + switch (OpType) + { + case ND_OP_REG: return "Register"; + case ND_OP_IMM: return "Immediate"; + case ND_OP_CONST: return "Constant"; + case ND_OP_MEM: return "Memory"; + case ND_OP_ADDR: return "Address"; + case ND_OP_OFFS: return "Offset"; + case ND_OP_BANK: return "Bank"; + default: return "???"; + } +} + + +// +// regtype_to_string +// +const char* regtype_to_string( + __in ND_REG_TYPE RegType + ) +{ + switch (RegType) + { + case ND_REG_GPR: return "General Purpose"; + case ND_REG_SEG: return "Segment"; + case ND_REG_FPU: return "FP"; + case ND_REG_MMX: return "MMX"; + case ND_REG_SSE: return "Vector"; + case ND_REG_BND: return "Bound"; + case ND_REG_MSK: return "Mask"; + case ND_REG_TILE: return "Tile"; + case ND_REG_SYS: return "System"; + case ND_REG_MSR: return "Model Specific"; + case ND_REG_XCR: return "Extended Control"; + case ND_REG_CR: return "Control"; + case ND_REG_DR: return "Debug"; + case ND_REG_TR: return "Test"; + case ND_REG_MXCSR: return "MXCSR"; + case ND_REG_PKRU: return "PKRU"; + case ND_REG_SSP: return "SSP"; + case ND_REG_FLG: return "Flags"; + case ND_REG_RIP: return "IP"; + default: return "???"; + } +} + + +// +// encoding_to_string +// +const char* encoding_to_string( + __in ND_OPERAND_ENCODING Encoding + ) +{ + switch (Encoding) + { + case ND_OPE_R: return "R"; + case ND_OPE_M: return "M"; + case ND_OPE_V: return "V"; + case ND_OPE_O: return "O"; + case ND_OPE_I: return "I"; + case ND_OPE_D: return "D"; + case ND_OPE_C: return "C"; + case ND_OPE_1: return "1"; + case ND_OPE_A: return "A"; + case ND_OPE_L: return "L"; + case ND_OPE_E: return "E"; + case ND_OPE_S: return "S"; + default: return ""; + } +} + + +// +// tuple_to_string +// +const char *tuple_to_string( + __in ND_TUPLE Tuple + ) +{ + switch (Tuple) + { + case ND_TUPLE_FV: return "Full"; + case ND_TUPLE_HV: return "Half"; + case ND_TUPLE_FVM: return "Full Mem"; + case ND_TUPLE_HVM: return "Half Mem"; + case ND_TUPLE_QVM: return "Quarter Mem"; + case ND_TUPLE_OVM: return "Eigth Mem"; + case ND_TUPLE_T1S: return "Tuple 1 Scalar"; + case ND_TUPLE_T1F: return "Tuple 1 Fixes"; + case ND_TUPLE_T2: return "Tuple 2"; + case ND_TUPLE_T4: return "Tuple 4"; + case ND_TUPLE_T8: return "Tuple 8"; + case ND_TUPLE_M128: return "Mem 128"; + case ND_TUPLE_DUP: return "MOVDDUP"; + case ND_TUPLE_T1S8: return "Tuple 1 scalar, 8 bit"; + case ND_TUPLE_T1S16: return "Tuple 1 scalar, 16 bit"; + case ND_TUPLE_T1_4X: return "Tuple 4 x 32 bit"; + default: return "None"; + } +} + + +// +// exception_to_string +// +const char *exception_evex_to_string( + __in ND_EX_TYPE_EVEX ExClass + ) +{ + switch (ExClass) + { + case ND_EXT_E1: return "E1"; + case ND_EXT_E1NF: return "E1NF"; + case ND_EXT_E2: return "E2"; + case ND_EXT_E3: return "E3"; + case ND_EXT_E3NF: return "E3NF"; + case ND_EXT_E4: return "E4"; + case ND_EXT_E4nb: return "E4.nb"; + case ND_EXT_E4NF: return "E4NF"; + case ND_EXT_E4NFnb: return "E4NF.nb"; + case ND_EXT_E5: return "E5"; + case ND_EXT_E5NF: return "E5NF"; + case ND_EXT_E6: return "E6"; + case ND_EXT_E6NF: return "E6NF"; + case ND_EXT_E7NM: return "E7NM"; + case ND_EXT_E9: return "E9"; + case ND_EXT_E9NF: return "E9NF"; + case ND_EXT_E10: return "E10"; + case ND_EXT_E10NF: return "E10NF"; + case ND_EXT_E11: return "E11"; + case ND_EXT_E12: return "E12"; + case ND_EXT_E12NP: return "E12NP"; + default: return "None"; + } +} + + +// +// hex_to_bin +// +BYTE hex_to_bin( + __in char HexByte + ) +{ + if ((HexByte >= '0') && (HexByte <= '9')) + { + return HexByte - '0'; + } + else if ((HexByte >= 'A') && (HexByte <= 'F')) + { + return HexByte - 'A' + 10; + } + else if ((HexByte >= 'a') && (HexByte <= 'f')) + { + return HexByte - 'a' + 10; + } + + return 0; +} + + +// +// str_strip +// Copies the InputString in OutputString, while eliminating the characters specified in Tokens +// +VOID str_strip( + __in char* InString, + __in DWORD LenInString, + __in char* Tokens, + __in DWORD LenTokString, + __out char* OutString, + __in DWORD CapOutString // capacity of out string including null character +) +{ + DWORD lenInStr, lenOutStr, lenTokStr; + DWORD itInStr = 0, itTokStr = 0; + lenTokStr = 0; + lenOutStr = 0; + + if ((NULL == InString) || (NULL == Tokens) || (NULL == OutString)) + { + return; + } + + lenInStr = (DWORD)strnlen_s(InString, ND_MIN_BUF_SIZE); + lenTokStr = (DWORD)strnlen_s(Tokens, ND_MIN_BUF_SIZE); + + lenInStr = (lenInStr > LenInString) ? LenInString : lenInStr; + lenTokStr = (lenTokStr > LenTokString) ? LenTokString : lenTokStr; + + + if ((0 == lenInStr) || (0 == lenTokStr)) + { + return; + } + + for (itInStr = 0; itInStr < lenInStr; itInStr++) + { + BOOLEAN found = FALSE; + for (itTokStr = 0; itTokStr < lenTokStr; itTokStr++) + { + if (InString[itInStr] == Tokens[itTokStr]) + { + found = TRUE; + break; + } + } + + if (!found) + { + // not enough space, bail out + if (lenOutStr >= CapOutString - 1) + { + return; + } + + OutString[lenOutStr] = InString[itInStr]; + lenOutStr++; + } + } +} + + +// +// regstr_to_idx +// +INT32 regstr_to_idx( + __in const char* Reg + ) +{ + static const char* reg64[] = + { + "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" + }; + + for (INT32 i = 0; i < ARRAYSIZE(reg64); i++) + { + if (!_stricmp(Reg, reg64[i])) + { + return i; + } + } + + return -1; +} + + +// +// match_gpr +// +BOOLEAN +match_gpr( + __in const char* Arg, + __in DWORD* Index + ) +{ + if (Arg[0] == '-') + { + INT32 idx = regstr_to_idx(Arg + 1); // this will be the name of the register or the NULL terminator + if (idx >= 0) + { + *Index = idx; + return TRUE; + } + } + + return FALSE; +} + +// +// print_instruction +// +void +print_instruction( + __in SIZE_T Rip, + __in PINSTRUX Instrux, + __in PDISASM_OPTIONS Options + ) +{ + char instruxText[ND_MIN_BUF_SIZE]; + DWORD k = 0, idx = 0, i = 0; + + printf("%p ", (void*)(Rip)); + + if (Options->Highlight) + { + // Display prefixes. + SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), + FOREGROUND_BLUE | FOREGROUND_GREEN | FOREGROUND_RED | FOREGROUND_INTENSITY); + for (idx = 0; idx < Instrux->PrefLength; idx++, k++) + { + printf("%02x", Instrux->InstructionBytes[k]); + } + SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), + FOREGROUND_BLUE | FOREGROUND_GREEN | FOREGROUND_RED); + + // Display opcodes. + SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), + FOREGROUND_GREEN | FOREGROUND_INTENSITY); + for (idx = 0; idx < (DWORD)(ND_IS_3DNOW(Instrux) ? Instrux->OpLength - 1 : Instrux->OpLength); idx++, k++) + { + printf("%02x", Instrux->InstructionBytes[k]); + } + SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), + FOREGROUND_BLUE | FOREGROUND_GREEN | FOREGROUND_RED); + + // Display modrm and sib. + SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), + FOREGROUND_GREEN | FOREGROUND_RED | FOREGROUND_INTENSITY); + for (idx = 0; idx < (DWORD)(Instrux->HasModRm + Instrux->HasSib); idx++, k++) + { + printf("%02x", Instrux->InstructionBytes[k]); + } + SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), + FOREGROUND_BLUE | FOREGROUND_GREEN | FOREGROUND_RED); + + // Display displacement. + SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), + FOREGROUND_BLUE | FOREGROUND_INTENSITY); + + for (idx = 0; idx < (DWORD)(Instrux->DispLength); idx++, k++) + { + printf("%02x", Instrux->InstructionBytes[k]); + } + SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), + FOREGROUND_BLUE | FOREGROUND_GREEN | FOREGROUND_RED); + + // Display relative offset/moffset/immediates. + SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), + FOREGROUND_RED | FOREGROUND_INTENSITY); + for (idx = 0; idx < (DWORD)(Instrux->Imm1Length + Instrux->Imm2Length + + Instrux->RelOffsLength + Instrux->MoffsetLength + + Instrux->HasSseImm + Instrux->AddrLength); idx++, k++) + { + printf("%02x", Instrux->InstructionBytes[k]); + } + SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), + FOREGROUND_BLUE | FOREGROUND_GREEN | FOREGROUND_RED); + + if (ND_IS_3DNOW(Instrux)) + { + SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), + FOREGROUND_GREEN | FOREGROUND_INTENSITY); + for (; k < Instrux->Length; k++) + { + printf("%02x", Instrux->InstructionBytes[k]); + } + SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), + FOREGROUND_BLUE | FOREGROUND_GREEN | FOREGROUND_RED); + } + } + + for (; k < Instrux->Length; k++) + { + printf("%02x", Instrux->InstructionBytes[k]); + } + + printf("%s", gSpaces[16 - Instrux->Length]); + + NdToText(Instrux, Rip, ND_MIN_BUF_SIZE, instruxText); + + printf("%s\n", instruxText); + + if (Options->ExtendedInfo) + { + const BYTE opsize[3] = { 2, 4, 8 }; + const BYTE adsize[3] = { 2, 4, 8 }; + const BYTE veclen[3] = { 16, 32, 64 }; + + printf(" DSIZE: %2d, ASIZE: %2d, VLEN: ", opsize[Instrux->EfOpMode] * 8, adsize[Instrux->AddrMode] * 8); + + if (ND_HAS_VECTOR(Instrux)) + { + printf("%2d\n", veclen[Instrux->VecMode] * 8); + } + else + { + printf("-\n"); + } + + printf(" ISA Set: %s, Ins cat: %s, CET tracked: %s\n", + set_to_string(Instrux->IsaSet), category_to_string(Instrux->Category), + Instrux->IsCetTracked ? "yes" : "no"); + + if (0 != Instrux->CpuidFlag.Flag) + { + char *regs[4] = { "eax", "ecx", "edx", "ebx" }; + + printf(" CPUID leaf: 0x%08x", Instrux->CpuidFlag.Leaf); + + if (Instrux->CpuidFlag.SubLeaf != ND_CFF_NO_SUBLEAF) + { + printf(", sub-leaf: 0x%08x", Instrux->CpuidFlag.SubLeaf); + } + + printf(", reg: %s, bit: %d\n", regs[Instrux->CpuidFlag.Reg], Instrux->CpuidFlag.Bit); + } + + if (Instrux->HasEvex) + { + printf(" EVEX Tuple Type: %s\n", + tuple_to_string(Instrux->TupleType)); + } + + if (Instrux->ExceptionClass != ND_EXC_None) + { + printf(" Exception class: %s, ", + Instrux->ExceptionClass == ND_EXC_SSE_AVX ? "SSE/VEX" : + Instrux->ExceptionClass == ND_EXC_EVEX ? "EVEX" : + Instrux->ExceptionClass == ND_EXC_OPMASK ? "Opmask" : + Instrux->ExceptionClass == ND_EXC_AMX ? "AMX" : "???"); + + switch (Instrux->ExceptionClass) + { + case ND_EXC_SSE_AVX: + printf("exception type: %d\n", Instrux->ExceptionType); + break; + case ND_EXC_EVEX: + printf("exception type: %s\n", exception_evex_to_string(Instrux->ExceptionType)); + break; + case ND_EXC_OPMASK: + printf("exception type: K%d\n", Instrux->ExceptionType + 19); + break; + case ND_EXC_AMX: + printf("exception type: AMX-E%d\n", Instrux->ExceptionType); + break; + default: + printf("exception type: ???\n"); + break; + } + } + + if (Instrux->FlagsAccess.RegAccess != 0) + { + DWORD fidx, all; + BOOLEAN individual = FALSE; + char *flags[22] = { "CF", NULL, "PF", NULL, "AF", NULL, "ZF", "SF", "TF", "IF", "DF", + "OF", "IOPL",NULL, "NT", NULL, "RF", "VM", "AC", "VIF", "VIP", "ID" }; + + all = Instrux->FlagsAccess.Tested.Raw | Instrux->FlagsAccess.Modified.Raw | Instrux->FlagsAccess.Set.Raw | + Instrux->FlagsAccess.Cleared.Raw | Instrux->FlagsAccess.Undefined.Raw; + printf(" FLAGS access\n "); + + for (fidx = 0; fidx < 21; fidx++) + { + if (flags[fidx] != NULL) + { + if (0 == (all & (1ULL << fidx))) + { + continue; + } + + individual = TRUE; + + printf("%s: ", flags[fidx]); + + if (Instrux->FlagsAccess.Tested.Raw & (1ULL << fidx)) + { + printf("t"); + } + + if (Instrux->FlagsAccess.Modified.Raw & (1ULL << fidx)) + { + printf("m"); + } + + if (Instrux->FlagsAccess.Set.Raw & (1ULL << fidx)) + { + printf("1"); + } + + if (Instrux->FlagsAccess.Cleared.Raw & (1ULL << fidx)) + { + printf("0"); + } + + if (Instrux->FlagsAccess.Undefined.Raw & (1ULL << fidx)) + { + printf("u"); + } + + printf(", "); + } + } + + if (!individual) + { + printf("Entire register"); + } + + printf("\n"); + } + + if (Instrux->IsaSet == ND_SET_X87) + { +#define FPU_FLG_ACC_TO_STR(x) ((x) == ND_FPU_FLAG_UNDEFINED ? "u" : \ + (x) == ND_FPU_FLAG_MODIFIED ? "m" : (x) == ND_FPU_FLAG_SET_0 ? "0" : "1") + + printf(" FPU flags access\n C0: %s, C1: %s, C2: %s, C3: %s, \n", + FPU_FLG_ACC_TO_STR(Instrux->FpuFlagsAccess.C0), FPU_FLG_ACC_TO_STR(Instrux->FpuFlagsAccess.C1), + FPU_FLG_ACC_TO_STR(Instrux->FpuFlagsAccess.C2), FPU_FLG_ACC_TO_STR(Instrux->FpuFlagsAccess.C3)); + } + + printf(" Valid modes\n" + " R0: %s, R1: %s, R2: %s, R3: %s\n" + " Real: %s, V8086: %s, Prot: %s, Compat: %s, Long: %s\n" + " SMM: %s, SGX: %s, TSX: %s, VMXRoot: %s, VMXNonRoot: %s\n", + Instrux->ValidModes.Ring0 ? "yes" : "no", + Instrux->ValidModes.Ring1 ? "yes" : "no", + Instrux->ValidModes.Ring2 ? "yes" : "no", + Instrux->ValidModes.Ring3 ? "yes" : "no", + Instrux->ValidModes.Real ? "yes" : "no", + Instrux->ValidModes.V8086 ? "yes" : "no", + Instrux->ValidModes.Protected ? "yes" : "no", + Instrux->ValidModes.Compat ? "yes" : "no", + Instrux->ValidModes.Long ? "yes" : "no", + Instrux->ValidModes.Smm ? "yes" : "no", + Instrux->ValidModes.Sgx ? "yes" : "no", + Instrux->ValidModes.Tsx ? "yes" : "no", + Instrux->ValidModes.VmxRoot ? "yes" : "no", + Instrux->ValidModes.VmxNonRoot ? "yes" : "no" + ); + + printf(" Valid prefixes\n" + " REP: %s, REPcc: %s, LOCK: %s\n" + " HLE: %s, XACQUIRE only: %s, XRELEASE only: %s\n" + " BND: %s, BHINT: %s, DNT: %s\n", + Instrux->ValidPrefixes.Rep ? "yes" : "no", + Instrux->ValidPrefixes.RepCond ? "yes" : "no", + Instrux->ValidPrefixes.Lock ? "yes" : "no", + Instrux->ValidPrefixes.Hle ? "yes" : "no", + Instrux->ValidPrefixes.Xacquire ? "yes" : "no", + Instrux->ValidPrefixes.Xrelease ? "yes" : "no", + Instrux->ValidPrefixes.Bnd ? "yes" : "no", + Instrux->ValidPrefixes.Bhint ? "yes" : "no", + Instrux->ValidPrefixes.Dnt ? "yes" : "no" + ); + + for (i = 0; i < Instrux->OperandsCount; i++) + { + printf(" Operand: %d, Acc: %s, Type: %10s, Size: %2d, RawSize: %2d, Encoding: %s", i, + Instrux->Operands[i].Access.Read && Instrux->Operands[i].Access.Write ? "RW" : + Instrux->Operands[i].Access.Write ? "-W" : Instrux->Operands[i].Access.Read ? "R-" : "--", + optype_to_string(Instrux->Operands[i].Type), Instrux->Operands[i].Size, + Instrux->Operands[i].RawSize, encoding_to_string(Instrux->Operands[i].Encoding) + ); + + if (ND_OP_MEM == Instrux->Operands[i].Type) + { + printf(", "); + + if (Instrux->Operands[i].Info.Memory.IsRipRel) + { + printf("RIP relative: yes, "); + } + + if (Instrux->Operands[i].Info.Memory.IsAG) + { + printf("Address Generator: yes, "); + } + + if (Instrux->Operands[i].Info.Memory.IsBitbase) + { + printf("Bitbase Addressing: yes, "); + } + + if (Instrux->Operands[i].Info.Memory.IsMib) + { + printf("MIB Addressing: yes, "); + } + + if (Instrux->Operands[i].Info.Memory.IsVsib) + { + printf("VSIB Addressing: yes, "); + } + + if (Instrux->Operands[i].Info.Memory.IsSibMem) + { + printf("Sibmem Addressing: yes, "); + } + + if (Instrux->Operands[i].Info.Memory.IsStack) + { + printf("Stack: yes, "); + } + + if (Instrux->Operands[i].Info.Memory.IsString) + { + printf("String: yes, "); + } + + if (Instrux->Operands[i].Info.Memory.IsShadowStack) + { + printf("Shadow Stack: yes, "); + } + + if (Instrux->Operands[i].Info.Memory.HasCompDisp) + { + printf("Compressed displacement: yes, "); + } + + if (Instrux->Operands[i].Info.Memory.HasBroadcast) + { + printf("Broadcast: yes, "); + } + + printf("\n "); + + if (Instrux->Operands[i].Info.Memory.HasSeg) + { + printf("Segment: %d, ", Instrux->Operands[i].Info.Memory.Seg); + } + + if (Instrux->Operands[i].Info.Memory.HasBase) + { + printf("Base: %d, ", Instrux->Operands[i].Info.Memory.Base); + } + + if (Instrux->Operands[i].Info.Memory.HasIndex) + { + printf("Index: %d * %d, ", + Instrux->Operands[i].Info.Memory.Index, Instrux->Operands[i].Info.Memory.Scale); + } + + if (Instrux->Operands[i].Info.Memory.HasDisp) + { + printf("Displacement: 0x%016llx, ", Instrux->Operands[i].Info.Memory.Disp); + } + + if (Instrux->Operands[i].Info.Memory.IsVsib) + { + printf("\n "); + printf("VSIB index size: %d, VSIB element size: %d, VSIB element count: %d", + Instrux->Operands[i].Info.Memory.Vsib.IndexSize, + Instrux->Operands[i].Info.Memory.Vsib.ElemSize, + Instrux->Operands[i].Info.Memory.Vsib.ElemCount); + } + } + + if (ND_OP_REG == Instrux->Operands[i].Type) + { + printf(", RegType: %16s, RegSize: %2d, RegId: %d, RegCount: %d\n", + regtype_to_string(Instrux->Operands[i].Info.Register.Type), + Instrux->Operands[i].Info.Register.Size, + Instrux->Operands[i].Info.Register.Reg, + Instrux->Operands[i].Info.Register.Count); + } + else + { + printf("\n"); + } + + if (Instrux->Operands[i].Decorator.HasBroadcast) + { + printf(" Decorator: Broadcast %d bytes element %d times\n", + Instrux->Operands[i].Decorator.Broadcast.Size, + Instrux->Operands[i].Decorator.Broadcast.Count); + } + + if (Instrux->Operands[i].Decorator.HasMask) + { + printf(" Decorator: Mask k%d\n", Instrux->Operands[i].Decorator.Mask.Msk); + } + + if (Instrux->Operands[i].Decorator.HasZero) + { + printf(" Decorator: Zero (no merging)\n"); + } + } + + printf("\n"); + } +} + + +// +// handle_search +// +void +handle_search( + __in PDISASM_OPTIONS Options + ) +{ + NDSTATUS status; + INSTRUX instrux; + SIZE_T rip = 0, i; + char text[ND_MIN_BUF_SIZE], target[ND_MIN_BUF_SIZE]; + char *token1, *token2, *ctx1, *ctx2; + BOOLEAN match; + + // Disassemble + rip = 0; + while (rip < Options->Size) + { + status = NdDecodeEx2(&instrux, Options->Buffer + rip, Options->Size - rip, Options->Mode, + Options->Mode, Options->Mode, ND_VEND_ANY); + if (!ND_SUCCESS(status)) + { + goto _continue; + } + + NdToText(&instrux, rip, ND_MIN_BUF_SIZE, text); + + // Copy the target. + memcpy(target, Options->Target, ND_MIN_BUF_SIZE); + for (i = 0; i < ND_MIN_BUF_SIZE; i++) + { + if (target[i] == ',') + { + target[i] = ' '; + } + + if (text[i] == ',') + { + text[i] = ' '; + } + } + + _strlwr_s(target, ND_MIN_BUF_SIZE); + _strlwr_s(text, ND_MIN_BUF_SIZE); + + // Try to match. + token1 = strtok_s(target, " ", &ctx1); + token2 = strtok_s(text, " ", &ctx2); + + match = TRUE; + + while (token1 && token2) + { + if (0 == strcmp(token1, "*")) + { + goto _continue_match; + } + + if (strlen(token1) != strlen(token2)) + { + match = FALSE; + break; + } + + for (i = 0; i < strlen(token1); i++) + { + if ((token1[i] != '?') && (token1[i] != token2[i])) + { + match = FALSE; + break; + } + } + + if (!match) + { + break; + } + +_continue_match: + token1 = strtok_s(NULL, " ", &ctx1); + token2 = strtok_s(NULL, " ", &ctx2); + } + + // Unfinished token - leave. + if (token1 || token2) + { + goto _continue; + } + + if (match) + { + SIZE_T rip2 = rip, count = 0; + + print_instruction(rip, &instrux, Options); + rip2 += instrux.Length; + + while (rip2 < Options->Size && count++ < 8) + { + status = NdDecodeEx2(&instrux, Options->Buffer + rip2, Options->Size - rip2, Options->Mode, + Options->Mode, Options->Mode, ND_VEND_ANY); + if (!ND_SUCCESS(status)) + { + printf("%p ERROR\n", (void*)rip2); + rip2++; + } + else + { + print_instruction(rip2, &instrux, Options); + rip2 += instrux.Length; + } + } + + printf("-----------------------------------------------------------------------\n"); + } + +_continue: + rip++; + } +} + + + +// +// handle_disasm +// +void +handle_disasm( + __in PDISASM_OPTIONS Options + ) +{ + NDSTATUS status; + INSTRUX instrux; + QWORD icount = 0, istart = 0, iend = 0, start = 0, end = 0, itotal = 0; + SIZE_T rip = 0, fsize = Options->Size; + PBYTE buffer = Options->Buffer; + BYTE mode = Options->Mode, vend = Options->Vendor; + + start = clock(); + + // Disassemble + rip = Options->Offset; + while (rip < Options->Size) + { + icount++; + + istart = __rdtsc(); + status = NdDecodeEx2(&instrux, buffer + rip, fsize - rip, mode, mode, mode, vend); + iend = __rdtsc(); + + itotal += iend - istart; + if (!ND_SUCCESS(status)) + { + if (Options->Print) + { + printf("%p ", (void*)(rip + Options->Rip)); + + printf("%02x", buffer[rip]); + + printf("%s", gSpaces[16 - 1]); + + printf("db 0x%02x (0x%08x)\n", buffer[rip], status); + } + + rip++; + } + else + { + if (Options->Print) + { + print_instruction(rip + Options->Rip, &instrux, Options); + } + + rip += instrux.Length; + } + } + + end = clock(); + + if (Options->Stats) + { + printf("Disassembled %lld instructions in %lldms, %4.4f instructions/second, %4.6f clocks/instruction\n", + icount, end - start, icount / (double)(end - start) * 1000, itotal / (double)icount); + } +} + + +// +// set_shemuctx_file +// +void set_shemuctx_file( + __in const char *FileName, + __in DISASM_OPTIONS *Options + ) +{ + HANDLE hFile; + DWORD fileSize; + BOOL readFileSuccess; + PCHAR fileBuf = NULL; + DWORD bytesRead; + + PCHAR lineStart, lineToken, ctx, lineBufCtx; + char lineBuf[ND_MIN_BUF_SIZE] = { 0 }; + INT32 regIdx; + QWORD regVal; + + // pre-init + hFile = INVALID_HANDLE_VALUE; + fileSize = 0; + regIdx = 0; + regVal = 0; + ctx = lineBufCtx = NULL; + + if ((NULL == FileName) || (NULL == Options)) + { + goto cleanup_and_exit; + } + + hFile = CreateFileA(FileName, GENERIC_READ, FILE_SHARE_READ, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL); + if (INVALID_HANDLE_VALUE == hFile) + { + goto cleanup_and_exit; + } + + fileSize = GetFileSize(hFile, NULL); + if (INVALID_FILE_SIZE == fileSize) + { + goto cleanup_and_exit; + } + + fileBuf = (PCHAR)VirtualAlloc(NULL, fileSize + 3ull, MEM_RESERVE | MEM_COMMIT, PAGE_READWRITE); + if (NULL == fileBuf) + { + goto cleanup_and_exit; + } + + readFileSuccess = ReadFile(hFile, fileBuf, fileSize, &bytesRead, NULL); + if (!readFileSuccess) + { + printf("ReadFile failed: GLA: %x\n", GetLastError()); + goto cleanup_and_exit; + } + + lineStart = strtok_s(fileBuf, "\r\n", &ctx); + while (lineStart) + { + char regStr[ND_MIN_BUF_SIZE] = { 0 }; + char valStr[ND_MIN_BUF_SIZE] = { 0 }; + BOOLEAN isRip = FALSE; + + if (0 == strnlen_s(lineStart, ND_MIN_BUF_SIZE)) + { + goto next_line; + } + strcpy_s(lineBuf, ND_MIN_BUF_SIZE, lineStart); + + lineToken = strtok_s(lineBuf, ":", &lineBufCtx); + if (NULL == lineToken) + { + goto next_line; + } + + str_strip(lineToken, (DWORD)strnlen_s(lineToken, ND_MIN_BUF_SIZE), " ,\"", + (DWORD)strnlen_s(" ,\"", ND_MIN_BUF_SIZE), regStr, ND_MIN_BUF_SIZE); + + // first element is the register + regIdx = regstr_to_idx(regStr); + if (regIdx < 0 || regIdx >= ARRAYSIZE(Options->ShemuRegs)) + { + if (!_stricmp(regStr, "rip")) + { + isRip = TRUE; + } + else + { + printf("Corrupt line: %s\n", lineStart); + goto next_line; + } + } + + // second element is the value + lineToken = strtok_s(NULL, ":", &lineBufCtx); + if ((NULL == lineToken)) + { + printf("Corrupt line: %s\n", lineStart); + goto next_line; + } + + str_strip(lineToken, (DWORD)strnlen_s(lineToken, ND_MIN_BUF_SIZE), " ,\"", + (DWORD)strnlen_s(" ,\"", ND_MIN_BUF_SIZE), valStr, ND_MIN_BUF_SIZE); + regVal = strtoull(valStr, NULL, 0); + + if (!isRip) + { + Options->ShemuRegs[regIdx] = (size_t)regVal; + } + else + { + Options->Rip = (size_t)regVal; + } + + next_line: + lineStart = strtok_s(NULL, "\r\n", &ctx); + memset(lineBuf, 0, ND_MIN_BUF_SIZE); + } + +cleanup_and_exit: + if (INVALID_HANDLE_VALUE != hFile) + { + CloseHandle(hFile); + } + if (NULL != fileBuf) + { + VirtualFree(fileBuf, 0, MEM_RELEASE); + } + +} + +void ShemuLog(PCHAR data) +{ + printf("%s", data); +} + +bool ShemuAccessMem(PSHEMU_CONTEXT Ctx, uint64_t Gla, size_t Size, uint8_t *Buffer, bool Store) +{ + UNREFERENCED_PARAMETER(Ctx); + UNREFERENCED_PARAMETER(Gla); + + if (!Store) + { + // On loads, always return 0. + memset(Buffer, 0, Size); + } + else + { + // On stores, do nothing. + } + + return true; +} + +// +// handle_shemu +// +void +handle_shemu( + PDISASM_OPTIONS Options + ) +{ + SHEMU_CONTEXT ctx; + SHEMU_STATUS shstatus; + char *fileName; + HANDLE hFile; + DWORD outSize; + SIZE_T rip = 0, fsize = Options->Size, offset = 0, decFileNameLength = 0, shellSize; + char *fNameDecoded; + PBYTE buffer = Options->Buffer; + + memset(&ctx, 0, sizeof(ctx)); + rip = Options->Rip; + fileName = Options->FileName; + + if (fileName == NULL) + { + decFileNameLength = strlen("hex_string_decoded.bin") + 1; + fNameDecoded = (char *)malloc(sizeof(char) * decFileNameLength); + } + else + { + decFileNameLength = strlen(fileName) + strlen("_decoded.bin") + 1; + fNameDecoded = (char *)malloc(sizeof(char) * decFileNameLength); + + } + if (NULL == fNameDecoded) + { + printf("Could not allocate file name.\n"); + } + else + { + if (fileName == NULL) + { + sprintf_s(fNameDecoded, decFileNameLength, "hex_string_decoded.bin"); + } + else + { + sprintf_s(fNameDecoded, decFileNameLength, "%s_decoded.bin", fileName); + } + } + + if (Options->Offset < PAGE_SIZE) + { + offset = Options->Offset; + } + + // A little extra space, since shellcodes tend to do accesses after their code... + shellSize = fsize + 0x100; + + // Allocate the shellcode, stack, shell bitmap and stack bitmaps. + ctx.Shellcode = malloc(shellSize); + if (NULL == ctx.Shellcode) + { + printf("Memory error: couldn't allocated %zu bytes!\n", fsize); + free(fNameDecoded); + return; + } + +#define STACK_SIZE 0x2000 + + ctx.Stack = malloc(STACK_SIZE); + if (NULL == ctx.Stack) + { + printf("Memory error: couldn't allocated %zu bytes!\n", fsize); + free(fNameDecoded); + return; + } + + ctx.Intbuf = malloc(shellSize + STACK_SIZE); + if (NULL == ctx.Intbuf) + { + printf("Memory error: couldn't allocated %zu bytes!\n", fsize); + free(fNameDecoded); + return; + } + + memset(ctx.Shellcode, 0, shellSize); + memset(ctx.Stack, 0, STACK_SIZE); + memcpy((BYTE *)ctx.Shellcode, (BYTE *)buffer, fsize); + memset(ctx.Intbuf, 0, shellSize + STACK_SIZE); + + ctx.ShellcodeBase = (rip != 0 ? rip & PAGE_MASK : 0x200000); + ctx.ShellcodeSize = (DWORD)shellSize; + ctx.StackBase = 0x100000; + ctx.StackSize = STACK_SIZE; + ctx.Registers.RegRsp = 0x101000; + ctx.IntbufSize = (DWORD)shellSize + STACK_SIZE; + + ctx.Registers.RegFlags = REG_RFLAG_IF | 2; + ctx.Registers.RegRip = ctx.ShellcodeBase + offset; + + ctx.Segments.Cs.Selector = 0x10; + ctx.Segments.Ds.Selector = 0x28; + ctx.Segments.Es.Selector = 0x28; + ctx.Segments.Ss.Selector = 0x28; + ctx.Segments.Fs.Selector = 0x30; + ctx.Segments.Fs.Base = 0x7FFF0000; + ctx.Segments.Gs.Selector = 0x30; + ctx.Segments.Gs.Base = 0x7FFF0000; + + // Dummy values, to resemble regular CR0/CR4 values. + ctx.Registers.RegCr0 = 0x0000000080050031; + ctx.Registers.RegCr4 = 0x0000000000170678; + + ctx.Mode = Options->Mode; + ctx.Ring = Options->Ring; + ctx.TibBase = Options->Mode == ND_CODE_32 ? ctx.Segments.Fs.Base : ctx.Segments.Gs.Base; + ctx.MaxInstructionsCount = 4096; + ctx.Flags = 0; + ctx.Options = SHEMU_OPT_TRACE_EMULATION; + ctx.Log = &ShemuLog; + ctx.AccessMemory = &ShemuAccessMem; + + // Configurable thresholds. + ctx.NopThreshold = SHEMU_DEFAULT_NOP_THRESHOLD; + ctx.StrThreshold = SHEMU_DEFAULT_STR_THRESHOLD; + ctx.MemThreshold = SHEMU_DEFAULT_MEM_THRESHOLD; + + if (Options->UseShemuRegs) + { + // Copy the new GPRs + memcpy(&ctx.Registers.RegRax, Options->ShemuRegs, sizeof(Options->ShemuRegs)); + + // Update the stack to point to the new RSP, if one exists + if (ctx.Registers.RegRsp != 0) + { + // Consider the stack base at least with a page before the current RSP. In case of pushes or operations + // which decrease the RSP, we will always give SHEMU_ABORT_BRANCH_OUTSIDE otherwise. + ctx.StackBase = ctx.Registers.RegRsp - 0x1000; + } + } + + shstatus = ShemuEmulate(&ctx); + + printf("Emulation terminated with status 0x%08x, flags: 0x%llx, %d NOPs\n", shstatus, ctx.Flags, ctx.NopCount); + if (ctx.Flags & SHEMU_FLAG_NOP_SLED) + { + printf(" SHEMU_FLAG_NOP_SLED\n"); + } + if (ctx.Flags & SHEMU_FLAG_LOAD_RIP) + { + printf(" SHEMU_FLAG_LOAD_RIP\n"); + } + if (ctx.Flags & SHEMU_FLAG_WRITE_SELF) + { + printf(" SHEMU_FLAG_WRITE_SELF\n"); + } + if (ctx.Flags & SHEMU_FLAG_TIB_ACCESS) + { + printf(" SHEMU_FLAG_TIB_ACCESS\n"); + } + if (ctx.Flags & SHEMU_FLAG_SYSCALL) + { + printf(" SHEMU_FLAG_SYSCALL\n"); + } + if (ctx.Flags & SHEMU_FLAG_STACK_STR) + { + printf(" SHEMU_FLAG_STACK_STR\n"); + } + if (ctx.Flags & SHEMU_FLAG_KPCR_ACCESS) + { + printf(" SHEMU_FLAG_KPCR_ACCESS\n"); + } + if (ctx.Flags & SHEMU_FLAG_SWAPGS) + { + printf(" SHEMU_FLAG_SWAPGS\n"); + } + if (ctx.Flags & SHEMU_FLAG_SYSCALL_MSR_READ) + { + printf(" SHEMU_FLAG_SYSCALL_MSR_READ\n"); + } + if (ctx.Flags & SHEMU_FLAG_SYSCALL_MSR_WRITE) + { + printf(" SHEMU_FLAG_SYSCALL_MSR_WRITE\n"); + } + + if (fNameDecoded != NULL) + { + hFile = CreateFileA(fNameDecoded, GENERIC_WRITE, FILE_SHARE_READ, NULL, + CREATE_ALWAYS, FILE_ATTRIBUTE_NORMAL, NULL); + if (INVALID_HANDLE_VALUE == hFile) + { + printf("Could not open the file %s : 0x%08x\n", fNameDecoded, GetLastError()); + return; + } + + WriteFile(hFile, (BYTE *)ctx.Shellcode, (DWORD)fsize, &outSize, NULL); + if (outSize == 0) + { + printf("No bytes written to %s!\n", fNameDecoded); + } + + CloseHandle(hFile); + free(fNameDecoded); + } + + free(ctx.Shellcode); + free(ctx.Stack); + free(ctx.Intbuf); +} + + +// +// _tmain +// +int main( + __in int argc, + __in char* argv[] + ) +{ + HANDLE hFile, hMapping; + DWORD fsize, offset; + SIZE_T rip; + char text[ND_MIN_BUF_SIZE], *fname, *target, *shemuCtxFname; + BYTE mode, print, highlight, fmode, hmode, stats, exi, vend, search, isShemu, isShemuCtxf, isKernel; + INT ret, i; + BYTE hexbuf[256], *buffer; + DISASM_OPTIONS options; + + // preinit + buffer = NULL; + memset(text, 0, sizeof(text)); + memset(&options, 0, sizeof(options)); + print = 1; + highlight = 0; + fmode = 0; + hmode = 0; + stats = 0; + exi = 0; + offset = 0; + search = 0; + vend = ND_VEND_ANY; + fname = NULL; + mode = ND_CODE_16; + hFile = NULL; + hMapping = NULL; + target = NULL; + shemuCtxFname = NULL; + rip = 0; + isShemu = 0; + isShemuCtxf = 0; + isKernel = 0; + + if (NULL == argv) + { + return -1; + } + + if (argc < 3) + { + uint32_t major, minor, revision; + char *date, *time; + + NdGetVersion(&major, &minor, &revision, &date, &time); + + printf("Napoca Disassembler version %d.%d.%d, built on %s %s\n", major, minor, revision, date, time); + printf("Usage: disasm -f file|-h hex-string -b[16|32|64] [-nv] [-iv] [-hl] [-s] [-c] [-shctxf contextfile] " + "[-reg_name reg_val]\n"); + printf(" -f file specify input file\n"); + printf(" -h hexstring specify hex string with instructions\n"); + printf(" -o offset start disasm at specified offset\n"); + printf(" -r rip use the provided RIP\n"); + printf(" -b[16|32|64] set decoding mode; default is 16\n"); + printf(" -v[intel|amd|cyrix|any] set preferred vendor\n"); + printf(" -s \"ins\" search for the given instructions\n"); + printf(" -nv don't print disassembly\n"); + printf(" -iv display statistics\n"); + printf(" -exi print extended info about instructions\n"); + printf(" -shemu emulate the file/hex-string\n"); + printf(" -shctxf contextfile specify file that contains the context for shemu. " + "Ignored if shemu is not used. Overrides registers specified in command line\n"); + printf(" File format: each row contains the format: [regname]:[regvalue]\n"); + printf(" -regname regval specify registers to be set for the shemu context. Ignored if shemu is not used\n"); + printf(" Examples of valid command line register naming: \"RegRax\" ; \"rax\" ; \"reg_rax\"\n"); + printf(" -k specify kernel mode for shemu emulation. Ignore if shemu is not specified.\n"); + printf(" -hl highlight instruction parts:\n"); + SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), + FOREGROUND_BLUE|FOREGROUND_GREEN|FOREGROUND_RED|FOREGROUND_INTENSITY); + printf(" light white prefixes\n"); + SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), FOREGROUND_GREEN|FOREGROUND_INTENSITY); + printf(" light green opcodes\n"); + SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), FOREGROUND_GREEN|FOREGROUND_RED|FOREGROUND_INTENSITY); + printf(" light yellow modrm and sib\n"); + SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), FOREGROUND_BLUE|FOREGROUND_INTENSITY); + printf(" light blue displacement\n"); + SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), FOREGROUND_RED|FOREGROUND_INTENSITY); + printf(" light red relative offset, immediate, address\n"); + SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), FOREGROUND_BLUE|FOREGROUND_GREEN|FOREGROUND_RED); + printf("Instrux size: %zx bytes\n", sizeof(INSTRUX)); + ret = -1; + goto cleanup_and_exit; + } + + i = 1; + while (i < argc) + { + DWORD gprIdx; + + if (match_gpr(argv[i], &gprIdx)) + { + if (i + 1 >= argc) + { + printf("No value given for %s!\n", argv[i]); + } + else + { + options.ShemuRegs[gprIdx] = (size_t)strtoull(argv[i + 1], NULL, 0); + options.UseShemuRegs = TRUE; + i++; + } + } + else if (strcmp(argv[i], "-shctxf") == 0) + { + if (i + 1 < argc) + { + isShemuCtxf = 1; + options.UseShemuRegs = TRUE; + + shemuCtxFname = argv[i + 1]; + i++; + } + } + else if (strcmp(argv[i], "-shemu") == 0) + { + isShemu = 1; + } + else if (argv[i][0] == '-' && argv[i][1] == 'f' && argv[i][2] == 0) + { + if (i + 1 < argc) + { + fmode = 1; + fname = argv[i + 1]; + i++; + } + } + else if (argv[i][0] == '-' && argv[i][1] == 'h' && argv[i][2] == 0) + { + if (i + 1 < argc) + { + hmode = 1; + fname = argv[i + 1]; + i++; + } + } + else if (argv[i][0] == '-' && argv[i][1] == 'o' && argv[i][2] == 0) + { + if (i + 1 < argc) + { + sscanf_s(argv[i + 1], "%x", &offset); + i++; + } + } + else if (argv[i][0] == '-' && argv[i][1] == 'r' && argv[i][2] == 0) + { + if (i + 1 < argc) + { + sscanf_s(argv[i + 1], "%zx", &rip); + i++; + } + } + else if (argv[i][0] == '-' && argv[i][1] == 'k' && argv[i][2] == 0) + { + isKernel = 1; + } + else if (0 == strcmp(argv[i], "-b16")) + { + mode = ND_CODE_16; + } + else if (0 == strcmp(argv[i], "-b32")) + { + mode = ND_CODE_32; + } + else if (0 == strcmp(argv[i], "-b64")) + { + mode = ND_CODE_64; + } + else if (0 == strcmp(argv[i], "-vintel")) + { + vend = ND_VEND_INTEL; + } + else if (0 == strcmp(argv[i], "-vamd")) + { + vend = ND_VEND_AMD; + } + else if (0 == strcmp(argv[i], "-vgeode")) + { + vend = ND_VEND_GEODE; + } + else if (0 == strcmp(argv[i], "-vcyrix")) + { + vend = ND_VEND_CYRIX; + } + else if (0 == strcmp(argv[i], "-vany")) + { + vend = ND_VEND_ANY; + } + else if (0 == strcmp(argv[i], "-nv")) + { + print = 0; + } + else if (0 == strcmp(argv[i], "-hl")) + { + highlight = 1; + } + else if (0 == strcmp(argv[i], "-iv")) + { + stats = 1; + } + else if (0 == strcmp(argv[i], "-exi")) + { + exi = 1; + } + else if (0 == strcmp(argv[i], "-s")) + { + search = 1; + + if (i + 1 == argc) + { + printf("-s requires an argument!\n"); + return -1; + } + + target = argv[++i]; + + if (strlen(target) >= ND_MIN_BUF_SIZE) + { + printf("Target instruction too long! Max is %d bytes!\n", ND_MIN_BUF_SIZE); + return -1; + } + } + else + { + printf("Unknown option: '%s'\n", argv[i]); + } + + i++; + } + + if (0 == fmode && 0 == hmode) + { + printf("Expecting -f or -h option!\n"); + return -1; + } + + if (fmode) + { + // Open the file. + hFile = CreateFileA(fname, GENERIC_READ|GENERIC_WRITE, FILE_SHARE_READ|FILE_SHARE_WRITE, NULL, + OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL); + if (INVALID_HANDLE_VALUE == hFile) + { + printf("Couldn't open file '%s': 0x%08x\n", fname, GetLastError()); + ret = -1; + goto cleanup_and_exit; + } + + // Create a file mapping. + hMapping = CreateFileMappingA(hFile, NULL, PAGE_READWRITE, 0, 0, "DisasmFile"); + if (NULL == hMapping) + { + printf("Couldn't create file mapping for '%s': 0x%08x\n", argv[1], GetLastError()); + ret = -1; + goto cleanup_and_exit; + } + + // Map the file. + buffer = MapViewOfFile(hMapping, FILE_MAP_ALL_ACCESS, 0, 0, 0); + if (NULL == buffer) + { + printf("Couldn't map the view for '%s': 0x%08x\n", argv[1], GetLastError()); + ret = -1; + goto cleanup_and_exit; + } + + fsize = GetFileSize(hFile, NULL); + } + else + { + DWORD idx; + + memset(hexbuf, 0, sizeof(hexbuf)); + + fsize = (DWORD)strlen(fname); + + if (fsize > 512) + { + printf("Max 256-bytes buffer accepted!\n"); + return -1; + } + + if (fsize % 2 == 1) + { + printf("Even-sized hex buffer expected!\n"); + return -1; + } + + for (idx = 0; idx < fsize / 2; idx++) + { + hexbuf[idx] = ((hex_to_bin(fname[idx * 2]) << 4) | (hex_to_bin(fname[idx * 2 + 1]))) & 0xFF; + } + + fname = NULL; + fsize /= 2; + buffer = hexbuf; + } + + if (offset >= fsize) + { + printf("The offset exceeds the buffer size!\n"); + ret = -1; + goto cleanup_and_exit; + } + + options.FileName = fname; + options.Buffer = buffer; + options.Size = fsize; + options.ExtendedInfo = exi; + options.Highlight = highlight; + options.Mode = mode; + options.Ring = isKernel ? 0 : 3; + options.Offset = offset; + options.Stats = stats; + options.Search = search; + options.Target = target; + options.Print = print; + options.Vendor = vend; + options.Rip = rip; + + if (isShemu) + { + if (isShemuCtxf) + { + set_shemuctx_file(shemuCtxFname, &options); + } + + handle_shemu(&options); + } + else if (search) + { + handle_search(&options); + } + else + { + handle_disasm(&options); + } + + // All should be good. + ret = 0; + +cleanup_and_exit: + if (fmode) + { + if (NULL != buffer) + { + UnmapViewOfFile(buffer); + + buffer = NULL; + } + + if (NULL != hMapping) + { + CloseHandle(hMapping); + + hMapping = NULL; + } + + if ((NULL != hFile) && (INVALID_HANDLE_VALUE != hFile)) + { + CloseHandle(hFile); + + hFile = NULL; + } + } + + return ret; +} diff --git a/disasmtool/disasmtool.vcxproj b/disasmtool/disasmtool.vcxproj new file mode 100644 index 0000000..fb6627f --- /dev/null +++ b/disasmtool/disasmtool.vcxproj @@ -0,0 +1,217 @@ + + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + {94F1B65D-3305-4CCB-9DF1-50B56900D867} + disasmtool + Win32Proj + disasmtool + 10.0.18362.0 + + + + Application + v142 + Unicode + true + + + Application + v142 + Unicode + + + Application + v142 + Unicode + true + + + Application + v142 + Unicode + + + + + + + + + + + + + + + + + + + <_ProjectFileVersion>14.0.23107.0 + + + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + true + + + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + true + + + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + false + + + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + false + false + $(LibraryPath) + + + + Disabled + ..\inc;..\bdshemu;%(AdditionalIncludeDirectories) + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + EnableFastChecks + MultiThreadedDebugDLL + Level4 + true + ProgramDatabase + $(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb + + + bddisasm.lib;bdshemu.lib;%(AdditionalDependencies) + $(OutDir)disasmtool.exe + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + true + Console + MachineX86 + + + + + X64 + + + /D "AMD64" %(AdditionalOptions) + Disabled + ..\inc;..\bdshemu;%(AdditionalIncludeDirectories) + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + EnableFastChecks + MultiThreadedDebugDLL + Level4 + true + ProgramDatabase + $(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb + + + bddisasm.lib;bdshemu.lib;%(AdditionalDependencies) + $(OutDir)disasmtool.exe + $(SolutionDir)bin\$(Platform)\$(Configuration)\;%(AdditionalLibraryDirectories) + LIBCMTD;%(IgnoreSpecificDefaultLibraries) + true + Console + MachineX64 + + + false + + + + + MaxSpeed + true + ..\inc;..\bdshemu;%(AdditionalIncludeDirectories) + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + MultiThreadedDLL + true + Level4 + true + ProgramDatabase + $(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb + + + bddisasm.lib;bdshemu.lib;%(AdditionalDependencies) + $(OutDir)disasmtool.exe + $(SolutionDir)bin\$(Platform)\$(Configuration)\;%(AdditionalLibraryDirectories) + true + Console + true + true + MachineX86 + + + + + X64 + + + /D "AMD64" %(AdditionalOptions) + MaxSpeed + AnySuitable + true + Speed + ..\inc;..\bdshemu;%(AdditionalIncludeDirectories) + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + MultiThreadedDLL + false + Level4 + true + ProgramDatabase + $(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb + + + true + + + bddisasm.lib;bdshemu.lib;%(AdditionalDependencies) + $(OutDir)disasmtool.exe + $(SolutionDir)bin\$(Platform)\$(Configuration)\;%(AdditionalLibraryDirectories) + false + LIBCMT;%(IgnoreSpecificDefaultLibraries) + true + Console + true + true + MachineX64 + + + + + + + + {3653aa19-048b-410e-b5c4-ff78e1d84c12} + + + {3c9b2ca7-cf4f-471b-bb72-6490c476cdca} + + + + + + \ No newline at end of file diff --git a/disasmtool/disasmtool.vcxproj.filters b/disasmtool/disasmtool.vcxproj.filters new file mode 100644 index 0000000..c7167ac --- /dev/null +++ b/disasmtool/disasmtool.vcxproj.filters @@ -0,0 +1,22 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav + + + + + Source Files + + + \ No newline at end of file diff --git a/disasmtool_lix/CMakeLists.txt b/disasmtool_lix/CMakeLists.txt new file mode 100644 index 0000000..67e7773 --- /dev/null +++ b/disasmtool_lix/CMakeLists.txt @@ -0,0 +1,172 @@ +cmake_minimum_required (VERSION 3.12) + +project(disasmtool LANGUAGES CXX) + +if (NOT CMAKE_BUILD_TYPE) + message(STATUS "No build type given. Will use 'Release'!") + set(CMAKE_BUILD_TYPE Release) +endif() + +if (CMAKE_CXX_FLAGS) + message(STATUS "Passed CXXFLAGS: ${CMAKE_CXX_FLAGS}") +endif() + +if (("${CMAKE_BUILD_TYPE}" STREQUAL "Debug") AND (CMAKE_CXX_FLAGS_DEBUG)) + message(STATUS "Passed CXXFLAGS_DEBUG: ${CMAKE_CXX_FLAGS_DEBUG}") +endif() + +if (("${CMAKE_BUILD_TYPE}" STREQUAL "Release") AND (CMAKE_CXX_FLAGS_RELEASE)) + message(STATUS "Passed CXXFLAGS_RELEASE: ${CMAKE_CXX_FLAGS_RELEASE}") +endif() + +get_filename_component(DISASM_DIRECTORY "${PROJECT_SOURCE_DIR}/.." REALPATH) +set(DISASM_BUILD_PREFIX "bin/x64") + +set(disasmtool_src_files + disasmtool.cpp + dumpers.cpp + ) + +find_library(DISASM_LIB bddisasm PATHS "${DISASM_DIRECTORY}/${DISASM_BUILD_PREFIX}/${CMAKE_BUILD_TYPE}" NO_DEFAULT_PATH) +message(STATUS "Disasm lib used: ${DISASM_LIB}") + +find_package(RapidJSON) + +if (RapidJSON_FOUND) + message(STATUS "Dependency: rapidjson found") + include_directories(${RapidJSON_INCLUDE_DIRS}) + add_compile_definitions(HAS_RAPIDJSON) + list(APPEND disasmtool_src_files rapidjson.cpp) +else() + message(FATAL_ERROR "Dependency: rapidjson not found") +endif() + +add_compile_options( + "$<$:-U_FORTIFY_SOURCE>" + "$<$:-D_FORTIFY_SOURCE=2>" + -Wall + -Wextra + -Wshadow + -Wformat-security + -Wstrict-overflow=2 + -Wno-unused-function + -Wno-multichar + -Werror=format-security + -pipe + -fpie + -fwrapv + -fno-strict-aliasing + -fstack-protector-strong + -ffunction-sections + -fdata-sections + -g3 + -gdwarf-4 + -grecord-gcc-switches + -march=native + -fno-omit-frame-pointer + # -fsanitize=leak + # -fsanitize=address + ) + +set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} \ +-Wl,--fatal-warnings \ +-Wl,--warn-common \ +-Wl,--no-undefined \ +-Wl,-z,noexecstack \ +-Wl,-z,relro \ +-Wl,-z,now \ +-Wl,--build-id") + +set(CMAKE_SHARED_LINKER_FLAGS_RELEASE "${CMAKE_SHARED_LINKER_FLAGS_RELEASE} -Wl,-O1") + +if (CMAKE_COMPILER_IS_GNUCC) + if (NOT (CMAKE_C_COMPILER_VERSION LESS 6.0)) + add_compile_options( + -Wshift-overflow=2 + -Wnull-dereference + -Wduplicated-cond + -Wlogical-op + -Wvla + ) + endif() + + if (NOT (CMAKE_C_COMPILER_VERSION LESS 7.0)) + add_compile_options( + -Wdangling-else + -Wshadow=global + -Walloc-zero + ) + endif() + + if (NOT (CMAKE_C_COMPILER_VERSION LESS 8.0)) + add_compile_options( + -Wmultistatement-macros + -Warray-bounds=2 + -Wformat-overflow=2 + -Wformat-truncation=1 + -Wstringop-truncation + -Wpointer-arith + -Wdouble-promotion + -Wmissing-include-dirs + -Wuninitialized + -Wmissing-noreturn + -Wsuggest-attribute=noreturn + -Walloca + -Wtrampolines + -Wcast-qual + -Wcast-align + -Wparentheses + -Wjump-misses-init + -Wfloat-conversion + -Wmissing-prototypes + -Wredundant-decls + -Wdisabled-optimization + -Woverlength-strings + -fstack-clash-protection + -static + ) + endif() +else() + add_compile_options( + -Wno-missing-braces + ) + + if (NOT (CMAKE_C_COMPILER_VERSION LESS 6.0)) + add_compile_options( + -Wshift-overflow + -Wnull-dereference + -Wvla + -Wdangling-else + -Wshadow + -Wpragmas + -Wtautological-compare + -Wzero-as-null-pointer-constant + ) + endif() +endif() + +include_directories( + ${DISASM_DIRECTORY}/inc + ${DISASM_DIRECTORY}/inc/bdshemu + ${DISASM_DIRECTORY}/bddisasm/include + ) + +add_executable(${CMAKE_PROJECT_NAME} ${disasmtool_src_files}) + +if ("${CMAKE_BUILD_TYPE}" STREQUAL "Release") + include(CheckIPOSupported) + check_ipo_supported(RESULT USE_IPO) + set_target_properties(${CMAKE_PROJECT_NAME} PROPERTIES INTERPROCEDURAL_OPTIMIZATION True) +endif() + +set_target_properties(${CMAKE_PROJECT_NAME} + PROPERTIES + POSITION_INDEPENDENT_CODE ON + CXX_STANDARD 17 + CXX_STANDARD_REQUIRED ON + CXX_EXTENSIONS ON + ) + +target_link_libraries(${CMAKE_PROJECT_NAME} ${DISASM_LIB}) + +unset(DISASM_LIB CACHE) diff --git a/disasmtool_lix/Makefile b/disasmtool_lix/Makefile new file mode 100644 index 0000000..17b8709 --- /dev/null +++ b/disasmtool_lix/Makefile @@ -0,0 +1,39 @@ +.PHONY: all last_build debug release + +CMAKE_BUILD_DIR = build + +CPUCOUNT := $(shell grep -c "^processor" /proc/cpuinfo) + +ifneq (,$(CPUCOUNT)) +EXTRA_MAKE_ARGS := -j$(CPUCOUNT) +endif + +# NINJA := $(shell which ninja 2>/dev/null) + +ifneq (,$(NINJA)) +GENERATOR := "Ninja" +else +GENERATOR := "Unix Makefiles" +endif + +$(shell if [ ! -d $(CMAKE_BUILD_DIR) ]; then mkdir $(CMAKE_BUILD_DIR); fi) + +all: last_build + +last_build: + @cmake -H. -G$(GENERATOR) -B$(CMAKE_BUILD_DIR) -DCMAKE_EXPORT_COMPILE_COMMANDS=ON + @cmake --build $(CMAKE_BUILD_DIR) -- $(EXTRA_MAKE_ARGS) + +debug: CMAKE_BUILD_TYPE := Debug +debug: build + +release: CMAKE_BUILD_TYPE := Release +release: build + +clean: + @if [ -d $(CMAKE_BUILD_DIR) ]; then cmake --build $(CMAKE_BUILD_DIR) --target clean; fi + +reset: + @if [ -d $(CMAKE_BUILD_DIR) ]; then rm -r $(CMAKE_BUILD_DIR); fi + + diff --git a/disasmtool_lix/disasm.hpp b/disasmtool_lix/disasm.hpp new file mode 100644 index 0000000..73cd8a0 --- /dev/null +++ b/disasmtool_lix/disasm.hpp @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2020 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include + +#ifdef HAS_RAPIDJSON +#include +using StringBuffer = rapidjson::StringBuffer; +#else +#include "external/json.hpp" +using json = nlohmann::json; +#endif + + +extern "C" +{ + + // On windows, simply include Windows.h +#ifndef _WIN32 +typedef void VOID, *PVOID; +typedef unsigned char BOOLEAN, *PBOOLEAN; +typedef char CHAR, *PCHAR; +typedef unsigned char BYTE, *PBYTE; +typedef unsigned short WORD, *PWORD; +typedef unsigned int DWORD, *PDWORD; +typedef unsigned long long QWORD, *PQWORD; +typedef size_t SIZE_T; +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef MAX_PATH +#define MAX_PATH 255 +#endif + +#ifndef __in +#define __in +#endif + +#ifndef __out +#define __out +#endif + +#ifndef __inout +#define __inout +#endif + +// Main disasm header file. +// #include "bdshemu.h" +#include "bddisasm.h" + +#undef __in +#undef __out +#undef __inout + +#include +#include +} + + +#include + + +std::string enc_mode_to_str(const uint8_t enc_mode); +std::string ins_class_to_str(const ND_INS_CLASS cls); +std::string ins_cat_to_str(ND_INS_CATEGORY category); +std::string ins_set_to_str(ND_INS_SET ins_set); +std::string reg_to_str(const int reg, const ND_REG_TYPE type); +std::string reg_type_to_str(const ND_REG_TYPE type); + +StringBuffer instrux_to_json(INSTRUX *instrux, size_t rip, bool text_only = false); +StringBuffer byte_to_json(uint8_t byte, size_t rip); +StringBuffer disassemble_one(uint8_t *bytes, size_t size, size_t rip, uint8_t bits, uint8_t vendor = ND_VEND_INTEL); + diff --git a/disasmtool_lix/disasmtool.cpp b/disasmtool_lix/disasmtool.cpp new file mode 100644 index 0000000..ae7bafd --- /dev/null +++ b/disasmtool_lix/disasmtool.cpp @@ -0,0 +1,736 @@ +/* + * Copyright (c) 2020 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include + +#include "external/argparse.h" + +#include "disasm.hpp" + +static const long NSEC_PER_SEC = (1000ULL * 1000ULL * 1000ULL); + +const char *gSpaces[16] = +{ + "", + " ", + " ", + " ", + " ", + " ", + " ", + " ", + " ", + " ", + " ", + " ", + " ", + " ", + " ", + " ", +}; + + +struct options { + size_t rip; + size_t offset; + size_t size; + size_t count; + + int bits; + + uint8_t vendor; + bool no_color; + bool verbose; + bool dump_stats; + bool interactive; + bool comm; + bool json_output; + + std::string in_file; + std::string hex_string; + std::string hex_file; + + // From here on, these are set internally + std::unique_ptr bytes; + size_t actual_size; + + bool output_redirected; +}; + + +extern "C" +{ + int nd_vsnprintf_s(char *buffer, size_t sizeOfBuffer, [[maybe_unused]] size_t count, const char *format, va_list argptr) + { + return vsnprintf(buffer, sizeOfBuffer, format, argptr); + } + + void * + nd_memset(void *s, int c, size_t n) + { + return memset(s, c, n); + } +} + + +static bool _hexstring_to_bytes(options &opts) +{ + if (!opts.hex_file.empty()) { + auto f = std::ifstream(opts.hex_file, std::ios::in); + + if (!f.is_open()) { + std::cerr << "Failed to open file " << opts.hex_file << std::endl; + return false; + } + + f.seekg(0, std::ios::end); + opts.hex_string.reserve(f.tellg()); + f.seekg(0, std::ios::beg); + + opts.hex_string.assign((std::istreambuf_iterator(f)), std::istreambuf_iterator()); + } + + if (opts.hex_string.empty()) + return false; + + opts.actual_size = 0; + opts.hex_string.erase(std::remove_if(opts.hex_string.begin(), opts.hex_string.end(), isspace), opts.hex_string.end()); + + // This is the maximum size, not the actual size + auto initial_size = opts.hex_string.length() / 2; + + opts.bytes = std::make_unique(initial_size); + auto bytes = opts.bytes.get(); + + for (size_t i = 0; i < opts.hex_string.length(); i += 2) { + auto pair = opts.hex_string.substr(i, 2); + char *end_ptr; + + if (pair == "0x" || pair == "0X" || pair == "\\x") + continue; + + auto b = std::strtoul(pair.c_str(), &end_ptr, 16); + + size_t conv_size = static_cast(end_ptr - pair.c_str()); + + if (conv_size != pair.length()) { + std::cerr << "Trying to convert invalid hex number: " << pair << std::endl; + return false; + } + + bytes[opts.actual_size++] = b; + } + + return true; +} + +static bool _file_to_bytes(options &opts) +{ + auto f = std::ifstream(opts.in_file, std::ios::in | std::ios::binary); + + if (!f.is_open()) { + std::cerr << "Failed to open file " << opts.in_file << std::endl; + return false; + } + + f.seekg(0, std::ios::end); + + opts.actual_size = f.tellg(); + + if (opts.offset >= opts.actual_size) { + std::cerr << "Offset bigger than file size" << std::endl; + return false; + } + + f.seekg(0, std::ios::beg); + + opts.bytes = std::make_unique(opts.actual_size); + + f.read(reinterpret_cast(opts.bytes.get()), opts.actual_size); + + return true; +} + +// Don't change the order (on linux these values are color codes) +enum Colors { + Reset = 0, +#if defined(_WIN32) + Red = FOREGROUND_INTENSITY | FOREGROUND_RED, + Green = FOREGROUND_INTENSITY | FOREGROUND_GREEN, + Yellow = FOREGROUND_INTENSITY | FOREGROUND_RED | FOREGROUND_GREEN, + Blue = FOREGROUND_INTENSITY | FOREGROUND_BLUE, + Magenta = FOREGROUND_INTENSITY | FOREGROUND_BLUE | FOREGROUND_RED, + Cyan = FOREGROUND_INTENSITY | FOREGROUND_BLUE | FOREGROUND_GREEN, + White = FOREGROUND_INTENSITY | FOREGROUND_BLUE | FOREGROUND_GREEN | FOREGROUND_RED, +#elif defined(__unix__) + Red, + Green, + Yellow, + Blue, + Magenta, + Cyan, + White, +#endif +}; + + +static void _set_text_color(Colors color) +{ +#if defined(_WIN32) + static WORD old_attrs = -1; + + if (old_attrs == -1) { + CONSOLE_SCREEN_BUFFER_INFO buffer_info; + GetConsoleScreenBufferInfo(GetStdHandle(STD_OUTPUT_HANDLE), &buffer_info); + old_attrs = buffer_info.wAttributes; + } + + if (color == Reset) + SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), old_attrs); + else + SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), color); +#elif defined(__unix__) + if (color == Reset) + std::cout << "\033[m"; + else + std::cout << "\033[0;3" << color << "m"; +#endif +} + + +static struct timespec diff_time(struct timespec &end, struct timespec &start) +{ + struct timespec result; + + if (end.tv_nsec > start.tv_nsec) { + result.tv_sec = end.tv_sec - start.tv_sec; + result.tv_nsec = end.tv_nsec - start.tv_nsec; + } else { + result.tv_sec = end.tv_sec - start.tv_sec - 1; + result.tv_nsec = NSEC_PER_SEC + end.tv_nsec - start.tv_nsec; + } + + return result; +} + + +void print_instruction(const size_t rip, INSTRUX *instrux, const options &opts) +{ + char instruxText[ND_MIN_BUF_SIZE]; + uint32_t k = 0; + + printf("%zx ", rip); + + if (!opts.no_color) + { + _set_text_color(White); + for (uint32_t idx = 0; idx < instrux->PrefLength; idx++, k++) + { + printf("%02x", instrux->InstructionBytes[k]); + } + + _set_text_color(Green); + for (uint32_t idx = 0; idx < (DWORD)(ND_IS_3DNOW(instrux) ? instrux->OpLength - 1 : instrux->OpLength); idx++, k++) + { + printf("%02x", instrux->InstructionBytes[k]); + } + + _set_text_color(Yellow); + for (uint32_t idx = 0; idx < (DWORD)(instrux->HasModRm + instrux->HasSib); idx++, k++) + { + printf("%02x", instrux->InstructionBytes[k]); + } + + _set_text_color(Blue); + for (uint32_t idx = 0; idx < (DWORD)(instrux->DispLength); idx++, k++) + { + printf("%02x", instrux->InstructionBytes[k]); + } + + _set_text_color(Red); + for (uint32_t idx = 0; idx < (DWORD)(instrux->Imm1Length + instrux->Imm2Length + + instrux->RelOffsLength + instrux->MoffsetLength + + instrux->HasSseImm + instrux->AddrLength); idx++, k++) + { + printf("%02x", instrux->InstructionBytes[k]); + } + + if (ND_IS_3DNOW(instrux)) + { + _set_text_color(Green); + for (; k < instrux->Length; k++) + { + printf("%02x", instrux->InstructionBytes[k]); + } + } + } + + _set_text_color(Reset); + + for (; k < instrux->Length; k++) + { + printf("%02x", instrux->InstructionBytes[k]); + } + + std::cout << gSpaces[16 - instrux->Length]; + + NdToText(instrux, rip, sizeof(instruxText), instruxText); + + std::cout << instruxText << std::endl; + + // if (Options->ExtendedInfo) + // { + // const BYTE opsize[3] = { 2, 4, 8 }; + // const BYTE adsize[3] = { 2, 4, 8 }; + // const BYTE veclen[3] = { 16, 32, 64 }; + + // printf(" DSIZE: %2d, ASIZE: %2d, VLEN: ", + // opsize[instrux->EfOpMode] * 8, adsize[instrux->AddrMode] * 8); + + // if (ND_HAS_VECTOR(instrux)) + // { + // printf("%2d\n", veclen[instrux->VecMode] * 8); + // } + // else + // { + // printf("-\n"); + // } + + // printf(" ISA Set: %s, Ins cat: %s, Ins class: %d, CET tracked: %s\n", + // set_to_string(instrux->IsaSet), category_to_string(instrux->Category), instrux->Instruction, + // instrux->IsCetTracked ? "yes" : "no"); + + // if (0 != instrux->CpuidFlag.Flag) + // { + // char *regs[4] = { "eax", "ecx", "edx", "ebx" }; + + // printf(" CPUID leaf: 0x%08x", instrux->CpuidFlag.Leaf); + + // if (instrux->CpuidFlag.SubLeaf != ND_CFF_NO_SUBLEAF) + // { + // printf(", sub-leaf: 0x%08x", instrux->CpuidFlag.SubLeaf); + // } + + // printf(", reg: %s, bit %d\n", regs[instrux->CpuidFlag.Reg], instrux->CpuidFlag.Bit); + // } + + // { + // DWORD fidx, all; + // char *flags[22] = { "CF", NULL, "PF", NULL, "AF", NULL, "ZF", "SF", "TF", "IF", "DF", "OF", "IOPL", NULL, "NT", NULL, "RF", "VM", "AC", "VIF", "VIP", "ID" }; + + // all = instrux->FlagsAccess.Tested.Raw | instrux->FlagsAccess.Modified.Raw | instrux->FlagsAccess.Set.Raw | + // instrux->FlagsAccess.Cleared.Raw | instrux->FlagsAccess.Undefined.Raw; + // printf(" FLAGS access: "); + + // for (fidx = 0; fidx < 21; fidx++) + // { + // if (flags[fidx] != NULL) + // { + // if (0 == (all & (1ULL << fidx))) + // { + // continue; + // } + + // printf("%s: ", flags[fidx]); + + // if (instrux->FlagsAccess.Tested.Raw & (1ULL << fidx)) + // { + // printf("t"); + // } + + // if (instrux->FlagsAccess.Modified.Raw & (1ULL << fidx)) + // { + // printf("m"); + // } + + // if (instrux->FlagsAccess.Set.Raw & (1ULL << fidx)) + // { + // printf("1"); + // } + + // if (instrux->FlagsAccess.Cleared.Raw & (1ULL << fidx)) + // { + // printf("0"); + // } + + // if (instrux->FlagsAccess.Undefined.Raw & (1ULL << fidx)) + // { + // printf("u"); + // } + + // printf("; "); + // } + // } + + // printf("\n"); + // } + + // printf(" Valid modes: R0: %s, R1: %s, R2: %s, R3: %s, Real: %s, V8086: %s, Prot: %s, Compat: %s, Long: %s, SMM: %s, SGX: %s, TSX: %s, VMXRoot: %s, VMXNonRoot: %s\n", + // instrux->ValidModes.Ring0 ? "yes" : "no", + // instrux->ValidModes.Ring1 ? "yes" : "no", + // instrux->ValidModes.Ring2 ? "yes" : "no", + // instrux->ValidModes.Ring3 ? "yes" : "no", + // instrux->ValidModes.Real ? "yes" : "no", + // instrux->ValidModes.V8086 ? "yes" : "no", + // instrux->ValidModes.Protected ? "yes" : "no", + // instrux->ValidModes.Compatibility ? "yes" : "no", + // instrux->ValidModes.Long ? "yes" : "no", + // instrux->ValidModes.Smm ? "yes" : "no", + // instrux->ValidModes.Sgx ? "yes" : "no", + // instrux->ValidModes.Tsx ? "yes" : "no", + // instrux->ValidModes.VmxRoot ? "yes" : "no", + // instrux->ValidModes.VmxNonRoot ? "yes" : "no" + // ); + + // for (i = 0; i < instrux->OperandsCount; i++) + // { + // printf(" Operand %d %s Type: %10s, Size: %2d, RawSize: %2d, Encoding: %s", i, + // instrux->Operands[i].Access.Read && instrux->Operands[i].Access.Write ? "RW" : + // instrux->Operands[i].Access.Write ? "-W" : instrux->Operands[i].Access.Read ? "R-" : "--", + // optype_to_string(instrux->Operands[i].Type), instrux->Operands[i].Size, + // instrux->Operands[i].RawSize, encoding_to_string(instrux->Operands[i].Encoding) + // ); + + // if (ND_OP_MEM == instrux->Operands[i].Type) + // { + // printf(", "); + + // if (instrux->Operands[i].Info.Memory.IsAG) + // { + // printf("Address Generator, "); + // } + + // if (instrux->Operands[i].Info.Memory.IsBitbase) + // { + // printf("Bitbase Addressing, "); + // } + + // if (instrux->Operands[i].Info.Memory.IsMib) + // { + // printf("MIB Addressing, "); + // } + + // if (instrux->Operands[i].Info.Memory.IsVsib) + // { + // printf("VSIB Addressing, "); + // } + + // if (instrux->Operands[i].Info.Memory.IsStack) + // { + // printf("Stack, "); + // } + + // if (instrux->Operands[i].Info.Memory.IsShadowStack) + // { + // printf("Shadow Stack, "); + // } + // } + + // if (ND_OP_REG == instrux->Operands[i].Type) + // { + // printf(", Type: %16s, Size: %2d, Reg: %d, Count: %d\n", + // regtype_to_string(instrux->Operands[i].Info.Register.Type), + // instrux->Operands[i].Info.Register.Size, + // instrux->Operands[i].Info.Register.Reg, + // instrux->Operands[i].Info.Register.Count); + // } + // else + // { + // printf("\n"); + // } + + // if (instrux->Operands[i].Decorator.HasBroadcast) + // { + // printf(" Decorator: Broadcast %d bytes element %d times\n", + // instrux->Operands[i].Decorator.Broadcast.Size, + // instrux->Operands[i].Decorator.Broadcast.Count); + // } + + // if (instrux->Operands[i].Decorator.HasMask) + // { + // printf(" Decorator: Mask k%d\n", instrux->Operands[i].Decorator.Mask.Msk); + // } + + // if (instrux->Operands[i].Decorator.HasZero) + // { + // printf(" Decorator: Zero (no merging)\n"); + // } + // } + + // printf("\n"); + // } +} + + +StringBuffer disassemble_one(uint8_t *bytes, size_t size, size_t rip, uint8_t bits, uint8_t vendor /* = ND_VEND_INTEL */) +{ + INSTRUX instrux; + + auto status = NdDecodeEx2(&instrux, bytes, size, bits, bits, bits, vendor); + if (!ND_SUCCESS(status)) + return byte_to_json(bytes[0], rip); + else + return instrux_to_json(&instrux, rip); +} + + +size_t disassemble(options &opts) +{ + struct timespec start; + clock_gettime(CLOCK_THREAD_CPUTIME_ID, &start); + + size_t icount = 0, miss_count = 0, ibytes = 0; + size_t rel_rip = opts.offset; + size_t total_disasm = 0; + auto bytes = reinterpret_cast(opts.bytes.get()); + auto disasm_size = std::min(opts.actual_size - opts.offset, opts.size); + + while ((total_disasm < disasm_size) && (icount < opts.count)) { + INSTRUX instrux; + + auto status = NdDecodeEx2(&instrux, + &bytes[rel_rip], + opts.actual_size - rel_rip, + opts.bits, + opts.bits, + opts.bits, + opts.vendor); + + if (!ND_SUCCESS(status)) { + if (!opts.dump_stats) { + + if (opts.json_output) { + auto j = byte_to_json(bytes[rel_rip], rel_rip + opts.rip); + std::cout << j.GetString() << std::endl; + } else { + printf("%zx ", rel_rip + opts.rip); + printf("%02x", bytes[rel_rip]); + printf("%s", gSpaces[16 - 1]); + printf("db 0x%02x\n", bytes[rel_rip]); + } + } + + rel_rip++; + total_disasm++; + + miss_count++; + } else { + icount++; + ibytes += instrux.Length; + + if (!opts.dump_stats) { + if (opts.json_output) { + auto j = instrux_to_json(&instrux, rel_rip + opts.rip); + std::cout << j.GetString() << std::endl; + } else + print_instruction(rel_rip + opts.rip, &instrux, opts); + } else if (opts.json_output) + instrux_to_json(&instrux, rel_rip + opts.rip); + + rel_rip += instrux.Length; + total_disasm += instrux.Length; + } + } + + struct timespec end; + clock_gettime(CLOCK_THREAD_CPUTIME_ID, &end); + + if (opts.dump_stats) + { + auto result = diff_time(end, start); + + long total_ns = result.tv_sec * NSEC_PER_SEC + result.tv_nsec; + + printf("Disassembled %zu instructions took %ld.%09ld seconds, %ld ns / instr.\n", + icount, result.tv_sec, result.tv_nsec, total_ns / icount); + printf("Invalid: %zu/%zu (%.2f) bytes\n", miss_count, ibytes, + (static_cast(miss_count) / static_cast(disasm_size)) * 100.0); + } + + opts.rip += rel_rip; + + return icount; +} + + +static bool _validate_and_fix_args(options& opts) +{ + if (!opts.interactive && !opts.comm) { + int total = 0; + + if (!opts.hex_string.empty()) + total++; + + if (!opts.hex_file.empty()) + total++; + + if (!opts.in_file.empty()) + total++; + + if (total == 0) { + std::cerr << "Give hex, file or hex-file..." << std::endl; + return false; + } else if (total > 1) { + std::cerr << "Only one of hex, file or hex-file can be present..." << std::endl; + return false; + } + } + + if (opts.interactive || opts.comm) { + if (!opts.in_file.empty() || !opts.hex_string.empty() || !opts.hex_file.empty()) { + std::cerr << "Interactive mode doesn't work with file, hex-string or hex-file" << std::endl; + return false; + } + + if (opts.size || opts.count || opts.offset) { + std::cerr << "Interactive mode doesn't work with size, count or offset" << std::endl; + return false; + } + } + + switch (opts.bits) { + case 64: + opts.bits = ND_DATA_64; + break; + + case 32: + opts.bits = ND_DATA_32; + break; + + case 16: + opts.bits = ND_DATA_16; + break; + + default: + std::cerr << "Please give --bits [64,32,16]" << std::endl; + return false; + } + + if (0 == opts.size) + opts.size = std::numeric_limits::max(); + + if (0 == opts.count) + opts.count = std::numeric_limits::max(); + + if (!isatty(fileno(stdout))) + opts.output_redirected = true; + + return true; +} + + +static size_t _get_hex_opt(ArgumentParser &parser, const std::string &field) +{ + return std::strtoul(parser.get(field).c_str(), nullptr, 0); +} + + +int main(int argc, char **argv) +{ + auto opts = options{}; + + auto parser = ArgumentParser(argv[0]); + + parser.add_argument("-i", "--interactive", "Interactive mode", false); + parser.add_argument("-c", "--comm", "Comm mode", false); + parser.add_argument("-r", "--rip", "Use this rip to disassemble", false); + parser.add_argument("-f", "--file", "Use this input file", false); + parser.add_argument("-x", "--hex", "Use this hex-string", false); + parser.add_argument("--hexfile", "Use this input file as a hex-string", false); + parser.add_argument("--no-color", "Don't use colors", false); + parser.add_argument("--offset", "Use this offset in file/hex-string", false); + parser.add_argument("--size", "Only disasemble this size from file/hex-string", false); + parser.add_argument("--count", "Only disasemble this many instructions", false); + parser.add_argument("--stats", "Dump statistics (time, count, etc.)", false); + parser.add_argument("-b", "--bits", "Use the arch [16, 32, 64]", false); + parser.add_argument("--verbose", "Verbose mode", false); + parser.add_argument("--json", "Output to json", false); + + try { + parser.parse(argc, argv); + } catch (const ArgumentParser::ArgumentNotFound& ex) { + std::cout << ex.what() << std::endl; + return 1; + } + + opts.bits = parser.get("bits"); + opts.interactive = parser.get("interactive"); + opts.comm = parser.get("comm"); + opts.offset = _get_hex_opt(parser, "offset"); + opts.size = _get_hex_opt(parser, "size"); + opts.count = _get_hex_opt(parser, "count"); + opts.rip = _get_hex_opt(parser, "rip"); + opts.in_file = parser.get("file"); + opts.hex_string = parser.get("hex"); + opts.hex_file = parser.get("hexfile"); + opts.no_color = parser.get("no-color"); + opts.dump_stats = parser.get("stats"); + opts.verbose = parser.get("verbose"); + opts.json_output = parser.get("json"); + + if (opts.verbose) { + std::cout << "interactive: " << opts.interactive << std::endl; + std::cout << "comm: " << opts.comm << std::endl; + std::cout << "rip: " << opts.rip << std::endl; + std::cout << "bits: " << opts.bits << std::endl; + std::cout << "offset: " << opts.offset << std::endl; + std::cout << "size: " << opts.offset << std::endl; + std::cout << "count: " << opts.count << std::endl; + std::cout << "in_file: " << opts.in_file << std::endl; + std::cout << "no-color: " << opts.no_color << std::endl; + std::cout << "stats: " << opts.dump_stats << std::endl; + std::cout << "hex: " << opts.hex_string << std::endl; + std::cout << "json: " << opts.json_output << std::endl; + } + + if (!_validate_and_fix_args(opts)) { + return 1; + } + + if (!opts.interactive && !opts.comm) { + if (!opts.hex_string.empty() || !opts.hex_file.empty()) { + if (!_hexstring_to_bytes(opts)) + return 1; + } else if (!opts.in_file.empty()) { + if (!_file_to_bytes(opts)) + return 1; + } + + if (opts.offset >= opts.actual_size) + return 1; + + disassemble(opts); + } else { + while (true) { + opts.hex_string.clear(); + + if (!opts.comm) + std::cout << ">> "; + + std::getline(std::cin, opts.hex_string); + + if (opts.hex_string == "q" + || opts.hex_string == "quit" + || opts.hex_string == "exit" + || opts.hex_string.empty()) { + + if (!opts.comm) + std::cout << "Bye!" << std::endl; + + break; + } + + _hexstring_to_bytes(opts); + + disassemble(opts); + + std::cout.flush(); + } + } + + return 0; +} diff --git a/disasmtool_lix/dumpers.cpp b/disasmtool_lix/dumpers.cpp new file mode 100644 index 0000000..63507a1 --- /dev/null +++ b/disasmtool_lix/dumpers.cpp @@ -0,0 +1,1839 @@ +/* + * Copyright (c) 2020 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +#include "disasm.hpp" + + +std::string enc_mode_to_str(const uint8_t enc_mode) +{ + switch (enc_mode) { + case ND_ENCM_LEGACY: return "legacy"; + case ND_ENCM_XOP: return "xop"; + case ND_ENCM_VEX: return "vex"; + case ND_ENCM_EVEX: return "evex"; + } + + return ""; +} + + +std::string ins_class_to_str(const ND_INS_CLASS cls) +{ + switch (cls) { + case ND_INS_INVALID: return "invalid"; + case ND_INS_AAA: return "aaa"; + case ND_INS_AAD: return "aad"; + case ND_INS_AAM: return "aam"; + case ND_INS_AAS: return "aas"; + case ND_INS_ADC: return "adc"; + case ND_INS_ADCX: return "adcx"; + case ND_INS_ADD: return "add"; + case ND_INS_ADDPD: return "addpd"; + case ND_INS_ADDPS: return "addps"; + case ND_INS_ADDSD: return "addsd"; + case ND_INS_ADDSS: return "addss"; + case ND_INS_ADDSUBPD: return "addsubpd"; + case ND_INS_ADDSUBPS: return "addsubps"; + case ND_INS_ADOX: return "adox"; + case ND_INS_AESDEC: return "aesdec"; + case ND_INS_AESDECLAST: return "aesdeclast"; + case ND_INS_AESENC: return "aesenc"; + case ND_INS_AESENCLAST: return "aesenclast"; + case ND_INS_AESIMC: return "aesimc"; + case ND_INS_AESKEYGENASSIST: return "aeskeygenassist"; + case ND_INS_ALTINST: return "altinst"; + case ND_INS_AND: return "and"; + case ND_INS_ANDN: return "andn"; + case ND_INS_ANDNPD: return "andnpd"; + case ND_INS_ANDNPS: return "andnps"; + case ND_INS_ANDPD: return "andpd"; + case ND_INS_ANDPS: return "andps"; + case ND_INS_ARPL: return "arpl"; + case ND_INS_BEXTR: return "bextr"; + case ND_INS_BLCFILL: return "blcfill"; + case ND_INS_BLCI: return "blci"; + case ND_INS_BLCIC: return "blcic"; + case ND_INS_BLCMSK: return "blcmsk"; + case ND_INS_BLCS: return "blcs"; + case ND_INS_BLENDPD: return "blendpd"; + case ND_INS_BLENDPS: return "blendps"; + case ND_INS_BLENDVPD: return "blendvpd"; + case ND_INS_BLENDVPS: return "blendvps"; + case ND_INS_BLSFILL: return "blsfill"; + case ND_INS_BLSI: return "blsi"; + case ND_INS_BLSIC: return "blsic"; + case ND_INS_BLSMSK: return "blsmsk"; + case ND_INS_BLSR: return "blsr"; + case ND_INS_BNDCL: return "bndcl"; + case ND_INS_BNDCN: return "bndcn"; + case ND_INS_BNDCU: return "bndcu"; + case ND_INS_BNDLDX: return "bndldx"; + case ND_INS_BNDMK: return "bndmk"; + case ND_INS_BNDMOV: return "bndmov"; + case ND_INS_BNDSTX: return "bndstx"; + case ND_INS_BOUND: return "bound"; + case ND_INS_BSF: return "bsf"; + case ND_INS_BSR: return "bsr"; + case ND_INS_BSWAP: return "bswap"; + case ND_INS_BT: return "bt"; + case ND_INS_BTC: return "btc"; + case ND_INS_BTR: return "btr"; + case ND_INS_BTS: return "bts"; + case ND_INS_BZHI: return "bzhi"; + case ND_INS_CALLFD: return "callfd"; + case ND_INS_CALLFI: return "callfi"; + case ND_INS_CALLNI: return "callni"; + case ND_INS_CALLNR: return "callnr"; + case ND_INS_CBW: return "cbw"; + case ND_INS_CDQ: return "cdq"; + case ND_INS_CDQE: return "cdqe"; + case ND_INS_CL1INVMB: return "cl1invmb"; + case ND_INS_CLAC: return "clac"; + case ND_INS_CLC: return "clc"; + case ND_INS_CLD: return "cld"; + case ND_INS_CLDEMOTE: return "cldemote"; + case ND_INS_CLEVICT0: return "clevict0"; + case ND_INS_CLEVICT1: return "clevict1"; + case ND_INS_CLFLUSH: return "clflush"; + case ND_INS_CLFLUSHOPT: return "clflushopt"; + case ND_INS_CLGI: return "clgi"; + case ND_INS_CLI: return "cli"; + case ND_INS_CLRSSBSY: return "clrssbsy"; + case ND_INS_CLTS: return "clts"; + case ND_INS_CLWB: return "clwb"; + case ND_INS_CLZERO: return "clzero"; + case ND_INS_CMC: return "cmc"; + case ND_INS_CMOVcc: return "cmovcc"; + case ND_INS_CMP: return "cmp"; + case ND_INS_CMPPD: return "cmppd"; + case ND_INS_CMPPS: return "cmpps"; + case ND_INS_CMPS: return "cmps"; + case ND_INS_CMPSD: return "cmpsd"; + case ND_INS_CMPSS: return "cmpss"; + case ND_INS_CMPXCHG: return "cmpxchg"; + case ND_INS_CMPXCHG16B: return "cmpxchg16b"; + case ND_INS_CMPXCHG8B: return "cmpxchg8b"; + case ND_INS_COMISD: return "comisd"; + case ND_INS_COMISS: return "comiss"; + case ND_INS_CPUID: return "cpuid"; + case ND_INS_CPU_READ: return "cpuread"; + case ND_INS_CPU_WRITE: return "cpuwrite"; + case ND_INS_CQO: return "cqo"; + case ND_INS_CRC32: return "crc32"; + case ND_INS_CVTDQ2PD: return "cvtdq2pd"; + case ND_INS_CVTDQ2PS: return "cvtdq2ps"; + case ND_INS_CVTPD2DQ: return "cvtpd2dq"; + case ND_INS_CVTPD2PI: return "cvtpd2pi"; + case ND_INS_CVTPD2PS: return "cvtpd2ps"; + case ND_INS_CVTPI2PD: return "cvtpi2pd"; + case ND_INS_CVTPI2PS: return "cvtpi2ps"; + case ND_INS_CVTPS2DQ: return "cvtps2dq"; + case ND_INS_CVTPS2PD: return "cvtps2pd"; + case ND_INS_CVTPS2PI: return "cvtps2pi"; + case ND_INS_CVTSD2SI: return "cvtsd2si"; + case ND_INS_CVTSD2SS: return "cvtsd2ss"; + case ND_INS_CVTSI2SD: return "cvtsi2sd"; + case ND_INS_CVTSI2SS: return "cvtsi2ss"; + case ND_INS_CVTSS2SD: return "cvtss2sd"; + case ND_INS_CVTSS2SI: return "cvtss2si"; + case ND_INS_CVTTPD2DQ: return "cvttpd2dq"; + case ND_INS_CVTTPD2PI: return "cvttpd2pi"; + case ND_INS_CVTTPS2DQ: return "cvttps2dq"; + case ND_INS_CVTTPS2PI: return "cvttps2pi"; + case ND_INS_CVTTSD2SI: return "cvttsd2si"; + case ND_INS_CVTTSS2SI: return "cvttss2si"; + case ND_INS_CWD: return "cwd"; + case ND_INS_CWDE: return "cwde"; + case ND_INS_DAA: return "daa"; + case ND_INS_DAS: return "das"; + case ND_INS_DEC: return "dec"; + case ND_INS_DELAY: return "delay"; + case ND_INS_DIV: return "div"; + case ND_INS_DIVPD: return "divpd"; + case ND_INS_DIVPS: return "divps"; + case ND_INS_DIVSD: return "divsd"; + case ND_INS_DIVSS: return "divss"; + case ND_INS_DMINT: return "dmint"; + case ND_INS_DPPD: return "dppd"; + case ND_INS_DPPS: return "dpps"; + case ND_INS_EMMS: return "emms"; + case ND_INS_ENCLS: return "encls"; + case ND_INS_ENCLU: return "enclu"; + case ND_INS_ENCLV: return "enclv"; + case ND_INS_ENDBR: return "endbr"; + case ND_INS_ENQCMD: return "enqcmd"; + case ND_INS_ENQCMDS: return "enqcmds"; + case ND_INS_ENTER: return "enter"; + case ND_INS_EXTRACTPS: return "extractps"; + case ND_INS_EXTRQ: return "extrq"; + case ND_INS_F2XM1: return "f2xm1"; + case ND_INS_FABS: return "fabs"; + case ND_INS_FADD: return "fadd"; + case ND_INS_FADDP: return "faddp"; + case ND_INS_FBLD: return "fbld"; + case ND_INS_FBSTP: return "fbstp"; + case ND_INS_FCHS: return "fchs"; + case ND_INS_FCMOVB: return "fcmovb"; + case ND_INS_FCMOVBE: return "fcmovbe"; + case ND_INS_FCMOVE: return "fcmove"; + case ND_INS_FCMOVNB: return "fcmovnb"; + case ND_INS_FCMOVNBE: return "fcmovnbe"; + case ND_INS_FCMOVNE: return "fcmovne"; + case ND_INS_FCMOVNU: return "fcmovnu"; + case ND_INS_FCMOVU: return "fcmovu"; + case ND_INS_FCOM: return "fcom"; + case ND_INS_FCOMI: return "fcomi"; + case ND_INS_FCOMIP: return "fcomip"; + case ND_INS_FCOMP: return "fcomp"; + case ND_INS_FCOMPP: return "fcompp"; + case ND_INS_FCOS: return "fcos"; + case ND_INS_FDECSTP: return "fdecstp"; + case ND_INS_FDIV: return "fdiv"; + case ND_INS_FDIVP: return "fdivp"; + case ND_INS_FDIVR: return "fdivr"; + case ND_INS_FDIVRP: return "fdivrp"; + case ND_INS_FEMMS: return "femms"; + case ND_INS_FFREE: return "ffree"; + case ND_INS_FFREEP: return "ffreep"; + case ND_INS_FIADD: return "fiadd"; + case ND_INS_FICOM: return "ficom"; + case ND_INS_FICOMP: return "ficomp"; + case ND_INS_FIDIV: return "fidiv"; + case ND_INS_FIDIVR: return "fidivr"; + case ND_INS_FILD: return "fild"; + case ND_INS_FIMUL: return "fimul"; + case ND_INS_FINCSTP: return "fincstp"; + case ND_INS_FIST: return "fist"; + case ND_INS_FISTP: return "fistp"; + case ND_INS_FISTTP: return "fisttp"; + case ND_INS_FISUB: return "fisub"; + case ND_INS_FISUBR: return "fisubr"; + case ND_INS_FLD: return "fld"; + case ND_INS_FLD1: return "fld1"; + case ND_INS_FLDCW: return "fldcw"; + case ND_INS_FLDENV: return "fldenv"; + case ND_INS_FLDL2E: return "fldl2e"; + case ND_INS_FLDL2T: return "fldl2t"; + case ND_INS_FLDLG2: return "fldlg2"; + case ND_INS_FLDLN2: return "fldln2"; + case ND_INS_FLDPI: return "fldpi"; + case ND_INS_FLDZ: return "fldz"; + case ND_INS_FMUL: return "fmul"; + case ND_INS_FMULP: return "fmulp"; + case ND_INS_FNCLEX: return "fnclex"; + case ND_INS_FNDISI: return "fndisi"; + case ND_INS_FNINIT: return "fninit"; + case ND_INS_FNOP: return "fnop"; + case ND_INS_FNSAVE: return "fnsave"; + case ND_INS_FNSTCW: return "fnstcw"; + case ND_INS_FNSTENV: return "fnstenv"; + case ND_INS_FNSTSW: return "fnstsw"; + case ND_INS_FPATAN: return "fpatan"; + case ND_INS_FPREM: return "fprem"; + case ND_INS_FPREM1: return "fprem1"; + case ND_INS_FPTAN: return "fptan"; + case ND_INS_FRINEAR: return "frinear"; + case ND_INS_FRNDINT: return "frndint"; + case ND_INS_FRSTOR: return "frstor"; + case ND_INS_FSCALE: return "fscale"; + case ND_INS_FSIN: return "fsin"; + case ND_INS_FSINCOS: return "fsincos"; + case ND_INS_FSQRT: return "fsqrt"; + case ND_INS_FST: return "fst"; + case ND_INS_FSTDW: return "fstdw"; + case ND_INS_FSTP: return "fstp"; + case ND_INS_FSTPNCE: return "fstpnce"; + case ND_INS_FSTSG: return "fstsg"; + case ND_INS_FSUB: return "fsub"; + case ND_INS_FSUBP: return "fsubp"; + case ND_INS_FSUBR: return "fsubr"; + case ND_INS_FSUBRP: return "fsubrp"; + case ND_INS_FTST: return "ftst"; + case ND_INS_FUCOM: return "fucom"; + case ND_INS_FUCOMI: return "fucomi"; + case ND_INS_FUCOMIP: return "fucomip"; + case ND_INS_FUCOMP: return "fucomp"; + case ND_INS_FUCOMPP: return "fucompp"; + case ND_INS_FXAM: return "fxam"; + case ND_INS_FXCH: return "fxch"; + case ND_INS_FXRSTOR: return "fxrstor"; + case ND_INS_FXSAVE: return "fxsave"; + case ND_INS_FXTRACT: return "fxtract"; + case ND_INS_FYL2X: return "fyl2x"; + case ND_INS_FYL2XP1: return "fyl2xp1"; + case ND_INS_GETSEC: return "getsec"; + case ND_INS_GF2P8AFFINEINVQB: return "gf2p8affineinvqb"; + case ND_INS_GF2P8AFFINEQB: return "gf2p8affineqb"; + case ND_INS_GF2P8MULB: return "gf2p8mulb"; + case ND_INS_HADDPD: return "haddpd"; + case ND_INS_HADDPS: return "haddps"; + case ND_INS_HLT: return "hlt"; + case ND_INS_HSUBPD: return "hsubpd"; + case ND_INS_HSUBPS: return "hsubps"; + case ND_INS_IDIV: return "idiv"; + case ND_INS_IMUL: return "imul"; + case ND_INS_IN: return "in"; + case ND_INS_INC: return "inc"; + case ND_INS_INCSSP: return "incssp"; + case ND_INS_INS: return "ins"; + case ND_INS_INSERTPS: return "insertps"; + case ND_INS_INSERTQ: return "insertq"; + case ND_INS_INT: return "int"; + case ND_INS_INT1: return "int1"; + case ND_INS_INT3: return "int3"; + case ND_INS_INTO: return "into"; + case ND_INS_INVD: return "invd"; + case ND_INS_INVEPT: return "invept"; + case ND_INS_INVLPG: return "invlpg"; + case ND_INS_INVLPGA: return "invlpga"; + case ND_INS_INVLPGB: return "invlpgb"; + case ND_INS_INVPCID: return "invpcid"; + case ND_INS_INVVPID: return "invvpid"; + case ND_INS_IRET: return "iret"; + case ND_INS_JMPE: return "jmpe"; + case ND_INS_JMPFD: return "jmpfd"; + case ND_INS_JMPFI: return "jmpfi"; + case ND_INS_JMPNI: return "jmpni"; + case ND_INS_JMPNR: return "jmpnr"; + case ND_INS_Jcc: return "jcc"; + case ND_INS_JrCXZ: return "jrcxz"; + case ND_INS_KADD: return "kadd"; + case ND_INS_KAND: return "kand"; + case ND_INS_KANDN: return "kandn"; + case ND_INS_KMERGE2L1H: return "kmerge2l1h"; + case ND_INS_KMERGE2L1L: return "kmerge2l1l"; + case ND_INS_KMOV: return "kmov"; + case ND_INS_KNOT: return "knot"; + case ND_INS_KOR: return "kor"; + case ND_INS_KORTEST: return "kortest"; + case ND_INS_KSHIFTL: return "kshiftl"; + case ND_INS_KSHIFTR: return "kshiftr"; + case ND_INS_KTEST: return "ktest"; + case ND_INS_KUNPCKBW: return "kunpckbw"; + case ND_INS_KUNPCKDQ: return "kunpckdq"; + case ND_INS_KUNPCKWD: return "kunpckwd"; + case ND_INS_KXNOR: return "kxnor"; + case ND_INS_KXOR: return "kxor"; + case ND_INS_LAHF: return "lahf"; + case ND_INS_LAR: return "lar"; + case ND_INS_LDDQU: return "lddqu"; + case ND_INS_LDMXCSR: return "ldmxcsr"; + case ND_INS_LDS: return "lds"; + case ND_INS_LDTILECFG: return "ldtilecfg"; + case ND_INS_LEA: return "lea"; + case ND_INS_LEAVE: return "leave"; + case ND_INS_LES: return "les"; + case ND_INS_LFENCE: return "lfence"; + case ND_INS_LFS: return "lfs"; + case ND_INS_LGDT: return "lgdt"; + case ND_INS_LGS: return "lgs"; + case ND_INS_LIDT: return "lidt"; + case ND_INS_LLDT: return "lldt"; + case ND_INS_LLWPCB: return "llwpcb"; + case ND_INS_LMSW: return "lmsw"; + case ND_INS_LOADALL: return "loadall"; + case ND_INS_LOADALLD: return "loadalld"; + case ND_INS_LODS: return "lods"; + case ND_INS_LOOP: return "loop"; + case ND_INS_LOOPNZ: return "loopnz"; + case ND_INS_LOOPZ: return "loopz"; + case ND_INS_LSL: return "lsl"; + case ND_INS_LSS: return "lss"; + case ND_INS_LTR: return "ltr"; + case ND_INS_LWPINS: return "lwpins"; + case ND_INS_LWPVAL: return "lwpval"; + case ND_INS_LZCNT: return "lzcnt"; + case ND_INS_MASKMOVDQU: return "maskmovdqu"; + case ND_INS_MASKMOVQ: return "maskmovq"; + case ND_INS_MAXPD: return "maxpd"; + case ND_INS_MAXPS: return "maxps"; + case ND_INS_MAXSD: return "maxsd"; + case ND_INS_MAXSS: return "maxss"; + case ND_INS_MCOMMIT: return "mcommit"; + case ND_INS_MFENCE: return "mfence"; + case ND_INS_MINPD: return "minpd"; + case ND_INS_MINPS: return "minps"; + case ND_INS_MINSD: return "minsd"; + case ND_INS_MINSS: return "minss"; + case ND_INS_MONITOR: return "monitor"; + case ND_INS_MONITORX: return "monitorx"; + case ND_INS_MONTMUL: return "montmul"; + case ND_INS_MOV: return "mov"; + case ND_INS_MOVAPD: return "movapd"; + case ND_INS_MOVAPS: return "movaps"; + case ND_INS_MOVBE: return "movbe"; + case ND_INS_MOVD: return "movd"; + case ND_INS_MOVDDUP: return "movddup"; + case ND_INS_MOVDIR64B: return "movdir64b"; + case ND_INS_MOVDIRI: return "movdiri"; + case ND_INS_MOVDQ2Q: return "movdq2q"; + case ND_INS_MOVDQA: return "movdqa"; + case ND_INS_MOVDQU: return "movdqu"; + case ND_INS_MOVHPD: return "movhpd"; + case ND_INS_MOVHPS: return "movhps"; + case ND_INS_MOVLHPS: return "movlhps"; + case ND_INS_MOVLPD: return "movlpd"; + case ND_INS_MOVLPS: return "movlps"; + case ND_INS_MOVMSKPD: return "movmskpd"; + case ND_INS_MOVMSKPS: return "movmskps"; + case ND_INS_MOVNTDQ: return "movntdq"; + case ND_INS_MOVNTDQA: return "movntdqa"; + case ND_INS_MOVNTI: return "movnti"; + case ND_INS_MOVNTPD: return "movntpd"; + case ND_INS_MOVNTPS: return "movntps"; + case ND_INS_MOVNTQ: return "movntq"; + case ND_INS_MOVNTSD: return "movntsd"; + case ND_INS_MOVNTSS: return "movntss"; + case ND_INS_MOVQ: return "movq"; + case ND_INS_MOVQ2DQ: return "movq2dq"; + case ND_INS_MOVS: return "movs"; + case ND_INS_MOVSD: return "movsd"; + case ND_INS_MOVSHDUP: return "movshdup"; + case ND_INS_MOVSLDUP: return "movsldup"; + case ND_INS_MOVSS: return "movss"; + case ND_INS_MOVSX: return "movsx"; + case ND_INS_MOVSXD: return "movsxd"; + case ND_INS_MOVUPD: return "movupd"; + case ND_INS_MOVUPS: return "movups"; + case ND_INS_MOVZX: return "movzx"; + case ND_INS_MOV_CR: return "movcr"; + case ND_INS_MOV_DR: return "movdr"; + case ND_INS_MOV_TR: return "movtr"; + case ND_INS_MPSADBW: return "mpsadbw"; + case ND_INS_MUL: return "mul"; + case ND_INS_MULPD: return "mulpd"; + case ND_INS_MULPS: return "mulps"; + case ND_INS_MULSD: return "mulsd"; + case ND_INS_MULSS: return "mulss"; + case ND_INS_MULX: return "mulx"; + case ND_INS_MWAIT: return "mwait"; + case ND_INS_MWAITX: return "mwaitx"; + case ND_INS_NEG: return "neg"; + case ND_INS_NOP: return "nop"; + case ND_INS_NOT: return "not"; + case ND_INS_OR: return "or"; + case ND_INS_ORPD: return "orpd"; + case ND_INS_ORPS: return "orps"; + case ND_INS_OUT: return "out"; + case ND_INS_OUTS: return "outs"; + case ND_INS_PABSB: return "pabsb"; + case ND_INS_PABSD: return "pabsd"; + case ND_INS_PABSW: return "pabsw"; + case ND_INS_PACKSSDW: return "packssdw"; + case ND_INS_PACKSSWB: return "packsswb"; + case ND_INS_PACKUSDW: return "packusdw"; + case ND_INS_PACKUSWB: return "packuswb"; + case ND_INS_PADDB: return "paddb"; + case ND_INS_PADDD: return "paddd"; + case ND_INS_PADDQ: return "paddq"; + case ND_INS_PADDSB: return "paddsb"; + case ND_INS_PADDSW: return "paddsw"; + case ND_INS_PADDUSB: return "paddusb"; + case ND_INS_PADDUSW: return "paddusw"; + case ND_INS_PADDW: return "paddw"; + case ND_INS_PALIGNR: return "palignr"; + case ND_INS_PAND: return "pand"; + case ND_INS_PANDN: return "pandn"; + case ND_INS_PAUSE: return "pause"; + case ND_INS_PAVGB: return "pavgb"; + case ND_INS_PAVGUSB: return "pavgusb"; + case ND_INS_PAVGW: return "pavgw"; + case ND_INS_PBLENDVB: return "pblendvb"; + case ND_INS_PBLENDW: return "pblendw"; + case ND_INS_PCLMULQDQ: return "pclmulqdq"; + case ND_INS_PCMPEQB: return "pcmpeqb"; + case ND_INS_PCMPEQD: return "pcmpeqd"; + case ND_INS_PCMPEQQ: return "pcmpeqq"; + case ND_INS_PCMPEQW: return "pcmpeqw"; + case ND_INS_PCMPESTRI: return "pcmpestri"; + case ND_INS_PCMPESTRM: return "pcmpestrm"; + case ND_INS_PCMPGTB: return "pcmpgtb"; + case ND_INS_PCMPGTD: return "pcmpgtd"; + case ND_INS_PCMPGTQ: return "pcmpgtq"; + case ND_INS_PCMPGTW: return "pcmpgtw"; + case ND_INS_PCMPISTRI: return "pcmpistri"; + case ND_INS_PCMPISTRM: return "pcmpistrm"; + case ND_INS_PCOMMIT: return "pcommit"; + case ND_INS_PCONFIG: return "pconfig"; + case ND_INS_PDEP: return "pdep"; + case ND_INS_PEXT: return "pext"; + case ND_INS_PEXTRB: return "pextrb"; + case ND_INS_PEXTRD: return "pextrd"; + case ND_INS_PEXTRQ: return "pextrq"; + case ND_INS_PEXTRW: return "pextrw"; + case ND_INS_PF2ID: return "pf2id"; + case ND_INS_PF2IW: return "pf2iw"; + case ND_INS_PFACC: return "pfacc"; + case ND_INS_PFADD: return "pfadd"; + case ND_INS_PFCMPEQ: return "pfcmpeq"; + case ND_INS_PFCMPGE: return "pfcmpge"; + case ND_INS_PFCMPGT: return "pfcmpgt"; + case ND_INS_PFMAX: return "pfmax"; + case ND_INS_PFMIN: return "pfmin"; + case ND_INS_PFMUL: return "pfmul"; + case ND_INS_PFNACC: return "pfnacc"; + case ND_INS_PFPNACC: return "pfpnacc"; + case ND_INS_PFRCPIT1: return "pfrcpit1"; + case ND_INS_PFRCPIT2: return "pfrcpit2"; + case ND_INS_PFRCPV: return "pfrcpv"; + case ND_INS_PFRSQIT1: return "pfrsqit1"; + case ND_INS_PFRSQRT: return "pfrsqrt"; + case ND_INS_PFRSQRTV: return "pfrsqrtv"; + case ND_INS_PFSUB: return "pfsub"; + case ND_INS_PFSUBR: return "pfsubr"; + case ND_INS_PHADDD: return "phaddd"; + case ND_INS_PHADDSW: return "phaddsw"; + case ND_INS_PHADDW: return "phaddw"; + case ND_INS_PHMINPOSUW: return "phminposuw"; + case ND_INS_PHSUBD: return "phsubd"; + case ND_INS_PHSUBSW: return "phsubsw"; + case ND_INS_PHSUBW: return "phsubw"; + case ND_INS_PI2FD: return "pi2fd"; + case ND_INS_PI2FW: return "pi2fw"; + case ND_INS_PINSRB: return "pinsrb"; + case ND_INS_PINSRD: return "pinsrd"; + case ND_INS_PINSRQ: return "pinsrq"; + case ND_INS_PINSRW: return "pinsrw"; + case ND_INS_PMADDUBSW: return "pmaddubsw"; + case ND_INS_PMADDWD: return "pmaddwd"; + case ND_INS_PMAXSB: return "pmaxsb"; + case ND_INS_PMAXSD: return "pmaxsd"; + case ND_INS_PMAXSW: return "pmaxsw"; + case ND_INS_PMAXUB: return "pmaxub"; + case ND_INS_PMAXUD: return "pmaxud"; + case ND_INS_PMAXUW: return "pmaxuw"; + case ND_INS_PMINSB: return "pminsb"; + case ND_INS_PMINSD: return "pminsd"; + case ND_INS_PMINSW: return "pminsw"; + case ND_INS_PMINUB: return "pminub"; + case ND_INS_PMINUD: return "pminud"; + case ND_INS_PMINUW: return "pminuw"; + case ND_INS_PMOVMSKB: return "pmovmskb"; + case ND_INS_PMOVSXBD: return "pmovsxbd"; + case ND_INS_PMOVSXBQ: return "pmovsxbq"; + case ND_INS_PMOVSXBW: return "pmovsxbw"; + case ND_INS_PMOVSXDQ: return "pmovsxdq"; + case ND_INS_PMOVSXWD: return "pmovsxwd"; + case ND_INS_PMOVSXWQ: return "pmovsxwq"; + case ND_INS_PMOVZXBD: return "pmovzxbd"; + case ND_INS_PMOVZXBQ: return "pmovzxbq"; + case ND_INS_PMOVZXBW: return "pmovzxbw"; + case ND_INS_PMOVZXDQ: return "pmovzxdq"; + case ND_INS_PMOVZXWD: return "pmovzxwd"; + case ND_INS_PMOVZXWQ: return "pmovzxwq"; + case ND_INS_PMULDQ: return "pmuldq"; + case ND_INS_PMULHRSW: return "pmulhrsw"; + case ND_INS_PMULHRW: return "pmulhrw"; + case ND_INS_PMULHUW: return "pmulhuw"; + case ND_INS_PMULHW: return "pmulhw"; + case ND_INS_PMULLD: return "pmulld"; + case ND_INS_PMULLW: return "pmullw"; + case ND_INS_PMULUDQ: return "pmuludq"; + case ND_INS_POP: return "pop"; + case ND_INS_POPA: return "popa"; + case ND_INS_POPCNT: return "popcnt"; + case ND_INS_POPF: return "popf"; + case ND_INS_POR: return "por"; + case ND_INS_PREFETCH: return "prefetch"; + case ND_INS_PREFETCHE: return "prefetche"; + case ND_INS_PREFETCHM: return "prefetchm"; + case ND_INS_PREFETCHNTA: return "prefetchnta"; + case ND_INS_PREFETCHT0: return "prefetcht0"; + case ND_INS_PREFETCHT1: return "prefetcht1"; + case ND_INS_PREFETCHT2: return "prefetcht2"; + case ND_INS_PREFETCHW: return "prefetchw"; + case ND_INS_PREFETCHWT1: return "prefetchwt1"; + case ND_INS_PSADBW: return "psadbw"; + case ND_INS_PSHUFB: return "pshufb"; + case ND_INS_PSHUFD: return "pshufd"; + case ND_INS_PSHUFHW: return "pshufhw"; + case ND_INS_PSHUFLW: return "pshuflw"; + case ND_INS_PSHUFW: return "pshufw"; + case ND_INS_PSIGNB: return "psignb"; + case ND_INS_PSIGND: return "psignd"; + case ND_INS_PSIGNW: return "psignw"; + case ND_INS_PSLLD: return "pslld"; + case ND_INS_PSLLDQ: return "pslldq"; + case ND_INS_PSLLQ: return "psllq"; + case ND_INS_PSLLW: return "psllw"; + case ND_INS_PSMASH: return "psmash"; + case ND_INS_PSRAD: return "psrad"; + case ND_INS_PSRAW: return "psraw"; + case ND_INS_PSRLD: return "psrld"; + case ND_INS_PSRLDQ: return "psrldq"; + case ND_INS_PSRLQ: return "psrlq"; + case ND_INS_PSRLW: return "psrlw"; + case ND_INS_PSUBB: return "psubb"; + case ND_INS_PSUBD: return "psubd"; + case ND_INS_PSUBQ: return "psubq"; + case ND_INS_PSUBSB: return "psubsb"; + case ND_INS_PSUBSW: return "psubsw"; + case ND_INS_PSUBUSB: return "psubusb"; + case ND_INS_PSUBUSW: return "psubusw"; + case ND_INS_PSUBW: return "psubw"; + case ND_INS_PSWAPD: return "pswapd"; + case ND_INS_PTEST: return "ptest"; + case ND_INS_PTWRITE: return "ptwrite"; + case ND_INS_PUNPCKHBW: return "punpckhbw"; + case ND_INS_PUNPCKHDQ: return "punpckhdq"; + case ND_INS_PUNPCKHQDQ: return "punpckhqdq"; + case ND_INS_PUNPCKHWD: return "punpckhwd"; + case ND_INS_PUNPCKLBW: return "punpcklbw"; + case ND_INS_PUNPCKLDQ: return "punpckldq"; + case ND_INS_PUNPCKLQDQ: return "punpcklqdq"; + case ND_INS_PUNPCKLWD: return "punpcklwd"; + case ND_INS_PUSH: return "push"; + case ND_INS_PUSHA: return "pusha"; + case ND_INS_PUSHF: return "pushf"; + case ND_INS_PVALIDATE: return "pvalidate"; + case ND_INS_PXOR: return "pxor"; + case ND_INS_RCL: return "rcl"; + case ND_INS_RCPPS: return "rcpps"; + case ND_INS_RCPSS: return "rcpss"; + case ND_INS_RCR: return "rcr"; + case ND_INS_RDFSBASE: return "rdfsbase"; + case ND_INS_RDGSBASE: return "rdgsbase"; + case ND_INS_RDMSR: return "rdmsr"; + case ND_INS_RDPID: return "rdpid"; + case ND_INS_RDPKRU: return "rdpkru"; + case ND_INS_RDPMC: return "rdpmc"; + case ND_INS_RDPRU: return "rdpru"; + case ND_INS_RDRAND: return "rdrand"; + case ND_INS_RDSEED: return "rdseed"; + case ND_INS_RDSHR: return "rdshr"; + case ND_INS_RDTSC: return "rdtsc"; + case ND_INS_RDTSCP: return "rdtscp"; + case ND_INS_RETF: return "retf"; + case ND_INS_RETN: return "retn"; + case ND_INS_RMPADJUST: return "rmpadjust"; + case ND_INS_RMPUPDATE: return "rmpupdate"; + case ND_INS_ROL: return "rol"; + case ND_INS_ROR: return "ror"; + case ND_INS_RORX: return "rorx"; + case ND_INS_ROUNDPD: return "roundpd"; + case ND_INS_ROUNDPS: return "roundps"; + case ND_INS_ROUNDSD: return "roundsd"; + case ND_INS_ROUNDSS: return "roundss"; + case ND_INS_RSDC: return "rsdc"; + case ND_INS_RSLDT: return "rsldt"; + case ND_INS_RSM: return "rsm"; + case ND_INS_RSQRTPS: return "rsqrtps"; + case ND_INS_RSQRTSS: return "rsqrtss"; + case ND_INS_RSSSP: return "rsssp"; + case ND_INS_RSTORSSP: return "rstorssp"; + case ND_INS_RSTS: return "rsts"; + case ND_INS_SAHF: return "sahf"; + case ND_INS_SAL: return "sal"; + case ND_INS_SALC: return "salc"; + case ND_INS_SAR: return "sar"; + case ND_INS_SARX: return "sarx"; + case ND_INS_SAVEPREVSSP: return "saveprevssp"; + case ND_INS_SBB: return "sbb"; + case ND_INS_SCAS: return "scas"; + case ND_INS_SERIALIZE: return "serialize"; + case ND_INS_SETSSBSY: return "setssbsy"; + case ND_INS_SETcc: return "setcc"; + case ND_INS_SFENCE: return "sfence"; + case ND_INS_SGDT: return "sgdt"; + case ND_INS_SHA1MSG1: return "sha1msg1"; + case ND_INS_SHA1MSG2: return "sha1msg2"; + case ND_INS_SHA1NEXTE: return "sha1nexte"; + case ND_INS_SHA1RNDS4: return "sha1rnds4"; + case ND_INS_SHA256MSG1: return "sha256msg1"; + case ND_INS_SHA256MSG2: return "sha256msg2"; + case ND_INS_SHA256RNDS2: return "sha256rnds2"; + case ND_INS_SHL: return "shl"; + case ND_INS_SHLD: return "shld"; + case ND_INS_SHLX: return "shlx"; + case ND_INS_SHR: return "shr"; + case ND_INS_SHRD: return "shrd"; + case ND_INS_SHRX: return "shrx"; + case ND_INS_SHUFPD: return "shufpd"; + case ND_INS_SHUFPS: return "shufps"; + case ND_INS_SIDT: return "sidt"; + case ND_INS_SKINIT: return "skinit"; + case ND_INS_SLDT: return "sldt"; + case ND_INS_SLWPCB: return "slwpcb"; + case ND_INS_SMINT: return "smint"; + case ND_INS_SMSW: return "smsw"; + case ND_INS_SPFLT: return "spflt"; + case ND_INS_SQRTPD: return "sqrtpd"; + case ND_INS_SQRTPS: return "sqrtps"; + case ND_INS_SQRTSD: return "sqrtsd"; + case ND_INS_SQRTSS: return "sqrtss"; + case ND_INS_STAC: return "stac"; + case ND_INS_STC: return "stc"; + case ND_INS_STD: return "std"; + case ND_INS_STGI: return "stgi"; + case ND_INS_STI: return "sti"; + case ND_INS_STMXCSR: return "stmxcsr"; + case ND_INS_STOS: return "stos"; + case ND_INS_STR: return "str"; + case ND_INS_STTILECFG: return "sttilecfg"; + case ND_INS_SUB: return "sub"; + case ND_INS_SUBPD: return "subpd"; + case ND_INS_SUBPS: return "subps"; + case ND_INS_SUBSD: return "subsd"; + case ND_INS_SUBSS: return "subss"; + case ND_INS_SVDC: return "svdc"; + case ND_INS_SVLDT: return "svldt"; + case ND_INS_SVTS: return "svts"; + case ND_INS_SWAPGS: return "swapgs"; + case ND_INS_SYSCALL: return "syscall"; + case ND_INS_SYSENTER: return "sysenter"; + case ND_INS_SYSEXIT: return "sysexit"; + case ND_INS_SYSRET: return "sysret"; + case ND_INS_T1MSKC: return "t1mskc"; + case ND_INS_TDPBF16PS: return "tdpbf16ps"; + case ND_INS_TDPBSSD: return "tdpbssd"; + case ND_INS_TDPBSUD: return "tdpbsud"; + case ND_INS_TDPBUSD: return "tdpbusd"; + case ND_INS_TDPBUUD: return "tdpbuud"; + case ND_INS_TEST: return "test"; + case ND_INS_TILELOADD: return "tileloadd"; + case ND_INS_TILELOADDT1: return "tileloaddt1"; + case ND_INS_TILERELEASE: return "tilerelease"; + case ND_INS_TILESTORED: return "tilestored"; + case ND_INS_TILEZERO: return "tilezero"; + case ND_INS_TLBSYNC: return "tlbsync"; + case ND_INS_TPAUSE: return "tpause"; + case ND_INS_TZCNT: return "tzcnt"; + case ND_INS_TZMSK: return "tzmsk"; + case ND_INS_UCOMISD: return "ucomisd"; + case ND_INS_UCOMISS: return "ucomiss"; + case ND_INS_UD0: return "ud0"; + case ND_INS_UD1: return "ud1"; + case ND_INS_UD2: return "ud2"; + case ND_INS_UMONITOR: return "umonitor"; + case ND_INS_UMWAIT: return "umwait"; + case ND_INS_UNPCKHPD: return "unpckhpd"; + case ND_INS_UNPCKHPS: return "unpckhps"; + case ND_INS_UNPCKLPD: return "unpcklpd"; + case ND_INS_UNPCKLPS: return "unpcklps"; + case ND_INS_V4FMADDPS: return "v4fmaddps"; + case ND_INS_V4FMADDSS: return "v4fmaddss"; + case ND_INS_V4FNMADDPS: return "v4fnmaddps"; + case ND_INS_V4FNMADDSS: return "v4fnmaddss"; + case ND_INS_VADDPD: return "vaddpd"; + case ND_INS_VADDPS: return "vaddps"; + case ND_INS_VADDSD: return "vaddsd"; + case ND_INS_VADDSS: return "vaddss"; + case ND_INS_VADDSUBPD: return "vaddsubpd"; + case ND_INS_VADDSUBPS: return "vaddsubps"; + case ND_INS_VAESDEC: return "vaesdec"; + case ND_INS_VAESDECLAST: return "vaesdeclast"; + case ND_INS_VAESENC: return "vaesenc"; + case ND_INS_VAESENCLAST: return "vaesenclast"; + case ND_INS_VAESIMC: return "vaesimc"; + case ND_INS_VAESKEYGENASSIST: return "vaeskeygenassist"; + case ND_INS_VALIGND: return "valignd"; + case ND_INS_VALIGNQ: return "valignq"; + case ND_INS_VANDNPD: return "vandnpd"; + case ND_INS_VANDNPS: return "vandnps"; + case ND_INS_VANDPD: return "vandpd"; + case ND_INS_VANDPS: return "vandps"; + case ND_INS_VBLENDMPD: return "vblendmpd"; + case ND_INS_VBLENDMPS: return "vblendmps"; + case ND_INS_VBLENDPD: return "vblendpd"; + case ND_INS_VBLENDPS: return "vblendps"; + case ND_INS_VBLENDVPD: return "vblendvpd"; + case ND_INS_VBLENDVPS: return "vblendvps"; + case ND_INS_VBROADCASTF128: return "vbroadcastf128"; + case ND_INS_VBROADCASTF32X2: return "vbroadcastf32x2"; + case ND_INS_VBROADCASTF32X4: return "vbroadcastf32x4"; + case ND_INS_VBROADCASTF32X8: return "vbroadcastf32x8"; + case ND_INS_VBROADCASTF64X2: return "vbroadcastf64x2"; + case ND_INS_VBROADCASTF64X4: return "vbroadcastf64x4"; + case ND_INS_VBROADCASTI128: return "vbroadcasti128"; + case ND_INS_VBROADCASTI32X2: return "vbroadcasti32x2"; + case ND_INS_VBROADCASTI32X4: return "vbroadcasti32x4"; + case ND_INS_VBROADCASTI32X8: return "vbroadcasti32x8"; + case ND_INS_VBROADCASTI64X2: return "vbroadcasti64x2"; + case ND_INS_VBROADCASTI64X4: return "vbroadcasti64x4"; + case ND_INS_VBROADCASTSD: return "vbroadcastsd"; + case ND_INS_VBROADCASTSS: return "vbroadcastss"; + case ND_INS_VCMPPD: return "vcmppd"; + case ND_INS_VCMPPS: return "vcmpps"; + case ND_INS_VCMPSD: return "vcmpsd"; + case ND_INS_VCMPSS: return "vcmpss"; + case ND_INS_VCOMISD: return "vcomisd"; + case ND_INS_VCOMISS: return "vcomiss"; + case ND_INS_VCOMPRESSPD: return "vcompresspd"; + case ND_INS_VCOMPRESSPS: return "vcompressps"; + case ND_INS_VCVTDQ2PD: return "vcvtdq2pd"; + case ND_INS_VCVTDQ2PS: return "vcvtdq2ps"; + case ND_INS_VCVTNE2PS2BF16: return "vcvtne2ps2bf16"; + case ND_INS_VCVTNEPS2BF16: return "vcvtneps2bf16"; + case ND_INS_VCVTPD2DQ: return "vcvtpd2dq"; + case ND_INS_VCVTPD2PS: return "vcvtpd2ps"; + case ND_INS_VCVTPD2QQ: return "vcvtpd2qq"; + case ND_INS_VCVTPD2UDQ: return "vcvtpd2udq"; + case ND_INS_VCVTPD2UQQ: return "vcvtpd2uqq"; + case ND_INS_VCVTPH2PS: return "vcvtph2ps"; + case ND_INS_VCVTPS2DQ: return "vcvtps2dq"; + case ND_INS_VCVTPS2PD: return "vcvtps2pd"; + case ND_INS_VCVTPS2PH: return "vcvtps2ph"; + case ND_INS_VCVTPS2QQ: return "vcvtps2qq"; + case ND_INS_VCVTPS2UDQ: return "vcvtps2udq"; + case ND_INS_VCVTPS2UQQ: return "vcvtps2uqq"; + case ND_INS_VCVTQQ2PD: return "vcvtqq2pd"; + case ND_INS_VCVTQQ2PS: return "vcvtqq2ps"; + case ND_INS_VCVTSD2SI: return "vcvtsd2si"; + case ND_INS_VCVTSD2SS: return "vcvtsd2ss"; + case ND_INS_VCVTSD2USI: return "vcvtsd2usi"; + case ND_INS_VCVTSI2SD: return "vcvtsi2sd"; + case ND_INS_VCVTSI2SS: return "vcvtsi2ss"; + case ND_INS_VCVTSS2SD: return "vcvtss2sd"; + case ND_INS_VCVTSS2SI: return "vcvtss2si"; + case ND_INS_VCVTSS2USI: return "vcvtss2usi"; + case ND_INS_VCVTTPD2DQ: return "vcvttpd2dq"; + case ND_INS_VCVTTPD2QQ: return "vcvttpd2qq"; + case ND_INS_VCVTTPD2UDQ: return "vcvttpd2udq"; + case ND_INS_VCVTTPD2UQQ: return "vcvttpd2uqq"; + case ND_INS_VCVTTPS2DQ: return "vcvttps2dq"; + case ND_INS_VCVTTPS2QQ: return "vcvttps2qq"; + case ND_INS_VCVTTPS2UDQ: return "vcvttps2udq"; + case ND_INS_VCVTTPS2UQQ: return "vcvttps2uqq"; + case ND_INS_VCVTTSD2SI: return "vcvttsd2si"; + case ND_INS_VCVTTSD2USI: return "vcvttsd2usi"; + case ND_INS_VCVTTSS2SI: return "vcvttss2si"; + case ND_INS_VCVTTSS2USI: return "vcvttss2usi"; + case ND_INS_VCVTUDQ2PD: return "vcvtudq2pd"; + case ND_INS_VCVTUDQ2PS: return "vcvtudq2ps"; + case ND_INS_VCVTUQQ2PD: return "vcvtuqq2pd"; + case ND_INS_VCVTUQQ2PS: return "vcvtuqq2ps"; + case ND_INS_VCVTUSI2SD: return "vcvtusi2sd"; + case ND_INS_VCVTUSI2SS: return "vcvtusi2ss"; + case ND_INS_VDBPSADBW: return "vdbpsadbw"; + case ND_INS_VDIVPD: return "vdivpd"; + case ND_INS_VDIVPS: return "vdivps"; + case ND_INS_VDIVSD: return "vdivsd"; + case ND_INS_VDIVSS: return "vdivss"; + case ND_INS_VDPBF16PS: return "vdpbf16ps"; + case ND_INS_VDPPD: return "vdppd"; + case ND_INS_VDPPS: return "vdpps"; + case ND_INS_VERR: return "verr"; + case ND_INS_VERW: return "verw"; + case ND_INS_VEXP2PD: return "vexp2pd"; + case ND_INS_VEXP2PS: return "vexp2ps"; + case ND_INS_VEXPANDPD: return "vexpandpd"; + case ND_INS_VEXPANDPS: return "vexpandps"; + case ND_INS_VEXTRACTF128: return "vextractf128"; + case ND_INS_VEXTRACTF32X4: return "vextractf32x4"; + case ND_INS_VEXTRACTF32X8: return "vextractf32x8"; + case ND_INS_VEXTRACTF64X2: return "vextractf64x2"; + case ND_INS_VEXTRACTF64X4: return "vextractf64x4"; + case ND_INS_VEXTRACTI128: return "vextracti128"; + case ND_INS_VEXTRACTI32X4: return "vextracti32x4"; + case ND_INS_VEXTRACTI32X8: return "vextracti32x8"; + case ND_INS_VEXTRACTI64X2: return "vextracti64x2"; + case ND_INS_VEXTRACTI64X4: return "vextracti64x4"; + case ND_INS_VEXTRACTPS: return "vextractps"; + case ND_INS_VFIXUPIMMPD: return "vfixupimmpd"; + case ND_INS_VFIXUPIMMPS: return "vfixupimmps"; + case ND_INS_VFIXUPIMMSD: return "vfixupimmsd"; + case ND_INS_VFIXUPIMMSS: return "vfixupimmss"; + case ND_INS_VFMADD132PD: return "vfmadd132pd"; + case ND_INS_VFMADD132PS: return "vfmadd132ps"; + case ND_INS_VFMADD132SD: return "vfmadd132sd"; + case ND_INS_VFMADD132SS: return "vfmadd132ss"; + case ND_INS_VFMADD213PD: return "vfmadd213pd"; + case ND_INS_VFMADD213PS: return "vfmadd213ps"; + case ND_INS_VFMADD213SD: return "vfmadd213sd"; + case ND_INS_VFMADD213SS: return "vfmadd213ss"; + case ND_INS_VFMADD231PD: return "vfmadd231pd"; + case ND_INS_VFMADD231PS: return "vfmadd231ps"; + case ND_INS_VFMADD231SD: return "vfmadd231sd"; + case ND_INS_VFMADD231SS: return "vfmadd231ss"; + case ND_INS_VFMADDPD: return "vfmaddpd"; + case ND_INS_VFMADDPS: return "vfmaddps"; + case ND_INS_VFMADDSD: return "vfmaddsd"; + case ND_INS_VFMADDSS: return "vfmaddss"; + case ND_INS_VFMADDSUB132PD: return "vfmaddsub132pd"; + case ND_INS_VFMADDSUB132PS: return "vfmaddsub132ps"; + case ND_INS_VFMADDSUB213PD: return "vfmaddsub213pd"; + case ND_INS_VFMADDSUB213PS: return "vfmaddsub213ps"; + case ND_INS_VFMADDSUB231PD: return "vfmaddsub231pd"; + case ND_INS_VFMADDSUB231PS: return "vfmaddsub231ps"; + case ND_INS_VFMADDSUBPD: return "vfmaddsubpd"; + case ND_INS_VFMADDSUBPS: return "vfmaddsubps"; + case ND_INS_VFMSUB132PD: return "vfmsub132pd"; + case ND_INS_VFMSUB132PS: return "vfmsub132ps"; + case ND_INS_VFMSUB132SD: return "vfmsub132sd"; + case ND_INS_VFMSUB132SS: return "vfmsub132ss"; + case ND_INS_VFMSUB213PD: return "vfmsub213pd"; + case ND_INS_VFMSUB213PS: return "vfmsub213ps"; + case ND_INS_VFMSUB213SD: return "vfmsub213sd"; + case ND_INS_VFMSUB213SS: return "vfmsub213ss"; + case ND_INS_VFMSUB231PD: return "vfmsub231pd"; + case ND_INS_VFMSUB231PS: return "vfmsub231ps"; + case ND_INS_VFMSUB231SD: return "vfmsub231sd"; + case ND_INS_VFMSUB231SS: return "vfmsub231ss"; + case ND_INS_VFMSUBADD132PD: return "vfmsubadd132pd"; + case ND_INS_VFMSUBADD132PS: return "vfmsubadd132ps"; + case ND_INS_VFMSUBADD213PD: return "vfmsubadd213pd"; + case ND_INS_VFMSUBADD213PS: return "vfmsubadd213ps"; + case ND_INS_VFMSUBADD231PD: return "vfmsubadd231pd"; + case ND_INS_VFMSUBADD231PS: return "vfmsubadd231ps"; + case ND_INS_VFMSUBADDPD: return "vfmsubaddpd"; + case ND_INS_VFMSUBADDPS: return "vfmsubaddps"; + case ND_INS_VFMSUBPD: return "vfmsubpd"; + case ND_INS_VFMSUBPS: return "vfmsubps"; + case ND_INS_VFMSUBSD: return "vfmsubsd"; + case ND_INS_VFMSUBSS: return "vfmsubss"; + case ND_INS_VFNMADD132PD: return "vfnmadd132pd"; + case ND_INS_VFNMADD132PS: return "vfnmadd132ps"; + case ND_INS_VFNMADD132SD: return "vfnmadd132sd"; + case ND_INS_VFNMADD132SS: return "vfnmadd132ss"; + case ND_INS_VFNMADD213PD: return "vfnmadd213pd"; + case ND_INS_VFNMADD213PS: return "vfnmadd213ps"; + case ND_INS_VFNMADD213SD: return "vfnmadd213sd"; + case ND_INS_VFNMADD213SS: return "vfnmadd213ss"; + case ND_INS_VFNMADD231PD: return "vfnmadd231pd"; + case ND_INS_VFNMADD231PS: return "vfnmadd231ps"; + case ND_INS_VFNMADD231SD: return "vfnmadd231sd"; + case ND_INS_VFNMADD231SS: return "vfnmadd231ss"; + case ND_INS_VFNMADDPD: return "vfnmaddpd"; + case ND_INS_VFNMADDPS: return "vfnmaddps"; + case ND_INS_VFNMADDSD: return "vfnmaddsd"; + case ND_INS_VFNMADDSS: return "vfnmaddss"; + case ND_INS_VFNMSUB132PD: return "vfnmsub132pd"; + case ND_INS_VFNMSUB132PS: return "vfnmsub132ps"; + case ND_INS_VFNMSUB132SD: return "vfnmsub132sd"; + case ND_INS_VFNMSUB132SS: return "vfnmsub132ss"; + case ND_INS_VFNMSUB213PD: return "vfnmsub213pd"; + case ND_INS_VFNMSUB213PS: return "vfnmsub213ps"; + case ND_INS_VFNMSUB213SD: return "vfnmsub213sd"; + case ND_INS_VFNMSUB213SS: return "vfnmsub213ss"; + case ND_INS_VFNMSUB231PD: return "vfnmsub231pd"; + case ND_INS_VFNMSUB231PS: return "vfnmsub231ps"; + case ND_INS_VFNMSUB231SD: return "vfnmsub231sd"; + case ND_INS_VFNMSUB231SS: return "vfnmsub231ss"; + case ND_INS_VFNMSUBPD: return "vfnmsubpd"; + case ND_INS_VFNMSUBPS: return "vfnmsubps"; + case ND_INS_VFNMSUBSD: return "vfnmsubsd"; + case ND_INS_VFNMSUBSS: return "vfnmsubss"; + case ND_INS_VFPCLASSPD: return "vfpclasspd"; + case ND_INS_VFPCLASSPS: return "vfpclassps"; + case ND_INS_VFPCLASSSD: return "vfpclasssd"; + case ND_INS_VFPCLASSSS: return "vfpclassss"; + case ND_INS_VFRCZPD: return "vfrczpd"; + case ND_INS_VFRCZPS: return "vfrczps"; + case ND_INS_VFRCZSD: return "vfrczsd"; + case ND_INS_VFRCZSS: return "vfrczss"; + case ND_INS_VGATHERDPD: return "vgatherdpd"; + case ND_INS_VGATHERDPS: return "vgatherdps"; + case ND_INS_VGATHERPF0DPD: return "vgatherpf0dpd"; + case ND_INS_VGATHERPF0DPS: return "vgatherpf0dps"; + case ND_INS_VGATHERPF0QPD: return "vgatherpf0qpd"; + case ND_INS_VGATHERPF0QPS: return "vgatherpf0qps"; + case ND_INS_VGATHERPF1DPD: return "vgatherpf1dpd"; + case ND_INS_VGATHERPF1DPS: return "vgatherpf1dps"; + case ND_INS_VGATHERPF1QPD: return "vgatherpf1qpd"; + case ND_INS_VGATHERPF1QPS: return "vgatherpf1qps"; + case ND_INS_VGATHERQPD: return "vgatherqpd"; + case ND_INS_VGATHERQPS: return "vgatherqps"; + case ND_INS_VGETEXPPD: return "vgetexppd"; + case ND_INS_VGETEXPPS: return "vgetexpps"; + case ND_INS_VGETEXPSD: return "vgetexpsd"; + case ND_INS_VGETEXPSS: return "vgetexpss"; + case ND_INS_VGETMANTPD: return "vgetmantpd"; + case ND_INS_VGETMANTPS: return "vgetmantps"; + case ND_INS_VGETMANTSD: return "vgetmantsd"; + case ND_INS_VGETMANTSS: return "vgetmantss"; + case ND_INS_VGF2P8AFFINEINVQB: return "vgf2p8affineinvqb"; + case ND_INS_VGF2P8AFFINEQB: return "vgf2p8affineqb"; + case ND_INS_VGF2P8MULB: return "vgf2p8mulb"; + case ND_INS_VHADDPD: return "vhaddpd"; + case ND_INS_VHADDPS: return "vhaddps"; + case ND_INS_VHSUBPD: return "vhsubpd"; + case ND_INS_VHSUBPS: return "vhsubps"; + case ND_INS_VINSERTF128: return "vinsertf128"; + case ND_INS_VINSERTF32X4: return "vinsertf32x4"; + case ND_INS_VINSERTF32X8: return "vinsertf32x8"; + case ND_INS_VINSERTF64X2: return "vinsertf64x2"; + case ND_INS_VINSERTF64X4: return "vinsertf64x4"; + case ND_INS_VINSERTI128: return "vinserti128"; + case ND_INS_VINSERTI32X4: return "vinserti32x4"; + case ND_INS_VINSERTI32X8: return "vinserti32x8"; + case ND_INS_VINSERTI64X2: return "vinserti64x2"; + case ND_INS_VINSERTI64X4: return "vinserti64x4"; + case ND_INS_VINSERTPS: return "vinsertps"; + case ND_INS_VLDDQU: return "vlddqu"; + case ND_INS_VLDMXCSR: return "vldmxcsr"; + case ND_INS_VMASKMOVDQU: return "vmaskmovdqu"; + case ND_INS_VMASKMOVPD: return "vmaskmovpd"; + case ND_INS_VMASKMOVPS: return "vmaskmovps"; + case ND_INS_VMAXPD: return "vmaxpd"; + case ND_INS_VMAXPS: return "vmaxps"; + case ND_INS_VMAXSD: return "vmaxsd"; + case ND_INS_VMAXSS: return "vmaxss"; + case ND_INS_VMCALL: return "vmcall"; + case ND_INS_VMCLEAR: return "vmclear"; + case ND_INS_VMFUNC: return "vmfunc"; + case ND_INS_VMGEXIT: return "vmgexit"; + case ND_INS_VMINPD: return "vminpd"; + case ND_INS_VMINPS: return "vminps"; + case ND_INS_VMINSD: return "vminsd"; + case ND_INS_VMINSS: return "vminss"; + case ND_INS_VMLAUNCH: return "vmlaunch"; + case ND_INS_VMLOAD: return "vmload"; + case ND_INS_VMMCALL: return "vmmcall"; + case ND_INS_VMOVAPD: return "vmovapd"; + case ND_INS_VMOVAPS: return "vmovaps"; + case ND_INS_VMOVD: return "vmovd"; + case ND_INS_VMOVDDUP: return "vmovddup"; + case ND_INS_VMOVDQA: return "vmovdqa"; + case ND_INS_VMOVDQA32: return "vmovdqa32"; + case ND_INS_VMOVDQA64: return "vmovdqa64"; + case ND_INS_VMOVDQU: return "vmovdqu"; + case ND_INS_VMOVDQU16: return "vmovdqu16"; + case ND_INS_VMOVDQU32: return "vmovdqu32"; + case ND_INS_VMOVDQU64: return "vmovdqu64"; + case ND_INS_VMOVDQU8: return "vmovdqu8"; + case ND_INS_VMOVHLPS: return "vmovhlps"; + case ND_INS_VMOVHPD: return "vmovhpd"; + case ND_INS_VMOVHPS: return "vmovhps"; + case ND_INS_VMOVLHPS: return "vmovlhps"; + case ND_INS_VMOVLPD: return "vmovlpd"; + case ND_INS_VMOVLPS: return "vmovlps"; + case ND_INS_VMOVMSKPD: return "vmovmskpd"; + case ND_INS_VMOVMSKPS: return "vmovmskps"; + case ND_INS_VMOVNTDQ: return "vmovntdq"; + case ND_INS_VMOVNTDQA: return "vmovntdqa"; + case ND_INS_VMOVNTPD: return "vmovntpd"; + case ND_INS_VMOVNTPS: return "vmovntps"; + case ND_INS_VMOVQ: return "vmovq"; + case ND_INS_VMOVSD: return "vmovsd"; + case ND_INS_VMOVSHDUP: return "vmovshdup"; + case ND_INS_VMOVSLDUP: return "vmovsldup"; + case ND_INS_VMOVSS: return "vmovss"; + case ND_INS_VMOVUPD: return "vmovupd"; + case ND_INS_VMOVUPS: return "vmovups"; + case ND_INS_VMPSADBW: return "vmpsadbw"; + case ND_INS_VMPTRLD: return "vmptrld"; + case ND_INS_VMPTRST: return "vmptrst"; + case ND_INS_VMREAD: return "vmread"; + case ND_INS_VMRESUME: return "vmresume"; + case ND_INS_VMRUN: return "vmrun"; + case ND_INS_VMSAVE: return "vmsave"; + case ND_INS_VMULPD: return "vmulpd"; + case ND_INS_VMULPS: return "vmulps"; + case ND_INS_VMULSD: return "vmulsd"; + case ND_INS_VMULSS: return "vmulss"; + case ND_INS_VMWRITE: return "vmwrite"; + case ND_INS_VMXOFF: return "vmxoff"; + case ND_INS_VMXON: return "vmxon"; + case ND_INS_VORPD: return "vorpd"; + case ND_INS_VORPS: return "vorps"; + case ND_INS_VP2INTERSECTD: return "vp2intersectd"; + case ND_INS_VP2INTERSECTQ: return "vp2intersectq"; + case ND_INS_VP4DPWSSD: return "vp4dpwssd"; + case ND_INS_VP4DPWSSDS: return "vp4dpwssds"; + case ND_INS_VPABSB: return "vpabsb"; + case ND_INS_VPABSD: return "vpabsd"; + case ND_INS_VPABSQ: return "vpabsq"; + case ND_INS_VPABSW: return "vpabsw"; + case ND_INS_VPACKSSDW: return "vpackssdw"; + case ND_INS_VPACKSSWB: return "vpacksswb"; + case ND_INS_VPACKUSDW: return "vpackusdw"; + case ND_INS_VPACKUSWB: return "vpackuswb"; + case ND_INS_VPADDB: return "vpaddb"; + case ND_INS_VPADDD: return "vpaddd"; + case ND_INS_VPADDQ: return "vpaddq"; + case ND_INS_VPADDSB: return "vpaddsb"; + case ND_INS_VPADDSW: return "vpaddsw"; + case ND_INS_VPADDUSB: return "vpaddusb"; + case ND_INS_VPADDUSW: return "vpaddusw"; + case ND_INS_VPADDW: return "vpaddw"; + case ND_INS_VPALIGNR: return "vpalignr"; + case ND_INS_VPAND: return "vpand"; + case ND_INS_VPANDD: return "vpandd"; + case ND_INS_VPANDN: return "vpandn"; + case ND_INS_VPANDND: return "vpandnd"; + case ND_INS_VPANDNQ: return "vpandnq"; + case ND_INS_VPANDQ: return "vpandq"; + case ND_INS_VPAVGB: return "vpavgb"; + case ND_INS_VPAVGW: return "vpavgw"; + case ND_INS_VPBLENDD: return "vpblendd"; + case ND_INS_VPBLENDMB: return "vpblendmb"; + case ND_INS_VPBLENDMD: return "vpblendmd"; + case ND_INS_VPBLENDMQ: return "vpblendmq"; + case ND_INS_VPBLENDMW: return "vpblendmw"; + case ND_INS_VPBLENDVB: return "vpblendvb"; + case ND_INS_VPBLENDW: return "vpblendw"; + case ND_INS_VPBROADCASTB: return "vpbroadcastb"; + case ND_INS_VPBROADCASTD: return "vpbroadcastd"; + case ND_INS_VPBROADCASTMB2Q: return "vpbroadcastmb2q"; + case ND_INS_VPBROADCASTMW2D: return "vpbroadcastmw2d"; + case ND_INS_VPBROADCASTQ: return "vpbroadcastq"; + case ND_INS_VPBROADCASTW: return "vpbroadcastw"; + case ND_INS_VPCLMULQDQ: return "vpclmulqdq"; + case ND_INS_VPCMOV: return "vpcmov"; + case ND_INS_VPCMPB: return "vpcmpb"; + case ND_INS_VPCMPD: return "vpcmpd"; + case ND_INS_VPCMPEQB: return "vpcmpeqb"; + case ND_INS_VPCMPEQD: return "vpcmpeqd"; + case ND_INS_VPCMPEQQ: return "vpcmpeqq"; + case ND_INS_VPCMPEQW: return "vpcmpeqw"; + case ND_INS_VPCMPESTRI: return "vpcmpestri"; + case ND_INS_VPCMPESTRM: return "vpcmpestrm"; + case ND_INS_VPCMPGTB: return "vpcmpgtb"; + case ND_INS_VPCMPGTD: return "vpcmpgtd"; + case ND_INS_VPCMPGTQ: return "vpcmpgtq"; + case ND_INS_VPCMPGTW: return "vpcmpgtw"; + case ND_INS_VPCMPISTRI: return "vpcmpistri"; + case ND_INS_VPCMPISTRM: return "vpcmpistrm"; + case ND_INS_VPCMPQ: return "vpcmpq"; + case ND_INS_VPCMPUB: return "vpcmpub"; + case ND_INS_VPCMPUD: return "vpcmpud"; + case ND_INS_VPCMPUQ: return "vpcmpuq"; + case ND_INS_VPCMPUW: return "vpcmpuw"; + case ND_INS_VPCMPW: return "vpcmpw"; + case ND_INS_VPCOMB: return "vpcomb"; + case ND_INS_VPCOMD: return "vpcomd"; + case ND_INS_VPCOMPRESSB: return "vpcompressb"; + case ND_INS_VPCOMPRESSD: return "vpcompressd"; + case ND_INS_VPCOMPRESSQ: return "vpcompressq"; + case ND_INS_VPCOMPRESSW: return "vpcompressw"; + case ND_INS_VPCOMQ: return "vpcomq"; + case ND_INS_VPCOMUB: return "vpcomub"; + case ND_INS_VPCOMUD: return "vpcomud"; + case ND_INS_VPCOMUQ: return "vpcomuq"; + case ND_INS_VPCOMUW: return "vpcomuw"; + case ND_INS_VPCOMW: return "vpcomw"; + case ND_INS_VPCONFLICTD: return "vpconflictd"; + case ND_INS_VPCONFLICTQ: return "vpconflictq"; + case ND_INS_VPDPBUSD: return "vpdpbusd"; + case ND_INS_VPDPBUSDS: return "vpdpbusds"; + case ND_INS_VPDPWSSD: return "vpdpwssd"; + case ND_INS_VPDPWSSDS: return "vpdpwssds"; + case ND_INS_VPERM2F128: return "vperm2f128"; + case ND_INS_VPERM2I128: return "vperm2i128"; + case ND_INS_VPERMB: return "vpermb"; + case ND_INS_VPERMD: return "vpermd"; + case ND_INS_VPERMI2B: return "vpermi2b"; + case ND_INS_VPERMI2D: return "vpermi2d"; + case ND_INS_VPERMI2PD: return "vpermi2pd"; + case ND_INS_VPERMI2PS: return "vpermi2ps"; + case ND_INS_VPERMI2Q: return "vpermi2q"; + case ND_INS_VPERMI2W: return "vpermi2w"; + case ND_INS_VPERMILPD: return "vpermilpd"; + case ND_INS_VPERMILPS: return "vpermilps"; + case ND_INS_VPERMILzz2PD: return "vpermilzz2pd"; + case ND_INS_VPERMILzz2PS: return "vpermilzz2ps"; + case ND_INS_VPERMPD: return "vpermpd"; + case ND_INS_VPERMPS: return "vpermps"; + case ND_INS_VPERMQ: return "vpermq"; + case ND_INS_VPERMT2B: return "vpermt2b"; + case ND_INS_VPERMT2D: return "vpermt2d"; + case ND_INS_VPERMT2PD: return "vpermt2pd"; + case ND_INS_VPERMT2PS: return "vpermt2ps"; + case ND_INS_VPERMT2Q: return "vpermt2q"; + case ND_INS_VPERMT2W: return "vpermt2w"; + case ND_INS_VPERMW: return "vpermw"; + case ND_INS_VPEXPANDB: return "vpexpandb"; + case ND_INS_VPEXPANDD: return "vpexpandd"; + case ND_INS_VPEXPANDQ: return "vpexpandq"; + case ND_INS_VPEXPANDW: return "vpexpandw"; + case ND_INS_VPEXTRB: return "vpextrb"; + case ND_INS_VPEXTRD: return "vpextrd"; + case ND_INS_VPEXTRQ: return "vpextrq"; + case ND_INS_VPEXTRW: return "vpextrw"; + case ND_INS_VPGATHERDD: return "vpgatherdd"; + case ND_INS_VPGATHERDQ: return "vpgatherdq"; + case ND_INS_VPGATHERQD: return "vpgatherqd"; + case ND_INS_VPGATHERQQ: return "vpgatherqq"; + case ND_INS_VPHADDBD: return "vphaddbd"; + case ND_INS_VPHADDBQ: return "vphaddbq"; + case ND_INS_VPHADDBW: return "vphaddbw"; + case ND_INS_VPHADDD: return "vphaddd"; + case ND_INS_VPHADDDQ: return "vphadddq"; + case ND_INS_VPHADDSW: return "vphaddsw"; + case ND_INS_VPHADDUBD: return "vphaddubd"; + case ND_INS_VPHADDUBQ: return "vphaddubq"; + case ND_INS_VPHADDUBW: return "vphaddubw"; + case ND_INS_VPHADDUDQ: return "vphaddudq"; + case ND_INS_VPHADDUWD: return "vphadduwd"; + case ND_INS_VPHADDUWQ: return "vphadduwq"; + case ND_INS_VPHADDW: return "vphaddw"; + case ND_INS_VPHADDWD: return "vphaddwd"; + case ND_INS_VPHADDWQ: return "vphaddwq"; + case ND_INS_VPHMINPOSUW: return "vphminposuw"; + case ND_INS_VPHSUBBW: return "vphsubbw"; + case ND_INS_VPHSUBD: return "vphsubd"; + case ND_INS_VPHSUBDQ: return "vphsubdq"; + case ND_INS_VPHSUBSW: return "vphsubsw"; + case ND_INS_VPHSUBW: return "vphsubw"; + case ND_INS_VPHSUBWD: return "vphsubwd"; + case ND_INS_VPINSRB: return "vpinsrb"; + case ND_INS_VPINSRD: return "vpinsrd"; + case ND_INS_VPINSRQ: return "vpinsrq"; + case ND_INS_VPINSRW: return "vpinsrw"; + case ND_INS_VPLZCNTD: return "vplzcntd"; + case ND_INS_VPLZCNTQ: return "vplzcntq"; + case ND_INS_VPMACSDD: return "vpmacsdd"; + case ND_INS_VPMACSDQH: return "vpmacsdqh"; + case ND_INS_VPMACSDQL: return "vpmacsdql"; + case ND_INS_VPMACSSDD: return "vpmacssdd"; + case ND_INS_VPMACSSDQH: return "vpmacssdqh"; + case ND_INS_VPMACSSDQL: return "vpmacssdql"; + case ND_INS_VPMACSSWD: return "vpmacsswd"; + case ND_INS_VPMACSSWW: return "vpmacssww"; + case ND_INS_VPMACSWD: return "vpmacswd"; + case ND_INS_VPMACSWW: return "vpmacsww"; + case ND_INS_VPMADCSSWD: return "vpmadcsswd"; + case ND_INS_VPMADCSWD: return "vpmadcswd"; + case ND_INS_VPMADD52HUQ: return "vpmadd52huq"; + case ND_INS_VPMADD52LUQ: return "vpmadd52luq"; + case ND_INS_VPMADDUBSW: return "vpmaddubsw"; + case ND_INS_VPMADDWD: return "vpmaddwd"; + case ND_INS_VPMASKMOVD: return "vpmaskmovd"; + case ND_INS_VPMASKMOVQ: return "vpmaskmovq"; + case ND_INS_VPMAXSB: return "vpmaxsb"; + case ND_INS_VPMAXSD: return "vpmaxsd"; + case ND_INS_VPMAXSQ: return "vpmaxsq"; + case ND_INS_VPMAXSW: return "vpmaxsw"; + case ND_INS_VPMAXUB: return "vpmaxub"; + case ND_INS_VPMAXUD: return "vpmaxud"; + case ND_INS_VPMAXUQ: return "vpmaxuq"; + case ND_INS_VPMAXUW: return "vpmaxuw"; + case ND_INS_VPMINSB: return "vpminsb"; + case ND_INS_VPMINSD: return "vpminsd"; + case ND_INS_VPMINSQ: return "vpminsq"; + case ND_INS_VPMINSW: return "vpminsw"; + case ND_INS_VPMINUB: return "vpminub"; + case ND_INS_VPMINUD: return "vpminud"; + case ND_INS_VPMINUQ: return "vpminuq"; + case ND_INS_VPMINUW: return "vpminuw"; + case ND_INS_VPMOVB2M: return "vpmovb2m"; + case ND_INS_VPMOVD2M: return "vpmovd2m"; + case ND_INS_VPMOVDB: return "vpmovdb"; + case ND_INS_VPMOVDW: return "vpmovdw"; + case ND_INS_VPMOVM2B: return "vpmovm2b"; + case ND_INS_VPMOVM2D: return "vpmovm2d"; + case ND_INS_VPMOVM2Q: return "vpmovm2q"; + case ND_INS_VPMOVM2W: return "vpmovm2w"; + case ND_INS_VPMOVMSKB: return "vpmovmskb"; + case ND_INS_VPMOVQ2M: return "vpmovq2m"; + case ND_INS_VPMOVQB: return "vpmovqb"; + case ND_INS_VPMOVQD: return "vpmovqd"; + case ND_INS_VPMOVQW: return "vpmovqw"; + case ND_INS_VPMOVSDB: return "vpmovsdb"; + case ND_INS_VPMOVSDW: return "vpmovsdw"; + case ND_INS_VPMOVSQB: return "vpmovsqb"; + case ND_INS_VPMOVSQD: return "vpmovsqd"; + case ND_INS_VPMOVSQW: return "vpmovsqw"; + case ND_INS_VPMOVSWB: return "vpmovswb"; + case ND_INS_VPMOVSXBD: return "vpmovsxbd"; + case ND_INS_VPMOVSXBQ: return "vpmovsxbq"; + case ND_INS_VPMOVSXBW: return "vpmovsxbw"; + case ND_INS_VPMOVSXDQ: return "vpmovsxdq"; + case ND_INS_VPMOVSXWD: return "vpmovsxwd"; + case ND_INS_VPMOVSXWQ: return "vpmovsxwq"; + case ND_INS_VPMOVUSDB: return "vpmovusdb"; + case ND_INS_VPMOVUSDW: return "vpmovusdw"; + case ND_INS_VPMOVUSQB: return "vpmovusqb"; + case ND_INS_VPMOVUSQD: return "vpmovusqd"; + case ND_INS_VPMOVUSQW: return "vpmovusqw"; + case ND_INS_VPMOVUSWB: return "vpmovuswb"; + case ND_INS_VPMOVW2M: return "vpmovw2m"; + case ND_INS_VPMOVWB: return "vpmovwb"; + case ND_INS_VPMOVZXBD: return "vpmovzxbd"; + case ND_INS_VPMOVZXBQ: return "vpmovzxbq"; + case ND_INS_VPMOVZXBW: return "vpmovzxbw"; + case ND_INS_VPMOVZXDQ: return "vpmovzxdq"; + case ND_INS_VPMOVZXWD: return "vpmovzxwd"; + case ND_INS_VPMOVZXWQ: return "vpmovzxwq"; + case ND_INS_VPMULDQ: return "vpmuldq"; + case ND_INS_VPMULHRSW: return "vpmulhrsw"; + case ND_INS_VPMULHUW: return "vpmulhuw"; + case ND_INS_VPMULHW: return "vpmulhw"; + case ND_INS_VPMULLD: return "vpmulld"; + case ND_INS_VPMULLQ: return "vpmullq"; + case ND_INS_VPMULLW: return "vpmullw"; + case ND_INS_VPMULTISHIFTQB: return "vpmultishiftqb"; + case ND_INS_VPMULUDQ: return "vpmuludq"; + case ND_INS_VPOPCNTB: return "vpopcntb"; + case ND_INS_VPOPCNTD: return "vpopcntd"; + case ND_INS_VPOPCNTQ: return "vpopcntq"; + case ND_INS_VPOPCNTW: return "vpopcntw"; + case ND_INS_VPOR: return "vpor"; + case ND_INS_VPORD: return "vpord"; + case ND_INS_VPORQ: return "vporq"; + case ND_INS_VPPERM: return "vpperm"; + case ND_INS_VPROLD: return "vprold"; + case ND_INS_VPROLQ: return "vprolq"; + case ND_INS_VPROLVD: return "vprolvd"; + case ND_INS_VPROLVQ: return "vprolvq"; + case ND_INS_VPRORD: return "vprord"; + case ND_INS_VPRORQ: return "vprorq"; + case ND_INS_VPRORVD: return "vprorvd"; + case ND_INS_VPRORVQ: return "vprorvq"; + case ND_INS_VPROTB: return "vprotb"; + case ND_INS_VPROTD: return "vprotd"; + case ND_INS_VPROTQ: return "vprotq"; + case ND_INS_VPROTW: return "vprotw"; + case ND_INS_VPSADBW: return "vpsadbw"; + case ND_INS_VPSCATTERDD: return "vpscatterdd"; + case ND_INS_VPSCATTERDQ: return "vpscatterdq"; + case ND_INS_VPSCATTERQD: return "vpscatterqd"; + case ND_INS_VPSCATTERQQ: return "vpscatterqq"; + case ND_INS_VPSHAB: return "vpshab"; + case ND_INS_VPSHAD: return "vpshad"; + case ND_INS_VPSHAQ: return "vpshaq"; + case ND_INS_VPSHAW: return "vpshaw"; + case ND_INS_VPSHLB: return "vpshlb"; + case ND_INS_VPSHLDD: return "vpshldd"; + case ND_INS_VPSHLDQ: return "vpshldq"; + case ND_INS_VPSHLDVD: return "vpshldvd"; + case ND_INS_VPSHLDVQ: return "vpshldvq"; + case ND_INS_VPSHLDVW: return "vpshldvw"; + case ND_INS_VPSHLDW: return "vpshldw"; + case ND_INS_VPSHLQ: return "vpshlq"; + case ND_INS_VPSHRDD: return "vpshrdd"; + case ND_INS_VPSHRDQ: return "vpshrdq"; + case ND_INS_VPSHRDVD: return "vpshrdvd"; + case ND_INS_VPSHRDVQ: return "vpshrdvq"; + case ND_INS_VPSHRDVW: return "vpshrdvw"; + case ND_INS_VPSHRDW: return "vpshrdw"; + case ND_INS_VPSHUFB: return "vpshufb"; + case ND_INS_VPSHUFBITQMB: return "vpshufbitqmb"; + case ND_INS_VPSHUFD: return "vpshufd"; + case ND_INS_VPSHUFHW: return "vpshufhw"; + case ND_INS_VPSHUFLW: return "vpshuflw"; + case ND_INS_VPSIGNB: return "vpsignb"; + case ND_INS_VPSIGND: return "vpsignd"; + case ND_INS_VPSIGNW: return "vpsignw"; + case ND_INS_VPSLLD: return "vpslld"; + case ND_INS_VPSLLDQ: return "vpslldq"; + case ND_INS_VPSLLQ: return "vpsllq"; + case ND_INS_VPSLLVD: return "vpsllvd"; + case ND_INS_VPSLLVQ: return "vpsllvq"; + case ND_INS_VPSLLVW: return "vpsllvw"; + case ND_INS_VPSLLW: return "vpsllw"; + case ND_INS_VPSRAD: return "vpsrad"; + case ND_INS_VPSRAQ: return "vpsraq"; + case ND_INS_VPSRAVD: return "vpsravd"; + case ND_INS_VPSRAVQ: return "vpsravq"; + case ND_INS_VPSRAVW: return "vpsravw"; + case ND_INS_VPSRAW: return "vpsraw"; + case ND_INS_VPSRLD: return "vpsrld"; + case ND_INS_VPSRLDQ: return "vpsrldq"; + case ND_INS_VPSRLQ: return "vpsrlq"; + case ND_INS_VPSRLVD: return "vpsrlvd"; + case ND_INS_VPSRLVQ: return "vpsrlvq"; + case ND_INS_VPSRLVW: return "vpsrlvw"; + case ND_INS_VPSRLW: return "vpsrlw"; + case ND_INS_VPSUBB: return "vpsubb"; + case ND_INS_VPSUBD: return "vpsubd"; + case ND_INS_VPSUBQ: return "vpsubq"; + case ND_INS_VPSUBSB: return "vpsubsb"; + case ND_INS_VPSUBSW: return "vpsubsw"; + case ND_INS_VPSUBUSB: return "vpsubusb"; + case ND_INS_VPSUBUSW: return "vpsubusw"; + case ND_INS_VPSUBW: return "vpsubw"; + case ND_INS_VPTERNLOGD: return "vpternlogd"; + case ND_INS_VPTERNLOGQ: return "vpternlogq"; + case ND_INS_VPTEST: return "vptest"; + case ND_INS_VPTESTMB: return "vptestmb"; + case ND_INS_VPTESTMD: return "vptestmd"; + case ND_INS_VPTESTMQ: return "vptestmq"; + case ND_INS_VPTESTMW: return "vptestmw"; + case ND_INS_VPTESTNMB: return "vptestnmb"; + case ND_INS_VPTESTNMD: return "vptestnmd"; + case ND_INS_VPTESTNMQ: return "vptestnmq"; + case ND_INS_VPTESTNMW: return "vptestnmw"; + case ND_INS_VPUNPCKHBW: return "vpunpckhbw"; + case ND_INS_VPUNPCKHDQ: return "vpunpckhdq"; + case ND_INS_VPUNPCKHQDQ: return "vpunpckhqdq"; + case ND_INS_VPUNPCKHWD: return "vpunpckhwd"; + case ND_INS_VPUNPCKLBW: return "vpunpcklbw"; + case ND_INS_VPUNPCKLDQ: return "vpunpckldq"; + case ND_INS_VPUNPCKLQDQ: return "vpunpcklqdq"; + case ND_INS_VPUNPCKLWD: return "vpunpcklwd"; + case ND_INS_VPXOR: return "vpxor"; + case ND_INS_VPXORD: return "vpxord"; + case ND_INS_VPXORQ: return "vpxorq"; + case ND_INS_VRANGEPD: return "vrangepd"; + case ND_INS_VRANGEPS: return "vrangeps"; + case ND_INS_VRANGESD: return "vrangesd"; + case ND_INS_VRANGESS: return "vrangess"; + case ND_INS_VRCP14PD: return "vrcp14pd"; + case ND_INS_VRCP14PS: return "vrcp14ps"; + case ND_INS_VRCP14SD: return "vrcp14sd"; + case ND_INS_VRCP14SS: return "vrcp14ss"; + case ND_INS_VRCP28PD: return "vrcp28pd"; + case ND_INS_VRCP28PS: return "vrcp28ps"; + case ND_INS_VRCP28SD: return "vrcp28sd"; + case ND_INS_VRCP28SS: return "vrcp28ss"; + case ND_INS_VRCPPS: return "vrcpps"; + case ND_INS_VRCPSS: return "vrcpss"; + case ND_INS_VREDUCEPD: return "vreducepd"; + case ND_INS_VREDUCEPS: return "vreduceps"; + case ND_INS_VREDUCESD: return "vreducesd"; + case ND_INS_VREDUCESS: return "vreducess"; + case ND_INS_VRNDSCALEPD: return "vrndscalepd"; + case ND_INS_VRNDSCALEPS: return "vrndscaleps"; + case ND_INS_VRNDSCALESD: return "vrndscalesd"; + case ND_INS_VRNDSCALESS: return "vrndscaless"; + case ND_INS_VROUNDPD: return "vroundpd"; + case ND_INS_VROUNDPS: return "vroundps"; + case ND_INS_VROUNDSD: return "vroundsd"; + case ND_INS_VROUNDSS: return "vroundss"; + case ND_INS_VRSQRT14PD: return "vrsqrt14pd"; + case ND_INS_VRSQRT14PS: return "vrsqrt14ps"; + case ND_INS_VRSQRT14SD: return "vrsqrt14sd"; + case ND_INS_VRSQRT14SS: return "vrsqrt14ss"; + case ND_INS_VRSQRT28PD: return "vrsqrt28pd"; + case ND_INS_VRSQRT28PS: return "vrsqrt28ps"; + case ND_INS_VRSQRT28SD: return "vrsqrt28sd"; + case ND_INS_VRSQRT28SS: return "vrsqrt28ss"; + case ND_INS_VRSQRTPS: return "vrsqrtps"; + case ND_INS_VRSQRTSS: return "vrsqrtss"; + case ND_INS_VSCALEFPD: return "vscalefpd"; + case ND_INS_VSCALEFPS: return "vscalefps"; + case ND_INS_VSCALEFSD: return "vscalefsd"; + case ND_INS_VSCALEFSS: return "vscalefss"; + case ND_INS_VSCATTERDPD: return "vscatterdpd"; + case ND_INS_VSCATTERDPS: return "vscatterdps"; + case ND_INS_VSCATTERPF0DPD: return "vscatterpf0dpd"; + case ND_INS_VSCATTERPF0DPS: return "vscatterpf0dps"; + case ND_INS_VSCATTERPF0QPD: return "vscatterpf0qpd"; + case ND_INS_VSCATTERPF0QPS: return "vscatterpf0qps"; + case ND_INS_VSCATTERPF1DPD: return "vscatterpf1dpd"; + case ND_INS_VSCATTERPF1DPS: return "vscatterpf1dps"; + case ND_INS_VSCATTERPF1QPD: return "vscatterpf1qpd"; + case ND_INS_VSCATTERPF1QPS: return "vscatterpf1qps"; + case ND_INS_VSCATTERQPD: return "vscatterqpd"; + case ND_INS_VSCATTERQPS: return "vscatterqps"; + case ND_INS_VSHUFF32X4: return "vshuff32x4"; + case ND_INS_VSHUFF64X2: return "vshuff64x2"; + case ND_INS_VSHUFI32X4: return "vshufi32x4"; + case ND_INS_VSHUFI64X2: return "vshufi64x2"; + case ND_INS_VSHUFPD: return "vshufpd"; + case ND_INS_VSHUFPS: return "vshufps"; + case ND_INS_VSQRTPD: return "vsqrtpd"; + case ND_INS_VSQRTPS: return "vsqrtps"; + case ND_INS_VSQRTSD: return "vsqrtsd"; + case ND_INS_VSQRTSS: return "vsqrtss"; + case ND_INS_VSTMXCSR: return "vstmxcsr"; + case ND_INS_VSUBPD: return "vsubpd"; + case ND_INS_VSUBPS: return "vsubps"; + case ND_INS_VSUBSD: return "vsubsd"; + case ND_INS_VSUBSS: return "vsubss"; + case ND_INS_VTESTPD: return "vtestpd"; + case ND_INS_VTESTPS: return "vtestps"; + case ND_INS_VUCOMISD: return "vucomisd"; + case ND_INS_VUCOMISS: return "vucomiss"; + case ND_INS_VUNPCKHPD: return "vunpckhpd"; + case ND_INS_VUNPCKHPS: return "vunpckhps"; + case ND_INS_VUNPCKLPD: return "vunpcklpd"; + case ND_INS_VUNPCKLPS: return "vunpcklps"; + case ND_INS_VXORPD: return "vxorpd"; + case ND_INS_VXORPS: return "vxorps"; + case ND_INS_VZEROALL: return "vzeroall"; + case ND_INS_VZEROUPPER: return "vzeroupper"; + case ND_INS_WAIT: return "wait"; + case ND_INS_WBINVD: return "wbinvd"; + case ND_INS_WBNOINVD: return "wbnoinvd"; + case ND_INS_WRFSBASE: return "wrfsbase"; + case ND_INS_WRGSBASE: return "wrgsbase"; + case ND_INS_WRMSR: return "wrmsr"; + case ND_INS_WRPKRU: return "wrpkru"; + case ND_INS_WRSHR: return "wrshr"; + case ND_INS_WRSS: return "wrss"; + case ND_INS_WRUSS: return "wruss"; + case ND_INS_XABORT: return "xabort"; + case ND_INS_XADD: return "xadd"; + case ND_INS_XBEGIN: return "xbegin"; + case ND_INS_XCHG: return "xchg"; + case ND_INS_XCRYPTCBC: return "xcryptcbc"; + case ND_INS_XCRYPTCFB: return "xcryptcfb"; + case ND_INS_XCRYPTCTR: return "xcryptctr"; + case ND_INS_XCRYPTECB: return "xcryptecb"; + case ND_INS_XCRYPTOFB: return "xcryptofb"; + case ND_INS_XEND: return "xend"; + case ND_INS_XGETBV: return "xgetbv"; + case ND_INS_XLATB: return "xlatb"; + case ND_INS_XOR: return "xor"; + case ND_INS_XORPD: return "xorpd"; + case ND_INS_XORPS: return "xorps"; + case ND_INS_XRESLDTRK: return "xresldtrik"; + case ND_INS_XRSTOR: return "xrstor"; + case ND_INS_XRSTORS: return "xrstors"; + case ND_INS_XSAVE: return "xsave"; + case ND_INS_XSAVEC: return "xsavec"; + case ND_INS_XSAVEOPT: return "xsaveopt"; + case ND_INS_XSAVES: return "xsaves"; + case ND_INS_XSETBV: return "xsetbv"; + case ND_INS_XSHA1: return "xsha1"; + case ND_INS_XSHA256: return "xsha256"; + case ND_INS_XSUSLDTRK: return "xsusldtrk"; + case ND_INS_XSTORE: return "xstore"; + case ND_INS_XTEST: return "xtest"; + } + + return ""; +} + + +std::string ins_cat_to_str(ND_INS_CATEGORY category) +{ + switch (category) { + case ND_CAT_INVALID: return "invalid"; + case ND_CAT_3DNOW: return "3dnow"; + case ND_CAT_AES: return "aes"; + case ND_CAT_AMX: return "amx"; + case ND_CAT_ARITH: return "arith"; + case ND_CAT_AVX: return "avx"; + case ND_CAT_AVX2: return "avx2"; + case ND_CAT_AVX2GATHER: return "avx2gather"; + case ND_CAT_AVX512: return "avx512"; + case ND_CAT_AVX512BF16: return "avx512bf16"; + case ND_CAT_AVX512VBMI: return "avx512vbmi"; + case ND_CAT_AVX512VP2INTERSECT: return "avx512vp2intersect"; + case ND_CAT_BITBYTE: return "bitbyte"; + case ND_CAT_BLEND: return "blend"; + case ND_CAT_BMI1: return "bmi1"; + case ND_CAT_BMI2: return "bmi2"; + case ND_CAT_BROADCAST: return "broadcast"; + case ND_CAT_CALL: return "call"; + case ND_CAT_CET: return "cet"; + case ND_CAT_CLDEMOTE: return "cldemote"; + case ND_CAT_CMOV: return "cmov"; + case ND_CAT_COMPRESS: return "compress"; + case ND_CAT_COND_BR: return "cond_br"; + case ND_CAT_CONFLICT: return "conflict"; + case ND_CAT_CONVERT: return "convert"; + case ND_CAT_DATAXFER: return "dataxfer"; + case ND_CAT_DECIMAL: return "decimal"; + case ND_CAT_ENQCMD: return "enqcmd"; + case ND_CAT_EXPAND: return "expand"; + case ND_CAT_FLAGOP: return "flagop"; + case ND_CAT_FMA4: return "fma4"; + case ND_CAT_GATHER: return "gather"; + case ND_CAT_GFNI: return "gfni"; + case ND_CAT_I386: return "i386"; + case ND_CAT_IFMA: return "ifma"; + case ND_CAT_INTERRUPT: return "interrupt"; + case ND_CAT_IO: return "io"; + case ND_CAT_IOSTRINGOP: return "iostringop"; + case ND_CAT_KMASK: return "kmask"; + case ND_CAT_KNL: return "knl"; + case ND_CAT_LOGIC: return "logic"; + case ND_CAT_LOGICAL: return "logical"; + case ND_CAT_LOGICAL_FP: return "logical_fp"; + case ND_CAT_LWP: return "lwp"; + case ND_CAT_LZCNT: return "lzcnt"; + case ND_CAT_MISC: return "misc"; + case ND_CAT_MMX: return "mmx"; + case ND_CAT_MOVDIR64B: return "movdir64b"; + case ND_CAT_MOVDIRI: return "movdiri"; + case ND_CAT_MPX: return "mpx"; + case ND_CAT_NOP: return "nop"; + case ND_CAT_PADLOCK: return "padlock"; + case ND_CAT_PCLMULQDQ: return "pclmulqdq"; + case ND_CAT_PCONFIG: return "pconfig"; + case ND_CAT_POP: return "pop"; + case ND_CAT_PREFETCH: return "prefetch"; + case ND_CAT_PTWRITE: return "ptwrite"; + case ND_CAT_PUSH: return "push"; + case ND_CAT_RDPID: return "rdpid"; + case ND_CAT_RDRAND: return "rdrand"; + case ND_CAT_RDSEED: return "rdseed"; + case ND_CAT_RDWRFSGS: return "rdwrfsgs"; + case ND_CAT_RET: return "ret"; + case ND_CAT_ROTATE: return "rotate"; + case ND_CAT_SCATTER: return "scatter"; + case ND_CAT_SEGOP: return "segop"; + case ND_CAT_SEMAPHORE: return "semaphore"; + case ND_CAT_SGX: return "sgx"; + case ND_CAT_SHA: return "sha"; + case ND_CAT_SHIFT: return "shift"; + case ND_CAT_SMAP: return "smap"; + case ND_CAT_SSE: return "sse"; + case ND_CAT_SSE2: return "sse2"; + case ND_CAT_STRINGOP: return "stringop"; + case ND_CAT_STTNI: return "sttni"; + case ND_CAT_SYSCALL: return "syscall"; + case ND_CAT_SYSRET: return "sysret"; + case ND_CAT_SYSTEM: return "system"; + case ND_CAT_UD: return "ud"; + case ND_CAT_UNCOND_BR: return "uncond_br"; + case ND_CAT_UNDOC: return "undoc"; + case ND_CAT_UNKNOWN: return "unknown"; + case ND_CAT_VAES: return "vaes"; + case ND_CAT_VFMA: return "vfma"; + case ND_CAT_VFMAPS: return "vfmaps"; + case ND_CAT_VNNI: return "vnni"; + case ND_CAT_VNNIW: return "vnniw"; + case ND_CAT_VPCLMULQDQ: return "vpclmulqdq"; + case ND_CAT_VPOPCNT: return "vpopcnt"; + case ND_CAT_VTX: return "vtx"; + case ND_CAT_WAITPKG: return "waitpkg"; + case ND_CAT_WBNOINVD: return "wbnoinvd"; + case ND_CAT_WIDENOP: return "widenop"; + case ND_CAT_X87_ALU: return "x87_alu"; + case ND_CAT_XOP: return "xop"; + case ND_CAT_XSAVE: return "xsave"; + } + + return ""; +} + + +std::string ins_set_to_str(ND_INS_SET ins_set) +{ + switch (ins_set) { + case ND_SET_INVALID: return "invalid"; + case ND_SET_3DNOW: return "3dnow"; + case ND_SET_ADX: return "adx"; + case ND_SET_AES: return "aes"; + case ND_SET_AMD: return "amd"; + case ND_SET_AMXBF16: return "amxbf16"; + case ND_SET_AMXINT8: return "amxint8"; + case ND_SET_AMXTILE: return "amxtile"; + case ND_SET_AVX: return "avx"; + case ND_SET_AVX2: return "avx2"; + case ND_SET_AVX2GATHER: return "avx2gather"; + case ND_SET_AVX5124FMAPS: return "avx5124fmaps"; + case ND_SET_AVX5124VNNIW: return "avx5124vnniw"; + case ND_SET_AVX512BF16: return "avx512bf16"; + case ND_SET_AVX512BITALG: return "avx512bitalg"; + case ND_SET_AVX512BW: return "avx512bw"; + case ND_SET_AVX512CD: return "avx512cd"; + case ND_SET_AVX512DQ: return "avx512dq"; + case ND_SET_AVX512ER: return "avx512er"; + case ND_SET_AVX512F: return "avx512f"; + case ND_SET_AVX512IFMA: return "avx512ifma"; + case ND_SET_AVX512PF: return "avx512pf"; + case ND_SET_AVX512VBMI: return "avx512vbmi"; + case ND_SET_AVX512VBMI2: return "avx512vbmi2"; + case ND_SET_AVX512VNNI: return "avx512vnni"; + case ND_SET_AVX512VP2INTERSECT: return "avx512vp2intersect"; + case ND_SET_AVX512VPOPCNTDQ: return "avx512vpopcntdq"; + case ND_SET_BMI1: return "bmi1"; + case ND_SET_BMI2: return "bmi2"; + case ND_SET_CET: return "cet"; + case ND_SET_CLDEMOTE: return "cldemote"; + case ND_SET_CLFSH: return "clfsh"; + case ND_SET_CLFSHOPT: return "clfshopt"; + case ND_SET_CLWB: return "clwb"; + case ND_SET_CLZERO: return "clzero"; + case ND_SET_CMPXCHG16B: return "cmpxchg16b"; + case ND_SET_CYRIX: return "cyrix"; + case ND_SET_CYRIX_SMM: return "cyrix_smm"; + case ND_SET_ENQCMD: return "enqcmd"; + case ND_SET_F16C: return "f16c"; + case ND_SET_FMA: return "fma"; + case ND_SET_FMA4: return "fma4"; + case ND_SET_FXSAVE: return "fxsave"; + case ND_SET_GFNI: return "gfni"; + case ND_SET_I186: return "i186"; + case ND_SET_INVLPGB: return "invlpgb"; + case ND_SET_I286PROT: return "i286prot"; + case ND_SET_I286REAL: return "i286real"; + case ND_SET_I386: return "i386"; + case ND_SET_I486: return "i486"; + case ND_SET_I486REAL: return "i486real"; + case ND_SET_I64: return "i64"; + case ND_SET_I86: return "i86"; + case ND_SET_INVPCID: return "invpcid"; + case ND_SET_LONGMODE: return "longmode"; + case ND_SET_LWP: return "lwp"; + case ND_SET_LZCNT: return "lzcnt"; + case ND_SET_MCOMMIT: return "mcommit"; + case ND_SET_MMX: return "mmx"; + case ND_SET_MOVBE: return "movbe"; + case ND_SET_MOVDIR64B: return "movdir64b"; + case ND_SET_MOVDIRI: return "movdiri"; + case ND_SET_MPX: return "mpx"; + case ND_SET_MWAITT: return "mwaitt"; + case ND_SET_PAUSE: return "pause"; + case ND_SET_PCLMULQDQ: return "pclmulqdq"; + case ND_SET_PCOMMIT: return "pcommit"; + case ND_SET_PCONFIG: return "pconfig"; + case ND_SET_PENTIUMREAL: return "pentiumreal"; + case ND_SET_PKU: return "pku"; + case ND_SET_POPCNT: return "popcnt"; + case ND_SET_PPRO: return "ppro"; + case ND_SET_PREFETCH_NOP: return "prefetch_nop"; + case ND_SET_PTWRITE: return "ptwrite"; + case ND_SET_RDPID: return "rdpid"; + case ND_SET_RDPMC: return "rdpmc"; + case ND_SET_RDPRU: return "rdpru"; + case ND_SET_RDRAND: return "rdrand"; + case ND_SET_RDSEED: return "rdseed"; + case ND_SET_RDTSCP: return "rdtscp"; + case ND_SET_RDWRFSGS: return "rdwrfsgs"; + case ND_SET_SCC: return "scc"; + case ND_SET_SERIALIZE: return "serialize"; + case ND_SET_SGX: return "sgx"; + case ND_SET_SHA: return "sha"; + case ND_SET_SMAP: return "smap"; + case ND_SET_SMX: return "smx"; + case ND_SET_SNP: return "snp"; + case ND_SET_SSE: return "sse"; + case ND_SET_SSE2: return "sse2"; + case ND_SET_SSE3: return "sse3"; + case ND_SET_SSE4: return "sse4"; + case ND_SET_SSE42: return "sse42"; + case ND_SET_SSE4A: return "sse4a"; + case ND_SET_SSSE3: return "ssse3"; + case ND_SET_SVM: return "svm"; + case ND_SET_TBM: return "tbm"; + case ND_SET_TSX: return "tsx"; + case ND_SET_TSXLDTRK: return "tsxldtrk"; + case ND_SET_UD: return "ud"; + case ND_SET_UNKNOWN: return "unknown"; + case ND_SET_VAES: return "vaes"; + case ND_SET_VPCLMULQDQ: return "vpclmulqdq"; + case ND_SET_VTX: return "vtx"; + case ND_SET_WAITPKG: return "waitpkg"; + case ND_SET_WBNOINVD: return "wbnoinvd"; + case ND_SET_X87: return "x87"; + case ND_SET_XOP: return "xop"; + case ND_SET_XSAVE: return "xsave"; + case ND_SET_XSAVEC: return "xsavec"; + case ND_SET_XSAVES: return "xsaves"; + } + + return ""; +} + + +std::string reg_to_str(const int reg, const ND_REG_TYPE type) +{ + switch (type) { + case ND_REG_NOT_PRESENT: + return "not_preset"; + + case ND_REG_GPR: + switch (reg) { + case REG_RAX: return "rax"; + case REG_RCX: return "rcx"; + case REG_RDX: return "rdx"; + case REG_RBX: return "rbx"; + case REG_RSP: return "rsp"; + case REG_RBP: return "rbp"; + case REG_RSI: return "rsi"; + case REG_RDI: return "rdi"; + case REG_R8: return "r8"; + case REG_R9: return "r9"; + case REG_R10: return "r10"; + case REG_R11: return "r11"; + case REG_R12: return "r12"; + case REG_R13: return "r13"; + case REG_R14: return "r14"; + case REG_R15: return "r15"; + } + + return ""; + + case ND_REG_SEG: + switch (reg) { + case REG_ES: return "es"; + case REG_CS: return "cs"; + case REG_SS: return "ss"; + case REG_DS: return "ds"; + case REG_FS: return "fs"; + case REG_GS: return "gs"; + case REG_INV6: return "inv6"; + case REG_INV7: return "inv7"; + } + + return ""; + + case ND_REG_FPU: + return "fpu"; + case ND_REG_MMX: + return "mmx"; + case ND_REG_SSE: + return "sse"; + case ND_REG_CR: + return "cr"; + case ND_REG_DR: + return "dr"; + case ND_REG_TR: + return "tr"; + case ND_REG_BND: + return "bnd"; + case ND_REG_MSK: + return "msk"; + case ND_REG_TILE: + return "tile"; + case ND_REG_MSR: + return "msr"; + case ND_REG_XCR: + return "xcr"; + case ND_REG_SYS: + return "sys"; + case ND_REG_X87: + return "x87"; + case ND_REG_MXCSR: + return "mxcsr"; + case ND_REG_PKRU: + return "pkru"; + case ND_REG_SSP: + return "ssp"; + case ND_REG_FLG: + return "flg"; + case ND_REG_RIP: + return "rip"; + } + + return ""; +} + + +std::string reg_type_to_str(const ND_REG_TYPE type) +{ + switch (type) { + case ND_REG_NOT_PRESENT: + return "present"; + case ND_REG_GPR: + return "gpr"; + case ND_REG_SEG: + return "seg"; + case ND_REG_FPU: + return "fpu"; + case ND_REG_MMX: + return "mmx"; + case ND_REG_SSE: + return "sse"; + case ND_REG_CR: + return "cr"; + case ND_REG_DR: + return "dr"; + case ND_REG_TR: + return "tr"; + case ND_REG_BND: + return "bnd"; + case ND_REG_MSK: + return "msk"; + case ND_REG_TILE: + return "tile"; + case ND_REG_MSR: + return "msr"; + case ND_REG_XCR: + return "xcr"; + case ND_REG_SYS: + return "sys"; + case ND_REG_X87: + return "x87"; + case ND_REG_MXCSR: + return "mxcsr"; + case ND_REG_PKRU: + return "pkru"; + case ND_REG_SSP: + return "ssp"; + case ND_REG_FLG: + return "flg"; + case ND_REG_RIP: + return "rip"; + } + + return ""; +} diff --git a/disasmtool_lix/external/argparse.h b/disasmtool_lix/external/argparse.h new file mode 100644 index 0000000..0a7f930 --- /dev/null +++ b/disasmtool_lix/external/argparse.h @@ -0,0 +1,276 @@ +/** + * argparse.h is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License v3 as published by + * the Free Software Foundation. + * + * argparse.h is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with argparse.h. If not, see . + * + * Author: Jesse Laning + */ + +#ifndef ARGPARSE_H +#define ARGPARSE_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +class ArgumentParser { + private: + struct Argument; + + public: + class ArgumentNotFound : public std::runtime_error { + public: + ArgumentNotFound(ArgumentParser::Argument &arg) noexcept + : std::runtime_error( + ("Required argument not found: " + arg._name).c_str()) {} + }; + + ArgumentParser(const std::string &desc) : _desc(desc), _help(false) {} + ArgumentParser(const std::string desc, int argc, char *argv[]) + : ArgumentParser(desc) { + parse(argc, argv); + } + + void add_argument(const std::string &name, const std::string &long_name, + const std::string &desc, const bool required = false) { + _arguments.push_back({name, desc, required}); + _pairs[name] = long_name; + } + + void add_argument(const std::string &name, const std::string &desc, + const bool required = false) { + _arguments.push_back({name, desc, required}); + } + + bool is_help() { return _help; } + + void print_help() { + std::cout << "Usage: " << _bin << " [options]" << std::endl; + std::cout << "Options:" << std::endl; + for (auto &a : _arguments) { + std::string name = a._name; + auto i = _pairs.find(name); + if (i != _pairs.end()) name.append(", " + i->second); + std::cout << " " << std::setw(23) << std::left << name << std::setw(23) + << a._desc + (a._required ? " (Required)" : "") << std::endl; + } + } + + void parse(int argc, char *argv[]) { + _bin = argv[0]; + if (argc > 1) { + std::string name; + std::vector arg_parts; + std::vector free_args; + auto push_arg = [&name, &arg_parts, this]() { + if (!name.empty()) { + if (name[0] == '-') { + _add_variable(name, arg_parts); + } else { + for (char c : name) { + _add_variable(std::string(1, c), arg_parts); + } + } + arg_parts.clear(); + } + }; + for (int i = 1; i < argc; i++) { + size_t slen = std::strlen(argv[i]); + if (slen == 0) { + continue; + } else if (slen >= 2 && argv[i][0] == '-' && !_is_number(argv[i])) { + push_arg(); + if (i == argc - 1) { + name = &(argv[i][1]); + push_arg(); + } else { + name = &(argv[i][1]); + } + } else if (name.empty()) { + free_args.push_back(argv[i]); + } else { + arg_parts.push_back(argv[i]); + if (i == argc - 1) { + push_arg(); + } + } + } + _add_variable("", free_args); + } + if (!_help) { + for (auto &a : _arguments) { + if (a._required) { + if (_variables.find(a._name) == _variables.end()) { + throw ArgumentNotFound(a); + } + } + } + } + } + + bool exists(const std::string &name) { + std::string t = _delimit(name); + if (_pairs.find(t) != _pairs.end()) t = _pairs[t]; + return _variables.find(t) != _variables.end(); + } + + template + std::vector getv(const std::string &name) { + std::vector argstr = getv(name); + std::vector v; + for (auto &s : argstr) { + std::istringstream in(s); + T t; + in >> t; + v.push_back(t); + } + return v; + } + + template + T get(const std::string &name) { + std::istringstream in(get(name)); + T t; + in >> t >> std::ws; + return t; + } + + private: + friend class ArgumentNotFound; + struct Argument { + public: + Argument(const std::string &name, const std::string &desc, + bool required = false) + : _name(name), _desc(desc), _required(required) {} + + std::string _name; + std::string _desc; + bool _required; + }; + inline void _add_variable(std::string name, + std::vector &arg_parts) { + if (name == "h" || name == "-help") { + _help = true; + print_help(); + } + _ltrim(name, [](int c) { return c != (int)'-'; }); + name = _delimit(name); + if (_pairs.find(name) != _pairs.end()) name = _pairs[name]; + _variables[name] = arg_parts; + } + static std::string _delimit(const std::string &name) { + return std::string(std::min(name.size(), (size_t)2), '-').append(name); + } + static std::string _strip(const std::string &name) { + size_t begin = 0; + begin += name.size() > 0 ? name[0] == '-' : 0; + begin += name.size() > 3 ? name[1] == '-' : 0; + return name.substr(begin); + } + static std::string _upper(const std::string &in) { + std::string out(in); + std::transform(out.begin(), out.end(), out.begin(), ::toupper); + return out; + } + static std::string _escape(const std::string &in) { + std::string out(in); + if (in.find(' ') != std::string::npos) + out = std::string("\"").append(out).append("\""); + return out; + } + static bool _not_space(int ch) { return !std::isspace(ch); } + static inline void _ltrim(std::string &s, bool (*f)(int) = _not_space) { + s.erase(s.begin(), std::find_if(s.begin(), s.end(), f)); + } + static inline void _rtrim(std::string &s, bool (*f)(int) = _not_space) { + s.erase(std::find_if(s.rbegin(), s.rend(), f).base(), s.end()); + } + static inline void _trim(std::string &s, bool (*f)(int) = _not_space) { + _ltrim(s, f); + _rtrim(s, f); + } + static inline std::string _ltrim_copy(std::string s, + bool (*f)(int) = _not_space) { + _ltrim(s, f); + return s; + } + static inline std::string _rtrim_copy(std::string s, + bool (*f)(int) = _not_space) { + _rtrim(s, f); + return s; + } + static inline std::string _trim_copy(std::string s, + bool (*f)(int) = _not_space) { + _trim(s, f); + return s; + } + template + inline std::string _join(InputIt begin, InputIt end, + const std::string &separator = " ") { + std::ostringstream ss; + if (begin != end) { + ss << *begin++; + } + while (begin != end) { + ss << separator; + ss << *begin++; + } + return ss.str(); + } + static inline bool _is_number(const char *arg) { + std::istringstream iss{std::string(arg)}; + float f; + iss >> std::noskipws >> f; + return iss.eof() && !iss.fail(); + } + + std::string _desc; + std::string _bin; + bool _help; + std::vector _arguments; + std::unordered_map> _variables; + std::unordered_map _pairs; +}; +template <> +inline std::string ArgumentParser::get(const std::string &name) { + std::string t = _delimit(name); + if (_pairs.find(t) != _pairs.end()) t = _pairs[t]; + auto v = _variables.find(t); + if (v != _variables.end()) { + return _join(v->second.begin(), v->second.end()); + } + return ""; +} +template <> +inline bool ArgumentParser::get(const std::string &name) { + return exists(name); +} +template <> +inline std::vector ArgumentParser::getv( + const std::string &name) { + std::string t = _delimit(name); + if (_pairs.find(t) != _pairs.end()) t = _pairs[t]; + auto v = _variables.find(t); + if (v != _variables.end()) { + return v->second; + } + return std::vector(); +} +#endif diff --git a/disasmtool_lix/rapidjson.cpp b/disasmtool_lix/rapidjson.cpp new file mode 100644 index 0000000..6377a95 --- /dev/null +++ b/disasmtool_lix/rapidjson.cpp @@ -0,0 +1,1174 @@ +/* + * Copyright (c) 2020 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +#include "disasm.hpp" + +#include + +#include +#include + + +using namespace rapidjson; + + +static void _start_object(Writer &writer) +{ + writer.StartObject(); +} + + +static void _start_object(Writer &writer, const char *key) +{ + writer.Key(key); + writer.StartObject(); +} + +static void _end_object(Writer &writer) +{ + writer.EndObject(); +} + + +static void _start_array(Writer &writer) +{ + writer.StartArray(); +} + + +static void _start_array(Writer &writer, const char *key) +{ + writer.Key(key); + writer.StartArray(); +} + +static void _end_array(Writer &writer) +{ + writer.EndArray(); +} + + +static void _write_uint(Writer &writer, unsigned int value) +{ + writer.Uint(value); +} + + +static void _write_uint(Writer &writer, const char *key, unsigned int value) +{ + writer.Key(key); + writer.Uint(value); +} + + +static void _write_int(Writer &writer, int value) +{ + writer.Int(value); +} + + +static void _write_int(Writer &writer, const char *key, int value) +{ + writer.Key(key); + writer.Int(value); +} + + +static void _write_uint64(Writer &writer, uint64_t value) +{ + writer.Int(value); +} + + +static void _write_uint64(Writer &writer, const char *key, uint64_t value) +{ + writer.Key(key); + writer.Int(value); +} + + +static void _write_int64(Writer &writer, int64_t value) +{ + writer.Int(value); +} + + +static void _write_int64(Writer &writer, const char *key, int64_t value) +{ + writer.Key(key); + writer.Int(value); +} + + +static void _write_string(Writer &writer, const std::string& value) +{ + writer.String(value.c_str()); +} + + +static void _write_string(Writer &writer, const char *key, const std::string& value) +{ + writer.Key(key); + writer.String(value.c_str()); +} + + +static void _write_string(Writer &writer, const char *value) +{ + writer.String(value); +} + + +static void _write_string(Writer &writer, const char *key, const char *value) +{ + writer.Key(key); + writer.String(value); +} + + +static void _write_bool(Writer &writer, bool value) +{ + writer.Bool(value); +} + + +static void _write_bool(Writer &writer, const char *key, bool value) +{ + writer.Key(key); + writer.Bool(value); +} + + +static int _disasm_size_to_int(const uint8_t mode) +{ + switch (mode) { + case 0: return 16; + case 1: return 32; + case 2: return 64; + } + + return mode; +} + + +static void _write_rex(Writer &writer, const INSTRUX *instrux) +{ + if (!instrux->HasRex) + return; + + _start_object(writer, "rex"); + + _write_uint(writer, "value", instrux->Rex.Rex); + + _write_uint(writer, "b", static_cast(instrux->Rex.b)); + _write_uint(writer, "x", static_cast(instrux->Rex.x)); + _write_uint(writer, "r", static_cast(instrux->Rex.r)); + _write_uint(writer, "w", static_cast(instrux->Rex.w)); + + _end_object(writer); +} + + +static void _write_modrm(Writer &writer, const INSTRUX *instrux) +{ + if (!instrux->HasModRm) + return; + + _start_object(writer, "modrm"); + + _write_uint(writer, "value", instrux->ModRm.ModRm); + _write_uint(writer, "rm", static_cast(instrux->ModRm.rm)); + _write_uint(writer, "reg", static_cast(instrux->ModRm.reg)); + _write_uint(writer, "mod", static_cast(instrux->ModRm.mod)); + + _end_object(writer); +} + + +static void _write_sib(Writer &writer, const INSTRUX *instrux) +{ + if (!instrux->HasSib) + return; + + _start_object(writer, "sib"); + + _write_uint(writer, "value", instrux->Sib.Sib); + _write_uint(writer, "base", static_cast(instrux->Sib.base)); + _write_uint(writer, "index", static_cast(instrux->Sib.index)); + _write_uint(writer, "scale", static_cast(instrux->Sib.scale)); + + _end_object(writer); +} + + +static void _write_drex(Writer &writer, const INSTRUX *instrux) +{ + if (!instrux->HasDrex) + return; + + _start_object(writer, "drex"); + + _write_uint(writer, "value", instrux->Drex.Drex); + _write_uint(writer, "b", static_cast(instrux->Drex.b)); + _write_uint(writer, "x", static_cast(instrux->Drex.x)); + _write_uint(writer, "r", static_cast(instrux->Drex.r)); + _write_uint(writer, "oc", static_cast(instrux->Drex.oc0)); + _write_uint(writer, "vd", static_cast(instrux->Drex.vd)); + _write_uint(writer, "d", static_cast(instrux->Drex.d)); + + _end_object(writer); +} + + +static void _write_vex2(Writer &writer, const INSTRUX *instrux) +{ + if (!instrux->HasVex || ND_VEXM_2B != instrux->VexMode) + return; + + _start_object(writer, "vex2"); + + _start_array(writer, "value"); + _write_uint(writer, instrux->Vex2.Vex[0]); + _write_uint(writer, instrux->Vex2.Vex[1]); + _end_array(writer); + + _write_uint(writer, "op", instrux->Vex2.op); + _write_uint(writer, "p", static_cast(instrux->Vex2.p)); + _write_uint(writer, "l", static_cast(instrux->Vex2.l)); + _write_uint(writer, "v", static_cast(instrux->Vex2.v)); + _write_uint(writer, "r", static_cast(instrux->Vex2.r)); + + _end_object(writer); +} + + +static void _write_vex3(Writer &writer, const INSTRUX *instrux) +{ + if (!instrux->HasVex || ND_VEXM_3B != instrux->VexMode) + return; + + _start_object(writer, "vex3"); + + _start_array(writer, "value"); + _write_uint(writer, instrux->Vex3.Vex[0]); + _write_uint(writer, instrux->Vex3.Vex[1]); + _write_uint(writer, instrux->Vex3.Vex[2]); + _end_array(writer); + + _write_uint(writer, "op", instrux->Vex3.op); + _write_uint(writer, "m", static_cast(instrux->Vex3.m)); + _write_uint(writer, "b", static_cast(instrux->Vex3.b)); + _write_uint(writer, "x", static_cast(instrux->Vex3.x)); + _write_uint(writer, "r", static_cast(instrux->Vex3.r)); + _write_uint(writer, "p", static_cast(instrux->Vex3.p)); + _write_uint(writer, "l", static_cast(instrux->Vex3.l)); + _write_uint(writer, "v", static_cast(instrux->Vex3.v)); + _write_uint(writer, "w", static_cast(instrux->Vex3.w)); + + _end_object(writer); +} + + +static void _write_xop(Writer &writer, const INSTRUX *instrux) +{ + if (!instrux->HasXop) + return; + + _start_object(writer, "xop"); + + _start_array(writer, "value"); + _write_uint(writer, instrux->Xop.Xop[0]); + _write_uint(writer, instrux->Xop.Xop[1]); + _write_uint(writer, instrux->Xop.Xop[2]); + _end_array(writer); + + _write_uint(writer, "op", instrux->Xop.op); + _write_uint(writer, "m", static_cast(instrux->Xop.m)); + _write_uint(writer, "b", static_cast(instrux->Xop.b)); + _write_uint(writer, "x", static_cast(instrux->Xop.x)); + _write_uint(writer, "r", static_cast(instrux->Xop.r)); + _write_uint(writer, "p", static_cast(instrux->Xop.p)); + _write_uint(writer, "l", static_cast(instrux->Xop.l)); + _write_uint(writer, "v", static_cast(instrux->Xop.v)); + _write_uint(writer, "w", static_cast(instrux->Xop.w)); + + _end_object(writer); +} + + +static void _write_evex(Writer &writer, const INSTRUX *instrux) +{ + if (!instrux->HasEvex) + return; + + _start_object(writer, "evex"); + + _start_array(writer, "value"); + _write_uint(writer, instrux->Evex.Evex[0]); + _write_uint(writer, instrux->Evex.Evex[1]); + _write_uint(writer, instrux->Evex.Evex[2]); + _write_uint(writer, instrux->Evex.Evex[3]); + _end_array(writer); + + _write_uint(writer, "op", instrux->Evex.op); + _write_uint(writer, "m", static_cast(instrux->Evex.m)); + _write_uint(writer, "zero", static_cast(instrux->Evex.zero)); + _write_uint(writer, "rp", static_cast(instrux->Evex.rp)); + _write_uint(writer, "b", static_cast(instrux->Evex.b)); + _write_uint(writer, "x", static_cast(instrux->Evex.x)); + _write_uint(writer, "r", static_cast(instrux->Evex.r)); + _write_uint(writer, "p", static_cast(instrux->Evex.p)); + _write_uint(writer, "one", static_cast(instrux->Evex.one)); + _write_uint(writer, "v", static_cast(instrux->Evex.v)); + _write_uint(writer, "w", static_cast(instrux->Evex.w)); + _write_uint(writer, "a", static_cast(instrux->Evex.a)); + _write_uint(writer, "vp", static_cast(instrux->Evex.vp)); + _write_uint(writer, "bm", static_cast(instrux->Evex.bm)); + _write_uint(writer, "l", static_cast(instrux->Evex.l)); + _write_uint(writer, "z", static_cast(instrux->Evex.z)); + + _end_object(writer); +} + + +static void _write_exs(Writer &writer, const INSTRUX *instrux) +{ + _start_object(writer, "exs"); + + _write_uint(writer, "w", static_cast(instrux->Exs.w)); + _write_uint(writer, "r", static_cast(instrux->Exs.r)); + _write_uint(writer, "x", static_cast(instrux->Exs.x)); + _write_uint(writer, "b", static_cast(instrux->Exs.b)); + _write_uint(writer, "rp", static_cast(instrux->Exs.rp)); + _write_uint(writer, "p", static_cast(instrux->Exs.p)); + _write_uint(writer, "m", static_cast(instrux->Exs.m)); + _write_uint(writer, "l", static_cast(instrux->Exs.l)); + _write_uint(writer, "v", static_cast(instrux->Exs.v)); + _write_uint(writer, "vp", static_cast(instrux->Exs.vp)); + _write_uint(writer, "bm", static_cast(instrux->Exs.bm)); + _write_uint(writer, "e", static_cast(instrux->Exs.e)); + _write_uint(writer, "z", static_cast(instrux->Exs.z)); + _write_uint(writer, "k", static_cast(instrux->Exs.k)); + _write_uint(writer, "s", static_cast(instrux->Exs.s)); + + _end_object(writer); +} + + +static void _write_prefixes(Writer &writer, const INSTRUX *instrux) +{ + _start_array(writer, "prefixes"); + + if (instrux->HasRex) + _write_string(writer, "rex"); + + if (instrux->HasVex) + _write_string(writer, "vex"); + + if (instrux->HasXop) + _write_string(writer, "xop"); + + if (instrux->HasEvex) + _write_string(writer, "evex"); + + if (instrux->HasMvex) + _write_string(writer, "mvex"); + + if (instrux->HasOpSize) + _write_string(writer, "op_size"); + + if (instrux->HasAddrSize) + _write_string(writer, "addr_size"); + + if (instrux->HasLock) + _write_string(writer, "lock"); + + if (instrux->HasRepnzXacquireBnd) + _write_string(writer, "repnz_xacquire_bnd"); + + if (instrux->HasRepRepzXrelease) + _write_string(writer, "rep_repz_xrelease"); + + if (instrux->HasSeg) + _write_string(writer, "seg"); + + _end_array(writer); +} + + +static void _write_chunks(Writer &writer, const INSTRUX *instrux) +{ + _start_array(writer, "chunks"); + + if (instrux->HasModRm) + _write_string(writer, "mod_rm"); + + if (instrux->HasSib) + _write_string(writer, "sib"); + + if (instrux->HasDrex) + _write_string(writer, "drex"); + + if (instrux->HasDisp) + _write_string(writer, "disp"); + + if (instrux->HasAddr) + _write_string(writer, "addr"); + + if (instrux->HasMoffset) + _write_string(writer, "moffset"); + + if (instrux->HasImm1) + _write_string(writer, "imm1"); + + if (instrux->HasImm2) + _write_string(writer, "imm2"); + + if (instrux->HasImm3) + _write_string(writer, "imm3"); + + if (instrux->HasRelOffs) + _write_string(writer, "rel_offs"); + + if (instrux->HasSseImm) + _write_string(writer, "sse_imm"); + + if (instrux->HasCompDisp) + _write_string(writer, "comp_disp"); + + if (instrux->HasBroadcast) + _write_string(writer, "broadcast"); + + if (instrux->HasMask) + _write_string(writer, "mask"); + + if (instrux->HasZero) + _write_string(writer, "zero"); + + if (instrux->HasEr) + _write_string(writer, "er"); + + if (instrux->HasSae) + _write_string(writer, "sae"); + + if (instrux->SignDisp) + _write_string(writer, "sign_disp"); + + _end_array(writer); +} + + +static void _write_access(Writer &writer, const char *key, const uint8_t access) +{ + _start_array(writer, key); + + if (access & ND_ACCESS_READ) + _write_string(writer, "read"); + + if (access & ND_ACCESS_WRITE) + _write_string(writer, "write"); + + if (access & ND_ACCESS_COND_READ) + _write_string(writer, "cond_read"); + + if (access & ND_ACCESS_COND_WRITE) + _write_string(writer, "cond_write"); + + if (access == ND_ACCESS_NONE) + _write_string(writer, "none"); + + _end_array(writer); +} + + +static void _start_write_default_op(Writer &writer, const ND_OPERAND &op) +{ + _start_object(writer); + + _start_array(writer, "flags"); + + if (op.Flags.IsDefault) + _write_string(writer, "default"); + + if (op.Flags.SignExtendedOp1) + _write_string(writer, "sign_extended_op1"); + + if (op.Flags.SignExtendedDws) + _write_string(writer, "sign_extended_dws"); + + _end_array(writer); + + _write_uint(writer, "size", op.Size); + _write_uint(writer, "raw_size", op.RawSize); + + _write_access(writer, "access", op.Access.Access); + + _start_object(writer, "decorator"); + + if (op.Decorator.HasMask) + _write_uint(writer, "mask", op.Decorator.Mask.Msk); // TODO: k0-k7 + + if (op.Decorator.HasZero) + _write_bool(writer, "zeroing", true); + + if (op.Decorator.HasBroadcast) { + _start_object(writer, "broadcast"); + + _write_uint(writer, "count", op.Decorator.Broadcast.Count); + _write_uint(writer, "size", op.Decorator.Broadcast.Size); + + _end_object(writer); + } + + if (op.Decorator.HasEr) + _write_bool(writer, "er", true); + + if (op.Decorator.HasSae) + _write_bool(writer, "sae", true); + + _end_object(writer); // "decorator" + + switch (op.Type) { + case ND_OP_NOT_PRESENT: + _write_string(writer, "type", "not_preset"); + break; + + case ND_OP_REG: + _write_string(writer, "type", "register"); + break; + + case ND_OP_MEM: + _write_string(writer, "type", "memory"); + break; + + case ND_OP_IMM: + _write_string(writer, "type", "immediate"); + break; + + case ND_OP_OFFS: + _write_string(writer, "type", "offset"); + break; + + case ND_OP_ADDR: + _write_string(writer, "type", "address"); + break; + + case ND_OP_CONST: + _write_string(writer, "type", "constant"); + break; + + case ND_OP_BANK: + _write_string(writer, "type", "bank"); + break; + + default: + _write_string(writer, "type", ""); + break; + } + + // returns without closing the object +} + + +static void _write_op_reg(Writer &writer, const ND_OPERAND &op) +{ + const auto& reg = op.Info.Register; + + _write_uint(writer, "size", reg.Size); + + _write_string(writer, "reg_type", reg_type_to_str(reg.Type)); + _write_string(writer, "reg", reg_to_str(reg.Reg, reg.Type)); + + _write_uint(writer, "reg_id", reg.Reg); + _write_uint(writer, "count", reg.Count); + + if (reg.IsHigh8) + _write_bool(writer, "is_high8", true); + + if (reg.IsBlock) + _write_bool(writer, "is_block", true); +} + + +static void _write_op_mem(Writer &writer, const ND_OPERAND &op) +{ + const auto& mem = op.Info.Memory; + + _start_array(writer, "flags"); + + if (mem.IsRipRel) + _write_string(writer, "rip_rel"); + + if (mem.IsStack) + _write_string(writer, "stack"); + + if (mem.IsString) + _write_string(writer, "string"); + + if (mem.IsShadowStack) + _write_string(writer, "shadow_stack"); + + if (mem.IsDirect) + _write_string(writer, "direct"); + + if (mem.IsBitbase) + _write_string(writer, "bitbase"); + + if (mem.IsAG) + _write_string(writer, "ag"); + + if (mem.IsMib) + _write_string(writer, "mib"); + + if (mem.HasBroadcast) + _write_string(writer, "broadcast"); + + _end_array(writer); + + if (mem.IsVsib) { + _start_object(writer, "vsib"); + + _write_uint(writer, "index_size", mem.Vsib.IndexSize); + _write_uint(writer, "elem_size", mem.Vsib.ElemSize); + _write_uint(writer, "elem_count", mem.Vsib.ElemCount); + + _end_object(writer); + } + + if (mem.HasSeg) + _write_uint(writer, "seg", mem.Seg); + + if (mem.HasBase) { + _write_uint(writer, "base_size", mem.BaseSize); + _write_uint(writer, "base", mem.Base); + } + + if (mem.HasIndex) { + _write_uint(writer, "index_size", mem.IndexSize); + _write_uint(writer, "index", mem.Index); + _write_uint(writer, "scale", mem.Scale); + } + + if (mem.HasDisp || mem.HasCompDisp) { + if (mem.HasDisp) + _write_uint(writer, "disp_size", mem.DispSize); + + if (mem.HasCompDisp) + _write_uint(writer, "comp_disp_size", mem.CompDispSize); + + _write_uint(writer, "disp", mem.Disp); + } +} + + +static void _write_operands(Writer &writer, const INSTRUX *instrux) +{ + _start_array(writer, "operands"); + + for (auto i = 0; i < instrux->OperandsCount; i++) { + const auto& op = instrux->Operands[i]; + + _start_write_default_op(writer, op); + + _start_object(writer, "info"); + + switch (op.Type) { + case ND_OP_REG: + _write_op_reg(writer, op); + break; + + case ND_OP_MEM: + _write_op_mem(writer, op); + break; + + case ND_OP_IMM: + _write_uint64(writer, "imm", op.Info.Immediate.Imm); + break; + + case ND_OP_OFFS: + _write_uint64(writer, "rel", op.Info.RelativeOffset.Rel); + break; + + case ND_OP_ADDR: + _write_uint(writer, "base_seg", op.Info.Address.BaseSeg); + _write_uint64(writer, "offset", op.Info.Address.Offset); + + break; + + case ND_OP_CONST: + _write_uint64(writer, "const", op.Info.Constant.Const); + break; + + case ND_OP_NOT_PRESENT: + case ND_OP_BANK: + break; + } + + _end_object(writer); // "info" + _end_object(writer); // the one from _start_write_default_op + } + + _end_array(writer); +} + + +static void _write_valid_modes(Writer &writer, const ND_VALID_MODES &modes) +{ + _start_array(writer, "valid_modes"); + + if (modes.Ring0) + _write_string(writer, "ring0"); + + if (modes.Ring1) + _write_string(writer, "ring1"); + + if (modes.Ring2) + _write_string(writer, "ring2"); + + if (modes.Ring3) + _write_string(writer, "ring3"); + + if (modes.Real) + _write_string(writer, "real"); + + if (modes.V8086) + _write_string(writer, "v8086"); + + if (modes.Protected) + _write_string(writer, "protected"); + + if (modes.Compat) + _write_string(writer, "compatibility"); + + if (modes.Long) + _write_string(writer, "long"); + + if (modes.Smm) + _write_string(writer, "smm"); + + if (modes.Sgx) + _write_string(writer, "sgx"); + + if (modes.Tsx) + _write_string(writer, "tsx"); + + if (modes.VmxRoot) + _write_string(writer, "vmx_root"); + + if (modes.VmxNonRoot) + _write_string(writer, "vmx_non_root"); + + if (modes.VmxOff) + _write_string(writer, "vmx_off"); + + _end_array(writer); +} + + +static void _write_valid_prefixes(Writer &writer, const ND_VALID_PREFIXES &prefixes) +{ + _start_array(writer, "valid_prefixes"); + + if (prefixes.Rep) + _write_string(writer, "rep"); + + if (prefixes.RepCond) + _write_string(writer, "rep_cond"); + + if (prefixes.Lock) + _write_string(writer, "lock"); + + if (prefixes.Hle) + _write_string(writer, "hle"); + + if (prefixes.Xacquire) + _write_string(writer, "xacquire"); + + if (prefixes.Xrelease) + _write_string(writer, "xrelease"); + + if (prefixes.Bnd) + _write_string(writer, "bnd"); + + if (prefixes.Bhint) + _write_string(writer, "bhint"); + + if (prefixes.HleNoLock) + _write_string(writer, "hle_no_lock"); + + if (prefixes.Dnt) + _write_string(writer, "dnt"); + + _end_array(writer); +} + + +static void _write_valid_decorators(Writer &writer, const ND_VALID_DECORATORS &decorators) +{ + _start_array(writer, "valid_decorators"); + + if (decorators.Er) + _write_string(writer, "er"); + + if (decorators.Sae) + _write_string(writer, "Sae"); + + if (decorators.Zero) + _write_string(writer, "Zero"); + + if (decorators.Mask) + _write_string(writer, "mask"); + + if (decorators.Broadcast) + _write_string(writer, "broadcast"); + + _end_array(writer); +} + + +static void _write_cpuid_flag(Writer &writer, const ND_CPUID_FLAG &cpuid_flag) +{ + if (0 == cpuid_flag.Flag) + return; + + _start_object(writer, "cpuid_flag"); + + _write_uint64(writer, "flag", cpuid_flag.Flag); + _write_uint(writer, "leaf", cpuid_flag.Leaf); + _write_uint(writer, "sub_leaf", static_cast(cpuid_flag.SubLeaf)); + _write_uint(writer, "reg", static_cast(cpuid_flag.Reg)); + _write_uint(writer, "bit", static_cast(cpuid_flag.Bit)); + + _end_object(writer); +} + + +static void _write_rflags(Writer &writer, const ND_RFLAGS &rflags, const char *key) +{ + _start_array(writer, key); + + if (rflags.CF) + _write_string(writer, "cf"); + + if (rflags.PF) + _write_string(writer, "pf"); + + if (rflags.AF) + _write_string(writer, "af"); + + if (rflags.ZF) + _write_string(writer, "zf"); + + if (rflags.SF) + _write_string(writer, "sf"); + + if (rflags.TF) + _write_string(writer, "tf"); + + if (rflags.IF) + _write_string(writer, "if"); + + if (rflags.DF) + _write_string(writer, "df"); + + if (rflags.OF) + _write_string(writer, "of"); + + if (rflags.IOPL) + _write_string(writer, "iopl"); + + if (rflags.NT) + _write_string(writer, "nt"); + + if (rflags.RF) + _write_string(writer, "rf"); + + if (rflags.VM) + _write_string(writer, "vm"); + + if (rflags.AC) + _write_string(writer, "ac"); + + if (rflags.VIF) + _write_string(writer, "vif"); + + if (rflags.VIP) + _write_string(writer, "vip"); + + if (rflags.ID) + _write_string(writer, "id"); + + _end_array(writer); +} + + +static void _write_flags_access(Writer &writer, INSTRUX *instrux) +{ + if (ND_ACCESS_NONE == instrux->FlagsAccess.RegAccess) + return; + + _start_object(writer, "flags_access"); + + _write_access(writer, "access", instrux->FlagsAccess.RegAccess); + + if ((instrux->FlagsAccess.RegAccess & ND_ACCESS_ANY_READ) && instrux->FlagsAccess.Tested.Raw) + _write_rflags(writer, instrux->FlagsAccess.Tested, "tested"); + + if ((instrux->FlagsAccess.RegAccess & ND_ACCESS_ANY_WRITE) && instrux->FlagsAccess.Modified.Raw) + _write_rflags(writer, instrux->FlagsAccess.Modified, "modified"); + + if (instrux->FlagsAccess.Set.Raw) + _write_rflags(writer, instrux->FlagsAccess.Set, "set"); + + if (instrux->FlagsAccess.Cleared.Raw) + _write_rflags(writer, instrux->FlagsAccess.Cleared, "cleared"); + + if (instrux->FlagsAccess.Undefined.Raw) + _write_rflags(writer, instrux->FlagsAccess.Undefined, "undefined"); + + _end_object(writer); +} + + +StringBuffer instrux_to_json(INSTRUX *instrux, size_t rip, bool text_only /* = false */) +{ + char text[ND_MIN_BUF_SIZE]; + + auto status = NdToText(instrux, rip, sizeof(text), text); + if (!ND_SUCCESS(status)) + text[0] = 0; + + auto s = StringBuffer {nullptr, 4096}; + auto writer = Writer {s, nullptr}; + + _start_object(writer); + + _write_string(writer, "text", text); + + if (text_only) { + _end_object(writer); + return s; + } + + _write_uint(writer, "def_code", _disasm_size_to_int(instrux->DefCode)); + _write_uint(writer, "def_data", _disasm_size_to_int(instrux->DefData)); + _write_uint(writer, "def_stack", _disasm_size_to_int(instrux->DefStack)); + + _write_string(writer, "enc_mode", enc_mode_to_str(instrux->EncMode)); + + _write_uint(writer, "addr_mode", _disasm_size_to_int(instrux->AddrMode)); + _write_uint(writer, "op_mode", _disasm_size_to_int(instrux->OpMode)); + _write_uint(writer, "ef_op_mode", _disasm_size_to_int(instrux->EfOpMode)); + _write_uint(writer, "vec_mode", _disasm_size_to_int(instrux->VecMode) * 8); + _write_uint(writer, "ef_vec_mnode", _disasm_size_to_int(instrux->EfVecMode) * 8); + + _write_rex(writer, instrux); + _write_modrm(writer, instrux); + _write_sib(writer, instrux); + _write_drex(writer, instrux); + _write_vex2(writer, instrux); + _write_vex3(writer, instrux); + _write_xop(writer, instrux); + _write_evex(writer, instrux); + + if (instrux->Rep) + _write_uint(writer, "rep", instrux->Rep); + + if (instrux->Seg) + _write_uint(writer, "seg", instrux->Seg); + + _write_uint(writer, "stack_words", instrux->StackWords); + + _write_exs(writer, instrux); + _write_prefixes(writer, instrux); + _write_chunks(writer, instrux); + + if (instrux->IsRepeated) + _write_bool(writer, "is_repeated", true); + + if (instrux->IsXacquireEnabled) + _write_bool(writer, "is_xacquire_enabled", true); + + if (instrux->IsXreleaseEnabled) + _write_bool(writer, "is_xrelease_enabled", true); + + if (instrux->IsRipRelative) + _write_bool(writer, "is_rip_relative", true); + + if (instrux->IsCetTracked) + _write_bool(writer, "is_cet_tracked", true); + + if (instrux->HasMandatory66) + _write_bool(writer, "mandatory_66", true); + + if (instrux->HasMandatoryF2) + _write_bool(writer, "mandatory_f2", true); + + if (instrux->HasMandatoryF3) + _write_bool(writer, "mandatory_f3", true); + + _write_uint(writer, "length", instrux->Length); + _write_uint(writer, "word_length", static_cast(instrux->WordLength)); + _write_uint(writer, "pref_length", static_cast(instrux->PrefLength)); + + _start_object(writer, "address"); + + _write_uint(writer, "ip", instrux->Address.Ip); + _write_uint(writer, "cs", instrux->Address.Cs); + + _end_object(writer); + + _write_uint(writer, "op_offset", static_cast(instrux->OpOffset)); + _write_uint(writer, "main_op_offset", static_cast(instrux->MainOpOffset)); + + if (instrux->HasAddr) { + _start_object(writer, "addr"); + + _write_uint(writer, "len", static_cast(instrux->AddrLength)); + _write_uint(writer, "offset", static_cast(instrux->AddrOffset)); + + _end_object(writer); + } + + if (instrux->HasMoffset) { + _start_object(writer, "moffset"); + + _write_uint64(writer, "value", instrux->Moffset); + _write_uint(writer, "len", static_cast(instrux->MoffsetLength)); + _write_uint(writer, "offset", static_cast(instrux->MoffsetOffset)); + + _end_object(writer); + }; + + if (instrux->HasDisp) { + _start_object(writer, "displacement"); + + _write_uint(writer, "value", instrux->Displacement); + _write_uint(writer, "len", static_cast(instrux->DispLength)); + _write_uint(writer, "offset", static_cast(instrux->DispOffset)); + + _end_object(writer); + } + + if (instrux->HasRelOffs) { + _start_object(writer, "relative_offset"); + + _write_uint(writer, "value", instrux->RelativeOffset); + _write_uint(writer, "len", static_cast(instrux->RelOffsLength)); + _write_uint(writer, "offset", static_cast(instrux->RelOffsOffset)); + + _end_object(writer); + } + + if (instrux->HasImm1) { + _start_object(writer, "immediate1"); + + _write_uint64(writer, "value", instrux->Immediate1); + _write_uint(writer, "len", static_cast(instrux->Imm1Length)); + _write_uint(writer, "offset", static_cast(instrux->Imm1Offset)); + + _end_object(writer); + } + + if (instrux->HasImm2) { + _start_object(writer, "immediate2"); + + _write_uint(writer, "value", instrux->Immediate2); + _write_uint(writer, "len", static_cast(instrux->Imm2Length)); + _write_uint(writer, "offset", static_cast(instrux->Imm2Offset)); + + _end_object(writer); + } + + if (instrux->HasImm3) { + _start_object(writer, "immediate3"); + + _write_uint(writer, "value", instrux->Immediate3); + _write_uint(writer, "len", static_cast(instrux->Imm3Length)); + _write_uint(writer, "offset", static_cast(instrux->Imm3Offset)); + + _end_object(writer); + } + + if (instrux->HasSseImm) { + _start_object(writer, "sse_immediate"); + + _write_uint(writer, "value", instrux->SseImmediate); + _write_uint(writer, "offset", static_cast(instrux->SseImmOffset)); + + _end_object(writer); + } + + _write_uint(writer, "sse_condition", instrux->SseCondition); + _write_uint(writer, "condition", instrux->Condition); + + _write_uint(writer, "operands_count", instrux->OperandsCount); + _write_uint(writer, "exp_operands_count", instrux->ExpOperandsCount); + _write_uint(writer, "operands_encoding_map", instrux->OperandsEncodingMap); + + _write_operands(writer, instrux); + + _write_access(writer, "rip_access", instrux->RipAccess); + _write_access(writer, "memory_access", instrux->MemoryAccess); + _write_access(writer, "stack_access", instrux->StackAccess); + + _write_flags_access(writer, instrux); + + _write_uint(writer, "attributes", instrux->Attributes); + + _write_string(writer, "class", ins_class_to_str(instrux->Iclass)); + _write_string(writer, "category", ins_cat_to_str(instrux->Category)); + _write_string(writer, "set", ins_set_to_str(instrux->IsaSet)); + + _write_cpuid_flag(writer, instrux->CpuidFlag); + + _write_valid_modes(writer, instrux->ValidModes); + _write_valid_prefixes(writer, instrux->ValidPrefixes); + _write_valid_decorators(writer, instrux->ValidDecorators); + + _write_string(writer, "mnemonic", instrux->Mnemonic); + + _start_array(writer, "opcode_bytes"); + + for (int i = 0; i < instrux->OpLength; i++) + _write_uint(writer, instrux->OpCodeBytes[i]); + + _end_array(writer); + + _write_uint(writer, "primary_opcode", instrux->PrimaryOpCode); + + _start_array(writer, "bytes"); + + for (int i = 0; i < instrux->Length; i++) + _write_uint(writer, instrux->InstructionBytes[i]); + + _end_array(writer); + + _end_object(writer); + + return s; +} + + +StringBuffer byte_to_json(uint8_t byte, size_t rip) +{ + auto s = StringBuffer {nullptr, 64}; + auto writer = Writer {s, nullptr}; + + _start_object(writer); + + _write_uint(writer, "byte", byte); + _write_uint(writer, "length", 1); + _write_uint64(writer, "rip", rip); + + _end_object(writer); + + return s; +} + + +const char *json_to_string(StringBuffer &j) +{ + return j.GetString(); +} diff --git a/docs/Makefile b/docs/Makefile new file mode 100644 index 0000000..d0c3cbf --- /dev/null +++ b/docs/Makefile @@ -0,0 +1,20 @@ +# Minimal makefile for Sphinx documentation +# + +# You can set these variables from the command line, and also +# from the environment for the first two. +SPHINXOPTS ?= +SPHINXBUILD ?= sphinx-build +SOURCEDIR = source +BUILDDIR = build + +# Put it first so that "make" without argument is like "make help". +help: + @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) + +.PHONY: help Makefile + +# Catch-all target: route all unknown targets to Sphinx using the new +# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). +%: Makefile + @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) diff --git a/docs/make.bat b/docs/make.bat new file mode 100644 index 0000000..9534b01 --- /dev/null +++ b/docs/make.bat @@ -0,0 +1,35 @@ +@ECHO OFF + +pushd %~dp0 + +REM Command file for Sphinx documentation + +if "%SPHINXBUILD%" == "" ( + set SPHINXBUILD=sphinx-build +) +set SOURCEDIR=source +set BUILDDIR=build + +if "%1" == "" goto help + +%SPHINXBUILD% >NUL 2>NUL +if errorlevel 9009 ( + echo. + echo.The 'sphinx-build' command was not found. Make sure you have Sphinx + echo.installed, then set the SPHINXBUILD environment variable to point + echo.to the full path of the 'sphinx-build' executable. Alternatively you + echo.may add the Sphinx directory to PATH. + echo. + echo.If you don't have Sphinx installed, grab it from + echo.http://sphinx-doc.org/ + exit /b 1 +) + +%SPHINXBUILD% -M %1 %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O% +goto end + +:help +%SPHINXBUILD% -M help %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O% + +:end +popd diff --git a/docs/source/conf.py b/docs/source/conf.py new file mode 100644 index 0000000..c418236 --- /dev/null +++ b/docs/source/conf.py @@ -0,0 +1,53 @@ +# Configuration file for the Sphinx documentation builder. +# +# This file only contains a selection of the most common options. For a full +# list see the documentation: +# https://www.sphinx-doc.org/en/master/usage/configuration.html + +# -- Path setup -------------------------------------------------------------- + +# If extensions (or modules to document with autodoc) are in another directory, +# add these directories to sys.path here. If the directory is relative to the +# documentation root, use os.path.abspath to make it absolute, like shown here. +# +# import os +# import sys +# sys.path.insert(0, os.path.abspath('.')) + + +# -- Project information ----------------------------------------------------- + +project = 'bddisasm' +copyright = '2020, Bitdefender' +author = 'Bitdefender' + + +# -- General configuration --------------------------------------------------- + +# Add any Sphinx extension module names here, as strings. They can be +# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom +# ones. +extensions = [ +] + +# Add any paths that contain templates here, relative to this directory. +templates_path = ['_templates'] + +# List of patterns, relative to source directory, that match files and +# directories to ignore when looking for source files. +# This pattern also affects html_static_path and html_extra_path. +exclude_patterns = [] + + +# -- Options for HTML output ------------------------------------------------- + +# The theme to use for HTML and HTML Help pages. See the documentation for +# a list of builtin themes. +# +html_theme = 'alabaster' +master_doc = 'index' + +# Add any paths that contain custom static files (such as style sheets) here, +# relative to this directory. They are copied after the builtin static files, +# so a file named "default.css" will overwrite the builtin "default.css". +html_static_path = [] diff --git a/docs/source/index.rst b/docs/source/index.rst new file mode 100644 index 0000000..66b5579 --- /dev/null +++ b/docs/source/index.rst @@ -0,0 +1,401 @@ +.. bddisasm documentation master file, created by + sphinx-quickstart on Wed Jul 8 13:39:28 2020. + You can adapt this file completely to your liking, but it should at least + contain the root `toctree` directive. + +Welcome to bddisasm's documentation! +==================================== + +.. toctree:: + :maxdepth: 2 + :caption: Contents: + +About +===== + +The Bitdefender x86 disassembler is a complete x86/x64 instruction decoder, +capable of providing full information about each decoded instruction. The +library is written entirely in C, with some Python 3 code for the instruction +tables generation. It has no external dependencies, and it is thread safe +by design. It can be easily integrated in any environment - we use it in +user mode on both Windows and Linux, in kernel mode on Windows and inside +VMX root of our own Napoca hypervisor. + +This documentation provides a high-level overview of the project and +how to use it. The information is bound to standard x86 instruction +semantics, hence there is no official Doxygen documentation Instead, the source +code and the header files contain rich comments, which provided detailed relevant +information. + + +Project goals +============= + +When we first started the project more than 5 years ago, there were no good +disassemblers available which werecapable of providing extensive information about the +decoded instructions. We decided to create, from scratch, such a disassembler, +which would then be used by all the projects that require one. The first +requirement was, therefore, that the library should be OS agnostic. We then +considered the main use-cases, where we decode and analyze instructions +in real time (for example, an instruction that just triggered a memory fault). +This meant that the decoder had to be very fast. Of course, having to be able +to integrate the library in any mode of operation and on any operating system +meant that it should be thread-safe by design, and no memory should be allocated. +We then considered that some of our use-cases required instruction emulation, +so the decoder must provide as much information about each instruction as +possible. Finally, given the latest ISA extensions proposed by Intel, the +disassembler must also be designed in a way that allows programmers to easily +add support for new instructions. The requirements, in a nutshell, are, therefore: + +.. hlist:: + :columns: 1 + + * OS and operating mode agnostic (Windows/Linux, user/kernel/VMX root) + * Speed (less than 500 clocks/decoded instruction) + * No memory overhead (no memory is allocated by the disassembler) + * Thread-safe (no global variables written, no threads created) + * Full instruction information + * Easy to extend + +We managed to achieve all of these goals. + +The library is successfully being +used in various user/kernel/VMX root projects, on both Windows and Linux. +On an Intel Core i7-8650U, it takes roughly 300 clocks to decode one instruction. +There is no memory overhead, the library is thread safe and it provides pretty +much all known information about each instruction. Finally, the instructions are +defined in an easy to understand, well documented textual format - adding support +for a new instruction requires describing the instruction in one +of these files, and re-building the tables. + +Using the disassembler +====================== + +Using the disassembler is very easy. Include the **bddisasm.h** header file +and link with the disassembler library (which is **bddisasm.lib** on Windows or +**libbddisasm.a** on Linux). Once this has been done, make sure the **nd_vsnprintf_s** and +**nd_memset** functions are defined. For example, do the following: + +.. code-block:: c + :linenos: + + int nd_vsnprintf_s( + char *buffer, + size_t sizeOfBuffer, + size_t count, + const char *format, + va_list argptr + ) + { + return _vsnprintf_s(buffer, sizeOfBuffer, count, format, argptr); + } + + void* nd_memset(void *s, int c, size_t n) + { + return memset(s, c, n); + } + +These are required to allow the integrator to use whatever implementation of +vsnprintf and memset they wish. Once this has been done, decoding an instruction is as +simple as calling one of the decoding API: + +.. code-block:: c + :linenos: + + #include "bddisasm/disasmtypes.h" + #include "bddisasm/bddisasm.h" + + int main() + { + INSTRUX ix; + unsigned char ins[2] = { 0x33, 0xC0 }; + NDSTATUS status; + + status = NdDecode(&ix, ins, ND_CODE_64, ND_DATA_64); + if (!ND_SUCCESS(status)) + { + printf("Decoding failed with error 0x%08x!\n", status); + return -1; + } + + printf("Decoded instruction with length %d!\n", ix.Length); + } + +When decoding an instruction, all the possible information is stored in the +output **INSTRUX** structure. There is no need to call any other helper functions. +However, the textual representation (the actual *disassembly*) of the instruction +has to be obtained by calling the **NdToText** API: + +.. code-block:: c + :linenos: + + #include "bddisasm/disasmtypes.h" + #include "bddisasm/bddisasm.h" + + int main() + { + INSTRUX ix; + unsigned char ins[2] = { 0x33, 0xC0 }; + NDSTATUS status; + char txt[ND_MIN_BUF_SIZE]; + + status = NdDecode(&ix, ins, ND_CODE_64, ND_DATA_64); + if (!ND_SUCCESS(status)) + { + printf("Decoding failed with error 0x%08x!\n", status); + return -1; + } + + NdToText(&ix, 0, sizeof(txt), txt); + + printf("Decoded instruction %s!\n", txt); + } + +The disassembler provides the **NdToText** function, but this function only +supports Intel style syntax. If one wishes to implement a different output +formatter, it can do so, by implementing a different **NdToText** function +(the existing function can be used as a template). + +Instruction information +======================= + +The information provided inside the **INSTRUX** structure covers all the known information +about the instruction. There are several categories of info offered: + +.. hlist:: + :columns: 1 + + * Instruction encoding information - prefixes, opcodes, modrm, sib, immediates, displacement + * Operand information, for both explicit and implicit operands - type, size, access, encoding + * Instruction meta information - instruction set, instruction type, instruction class + * Accepted prefixes - lock, rep, hle, etc. + * Valid modes for the instruction - real, protected, long, ring 0/1/2/3, etc. + * CPUID leaf information - allows to directly test if the instruction is available or not + * Flags access - for each flag, access type (tested, modified, cleared, set to 1, undefined) + * FPU flags access - for FPU instructions + * For VEX/SSE instructions - exception class + * For EVEX instructions - decorator info, tuple type, exception class + +For memory operands, the following information is provided: + +.. hlist:: + :columns: 1 + + * Segment + * Base register + * Index register, with scale + * Displacement + * VSIB information - index size, element size, element count + * Extended addressing information - address generation, mib, sibmem, string operation indicator, stack access indicator, bitbase, etc. + +This is the most relevant information provided by it. For more info, +look at the **bddisasm.h** file, which contains all the definitions, +together with ample comments describing each one of them. + +Examples +======== + +Assuming we have already decoded an instruction as follows: + +.. code-block:: c + :linenos: + + #include "bddisasm/disasmtypes.h" + #include "bddisasm/bddisasm.h" + + int main() + { + INSTRUX ix; + unsigned char ins[2] = { 0x33, 0xC0 }; + NDSTATUS status; + char txt[ND_MIN_BUF_SIZE]; + + status = NdDecode(&ix, ins, ND_CODE_64, ND_DATA_64); + if (!ND_SUCCESS(status)) + { + printf("Decoding failed with error 0x%08x!\n", status); + return -1; + } + } + +we will provide some examples of how we can obtain specific information about the instruction. + +Determining the length of an instruction +---------------------------------------- + +.. code-block:: c + :linenos: + + ix.Length; // Length in bytes. + + +Determining the number of operands of an instruction +---------------------------------------------------- + +.. code-block:: c + :linenos: + + ix.OperandsCount; // Total operands count. + ix.ExpOperandsCount; // Explicit operands count. + +Determining the operand and address size +---------------------------------------- + +.. code-block:: c + :linenos: + + if (ix.OpMode == ND_OPSZ_16) // 16 bit operand size. + if (ix.OpMode == ND_OPSZ_32) // 32 bit operand size. + if (ix.OpMode == ND_OPSZ_64) // 64 bit operand size. + if (ix.AddrMode == ND_ADDR_16) // 16 bit address size. + if (ix.AddrMode == ND_ADDR_32) // 32 bit address size. + if (ix.AddrMode == ND_ADDR_64) // 64 bit address size. + +Determining if the instruction has modrm, SIB or displacement +------------------------------------------------------------- + +.. code-block:: c + :linenos: + + if (ix.HasModrm) // The instruction has Mod R/M. + if (ix.HasSib) // The instruction has SIB. + if (ix.HasDisp) // The instruction has displacement. + +Determining if the first operand is register EAX +------------------------------------------------ + +.. code-block:: c + :linenos: + + if (ND_IS_OP_REG(&ix.Operands[0], ND_REG_GPR, 4, REG_EAX)) + +Determining if the second operand is the stack +---------------------------------------------- + +.. code-block:: c + :linenos: + + if (ix.Operands[1].Type == ND_OP_MEM && + ix.Operands[1].Info.Memory.IsStack) + +Determining if the instruction is a conditional branch +------------------------------------------------------ + +.. code-block:: c + :linenos: + + if (ix.Category == ND_CAT_COND_BR) + +Determining if the instruction is "ADD" or "SUB" +------------------------------------------------ + +.. code-block:: c + :linenos: + + if (ix.Instruction == ND_INS_ADD || + ix.Instruction == ND_INS_SUB) + +Determining if the instruction accesses various flags +----------------------------------------------------- + +.. code-block:: c + :linenos: + + if (ix.FlagsAccess.Modified.CF) // Is CF modified? + if (ix.FlagsAccess.Undefined.OF) // Is OF undefined? + if (ix.FlagsAccess.Cleared.ZF) // Is ZF cleared? + if (ix.FlagsAccess.Set.PF) // Is PF set? + if (ix.FlagsAccess.Tested.CF) // Is CF tested? + + +Determining if the instruction is supported on the current CPU +-------------------------------------------------------------- + +.. code-block:: c + :linenos: + + if (ix.CpuidFlag.Leaf == ND_CFF_NO_LEAF) + { + // The instruction is present on pretty much all CPUs, + // there is no CPUID bit flag test. + } + else + { + int regs[4]; + int sorted[4]; + + if (ix.CpuidFlag.SubLeaf == ND_CFF_NO_SUBLEAF) + { + // No subleaf. + __cpuid(regs, ix.CpuidFlag.Leaf); + } + else + { + __cpuidex(regs, ix.CpuidFlag.Leaf, ix.CpuidFlag.SubLeaf); + } + + // regs is defined by MSDN as eax, ebx, ecx, edx, so sort them + // in Intel order. + sorted[0] = regs[0]; // eax + sorted[1] = regs[2]; // ecx + sorted[2] = regs[3]; // edx + sorted[3] = regs[1]; // ebx + + if (sorted[ix.CpuidFlag.Reg] & (1ULL << ix.CpuidFlag.Bit)) + { + // The instruction is supported! + } + } + +Determining if the instruction accepts various prefixes +------------------------------------------------------- + +.. code-block:: c + :linenos: + + if (ix.ValidPrefixes.Lock) // The instruction accepts LOCK. + if (ix.ValidPrefixes.Hle) // The instruction accepts hardware lock elision prefix. + if (ix.ValidPrefixes.Rep) // The instruction accepts unconditional REP prefix. + +Determining if the instruction is valid in various modes +-------------------------------------------------------- + +.. code-block:: c + :linenos: + + if (ix.ValidModes.Real) // The instruction is valid in real mode. + if (ix.ValidModes.Long) // The instruction is valid in long mode. + if (ix.ValidModes.Tsx) // The instruction is valid in a transaction. + if (!ix.ValidModes.Ring3) // The instruction is not valid in user-mode. + +Determining if the instruction is a branch of any kind +------------------------------------------------------ + +.. code-block:: c + :linenos: + + if (ix.RipAccess & ND_ACCESS_ANY_WRITE) // Instruction writes RIP. + +Computing the linear address of a memory operand +------------------------------------------------ + +.. code-block:: c + :linenos: + + // Note: we don't consider bitbase or VSIB addressing. + if (memOp->Info.Memory.HasBase) + { + gla += ND_TRIM(memOp->Info.Memory.BaseSize, REG(memOp->Info.Memory.Base)); + } + + if (memOp->Info.Memory.HasIndex) + { + gla += ND_TRIM(memOp->Info.Memory.IndexSize, REG(memOp->Info.Memory.Index)) * memOp->Info.Memory.Scale; + } + + if (memOp->Info.Memory.HasDisp) + { + gla += memOp->Info.Memory.Disp; + } + + diff --git a/inc/bddisasm.h b/inc/bddisasm.h new file mode 100644 index 0000000..2c9d3a7 --- /dev/null +++ b/inc/bddisasm.h @@ -0,0 +1,1454 @@ +/* + * Copyright (c) 2020 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _BDDISASM_H_ +#define _BDDISASM_H_ + +#include "disasmstatus.h" +#include "registers.h" +#include "constants.h" +#include "cpuidflags.h" +#include "version.h" + +#ifdef _MSC_VER +#pragma warning(push) +#pragma warning(disable: 4214) // Bitfield in type other than int. +#pragma warning(disable: 4201) // Nonstandard extension used: nameless struct/union. +#endif + +// +// Preferred vendor; the disassembler will try to be smart and disassemble as much as it can, but if there are +// encoding conflicts, than an alternate vendor can be selected. Note that this has effect only on conflicting +// encodings. +// +#define ND_VEND_ANY 0 // Generic decode, include any vendor. +#define ND_VEND_INTEL 1 // Prefer Intel. +#define ND_VEND_AMD 2 // Prefer AMD. +#define ND_VEND_GEODE 3 // Prefer Geode. +#define ND_VEND_CYRIX 4 // Prefer Cyrix. + +// +// Code type +// +#define ND_CODE_16 0 // 16 bit decode mode. +#define ND_CODE_32 1 // 32 bit decode mode. +#define ND_CODE_64 2 // 64 bit decode mode. + +// +// Data type +// +#define ND_DATA_16 0 // 16 bit data size. +#define ND_DATA_32 1 // 32 bit data size. +#define ND_DATA_64 2 // 64 bit data size. + +// +// Stack type +// +#define ND_STACK_16 0 // 16 bit stack size. +#define ND_STACK_32 1 // 32 bit stack size. +#define ND_STACK_64 2 // 64 bit stack size. + +// +// Addressing mode +// +#define ND_ADDR_16 0 // 16 bit addressing. +#define ND_ADDR_32 1 // 32 bit addressing. +#define ND_ADDR_64 2 // 64 bit addressing. + +// +// Operand mode/size +// +#define ND_OPSZ_16 0 // 16 bit operand size. +#define ND_OPSZ_32 1 // 32 bit operand size. +#define ND_OPSZ_64 2 // 64 bit operand size. + +// +// Vector mode/size +// +#define ND_VECM_128 0 // 128 bit vector size. +#define ND_VECM_256 1 // 256 bit vector size. +#define ND_VECM_512 2 // 512 bit vector size. + +// +// Encoding mode +// +#define ND_ENCM_LEGACY 0 // Legacy encoded instruction. +#define ND_ENCM_XOP 1 // XOP encoded instruction. +#define ND_ENCM_VEX 2 // VEX (bot 2B or 3B) encoded instruction. +#define ND_ENCM_EVEX 3 // EVEX encoded instruction. + +// +// VEX prefixes +// +#define ND_VEXM_2B 0 // 2B VEX prefix (0xC5). +#define ND_VEXM_3B 1 // 3B VEX prefix (0xC4). + + +// +// Size definitions +// +#define ND_SIZE_8BIT 1 // 1 byte. +#define ND_SIZE_16BIT 2 // 1 word or 2 bytes. +#define ND_SIZE_32BIT 4 // 1 double word or 4 bytes. +#define ND_SIZE_48BIT 6 // 1 fword or 6 bytes. +#define ND_SIZE_64BIT 8 // 1 qword or 8 bytes. +#define ND_SIZE_80BIT 10 // 1 fpu word or 10 bytes. +#define ND_SIZE_112BIT 14 // FPU environment, 14 bytes. +#define ND_SIZE_128BIT 16 // 1 xmm word or 16 bytes. +#define ND_SIZE_224BIT 28 // FPU environment, 28 bytes. +#define ND_SIZE_256BIT 32 // 1 ymm word or 32 bytes. +#define ND_SIZE_512BIT 64 // 1 zmm word or 64 bytes. +#define ND_SIZE_752BIT 94 // FPU state, 94 bytes. +#define ND_SIZE_864BIT 108 // FPU state, 108 bytes. +#define ND_SIZE_4096BIT 512 // Extended state, 512 bytes. +#define ND_SIZE_1KB 1024 // Tile register, 1KB. +#define ND_SIZE_CACHE_LINE 0xFFFFFFFE // The size of a cache line. +#define ND_SIZE_UNKNOWN 0xFFFFFFFF // Unknown/invalid size. + + +typedef uint32_t ND_OPERAND_SIZE; + +typedef uint32_t ND_REG_SIZE; + + +// +// Prefix definitions +// +#define ND_PREFIX_G0_LOCK 0xF0 // LOCK prefix. +#define ND_PREFIX_G1_REPNE_REPNZ 0xF2 // REPNE/REPNZ prefix. +#define ND_PREFIX_G1_XACQUIRE 0xF2 // XACQUIRE prefix. +#define ND_PREFIX_G1_REPE_REPZ 0xF3 // REPE/REPZ prefix. +#define ND_PREFIX_G1_XRELEASE 0xF3 // XRELEASE prefix. +#define ND_PREFIX_G1_BND 0xF2 // BND prefix. +#define ND_PREFIX_G2_SEG_CS 0x2E // CS segment override. +#define ND_PREFIX_G2_SEG_SS 0x36 // SS segment override. +#define ND_PREFIX_G2_SEG_DS 0x3E // DS segment override. +#define ND_PREFIX_G2_SEG_ES 0x26 // ES segment override. +#define ND_PREFIX_G2_SEG_FS 0x64 // FS segment override. +#define ND_PREFIX_G2_SEG_GS 0x65 // GS segment override. +#define ND_PREFIX_G2_BR_NOT_TAKEN 0x2E // Branch not taken hint. +#define ND_PREFIX_G2_BR_TAKEN 0x3E // Branch taken hint. +#define ND_PREFIX_G2_BR_ALT 0x64 // Alternating branch hint. +#define ND_PREFIX_G2_NO_TRACK 0x3E // Do not track prefix. +#define ND_PREFIX_G3_OPERAND_SIZE 0x66 // Operand size override. +#define ND_PREFIX_G4_ADDR_SIZE 0x67 // Address size override. + +#define ND_PREFIX_REX_MIN 0x40 // First REX prefix. +#define ND_PREFIX_REX_MAX 0x4F // Last REX prefix. +#define ND_PREFIX_VEX_2B 0xC5 // 2B VEX prefix. +#define ND_PREFIX_VEX_3B 0xC4 // 3B VEX prefix. +#define ND_PREFIX_XOP 0x8F // XOP prefix. +#define ND_PREFIX_EVEX 0x62 // EVEX prefix. + + +// +// Instruction flags +// +#define ND_FLAG_MODRM 0x00000001 // The instruction has modrm. +#define ND_FLAG_F64 0x00000002 // The operand is forced to 64 bit. Size changing prefix 0x66 is ignored. +#define ND_FLAG_D64 0x00000004 // The default operand size is 64 bit. Size changing prefix 0x66 + // changes the size to 16 bit. No 32 bit version can be encoded. +#define ND_FLAG_O64 0x00000008 // The instruction is available only in 64 bit mode. +#define ND_FLAG_I64 0x00000010 // The instruction is invalid in 64 bit mode. +#define ND_FLAG_COND 0x00000020 // The instruction has a condition code encoded in low 4 bits of the opcode. +#define ND_FLAG_SSE_CONDB 0x00000040 // The instruction has a SSE condition byte. +#define ND_FLAG_VSIB 0x00000080 // The instruction uses VSIB addressing mode. +#define ND_FLAG_MIB 0x00000100 // The instruction used MIB addressing mode. +#define ND_FLAG_LIG 0x00000200 // L flag inside XOP/VEX/EVEX is ignored. +#define ND_FLAG_WIG 0x00000400 // W flag inside XOP/VEX/EVEX is ignored. +#define ND_FLAG_3DNOW 0x00000800 // The instruction is 3DNow!. The opcode is the last byte. +#define ND_FLAG_LOCK_SPECIAL 0x00001000 // MOV to/from CR in 16/32 bit, on AMD, extend the access to + // high 8 CRs via the LOCK prefix. +#define ND_FLAG_MMASK 0x00002000 // Mandatory mask. The instruction does not accept k0 as mask. +#define ND_FLAG_NOMZ 0x00004000 // Zeroing is not permitted when accessing memory. +#define ND_FLAG_NOL0 0x00008000 // SSE 128 encoding is not permitted for the instruction. +#define ND_FLAG_NOA16 0x00010000 // The instruction does not support 16 bit addressing. +#define ND_FLAG_MFR 0x00020000 // The Mod inside Mod R/M is forced to reg. No SIB/disp present. +#define ND_FLAG_VECTOR 0x00040000 // The instruction is a SIMD instruction that operates on vector regs. +#define ND_FLAG_S66 0x00080000 // Special flag for mandatory 0x66 prefix that actually changes + // the default op length. +#define ND_FLAG_BITBASE 0x00100000 // The instruction uses bitbase addressing mode. +#define ND_FLAG_AG 0x00200000 // The instruction is an address generator; no actual memory access. +#define ND_FLAG_SHS 0x00400000 // The instruction does a shadow stack access. +#define ND_FLAG_CETT 0x00800000 // The instruction is CET tracked. +#define ND_FLAG_SERIAL 0x01000000 // The instruction is serializing. +#define ND_FLAG_NO_RIP_REL 0x02000000 // The instruction doesn't work with RIP relative addressing. +#define ND_FLAG_NO66 0x04000000 // The 0x66 prefix is not accepted by the instruction. +#define ND_FLAG_SIBMEM 0x08000000 // sibmem addressing is used (Intel AMX instructions). + + +// +// Accepted prefixes map +// +#define ND_PREF_REP 0x0001 // The instruction supports REP prefix. +#define ND_PREF_REPC 0x0002 // The instruction supports REPZ/REPNZ prefixes. +#define ND_PREF_LOCK 0x0004 // The instruction supports LOCK prefix. +#define ND_PREF_HLE 0x0008 // The instruction supports XACQUIRE/XRELEASE prefixes. +#define ND_PREF_XACQUIRE 0x0010 // The instruction supports only XACQUIRE. +#define ND_PREF_XRELEASE 0x0020 // The instruction supports only XRELEASE. +#define ND_PREF_BND 0x0040 // The instruction supports BND prefix. +#define ND_PREF_BHINT 0x0080 // The instruction supports branch hints. +#define ND_PREF_HLE_WO_LOCK 0x0100 // HLE prefix is accepted without LOCK. +#define ND_PREF_DNT 0x0200 // The instruction supports the DNT (Do Not Track) CET prefix. + + +// +// Accepted decorators map. These are stored per-instruction. There are also per-operand indicators for +// each decorator. +// +#define ND_DECO_ER 0x01 // Embedded rounding is accepted. +#define ND_DECO_SAE 0x02 // Suppress all Exceptions is accepted. +#define ND_DECO_ZERO 0x04 // Zeroing is accepted. +#define ND_DECO_MASK 0x08 // Masking is accepted. +#define ND_DECO_BROADCAST 0x10 // Memory broadcast is accepted. + + +// +// Operand access flags. +// +#define ND_ACCESS_NONE 0 // The operand is not accessed. +#define ND_ACCESS_READ 1 // The operand is read. +#define ND_ACCESS_WRITE 2 // The operand is written. +#define ND_ACCESS_COND_READ 4 // The operand is read only if some conditions are met. +#define ND_ACCESS_COND_WRITE 8 // The operand is written only if some conditions are met (ie: CMOVcc). +#define ND_ACCESS_ANY_READ (ND_ACCESS_READ | ND_ACCESS_COND_READ) // Any read mask. +#define ND_ACCESS_ANY_WRITE (ND_ACCESS_WRITE | ND_ACCESS_COND_WRITE) // Any write mask. + + +// +// Predicate/condition definitions. +// +#define ND_COND_OVERFLOW 0x0 // OF +#define ND_COND_CARRY 0x2 // CF +#define ND_COND_BELOW 0x2 // CF +#define ND_COND_NOT_ABOVE_OR_EQUAL 0x2 // CF +#define ND_COND_ZERO 0x4 // ZF +#define ND_COND_EQUAL 0x4 // ZF +#define ND_COND_BELOW_OR_EQUAL 0x6 // CF | ZF +#define ND_COND_NOT_ABOVE 0x6 // CF | ZF +#define ND_COND_SIGN 0x8 // SF +#define ND_COND_PARITY 0xA // PF +#define ND_COND_LESS 0xC // SF ^ OF +#define ND_COND_LESS_OR_EQUAL 0xE // (SF ^ OF) | ZF +#define ND_COND_NOT(p) ((p) | 0x1) // Negates the predicate. + +// Kept for backwards compatibility - renamed to ND_COND*. +#define ND_PRED_OVERFLOW 0x0 // OF +#define ND_PRED_CARRY 0x2 // CF +#define ND_PRED_BELOW 0x2 // CF +#define ND_PRED_NOT_ABOVE_OR_EQUAL 0x2 // CF +#define ND_PRED_ZERO 0x4 // ZF +#define ND_PRED_EQUAL 0x4 // ZF +#define ND_PRED_BELOW_OR_EQUAL 0x6 // CF | ZF +#define ND_PRED_NOT_ABOVE 0x6 // CF | ZF +#define ND_PRED_SIGN 0x8 // SF +#define ND_PRED_PARITY 0xA // PF +#define ND_PRED_LESS 0xC // SF ^ OF +#define ND_PRED_LESS_OR_EQUAL 0xE // (SF ^ OF) | ZF +#define ND_PRED_NOT(p) ((p) | 0x1) // Negates the predicate. + + +// +// Condition code definitions. These apply to condition codes encoded in instruction bytes as used by some SSE/AVX +// instructions. +// +#define ND_SSE_COND_EQ 0x00 // Equal. +#define ND_SSE_COND_LT 0x01 // Less-than. +#define ND_SSE_COND_LE 0x02 // Less-than or equal. +#define ND_SSE_COND_UNORD 0x03 // Unordered. +#define ND_SSE_COND_FALSE1 0x03 // False. +#define ND_SSE_COND_NEQ 0x04 // Not equal. +#define ND_SSE_COND_NLT 0x05 // Not less-than. +#define ND_SSE_COND_NLE 0x06 // Not less-than or equal. +#define ND_SSE_COND_ORD 0x07 // Ordered. +#define ND_SSE_COND_TRUE1 0x07 // True. +#define ND_SSE_COND_EQ_UQ 0x08 // Equal. +#define ND_SSE_COND_NGE 0x09 // Not greater-than or equal. +#define ND_SSE_COND_NGT 0x0A // Not greater-than. +#define ND_SSE_COND_FALSE 0x0B // False. +#define ND_SSE_COND_NEQ_OQ 0x0C // Not equal. +#define ND_SSE_COND_GE 0x0D // Greater-than or equal. +#define ND_SSE_COND_GT 0x0E // Greater-than. +#define ND_SSE_COND_TRUE 0x0F // True. +#define ND_SSE_COND_EQ_OS 0x10 // Equal. +#define ND_SSE_COND_LT_OQ 0x11 // Less-than. +#define ND_SSE_COND_LE_OQ 0x12 // Less-than or equal. +#define ND_SSE_COND_UNORD_S 0x13 // Unordered. +#define ND_SSE_COND_NEQ_US 0x14 // Not equal. +#define ND_SSE_COND_NLT_UQ 0x15 // Not less-than. +#define ND_SSE_COND_NLE_UQ 0x16 // Not less-than or equal. +#define ND_SSE_COND_ORD_S 0x17 // Ordered. +#define ND_SSE_COND_EQ_US 0x18 // Equal. +#define ND_SSE_COND_NGE_UQ 0x19 // Not greater-than or equal. +#define ND_SSE_COND_NGT_UQ 0x1A // Not greater-than. +#define ND_SSE_COND_FALSE_OS 0x1B // False. +#define ND_SSE_COND_NEQ_OS 0x1C // Not equal. +#define ND_SSE_COND_GE_OQ 0x1D // Greater-than or equal. +#define ND_SSE_COND_GT_OQ 0x1E // Greater-than. +#define ND_SSE_COND_TRUE_US 0x1F // True. + + +// +// Valid CPU modes. +// +// Group 1: ring +#define ND_MOD_R0 0x0001 // Instruction valid in ring 0. +#define ND_MOD_R1 0x0002 // Instruction valid in ring 1. +#define ND_MOD_R2 0x0004 // Instruction valid in ring 2. +#define ND_MOD_R3 0x0008 // Instruction valid in ring 3. + +// Group 2: operating mode. +#define ND_MOD_REAL 0x0010 // Instruction valid in real mode. +#define ND_MOD_V8086 0x0020 // Instruction valid in virtual 8086 mode. +#define ND_MOD_PROT 0x0040 // Instruction valid in protected mode. +#define ND_MOD_COMPAT 0x0080 // Instruction valid in compatibility mode. +#define ND_MOD_LONG 0x0100 // Instruction valid in long mode. +#define ND_MOD_SMM 0x0200 // Instruction valid in System-Management Mode. + +// Group 3: SGX and TSX +#define ND_MOD_SGX 0x0400 // Instruction valid in SGX enclaves. +#define ND_MOD_TSX 0x0800 // Instruction valid in TSX transactional regions. + +// Group 4: VMX +#define ND_MOD_VMXR 0x1000 // Instruction valid in VMX Root mode. +#define ND_MOD_VMXN 0x2000 // Instruction valid in VMX non-root mode. +#define ND_MOD_VMXO 0x4000 // Instruction valid outside VMX operation. + +#define ND_MOD_RING_MASK 0x000F // Valid ring mask. +#define ND_MOD_MODE_MASK 0x03F0 // Valid mode mask. +#define ND_MOD_OTHER_MASK 0x0C00 // Misc mask. +#define ND_MOD_VMX_MASK 0x7000 // VMX mask. + +// For instructions valid in any operating mode. +#define ND_MOD_ANY 0xFFFF // Instruction valid in any mode. + + +// +// Misc constants +// +#define ND_MAX_INSTRUCTION_LENGTH 15 // 15 bytes is the maximum instruction length supported by the x86 arch. +#define ND_MAX_MNEMONIC_LENGTH 32 // Should do for now. +#define ND_MIN_BUF_SIZE 128 // Textual disassembly minimal buffer size. +#define ND_MAX_OPERAND 10 // No more than 10 operands/instruction, but I'm generous. +#define ND_MAX_REGISTER_SIZE 64 // Maximum register size - 64 bytes. + +#define ND_MAX_GPR_REGS 16 // Max number of GPRs. +#define ND_MAX_SEG_REGS 8 // Max number of segment registers. +#define ND_MAX_FPU_REGS 8 // Max number of FPU registers. +#define ND_MAX_MMX_REGS 8 // Max number of MMX registers. +#define ND_MAX_SSE_REGS 32 // Max number of SSE registers. +#define ND_MAX_CR_REGS 16 // Max number of control registers. +#define ND_MAX_DR_REGS 16 // Max number of debug registers. +#define ND_MAX_TR_REGS 16 // Max number of test registers. +#define ND_MAX_MSK_REGS 8 // Max number of mask registers. +#define ND_MAX_BND_REGS 4 // Max number of bound registers. +#define ND_MAX_SYS_REGS 8 // Max number of system registers. +#define ND_MAX_X87_REGS 8 // Max number of x87 state/control registers registers. +#define ND_MAX_TILE_REGS 8 // Max number of tile registers. + + + +// +// Misc macros. +// + +// Sign extend 8 bit to 64 bit. +#define ND_SIGN_EX_8(x) ((x) & 0x00000080 ? 0xFFFFFFFFFFFFFF00 | (x) : (x)) +// Sign extend 16 bit to 64 bit. +#define ND_SIGN_EX_16(x) ((x) & 0x00008000 ? 0xFFFFFFFFFFFF0000 | (x) : (x)) +// Sign extend 32 bit to 64 bit. +#define ND_SIGN_EX_32(x) ((x) & 0x80000000 ? 0xFFFFFFFF00000000 | (x) : (x)) +// Wrapper for for ND_SIGN_EX_8/ND_SIGN_EX_16/ND_SIGN_EX_32. Sign extend sz bytes to 64 bits. +#define ND_SIGN_EX(sz, x) ((sz) == 1 ? ND_SIGN_EX_8(x) : (sz) == 2 ? ND_SIGN_EX_16(x) : \ + (sz) == 4 ? ND_SIGN_EX_32(x) : (x)) +// Trim 64 bits to sz bytes. +#define ND_TRIM(sz, x) ((sz) == 1 ? (x) & 0xFF : (sz) == 2 ? (x) & 0xFFFF : \ + (sz) == 4 ? (x) & 0xFFFFFFFF : (x)) +// Returns most significant bit, given size in bytes sz. +#define ND_MSB(sz, x) ((sz) == 1 ? ((x) >> 7) & 1 : (sz) == 2 ? ((x) >> 15) & 1 : \ + (sz) == 4 ? ((x) >> 31) & 1 : ((x) >> 63) & 1) +// Returns least significant bit. +#define ND_LSB(sz, x) ((x) & 1) +// Convert a size in bytes to a bitmask. +#define ND_SIZE_TO_MASK(sz) (((sz) < 8) ? ((1ULL << ((sz) * 8)) - 1) : (0xFFFFFFFFFFFFFFFF)) +// Get bit at position bit from x. +#define ND_GET_BIT(bit, x) (((x) >> (bit)) & 1) +// Return the sign of sz bytes long value x. +#define ND_GET_SIGN(sz, x) ND_MSB(sz, x) +// Sets the sign of the sz bytes long value x. +#define ND_SET_SIGN(sz, x) ND_SIGN_EX(sz, x) + +#ifdef BIG_ENDIAN +#define ND_FETCH_64(b) ((uint64_t)FETCH_uint32_t((char *)b) | ((uint64_t)FETCH_uint32_t((char *)b + 4) << 32)) +#define ND_FETCH_32(b) ((uint32_t)FETCH_WORD((char *)b) | ((uint32_t)FETCH_WORD((char *)b + 2) << 16)) +#define ND_FETCH_16(b) ((((char *)b)[0]) | (((char *)b)[1] << 8)) +#define ND_FETCH_8(b) (*((char *)b)) +#else +#define ND_FETCH_64(b) (*((uint64_t *)(b))) +#define ND_FETCH_32(b) (*((uint32_t *)(b))) +#define ND_FETCH_16(b) (*((uint16_t *)(b))) +#define ND_FETCH_8(b) (*((uint8_t *)(b))) +#endif + + +// +// Helper macros which simply test the presence of various ND_FLAG_* in the instruction attributes. +// +#define ND_IS_3DNOW(ix) (!!((ix)->Attributes & ND_FLAG_3DNOW)) +#define ND_HAS_PREDICATE(ix) (!!((ix)->Attributes & ND_FLAG_COND)) +#define ND_HAS_CONDITION(ix) (!!((ix)->Attributes & ND_FLAG_COND)) +#define ND_HAS_SSE_CONDITION(ix) (!!((ix)->Attributes & ND_FLAG_SSE_CONDB)) +#define ND_HAS_MODRM(ix) (!!((ix)->Attributes & ND_FLAG_MODRM)) +#define ND_HAS_VSIB(ix) (!!((ix)->Attributes & ND_FLAG_VSIB)) +#define ND_HAS_MIB(ix) (!!((ix)->Attributes & ND_FLAG_MIB)) +#define ND_HAS_VECTOR(ix) (!!((ix)->Attributes & ND_FLAG_VECTOR)) +#define ND_HAS_BITBASE(ix) (!!((ix)->Attributes & ND_FLAG_BITBASE)) +#define ND_HAS_AG(ix) (!!((ix)->Attributes & ND_FLAG_AG)) +#define ND_HAS_SIBMEM(ix) (!!((ix)->Attributes & ND_FLAG_SIBMEM)) +#define ND_HAS_SHS(ix) (!!((ix)->Attributes & ND_FLAG_SHS)) +#define ND_HAS_CETT(ix) (!!((ix)->Attributes & ND_FLAG_CETT)) + +// +// Supported prefixes macros. +// +#define ND_REP_SUPPORT(ix) (!!((ix)->ValidPrefixes.Rep)) +#define ND_REPC_SUPPORT(ix) (!!((ix)->ValidPrefixes.RepCond)) +#define ND_LOCK_SUPPORT(ix) (!!((ix)->ValidPrefixes.Lock)) +#define ND_HLE_SUPPORT(ix) (!!((ix)->ValidPrefixes.Hle)) +#define ND_XACQUIRE_SUPPORT(ix) (!!((ix)->ValidPrefixes.Xacquire)) +#define ND_XRELEASE_SUPPORT(ix) (!!((ix)->ValidPrefixes.Xrelease)) +#define ND_BND_SUPPORT(ix) (!!((ix)->ValidPrefixes.Bnd)) +#define ND_BHINT_SUPPORT(ix) (!!((ix)->ValidPrefixes.Bhint)) +#define ND_DNT_SUPPORT(ix) (!!((ix)->ValidPrefixes.Dnt)) + +// +// Decorators map macros. +// +#define ND_DECORATOR_SUPPORT(ix) ((ix)->ValidDecorators.Raw != 0) +#define ND_MASK_SUPPORT(ix) (!!((ix)->ValidDecorators.Mask)) +#define ND_ZERO_SUPPORT(ix) (!!((ix)->ValidDecorators.Zero)) +#define ND_ER_SUPPORT(ix) (!!((ix)->ValidDecorators.Er)) +#define ND_SAE_SUPPORT(ix) (!!((ix)->ValidDecorators.Sae)) +#define ND_BROADCAST_SUPPORT(ix) (!!((ix)->ValidDecorators.Broadcast)) + +// Generates a unique ID per register type, size and reg. +#define ND_OP_REG_ID(op) (((op)->Type << 24) | ((op)->Info.Register.Type << 16) | \ + ((op)->Info.Register.Size << 8) | ((op)->Info.Register.Reg)) + +// Example: ND_IS_OP_REG(op, ND_REG_GPR, 4, REG_ESP) +// Example: ND_IS_OP_REG(op, ND_REG_CR, 8, REG_CR3) +// Example: ND_IS_OP_REG(op, ND_REG_RIP, 8, 0) + +// Checks if the indicated operand op is a register of type t, with size s and index r. +#define ND_IS_OP_REG(op, t, s, r) ((uint32_t)(ND_OP_REG_ID(op)) == (uint32_t)((ND_OP_REG << 24)|(t << 16)|(s << 8)|(r))) + +// Checjs if the indicated operand is the stack. +#define ND_IS_OP_STACK(op) ((op)->Type == ND_OP_MEM && (op)->Info.Memory.IsStack) + + +// +// Operand types. +// +typedef enum _ND_OPERAND_TYPE +{ + ND_OP_NOT_PRESENT, // Indicates the absence of any operand. + ND_OP_REG, // The operand is a register. + ND_OP_MEM, // The operand is located in memory. + ND_OP_IMM, // The operand is an immediate. + ND_OP_OFFS, // The operand is a relative offset. + ND_OP_ADDR, // The operand is an absolute address, in the form seg:offset. + ND_OP_CONST, // The operand is an implicit constant. + ND_OP_BANK, // An entire bank/set of registers are being accessed. Used in PUSHA/POPA/XSAVE/LOADALL. +} ND_OPERAND_TYPE; + + +// +// Register types. +// +typedef enum _ND_REG_TYPE +{ + ND_REG_NOT_PRESENT, + ND_REG_GPR, // The register is a 8/16/32/64 bit general purpose register. + ND_REG_SEG, // The register is a segment register. + ND_REG_FPU, // The register is a 80-bit FPU register. + ND_REG_MMX, // The register is a 64-bit MMX register. + ND_REG_SSE, // The register is a 128/256/512 bit SSE vector register. + ND_REG_CR, // The register is a control register. + ND_REG_DR, // The register is a debug register. + ND_REG_TR, // The register is a test register. + ND_REG_BND, // The register is a bound register. + ND_REG_MSK, // The register is a mask register. + ND_REG_TILE, // The register is a tile register. + ND_REG_MSR, // The register is a model specific register. + ND_REG_XCR, // The register is a extended control register. + ND_REG_SYS, // The register is a system register. + ND_REG_X87, // The register is a x87 status/control register. + ND_REG_MXCSR, // The register is the MXCSR register. + ND_REG_PKRU, // The register is the PKRU register. + ND_REG_SSP, // The register is the SSP (Shadow Stack Pointer) register. + ND_REG_FLG, // The register is the FLAGS register. + ND_REG_RIP, // The register is the instruction pointer register. +} ND_REG_TYPE; + + +// +// Operand encoding types. +// +typedef enum _ND_OPERAND_ENCODING +{ + ND_OPE_NP, // No encoding present. + ND_OPE_R, // Operand encoded in modrm.reg. + ND_OPE_M, // Operand encoded in modrm.rm. + ND_OPE_V, // Operand encoded in Xop/Vex/Evex/Mvex.(v')vvvv + ND_OPE_D, // Operand is encoded inside subsequent instruction bytes. + ND_OPE_O, // Operand is encoded in low 3 bit of the opcode. + ND_OPE_I, // Operand is an immediate. + ND_OPE_C, // Operand is CL. + ND_OPE_1, // Operand is 1. + ND_OPE_L, // Operand is reg encoded in immediate. + ND_OPE_A, // Operand is encoded in Evex.aaa. + ND_OPE_E, // Operand is a MSR or XCR encoded in ECX register. + ND_OPE_S, // Operand is implicit/suppressed. Not encoded anywhere. +} ND_OPERAND_ENCODING; + + +// +// Instruction tuple type; used to determine compressed displacement size for disp8 EVEX instructions. Note that +// most of the EVEX encoded instructions use the compressed displacement addressing scheme. +// +typedef enum _ND_TUPLE +{ + ND_TUPLE_None, + ND_TUPLE_FV, // Full Vector + ND_TUPLE_HV, // Half Vector + ND_TUPLE_T1S8, // Tuple1 scalar, size 8 bit + ND_TUPLE_T1S16, // Tuple1 scalar, size 16 bit + ND_TUPLE_T1S, // Tuple1 scalar, size 32/64 bit + ND_TUPLE_T1F, // Tuple1 float, size 32/64 bit + ND_TUPLE_T2, // Tuple2, 64/128 bit + ND_TUPLE_T4, // Tuple4, 128/256 bit + ND_TUPLE_T8, // Tuple8, 256 bit + ND_TUPLE_FVM, // Full Vector Memory + ND_TUPLE_HVM, // Half Vector Memory + ND_TUPLE_QVM, // Quarter Vector Memory + ND_TUPLE_OVM, // Oct Vector Memory + ND_TUPLE_M128, // M128, 128 bit + ND_TUPLE_DUP, // DUP (VMOVDDUP) + ND_TUPLE_T1_4X, // 4 x 32 bit Memory Elements are referenced +} ND_TUPLE; + + +// +// EVEX rounding control. +// +typedef enum _ND_ROUNDING +{ + ND_RND_RNE, // Round to nearest equal. + ND_RND_RD, // Round down. + ND_RND_RU, // Round up. + ND_RND_RZ, // round to zero. +} ND_ROUNDING; + + +// +// Exception classes. Different instruction sets or encodings are covered by different exception classes. +// +typedef enum _ND_EX_CLASS +{ + ND_EXC_None, + ND_EXC_SSE_AVX, // SSE/AVX exception class (for legacy encoded SSE instructions and VEX instructions). + ND_EXC_EVEX, // EVEX exception class (for EVEX encoded AVX* instructions). + ND_EXC_OPMASK, // Opmask instructions exception class. + ND_EXC_AMX, // AMX exception class type (for VEX encoded AMX instructions). +} ND_EX_CLASS; + + +// +// SSE/AVX exception types. Covers VEX instructions as well, except for AMX instructions. +// +typedef enum _ND_EX_TYPE_SSE_AVX +{ + ND_EXT_SSE_AVX_None, + ND_EXT_1, + ND_EXT_2, + ND_EXT_3, + ND_EXT_4, + ND_EXT_5, + ND_EXT_6, + ND_EXT_7, + ND_EXT_8, + ND_EXT_9, + ND_EXT_10, + ND_EXT_11, + ND_EXT_12, + ND_EXT_13, +} ND_EX_TYPE_SSE_AVX; + + +// +// EVEX exception types. +// +typedef enum _ND_EX_TYPE_EVEX +{ + ND_EXT_EVEX_None, + ND_EXT_E1, + ND_EXT_E1NF, + ND_EXT_E2, + ND_EXT_E3, + ND_EXT_E3NF, + ND_EXT_E4, + ND_EXT_E4nb, + ND_EXT_E4NF, + ND_EXT_E4NFnb, + ND_EXT_E5, + ND_EXT_E5NF, + ND_EXT_E6, + ND_EXT_E6NF, + ND_EXT_E7NM, + ND_EXT_E9, + ND_EXT_E9NF, + ND_EXT_E10, + ND_EXT_E10NF, + ND_EXT_E11, + ND_EXT_E12, + ND_EXT_E12NP, +} ND_EX_TYPE_EVEX; + + +// +// Opmask exception types. +// +typedef enum _ND_EX_TYPE_OPMASK +{ + ND_EXT_OPMASK_None, + ND_EXT_K20, + ND_EXT_K21, +} ND_EX_TYPE_OPMASK; + + +// +// AMX exception types. +// +typedef enum _ND_EX_TYPE_AMX +{ + ND_EXT_AMX_None, + ND_EXT_AMX_E1, + ND_EXT_AMX_E2, + ND_EXT_AMX_E3, + ND_EXT_AMX_E4, + ND_EXT_AMX_E5, + ND_EXT_AMX_E6, +} ND_EX_TYPE_AMX; + + +// +// Operands access map. Contains every register except for MSR & XCR, includes memory, flags, RIP, stack. +// Use NdGetFullAccessMap to populate this structure. +// +typedef struct _ND_ACCESS_MAP +{ + uint8_t RipAccess; + uint8_t FlagsAccess; + uint8_t StackAccess; + uint8_t MemAccess; + uint8_t MxcsrAccess; + uint8_t PkruAccess; + uint8_t SspAccess; + uint8_t GprAccess[ND_MAX_GPR_REGS]; + uint8_t SegAccess[ND_MAX_SEG_REGS]; + uint8_t FpuAccess[ND_MAX_FPU_REGS]; + uint8_t MmxAccess[ND_MAX_MMX_REGS]; + uint8_t SseAccess[ND_MAX_SSE_REGS]; + uint8_t CrAccess [ND_MAX_CR_REGS ]; + uint8_t DrAccess [ND_MAX_DR_REGS ]; + uint8_t TrAccess [ND_MAX_TR_REGS ]; + uint8_t BndAccess[ND_MAX_BND_REGS]; + uint8_t MskAccess[ND_MAX_MSK_REGS]; + uint8_t SysAccess[ND_MAX_SYS_REGS]; + uint8_t X87Access[ND_MAX_X87_REGS]; +} ND_ACCESS_MAP, *PND_ACCESS_MAP; + + + +// +// Operand access mode. +// +typedef union _ND_OPERAND_ACCESS +{ + uint8_t Access; + struct + { + uint8_t Read : 1; // The operand is read. + uint8_t Write : 1; // The operand is written. + uint8_t CondRead : 1; // The operand is read only under some conditions. + uint8_t CondWrite : 1; // The operand is written only under some conditions. + }; +} ND_OPERAND_ACCESS; + + +// +// Operand flags. +// +typedef union _ND_OPERAND_FLAGS +{ + uint8_t Flags; + struct + { + uint8_t IsDefault : 1; // 1 if the operand is default. This also applies to implicit ops. + uint8_t SignExtendedOp1 : 1; // 1 if the operand is sign extended to the first operands' size. + uint8_t SignExtendedDws : 1; // 1 if the operand is sign extended to the default word size. + }; +} ND_OPERAND_FLAGS; + + +// +// Constant operand. +// +typedef struct _ND_OPDESC_CONSTANT +{ + uint64_t Const; // Instruction constant, ie ROL reg, 1. +} ND_OPDESC_CONSTANT; + + +// +// Immediate operand. +// +typedef struct _ND_OPDESC_IMMEDIATE +{ + uint64_t Imm; // Immediate. Only Size bytes are valid. The rest are undefined. +} ND_OPDESC_IMMEDIATE; + + +// +// Relative offset operand. +// +typedef struct _ND_OPDESC_REL_OFFSET +{ + uint64_t Rel; // Relative offset (relative to the current RIP). Sign extended. +} ND_OPDESC_RELOFFSET; + + +// +// Describes a register operand. Count registers are used starting with Reg. +// +typedef struct _ND_OPDESC_REGISTER +{ + ND_REG_TYPE Type; // The register type. See enum ND_REG_TYPE. + ND_REG_SIZE Size; // Indicates the register size. This may not be equal to the Size + // field, as a smaller amount of data may be processed from a + // register (especially if we have a SSE register or a mask register). + // Also note that as of now, 64 bytes is the maximum register size. + uint32_t Reg; // The register number/ID. + uint32_t Count; // The number of registers accessed, starting with Reg. + + bool IsHigh8:1; // TRUE if this is AH, CH, DH or BH register. + bool IsBlock:1; // TRUE if this is a block register addressing. +} ND_OPDESC_REGISTER; + + +// +// Describes an address operand. +// +typedef struct _ND_OPDESC_ADDRESS +{ + // Size is the size of the address. Usually 4 (16 bit mode) or 6 (32 bit mode) or 10 (64 bit). + uint16_t BaseSeg; // Base segment selector of the address. + uint64_t Offset; // Offset inside the segment. +} ND_OPDESC_ADDRESS; + + +// +// Describes a memory operand. +// +typedef struct _ND_OPDESC_MEMORY +{ + bool HasSeg:1; // TRUE if segment is present & used. + bool HasBase:1; // TRUE if base register is present. + bool HasIndex:1; // TRUE if index & scale are present. + bool HasDisp:1; // TRUE if displacement is present. + bool HasCompDisp:1; // TRUE if compressed disp8 is used (EVEX instructions). + bool HasBroadcast:1; // TRUE if the memory operand is a broadcast operand. + + bool IsRipRel:1; // TRUE if this is a rip-relative addressing. Base, Index, Scale are + // all ignored. + bool IsStack:1; // TRUE if this is a stack op. Note that explicit stack accesses are not + // included (eg: mov eax, [rsp] will NOT set IsStack). + bool IsString:1; // TRUE for [RSI] and [RDI] operands inside string operations. + bool IsShadowStack:1; // TRUE if this is a shadow stack access. + bool IsDirect:1; // TRUE if direct addressing (MOV [...], EAX, 0xA3). + bool IsBitbase:1; // TRUE if this is a bit base. Used for BT* instructions. The bitbase + // stored in the second operand must be added to the linear address. + bool IsAG:1; // TRUE if the memory operand is address generation and no mem access is + // made. + bool IsMib:1; // TRUE if MIB addressing is used (MPX instructions). + bool IsVsib:1; // TRUE if the index register selects a vector register. + bool IsSibMem:1; // TRUE if the addressing uses sibmem (AMX instructions). + + + ND_REG_SIZE BaseSize; // Base size, in bytes. Max 8 bytes. + ND_REG_SIZE IndexSize; // Ditto for index size. Max 8 bytes. + uint8_t DispSize; // Displacement size. Max 4 bytes. + uint8_t CompDispSize; // Compressed displacement size - 1, 2, 4, 8, 16, 32, 64. + + struct + { + uint8_t IndexSize; // VSIB index size. + uint8_t ElemSize; // VSIB element size. + uint8_t ElemCount; // Number of elements scattered/gathered/prefetched. + } Vsib; + + uint8_t Seg; // Base segment used to address the memory. 0 = es, 1 = cs, etc. + uint8_t Base; // Base register. Can only be a GPR. + uint8_t Index; // Index register. Can be a vector reg (ZMM0-ZMM31). + uint8_t Scale; // Scale: 1, 2, 4 or 8. Always present if Index is present. + + uint64_t Disp; // Sign extended displacement. + +} ND_OPDESC_MEMORY; + + +// +// Describes a decorator. +// +typedef struct _ND_OPERAND_DECORATOR +{ + bool HasMask:1; // TRUE if mask is present, 0 otherwise. + bool HasZero:1; // TRUE if zeroing will be made, 0 if merging will be made. + bool HasBroadcast:1; // TRUE if broadcasting is being made. Valid only for memory operands. + + // These are used only to indicate where the SAE and ER decorators should be placed in the disassembly. + // Otherwise, SAE and ER are global, per instruction, and don't apply to a single operand. + bool HasSae:1; // TRUE if SAE is present. + bool HasEr:1; // TRUE if ER is present. + + // Mask register specifier. + struct + { + uint8_t Msk; // Mask register used. Only k0-k7 can be encoded. + } Mask; + + // Broadcast specifier + struct + { + uint8_t Count; // Number of times to broadcast the element. + uint8_t Size; // Size of one element. + } Broadcast; + +} ND_OPERAND_DECORATOR; + + +// +// Extended operand information. +// +typedef struct _ND_OPERAND +{ + ND_OPERAND_TYPE Type; // Operand type. One of ND_OPERAND_TYPE enumerations. + ND_OPERAND_ENCODING Encoding; // Where is the operand encoded - modrm.reg, modrm.rm, etc. + ND_OPERAND_SIZE Size; // Operand size in bytes. This should be used when operating with + // the operand. It includes sign-extension or zero-extensions. + // Note that the Size field indicates the actual amount of data + // used for processing. If the operand type is a register, it MAY NOT + // indicate the register size. Use the Info.Register.Size + // field to get the actual register size. + ND_OPERAND_SIZE RawSize; // Raw size inside the instruction. This will usually be identical + // to Size; however, some instructions force the actual size of their + // operands to 64 bit; PUSH/POP or branches are good examples; although + // the raw size of the relative offset or the immediate will be RawSize, + // internally, the CPU will use Size (usually sign-extended). + ND_OPERAND_ACCESS Access; // Access mode (read, write, read-write, etc.) + ND_OPERAND_FLAGS Flags; // Misc operand flags. + + // Depending in the Type field, one of these subfields contains information about the operand. + union + { + ND_OPDESC_CONSTANT Constant; // Constant, if operand type is ND_OP_CONST. + ND_OPDESC_IMMEDIATE Immediate; // Immediate, if operand type is ND_OP_IMM. + ND_OPDESC_REGISTER Register; // Register, if operand type if ND_OP_REG. + ND_OPDESC_RELOFFSET RelativeOffset; // Relative offset, if operand type is ND_OP_REL_OFFS. + ND_OPDESC_ADDRESS Address; // Address, if operand type is ND_OP_ADDR. + ND_OPDESC_MEMORY Memory; // Memory, if operand type is ND_OP_MEM. + } Info; + + ND_OPERAND_DECORATOR Decorator; // Decorator information. + +} ND_OPERAND, *PND_OPERAND; + + + +// +// REX prefix. +// +typedef union _ND_REX +{ + uint8_t Rex; + struct + { + uint8_t b : 1; // b (rm or low opcode) extension field. + uint8_t x : 1; // x (index) extension field. + uint8_t r : 1; // r (reg) extension field. + uint8_t w : 1; // w (size) extension field. Promotes to 64 bit. + }; +} ND_REX; + + +// +// Mod R/M byte. +// +typedef union _ND_MODRM +{ + uint8_t ModRm; + struct + { + uint8_t rm : 3; // rm field. + uint8_t reg : 3; // reg field. + uint8_t mod : 2; // mod field. Indicates memory access (0, 1 or 2), or register access (3). + }; +} ND_MODRM; + + +// +// SIB byte. +// +typedef union _ND_SIB +{ + uint8_t Sib; + struct + { + uint8_t base : 3; // Base register. + uint8_t index : 3; // Index register. + uint8_t scale : 2; // Scale. + }; +} ND_SIB; + + +// +// DREX byte. Exactly as AMD defined it. No actual instructions exist that use DREX encoding. +// +typedef union _ND_DREX +{ + uint8_t Drex; + struct + { + uint8_t b : 1; + uint8_t x : 1; + uint8_t r : 1; + uint8_t oc0 : 1; + uint8_t vd : 3; + uint8_t d : 1; + }; +} ND_DREX; + + +// +// 2-bytes VEX. Exactly as Intel defined it. +// +typedef union _ND_VEX2 +{ + uint8_t Vex[2]; + struct + { + uint8_t op; // 0xC5 + + uint8_t p : 2; // p0, p1 + uint8_t l : 1; // L + uint8_t v : 4; // ~v0, ~v1, ~v2, ~v3 + uint8_t r : 1; // ~R + }; +} ND_VEX2; + + +// +// 3-bytes VEX. Exactly as Intel defined it. +// +typedef union _ND_VEX3 +{ + uint8_t Vex[3]; + struct + { + uint8_t op; // 0xC4 + + uint8_t m : 5; // m0, m1, m2, m3, m4 + uint8_t b : 1; // ~B + uint8_t x : 1; // ~X + uint8_t r : 1; // ~R + + uint8_t p : 2; // p0, p1 + uint8_t l : 1; // L + uint8_t v : 4; // ~v0, ~v1, ~v2, ~v3 + uint8_t w : 1; // W + }; +} ND_VEX3; + + +// +// XOP. Exactly as AMD defined it. +// +typedef union _ND_XOP +{ + uint8_t Xop[3]; + struct + { + uint8_t op; // 0x8F + + uint8_t m : 5; // m0, m1, m2, m3, m4 + uint8_t b : 1; // ~B + uint8_t x : 1; // ~X + uint8_t r : 1; // ~R + + uint8_t p : 2; // p0, p1 + uint8_t l : 1; // L + uint8_t v : 4; // ~v0, ~v1, ~v2, ~v3 + uint8_t w : 1; // W + }; +} ND_XOP; + + +// +// EVEX prefix. Exactly as Intel defined it. +// +typedef union _ND_EVEX +{ + uint8_t Evex[4]; + struct + { + uint8_t op; // 0x62 + + uint8_t m : 2; // m0, m1 + uint8_t zero : 2; // 00 + uint8_t rp : 1; // ~R' + uint8_t b : 1; // ~B + uint8_t x : 1; // ~X + uint8_t r : 1; // ~R + + uint8_t p : 2; // p0, p1 + uint8_t one : 1; // 1 + uint8_t v : 4; // ~v0, ~v1, ~v2, ~v3 + uint8_t w : 1; // W + + uint8_t a : 3; // a0, a1, a2 + uint8_t vp : 1; // ~V' + uint8_t bm : 1; // b + uint8_t l : 2; // L'L + uint8_t z : 1; // z + }; +} ND_EVEX; + + +// +// Describes the CPUID leaf, sub-leaf, register & bit that indicate whether an instruction is supported or not. +// If Leaf == ND_CFF_NO_LEAF, the instruction is supported on any CPU, and no CPUID flag exists. +// If SubLeaf == ND_CFF_NO_SUBLEAF, there is no subleaf to check. +// +typedef union _ND_CPUID_FLAG +{ + uint64_t Flag; + struct + { + uint32_t Leaf; // CPUID leaf. ND_CFF_NO_LEAF if not applicable. + uint32_t SubLeaf : 24; // CPUID sub-leaf. ND_CFF_NO_SUBLEAF if not applicable. + uint32_t Reg : 3; // The register that contains info regarding the instruction. + uint32_t Bit : 5; // Bit inside the register that indicates whether the instruction is present. + }; +} ND_CPUID_FLAG; + + +// +// Each instruction may accept one or more prefixes. This structure indicates which prefixes are valid for the +// given instruction. +// +typedef union _ND_VALID_PREFIXES +{ + uint16_t Raw; + struct + { + uint16_t Rep : 1; // The instruction supports REP prefix. + uint16_t RepCond : 1; // The instruction supports REPZ/REPNZ prefixes. + uint16_t Lock : 1; // The instruction supports LOCK prefix. + uint16_t Hle : 1; // The instruction supports XACQUIRE/XRELEASE prefixes. + uint16_t Xacquire : 1; // The instruction supports only XACQUIRE. + uint16_t Xrelease : 1; // The instruction supports only XRELEASE. + uint16_t Bnd : 1; // The instruction supports BND prefix. + uint16_t Bhint : 1; // The instruction supports branch hints. + uint16_t HleNoLock : 1; // HLE prefix is accepted without LOCK. + uint16_t Dnt : 1; // The instruction supports the DNT (Do Not Track) CET prefix. + }; +} ND_VALID_PREFIXES, *PND_VALID_PREFIXES; + + +// +// Each instruction may accept several decorators. This instruction indicates which decorators are valid for the +// given instruction. +// +typedef union _ND_VALID_DECORATORS +{ + uint8_t Raw; + struct + { + uint8_t Er : 1; // The instruction supports embedded rounding mode. + uint8_t Sae : 1; // The instruction supports suppress all exceptions mode. + uint8_t Zero : 1; // The instruction supports zeroing. + uint8_t Mask : 1; // The instruction supports mask registers. + uint8_t Broadcast : 1; // The instruction supports broadcast. + }; +} ND_VALID_DECORATORS, *PND_VALID_DECORATORS; + + +// +// Each instruction is valid or invalid in any certain mode. This indicates which modes the instruction is valid in. +// If the bit is set, the isntruction is valid in that given mode. +// +typedef union _ND_VALID_MODES +{ + uint16_t Raw; + struct + { + // Group 1: privilege level. + uint16_t Ring0 : 1; // The instruction is valid in ring 0. + uint16_t Ring1 : 1; // The instruction is valid in ring 1. + uint16_t Ring2 : 1; // The instruction is valid in ring 2. + uint16_t Ring3 : 1; // The instruction is valid in ring 3. + + // Group 2: operating mode - the CPU can be on only one of these modes at any moment. + uint16_t Real : 1; // The instruction is valid in real mode. + uint16_t V8086 : 1; // The instruction is valid in Virtual 8086 mode. + uint16_t Protected : 1; // The instruction is valid in protected mode (32 bit). + uint16_t Compat : 1; // The instruction is valid in compatibility mode (32 bit in 64 bit). + uint16_t Long : 1; // The instruction is valid in long mode. + uint16_t Smm : 1; // The instruction is valid in System Management Mode. + + // Group 3: special modes - these may be active inside other modes (example: TSX in Long mode). + uint16_t Sgx : 1; // The instruction is valid in SGX mode. + uint16_t Tsx : 1; // The instruction is valid in transactional regions. + + // Group 4: VMX mode - they engulf all the other modes. + uint16_t VmxRoot : 1; // The instruction is valid in VMX root mode. + uint16_t VmxNonRoot : 1;// The instruction is valid in VMX non root mode. + uint16_t VmxOff : 1; // The instruction is valid outside VMX operation. + }; +} ND_VALID_MODES, *PND_VALID_MODES; + + +// +// RFLAGS register. This structure reflects the actual position of each flag insdide the RFLAGS register, so it can +// be used for direct processing. +// +typedef union _ND_RFLAGS +{ + uint32_t Raw; + struct + { + uint32_t CF : 1; // Carry flag. + uint32_t Reserved1 : 1; // Reserved, must be 1. + uint32_t PF : 1; // Parity flag. + uint32_t Reserved2 : 1; // Reserved. + uint32_t AF : 1; // Auxiliary flag. + uint32_t Reserved3 : 1; // Reserved. + uint32_t ZF : 1; // Zero flag. + uint32_t SF : 1; // Sign flag. + uint32_t TF : 1; // Trap flag. + uint32_t IF : 1; // Interrupt flag. + uint32_t DF : 1; // Direction flag. + uint32_t OF : 1; // Overflow flag. + uint32_t IOPL : 2; // I/O privilege level flag. + uint32_t NT : 1; // Nested task flag. + uint32_t Reserved4 : 1; // Reserved. + uint32_t RF : 1; // Resume flag. + uint32_t VM : 1; // Virtual mode flag. + uint32_t AC : 1; // Alignment check flag. + uint32_t VIF : 1; // Virtual interrupts flag. + uint32_t VIP : 1; // Virtual interrupt pending flag. + uint32_t ID : 1; // CPUID identification flag. + }; +} ND_RFLAGS, *PND_RFLAGS; + + +#define ND_FPU_FLAG_SET_0 0 // The FPU status flag is cleared to 0. +#define ND_FPU_FLAG_SET_1 1 // The FPU status flag is set to 1. +#define ND_FPU_FLAG_MODIFIED 2 // The FPU status flag is modified according to a result. +#define ND_FPU_FLAG_UNDEFINED 3 // The FPU status flag is undefined or unaffected. + +// +// FPU status flags. Each status flag can be one of ND_FPU_FLAG*. +// +typedef struct _ND_FPU_FLAGS +{ + uint8_t C0 : 2; // C0 flag access mode. See ND_FPU_FLAG_*. + uint8_t C1 : 2; // C1 flag access mode. See ND_FPU_FLAG_*. + uint8_t C2 : 2; // C2 flag access mode. See ND_FPU_FLAG_*. + uint8_t C3 : 2; // C3 flag access mode. See ND_FPU_FLAG_*. +} ND_FPU_FLAGS, *PND_FPU_FLAGS; + + +// +// Describes a decoded instruction. All the possible information about the instruction is contained in this structure. +// You don't have to call any other APIs to gather any more info about it. +// +typedef struct _INSTRUX +{ + uint8_t DefCode:4; // ND_CODE_*. Indicates disassembly mode. + uint8_t DefData:4; // ND_DATA_*. Indicates default data size. + uint8_t DefStack:4; // ND_STACK_*. Indicates default stack pointer width. + uint8_t EncMode:4; // ND_ENCM_*. Indicates encoding mode. + uint8_t VexMode:4; // ND_VEX_*. Indicates the VEX mode, if any. + uint8_t AddrMode:4; // ND_ADDR_*. Indicates addressing mode. + uint8_t OpMode:4; // ND_OPSZ_*. Indicates operand mode/size. + uint8_t EfOpMode:4; // ND_OPSZ_*. Indicates effective operand mode/size. + uint8_t VecMode:4; // ND_VECM_*. Indicates vector length. + uint8_t EfVecMode:4; // ND_VECM_*. Indicates effective vector length. + + // Prefixes. + bool HasRex:1; // TRUE - REX is present. + bool HasVex:1; // TRUE - VEX is present. + bool HasXop:1; // TRUE - XOP is present. + bool HasEvex:1; // TRUE - EVEX is present. + bool HasMvex:1; // TRUE - MVEX is present. + bool HasOpSize:1; // TRUE - 0x66 present. + bool HasAddrSize:1; // TRUE - 0x67 present. + bool HasLock:1; // TRUE - 0xF0 present. + bool HasRepnzXacquireBnd:1; // TRUE - 0xF2 present. + bool HasRepRepzXrelease:1; // TRUE - 0xF3 present. + bool HasSeg:1; // TRUE - segment override present. + + // Indicators for prefix activation. + bool IsRepeated:1; // TRUE - the instruction is REPed up to RCX times. + bool IsXacquireEnabled:1; // TRUE - the instruction is XACQUIRE enabled. + bool IsXreleaseEnabled:1; // TRUE - the instruction is XRELEASE enabled. + bool IsRipRelative:1; // TRUE - the instruction uses RIP relative addressing. + bool IsCetTracked:1; // TRUE - this is an indirect CALL/JMP that is CET tracked. + + // Instruction chunks. + bool HasModRm:1; // TRUE - we have valid MODRM. + bool HasSib:1; // TRUE - we have valid SIB. + bool HasDrex:1; // TRUE - we have valid DREX. + bool HasDisp:1; // TRUE - the instruction has displacement. + bool HasAddr:1; // TRUE - the instruction contains a direct address (ie, CALL far 0x9A) + bool HasMoffset:1; // TRUE - the instruction contains a moffset (ie, MOV al, [mem], 0xA0) + bool HasImm1:1; // TRUE - immediate present. + bool HasImm2:1; // TRUE - second immediate present. + bool HasImm3:1; // TRUE - third immediate present. + bool HasRelOffs:1; // TRUE - the instruction contains a relative offset (ie, Jcc 0x7x). + bool HasSseImm:1; // TRUE - SSE immediate that encodes additional registers is present. + bool HasCompDisp:1; // TRUE - the instruction uses compressed displacement + bool HasBroadcast:1; // TRUE - the instruction uses broadcast addressing + bool HasMask:1; // TRUE - the instruction has mask. + bool HasZero:1; // TRUE - the instruction uses zeroing. + bool HasEr:1; // TRUE - the instruction has embedded rounding. + bool HasSae:1; // TRUE - the instruction has SAE. + + bool SignDisp:1; // Displacement sign. 0 is positive, 1 is negative. + + // Encoding specifics. + bool HasMandatory66:1; // 0x66 is mandatory prefix. Does not behave as size-changing prefix. + bool HasMandatoryF2:1; // 0x66 is mandatory prefix. Does not behave as REP prefix. + bool HasMandatoryF3:1; // 0x66 is mandatory prefix. Does not behave as REP prefix. + + // Instruction components lengths. Will be 0 if the given field is not present. + uint8_t Length; // 1-15 valid. Instructions longer than 15 bytes will cause #GP. + + uint8_t WordLength:4; // The length of the instruction word. 2, 4 or 8. + uint8_t PrefLength:4; // The total number of bytes consumed by prefixes. This will also be + // the offset to the first opcode. The primary opcode will always be + // the last one, so at offset PrefixesLength + OpcodeLength - 1 + uint8_t OpLength:4; // Number of opcode bytes. Max 3. + uint8_t DispLength:4; // Displacement length, in bytes. Maximum 4. + uint8_t AddrLength:4; // Absolute address length, in bytes. Maximum 8 bytes. + uint8_t MoffsetLength:4; // Memory offset length, in bytes. Maximum 8 bytes. + uint8_t Imm1Length:4; // First immediate length, in bytes. Maximum 8 bytes. + uint8_t Imm2Length:4; // Second immediate length, in bytes. Maximum 8 bytes. + uint8_t Imm3Length:4; // Third immediate length, in bytes. Maximum 8 bytes. + uint8_t RelOffsLength:4; // Relative offset length, in bytes. Maximum 4 bytes. + + // Instruction components offsets. Will be 0 if the given field is not present. Prefixes ALWAYS start at offset 0. + uint8_t OpOffset:4; // The offset of the first opcode, inside the instruction. + uint8_t MainOpOffset:4; // The offset of the nominal opcode, inside the instruction. + uint8_t DispOffset:4; // The offset of the displacement, inside the instruction + uint8_t AddrOffset:4; // The offset of the hard-coded address. + uint8_t MoffsetOffset:4; // The offset of the absolute address, inside the instruction + uint8_t Imm1Offset:4; // The offset of the immediate, inside the instruction + uint8_t Imm2Offset:4; // The offset of the second immediate, if any, inside the instruction + uint8_t Imm3Offset:4; // The offset of the third immediate, if any, inside the instruction + uint8_t RelOffsOffset:4; // The offset of the relative offset used in instruction. + uint8_t SseImmOffset:4; // The offset of the SSE immediate, if any, inside the instruction. + uint8_t ModRmOffset:4; // The offset of the mod rm byte inside the instruction, if any. + // If SIB is also present, it will always be at ModRmOffset + 1. + + uint8_t StackWords; // Number of words accessed on/from the stack. + + uint8_t Rep; // The last rep/repz/repnz prefix. 0 if none. + uint8_t Seg; // The last segment override prefix. 0 if none. FS/GS if 64 bit. + uint8_t Bhint; // The last segment override indicating a branch hint. + ND_REX Rex; // REX prefix. + ND_MODRM ModRm; // ModRM byte. + ND_SIB Sib; // SIB byte. + ND_DREX Drex; // DREX byte. Part of AMD SSE 5. Never shipped. + + union + { + ND_VEX2 Vex2; // VEX 2 prefix. + ND_VEX3 Vex3; // VEX 3 prefix. + ND_XOP Xop; // XOP prefix. + ND_EVEX Evex; // EVEX prefix. + }; + + // This structures contains the fields extracted from either REX, XOP, VEX, EVEX or MVEX fields. They're globally + // placed here, in order to avoid testing for each kind of prefix each time. Instead, one can use the different + // fields directly from here, regardless the actual encoding mode. + struct + { + uint32_t w:1; // REX/XOP/VEX/EVEX/MVEX.W field + uint32_t r:1; // REX/XOP/VEX/EVEX/MVEX.R field (reg extension) + uint32_t x:1; // REX/XOP/VEX/EVEX/MVEX.X field (index extension) + uint32_t b:1; // REX/XOP/VEX/EVEX/MVEX.B field (base extension) + uint32_t rp:1; // EVEX/MVEX.R' (reg extension) + uint32_t p:2; // XOP/VEX/EVEX/MVEX.pp (embedded prefix) + uint32_t m:5; // XOP/VEX/EVEX/MVEX.mmmmm (decoding table) + uint32_t l:2; // XOP/VEX.L or EVEX.L'L (vector length) + uint32_t v:4; // XOP/VEX.VVVV or EVEX/MVEX.VVVV (additional operand) + uint32_t vp:1; // EVEX/MVEX.V' (vvvv extension) + uint32_t bm:1; // EVEX.b (broadcast) + uint32_t e:1; // MVEX.e (eviction hint) + uint32_t z:1; // EVEX.z (zero) + uint32_t k:3; // EVEX.aaa/MVEX.kkk (mask registers) + uint32_t s:3; // MVEX.sss (swizzle) + } Exs; + + union + { + struct + { + uint32_t Ip; + uint16_t Cs; + }; + } Address; // seg:offset address. + + uint64_t Moffset; // Offset. Used by 'O' operands. It's an absolute address. + uint32_t Displacement; // Displacement. Max 4 bytes. Used in ModRM instructions. + uint32_t RelativeOffset; // Relative offset, used for branches. Max 4 bytes. + uint64_t Immediate1; // Can be 8 bytes on x64 + uint8_t Immediate2; // For enter, mainly. Can only be 1 byte. + uint8_t Immediate3; // Third additional immediate. Limited to 1 byte for now. + uint8_t SseImmediate; // This immediate actually selects a register. + uint8_t SseCondition; // Condition code encoded in additional byte. + uint8_t Condition; // Condition code encoded in low 4 bit of the opcode. + uint8_t Predicate; // Same as Condition, kept for backwards compatibility. + + uint8_t OperandsCount; // Number of operands. + uint8_t ExpOperandsCount; // Number of explicit operands. Use this if you want to ignore + // implicit operands such as stack, flags, etc. + uint16_t OperandsEncodingMap; // What parts of the instruction encode operands. + ND_OPERAND Operands[ND_MAX_OPERAND]; // Instruction operands. + + // As extracted from the operands themselves. + uint8_t RipAccess; // RIP access mode (read/write). + uint8_t StackAccess; // Stack access mode (push/pop). + uint8_t MemoryAccess; // Memory access mode (read/write, including stack or shadow stack). + + struct + { + uint8_t RegAccess; // RFLAGS access mode (read/write), as per the entire register. + ND_RFLAGS Tested; // Tested flags. + ND_RFLAGS Modified; // Modified (according to the result) flags. + ND_RFLAGS Set; // Flags that are always set to 1. + ND_RFLAGS Cleared; // Flags that are always cleared to 0. + ND_RFLAGS Undefined; // Undefined flags. + } FlagsAccess; + + ND_FPU_FLAGS FpuFlagsAccess; // FPU status word C0-C3 bits access. Valid only for FPU instructions! + + uint8_t ExceptionClass; // ND_EX_CLASS_TYPE, indicates the exception class type. + uint8_t ExceptionType; // Exception type. Depends on ExceptionClass. + uint8_t TupleType; // EVEX tuple type, if EVEX. Check out ND_TUPLE. + uint8_t RoundingMode; // EVEX rounding mode, if present. Check out ND_ROUNDING. + + // Stored inside the instruction entry as well. These are specific for an instruction and do not depend on + // encoding. Use the flags definitions (ND_FLAG_*, ND_PREF_*, ND_DECO_*, ND_EXOP_*) to access specific bits. + uint32_t Attributes; // Instruction attributes/flags. A collection of ND_FLAG_*. + union + { + ND_INS_CLASS Instruction; // One of the ND_INS_* + ND_INS_CLASS Iclass; // Same as Instruction. + }; + ND_INS_CATEGORY Category; // One of the ND_CAT_* + ND_INS_SET IsaSet; // One of the ND_SET_* + ND_CPUID_FLAG CpuidFlag; // CPUID support flag. + ND_VALID_MODES ValidModes; // Valid CPU modes for the instruction. + ND_VALID_PREFIXES ValidPrefixes; // Indicates which prefixes are valid for this instruction. + ND_VALID_DECORATORS ValidDecorators; // What decorators are accepted by the instruction. + uint64_t Reserved1; // Padding purpose. Aligns the mnemonic to 8 bytes. + char Mnemonic[ND_MAX_MNEMONIC_LENGTH]; // Instruction mnemonic. + uint8_t OpCodeBytes[3]; // Opcode bytes - escape codes and main op code + uint8_t PrimaryOpCode; // Main/nominal opcode + uint32_t Reserved2; // Padding purpose. Aligns the InstructionBytes to 16 bytes. + uint8_t InstructionBytes[16]; // The entire instruction. + +} INSTRUX, *PINSTRUX; + + +// +// API +// +void +NdGetVersion( + uint32_t *Major, + uint32_t *Minor, + uint32_t *Revision, + char **BuildDate, + char **BuildTime + ); + +NDSTATUS +NdDecode( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t DefCode, + uint8_t DefData + ); + +NDSTATUS +NdDecodeEx( + INSTRUX *Instrux, + const uint8_t *Code, + size_t Size, + uint8_t DefCode, + uint8_t DefData + ); + +NDSTATUS +NdDecodeEx2( + INSTRUX *Instrux, + const uint8_t *Code, + size_t Size, + uint8_t DefCode, + uint8_t DefData, + uint8_t DefStack, + uint8_t PreferedVendor + ); + +NDSTATUS +NdToText( + const INSTRUX *Instrux, + uint64_t Rip, + uint32_t BufferSize, + char *Buffer + ); + +bool +NdIsInstruxRipRelative( + const INSTRUX *Instrux + ); + +NDSTATUS +NdGetFullAccessMap( + const INSTRUX *Instrux, + ND_ACCESS_MAP *AccessMap + ); + + +// #pragma warning(default: 4214) // Bitfield in type other than int. +// #pragma warning(default: 4201) // Nonstandard extension used: nameless struct/union. +#ifdef _MSC_VER +#pragma warning(pop) +#endif + +#endif // _BDDISASM_H_ diff --git a/inc/bdshemu/bdshemu.h b/inc/bdshemu/bdshemu.h new file mode 100644 index 0000000..06677e7 --- /dev/null +++ b/inc/bdshemu/bdshemu.h @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2020 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _BDSHEMU_H_ +#define _BDSHEMU_H_ + + +#include "bddisasm.h" + + +// +// Print function. Used to log emulation traces. +// +typedef void +(*ShemuPrint)( + char *Data // Data to be printed. + ); + + +// +// Access memory function. Simply return true if the access was handled, or false if it wasn't. +// If the function is not provided in SHEMU_CONTEXT, or if it returns false, the emulation will be terminated. +// Note that the integrator is free to handle external memory access as it pleases. +// Loads could always yield the same value (0), a random value or they could return actual memory values. +// Stores could be discarded, or they could be buffered in a store-buffer like structure. +// Note that by using the ShemuContext, the integrator knows whether the access is user or supervisor (the Ring field +// inside ShemuContext), and he knows whether it is 16/32/64 bit mode (Mode field inside ShemuContext). +// +typedef bool +(*ShemuMemAccess)( + void *ShemuContext, // Shemu emulation context. + uint64_t Gla, // Linear address to be accessed. + size_t Size, // Number of bytes to access. + uint8_t *Buffer, // Contains the read content (if Store is false), or the value to be stored at Gla. + bool Store // If false, read content at Gla. Otherwise, write content at Gla. + ); + + +// Percent of emulated instructions that must be NOP to consider a NOP sled is present. +#define SHEMU_DEFAULT_NOP_THRESHOLD 75 +// Consecutive printable characters on stack to consider a stack string access. +#define SHEMU_DEFAULT_STR_THRESHOLD 8 +// Will not emulate more than this number of external memory accesses. Once this threshold is exceeded, any external +// access will abort the emulation. +#define SHEMU_DEFAULT_MEM_THRESHOLD 0 + + +// +// General purpose registers. +// +typedef struct _SHEMU_GPR_REGS +{ + uint64_t RegRax; + uint64_t RegRcx; + uint64_t RegRdx; + uint64_t RegRbx; + uint64_t RegRsp; + uint64_t RegRbp; + uint64_t RegRsi; + uint64_t RegRdi; + uint64_t RegR8; + uint64_t RegR9; + uint64_t RegR10; + uint64_t RegR11; + uint64_t RegR12; + uint64_t RegR13; + uint64_t RegR14; + uint64_t RegR15; + uint64_t RegCr2; + uint64_t RegFlags; + uint64_t RegDr7; + uint64_t RegRip; + uint64_t RegCr0; + uint64_t RegCr4; + uint64_t RegCr3; + uint64_t RegCr8; + uint64_t RegIdtBase; + uint64_t RegIdtLimit; + uint64_t RegGdtBase; + uint64_t RegGdtLimit; + + uint64_t FpuRip; +} SHEMU_GPR_REGS, *PSHEMU_GPR_REGS; + + +// +// Segment register (with its hidden part). +// +typedef struct _SHEMU_SEG +{ + uint64_t Base; + uint64_t Limit; + uint64_t Selector; + uint64_t AccessRights; +} SHEMU_SEG, *PSHEMU_SEG; + + +// +// The segment registers. +// +typedef struct _SHEMU_SEG_REGS +{ + SHEMU_SEG Es; + SHEMU_SEG Cs; + SHEMU_SEG Ss; + SHEMU_SEG Ds; + SHEMU_SEG Fs; + SHEMU_SEG Gs; +} SHEMU_SEG_REGS, *PSHEMU_SEG_REGS; + + +// +// Emulation context. All of these fields must be provided as input, although most of them can be 0. +// +typedef struct _SHEMU_CONTEXT +{ + // Current instruction. Doesn't have to be provided; it always contains the currently emulated instruction. + // When #ShemuEmulate returns, this will contain the last emulated instruction. In case of an emulation failure, + // it can be inspected, to gather more info about what went wrong. + INSTRUX Instruction; + + // General purpose registers state. On input, the initial state. Will be updated after each emulated instruction. + SHEMU_GPR_REGS Registers; + + // Segment registers state. On input, the initial state. May be updated after some instructions. + SHEMU_SEG_REGS Segments; + + // MMX register state. 8 x 8 bytes = 64 bytes for the MMX registers. Can be provided on input, if needed. + uint64_t MmxRegisters[ND_MAX_MMX_REGS]; + + // SSE registers state. 32 x 64 bytes = 2048 bytes for the SSE registers. Can be provided on input, if needed. + uint8_t SseRegisters[ND_MAX_SSE_REGS * ND_MAX_REGISTER_SIZE]; + + // Operating mode (ND_CODE_16, ND_CODE_32 or ND_CODE_64). Must be provided as input. + uint8_t Mode; + + // Operating ring (0, 1, 2, 3). Must be provided as input. + uint8_t Ring; + + // The suspicious code to be emulated. Must be provided as input. + uint8_t *Shellcode; + + // Virtual stack. RSP will point somewhere inside. Must be allocated as input, and it can be initialized with + // actual stack contents. Can also be 0-filled. + uint8_t *Stack; + + // Internal use. Must be at least the size of the shell + stack. Needs not be initialized, but must be allocated + // and accessible on input. + uint8_t *Intbuf; + + // Shellcode base address (the address the shellcode would see). Must be provided as input. + uint64_t ShellcodeBase; + + // Stack base address (the RSP the shellcode would see). Must be provided as input. + uint64_t StackBase; + + // Shellcode size. Must be provided as input. Usually just a page in size, but can be larger. + uint32_t ShellcodeSize; + + // Stack size. Must be provided as input. Minimum two pages. + uint32_t StackSize; + + // Internal buffer size. Must be provided as input. Must be at least the size of the shell + stack. + uint32_t IntbufSize; + + // Number of NOPs encountered. Should be 0 on input. + uint32_t NopCount; + + // The length of the string constructed on the stack, if any. Should be 0 on input. + uint32_t StrLength; + + // Number of external memory access (outside stack/shellcode). Should be 0 on input. + uint32_t ExtMemAccess; + + // Number of emulated instructions. Should be 0 on input. Once InstructionsCount reaches MaxInstructionsCount, + // emulation will stop. + uint32_t InstructionsCount; + + // Max number of instructions that should be emulated. Once this limit has been reached, emulation will stop. + // Lower values will mean faster processing, but less chances of detection. Higher values mean low performance, + // but very high chances of yielding useful results. Must be provided as input. + uint32_t MaxInstructionsCount; + + // Base address of the Thread Information Block (the TIB the shellcode would normally see). Must be provided as + // input. + uint64_t TibBase; + + // Shellcode Flags (see SHEMU_FLAG_*). Must be provided as input. + uint64_t Flags; + + // Emulation options. See SHEMU_OPT_* for possible options. Must be provided as input. + uint32_t Options; + + // Percent of NOPs (out of total instructions emulated) that trigger NOP sled detection. Must be provided as input. + uint32_t NopThreshold; + + // Stack string length threshold. Stack-constructed strings must be at least this long to trigger stack string + // detection. Must be provided as input. + uint32_t StrThreshold; + + // Number of external mem accesses threshold. No more than this number of external accesses will be issued. Must + // be provided as input. + uint32_t MemThreshold; + + // Optional auxiliary data, provided by the integrator. Can be NULL, or can point to integrator specific data. + // Shemu will not use this data in any way, but callbacks that receive a SHEMU_CONTEXT pointer (such as + // #AccessMemory) can use it to reference integrator private information. + void *AuxData; + + // If provided, will be used for tracing. Can be NULL. + ShemuPrint Log; + + // If provided, will try to access additional memory. Can be NULL. + ShemuMemAccess AccessMemory; + +} SHEMU_CONTEXT, *PSHEMU_CONTEXT; + + +typedef unsigned int SHEMU_STATUS; + + +// +// Emulation abort reasons. +// +#define SHEMU_SUCCESS 0 // Successfully emulated up to MaxInstructions. +#define SHEMU_ABORT_GLA_OUTSIDE 1 // Address accessed outside the shellcode or stack page. +#define SHEMU_ABORT_BRANCH_OUTSIDE 2 // A branch outside the shellcode page. +#define SHEMU_ABORT_UNSUPPORTED_INSTRUX 3 // A valid but unsupported instruction was encountered. +#define SHEMU_ABORT_INVALID_INSTRUX 4 // An invalid instruction was encountered. +#define SHEMU_ABORT_ADDRESSING_UNSUPPORTED 5 // An unsupported addressing scheme used (ie, VSIB). +#define SHEMU_ABORT_REGISTER_NOT_SUPPORTED 6 // An unsupported register was used (ie, DR). +#define SHEMU_ABORT_INVALID_PARAMETER 7 // An invalid parameter was supplied. +#define SHEMU_ABORT_OP_TOO_LARGE 8 // An operand that is too large was encountered. +#define SHEMU_ABORT_NO_PRIVILEGE 9 // A privileged instruction outside kernel mode. +#define SHEMU_ABORT_CANT_EMULATE 10 // A valid, but only partially handled instruction. +#define SHEMU_ABORT_SHELLCODE_DETECTED 0xFFFFFFFF // Shellcode criteria met (see the shellcode flags). + + +// +// Shellcode flags. +// +// General and user-mode flags. +#define SHEMU_FLAG_NOP_SLED 0x00000001 // Long sequence of NOP instructions. +#define SHEMU_FLAG_LOAD_RIP 0x00000002 // The code loads RIP (CALL/POP, FNSTENV/POP, etc.) +#define SHEMU_FLAG_WRITE_SELF 0x00000004 // The code writes itself (decryption, unpacking, etc.) +#define SHEMU_FLAG_TIB_ACCESS 0x00000008 // The code accesses the TIB. +#define SHEMU_FLAG_SYSCALL 0x00000010 // The code does a direct syscall/sysenter. +#define SHEMU_FLAG_STACK_STR 0x00000020 // The code constructs & uses strings on the stack. +// Kernel specific flags. +#define SHEMU_FLAG_KPCR_ACCESS 0x00010000 // KPCR current thread access via gs:[0x188]/fs:[0x124]. +#define SHEMU_FLAG_SWAPGS 0x00020000 // SWAPGS was executed. +#define SHEMU_FLAG_SYSCALL_MSR_READ 0x00040000 // A SYSCALL/SYSENTER MSR read. +#define SHEMU_FLAG_SYSCALL_MSR_WRITE 0x00080000 // A SYSCALL/SYSENTER MSR write. + + +// +// Emulation options. +// +#define SHEMU_OPT_TRACE_EMULATION 0x00000001 // Trace each emulated instruction. +#define SHEMU_OPT_STOP_ON_EXPLOIT 0x00000002 // When shellcode indications are confirmed, stop emulation. + + +// +// At least this amount must be allocated for internal use. +// +#define SHEMU_INTERNAL_BUFFER_SIZE(ctx) ((ctx)->ShellcodeSize + (ctx)->StackSize) + + +// +// API +// +SHEMU_STATUS +ShemuEmulate( + SHEMU_CONTEXT *Context + ); + + +#endif // !_BDSHEMU_H_ diff --git a/inc/constants.h b/inc/constants.h new file mode 100644 index 0000000..154e1c2 --- /dev/null +++ b/inc/constants.h @@ -0,0 +1,1687 @@ +// +// This file was auto-generated by generate_tables.py from defs.dat. DO NOT MODIFY! +// + +#ifndef _CONSTANTS_H_ +#define _CONSTANTS_H_ + + +typedef enum _ND_INS_CLASS +{ + ND_INS_INVALID = 0, + ND_INS_AAA, + ND_INS_AAD, + ND_INS_AAM, + ND_INS_AAS, + ND_INS_ADC, + ND_INS_ADCX, + ND_INS_ADD, + ND_INS_ADDPD, + ND_INS_ADDPS, + ND_INS_ADDSD, + ND_INS_ADDSS, + ND_INS_ADDSUBPD, + ND_INS_ADDSUBPS, + ND_INS_ADOX, + ND_INS_AESDEC, + ND_INS_AESDECLAST, + ND_INS_AESENC, + ND_INS_AESENCLAST, + ND_INS_AESIMC, + ND_INS_AESKEYGENASSIST, + ND_INS_ALTINST, + ND_INS_AND, + ND_INS_ANDN, + ND_INS_ANDNPD, + ND_INS_ANDNPS, + ND_INS_ANDPD, + ND_INS_ANDPS, + ND_INS_ARPL, + ND_INS_BEXTR, + ND_INS_BLCFILL, + ND_INS_BLCI, + ND_INS_BLCIC, + ND_INS_BLCMSK, + ND_INS_BLCS, + ND_INS_BLENDPD, + ND_INS_BLENDPS, + ND_INS_BLENDVPD, + ND_INS_BLENDVPS, + ND_INS_BLSFILL, + ND_INS_BLSI, + ND_INS_BLSIC, + ND_INS_BLSMSK, + ND_INS_BLSR, + ND_INS_BNDCL, + ND_INS_BNDCN, + ND_INS_BNDCU, + ND_INS_BNDLDX, + ND_INS_BNDMK, + ND_INS_BNDMOV, + ND_INS_BNDSTX, + ND_INS_BOUND, + ND_INS_BSF, + ND_INS_BSR, + ND_INS_BSWAP, + ND_INS_BT, + ND_INS_BTC, + ND_INS_BTR, + ND_INS_BTS, + ND_INS_BZHI, + ND_INS_CALLFD, + ND_INS_CALLFI, + ND_INS_CALLNI, + ND_INS_CALLNR, + ND_INS_CBW, + ND_INS_CDQ, + ND_INS_CDQE, + ND_INS_CL1INVMB, + ND_INS_CLAC, + ND_INS_CLC, + ND_INS_CLD, + ND_INS_CLDEMOTE, + ND_INS_CLEVICT0, + ND_INS_CLEVICT1, + ND_INS_CLFLUSH, + ND_INS_CLFLUSHOPT, + ND_INS_CLGI, + ND_INS_CLI, + ND_INS_CLRSSBSY, + ND_INS_CLTS, + ND_INS_CLWB, + ND_INS_CLZERO, + ND_INS_CMC, + ND_INS_CMOVcc, + ND_INS_CMP, + ND_INS_CMPPD, + ND_INS_CMPPS, + ND_INS_CMPS, + ND_INS_CMPSD, + ND_INS_CMPSS, + ND_INS_CMPXCHG, + ND_INS_CMPXCHG16B, + ND_INS_CMPXCHG8B, + ND_INS_COMISD, + ND_INS_COMISS, + ND_INS_CPUID, + ND_INS_CPU_READ, + ND_INS_CPU_WRITE, + ND_INS_CQO, + ND_INS_CRC32, + ND_INS_CVTDQ2PD, + ND_INS_CVTDQ2PS, + ND_INS_CVTPD2DQ, + ND_INS_CVTPD2PI, + ND_INS_CVTPD2PS, + ND_INS_CVTPI2PD, + ND_INS_CVTPI2PS, + ND_INS_CVTPS2DQ, + ND_INS_CVTPS2PD, + ND_INS_CVTPS2PI, + ND_INS_CVTSD2SI, + ND_INS_CVTSD2SS, + ND_INS_CVTSI2SD, + ND_INS_CVTSI2SS, + ND_INS_CVTSS2SD, + ND_INS_CVTSS2SI, + ND_INS_CVTTPD2DQ, + ND_INS_CVTTPD2PI, + ND_INS_CVTTPS2DQ, + ND_INS_CVTTPS2PI, + ND_INS_CVTTSD2SI, + ND_INS_CVTTSS2SI, + ND_INS_CWD, + ND_INS_CWDE, + ND_INS_DAA, + ND_INS_DAS, + ND_INS_DEC, + ND_INS_DELAY, + ND_INS_DIV, + ND_INS_DIVPD, + ND_INS_DIVPS, + ND_INS_DIVSD, + ND_INS_DIVSS, + ND_INS_DMINT, + ND_INS_DPPD, + ND_INS_DPPS, + ND_INS_EMMS, + ND_INS_ENCLS, + ND_INS_ENCLU, + ND_INS_ENCLV, + ND_INS_ENDBR, + ND_INS_ENQCMD, + ND_INS_ENQCMDS, + ND_INS_ENTER, + ND_INS_EXTRACTPS, + ND_INS_EXTRQ, + ND_INS_F2XM1, + ND_INS_FABS, + ND_INS_FADD, + ND_INS_FADDP, + ND_INS_FBLD, + ND_INS_FBSTP, + ND_INS_FCHS, + ND_INS_FCMOVB, + ND_INS_FCMOVBE, + ND_INS_FCMOVE, + ND_INS_FCMOVNB, + ND_INS_FCMOVNBE, + ND_INS_FCMOVNE, + ND_INS_FCMOVNU, + ND_INS_FCMOVU, + ND_INS_FCOM, + ND_INS_FCOMI, + ND_INS_FCOMIP, + ND_INS_FCOMP, + ND_INS_FCOMPP, + ND_INS_FCOS, + ND_INS_FDECSTP, + ND_INS_FDIV, + ND_INS_FDIVP, + ND_INS_FDIVR, + ND_INS_FDIVRP, + ND_INS_FEMMS, + ND_INS_FFREE, + ND_INS_FFREEP, + ND_INS_FIADD, + ND_INS_FICOM, + ND_INS_FICOMP, + ND_INS_FIDIV, + ND_INS_FIDIVR, + ND_INS_FILD, + ND_INS_FIMUL, + ND_INS_FINCSTP, + ND_INS_FIST, + ND_INS_FISTP, + ND_INS_FISTTP, + ND_INS_FISUB, + ND_INS_FISUBR, + ND_INS_FLD, + ND_INS_FLD1, + ND_INS_FLDCW, + ND_INS_FLDENV, + ND_INS_FLDL2E, + ND_INS_FLDL2T, + ND_INS_FLDLG2, + ND_INS_FLDLN2, + ND_INS_FLDPI, + ND_INS_FLDZ, + ND_INS_FMUL, + ND_INS_FMULP, + ND_INS_FNCLEX, + ND_INS_FNDISI, + ND_INS_FNINIT, + ND_INS_FNOP, + ND_INS_FNSAVE, + ND_INS_FNSTCW, + ND_INS_FNSTENV, + ND_INS_FNSTSW, + ND_INS_FPATAN, + ND_INS_FPREM, + ND_INS_FPREM1, + ND_INS_FPTAN, + ND_INS_FRINEAR, + ND_INS_FRNDINT, + ND_INS_FRSTOR, + ND_INS_FSCALE, + ND_INS_FSIN, + ND_INS_FSINCOS, + ND_INS_FSQRT, + ND_INS_FST, + ND_INS_FSTDW, + ND_INS_FSTP, + ND_INS_FSTPNCE, + ND_INS_FSTSG, + ND_INS_FSUB, + ND_INS_FSUBP, + ND_INS_FSUBR, + ND_INS_FSUBRP, + ND_INS_FTST, + ND_INS_FUCOM, + ND_INS_FUCOMI, + ND_INS_FUCOMIP, + ND_INS_FUCOMP, + ND_INS_FUCOMPP, + ND_INS_FXAM, + ND_INS_FXCH, + ND_INS_FXRSTOR, + ND_INS_FXSAVE, + ND_INS_FXTRACT, + ND_INS_FYL2X, + ND_INS_FYL2XP1, + ND_INS_GETSEC, + ND_INS_GF2P8AFFINEINVQB, + ND_INS_GF2P8AFFINEQB, + ND_INS_GF2P8MULB, + ND_INS_HADDPD, + ND_INS_HADDPS, + ND_INS_HLT, + ND_INS_HSUBPD, + ND_INS_HSUBPS, + ND_INS_IDIV, + ND_INS_IMUL, + ND_INS_IN, + ND_INS_INC, + ND_INS_INCSSP, + ND_INS_INS, + ND_INS_INSERTPS, + ND_INS_INSERTQ, + ND_INS_INT, + ND_INS_INT1, + ND_INS_INT3, + ND_INS_INTO, + ND_INS_INVD, + ND_INS_INVEPT, + ND_INS_INVLPG, + ND_INS_INVLPGA, + ND_INS_INVLPGB, + ND_INS_INVPCID, + ND_INS_INVVPID, + ND_INS_IRET, + ND_INS_JMPE, + ND_INS_JMPFD, + ND_INS_JMPFI, + ND_INS_JMPNI, + ND_INS_JMPNR, + ND_INS_Jcc, + ND_INS_JrCXZ, + ND_INS_KADD, + ND_INS_KAND, + ND_INS_KANDN, + ND_INS_KMERGE2L1H, + ND_INS_KMERGE2L1L, + ND_INS_KMOV, + ND_INS_KNOT, + ND_INS_KOR, + ND_INS_KORTEST, + ND_INS_KSHIFTL, + ND_INS_KSHIFTR, + ND_INS_KTEST, + ND_INS_KUNPCKBW, + ND_INS_KUNPCKDQ, + ND_INS_KUNPCKWD, + ND_INS_KXNOR, + ND_INS_KXOR, + ND_INS_LAHF, + ND_INS_LAR, + ND_INS_LDDQU, + ND_INS_LDMXCSR, + ND_INS_LDS, + ND_INS_LDTILECFG, + ND_INS_LEA, + ND_INS_LEAVE, + ND_INS_LES, + ND_INS_LFENCE, + ND_INS_LFS, + ND_INS_LGDT, + ND_INS_LGS, + ND_INS_LIDT, + ND_INS_LLDT, + ND_INS_LLWPCB, + ND_INS_LMSW, + ND_INS_LOADALL, + ND_INS_LOADALLD, + ND_INS_LODS, + ND_INS_LOOP, + ND_INS_LOOPNZ, + ND_INS_LOOPZ, + ND_INS_LSL, + ND_INS_LSS, + ND_INS_LTR, + ND_INS_LWPINS, + ND_INS_LWPVAL, + ND_INS_LZCNT, + ND_INS_MASKMOVDQU, + ND_INS_MASKMOVQ, + ND_INS_MAXPD, + ND_INS_MAXPS, + ND_INS_MAXSD, + ND_INS_MAXSS, + ND_INS_MCOMMIT, + ND_INS_MFENCE, + ND_INS_MINPD, + ND_INS_MINPS, + ND_INS_MINSD, + ND_INS_MINSS, + ND_INS_MONITOR, + ND_INS_MONITORX, + ND_INS_MONTMUL, + ND_INS_MOV, + ND_INS_MOVAPD, + ND_INS_MOVAPS, + ND_INS_MOVBE, + ND_INS_MOVD, + ND_INS_MOVDDUP, + ND_INS_MOVDIR64B, + ND_INS_MOVDIRI, + ND_INS_MOVDQ2Q, + ND_INS_MOVDQA, + ND_INS_MOVDQU, + ND_INS_MOVHPD, + ND_INS_MOVHPS, + ND_INS_MOVLHPS, + ND_INS_MOVLPD, + ND_INS_MOVLPS, + ND_INS_MOVMSKPD, + ND_INS_MOVMSKPS, + ND_INS_MOVNTDQ, + ND_INS_MOVNTDQA, + ND_INS_MOVNTI, + ND_INS_MOVNTPD, + ND_INS_MOVNTPS, + ND_INS_MOVNTQ, + ND_INS_MOVNTSD, + ND_INS_MOVNTSS, + ND_INS_MOVQ, + ND_INS_MOVQ2DQ, + ND_INS_MOVS, + ND_INS_MOVSD, + ND_INS_MOVSHDUP, + ND_INS_MOVSLDUP, + ND_INS_MOVSS, + ND_INS_MOVSX, + ND_INS_MOVSXD, + ND_INS_MOVUPD, + ND_INS_MOVUPS, + ND_INS_MOVZX, + ND_INS_MOV_CR, + ND_INS_MOV_DR, + ND_INS_MOV_TR, + ND_INS_MPSADBW, + ND_INS_MUL, + ND_INS_MULPD, + ND_INS_MULPS, + ND_INS_MULSD, + ND_INS_MULSS, + ND_INS_MULX, + ND_INS_MWAIT, + ND_INS_MWAITX, + ND_INS_NEG, + ND_INS_NOP, + ND_INS_NOT, + ND_INS_OR, + ND_INS_ORPD, + ND_INS_ORPS, + ND_INS_OUT, + ND_INS_OUTS, + ND_INS_PABSB, + ND_INS_PABSD, + ND_INS_PABSW, + ND_INS_PACKSSDW, + ND_INS_PACKSSWB, + ND_INS_PACKUSDW, + ND_INS_PACKUSWB, + ND_INS_PADDB, + ND_INS_PADDD, + ND_INS_PADDQ, + ND_INS_PADDSB, + ND_INS_PADDSW, + ND_INS_PADDUSB, + ND_INS_PADDUSW, + ND_INS_PADDW, + ND_INS_PALIGNR, + ND_INS_PAND, + ND_INS_PANDN, + ND_INS_PAUSE, + ND_INS_PAVGB, + ND_INS_PAVGUSB, + ND_INS_PAVGW, + ND_INS_PBLENDVB, + ND_INS_PBLENDW, + ND_INS_PCLMULQDQ, + ND_INS_PCMPEQB, + ND_INS_PCMPEQD, + ND_INS_PCMPEQQ, + ND_INS_PCMPEQW, + ND_INS_PCMPESTRI, + ND_INS_PCMPESTRM, + ND_INS_PCMPGTB, + ND_INS_PCMPGTD, + ND_INS_PCMPGTQ, + ND_INS_PCMPGTW, + ND_INS_PCMPISTRI, + ND_INS_PCMPISTRM, + ND_INS_PCOMMIT, + ND_INS_PCONFIG, + ND_INS_PDEP, + ND_INS_PEXT, + ND_INS_PEXTRB, + ND_INS_PEXTRD, + ND_INS_PEXTRQ, + ND_INS_PEXTRW, + ND_INS_PF2ID, + ND_INS_PF2IW, + ND_INS_PFACC, + ND_INS_PFADD, + ND_INS_PFCMPEQ, + ND_INS_PFCMPGE, + ND_INS_PFCMPGT, + ND_INS_PFMAX, + ND_INS_PFMIN, + ND_INS_PFMUL, + ND_INS_PFNACC, + ND_INS_PFPNACC, + ND_INS_PFRCPIT1, + ND_INS_PFRCPIT2, + ND_INS_PFRCPV, + ND_INS_PFRSQIT1, + ND_INS_PFRSQRT, + ND_INS_PFRSQRTV, + ND_INS_PFSUB, + ND_INS_PFSUBR, + ND_INS_PHADDD, + ND_INS_PHADDSW, + ND_INS_PHADDW, + ND_INS_PHMINPOSUW, + ND_INS_PHSUBD, + ND_INS_PHSUBSW, + ND_INS_PHSUBW, + ND_INS_PI2FD, + ND_INS_PI2FW, + ND_INS_PINSRB, + ND_INS_PINSRD, + ND_INS_PINSRQ, + ND_INS_PINSRW, + ND_INS_PMADDUBSW, + ND_INS_PMADDWD, + ND_INS_PMAXSB, + ND_INS_PMAXSD, + ND_INS_PMAXSW, + ND_INS_PMAXUB, + ND_INS_PMAXUD, + ND_INS_PMAXUW, + ND_INS_PMINSB, + ND_INS_PMINSD, + ND_INS_PMINSW, + ND_INS_PMINUB, + ND_INS_PMINUD, + ND_INS_PMINUW, + ND_INS_PMOVMSKB, + ND_INS_PMOVSXBD, + ND_INS_PMOVSXBQ, + ND_INS_PMOVSXBW, + ND_INS_PMOVSXDQ, + ND_INS_PMOVSXWD, + ND_INS_PMOVSXWQ, + ND_INS_PMOVZXBD, + ND_INS_PMOVZXBQ, + ND_INS_PMOVZXBW, + ND_INS_PMOVZXDQ, + ND_INS_PMOVZXWD, + ND_INS_PMOVZXWQ, + ND_INS_PMULDQ, + ND_INS_PMULHRSW, + ND_INS_PMULHRW, + ND_INS_PMULHUW, + ND_INS_PMULHW, + ND_INS_PMULLD, + ND_INS_PMULLW, + ND_INS_PMULUDQ, + ND_INS_POP, + ND_INS_POPA, + ND_INS_POPCNT, + ND_INS_POPF, + ND_INS_POR, + ND_INS_PREFETCH, + ND_INS_PREFETCHE, + ND_INS_PREFETCHM, + ND_INS_PREFETCHNTA, + ND_INS_PREFETCHT0, + ND_INS_PREFETCHT1, + ND_INS_PREFETCHT2, + ND_INS_PREFETCHW, + ND_INS_PREFETCHWT1, + ND_INS_PSADBW, + ND_INS_PSHUFB, + ND_INS_PSHUFD, + ND_INS_PSHUFHW, + ND_INS_PSHUFLW, + ND_INS_PSHUFW, + ND_INS_PSIGNB, + ND_INS_PSIGND, + ND_INS_PSIGNW, + ND_INS_PSLLD, + ND_INS_PSLLDQ, + ND_INS_PSLLQ, + ND_INS_PSLLW, + ND_INS_PSMASH, + ND_INS_PSRAD, + ND_INS_PSRAW, + ND_INS_PSRLD, + ND_INS_PSRLDQ, + ND_INS_PSRLQ, + ND_INS_PSRLW, + ND_INS_PSUBB, + ND_INS_PSUBD, + ND_INS_PSUBQ, + ND_INS_PSUBSB, + ND_INS_PSUBSW, + ND_INS_PSUBUSB, + ND_INS_PSUBUSW, + ND_INS_PSUBW, + ND_INS_PSWAPD, + ND_INS_PTEST, + ND_INS_PTWRITE, + ND_INS_PUNPCKHBW, + ND_INS_PUNPCKHDQ, + ND_INS_PUNPCKHQDQ, + ND_INS_PUNPCKHWD, + ND_INS_PUNPCKLBW, + ND_INS_PUNPCKLDQ, + ND_INS_PUNPCKLQDQ, + ND_INS_PUNPCKLWD, + ND_INS_PUSH, + ND_INS_PUSHA, + ND_INS_PUSHF, + ND_INS_PVALIDATE, + ND_INS_PXOR, + ND_INS_RCL, + ND_INS_RCPPS, + ND_INS_RCPSS, + ND_INS_RCR, + ND_INS_RDFSBASE, + ND_INS_RDGSBASE, + ND_INS_RDMSR, + ND_INS_RDPID, + ND_INS_RDPKRU, + ND_INS_RDPMC, + ND_INS_RDPRU, + ND_INS_RDRAND, + ND_INS_RDSEED, + ND_INS_RDSHR, + ND_INS_RDTSC, + ND_INS_RDTSCP, + ND_INS_RETF, + ND_INS_RETN, + ND_INS_RMPADJUST, + ND_INS_RMPUPDATE, + ND_INS_ROL, + ND_INS_ROR, + ND_INS_RORX, + ND_INS_ROUNDPD, + ND_INS_ROUNDPS, + ND_INS_ROUNDSD, + ND_INS_ROUNDSS, + ND_INS_RSDC, + ND_INS_RSLDT, + ND_INS_RSM, + ND_INS_RSQRTPS, + ND_INS_RSQRTSS, + ND_INS_RSSSP, + ND_INS_RSTORSSP, + ND_INS_RSTS, + ND_INS_SAHF, + ND_INS_SAL, + ND_INS_SALC, + ND_INS_SAR, + ND_INS_SARX, + ND_INS_SAVEPREVSSP, + ND_INS_SBB, + ND_INS_SCAS, + ND_INS_SERIALIZE, + ND_INS_SETSSBSY, + ND_INS_SETcc, + ND_INS_SFENCE, + ND_INS_SGDT, + ND_INS_SHA1MSG1, + ND_INS_SHA1MSG2, + ND_INS_SHA1NEXTE, + ND_INS_SHA1RNDS4, + ND_INS_SHA256MSG1, + ND_INS_SHA256MSG2, + ND_INS_SHA256RNDS2, + ND_INS_SHL, + ND_INS_SHLD, + ND_INS_SHLX, + ND_INS_SHR, + ND_INS_SHRD, + ND_INS_SHRX, + ND_INS_SHUFPD, + ND_INS_SHUFPS, + ND_INS_SIDT, + ND_INS_SKINIT, + ND_INS_SLDT, + ND_INS_SLWPCB, + ND_INS_SMINT, + ND_INS_SMSW, + ND_INS_SPFLT, + ND_INS_SQRTPD, + ND_INS_SQRTPS, + ND_INS_SQRTSD, + ND_INS_SQRTSS, + ND_INS_STAC, + ND_INS_STC, + ND_INS_STD, + ND_INS_STGI, + ND_INS_STI, + ND_INS_STMXCSR, + ND_INS_STOS, + ND_INS_STR, + ND_INS_STTILECFG, + ND_INS_SUB, + ND_INS_SUBPD, + ND_INS_SUBPS, + ND_INS_SUBSD, + ND_INS_SUBSS, + ND_INS_SVDC, + ND_INS_SVLDT, + ND_INS_SVTS, + ND_INS_SWAPGS, + ND_INS_SYSCALL, + ND_INS_SYSENTER, + ND_INS_SYSEXIT, + ND_INS_SYSRET, + ND_INS_T1MSKC, + ND_INS_TDPBF16PS, + ND_INS_TDPBSSD, + ND_INS_TDPBSUD, + ND_INS_TDPBUSD, + ND_INS_TDPBUUD, + ND_INS_TEST, + ND_INS_TILELOADD, + ND_INS_TILELOADDT1, + ND_INS_TILERELEASE, + ND_INS_TILESTORED, + ND_INS_TILEZERO, + ND_INS_TLBSYNC, + ND_INS_TPAUSE, + ND_INS_TZCNT, + ND_INS_TZMSK, + ND_INS_UCOMISD, + ND_INS_UCOMISS, + ND_INS_UD0, + ND_INS_UD1, + ND_INS_UD2, + ND_INS_UMONITOR, + ND_INS_UMWAIT, + ND_INS_UNPCKHPD, + ND_INS_UNPCKHPS, + ND_INS_UNPCKLPD, + ND_INS_UNPCKLPS, + ND_INS_V4FMADDPS, + ND_INS_V4FMADDSS, + ND_INS_V4FNMADDPS, + ND_INS_V4FNMADDSS, + ND_INS_VADDPD, + ND_INS_VADDPS, + ND_INS_VADDSD, + ND_INS_VADDSS, + ND_INS_VADDSUBPD, + ND_INS_VADDSUBPS, + ND_INS_VAESDEC, + ND_INS_VAESDECLAST, + ND_INS_VAESENC, + ND_INS_VAESENCLAST, + ND_INS_VAESIMC, + ND_INS_VAESKEYGENASSIST, + ND_INS_VALIGND, + ND_INS_VALIGNQ, + ND_INS_VANDNPD, + ND_INS_VANDNPS, + ND_INS_VANDPD, + ND_INS_VANDPS, + ND_INS_VBLENDMPD, + ND_INS_VBLENDMPS, + ND_INS_VBLENDPD, + ND_INS_VBLENDPS, + ND_INS_VBLENDVPD, + ND_INS_VBLENDVPS, + ND_INS_VBROADCASTF128, + ND_INS_VBROADCASTF32X2, + ND_INS_VBROADCASTF32X4, + ND_INS_VBROADCASTF32X8, + ND_INS_VBROADCASTF64X2, + ND_INS_VBROADCASTF64X4, + ND_INS_VBROADCASTI128, + ND_INS_VBROADCASTI32X2, + ND_INS_VBROADCASTI32X4, + ND_INS_VBROADCASTI32X8, + ND_INS_VBROADCASTI64X2, + ND_INS_VBROADCASTI64X4, + ND_INS_VBROADCASTSD, + ND_INS_VBROADCASTSS, + ND_INS_VCMPPD, + ND_INS_VCMPPS, + ND_INS_VCMPSD, + ND_INS_VCMPSS, + ND_INS_VCOMISD, + ND_INS_VCOMISS, + ND_INS_VCOMPRESSPD, + ND_INS_VCOMPRESSPS, + ND_INS_VCVTDQ2PD, + ND_INS_VCVTDQ2PS, + ND_INS_VCVTNE2PS2BF16, + ND_INS_VCVTNEPS2BF16, + ND_INS_VCVTPD2DQ, + ND_INS_VCVTPD2PS, + ND_INS_VCVTPD2QQ, + ND_INS_VCVTPD2UDQ, + ND_INS_VCVTPD2UQQ, + ND_INS_VCVTPH2PS, + ND_INS_VCVTPS2DQ, + ND_INS_VCVTPS2PD, + ND_INS_VCVTPS2PH, + ND_INS_VCVTPS2QQ, + ND_INS_VCVTPS2UDQ, + ND_INS_VCVTPS2UQQ, + ND_INS_VCVTQQ2PD, + ND_INS_VCVTQQ2PS, + ND_INS_VCVTSD2SI, + ND_INS_VCVTSD2SS, + ND_INS_VCVTSD2USI, + ND_INS_VCVTSI2SD, + ND_INS_VCVTSI2SS, + ND_INS_VCVTSS2SD, + ND_INS_VCVTSS2SI, + ND_INS_VCVTSS2USI, + ND_INS_VCVTTPD2DQ, + ND_INS_VCVTTPD2QQ, + ND_INS_VCVTTPD2UDQ, + ND_INS_VCVTTPD2UQQ, + ND_INS_VCVTTPS2DQ, + ND_INS_VCVTTPS2QQ, + ND_INS_VCVTTPS2UDQ, + ND_INS_VCVTTPS2UQQ, + ND_INS_VCVTTSD2SI, + ND_INS_VCVTTSD2USI, + ND_INS_VCVTTSS2SI, + ND_INS_VCVTTSS2USI, + ND_INS_VCVTUDQ2PD, + ND_INS_VCVTUDQ2PS, + ND_INS_VCVTUQQ2PD, + ND_INS_VCVTUQQ2PS, + ND_INS_VCVTUSI2SD, + ND_INS_VCVTUSI2SS, + ND_INS_VDBPSADBW, + ND_INS_VDIVPD, + ND_INS_VDIVPS, + ND_INS_VDIVSD, + ND_INS_VDIVSS, + ND_INS_VDPBF16PS, + ND_INS_VDPPD, + ND_INS_VDPPS, + ND_INS_VERR, + ND_INS_VERW, + ND_INS_VEXP2PD, + ND_INS_VEXP2PS, + ND_INS_VEXPANDPD, + ND_INS_VEXPANDPS, + ND_INS_VEXTRACTF128, + ND_INS_VEXTRACTF32X4, + ND_INS_VEXTRACTF32X8, + ND_INS_VEXTRACTF64X2, + ND_INS_VEXTRACTF64X4, + ND_INS_VEXTRACTI128, + ND_INS_VEXTRACTI32X4, + ND_INS_VEXTRACTI32X8, + ND_INS_VEXTRACTI64X2, + ND_INS_VEXTRACTI64X4, + ND_INS_VEXTRACTPS, + ND_INS_VFIXUPIMMPD, + ND_INS_VFIXUPIMMPS, + ND_INS_VFIXUPIMMSD, + ND_INS_VFIXUPIMMSS, + ND_INS_VFMADD132PD, + ND_INS_VFMADD132PS, + ND_INS_VFMADD132SD, + ND_INS_VFMADD132SS, + ND_INS_VFMADD213PD, + ND_INS_VFMADD213PS, + ND_INS_VFMADD213SD, + ND_INS_VFMADD213SS, + ND_INS_VFMADD231PD, + ND_INS_VFMADD231PS, + ND_INS_VFMADD231SD, + ND_INS_VFMADD231SS, + ND_INS_VFMADDPD, + ND_INS_VFMADDPS, + ND_INS_VFMADDSD, + ND_INS_VFMADDSS, + ND_INS_VFMADDSUB132PD, + ND_INS_VFMADDSUB132PS, + ND_INS_VFMADDSUB213PD, + ND_INS_VFMADDSUB213PS, + ND_INS_VFMADDSUB231PD, + ND_INS_VFMADDSUB231PS, + ND_INS_VFMADDSUBPD, + ND_INS_VFMADDSUBPS, + ND_INS_VFMSUB132PD, + ND_INS_VFMSUB132PS, + ND_INS_VFMSUB132SD, + ND_INS_VFMSUB132SS, + ND_INS_VFMSUB213PD, + ND_INS_VFMSUB213PS, + ND_INS_VFMSUB213SD, + ND_INS_VFMSUB213SS, + ND_INS_VFMSUB231PD, + ND_INS_VFMSUB231PS, + ND_INS_VFMSUB231SD, + ND_INS_VFMSUB231SS, + ND_INS_VFMSUBADD132PD, + ND_INS_VFMSUBADD132PS, + ND_INS_VFMSUBADD213PD, + ND_INS_VFMSUBADD213PS, + ND_INS_VFMSUBADD231PD, + ND_INS_VFMSUBADD231PS, + ND_INS_VFMSUBADDPD, + ND_INS_VFMSUBADDPS, + ND_INS_VFMSUBPD, + ND_INS_VFMSUBPS, + ND_INS_VFMSUBSD, + ND_INS_VFMSUBSS, + ND_INS_VFNMADD132PD, + ND_INS_VFNMADD132PS, + ND_INS_VFNMADD132SD, + ND_INS_VFNMADD132SS, + ND_INS_VFNMADD213PD, + ND_INS_VFNMADD213PS, + ND_INS_VFNMADD213SD, + ND_INS_VFNMADD213SS, + ND_INS_VFNMADD231PD, + ND_INS_VFNMADD231PS, + ND_INS_VFNMADD231SD, + ND_INS_VFNMADD231SS, + ND_INS_VFNMADDPD, + ND_INS_VFNMADDPS, + ND_INS_VFNMADDSD, + ND_INS_VFNMADDSS, + ND_INS_VFNMSUB132PD, + ND_INS_VFNMSUB132PS, + ND_INS_VFNMSUB132SD, + ND_INS_VFNMSUB132SS, + ND_INS_VFNMSUB213PD, + ND_INS_VFNMSUB213PS, + ND_INS_VFNMSUB213SD, + ND_INS_VFNMSUB213SS, + ND_INS_VFNMSUB231PD, + ND_INS_VFNMSUB231PS, + ND_INS_VFNMSUB231SD, + ND_INS_VFNMSUB231SS, + ND_INS_VFNMSUBPD, + ND_INS_VFNMSUBPS, + ND_INS_VFNMSUBSD, + ND_INS_VFNMSUBSS, + ND_INS_VFPCLASSPD, + ND_INS_VFPCLASSPS, + ND_INS_VFPCLASSSD, + ND_INS_VFPCLASSSS, + ND_INS_VFRCZPD, + ND_INS_VFRCZPS, + ND_INS_VFRCZSD, + ND_INS_VFRCZSS, + ND_INS_VGATHERDPD, + ND_INS_VGATHERDPS, + ND_INS_VGATHERPF0DPD, + ND_INS_VGATHERPF0DPS, + ND_INS_VGATHERPF0QPD, + ND_INS_VGATHERPF0QPS, + ND_INS_VGATHERPF1DPD, + ND_INS_VGATHERPF1DPS, + ND_INS_VGATHERPF1QPD, + ND_INS_VGATHERPF1QPS, + ND_INS_VGATHERQPD, + ND_INS_VGATHERQPS, + ND_INS_VGETEXPPD, + ND_INS_VGETEXPPS, + ND_INS_VGETEXPSD, + ND_INS_VGETEXPSS, + ND_INS_VGETMANTPD, + ND_INS_VGETMANTPS, + ND_INS_VGETMANTSD, + ND_INS_VGETMANTSS, + ND_INS_VGF2P8AFFINEINVQB, + ND_INS_VGF2P8AFFINEQB, + ND_INS_VGF2P8MULB, + ND_INS_VHADDPD, + ND_INS_VHADDPS, + ND_INS_VHSUBPD, + ND_INS_VHSUBPS, + ND_INS_VINSERTF128, + ND_INS_VINSERTF32X4, + ND_INS_VINSERTF32X8, + ND_INS_VINSERTF64X2, + ND_INS_VINSERTF64X4, + ND_INS_VINSERTI128, + ND_INS_VINSERTI32X4, + ND_INS_VINSERTI32X8, + ND_INS_VINSERTI64X2, + ND_INS_VINSERTI64X4, + ND_INS_VINSERTPS, + ND_INS_VLDDQU, + ND_INS_VLDMXCSR, + ND_INS_VMASKMOVDQU, + ND_INS_VMASKMOVPD, + ND_INS_VMASKMOVPS, + ND_INS_VMAXPD, + ND_INS_VMAXPS, + ND_INS_VMAXSD, + ND_INS_VMAXSS, + ND_INS_VMCALL, + ND_INS_VMCLEAR, + ND_INS_VMFUNC, + ND_INS_VMGEXIT, + ND_INS_VMINPD, + ND_INS_VMINPS, + ND_INS_VMINSD, + ND_INS_VMINSS, + ND_INS_VMLAUNCH, + ND_INS_VMLOAD, + ND_INS_VMMCALL, + ND_INS_VMOVAPD, + ND_INS_VMOVAPS, + ND_INS_VMOVD, + ND_INS_VMOVDDUP, + ND_INS_VMOVDQA, + ND_INS_VMOVDQA32, + ND_INS_VMOVDQA64, + ND_INS_VMOVDQU, + ND_INS_VMOVDQU16, + ND_INS_VMOVDQU32, + ND_INS_VMOVDQU64, + ND_INS_VMOVDQU8, + ND_INS_VMOVHLPS, + ND_INS_VMOVHPD, + ND_INS_VMOVHPS, + ND_INS_VMOVLHPS, + ND_INS_VMOVLPD, + ND_INS_VMOVLPS, + ND_INS_VMOVMSKPD, + ND_INS_VMOVMSKPS, + ND_INS_VMOVNTDQ, + ND_INS_VMOVNTDQA, + ND_INS_VMOVNTPD, + ND_INS_VMOVNTPS, + ND_INS_VMOVQ, + ND_INS_VMOVSD, + ND_INS_VMOVSHDUP, + ND_INS_VMOVSLDUP, + ND_INS_VMOVSS, + ND_INS_VMOVUPD, + ND_INS_VMOVUPS, + ND_INS_VMPSADBW, + ND_INS_VMPTRLD, + ND_INS_VMPTRST, + ND_INS_VMREAD, + ND_INS_VMRESUME, + ND_INS_VMRUN, + ND_INS_VMSAVE, + ND_INS_VMULPD, + ND_INS_VMULPS, + ND_INS_VMULSD, + ND_INS_VMULSS, + ND_INS_VMWRITE, + ND_INS_VMXOFF, + ND_INS_VMXON, + ND_INS_VORPD, + ND_INS_VORPS, + ND_INS_VP2INTERSECTD, + ND_INS_VP2INTERSECTQ, + ND_INS_VP4DPWSSD, + ND_INS_VP4DPWSSDS, + ND_INS_VPABSB, + ND_INS_VPABSD, + ND_INS_VPABSQ, + ND_INS_VPABSW, + ND_INS_VPACKSSDW, + ND_INS_VPACKSSWB, + ND_INS_VPACKUSDW, + ND_INS_VPACKUSWB, + ND_INS_VPADDB, + ND_INS_VPADDD, + ND_INS_VPADDQ, + ND_INS_VPADDSB, + ND_INS_VPADDSW, + ND_INS_VPADDUSB, + ND_INS_VPADDUSW, + ND_INS_VPADDW, + ND_INS_VPALIGNR, + ND_INS_VPAND, + ND_INS_VPANDD, + ND_INS_VPANDN, + ND_INS_VPANDND, + ND_INS_VPANDNQ, + ND_INS_VPANDQ, + ND_INS_VPAVGB, + ND_INS_VPAVGW, + ND_INS_VPBLENDD, + ND_INS_VPBLENDMB, + ND_INS_VPBLENDMD, + ND_INS_VPBLENDMQ, + ND_INS_VPBLENDMW, + ND_INS_VPBLENDVB, + ND_INS_VPBLENDW, + ND_INS_VPBROADCASTB, + ND_INS_VPBROADCASTD, + ND_INS_VPBROADCASTMB2Q, + ND_INS_VPBROADCASTMW2D, + ND_INS_VPBROADCASTQ, + ND_INS_VPBROADCASTW, + ND_INS_VPCLMULQDQ, + ND_INS_VPCMOV, + ND_INS_VPCMPB, + ND_INS_VPCMPD, + ND_INS_VPCMPEQB, + ND_INS_VPCMPEQD, + ND_INS_VPCMPEQQ, + ND_INS_VPCMPEQW, + ND_INS_VPCMPESTRI, + ND_INS_VPCMPESTRM, + ND_INS_VPCMPGTB, + ND_INS_VPCMPGTD, + ND_INS_VPCMPGTQ, + ND_INS_VPCMPGTW, + ND_INS_VPCMPISTRI, + ND_INS_VPCMPISTRM, + ND_INS_VPCMPQ, + ND_INS_VPCMPUB, + ND_INS_VPCMPUD, + ND_INS_VPCMPUQ, + ND_INS_VPCMPUW, + ND_INS_VPCMPW, + ND_INS_VPCOMB, + ND_INS_VPCOMD, + ND_INS_VPCOMPRESSB, + ND_INS_VPCOMPRESSD, + ND_INS_VPCOMPRESSQ, + ND_INS_VPCOMPRESSW, + ND_INS_VPCOMQ, + ND_INS_VPCOMUB, + ND_INS_VPCOMUD, + ND_INS_VPCOMUQ, + ND_INS_VPCOMUW, + ND_INS_VPCOMW, + ND_INS_VPCONFLICTD, + ND_INS_VPCONFLICTQ, + ND_INS_VPDPBUSD, + ND_INS_VPDPBUSDS, + ND_INS_VPDPWSSD, + ND_INS_VPDPWSSDS, + ND_INS_VPERM2F128, + ND_INS_VPERM2I128, + ND_INS_VPERMB, + ND_INS_VPERMD, + ND_INS_VPERMI2B, + ND_INS_VPERMI2D, + ND_INS_VPERMI2PD, + ND_INS_VPERMI2PS, + ND_INS_VPERMI2Q, + ND_INS_VPERMI2W, + ND_INS_VPERMILPD, + ND_INS_VPERMILPS, + ND_INS_VPERMILzz2PD, + ND_INS_VPERMILzz2PS, + ND_INS_VPERMPD, + ND_INS_VPERMPS, + ND_INS_VPERMQ, + ND_INS_VPERMT2B, + ND_INS_VPERMT2D, + ND_INS_VPERMT2PD, + ND_INS_VPERMT2PS, + ND_INS_VPERMT2Q, + ND_INS_VPERMT2W, + ND_INS_VPERMW, + ND_INS_VPEXPANDB, + ND_INS_VPEXPANDD, + ND_INS_VPEXPANDQ, + ND_INS_VPEXPANDW, + ND_INS_VPEXTRB, + ND_INS_VPEXTRD, + ND_INS_VPEXTRQ, + ND_INS_VPEXTRW, + ND_INS_VPGATHERDD, + ND_INS_VPGATHERDQ, + ND_INS_VPGATHERQD, + ND_INS_VPGATHERQQ, + ND_INS_VPHADDBD, + ND_INS_VPHADDBQ, + ND_INS_VPHADDBW, + ND_INS_VPHADDD, + ND_INS_VPHADDDQ, + ND_INS_VPHADDSW, + ND_INS_VPHADDUBD, + ND_INS_VPHADDUBQ, + ND_INS_VPHADDUBW, + ND_INS_VPHADDUDQ, + ND_INS_VPHADDUWD, + ND_INS_VPHADDUWQ, + ND_INS_VPHADDW, + ND_INS_VPHADDWD, + ND_INS_VPHADDWQ, + ND_INS_VPHMINPOSUW, + ND_INS_VPHSUBBW, + ND_INS_VPHSUBD, + ND_INS_VPHSUBDQ, + ND_INS_VPHSUBSW, + ND_INS_VPHSUBW, + ND_INS_VPHSUBWD, + ND_INS_VPINSRB, + ND_INS_VPINSRD, + ND_INS_VPINSRQ, + ND_INS_VPINSRW, + ND_INS_VPLZCNTD, + ND_INS_VPLZCNTQ, + ND_INS_VPMACSDD, + ND_INS_VPMACSDQH, + ND_INS_VPMACSDQL, + ND_INS_VPMACSSDD, + ND_INS_VPMACSSDQH, + ND_INS_VPMACSSDQL, + ND_INS_VPMACSSWD, + ND_INS_VPMACSSWW, + ND_INS_VPMACSWD, + ND_INS_VPMACSWW, + ND_INS_VPMADCSSWD, + ND_INS_VPMADCSWD, + ND_INS_VPMADD52HUQ, + ND_INS_VPMADD52LUQ, + ND_INS_VPMADDUBSW, + ND_INS_VPMADDWD, + ND_INS_VPMASKMOVD, + ND_INS_VPMASKMOVQ, + ND_INS_VPMAXSB, + ND_INS_VPMAXSD, + ND_INS_VPMAXSQ, + ND_INS_VPMAXSW, + ND_INS_VPMAXUB, + ND_INS_VPMAXUD, + ND_INS_VPMAXUQ, + ND_INS_VPMAXUW, + ND_INS_VPMINSB, + ND_INS_VPMINSD, + ND_INS_VPMINSQ, + ND_INS_VPMINSW, + ND_INS_VPMINUB, + ND_INS_VPMINUD, + ND_INS_VPMINUQ, + ND_INS_VPMINUW, + ND_INS_VPMOVB2M, + ND_INS_VPMOVD2M, + ND_INS_VPMOVDB, + ND_INS_VPMOVDW, + ND_INS_VPMOVM2B, + ND_INS_VPMOVM2D, + ND_INS_VPMOVM2Q, + ND_INS_VPMOVM2W, + ND_INS_VPMOVMSKB, + ND_INS_VPMOVQ2M, + ND_INS_VPMOVQB, + ND_INS_VPMOVQD, + ND_INS_VPMOVQW, + ND_INS_VPMOVSDB, + ND_INS_VPMOVSDW, + ND_INS_VPMOVSQB, + ND_INS_VPMOVSQD, + ND_INS_VPMOVSQW, + ND_INS_VPMOVSWB, + ND_INS_VPMOVSXBD, + ND_INS_VPMOVSXBQ, + ND_INS_VPMOVSXBW, + ND_INS_VPMOVSXDQ, + ND_INS_VPMOVSXWD, + ND_INS_VPMOVSXWQ, + ND_INS_VPMOVUSDB, + ND_INS_VPMOVUSDW, + ND_INS_VPMOVUSQB, + ND_INS_VPMOVUSQD, + ND_INS_VPMOVUSQW, + ND_INS_VPMOVUSWB, + ND_INS_VPMOVW2M, + ND_INS_VPMOVWB, + ND_INS_VPMOVZXBD, + ND_INS_VPMOVZXBQ, + ND_INS_VPMOVZXBW, + ND_INS_VPMOVZXDQ, + ND_INS_VPMOVZXWD, + ND_INS_VPMOVZXWQ, + ND_INS_VPMULDQ, + ND_INS_VPMULHRSW, + ND_INS_VPMULHUW, + ND_INS_VPMULHW, + ND_INS_VPMULLD, + ND_INS_VPMULLQ, + ND_INS_VPMULLW, + ND_INS_VPMULTISHIFTQB, + ND_INS_VPMULUDQ, + ND_INS_VPOPCNTB, + ND_INS_VPOPCNTD, + ND_INS_VPOPCNTQ, + ND_INS_VPOPCNTW, + ND_INS_VPOR, + ND_INS_VPORD, + ND_INS_VPORQ, + ND_INS_VPPERM, + ND_INS_VPROLD, + ND_INS_VPROLQ, + ND_INS_VPROLVD, + ND_INS_VPROLVQ, + ND_INS_VPRORD, + ND_INS_VPRORQ, + ND_INS_VPRORVD, + ND_INS_VPRORVQ, + ND_INS_VPROTB, + ND_INS_VPROTD, + ND_INS_VPROTQ, + ND_INS_VPROTW, + ND_INS_VPSADBW, + ND_INS_VPSCATTERDD, + ND_INS_VPSCATTERDQ, + ND_INS_VPSCATTERQD, + ND_INS_VPSCATTERQQ, + ND_INS_VPSHAB, + ND_INS_VPSHAD, + ND_INS_VPSHAQ, + ND_INS_VPSHAW, + ND_INS_VPSHLB, + ND_INS_VPSHLDD, + ND_INS_VPSHLDQ, + ND_INS_VPSHLDVD, + ND_INS_VPSHLDVQ, + ND_INS_VPSHLDVW, + ND_INS_VPSHLDW, + ND_INS_VPSHLQ, + ND_INS_VPSHRDD, + ND_INS_VPSHRDQ, + ND_INS_VPSHRDVD, + ND_INS_VPSHRDVQ, + ND_INS_VPSHRDVW, + ND_INS_VPSHRDW, + ND_INS_VPSHUFB, + ND_INS_VPSHUFBITQMB, + ND_INS_VPSHUFD, + ND_INS_VPSHUFHW, + ND_INS_VPSHUFLW, + ND_INS_VPSIGNB, + ND_INS_VPSIGND, + ND_INS_VPSIGNW, + ND_INS_VPSLLD, + ND_INS_VPSLLDQ, + ND_INS_VPSLLQ, + ND_INS_VPSLLVD, + ND_INS_VPSLLVQ, + ND_INS_VPSLLVW, + ND_INS_VPSLLW, + ND_INS_VPSRAD, + ND_INS_VPSRAQ, + ND_INS_VPSRAVD, + ND_INS_VPSRAVQ, + ND_INS_VPSRAVW, + ND_INS_VPSRAW, + ND_INS_VPSRLD, + ND_INS_VPSRLDQ, + ND_INS_VPSRLQ, + ND_INS_VPSRLVD, + ND_INS_VPSRLVQ, + ND_INS_VPSRLVW, + ND_INS_VPSRLW, + ND_INS_VPSUBB, + ND_INS_VPSUBD, + ND_INS_VPSUBQ, + ND_INS_VPSUBSB, + ND_INS_VPSUBSW, + ND_INS_VPSUBUSB, + ND_INS_VPSUBUSW, + ND_INS_VPSUBW, + ND_INS_VPTERNLOGD, + ND_INS_VPTERNLOGQ, + ND_INS_VPTEST, + ND_INS_VPTESTMB, + ND_INS_VPTESTMD, + ND_INS_VPTESTMQ, + ND_INS_VPTESTMW, + ND_INS_VPTESTNMB, + ND_INS_VPTESTNMD, + ND_INS_VPTESTNMQ, + ND_INS_VPTESTNMW, + ND_INS_VPUNPCKHBW, + ND_INS_VPUNPCKHDQ, + ND_INS_VPUNPCKHQDQ, + ND_INS_VPUNPCKHWD, + ND_INS_VPUNPCKLBW, + ND_INS_VPUNPCKLDQ, + ND_INS_VPUNPCKLQDQ, + ND_INS_VPUNPCKLWD, + ND_INS_VPXOR, + ND_INS_VPXORD, + ND_INS_VPXORQ, + ND_INS_VRANGEPD, + ND_INS_VRANGEPS, + ND_INS_VRANGESD, + ND_INS_VRANGESS, + ND_INS_VRCP14PD, + ND_INS_VRCP14PS, + ND_INS_VRCP14SD, + ND_INS_VRCP14SS, + ND_INS_VRCP28PD, + ND_INS_VRCP28PS, + ND_INS_VRCP28SD, + ND_INS_VRCP28SS, + ND_INS_VRCPPS, + ND_INS_VRCPSS, + ND_INS_VREDUCEPD, + ND_INS_VREDUCEPS, + ND_INS_VREDUCESD, + ND_INS_VREDUCESS, + ND_INS_VRNDSCALEPD, + ND_INS_VRNDSCALEPS, + ND_INS_VRNDSCALESD, + ND_INS_VRNDSCALESS, + ND_INS_VROUNDPD, + ND_INS_VROUNDPS, + ND_INS_VROUNDSD, + ND_INS_VROUNDSS, + ND_INS_VRSQRT14PD, + ND_INS_VRSQRT14PS, + ND_INS_VRSQRT14SD, + ND_INS_VRSQRT14SS, + ND_INS_VRSQRT28PD, + ND_INS_VRSQRT28PS, + ND_INS_VRSQRT28SD, + ND_INS_VRSQRT28SS, + ND_INS_VRSQRTPS, + ND_INS_VRSQRTSS, + ND_INS_VSCALEFPD, + ND_INS_VSCALEFPS, + ND_INS_VSCALEFSD, + ND_INS_VSCALEFSS, + ND_INS_VSCATTERDPD, + ND_INS_VSCATTERDPS, + ND_INS_VSCATTERPF0DPD, + ND_INS_VSCATTERPF0DPS, + ND_INS_VSCATTERPF0QPD, + ND_INS_VSCATTERPF0QPS, + ND_INS_VSCATTERPF1DPD, + ND_INS_VSCATTERPF1DPS, + ND_INS_VSCATTERPF1QPD, + ND_INS_VSCATTERPF1QPS, + ND_INS_VSCATTERQPD, + ND_INS_VSCATTERQPS, + ND_INS_VSHUFF32X4, + ND_INS_VSHUFF64X2, + ND_INS_VSHUFI32X4, + ND_INS_VSHUFI64X2, + ND_INS_VSHUFPD, + ND_INS_VSHUFPS, + ND_INS_VSQRTPD, + ND_INS_VSQRTPS, + ND_INS_VSQRTSD, + ND_INS_VSQRTSS, + ND_INS_VSTMXCSR, + ND_INS_VSUBPD, + ND_INS_VSUBPS, + ND_INS_VSUBSD, + ND_INS_VSUBSS, + ND_INS_VTESTPD, + ND_INS_VTESTPS, + ND_INS_VUCOMISD, + ND_INS_VUCOMISS, + ND_INS_VUNPCKHPD, + ND_INS_VUNPCKHPS, + ND_INS_VUNPCKLPD, + ND_INS_VUNPCKLPS, + ND_INS_VXORPD, + ND_INS_VXORPS, + ND_INS_VZEROALL, + ND_INS_VZEROUPPER, + ND_INS_WAIT, + ND_INS_WBINVD, + ND_INS_WBNOINVD, + ND_INS_WRFSBASE, + ND_INS_WRGSBASE, + ND_INS_WRMSR, + ND_INS_WRPKRU, + ND_INS_WRSHR, + ND_INS_WRSS, + ND_INS_WRUSS, + ND_INS_XABORT, + ND_INS_XADD, + ND_INS_XBEGIN, + ND_INS_XCHG, + ND_INS_XCRYPTCBC, + ND_INS_XCRYPTCFB, + ND_INS_XCRYPTCTR, + ND_INS_XCRYPTECB, + ND_INS_XCRYPTOFB, + ND_INS_XEND, + ND_INS_XGETBV, + ND_INS_XLATB, + ND_INS_XOR, + ND_INS_XORPD, + ND_INS_XORPS, + ND_INS_XRESLDTRK, + ND_INS_XRSTOR, + ND_INS_XRSTORS, + ND_INS_XSAVE, + ND_INS_XSAVEC, + ND_INS_XSAVEOPT, + ND_INS_XSAVES, + ND_INS_XSETBV, + ND_INS_XSHA1, + ND_INS_XSHA256, + ND_INS_XSTORE, + ND_INS_XSUSLDTRK, + ND_INS_XTEST, + +} ND_INS_CLASS; + + +typedef enum _ND_INS_SET +{ + ND_SET_INVALID = 0, + ND_SET_3DNOW, + ND_SET_ADX, + ND_SET_AES, + ND_SET_AMD, + ND_SET_AMXBF16, + ND_SET_AMXINT8, + ND_SET_AMXTILE, + ND_SET_AVX, + ND_SET_AVX2, + ND_SET_AVX2GATHER, + ND_SET_AVX5124FMAPS, + ND_SET_AVX5124VNNIW, + ND_SET_AVX512BF16, + ND_SET_AVX512BITALG, + ND_SET_AVX512BW, + ND_SET_AVX512CD, + ND_SET_AVX512DQ, + ND_SET_AVX512ER, + ND_SET_AVX512F, + ND_SET_AVX512IFMA, + ND_SET_AVX512PF, + ND_SET_AVX512VBMI, + ND_SET_AVX512VBMI2, + ND_SET_AVX512VNNI, + ND_SET_AVX512VP2INTERSECT, + ND_SET_AVX512VPOPCNTDQ, + ND_SET_BMI1, + ND_SET_BMI2, + ND_SET_CET, + ND_SET_CLDEMOTE, + ND_SET_CLFSH, + ND_SET_CLFSHOPT, + ND_SET_CLWB, + ND_SET_CLZERO, + ND_SET_CMPXCHG16B, + ND_SET_CYRIX, + ND_SET_CYRIX_SMM, + ND_SET_ENQCMD, + ND_SET_F16C, + ND_SET_FMA, + ND_SET_FMA4, + ND_SET_FXSAVE, + ND_SET_GFNI, + ND_SET_I186, + ND_SET_I286PROT, + ND_SET_I286REAL, + ND_SET_I386, + ND_SET_I486, + ND_SET_I486REAL, + ND_SET_I64, + ND_SET_I86, + ND_SET_INVLPGB, + ND_SET_INVPCID, + ND_SET_LONGMODE, + ND_SET_LWP, + ND_SET_LZCNT, + ND_SET_MCOMMIT, + ND_SET_MMX, + ND_SET_MOVBE, + ND_SET_MOVDIR64B, + ND_SET_MOVDIRI, + ND_SET_MPX, + ND_SET_MWAITT, + ND_SET_PAUSE, + ND_SET_PCLMULQDQ, + ND_SET_PCOMMIT, + ND_SET_PCONFIG, + ND_SET_PENTIUMREAL, + ND_SET_PKU, + ND_SET_POPCNT, + ND_SET_PPRO, + ND_SET_PREFETCH_NOP, + ND_SET_PTWRITE, + ND_SET_RDPID, + ND_SET_RDPMC, + ND_SET_RDPRU, + ND_SET_RDRAND, + ND_SET_RDSEED, + ND_SET_RDTSCP, + ND_SET_RDWRFSGS, + ND_SET_SCC, + ND_SET_SERIALIZE, + ND_SET_SGX, + ND_SET_SHA, + ND_SET_SMAP, + ND_SET_SMX, + ND_SET_SNP, + ND_SET_SSE, + ND_SET_SSE2, + ND_SET_SSE3, + ND_SET_SSE4, + ND_SET_SSE42, + ND_SET_SSE4A, + ND_SET_SSSE3, + ND_SET_SVM, + ND_SET_TBM, + ND_SET_TSX, + ND_SET_TSXLDTRK, + ND_SET_UD, + ND_SET_UNKNOWN, + ND_SET_VAES, + ND_SET_VPCLMULQDQ, + ND_SET_VTX, + ND_SET_WAITPKG, + ND_SET_WBNOINVD, + ND_SET_X87, + ND_SET_XOP, + ND_SET_XSAVE, + ND_SET_XSAVEC, + ND_SET_XSAVES, + +} ND_INS_SET; + + +typedef enum _ND_INS_TYPE +{ + ND_CAT_INVALID = 0, + ND_CAT_3DNOW, + ND_CAT_AES, + ND_CAT_AMX, + ND_CAT_ARITH, + ND_CAT_AVX, + ND_CAT_AVX2, + ND_CAT_AVX2GATHER, + ND_CAT_AVX512, + ND_CAT_AVX512BF16, + ND_CAT_AVX512VBMI, + ND_CAT_AVX512VP2INTERSECT, + ND_CAT_BITBYTE, + ND_CAT_BLEND, + ND_CAT_BMI1, + ND_CAT_BMI2, + ND_CAT_BROADCAST, + ND_CAT_CALL, + ND_CAT_CET, + ND_CAT_CLDEMOTE, + ND_CAT_CMOV, + ND_CAT_COMPRESS, + ND_CAT_COND_BR, + ND_CAT_CONFLICT, + ND_CAT_CONVERT, + ND_CAT_DATAXFER, + ND_CAT_DECIMAL, + ND_CAT_ENQCMD, + ND_CAT_EXPAND, + ND_CAT_FLAGOP, + ND_CAT_FMA4, + ND_CAT_GATHER, + ND_CAT_GFNI, + ND_CAT_I386, + ND_CAT_IFMA, + ND_CAT_INTERRUPT, + ND_CAT_IO, + ND_CAT_IOSTRINGOP, + ND_CAT_KMASK, + ND_CAT_KNL, + ND_CAT_LOGIC, + ND_CAT_LOGICAL, + ND_CAT_LOGICAL_FP, + ND_CAT_LWP, + ND_CAT_LZCNT, + ND_CAT_MISC, + ND_CAT_MMX, + ND_CAT_MOVDIR64B, + ND_CAT_MOVDIRI, + ND_CAT_MPX, + ND_CAT_NOP, + ND_CAT_PADLOCK, + ND_CAT_PCLMULQDQ, + ND_CAT_PCONFIG, + ND_CAT_POP, + ND_CAT_PREFETCH, + ND_CAT_PTWRITE, + ND_CAT_PUSH, + ND_CAT_RDPID, + ND_CAT_RDRAND, + ND_CAT_RDSEED, + ND_CAT_RDWRFSGS, + ND_CAT_RET, + ND_CAT_ROTATE, + ND_CAT_SCATTER, + ND_CAT_SEGOP, + ND_CAT_SEMAPHORE, + ND_CAT_SGX, + ND_CAT_SHA, + ND_CAT_SHIFT, + ND_CAT_SMAP, + ND_CAT_SSE, + ND_CAT_SSE2, + ND_CAT_STRINGOP, + ND_CAT_STTNI, + ND_CAT_SYSCALL, + ND_CAT_SYSRET, + ND_CAT_SYSTEM, + ND_CAT_UD, + ND_CAT_UNCOND_BR, + ND_CAT_UNDOC, + ND_CAT_UNKNOWN, + ND_CAT_VAES, + ND_CAT_VFMA, + ND_CAT_VFMAPS, + ND_CAT_VNNI, + ND_CAT_VNNIW, + ND_CAT_VPCLMULQDQ, + ND_CAT_VPOPCNT, + ND_CAT_VTX, + ND_CAT_WAITPKG, + ND_CAT_WBNOINVD, + ND_CAT_WIDENOP, + ND_CAT_X87_ALU, + ND_CAT_XOP, + ND_CAT_XSAVE, + +} ND_INS_CATEGORY; + + + +#endif diff --git a/inc/cpuidflags.h b/inc/cpuidflags.h new file mode 100644 index 0000000..50042d8 --- /dev/null +++ b/inc/cpuidflags.h @@ -0,0 +1,107 @@ +#ifndef _CPUID_FLAGS_H_ +#define _CPUID_FLAGS_H_ + +#define ND_CFF_NO_LEAF 0xFFFFFFFF +#define ND_CFF_NO_SUBLEAF 0x00FFFFFF + + +#define ND_CFF(leaf, subleaf, reg, bit) ((uint64_t)(leaf) | ((uint64_t)((subleaf) & 0xFFFFFF) << 32) | ((uint64_t)(reg) << 56) | ((uint64_t)(bit) << 59)) + +#define ND_CFF_FPU ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 0) +#define ND_CFF_MSR ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 5) +#define ND_CFF_CX8 ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 8) +#define ND_CFF_SEP ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 11) +#define ND_CFF_CMOV ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 15) +#define ND_CFF_CLFSH ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 19) +#define ND_CFF_MMX ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 23) +#define ND_CFF_FXSAVE ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 24) +#define ND_CFF_SSE ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 25) +#define ND_CFF_SSE2 ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 26) +#define ND_CFF_SSE3 ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 0) +#define ND_CFF_PCLMULQDQ ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 1) +#define ND_CFF_MONITOR ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 3) +#define ND_CFF_VTX ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 5) +#define ND_CFF_SMX ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 6) +#define ND_CFF_SSSE3 ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 9) +#define ND_CFF_FMA ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 12) +#define ND_CFF_SSE4 ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 19) +#define ND_CFF_SSE42 ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 20) +#define ND_CFF_MOVBE ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 22) +#define ND_CFF_POPCNT ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 23) +#define ND_CFF_AES ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 25) +#define ND_CFF_XSAVE ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 26) +#define ND_CFF_AVX ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 28) +#define ND_CFF_F16C ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 29) +#define ND_CFF_RDRAND ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 30) +#define ND_CFF_RDWRFSGS ND_CFF(0x00000007, 0x00000000, REG_EBX, 0) +#define ND_CFF_SGX ND_CFF(0x00000007, 0x00000000, REG_EBX, 2) +#define ND_CFF_BMI1 ND_CFF(0x00000007, 0x00000000, REG_EBX, 3) +#define ND_CFF_HLE ND_CFF(0x00000007, 0x00000000, REG_EBX, 4) +#define ND_CFF_AVX2 ND_CFF(0x00000007, 0x00000000, REG_EBX, 5) +#define ND_CFF_BMI2 ND_CFF(0x00000007, 0x00000000, REG_EBX, 8) +#define ND_CFF_INVPCID ND_CFF(0x00000007, 0x00000000, REG_EBX, 10) +#define ND_CFF_RTM ND_CFF(0x00000007, 0x00000000, REG_EBX, 11) +#define ND_CFF_MPX ND_CFF(0x00000007, 0x00000000, REG_EBX, 14) +#define ND_CFF_AVX512F ND_CFF(0x00000007, 0x00000000, REG_EBX, 16) +#define ND_CFF_AVX512DQ ND_CFF(0x00000007, 0x00000000, REG_EBX, 17) +#define ND_CFF_RDSEED ND_CFF(0x00000007, 0x00000000, REG_EBX, 18) +#define ND_CFF_ADX ND_CFF(0x00000007, 0x00000000, REG_EBX, 19) +#define ND_CFF_SMAP ND_CFF(0x00000007, 0x00000000, REG_EBX, 20) +#define ND_CFF_AVX512IFMA ND_CFF(0x00000007, 0x00000000, REG_EBX, 21) +#define ND_CFF_PCOMMIT ND_CFF(0x00000007, 0x00000000, REG_EBX, 22) +#define ND_CFF_CLFSHOPT ND_CFF(0x00000007, 0x00000000, REG_EBX, 23) +#define ND_CFF_CLWB ND_CFF(0x00000007, 0x00000000, REG_EBX, 24) +#define ND_CFF_AVX512PF ND_CFF(0x00000007, 0x00000000, REG_EBX, 26) +#define ND_CFF_AVX512ER ND_CFF(0x00000007, 0x00000000, REG_EBX, 27) +#define ND_CFF_AVX512CD ND_CFF(0x00000007, 0x00000000, REG_EBX, 28) +#define ND_CFF_SHA ND_CFF(0x00000007, 0x00000000, REG_EBX, 29) +#define ND_CFF_AVX512BW ND_CFF(0x00000007, 0x00000000, REG_EBX, 30) +#define ND_CFF_PREFETCHWT1 ND_CFF(0x00000007, 0x00000000, REG_ECX, 0) +#define ND_CFF_AVX512VBMI ND_CFF(0x00000007, 0x00000000, REG_ECX, 1) +#define ND_CFF_PKU ND_CFF(0x00000007, 0x00000000, REG_ECX, 3) +#define ND_CFF_WAITPKG ND_CFF(0x00000007, 0x00000000, REG_ECX, 5) +#define ND_CFF_AVX512VBMI2 ND_CFF(0x00000007, 0x00000000, REG_ECX, 6) +#define ND_CFF_CET ND_CFF(0x00000007, 0x00000000, REG_ECX, 7) +#define ND_CFF_GFNI ND_CFF(0x00000007, 0x00000000, REG_ECX, 8) +#define ND_CFF_VAES ND_CFF(0x00000007, 0x00000000, REG_ECX, 9) +#define ND_CFF_VPCLMULQDQ ND_CFF(0x00000007, 0x00000000, REG_ECX, 10) +#define ND_CFF_AVX512VNNI ND_CFF(0x00000007, 0x00000000, REG_ECX, 11) +#define ND_CFF_AVX512BITALG ND_CFF(0x00000007, 0x00000000, REG_ECX, 12) +#define ND_CFF_AVX512VPOPCNTDQ ND_CFF(0x00000007, 0x00000000, REG_ECX, 14) +#define ND_CFF_RDPID ND_CFF(0x00000007, 0x00000000, REG_ECX, 22) +#define ND_CFF_CLDEMOTE ND_CFF(0x00000007, 0x00000000, REG_ECX, 25) +#define ND_CFF_MOVDIRI ND_CFF(0x00000007, 0x00000000, REG_ECX, 27) +#define ND_CFF_MOVDIR64B ND_CFF(0x00000007, 0x00000000, REG_ECX, 28) +#define ND_CFF_ENQCMD ND_CFF(0x00000007, 0x00000000, REG_ECX, 29) +#define ND_CFF_AVX5124VNNIW ND_CFF(0x00000007, 0x00000000, REG_EDX, 2) +#define ND_CFF_AVX5124FMAPS ND_CFF(0x00000007, 0x00000000, REG_EDX, 3) +#define ND_CFF_AVX512VP2INTERSECT ND_CFF(0x00000007, 0x00000000, REG_EDX, 8) +#define ND_CFF_SERIALIZE ND_CFF(0x00000007, 0x00000000, REG_EDX, 14) +#define ND_CFF_TSXLDTRK ND_CFF(0x00000007, 0x00000000, REG_EDX, 16) +#define ND_CFF_PCONFIG ND_CFF(0x00000007, 0x00000000, REG_EDX, 18) +#define ND_CFF_AMXBF16 ND_CFF(0x00000007, 0x00000000, REG_EDX, 22) +#define ND_CFF_AMXTILE ND_CFF(0x00000007, 0x00000000, REG_EDX, 24) +#define ND_CFF_AMXINT8 ND_CFF(0x00000007, 0x00000000, REG_EDX, 25) +#define ND_CFF_AVX512BF16 ND_CFF(0x00000007, 0x00000001, REG_EAX, 5) +#define ND_CFF_XSAVEOPT ND_CFF(0x0000000D, 0x00000001, REG_EAX, 0) +#define ND_CFF_XSAVEC ND_CFF(0x0000000D, 0x00000001, REG_EAX, 1) +#define ND_CFF_XSAVES ND_CFF(0x0000000D, 0x00000001, REG_EAX, 3) +#define ND_CFF_PTWRITE ND_CFF(0x00000014, 0x00000000, REG_EBX, 4) +#define ND_CFF_SVM ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 2) +#define ND_CFF_LZCNT ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 5) +#define ND_CFF_SSE4A ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 6) +#define ND_CFF_PREFETCHW ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 8) +#define ND_CFF_FSC ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 11) +#define ND_CFF_XOP ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 11) +#define ND_CFF_LWP ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 15) +#define ND_CFF_FMA4 ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 16) +#define ND_CFF_TBM ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 21) +#define ND_CFF_INVLPGB ND_CFF(0x80000001, 0xFFFFFFFF, REG_EDX, 24) +#define ND_CFF_RDTSCP ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 27) +#define ND_CFF_3DNOW ND_CFF(0x80000001, 0xFFFFFFFF, REG_EDX, 31) +#define ND_CFF_WBNOINVD ND_CFF(0x80000008, 0xFFFFFFFF, REG_EBX, 9) +#define ND_CFF_RDPRU ND_CFF(0x80000008, 0xFFFFFFFF, REG_EBX, 4) +#define ND_CFF_MCOMMIT ND_CFF(0x80000008, 0xFFFFFFFF, REG_EBX, 8) +#define ND_CFF_SNP ND_CFF(0x8000001F, 0xFFFFFFFF, REG_EAX, 4) + +#endif // _CPUID_FLAGS_H_ diff --git a/inc/disasmstatus.h b/inc/disasmstatus.h new file mode 100644 index 0000000..330501f --- /dev/null +++ b/inc/disasmstatus.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2020 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _DISASMSTATUS_H_ +#define _DISASMSTATUS_H_ + +// +// Return statuses. +// +typedef unsigned int NDSTATUS; + +// Success codes are all < 0x80000000. +#define ND_STATUS_SUCCESS 0x00000000 // All good. + +// Hint/success codes. +#define ND_STATUS_HINT_OPERAND_NOT_USED 0x00000001 + +// Error codes are all > 0x80000000. +#define ND_STATUS_BUFFER_TOO_SMALL 0x80000001 // The provided input buffer is too small. +#define ND_STATUS_INVALID_ENCODING 0x80000002 // Invalid encoding/instruction. +#define ND_STATUS_INSTRUCTION_TOO_LONG 0x80000003 // Instruction exceeds the maximum 15 bytes. +#define ND_STATUS_INVALID_PREFIX_SEQUENCE 0x80000004 // Invalid prefix sequence is present. +#define ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION 0x80000005 // The instruction uses an invalid register. +#define ND_STATUS_XOP_WITH_PREFIX 0x80000006 // XOP is present, but also a legacy prefix. +#define ND_STATUS_VEX_WITH_PREFIX 0x80000007 // VEX is present, but also a legacy prefix. +#define ND_STATUS_EVEX_WITH_PREFIX 0x80000008 // EVEX is present, but also a legacy prefix. +#define ND_STATUS_INVALID_ENCODING_IN_MODE 0x80000009 // Invalid encoding/instruction. +#define ND_STATUS_BAD_LOCK_PREFIX 0x8000000A // Invalid usage of LOCK. +#define ND_STATUS_CS_LOAD 0x8000000B // An attempt to load the CS register. +#define ND_STATUS_66_NOT_ACCEPTED 0x8000000C // 0x66 prefix is not accepted. +#define ND_STATUS_16_BIT_ADDRESSING_NOT_SUPPORTED 0x8000000D // 16 bit addressing mode not supported. +#define ND_STATUS_RIP_REL_ADDRESSING_NOT_SUPPORTED 0x8000000E // RIP-relative addressing not supported. + +// VEX/EVEX specific errors. +#define ND_STATUS_VSIB_WITHOUT_SIB 0x80000030 // Instruction uses VSIB, but SIB is not present. +#define ND_STATUS_INVALID_VSIB_REGS 0x80000031 // VSIB addressing, same vector reg used more than once. +#define ND_STATUS_VEX_VVVV_MUST_BE_ZERO 0x80000032 // VEX.VVVV field must be zero. +#define ND_STATUS_MASK_NOT_SUPPORTED 0x80000033 // Masking is not supported. +#define ND_STATUS_MASK_REQUIRED 0x80000034 // Masking is mandatory. +#define ND_STATUS_ER_SAE_NOT_SUPPORTED 0x80000035 // Embedded rounding/SAE not supported. +#define ND_STATUS_ZEROING_NOT_SUPPORTED 0x80000036 // Zeroing not supported. +#define ND_STATUS_ZEROING_ON_MEMORY 0x80000037 // Zeroing on memory. +#define ND_STATUS_ZEROING_NO_MASK 0x80000038 // Zeroing without masking. +#define ND_STATUS_BROADCAST_NOT_SUPPORTED 0x80000039 // Broadcast not supported. + +// Not encoding specific. +#define ND_STATUS_INVALID_PARAMETER 0x80000100 // An invalid parameter was provided. +#define ND_STATUS_INVALID_INSTRUX 0x80000101 // The INSTRUX contains unexpected values. +#define ND_STATUS_BUFFER_OVERFLOW 0x80000103 // Not enough space is available to format textual disasm. + +#define ND_STATUS_INTERNAL_ERROR 0x80000200 // Internal error occurred. + + +#define ND_SUCCESS(status) (status < 0x80000000) + +#endif diff --git a/inc/disasmtypes.h b/inc/disasmtypes.h new file mode 100644 index 0000000..dd90f24 --- /dev/null +++ b/inc/disasmtypes.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2020 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _DISASM_TYPES_H_ +#define _DISASM_TYPES_H_ + +#if defined(KERNEL_MODE) && defined(_MSC_VER) +# include +# include + +#else + +# include +# include +# include + +#endif + +#endif diff --git a/inc/registers.h b/inc/registers.h new file mode 100644 index 0000000..91e4be8 --- /dev/null +++ b/inc/registers.h @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2020 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _REGISTERS_H_ +#define _REGISTERS_H_ + +// +// Registers enumerations +// +enum +{ + REG_RAX, REG_RCX, REG_RDX, REG_RBX, REG_RSP, REG_RBP, REG_RSI, REG_RDI, + REG_R8, REG_R9, REG_R10, REG_R11, REG_R12, REG_R13, REG_R14, REG_R15, +}; + +enum +{ + REG_EAX, REG_ECX, REG_EDX, REG_EBX, REG_ESP, REG_EBP, REG_ESI, REG_EDI, + REG_R8D, REG_R9D, REG_R10D,REG_R11D,REG_R12D,REG_R13D,REG_R14D,REG_R15D, +}; + +enum +{ + REG_AX, REG_CX, REG_DX, REG_BX, REG_SP, REG_BP, REG_SI, REG_DI, + REG_R8W, REG_R9W, REG_R10W,REG_R11W,REG_R12W,REG_R13W,REG_R14W,REG_R15W, +}; + +enum +{ + REG_AL, REG_CL, REG_DL, REG_BL, REG_AH, REG_CH, REG_DH, REG_BH, +}; + +enum +{ + REG_AL64, REG_CL64, REG_DL64, REG_BL64, REG_SPL, REG_BPL, REG_SIL, REG_DIL, + REG_R8L, REG_R9L, REG_R10L, REG_R11L, REG_R12L, REG_R13L, REG_R14L, REG_R15L, +}; + +enum +{ + REG_ES, REG_CS, REG_SS, REG_DS, REG_FS, REG_GS, REG_INV6, REG_INV7, +}; + +enum +{ + REG_CR0, REG_CR1, REG_CR2, REG_CR3, REG_CR4, REG_CR5, REG_CR6, REG_CR7, + REG_CR8, REG_CR9, REG_CR10, REG_CR11, REG_CR12, REG_CR13, REG_CR14, REG_CR15, +}; + +enum +{ + REG_DR0, REG_DR1, REG_DR2, REG_DR3, REG_DR4, REG_DR5, REG_DR6, REG_DR7, + REG_DR8, REG_DR9, REG_DR10, REG_DR11, REG_DR12, REG_DR13, REG_DR14, REG_DR15, +}; + +enum +{ + REG_TR0, REG_TR1, REG_TR2, REG_TR3, REG_TR4, REG_TR5, REG_TR6, REG_TR7, + REG_TR8, REG_TR9, REG_TR10, REG_TR11, REG_TR12, REG_TR13, REG_TR14, REG_TR15, +}; + +enum +{ + REG_K0, REG_K1, REG_K2, REG_K3, REG_K4, REG_K5, REG_K6, REG_K7, +}; + +enum +{ + REG_BND0, REG_BND1, REG_BND2, REG_BND3, +}; + +enum +{ + REG_ST0, REG_ST1, REG_ST2, REG_ST3, REG_ST4, REG_ST5, REG_ST6, REG_ST7, +}; + +enum +{ + REG_XMM0, REG_XMM1, REG_XMM2, REG_XMM3, REG_XMM4, REG_XMM5, REG_XMM6, REG_XMM7, + REG_XMM8, REG_XMM9, REG_XMM10, REG_XMM11, REG_XMM12, REG_XMM13, REG_XMM14, REG_XMM15, + REG_XMM16, REG_XMM17, REG_XMM18, REG_XMM19, REG_XMM20, REG_XMM21, REG_XMM22, REG_XMM23, + REG_XMM24, REG_XMM25, REG_XMM26, REG_XMM27, REG_XMM28, REG_XMM29, REG_XMM30, REG_XMM31, +}; + +enum +{ + REG_YMM0, REG_YMM1, REG_YMM2, REG_YMM3, REG_YMM4, REG_YMM5, REG_YMM6, REG_YMM7, + REG_YMM8, REG_YMM9, REG_YMM10, REG_YMM11, REG_YMM12, REG_YMM13, REG_YMM14, REG_YMM15, + REG_YMM16, REG_YMM17, REG_YMM18, REG_YMM19, REG_YMM20, REG_YMM21, REG_YMM22, REG_YMM23, + REG_YMM24, REG_YMM25, REG_YMM26, REG_YMM27, REG_YMM28, REG_YMM29, REG_YMM30, REG_YMM31, +}; + +enum +{ + REG_ZMM0, REG_ZMM1, REG_ZMM2, REG_ZMM3, REG_ZMM4, REG_ZMM5, REG_ZMM6, REG_ZMM7, + REG_ZMM8, REG_ZMM9, REG_ZMM10, REG_ZMM11, REG_ZMM12, REG_ZMM13, REG_ZMM14, REG_ZMM15, + REG_ZMM16, REG_ZMM17, REG_ZMM18, REG_ZMM19, REG_ZMM20, REG_ZMM21, REG_ZMM22, REG_ZMM23, + REG_ZMM24, REG_ZMM25, REG_ZMM26, REG_ZMM27, REG_ZMM28, REG_ZMM29, REG_ZMM30, REG_ZMM31, +}; + +enum +{ + REG_GDTR, REG_IDTR, REG_LDTR, REG_TR, +}; + +enum +{ + REG_X87_CONTROL, REG_X87_TAG, REG_X87_STATUS, +}; + +enum +{ + REG_XCR0, REG_XCR1, REG_XCR_ANY = 0xFF, +}; + +#define REG_IA32_TSC 0x00000010 +#define REG_IA32_SYSENTER_CS 0x00000174 +#define REG_IA32_SYSENTER_ESP 0x00000175 +#define REG_IA32_SYSENTER_EIP 0x00000176 +#define REG_IA32_STAR 0xC0000081 +#define REG_IA32_LSTAR 0xC0000082 +#define REG_IA32_FMASK 0xC0000084 +#define REG_IA32_FS_BASE 0xC0000100 +#define REG_IA32_GS_BASE 0xC0000101 +#define REG_IA32_KERNEL_GS_BASE 0xC0000102 +#define REG_IA32_TSC_AUX 0xC0000103 +#define REG_MSR_ANY 0xFFFFFFFF + +#define REG_RFLAG_CF (1 << 0) +#define REG_RFLAG_PF (1 << 2) +#define REG_RFLAG_AF (1 << 4) +#define REG_RFLAG_ZF (1 << 6) +#define REG_RFLAG_SF (1 << 7) +#define REG_RFLAG_TF (1 << 8) +#define REG_RFLAG_IF (1 << 9) +#define REG_RFLAG_DF (1 << 10) +#define REG_RFLAG_OF (1 << 11) +#define REG_RFLAG_IOPL (3 << 12) +#define REG_RFLAG_NT (1 << 14) +#define REG_RFLAG_RF (1 << 16) +#define REG_RFLAG_VM (1 << 17) +#define REG_RFLAG_AC (1 << 18) +#define REG_RFLAG_VIF (1 << 19) +#define REG_RFLAG_VIP (1 << 20) +#define REG_RFLAG_ID (1 << 21) + +#endif diff --git a/inc/version.h b/inc/version.h new file mode 100644 index 0000000..bd746fd --- /dev/null +++ b/inc/version.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2020 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _DISASM_VER_H_ +#define _DISASM_VER_H_ + +#define DISASM_VERSION_MAJOR 1 +#define DISASM_VERSION_MINOR 25 +#define DISASM_VERSION_REVISION 0 + +#endif // _DISASM_VER_H_ diff --git a/isagenerator/Makefile b/isagenerator/Makefile new file mode 100644 index 0000000..38f5666 --- /dev/null +++ b/isagenerator/Makefile @@ -0,0 +1,4 @@ +.PHONY: all + +all: + python3 generate_tables.py instructions \ No newline at end of file diff --git a/isagenerator/README.md b/isagenerator/README.md new file mode 100644 index 0000000..2e86e9c --- /dev/null +++ b/isagenerator/README.md @@ -0,0 +1,184 @@ +# Introduction +This project is used to generate all the C header files and structures used by the main disassembler. The project contains two main components: + +1. Instruction specifications (inside the instructions folder) +2. Generation scripts (disasmlib.py & generate_tables.py) + +The instruction specification also contains additional information such as CPUID feature flag, valid operating modes or FLAGS access. +There are two scripts in the project: the disasmlib.py, which is a library used to parse to instruction specifications and provide all the information in classes, and the generate_tables.py, which uses the disasmlib.py library in order to generate the relevant C files & structures. Adding support for a brand new instruction is usually done by simply adding it inside the relevant table file. The modes, flags or cpuid files may also be modified, if the instruction operates on the flags, has some operating mode restrictions and requires a certain CPUID flag to be set. Normally, the disasmlib.py and generate_tables.py scripts don't need to be modified; the only exception to this is if a new encoding is created, which would also require the main disassembler to be updated. + +## Instruction specification syntax +Instruction specifiers have the following format: +mnemonic|explicit operands|implicit operands|encoding|flags +NOTE: Everything is case sensitive, except for the mnemonic. + +### Mnemonic +This is plain and simple the instruction mnemonic, as defined by the Intel docs. + +### Explicit operands +This sections lists all the explicit operands of the instruction. An operand is explicit if it needs to be manually specified when assembling an instruction. For example, the instruction "ADD eax, ecx" has two explicit operands: "eax" and "ecx". The format for the operands can be seen in the "Operands specification syntax" section. + +### Implicit operands +Many instructions operate on additional implicit operands. A very good example is the flags register, which is tested or modified by many instructions, but it doesn't have to be specified in the instruction. In our previous example, "ADD eax, ecx" has two explicit operands, but it also has an implicit operand, the "FLAGS" register which is modified according to the result. The format for the operands can be seen in the "Operands specification syntax" section. + +## Operands specification syntax + +### Type + size specifiers + +#### Operand type +Please refer to valid_optype inside disasmlib.py for the list & description of valid operand type. + +#### Operand size +Please refer to valid_opsize inside disasmlib.py for the list & description of valid operand sizes. + +### Hard-coded specifiers +Please refer to valid_impops inside disasmlib.py for the list & description of valid implicit operands. + +## Instruction encoding +Instruction encoding must follow the explicit & implicit operands sections, and must be enclosed in square brackets. + +### Legacy encoding +The following specifiers can be used to describe a legacy instruction encoding: +- 0x66 - the 0x66 prefix must be present +- 0xF3 - the 0xF3 prefix must be present +- 0xF2 - the 0xF2 prefix must be present +- NP - the instruction must be encoded without 0x66, 0xF3 and 0xF2 prefixes; presence of any of them will cause a #UD +- a0xF3 - the 0xF3 prefix must be present, and its absence encodes another instruction. This is used for instructions + which are still valid with 0x66 prefix (for example, PAUSE vs NOP) +- o64 - the instruction encoding is valid only in 64 bit mode +- rexw - REX prefix must be present and the REX.W bit must be set +- rex - REX prefix must be present +- rep - any REP prefix must be present +- ds16 - encoding valid when data size is 16 bit +- ds32 - encoding valid when data size is 32 bit +- ds64 - encoding valid when data size is 64 bit +- dds64 - encoding valid when default data size is 64 bit +- fds64 - encoding valid when data size is forced to 64 bit +- as16 - encoding valid when 16 bit addressing is used +- as32 - encoding valid when 32 bit addressing is used +- as64 - encoding valid when 64 bit addressing is used +- /r - a modrm byte follows the instruction +- /x - where x is a natural number in the interval [0, 7], indicates that the encoding requires the modrm.reg field + to have the indicated value x (for example: /3 indicates that the encoding requires modrm.reg == 3) +- /0xXX - where 0xXX is a hex number, indicates that the modrm value must be fixed to 0xXX +- /x:mem - like /x, but modrm.mod must encode a memory access (modrm.mod != 3) +- /x:reg - like /x, but modrm.mod must encode a reg access (modrm.mod == 3) +- modrmpmp - prefer the modrm.mod for encoding redirection instead of modrm.reg +- ib - an immediate byte follows the instruction +- iw - an immediate word follows the instruction +- iz - an immediate word or dword follows the instruction +- iv - an immediate word, dword or qword follows the instruction +- cb - a byte encoded relative offset follows the instruction +- cz - a word or dword encoded relative offset follows the instruction +- cp - a far pointer follows the instruction +- bitbase - instruction uses bitbase addressing +- mib - instruction uses MIB addressing +- 0xXX - instruction opcode (at least one must be present) +- is4 - a registers encoded in a following immediate byte + +### XOP encoding +An instruction uses XOP encoding if the keyword xop is used as the first specifier. Other specifiers: +- m - indicates the XOP encoding map +- w - indicates the value of the XOP.W flag; can be 0 or 1 + +### VEX encoding +An instruction uses VEX encoding if the keyword vex is used as the first specifier. Other specifiers: +- m - indicates the VEX encoding map (1 - 0x0F, 2 - 0x0F 0x38, 3 - 0x0F 0x3A) +- p - indicates the VEX legacy compressed prefix value (0 - NP, 1 - 0x66, 2 - 0xF3, 3 - 0xF2) +- w - indicates the VEX.W value; (0 - 32 bit, 1 - 64 bit, x - both values are valid, i - ignored) +- l - indicates the VEX vector length (0 - 128 bit, 1 - 256 bit, x - both values are valid, i - ignored) +- vsib - VSIB addressing is used + +### EVEX encoding +An instruction uses EVEX encoding if the keyword evex is used as the first specifier. Other specifiers: +- m - indicates the EVEX encoding map (1 - 0x0F, 2 - 0x0F 0x38, 3 - 0x0F 0x3A) +- p - indicates the VEX legacy compressed prefix value (0 - NP, 1 - 0x66, 2 - 0xF3, 3 - 0xF2) +- w - indicates the VEX.W value; (0 - 32 bit, 1 - 64 bit, x - both values are valid, i - ignored) +- l - indicates the VEX vector length (0 - 128 bit, 1 - 256 bit, 2 - 512 bit, x - all values are valid, i - ignored) +- vsib - VSIB addressing is used + +## Flags +Zero or more flags can follow the instruction encoding, specifying additional information about the instruction. Each flag is preceded by a keyword formed of only one letter. + +### Instruction set - s +Defining an instruction set will automatically define a new constant inside the constants.h file. Anything can be specified for the instruction set. Specifying, for example, the set "TEST" would automatically define "ND_ISA_TEST" which can then be used to identify instructions belonging to that set. If the set is not specified, the default set "UNKNOWN" will be used. + +### Instruction type - t +Defining an instruction type will automatically define a new constant inside the constants.h file. Anything can be specified for the instruction type. Specifying, for example, the category "TEST" would automatically define "ND_CAT_TEST" which can then be used to identify instructions. Absence of the type specifier will default to the "UNKNOWN" instruction category. + +### Instruction class - c +By default, the mnemonic defines the instruction class. Specifying something else will override this (for example, in case of LODSB/LODSW/LODSD/LODSQ, the generic LODS instruction class is specified). If the mnemonic is "TEST", for example, the class "ND_INS_TEST" will be defined automatically which can then be used to identify the instruction. Explicitly specifying the class will override the default value. + +### Attributes - a +The instruction attributes are the instruction properties (for example, that the modrm is present, or the instruction uses mandatory masking). Please refer to valid_attributes inside disasmlib.py for the list of valid attributes. + +### Operand access map - w +For each instruction operand (both explicit and implicit), the access type must be specified using the w keyword. In order to separate access for each operand, use |. Please refer to valid_access inside disasmlib.py for valid options. Note that in case of EVEX instructions that support masking, the mask register is considered a separate operand. For example, given the instruction "ADD Ev,Gv Fv" would need the access to be specified for all three operands like follows: "w:RW|R|W", which means the first operand (Ev) is read and written, the second one (Gv) is read and the third (Fv) is written. + +### Accepted prefixes map - p +Indicates the prefixes accepted by the instruction. Please refer to valid_prefixes inside disasmlib.py for valid prefixes. In some cases (for example, the "LOCK" prefix), if the instruction is encoded using the "LOCK" prefix but this is not specified in the instruction description, decoding will fail. In all the other cases, the prefix is simply ignored - it will be digested by the decoder, but it will not be shown in the disassembly, nor it will cause the instruction description to be different, aside from the fact that the relevant field indicating the presence of the prefix being set. + +### CPUID feature flag - i +Indicates the CPUID feature flag required to identify the support for the instruction. CPUID feature flags are defined inside the cpuid.dat flag. The CPUID feature flags defined in the cpuid.dat flag can then be specified to the i directive. + +### Valid operating modes - m +This indicates what modes the instruction is valid in. The modes are defined inside the modes.dat file, and can then be used with the m directive. +NOTE: The mode can be specified inline inside the m directive as well. + +### Flags access - f +This indicates the per flag access of the instruction. The flags access are defined inside the flags.dat file, and can then be used with the f directive. +NOTE: The flags access can be specified inline inside the f directive as well. + +### EVEX tuple type - l +Specifies the EVEX tuple type. Please refer to valid_tuples inside disasmlib.py for more info. + +### EVEX exception class - e +Specifies the EVEX exception class, as defined by Intel. + +### FPU flags access - u +Indicates the access type for the FPU status word flags C0, C1, C2, C3. Applicable to x87 instructions only. Each flag can be: +- 0 - cleared to 0 +- 1 - set to 1 +- m - modified according to a result +- u - undefined or unaffected +Specification syntax is similar to the regular flags: "u:C0=m|C1=u|C2=0|C3=1". Missing flags will be undefined by default. + +## Important files + +The instructions folder contains all the relevant files: + +- table_* - contain the actual instruction encodings. +- cpuid.dat - contains the CPUID feature flags used by the instructions. +- modes.dat - contains the valid operating modes used by the instructions. +- flags.dat - contains the flags access for the instructions. + +Generic example: + +``` +Mnemonic Op1,Op2 Op3 [encoding] s:SET, t:TYPE, c:CLASS, p:PREFIXES, w:R|R|R|R|R, f:CF=m, i:CPUID + +Anatomy of an instruction specifier: +Mnemonic Explicit ops Implicit ops Encoding Attributes +CMPXCHG Eb,Gb AL,Fv [ 0x0F 0xB0 /r] s:I486REAL, t:SEMAPHORE, w:RCW|R|RCW|W, f:ARITH, p:LOCK|HLE + A A A A A A A A A A A A A + | | | | | | | | | | | | | + | | | | | | | | | | | | | + | | | | | | | | | | | | +---------- Accepted prefixes: "LOCK" and "HLE" + | | | | | | | | | | | +------------------- Instruction flags operation: arithmetic class + | | | | | | | | | | +---------------------------------- Operand access map: operand 1 (Eb) is read, but conditionally written + | | | | | | | | | | operand 2 (Gb) is read + | | | | | | | | | | operand 3 (AL) is read and conditionally written + | | | | | | | | | | operand 4 (Fv) is written + | | | | | | | | | +----------------------------------------------- Instruction type: "SEMAPHORE" + | | | | | | | | +----------------------------------------------------------- Instruction set: "I486REAL" + | | | | | | | +---------------------------------------------------------------------------- The instruction has a modrm byte following + | | | | | | +--------------------------------------------------------------------------------- Second opcode is "0xB0" + | | | | | +-------------------------------------------------------------------------------------- First opcode is "0x0F" + | | | | +--------------------------------------------------------------------------------------------------------------- Implicit operand 2: the RFLAGS register + | | | +------------------------------------------------------------------------------------------------------------------ Implicit operand 1: the 8 bit register "AL" + | | +----------------------------------------------------------------------------------------------------------------------------- Explicit operand 2: "G" = general purpose register encoded in modrm.reg + | | "b" = 1 byte in size + | +-------------------------------------------------------------------------------------------------------------------------------- Explicit operand 1: "E" = general purpose register or memory, encoded in modrm.rm, + | "b" = 1 byte in size + +-------------------------------------------------------------------------------------------------------------------------------------------- The instruction mnemonic: "CMPXCHG" +``` \ No newline at end of file diff --git a/isagenerator/disasmlib.py b/isagenerator/disasmlib.py new file mode 100644 index 0000000..df4681b --- /dev/null +++ b/isagenerator/disasmlib.py @@ -0,0 +1,1349 @@ +# +# Copyright (c) 2020 Bitdefender +# SPDX-License-Identifier: Apache-2.0 +# +import os +import sys +import re +import glob + + +valid_attributes = { + 'MODRM', # Mod r/m is present. + 'II64', # Instruction invalid in 64 bit mode. + 'F64', # Operand size forced to 64 bit. + 'D64', # Operand size defaults to 64 bit. + 'O64', # Instruction valid only in 64 bit mode. + 'SSECONDB', # Instruction has condition byte. + 'COND', # Instruction has predicated encoded in lower 4 bit of the opcode. + 'VSIB', # Instruction uses VSIB addressing. + 'MIB', # Instruction uses MIB addressing. + 'LIG', # *vex.L is ignored. + 'WIG', # *vex.W is ignored. + '3DNOW', # Instruction uses 3dnow encoding. + 'MMASK', # Instruction must have mask specified (mask cannot be k0). + 'NOMZ', # Zeroing not allowed with memory addressing. + 'LOCKSP', # Special lock - MOV CR on amd can use LOCK to access CR8 in 32 bit mode. + 'NOL0', # Vector length 128 not supported. + 'NOA16', # 16 bit addressing not supported. + 'NO66', # 0x66 prefix causes #UD. + 'NORIPREL', # RIP relative addressing not supported. + 'VECT', # Vector instruction. + 'S66', # 0x66 prefix changes length even if it is in special map (66, f2, f3). + 'BITBASE', # Instruction uses bitbase addressing. + 'AG', # Instruction uses address generation, no memory access. + 'SHS', # Instruction accesses the shadow stack. + 'MFR', # The Mod inside Mod R/M is forced to register. No SIB/disp present. + 'CETT', # Instruction is CET tracked. + 'OP1DEF', # Operand 1 is default (implicit). + 'OP2DEF', # Operand 2 is default (implicit). + 'OP2SEXO1', # Operand 2 is sign-extended to the size of the first operand. + 'OP3SEXO1', # Operand 3 is sign-extended to the size of the first operand. + 'OP1SEXDW', # Operand 1 is sign-extended to the size of the default word. + 'PREFIX', # Prefix. + 'SERIAL', # Instruction is serializing. + 'SIBMEM', # Instruction uses sibmem addressing (AMX instructions). +} + +# +# Explicit operands types. +# +valid_optype = [ + 'A', # Direct address: the instruction has no ModR/M byte; the address of the + # operand is encoded in the instruction. No base register, index register, + # or scaling factor can be applied (for example, far JMP (EA)). + 'B', # The VEX.vvvv field of the VEX prefix selects a general purpose register. + 'C', # The reg field of the ModR/M byte selects a control register (for example, + # MOV (0F20, 0F22)). + 'D', # The reg field of the ModR/M byte selects a debug register (for example, + # MOV (0F21,0F23)). + 'E', # A ModR/M byte follows the opcode and specifies the operand. The operand + # is either a general-purpose register or a memory address. If it is a + # memory address, the address is computed from a segment register and any + # of the following values: a base register, an index register, a scaling + # factor, a displacement. + 'F', # EFLAGS/RFLAGS Register. + 'G', # The reg field of the ModR/M byte selects a general register (for example, + # AX (000)). + 'H', # The VEX.vvvv field of the VEX prefix selects a 128-bit XMM register or a + # 256-bit YMM register, determined by operand type. For legacy SSE + # encodings this operand does not exist, changing the instruction to + # destructive form. Addition: 512 bit ZMM register may also be selected in + # EVEX encodings. + 'I', # Immediate data: the operand value is encoded in subsequent bytes of the + # instruction. + 'J', # The instruction contains a relative offset to be added to the instruction + # pointer register (for example, JMP (0E9), LOOP). + 'K', # The operand is the stack. + 'L', # The upper 4 bits of the 8-bit immediate selects a 128-bit XMM register + # or a 256-bit YMM register, determined by operand type. (the MSB is + # ignored in 32-bit mode). Addition: a 512 bit ZMM register may also be + # selected using EVEX encoding. + 'M', # The ModR/M byte may refer only to memory (for example, BOUND, LES, LDS, + # LSS, LFS, LGS, CMPXCHG8B). + 'N', # The R/M field of the ModR/M byte selects a packed-quadword, MMX + # technology register. + 'O', # The instruction has no ModR/M byte. The offset of the operand is coded + # as a word or double word (depending on address size attribute) in the + # instruction. No base register, index register, or scaling factor can be + # applied (for example, MOV (A0-A3)). + 'P', # The reg field of the ModR/M byte selects a packed quadword MMX technology + # register. + 'Q', # A ModR/M byte follows the opcode and specifies the operand. The operand + # is either an MMX technology register or a memory address. If it is a + # memory address, the address is computed from a segment register and any + # of the following values: a base register, an index register, a scaling + # factor, and a displacement. + 'R', # The R/M field of the ModR/M byte may refer only to a general register + # (for example, MOV (0F20-0F23)). + 'S', # The reg field of the ModR/M byte selects a segment register (for example, MOV (8C,8E)). + 'T', # The reg field of the ModR/M byte selects a test register (for example, MOV (0F24, 0F26)). + 'U', # The R/M field of the ModR/M byte selects a 128-bit XMM register or a 256-bit YMM register, + # determined by operand type. Addition: a 512-bit ZMM register may also be selected using EVEX + # encodings. + 'V', # The reg field of the ModR/M byte selects a 128-bit XMM register or a 256-bit YMM register, + # determined by operand type. Addition: a 512-bit ZMM register may also be selected using + # EVEX encodings. + 'W', # A ModR/M byte follows the opcode and specifies the operand. The operand is either a 128-bit + # XMM register, a 256-bit YMM register (determined by operand type), or a memory address. If it is + # a memory address, the address is computed from a segment register and any of the following values: + # a base register, an index register, a scaling factor, and a displacement. Addition:a 512-bit ZMM + # register may also be selected # using EVEX encodings. + 'X', # Memory addressed by the DS:rSI register pair (for example, MOVS, CMPS, OUTS, or LODS). + 'Y', # Memory addressed by the ES:rDI register pair (for example, MOVS, CMPS, INS, STOS, or SCAS). + 'Z', # The low 3 bits inside the opcode select a general purpose register. R field inside REX may + # extend it. + 'rB', # The reg field selects a BND register. + 'mB', # The rm field selects A BND register or a memory location. + 'rK', # The reg field selects a mask register. + 'vK', # The vvvv field of the VEX prefix selects a mask register. + 'mK', # The rm field selects e mask register. + 'aK', # The aaa field inside evex selects a mask register which is used for masking of a destination + # operand. + 'rM', # The reg field inside modrm encodes the base address of a memory operand. Default segment is ES. + 'mM', # The rm field inside modrm encodes the base address of a memory operand, iregardless of the mod + # fields. Default segment is DS. + 'rT', # The reg field inside modrm encodes a TMM register (AMX extension). + 'mT', # The rm field inside modrm encodes a TMM register (AMX extension). + 'vT', # The v field inside vex encodes a TMM register (AMX extension). +] + +# Operand sizes. +valid_opsize = [ + 'a', # Two one-word operands in memory or two double-word operands in memory, + # depending on operand-size attribute (used only by the BOUND instruction). + 'b', # Byte, regardless of operand-size attribute. + 'c', # Byte or word, depending on operand-size attribute. + 'd', # Doubleword, regardless of operand-size attribute. + + 'dq', # Double-quadword, regardless of operand-size attribute (XMM register or + # 128 bit memory location). A smaller quantity from the 128 bit register may be accessed. + + 'e', # eighth = word or dword or qword. + 'f', # fourth = dword or qword or oword. + 'h', # half = qword or oword or yword. + 'n', # normal = 128, 256 or 512 bits, depending on vector length. + 'u', # 256 or 512 bit, depending on vector length. + + # VSIB addressing + 'vm32x', # VSIB addressing, using DWORD indices in XMM register, select 32/64 bit. + 'vm32y', # VSIB addressing, using DWORD indices in YMM register, select 32/64 bit. + 'vm32z', # VSIB addressing, using DWORD indices in ZMM register, select 32/64 bit. + 'vm32h', # VSIB addressing, using DWORD indices in half register, select 32/64 bit. + 'vm32n', # VSIB addressing, using DWORD indices in normal register, select 32/64 bit. + 'vm64x', # VSIB addressing, using QWORD indices in XMM register, select 32/64 bit. + 'vm64y', # VSIB addressing, using QWORD indices in YMM register, select 32/64 bit. + 'vm64z', # VSIB addressing, using QWORD indices in ZMM register, select 32/64 bit. + 'vm64h', # VSIB addressing, using QWORD indices in half register, select 32/64 bit. + 'vm64n', # VSIB addressing, using QWORD indices in normal register, select 32/64 bit. + + # MIB addressing + 'mib', # MIB addressing, the base & the index are used to form a pointer. + + # Stack sizes and partial access + 'v2', # Two stack words. + 'v3', # Three stack words. + 'v4', # Four stack words. + 'v8', # Eight stack words. + + # These are aliased over 'dq.*' encodings. + 'o', # Always 128 bits/2 QWORDs. Same as 'dq'. + 'oq', # 512 bit regardless the operand size/vector length. + 'p', # 32, 48 or 80 bits pointer, depending on operand size. + 'pd', # 128 bit or 256 bit double-precision fp data. + 'ps', # 128 bit or 256 bit single-prevision fp data. + 'q', # Always 1 QWORD. + 'qq', # Always 4 QWORDs. + 's', # 6-byte or 10-byte pseudo-descriptor. + 'sd', # Scalar element of 128 bit double-precision fp data. + 'ss', # Scalar element of 128 bit single-precision fp data. + 'v', # WORD, DWORD or QWORD, depending on operand size. + 'w', # Always WORD. + 'x', # 128 bit, 256 bit, depending on operand size. + 'y', # DWORD or QWORD, depending on operand size. + 'yf', # Always QWORD in 64 bit mode and DWORD in 16/32 bit mode. + 'z', # WORD for 16 bit op size, DWORD for 32 & 64 bit operand size. + '?', # Unknown operand size. Depends on many factors (for example, XSAVE). + '0', # Used for instructions that do not actually access any memory. + 'asz', # The size of the operand is given by the current addressing mode. + 'ssz', # The size of the operand is given by the current stack mode. + 'fa', # FPU integer binary coded decimal. + 'fw', # FPU real word. + 'fd', # FPU real dword. + 'fq', # FPU real qword. + 'ft', # FPU real extended. + 'fe', # FPU environment. + 'fs', # FPU state. + 'l', # Either a 64 bit or a 128 bit operand size (used by BNDMOV). + 'rx', # 512 bytes extended state. + 'cl', # 32/64/128 bytes - the size of one cache line. + 't', # A tile register. The size varies dependning on execution environment, but can be as high as 1K. +] + +# Implicit/fixed operands. Self explanatory. +valid_impops = {# register size + 'AH' : ('AH', 'b'), # AH register. + 'AL' : ('rAX', 'b'), # AL register. + 'AX' : ('rAX', 'w'), # AX register. + 'EAX' : ('rAX', 'd'), # EAX register. + 'RAX' : ('rAX', 'q'), # RAX register. + 'eAX' : ('rAX', 'z'), # AX or EAX register, depending on op size. + 'rAX' : ('rAX', 'v'), # AX, EAX or RAX register, depending on op size. + 'yAX' : ('rAX', 'y'), # EAX or RAX register, depending on op size. + 'CL' : ('rCX', 'b'), # CL register. + 'ECX' : ('rCX', 'd'), # ECX register. + 'RCX' : ('rCX', 'q'), # RCX register. + 'eCX' : ('rCX', 'z'), # CX or ECX register. + 'rCX' : ('rCX', 'v'), # CX, ECX or RCX register, depending on op size. + 'yCX' : ('rCX', 'y'), # ECX or RCX register, depending on op size. + 'aCX' : ('rCX', 'asz'), # CX, ECX or RCX register, depedning on address size. + 'DX' : ('rDX', 'w'), # DX register. + 'EDX' : ('rDX', 'd'), # EDX register. + 'RDX' : ('rDX', 'q'), # RDX register. + 'eDX' : ('rDX', 'z'), # DX or EDX register, depending on op size. + 'rDX' : ('rDX', 'v'), # DX, EDX or RDX register, depending on op size. + 'yDX' : ('rDX', 'y'), # EDX or RDX register, depending on op size. + 'EBX' : ('rBX', 'd'), # EBX register. + 'RBX' : ('rBX', 'q'), # RBX register. + 'rBX' : ('rBX', 'v'), # BX, EBX or RBX register, depending on op size. + 'yBX' : ('rBX', 'y'), # EBX or RBX register, depending on op size. + 'rBP' : ('rBP', 'v'), # BP, EBP or RBP register, depending on op size. + 'sBP' : ('rBP', 'ssz'), # BP, EBP or RBP register, depending on stack size. + 'rSP' : ('rSP', 'v'), # SP, ESP or RSP register, depending on op size. + 'sSP' : ('rSP', 'ssz'), # SP, ESP or RSP register, depending on stack size. + 'aSI' : ('rSI', 'asz'), # SI, ESI, or RSI register, depending on address size. + 'aDI' : ('rDI', 'asz'), # DI, EDI, or RDI register, depending on address size. + 'R11' : ('rR11', 'q'), # R11 register. + 'rIP' : ('rIP', 'v'), # IP, EIP or RIP, depending on op size. + '1' : ('1', 'b'), # Constant 1. + 'XMM0' : ('XMM0', 'dq'), # XMM0 register. + 'ST(0)' : ('ST(0)', 'ft'), # ST(0) register. + 'ST(i)' : ('ST(i)', 'ft'), # ST(1) register. + 'CS' : ('CS', 'v'), # CS register. + 'SS' : ('SS', 'v'), # SS register. + 'DS' : ('DS', 'v'), # DS register. + 'ES' : ('ES', 'v'), # ES register. + 'FS' : ('FS', 'v'), # FS register. + 'GS' : ('GS', 'v'), # GS register. + 'CR0' : ('CR0', 'yf'), # CR0 register. + 'XCR' : ('XCR', 'q'), # An XCR register. + 'XCR0' : ('XCR0', 'q'), # XCR0 register. + 'MSR' : ('MSR', 'q'), # A MSR. + 'TSC' : ('TSC', 'q'), # TSC register. + 'TSCAUX' : ('TSCAUX', 'q'), # TSXAUX register. + 'SCS' : ('SCS', 'q'), # IA32_SYSNETER_CS register. + 'SEIP' : ('SEIP', 'q'), # IA32_SYSENTER_EIP register. + 'SESP' : ('SESP', 'q'), # IA32_SYSENTER_ESP register. + 'FSBASE' : ('FSBASE', 'q'), # IA32_FS_BASE register. + 'GSBASE' : ('GSBASE', 'q'), # IA32_GS_BASE register. + 'KGSBASE' : ('KGSBASE', 'q'), # IA32_KERNEL_GS_BASE register. + 'STAR' : ('STAR', 'q'), # IA32_STAR register. + 'LSTAR' : ('LSTAR', 'q'), # IA32_LSTAR register. + 'FMASK' : ('FMASK', 'q'), # IA32_FMASK register. + 'GDTR' : ('GDTR', 's'), # GDT register. + 'IDTR' : ('IDTR', 's'), # IDT register. + 'LDTR' : ('LDTR', 'w'), # LDT register. + 'TR' : ('TR', 'w'), # Task register. + 'BANK' : ('BANK', '?'), # A register bank. + 'X87CONTROL':('X87CONTROL', 'w'), # X87 control register. + 'X87TAG' : ('X87TAG', 'w'), # X87 tag register. + 'X87STATUS': ('X87STATUS', 'w'), # X87 status register. + 'MXCSR' : ('MXCSR', 'd'), # MXCSR register. + 'PKRU' : ('PKRU', 'd'), # PKRU register. + 'SSP' : ('SSP', 'y'), # Shadow stack pointer. + + # Implicit memory operands. + 'pBXALb' : ('pBXAL', 'b'), # Implicit [RBX + AL], as used by XLAT. + 'pDIq' : ('pDI', 'q'), # Implicit qword [RDI]. + 'pDIdq' : ('pDI', 'dq'), # Implicit xmmword [RDI]. + 'SHS' : ('SHS', 'v'), # Shadow stack access, 1 word. + 'SHS2' : ('SHS', 'v2'), # Shadow stack, 2 words. + 'SHS3' : ('SHS', 'v3'), # Shadow stack, 3 words. + 'SHS4' : ('SHS', 'v4'), # Shadow stack, 4 words. +} + +# If an operand type is not present here, than that operand is implicit & it's not encoded inside the instruction. +operand_encoding = { + 'A' : 'D', # Immediate, encoded directly in the instruction bytes. + 'B' : 'V', # VEX/EVEX.vvvv encoded general purpose register. + 'C' : 'R', # Modrm.reg encoded control register. + 'D' : 'R', # Modrm.reg encoded debug register. + 'E' : 'M', # Modrm.rm encoded general purpose register or memory. + 'G' : 'R', # Modrm.reg encoded general purpose register. + 'H' : 'V', # VEX/EVEX.vvvv encoded vector register. + 'I' : 'I', # Immediate, encoded directly in the instruction bytes. + 'J' : 'D', # Relative offset, encoded directly in the instruction bytes. + 'L' : 'L', # Register encoded in an immediate. + 'M' : 'M', # Modrm.rm encoded memory. + 'N' : 'M', # Modrm.rm encoded MMX register. + 'O' : 'D', # Absolute memory encoded directly in the instruction. + 'P' : 'R', # Modrm.reg encoded MMX register. + 'Q' : 'M', # Modrm.rm encoded MMX register or memory. + 'R' : 'M', # Modrm.rm encoded general purpose register. + 'S' : 'R', # Modrm.reg encoded segment register. + 'T' : 'R', # Modrm.reg encoded test register. + 'U' : 'M', # Modrm.rm encoded vector register. + 'V' : 'R', # Modrm.reg encoded vector register. + 'W' : 'M', # Modrm.rm encoded vector register or memory. + 'Z' : 'O', # General purpose register encoded in opcode low 3 bit. + 'rB' : 'R', # Modrm.reg encoded bound register. + 'mB' : 'M', # Modrm.rm encoded bound register or memory. + 'rK' : 'R', # Modrm.reg encoded mask register. + 'vK' : 'V', # VEX/EVEX.vvvv encoded mask register. + 'mK' : 'M', # Modrm.rm encoded mask register or memory. + 'aK' : 'A', # EVEX.aaa encoded mask register. + 'mR' : 'R', # Modrm.reg encoded memory. + 'mM' : 'M', # Modrm.rm encoded memory (always). + '1' : '1', # Constant 1. + 'CL' : 'C', # CL register. + 'ST(i)' : 'M', # Modrm.rm encoded FPU register. +} + +valid_prefixes = [ + 'REP', # Rep prefix is accepted. + 'REPC', # Conditional rep prefix is accepted. + 'HLE', # Hardware Lock Elision accepted. + 'BND', # Bound prefix accepted (MPX). + 'LOCK', # Lock prefix accepted. + 'BH', # Branch hints accepted. + 'XACQUIRE', # Xacquire prefix accepted. + 'XRELEASE', # Xrelease prefix accepted. + 'HLEWOL', # HLE prefix is accepted without lock - used by MOV instructions. + 'DNT', # Do Not Track prefix accepted (CET). +] + +valid_access = [ + 'N', # No access. + 'R', # Read. + 'W', # Write. + 'CR', # Conditional read. + 'CW', # Conditional write. + 'RW', # Read-Write. + 'CRW', # Conditional Read-Write. + 'RCW', # Read-Conditional Write. + 'CRCW', # Conditional Read-Conditional Write. +] + +valid_flags = [ + 'CF', # Carry. + 'PF', # Parity. + 'AF', # Auxiliary. + 'ZF', # Zero. + 'SF', # Sign. + 'TF', # Trap. + 'IF', # Interrupt. + 'DF', # Direction. + 'OF', # Overflow. + 'IOPL', # I/O privilege level. + 'NT', # Nested Task. + 'RF', # Resume Flag. + 'VM', # V8086 mmode. + 'AC', # Alignment Check. + 'VIF', # Virtual IF. + 'VIP', # Virtual IP. + 'ID' # CPUID ID flag. +] + +valid_flag_op = [ + 'm', # modified. + 't', # tested. + '0', # cleared. + '1', # set. + 'u', # undefined. + 'n', # not accessed. +] + +valid_cpu_modes = [ + 'r0', # Ring 0. + 'r1', # Ring 1. + 'r2', # Ring 2. + 'r3', # Ring 3. + 'real', # Real mode. + 'v8086', # V8086 mode. + 'prot', # Protected mode. + 'compat', # Compatibility mode. + 'long', # Long mode. + 'smm', # System Management Mode. + 'sgx', # Software Guard Extensions SGX enclave. + 'tsx', # Transactional Synchronization Extensions. + 'vmxr', # VMX root. + 'vmxn', # VMX non-root. + 'vmxo', # Outside VMX operation. +] + +valid_mode_groups = [ + "ring", + "mode", + "vmx", + "other", +] + +valid_ring_modes = [ + "r0", + "r1", + "r2", + "r3", +] + +valid_mode_modes = [ + "real", + "smm", + "v8086", + "prot", + "compat", + "long", +] + +valid_vmx_modes = [ + "vmxr", + "vmxn", + "vmxo", +] + +valid_other_modes = [ + "sgx", + "tsx", +] + +valid_mode_map = { + "ring" : valid_ring_modes, + "mode" : valid_mode_modes, + "vmx" : valid_vmx_modes, + "other" : valid_other_modes, +} + + +valid_decorators = [ + '{K}', # Masking support. + '{z}', # Zeroing support. + '{sae}', # Surpress All Exceptions. + '{er}', # Embedded Rounding. + '|B32', # Broadcast 32. + '|B64', # Broadcast 64. +] + +valid_tuples = [ + 'fv', # Full Vector, Load+Op (Full Vector Dword/Qword). + 'hv', # Half Vector, Load+Op (Half Vector). + 'fvm', # Full Vector Memory, Load/store or subDword full vector. + 'hvm', # Half Vector Memory, SubQword Conversion. + 'qvm', # Quarter Vector Memory, SubDword Conversion. + 'ovm', # Oct Vector Memory, SubWord Conversion. + 'dup', # Dup, VMOVDDUP. + 'm128', # Mem 128, Shift count from memory. + 't1s8', # Tuple 1 Scalar, 8 bit, 1Tuple less than Full Vector. + 't1s16', # Tuple 1 Scalar, 16 bit, 1Tuple less than Full Vector. + 't1s', # Tuple 1 Scalar, 32/64 bit, 1Tuple less than Full Vector. + 't1f', # Tuple 1 Fixed, 1 Tuple memsize not affected by EVEX.W. + 't2', # Tuple 2, Broadcast (2 elements). + 't4', # Tuple 4, Broadcast (4 elements). + 't8', # Tuple 8, Broadcast (8 elements). + 't1_4x', +] + +class InvalidEncodingException(Exception): + def __init__(self, value): + self.value = value + + def __str__(self): + return repr(self.value) + +class ParseLineException(Exception): + def __init__(self, value): + self.value = value + + def __str__(self): + return repr(self.value) + + +def reverse_dict(d): + r = {} + for k in d: + r[d[k]] = k + return r + +def my_str(x): + if x is None: + return x + else: + return str(x) + + +# +# CPUID feature flags. +# +class CpuidFeatureFlag(): + def __init__(self, finfo): + self.Name = finfo["name"] + self.Leaf = finfo["leaf"] + self.SubLeaf = finfo["subleaf"] + self.Reg = finfo["reg"] + self.Bit = finfo["bit"] + + def __str__(self): + return "%s: %s, %s, %s, %s" % (self.Name, self.Leaf, self.SubLeaf, self.Reg, self.Bit) + + +# +# Operand description +# +class Operand(): + def __init__(self, op, access, flags, imp = False): + self.Raw = op + self.Type = 0 + self.Size = 0 + self.Flags = flags + self.Decorators = [] + self.Access = [] + self.Block = 0 + self.Encoding = 'S' + self.Implicit = imp + orig = op + + # Handle block registers. + if op.endswith('+3'): + self.Block = 4 + op = op.replace('+3', '') + elif op.endswith('+1'): + self.Block = 2 + op = op.replace('+1', '') + + # Handle the decorators. + for dec in valid_decorators: + if -1 != op.find(dec): + # Found decorator. + self.Decorators.append(dec) + # Remove it from the opstring. + op = op.replace(dec, "") + + # Handle hard-coded operators - those that are implicit/are not encoded anywhere. + if op in valid_impops: + self.Type, self.Size = valid_impops[op][0], valid_impops[op][1] + # Now handle explicit operators. + else: + # Attempt a match inside the explicit operands map. + for opt in valid_optype: + if op.startswith(opt): + self.Type = opt + op = op.replace(opt, "") + break + + # Now the operand size. After parsing the decorator and the operand type, we should be left with + # the operand size only. + if self.Type in ['rK', 'mK', 'vK', 'aK'] and not op in valid_opsize: + self.Size = 'q' + elif op in valid_opsize: + self.Size = op + else: + raise InvalidEncodingException('Invalid operand size specified: ' + orig) + + if self.Type in operand_encoding: + self.Encoding = operand_encoding[self.Type] + elif self.Raw in operand_encoding: + self.Encoding = operand_encoding[self.Raw] + + if imp and 'OPDEF' not in self.Flags: + self.Flags.append('OPDEF') + + self.Access = access + + def __str__(self): + if True: + return self.Raw + + +# +# Prefixes. +# +class Prefix(): + def __init__(self, prefix): + self.Mnemonic = prefix["mnemonic"] + self.Encoding = prefix["encoding"] + + def __str__(self): + return self.Mnemonic + + +# +# Instructions. +# +class Instruction(): + def __init__(self, iinfo): + # Fill in raw instruction information + self.Mnemonic = iinfo["mnemonic"] + self.RawEnc = iinfo["encoding"] + self.Flags = iinfo["flags"] + self.Prefmap = iinfo["prefixes"] + self.Set = iinfo["set"] + self.Category = iinfo["cat"] + self.Class = iinfo["class"] + self.Rwm = iinfo["rwm"] + self.Id = iinfo["cff"] or self.Set + self.Tuple = iinfo["tuple"] + self.ExClass = iinfo["exclass"] + self.RevFlagsAccess = iinfo["flgaccess"] + self.Modes = iinfo["modes"] + self.FpuFlags = iinfo["fpuflg"] + + # First redirecton class: opcodes + self.Opcodes = [] + self.Prefixes = [] + self.DecoFlags = [] + # Second redirection class: Modrm + self.HasModrm = self.ModrmRedirAfterMpref = False + self.Mod = self.Reg = self.Rm = None + # Third redirection class: mandatory prefix. + self.Np = self.MustHave66 = self.MustHaveF2 = self.MustHaveF3 = False + # Fourth redirection class: operating mode + self.RedM16 = self.RedM32 = self.RedM64 = False + # Fifth redirection class: default operand size + self.RedDs16 = self.RedDs32 = self.RedDs64 = self.RedDDs64 = self.RedFDs64 = False + # Sixth redirection class: default address size + self.RedAs16 = self.RedAs32 = self.RedAs64 = False + # Seventh redirecton class: rex, rex.w, rep, repz + self.RedRex = self.RedRexW = self.RedRep = self.Red64 = self.RedF3 = False + # Misc - vendor + self.Vendor = None + + # XOP, VEX and EVEX classes. + self.Vex = self.Xop = self.Evex = self.Mvex = False + self.M = self.P = self.L = self.W = None + + # Now parse each info chunk and extract the actual data + for t in iinfo["encoding"].split(' '): + if '0x66' == t and not self.Opcodes and not (self.Xop or self.Vex or self.Evex): + self.Prefixes.append(0x66) + self.MustHave66 = True + elif '0xF3' == t and not self.Opcodes and not (self.Xop or self.Vex or self.Evex): + self.Prefixes.append(0xF3) + self.MustHaveF3 = True + elif '0xF2' == t and not self.Opcodes and not (self.Xop or self.Vex or self.Evex): + self.Prefixes.append(0xF2) + self.MustHaveF2 = True + elif 'NP' == t: + self.Np = True + elif 'a0xF3' == t: + self.Prefixes.append(0xF3) + self.RedF3 = True + elif 'o64' == t: + self.Red64 = True + elif 'rexw' == t: + self.RedRexW = True + elif 'rex' == t: + self.RedRex = True + elif 'rep' == t: + self.RedRep = True + elif 'ds16' == t: + self.RedDs16 = True + elif 'ds32' == t: + self.RedDs32 = True + elif 'ds64' == t: + self.RedDs64 = True + elif 'dds64' == t: + self.RedDDs64 = True + elif 'fds64' == t: + self.RedFDs64 = True + elif 'as16' == t: + self.RedAs16 = True + elif 'as32' == t: + self.RedAs32 = True + elif 'as64' == t: + self.RedAs64 = True + elif t.startswith('/'): + self.HasModrm = True + self.Flags.append('MODRM') + if t.endswith(':mem'): + self.Mod = 'mem' + if t.endswith('reg'): + self.Mod = 'reg' + t = t.replace(':mem', '').replace(':reg', '') + for i in range(0, 8): + if '/%d' % i == t: + self.Reg = i + if re.match(r'0x[0-9a-fA-F]{2}', t[1:]): + mrm = int(t[1:], 16) + if 0xC0 == (mrm & 0xC0): + self.Mod = 'reg' + else: + self.Mod = 'mem' + self.Rm = mrm & 7 + self.Reg = (mrm >> 3) & 7 + elif 'modrm' == t: + self.HasModrm = True + self.Flags.append('MODRM') + elif t.startswith('mod:'): + self.Mod = t[4:] + if self.Mod not in ['mem', 'reg']: + raise InvalidEncodingException('Invalid encoding: illegal "mod" modifier') + elif t.startswith('reg:'): + self.Reg = t[4:] + if self.Reg not in ['0', '1', '2', '3', '4', '5', '6', '7']: + raise InvalidEncodingException('Invalid encoding: illegal "reg" value') + self.Reg = int(self.Reg) + elif t.startswith('rm:'): + self.Rm = t[3:] + if self.Rm not in ['0', '1', '2', '3', '4', '5', '6', '7']: + raise InvalidEncodingException('Invalid encoding: illegal "rm" value') + self.Rm = int(self.Rm) + elif t.startswith('modrmpmp'): + self.ModrmRedirAfterMpref = True + elif t == 'xop': + self.Xop = True + elif t == 'vex': + self.Vex = True + elif t == 'evex': + self.Evex = True + elif t == 'mvex': + self.Mvex = True + elif t.startswith('m:'): + self.M = t[2:] + if self.M not in ['0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C']: + raise InvalidEncodingException('Invalid encoding: illegal "mmmmm" value') + self.M = int(self.M, 16) + elif t.startswith('p:'): + self.P = t[2:] + if not self.P in ['0', '1', '2', '3']: + raise InvalidEncodingException('Invalid encoding: illegal "pp" value!') + self.P = int(self.P) + elif t.startswith('l:'): + self.L = t[2:] + if self.L == '128': + self.L = 0 + elif self.L == '256': + self.L = 1 + elif self.L == '512': + self.L = 2 + elif self.L == 'x': + self.L = None + elif self.L == 'i': + self.L = None + if 'LIG' not in self.Flags: + self.Flags.append('LIG') + elif self.L in ['0', '1', '2', '3']: + self.L = int(self.L) + else: + raise InvalidEncodingException('Invalid encoding: illegal "l" value!') + elif t.startswith('w:'): + self.W = self.RawW = t[2:] + if self.W == 'x': + self.W = None + elif self.W == 'i': + self.W = None + if 'WIG' not in self.Flags: + self.Flags.append('WIG') + elif self.W in ['0', '1']: + self.W = int(self.W) + else: + raise InvalidEncodingException('Invalid encoding: illegal "w" value!') + elif re.match(r'0x[0-9a-fA-F]{2}', t): + self.Opcodes.append(int(t, 16)) + elif t in ['intel', 'amd', 'via', 'cyrix']: + self.Vendor = t + elif 'vsib' == t: + self.HasVsib = True + if 'VSIB' not in self.Flags: + self.Flags.append('VSIB') + elif 'mib' == t: + self.HasMib = True + if 'MIB' not in self.Flags: + self.Flags.append('MIB') + elif 'bitbase' == t: + self.HasBitbase = True + if 'BITBASE' not in self.Flags: + self.Flags.append('BITBASE') + elif 'sibmem' == t: + self.HasSibMem = True + if 'SIBMEM' not in self.Flags: + self.Flags.append('SIBMEM') + elif t in ['ib', 'iw', 'iz', 'iv', 'id', 'cb', 'cz', 'cv', 'cp', 'is4']: + # Not used for now, but they must be specified, for a complete instruction encoding specification. + pass + elif t.startswith('evex.'): + tokens2 = t.split('.') + self.Evex = True + self.M = self.P = self.L = self.W = 0 + for t2 in tokens2[1:]: + # Handle the L specifier + if t2 == 'LIG': + self.L = None + if 'LIG' not in self.Flags: + self.Flags.append('LIG') + elif t2 == 'LANY': + self.L = None + elif t2 == '128' or t2 == 'LZ' or t2 == 'L0': + self.L = 0 + elif t2 == '256' or t2 == 'L1': + self.L = 1 + elif t2 == '512' or t2 == 'L2': + self.L = 2 + # Handle the W specifier + elif t2 == 'WIG': + self.W = None + if 'WIG' not in self.Flags: + self.Flags.append('WIG') + elif t2 == 'WANY': + self.W = None + elif t2 == 'W0': + self.W = 0 + elif t2 == 'W1': + self.W = 1 + # Handle compressed prefix + elif t2 == '66': + self.P = 1 + elif t2 == 'F3': + self.P = 2 + elif t2 == 'F2': + self.P = 3 + # Handle opcode map + elif t2 == '0F': + self.M = 1 + elif t2 == '0F38': + self.M = 2 + elif t2 == '0F3A': + self.M = 3 + elif t2 in ['NDS', 'NDD', 'DDS']: + pass + else: + raise InvalidEncodingException('Unknwon new evex token: %s/%s' % (t, t2)) + else: + raise InvalidEncodingException('Unknown token: %s' % t) + + # Pre-process the explicit operands. The mask register is contained as a decorator, but put it as a direct + # operand as well. The access flag is already present in rwm. + if len(iinfo["expops"]) >= 1 and iinfo["expops"][0].find("{K") > 0: + iinfo["expops"].insert(1, 'aKq') + + # Parse the explicit instruction operands. + self.ExpOps = self.process_operands(iinfo["expops"], False) + + # Parse the implicit instruction operands. + self.ImpOps = self.process_operands(iinfo["impops"], True) + + # Post-process the operands. We fill up the flags with additional info based on the operands. + for op in self.ExpOps: + for deco in op.Decorators: + self.DecoFlags.append({'{K}':'MASK', '{z}':'ZERO', '{sae}':'SAE', '{er}':'ER', '|B32':'BROADCAST', '|B64':'BROADCAST'}[deco]) + if op.Type in ['U', 'V', 'W', 'H', 'L'] and 'VECT' not in self.Flags: + self.Flags.append('VECT') + + # VEX, XOP, EVEX and MVEX instructions are not valid in real or v8086 modes. + if self.Vex or self.Xop or self.Evex or self.Mvex: + if 'real' in self.Modes: + self.Modes.remove('real') + if 'v8086' in self.Modes: + self.Modes.remove('v8086') + if 'long' not in self.Modes and 'II64' not in self.Flags: + self.Flags.append('II64') + if 'long' in self.Modes and 'prot' not in self.Modes and 'O64' not in self.Flags: + self.Flags.append('O64') + + # Split the instruction into encoding entities. + e = self.split_encoding() + if self.Vex or self.Xop or self.Evex: + self.Spec = { "mmmmm" : e[0], "opcodes" : e[1], "modrm" : e[2], "pp" : e[3], "l" : e[4], "w" : e[5] } + else: + self.Spec = { "opcodes" : e[0], "modrm" : e[1], "mpre" : e[2], "mode" : e[3], "dsize" : e[4], \ + "asize" : e[5], "opre" : e[6], "vendor" : e[7] } + + def process_operands(self, ops, imp = False): + p = 1 + res = [] + for op in ops: + if op == "nil": + break + flags = [] + if not imp: + for f in self.Flags: + if f.startswith('OP%d' % p): + flags.append('OP' + f[3:]) + self.Flags.remove(f) + else: + flags.append('OPDEF') + if not imp: + res.append(Operand(op, self.Rwm[p - 1], flags, imp)) + else: + res.append(Operand(op, self.Rwm[len(self.ExpOps) + p - 1], flags, imp)) + p += 1 + return res + + def split_encoding(self): + if self.Vex or self.Xop or self.Evex or self.Mvex: + return self.split_encoding_vex() + else: + return self.split_encoding_legacy() + + def split_encoding_vex(self): + # First, get the 'mmmmm' - VEX decoding table. + mmmmm = '%x' % self.M + # Now get the opcode. Should be only one. + opcodes = ['%02x' % x for x in self.Opcodes] + # Get the modrm redirections. + modrm = { "mod": self.Mod, "reg": my_str(self.Reg), "rm": my_str(self.Rm), "modpost": None } + # Get the pp, if any. + pp = my_str(self.P) + # Get the l, if any. + l = my_str(self.L) + # Get the w, if any. + w = my_str(self.W) + return (mmmmm, opcodes, modrm, pp, l, w) + + def split_encoding_legacy(self): + # First redirection class, the opcode. + opcodes = ['%02x' % x for x in self.Opcodes] + # Second redirection class, modrm + modrm = { "mod": self.Mod, "reg": my_str(self.Reg), "rm": my_str(self.Rm), "modpost": None } + # Third redirection class, mandatory prefixes + mprefixes = [] + if self.MustHaveF2: + mprefixes.append('F2') + if self.MustHaveF3: + mprefixes.append('F3') + if self.MustHave66: + mprefixes.append('66') + if self.Np: + mprefixes.append('NP') + if len(mprefixes) == 0 and (not (self.Xop or self.Vex or self.Evex or self.Mvex)) and\ + (self.Opcodes[0] == 0x0F and self.Opcodes[1] in [0x3A, 0x38]): + mprefixes.append(None) + # Fourth redirection class, operating mode. + mode = [] + if self.RedM16: + mode.append('m16') + elif self.RedM32: + mode.append('m32') + elif self.RedM64: + mode.append('m64') + # Fifth redirection class, default operand size. + dsize = [] + if self.RedDs16: + dsize.append('ds16') + elif self.RedDs32: + dsize.append('ds32') + elif self.RedDs64: + dsize.append('ds64') + elif self.RedDDs64: + dsize.append('dds64') + elif self.RedFDs64: + dsize.append('fds64') + # Sixth redirection class, default address size. + asize = [] + if self.RedAs16: + asize.append('as16') + elif self.RedAs32: + asize.append('as32') + elif self.RedAs64: + asize.append('as64') + # Seventh redirection class, REX prefix, REX.W, 64 bit mode, 0xF3, SIB. The important aspect here is that unlike + # the other classes, this is not exhaustive - if an instruction does not fit in any of the entries, it + # will default to index 0 (and it will not return invalid encoding, unless entry 0 is invalid). + oprefixes = [] + if self.RedRex: + oprefixes.append('rex') + if self.RedRexW: + oprefixes.append('rexw') + if self.Red64: + oprefixes.append('64') + if self.RedF3: + oprefixes.append('aF3') + if self.RedRep: + oprefixes.append('rep') + # Vendor redirection, if any. + return (opcodes, modrm, mprefixes, mode, dsize, asize, oprefixes, self.Vendor) + + + def __str__(self): + # Get the operands + ops = '' + for o in self.ExpOps: + ops += o.__str__() + ',' + ops = ops[:-1] + + # Return a text reprezentation of the encoding + return (self.Mnemonic + ' ' + ops).strip() + + + +def parse_entry(entry, template_flags = {}, template_cpuid = {}, template_modes = {}): + # make sure this is not a comment. Skip comments. + if entry.startswith('#') or len(entry) < 4: return None + + try: + # Preprocess: remove comments, CR/LF + com = entry.find('#') + x = entry.replace('\x0D', '').replace('\x0A', '') + if -1 != com: x = entry[:com] + + # Space can't be the first character. + if x[0] == ' ': + raise ParseLineException('Space cannot be the first character!') + + # Extract the mnemonic + mnemonic = x[0:x.find(' ')].strip() + + # Extract the explicit operands + x = x[x.find(' '):].strip() + expops = x[:x.find(' ')].split(',') + if len(expops) == 1 and expops[0] == 'nil': expops = [] + + # Extract the implicit operands + x = x[x.find(' '):].strip() + impops = x[:x.find(' ')].split(',') + if len(impops) == 1 and impops[0] == 'nil': impops = [] + + # Extract the encoding + x = x[x.find('[')+1:] + encoding = x[:x.find(']')].strip() + + # Extract the flags, class, set, category, encoding, prefmap + attributes = prefmap = isaset = category = iclass = adop = rwm = None + cff = tuple = flgaccess = modes = exclass = fpuflg = None + + x = x[x.find(']')+1:].strip() + + while x: + start = x.find(':') + end = x.find(',') + if start == -1: + break + if end == -1: + end = len(x) + token = x[:start].strip() + value = x[start+1:end].strip() + + # parse token + if token == 'a': # Instruction attributes. + attributes = value.split('|') + elif token == 'p': # Accepted prefixes. + prefmap = value.split('|') + elif token == 's': # Instruction set + isaset = value + elif token == 't': # Instruction type + category = value + elif token == 'c': # Instruction class. Defaults to the mnemonic if not specified. + iclass = value + elif token == 'w': # Read/write map + rwm = value.split('|') + elif token == 'i': # CPUID. + cff = value + elif token == 'l': # tuple + tuple = value + elif token == 'e': + exclass = value + elif token == 'f': # Flags access + flgaccess = [] + for v in value.split('|'): + if v in template_flags: + flgaccess += template_flags[v].split('|') + else: + flgaccess.append(v) + elif token == 'u': + fpuflg = ['u', 'u', 'u', 'u'] # each one is undefined. + for v in value.split('|'): + flg, acc = v.split('=') + if flg not in ['C0', 'C1', 'C2', 'C3']: + raise ParseLineException('Unknown FPU flag: %s' % flg) + if acc not in ['0', '1', 'm', 'u']: + raise ParseLineException('Unknown FPU flag access: %s' % acc) + fpuflg[int(flg[1])] = acc + elif token == 'm': # CPU modes. + # Example: m:ring=0,1,2,3|vmx=root,nonroot|mode=real,v8086,smm,prot,compat,long|other=sgx,tsx + # Note: any group that is not specified is considered entirely valid + # Note: any group that is specified overrides all the other fields in the group; example: + # mode=real - this means the instruction is valid ONLY in real mode. + # mode=!v8086 - this means the instructiom is valid is ANY mode except for V8086 + tmodes = [] + for t in value.split('|'): + if t in template_modes: + tmodes += template_modes[t].split('|') + else: + tmodes.append(t) + + modes = [] + groups = {} + for g in valid_mode_groups: + groups[g] = {} + groups[g]["negated"] = False + groups[g]["specified"] = False + groups[g]["modes"] = [] + + for tm in tmodes: + m, v = tm.split('=') + for vx in v.split('+'): + negated = False + if vx.startswith('!'): + vx = vx[1:] + groups[m]["negated"] = True + if m not in valid_mode_groups: + raise ParseLineException('Unknown CPU mode group specified: %s' % m) + if vx not in valid_mode_map[m]: + raise ParseLineException('Mode %s is not valid for mode group %s; it can be one of [%s]' % + (vx, m, ','.join(valid_mode_map[m]))) + groups[m]["specified"] = True + groups[m]["modes"].append(vx) + + for g in groups: + if not groups[g]["specified"]: + modes += valid_mode_map[g] + elif not groups[g]["negated"]: + modes += groups[g]["modes"] + else: + modes += [x for x in valid_mode_map[g] if x not in groups[g]["modes"]] + else: + raise ParseLineException('Unknown token specified: %s' % token) + + # Advance + if -1 == x.find(','): + x = '' + else: + x = x[x.find(',')+1:].strip() + + if attributes is None: + attributes = [] + if prefmap is None: + prefmap = [] + if isaset is None: + isaset = 'UNKNOWN' + if category is None: + category = 'UNKNOWN' + if iclass is None: + iclass = mnemonic + if rwm is None: + rwm = [] + if cff is None: + cff = None + if modes is None: + # No mode specified, assume validity in all modes. + modes = [] + modes += valid_cpu_modes + if flgaccess is None: + flgaccess = [] + if fpuflg is None: + # fpuflg[x] is for Cx (fpuflg[0] = C0, fpuflg[1] = C1, etc.) + # u = undefined, m = modified, 0 = cleared to 0, 1 = set to 1. + fpuflg = ['u', 'u', 'u', 'u'] + + # Validate the tokens. + # The set can be anything. + # The type can be anything. + # The iclass can be missing, it will default to the mnemonic. + + # The read/write map must have the same size as the number of operands. + if len(rwm) < len(expops) + len(impops): + raise ParseLineException('Invalid number of operand access specifiers: provided %d, expecting at least %d' % + (len(rwm), len(expops) + len(impops))) + for r in rwm: + if r not in valid_access: + raise ParseLineException('Unknown access specifier "%s", expecting one of [%s]' % + (r, ','.join(valid_access))) + # The CPUID can be anything, even if it doesn't match something specified in cpuid.dat. + + # The modes must be one of the valid modes. + for m in modes: + if m.startswith('!'): + m = m[1:] + if m not in valid_cpu_modes: + raise ParseLineException('Unknown CPU mode specifier "%s", expecting one of [%s]' % + (m, ','.join(valid_cpu_modes))) + + # Validate the prefixes. + for p in prefmap: + if p not in valid_prefixes: + raise ParseLineException('Unknown prefix specifier "%s", expecting one of [%s]' % + (p, ','.join(valid_prefixes))) + + # Validate the tuples. + if tuple and tuple not in valid_tuples: + raise ParseLineException('Unknown tuple specifier "%s", expecting one of [%s]' % + (tuple, ','.join(valid_tuples))) + + # Validate the attributes. + for a in attributes: + if a not in valid_attributes: + raise ParseLineException('Unknown attribute specifier "%s", expecting one of [%s]' % + (a, ','.join(valid_attributes))) + + # Validate the flags. + revflg = {} + for m in valid_flag_op: + revflg[m] = [] + for flg in flgaccess: + f, m = flg.split('=') + if m not in valid_flag_op: + raise ParseLineException('Unknow flag access specifier "%s", expecting one of [%s]' % + (m, ','.join(valid_flag_op))) + if f not in valid_flags: + raise ParseLineException('Unknow flag specifier "%s", expecting one of [%s]' % + (f, ','.join(valid_flas))) + revflg[m].append(f) + flgaccess = revflg + + iinfo = { + "mnemonic" : mnemonic, # Mnemonic + "expops" : expops, # Explicit operands + "impops" : impops, # Implicit operands + "encoding" : encoding, # Encoding + "flags" : attributes, # Instruction attributes + "prefixes" : prefmap, # Accepted prefixes + "set" : isaset, # Instruction set + "cat" : category, # Instruction category + "class" : iclass, # Instruction class + "rwm" : rwm, # Read/write operands map + "cff" : cff, # CPUID feature flag + "tuple" : tuple, # Tuple type, for EVEX instruxtions + "exclass" : exclass, # Exception class, for SSE/VEX/EVEX instructions + "flgaccess" : flgaccess, # RFLAGS access + "modes" : modes, # Valid operating modes + "fpuflg" : fpuflg, # FPU flags access (C0, C1, C2, C3), valid for x87 instructions only + } + + if 'PREFIX' in attributes: + return None + + try: + ins = Instruction(iinfo) + except: + raise + + except Exception as e: + raise + + return ins + + + +def parse_ins_file(fpath, template_flags = {}, template_cpuid = {}, template_modes = {}): + instructions = [] + lcount = 0 + for line in open(fpath, 'rt'): + lcount += 1 + try: + ins = parse_entry(line, template_flags, template_cpuid, template_modes) + if ins: instructions.append(ins) + except Exception as e: + print('ERROR: Parsing failed at %s:%d: %s' % (fpath, lcount, e)) + raise + return instructions + + + +def parse_pre_file(fpath): + prefixes = [] + for line in open(fpath, 'rt'): + # Ignore comments. + if line.startswith('#'): + continue + res = re.findall(r'([^\s]+)\s*\[\s*(0x[0-9a-fA-F]+)\]', line) + if not res: + continue + res = res[0] + pref = {} + pref["mnemonic"] = res[0] + pref["encoding"] = res[1] + prefixes.append(Prefix(pref)) + return prefixes + + + +def parse_cff_file(fpath): + features = [] + for line in open(fpath, 'rt'): + if line.startswith('#'): + continue + res = re.findall(r'([^\s]+)\s+:\s+(0x[0-9a-fA-F]+),\s+(0x[0-9a-fA-F]+),\s+(EAX|ECX|EDX|EBX),\s+(\d+)', line) + if not res: + continue + res = res[0] + cffi = {} + cffi["name"] = res[0] + cffi["leaf"] = res[1] + cffi["subleaf"] = res[2] + cffi["reg"] = res[3] + cffi["bit"] = res[4] + features.append(CpuidFeatureFlag(cffi)) + return features + + +def parse_flags_file(fpath): + flags = {} + for line in open(fpath, 'rt'): + if line.startswith('#'): + continue + res = re.findall(r'([^\s]+)\s+:([^$]+)', line) + if not res: + continue + res = res[0] + flags[res[0]] = res[1].strip('\n\r ') + return flags + + +def parse_modess_file(fpath): + modes = {} + for line in open(fpath, 'rt'): + if line.startswith('#'): + continue + res = re.findall(r'([^\s]+)\s+:([^$]+)', line) + if not res: + continue + res = res[0] + modes[res[0]] = res[1].strip('\n\r ') + return modes + + +# +# ============================================================================= +# Main +# ============================================================================= +# +if __name__ == "__main__": + if len(sys.argv) < 2: + print('Usage: %s defs-file' % os.path.basename(sys.argv[0])) + sys.exit(-1) + + # Parse the flags file. + flags = parse_flags_file('%s/flags.dat' % sys.argv[1]) + + # Parse the prefixes + prefixes = parse_pre_file('%s/prefixes.dat' % sys.argv[1]) + + # Parse the cpuid feature flags and extract each feature + features = parse_cff_file('%s/cpuid.dat' % sys.argv[1]) + + # Parse the modes file. + modes = parse_modess_file('%s/modes.dat' % sys.argv[1]) + + # Parse the instruction file and extract the instructions + instructions = [] + for fn in glob.glob('%s/table*.dat' % sys.argv[1]): + instructions += parse_ins_file(fn, flags, features) + + # Sort the instructions. + instructions = sorted(instructions, key = lambda x: x.Mnemonic) + for i in range(0, len(instructions)): + print(instructions[i]) + + for i in range(0, len(prefixes)): + print(prefixes[i]) + + features = sorted(features, key = lambda x: x.Name) + for i in range(0, len(features)): + print(features[i]) diff --git a/isagenerator/generate_tables.py b/isagenerator/generate_tables.py new file mode 100644 index 0000000..796ae9b --- /dev/null +++ b/isagenerator/generate_tables.py @@ -0,0 +1,1262 @@ +#!/usr/bin/env python3 +# +# Copyright (c) 2020 Bitdefender +# SPDX-License-Identifier: Apache-2.0 +# +import os +import sys +import re +import copy +import glob +import disasmlib + + +flags = { + 'MODRM' : 'ND_FLAG_MODRM', + 'II64' : 'ND_FLAG_I64', + 'F64' : 'ND_FLAG_F64', + 'D64' : 'ND_FLAG_D64', + 'O64' : 'ND_FLAG_O64', + 'SSECONDB' : 'ND_FLAG_SSE_CONDB', + 'COND' : 'ND_FLAG_COND', + 'VSIB' : 'ND_FLAG_VSIB', + 'MIB' : 'ND_FLAG_MIB', + 'LIG' : 'ND_FLAG_LIG', + 'WIG' : 'ND_FLAG_WIG', + '3DNOW' : 'ND_FLAG_3DNOW', + 'MMASK' : 'ND_FLAG_MMASK', + 'NOMZ' : 'ND_FLAG_NOMZ', + 'LOCKSP' : 'ND_FLAG_LOCK_SPECIAL', + 'NOL0' : 'ND_FLAG_NOL0', + 'NOA16' : 'ND_FLAG_NOA16', + 'NO66' : 'ND_FLAG_NO66', + 'NORIPREL' : 'ND_FLAG_NO_RIP_REL', + 'VECT' : 'ND_FLAG_VECTOR', + 'S66' : 'ND_FLAG_S66', + 'BITBASE' : 'ND_FLAG_BITBASE', + 'AG' : 'ND_FLAG_AG', + 'SHS' : 'ND_FLAG_SHS', + 'MFR' : 'ND_FLAG_MFR', + 'CETT' : 'ND_FLAG_CETT', + 'SERIAL' : 'ND_FLAG_SERIAL', + 'SIBMEM' : 'ND_FLAG_SIBMEM', +} + +prefixes_map = { + 'REP' : 'ND_PREF_REP', + 'REPC' : 'ND_PREF_REPC', + 'HLE' : 'ND_PREF_HLE', + 'BND' : 'ND_PREF_BND', + 'LOCK' : 'ND_PREF_LOCK', + 'BH' : 'ND_PREF_BHINT', + 'XACQUIRE' : 'ND_PREF_XACQUIRE', + 'XRELEASE' : 'ND_PREF_XRELEASE', + 'HLEWOL' : 'ND_PREF_HLE_WO_LOCK', + 'DNT' : 'ND_PREF_DNT', +} + +decorators_map = { + 'MASK' : 'ND_DECO_MASK', + 'BROADCAST': 'ND_DECO_BROADCAST', + 'ZERO' : 'ND_DECO_ZERO', + 'SAE' : 'ND_DECO_SAE', + 'ER' : 'ND_DECO_ER', +} + +# Per operand flags. +opflags = { + 'OPDEF' : 'ND_OPF_DEFAULT', # Default operand. Not encoded anywhere. + 'OPSEXO1' : 'ND_OPF_SEX_OP1', + 'OPSEXDW' : 'ND_OPF_SEX_DWS', +} + +# Explicit operands map. +optype = { + 'A' : 'ND_OPT_A', + 'B' : 'ND_OPT_B', + 'C' : 'ND_OPT_C', + 'D' : 'ND_OPT_D', + 'E' : 'ND_OPT_E', + 'F' : 'ND_OPT_F', + 'G' : 'ND_OPT_G', + 'H' : 'ND_OPT_H', + 'I' : 'ND_OPT_I', + 'J' : 'ND_OPT_J', + 'K' : 'ND_OPT_K', + 'L' : 'ND_OPT_L', + 'M' : 'ND_OPT_M', + 'N' : 'ND_OPT_N', + 'O' : 'ND_OPT_O', + 'P' : 'ND_OPT_P', + 'Q' : 'ND_OPT_Q', + 'R' : 'ND_OPT_R', + 'S' : 'ND_OPT_S', + 'T' : 'ND_OPT_T', + 'U' : 'ND_OPT_U', + 'V' : 'ND_OPT_V', + 'W' : 'ND_OPT_W', + 'X' : 'ND_OPT_X', + 'Y' : 'ND_OPT_Y', + 'Z' : 'ND_OPT_Z', + 'rB' : 'ND_OPT_rB', + 'mB' : 'ND_OPT_mB', + 'rK' : 'ND_OPT_rK', + 'vK' : 'ND_OPT_vK', + 'mK' : 'ND_OPT_mK', + 'aK' : 'ND_OPT_aK', + 'rM' : 'ND_OPT_rM', + 'mM' : 'ND_OPT_mM', + 'rT' : 'ND_OPT_rT', + 'mT' : 'ND_OPT_mT', + 'vT' : 'ND_OPT_vT', + + # Implicit operands. + '1' : 'ND_OPT_CONST_1', + 'AH' : 'ND_OPT_GPR_AH', + 'rAX' : 'ND_OPT_GPR_rAX', + 'rCX' : 'ND_OPT_GPR_rCX', + 'rDX' : 'ND_OPT_GPR_rDX', + 'rBX' : 'ND_OPT_GPR_rBX', + 'rSP' : 'ND_OPT_GPR_rSP', + 'rBP' : 'ND_OPT_GPR_rBP', + 'rSI' : 'ND_OPT_GPR_rSI', + 'rDI' : 'ND_OPT_GPR_rDI', + 'rR11' : 'ND_OPT_GPR_rR11', + 'rIP' : 'ND_OPT_RIP', + 'CS' : 'ND_OPT_SEG_CS', + 'SS' : 'ND_OPT_SEG_SS', + 'DS' : 'ND_OPT_SEG_DS', + 'ES' : 'ND_OPT_SEG_ES', + 'FS' : 'ND_OPT_SEG_FS', + 'GS' : 'ND_OPT_SEG_GS', + 'ST(0)' : 'ND_OPT_FPU_ST0', + 'ST(i)' : 'ND_OPT_FPU_STX', + 'XMM0' : 'ND_OPT_SSE_XMM0', + + # Memory operands + 'pBXAL' : 'ND_OPT_MEM_rBX_AL', + 'pDI' : 'ND_OPT_MEM_rDI', + 'SHS' : 'ND_OPT_MEM_SHS', + + # System registers, MSRs, XCRs, etc. + 'GDTR' : 'ND_OPT_SYS_GDTR', + 'IDTR' : 'ND_OPT_SYS_IDTR', + 'LDTR' : 'ND_OPT_SYS_LDTR', + 'TR' : 'ND_OPT_SYS_TR', + 'CR0' : 'ND_OPT_CR_0', + 'XCR' : 'ND_OPT_XCR', + 'XCR0' : 'ND_OPT_XCR_0', + 'MSR' : 'ND_OPT_MSR', + 'FSBASE' : 'ND_OPT_MSR_FSBASE', + 'GSBASE' : 'ND_OPT_MSR_GSBASE', + 'KGSBASE' : 'ND_OPT_MSR_KGSBASE', + 'SCS' : 'ND_OPT_MSR_SCS', + 'SEIP' : 'ND_OPT_MSR_SEIP', + 'SESP' : 'ND_OPT_MSR_SESP', + 'TSC' : 'ND_OPT_MSR_TSC', + 'TSCAUX' : 'ND_OPT_MSR_TSCAUX', + 'STAR' : 'ND_OPT_MSR_STAR', + 'LSTAR' : 'ND_OPT_MSR_LSTAR', + 'FMASK' : 'ND_OPT_MSR_FMASK', + 'BANK' : 'ND_OPT_REG_BANK', + 'X87CONTROL':'ND_OPT_X87_CONTROL', + 'X87TAG' : 'ND_OPT_X87_TAG', + 'X87STATUS': 'ND_OPT_X87_STATUS', + 'MXCSR' : 'ND_OPT_MXCSR', + 'PKRU' : 'ND_OPT_PKRU', + 'SSP' : 'ND_OPT_SSP', +} + +opsize = { + 'a' : 'ND_OPS_a', + 'b' : 'ND_OPS_b', + 'c' : 'ND_OPS_c', + 'd' : 'ND_OPS_d', + 'dq' : 'ND_OPS_dq', + 'e' : 'ND_OPS_e', + 'f' : 'ND_OPS_f', + 'h' : 'ND_OPS_h', + 'n' : 'ND_OPS_n', + 'u' : 'ND_OPS_u', + 'vm32x' : 'ND_OPS_vm32x', + 'vm32y' : 'ND_OPS_vm32y', + 'vm32z' : 'ND_OPS_vm32z', + 'vm32h' : 'ND_OPS_vm32h', + 'vm32n' : 'ND_OPS_vm32n', + 'vm64x' : 'ND_OPS_vm64x', + 'vm64y' : 'ND_OPS_vm64y', + 'vm64z' : 'ND_OPS_vm64z', + 'vm64h' : 'ND_OPS_vm64h', + 'vm64n' : 'ND_OPS_vm64n', + 'mib' : 'ND_OPS_mib', + 'v2' : 'ND_OPS_v2', + 'v3' : 'ND_OPS_v3', + 'v4' : 'ND_OPS_v4', + 'v8' : 'ND_OPS_v8', + 'oq' : 'ND_OPS_oq', + 'p' : 'ND_OPS_p', + 'pd' : 'ND_OPS_pd', + 'ps' : 'ND_OPS_ps', + 'q' : 'ND_OPS_q', + 'qq' : 'ND_OPS_qq', + 's' : 'ND_OPS_s', + 'sd' : 'ND_OPS_sd', + 'ss' : 'ND_OPS_ss', + 'v' : 'ND_OPS_v', + 'w' : 'ND_OPS_w', + 'x' : 'ND_OPS_x', + 'y' : 'ND_OPS_y', + 'yf' : 'ND_OPS_yf', + 'z' : 'ND_OPS_z', + '?' : 'ND_OPS_unknown', + '0' : 'ND_OPS_0', + 'asz' : 'ND_OPS_asz', + 'ssz' : 'ND_OPS_ssz', + 'fa' : 'ND_OPS_fa', + 'fw' : 'ND_OPS_fw', + 'fd' : 'ND_OPS_fd', + 'fq' : 'ND_OPS_fq', + 'ft' : 'ND_OPS_ft', + 'fe' : 'ND_OPS_fe', + 'fs' : 'ND_OPS_fs', + 'l' : 'ND_OPS_l', + 'rx' : 'ND_OPS_rx', + 'cl' : 'ND_OPS_cl', + 't' : 'ND_OPS_t', +} + +opdecorators = { + '{K}' : 'ND_OPD_MASK', + '{z}' : 'ND_OPD_Z', + '{sae}' : 'ND_OPD_SAE', + '{er}' : 'ND_OPD_ER', + '|B32' : 'ND_OPD_B32', + '|B64' : 'ND_OPD_B64', +} + +accessmap = { + 'R' : 'ND_OPF_R', + 'W' : 'ND_OPF_W', + 'CR' : 'ND_OPF_CR', + 'CW' : 'ND_OPF_CW', + 'RW' : 'ND_OPF_RW', + 'RCW' : 'ND_OPF_RCW', + 'CRW' : 'ND_OPF_CRW', + 'CRCW' : 'ND_OPF_CRCW', + 'N' : 'ND_OPF_N', +} + +tuples = { + None : '0', + 'fv' : 'ND_TUPLE_FV', + 'hv' : 'ND_TUPLE_HV', + 'fvm' : 'ND_TUPLE_FVM', + 'hvm' : 'ND_TUPLE_HVM', + 'qvm' : 'ND_TUPLE_QVM', + 'ovm' : 'ND_TUPLE_OVM', + 'dup' : 'ND_TUPLE_DUP', + 'm128' : 'ND_TUPLE_M128', + 't1s8' : 'ND_TUPLE_T1S8', + 't1s16' : 'ND_TUPLE_T1S16', + 't1s' : 'ND_TUPLE_T1S', + 't1f' : 'ND_TUPLE_T1F', + 't2' : 'ND_TUPLE_T2', + 't4' : 'ND_TUPLE_T4', + 't8' : 'ND_TUPLE_T8', + 't1_4x' : 'ND_TUPLE_T1_4X', +} + +extype = { + None : '0', + + # SSE/AVX + '1' : 'ND_EXT_1', + '2' : 'ND_EXT_2', + '3' : 'ND_EXT_3', + '4' : 'ND_EXT_4', + '5' : 'ND_EXT_5', + '6' : 'ND_EXT_6', + '7' : 'ND_EXT_7', + '8' : 'ND_EXT_8', + '9' : 'ND_EXT_9', + '10' : 'ND_EXT_10', + '11' : 'ND_EXT_11', + '12' : 'ND_EXT_12', + '13' : 'ND_EXT_13', + + # EVEX + 'E1' : 'ND_EXT_E1', + 'E1NF' : 'ND_EXT_E1NF', + 'E2' : 'ND_EXT_E2', + 'E3' : 'ND_EXT_E3', + 'E3NF' : 'ND_EXT_E3NF', + 'E4' : 'ND_EXT_E4', + 'E4nb' : 'ND_EXT_E4nb', + 'E4NF' : 'ND_EXT_E4NF', + 'E4NFnb': 'ND_EXT_E4NFnb', + 'E5' : 'ND_EXT_E5', + 'E5NF' : 'ND_EXT_E5NF', + 'E6' : 'ND_EXT_E6', + 'E6NF' : 'ND_EXT_E6NF', + 'E7NM' : 'ND_EXT_E7NM', + 'E9' : 'ND_EXT_E9', + 'E9NF' : 'ND_EXT_E9NF', + 'E10' : 'ND_EXT_E10', + 'E10NF' : 'ND_EXT_E10NF', + 'E11' : 'ND_EXT_E11', + 'E12' : 'ND_EXT_E12', + 'E12NP' : 'ND_EXT_E12NP', + + # Opmask + 'K20' : 'ND_EXT_K20', + 'K21' : 'ND_EXT_K21', + + # AMX + 'AMX_E1': 'ND_EXT_AMX_E1', + 'AMX_E2': 'ND_EXT_AMX_E2', + 'AMX_E3': 'ND_EXT_AMX_E3', + 'AMX_E4': 'ND_EXT_AMX_E4', + 'AMX_E5': 'ND_EXT_AMX_E5', + 'AMX_E6': 'ND_EXT_AMX_E6', +} + +modes = { + 'r0' : 'ND_MOD_R0', + 'r1' : 'ND_MOD_R1', + 'r2' : 'ND_MOD_R2', + 'r3' : 'ND_MOD_R3', + 'real' : 'ND_MOD_REAL', + 'v8086' : 'ND_MOD_V8086', + 'prot' : 'ND_MOD_PROT', + 'compat': 'ND_MOD_COMPAT', + 'long' : 'ND_MOD_LONG', + 'smm' : 'ND_MOD_SMM', + 'sgx' : 'ND_MOD_SGX', + 'tsx' : 'ND_MOD_TSX', + 'vmxr' : 'ND_MOD_VMXR', + 'vmxn' : 'ND_MOD_VMXN', + 'vmxo' : 'ND_MOD_VMXO', +} + +indexes = { + "root" : 0, + "None" : 0, + None : 0, + + # modrm.mod + "mem" : 0, + "reg" : 1, + + # mandatory prefixes + "NP" : 0, + "66" : 1, + "F3" : 2, + "F2" : 3, + + # other prefixes + "rex" : 1, + "rexw" : 2, + "64" : 3, + "aF3" : 4, + "rep" : 5, + "sib" : 6, + + # Mode + "m16" : 1, + "m32" : 2, + "m64" : 3, + + # Default data size + "ds16" : 1, + "ds32" : 2, + "ds64" : 3, + "dds64" : 4, + "fds64" : 5, + + # Default address size + "as16" : 1, + "as32" : 2, + "as64" : 3, + + # Vendor redirection. + "any" : 0, + "intel" : 1, + "amd" : 2, + "geode" : 3, + "cyrix" : 4, +} + +ilut = { + "root" : ("ND_ILUT_ROOT", 1, "ND_TABLE"), + "opcode" : ("ND_ILUT_OPCODE", 256, "ND_TABLE_OPCODE"), + "opcode_3dnow" : ("ND_ILUT_OPCODE_3DNOW", 256, "ND_TABLE_OPCODE"), + "modrmmod" : ("ND_ILUT_MODRM_MOD", 2, "ND_TABLE_MODRM_MOD"), + "modrmmodpost" : ("ND_ILUT_MODRM_MOD", 2, "ND_TABLE_MODRM_MOD"), + "modrmreg" : ("ND_ILUT_MODRM_REG", 8, "ND_TABLE_MODRM_REG"), + "modrmrm" : ("ND_ILUT_MODRM_RM", 8, "ND_TABLE_MODRM_RM"), + "mprefix" : ("ND_ILUT_MAN_PREFIX", 4, "ND_TABLE_MPREFIX"), + "mode" : ("ND_ILUT_MODE", 4, "ND_TABLE_MODE"), + "dsize" : ("ND_ILUT_DSIZE", 6, "ND_TABLE_DSIZE"), + "asize" : ("ND_ILUT_ASIZE", 4, "ND_TABLE_ASIZE"), + "auxiliary" : ("ND_ILUT_AUXILIARY", 6, "ND_TABLE_AUXILIARY"), + "vendor" : ("ND_ILUT_VENDOR", 6, "ND_TABLE_VENDOR"), + "mmmmm" : ("ND_ILUT_VEX_MMMMM", 32, "ND_TABLE_VEX_MMMMM"), + "pp" : ("ND_ILUT_VEX_PP", 4, "ND_TABLE_VEX_PP"), + "l" : ("ND_ILUT_VEX_L", 4, "ND_TABLE_VEX_L"), + "w" : ("ND_ILUT_VEX_W", 2, "ND_TABLE_VEX_W"), +} + + +mnemonics = [] +mnemonics_prefix = [] + +instructions = [] +prefixes = [] +features = [] + + +# +# Convert one operand into it's C/C++ representation. +# +def cdef_operand(self): + return "OP(%s, %s, %s, %s, %d)" % (optype[self.Type], opsize[self.Size], \ + '|'.join([opflags[x] for x in self.Flags] + [accessmap[self.Access]]) or '0', \ + '|'.join([opdecorators[x] for x in self.Decorators]) or 0, self.Block) + +disasmlib.Operand.cdef = cdef_operand + + +# +# Convert one instruction into it's C/C++ representation. +# +def cdef_instruction(self): + c = '' + + c += ' // Pos:%d Instruction:"%s" Encoding:"%s"/"%s"\n' % \ + (self.Icount, self.__str__(), self.RawEnc, ''.join([x.Encoding for x in self.ExpOps]).replace('S', '')) + + c += ' {\n ' + + # Add the instruction class + c += 'ND_INS_' + self.Class + ', ' + + # Add the instruction type + c += 'ND_CAT_' + self.Category + ', ' + + # Add the instruction set + c += 'ND_SET_' + self.Set + ', ' + + # Add the mneomonic index. + c += '%d, ' % (mnemonics.index(self.Mnemonic)) + + c += '\n ' + + + # Add the valid modes map. + all = True + for m in modes: + if m not in self.Modes: + all = False + if all: + c += 'ND_MOD_ANY, ' + else: + c += '|'.join([modes[m] for m in self.Modes]) + ', ' + + c += '\n ' + + # Add the prefixes map. + c += '|'.join([prefixes_map[x] for x in self.Prefmap] or '0') + ', ' + + # Add the decorators map. + c += '|'.join([decorators_map[x] for x in self.DecoFlags] or '0') + ', ' + + # Add the tuple type and the explicit operands count. + c += 'ND_OPS_CNT(%d, %d), ' % (len(self.ExpOps), len(self.ImpOps)) + + exclass = None + if self.ExClass: + if self.ExClass in ['0', '1', '2', '3', '4', '5', '6', '7', '8', '9', '10', '11', '12', '13']: + exclass = 'ND_EXC_SSE_AVX' + elif self.ExClass in ['K20', 'K21']: + exclass = 'ND_EXC_OPMASK' + elif self.ExClass.startswith('AMX_'): + exclass = 'ND_EXC_AMX' + else: + exclass = 'ND_EXC_EVEX' + + if self.Evex: + # EVEX encoded instructions, store the tuple type. + c += '%s, ' % (tuples[self.Tuple]) + else: + c += '0, ' + + # Store exception type & class, if any. + if exclass: + c += '%s, %s, ' % (extype[self.ExClass], exclass) + else: + c += '0, 0, ' + + # Add the FPU flags access, if the instruction is fpu. + if self.Set == 'X87': + value = 0 + acc = { '0': 0, '1': 1, 'm': 2, 'u': 3 } + for i in range(0, 4): + value |= acc[self.FpuFlags[i]] << (i * 2) + c += '0x%02x, ' % value + else: + c += '0, ' + + # The 2 reserved fields. + c += '0, 0, ' + + # Add the instruction flags + fs = '|'.join([flags[x] for x in self.Flags if x != 'nil' and not x.startswith('OP1') and not x.startswith('OP2')\ + and not x.startswith('OP3') and not x.startswith('OP4')\ + and not x.startswith('OP5') and not x.startswith('OP6')\ + ]) or 0 + + c += '%s, ' % fs + + # Store the CPUID flag, if any + flg = "0" + for feat in features: + if feat.Name == self.Id: + flg = "ND_CFF_%s" % feat.Name + c += "%s, " % flg + + # Store the accessed flags, if any. + for m in ['t', 'm', '1', '0']: + flg = "0" + dst = self.RevFlagsAccess[m] + if m == '1' or m == '0': + dst = dst + self.RevFlagsAccess['u'] + for f in dst: + flg += '|REG_RFLAG_%s' % f.upper() + c += "\n %s," % flg + + # Add the instruction operands + for op in self.ExpOps + self.ImpOps: + c += "\n " + op.cdef() + ", " + + c += '\n }' + + return c + +disasmlib.Instruction.cdef = cdef_instruction + + +# +# Initially, t is an empty hash-table. +# +def group_instructions(ilist): + d = { } + is3dnow = False + priorities = ["opcode", "vendor", "modrmmod", "modrmreg", "modrmmodpost", "modrmrm", "mprefix", "mode", "dsize", \ + "asize", "auxiliary", "_"] + + for i in ilist: + if '3DNOW' in i.Flags: + is3dnow = True + else: + is3dnow = False + + if i.Spec["opcodes"]: + if is3dnow: + d["__TYPE__"] = "opcode_3dnow" + else: + d["__TYPE__"] = "opcode" + elif i.Spec["mpre"] and i.ModrmRedirAfterMpref: + if "__TYPE__" not in d or d["__TYPE__"] in priorities[-1:]: + d["__TYPE__"] = "mprefix" + elif i.Spec["vendor"]: + if "__TYPE__" not in d or d["__TYPE__"] in priorities[-10:]: + d["__TYPE__"] = "vendor" + elif i.Spec["modrm"]["mod"]: + if "__TYPE__" not in d or d["__TYPE__"] in priorities[-9:]: + d["__TYPE__"] = "modrmmod" + elif i.Spec["modrm"]["reg"]: + if "__TYPE__" not in d or d["__TYPE__"] in priorities[-8:]: + d["__TYPE__"] = "modrmreg" + elif i.Spec["modrm"]["modpost"]: + if "__TYPE__" not in d or d["__TYPE__"] in priorities[-7:]: + d["__TYPE__"] = "modrmmodpost" + elif i.Spec["modrm"]["rm"]: + if "__TYPE__" not in d or d["__TYPE__"] in priorities[-6:]: + d["__TYPE__"] = "modrmrm" + elif i.Spec["mpre"]: + if "__TYPE__" not in d or d["__TYPE__"] in priorities[-5:]: + d["__TYPE__"] = "mprefix" + elif i.Spec["mode"]: + if "__TYPE__" not in d or d["__TYPE__"] in priorities[-4:]: + d["__TYPE__"] = "mode" + elif i.Spec["dsize"]: + if "__TYPE__" not in d or d["__TYPE__"] in priorities[-3:]: + d["__TYPE__"] = "dsize" + elif i.Spec["asize"]: + if "__TYPE__" not in d or d["__TYPE__"] in priorities[-2:]: + d["__TYPE__"] = "asize" + elif i.Spec["opre"]: + if "__TYPE__" not in d or d["__TYPE__"] in priorities[-1:]: + d["__TYPE__"] = "auxiliary" + elif len(ilist) == 1: + return ilist[0] + + + for i in ilist: + if d["__TYPE__"] in ["opcode", "opcode_3dnow"]: + # Opcode redirection, add the next opcode to the hash, and remove it from the spec. + if int(i.Spec["opcodes"][0], 16) not in d: + d[int(i.Spec["opcodes"][0], 16)] = [i] + else: + d[int(i.Spec["opcodes"][0], 16)].append(i) + + # Remove the opcode for this instruction. + del i.Spec["opcodes"][0] + elif d["__TYPE__"] == "modrmmod": + if not i.Spec["modrm"]["mod"]: + if "mem" not in d: + d["mem"] = [i] + else: + d["mem"].append(i) + + if "reg" not in d: + d["reg"] = [copy.deepcopy(i)] + else: + d["reg"].append(copy.deepcopy(i)) + else: + if i.Spec["modrm"]["mod"] not in d: + d[i.Spec["modrm"]["mod"]] = [i] + else: + d[i.Spec["modrm"]["mod"]].append(i) + # Remove the mod specifier. + i.Spec["modrm"]["mod"] = None + elif d["__TYPE__"] == "modrmreg": + if int(i.Spec["modrm"]["reg"]) not in d: + d[int(i.Spec["modrm"]["reg"])] = [i] + else: + d[int(i.Spec["modrm"]["reg"])].append(i) + # Remove the reg specifier + i.Spec["modrm"]["reg"] = None + elif d["__TYPE__"] == "modrmmodpost": + if not i.Spec["modrm"]["modpost"]: + if "mem" not in d: + d["mem"] = [i] + else: + d["mem"].append(i) + + if "reg" not in d: + d["reg"] = [copy.deepcopy(i)] + else: + d["reg"].append(copy.deepcopy(i)) + else: + if i.Spec["modrm"]["modpost"] not in d: + d[i.Spec["modrm"]["modpost"]] = [i] + else: + d[i.Spec["modrm"]["modpost"]].append(i) + # Remove the modpost specifier. + i.Spec["modrm"]["modpost"] = None + elif d["__TYPE__"] == "modrmrm": + if int(i.Spec["modrm"]["rm"]) not in d: + d[int(i.Spec["modrm"]["rm"])] = [i] + else: + d[int(i.Spec["modrm"]["rm"])].append(i) + # Remove the reg specifier + i.Spec["modrm"]["rm"] = None + elif d["__TYPE__"] == "mprefix": + if not i.Spec["mpre"]: + p = "None" + else: + p = i.Spec["mpre"][0] + if p not in d: + d[p] = [i] + else: + d[p].append(i) + # Remove the prefix from the list. + if p != "None": + del i.Spec["mpre"][0] + elif d["__TYPE__"] == "mode": + if not i.Spec["mode"]: + p = "None" + else: + p = i.Spec["mode"][0] + if p not in d: + d[p] = [i] + else: + d[p].append(i) + # Remove the auxiliary redirector + if p != "None": + del i.Spec["mode"][0] + elif d["__TYPE__"] == "dsize": + if not i.Spec["dsize"]: + p = "None" + else: + p = i.Spec["dsize"][0] + if p not in d: + d[p] = [i] + else: + d[p].append(i) + # Remove the auxiliary redirector + if p != "None": + del i.Spec["dsize"][0] + elif d["__TYPE__"] == "asize": + if not i.Spec["asize"]: + p = "None" + else: + p = i.Spec["asize"][0] + if p not in d: + d[p] = [i] + else: + d[p].append(i) + # Remove the auxiliary redirector + if p != "None": + del i.Spec["asize"][0] + elif d["__TYPE__"] == "auxiliary": + if not i.Spec["opre"]: + p = "None" + else: + p = i.Spec["opre"][0] + if p not in d: + d[p] = [i] + else: + d[p].append(i) + # Remove the auxiliary redirector + if p != "None": + del i.Spec["opre"][0] + elif d["__TYPE__"] == "vendor": + if not i.Spec["vendor"]: + p = "None" + else: + p = i.Spec["vendor"] + if p not in d: + d[p] = [i] + else: + d[p].append(i) + # Remove the vendor redirector + if p != "None": + i.Spec["vendor"] = None + else: + print("Don't know what to do!") + raise Exception("WTF???") + + return d + + + +def group_instructions_vex_xop_evex(ilist): + d = { } + + for i in ilist: + if i.Spec["mmmmm"]: + d["__TYPE__"] = "mmmmm" + elif i.Spec["opcodes"]: + if "__TYPE__" not in d or d["__TYPE__"] in ["w", "l", "pp", "modrmrm", "modrmmodpost", "modrmreg", \ + "modrmmod"]: + d["__TYPE__"] = "opcode" + elif i.Spec["pp"]: + if "__TYPE__" not in d or d["__TYPE__"] in ["w", "l", "modrmrm", "modrmmodpost", "modrmreg"]: + d["__TYPE__"] = "pp" + elif i.Spec["modrm"]["mod"]: + if "__TYPE__" not in d or d["__TYPE__"] in ["w", "l", "modrmrm", "modrmmodpost", "modrmreg"]: + d["__TYPE__"] = "modrmmod" + elif i.Spec["modrm"]["reg"]: + if "__TYPE__" not in d or d["__TYPE__"] in ["w", "l", "modrmrm", "modrmmodpost"]: + d["__TYPE__"] = "modrmreg" + elif i.Spec["modrm"]["modpost"]: + if "__TYPE__" not in d or d["__TYPE__"] in ["w", "l", "modrmrm"]: + d["__TYPE__"] = "modrmmodpost" + elif i.Spec["modrm"]["rm"]: + if "__TYPE__" not in d or d["__TYPE__"] in ["w", "l"]: + d["__TYPE__"] = "modrmrm" + + elif i.Spec["l"]: + if "__TYPE__" not in d or d["__TYPE__"] in ["w"]: + d["__TYPE__"] = "l" + elif i.Spec["w"]: + if "__TYPE__" not in d: + d["__TYPE__"] = "w" + elif len(ilist) == 1: + return ilist[0] + + + for i in ilist: + if d["__TYPE__"] == "mmmmm": + if int(i.Spec["mmmmm"], 16) not in d: + d[int(i.Spec["mmmmm"], 16)] = [i] + else: + d[int(i.Spec["mmmmm"], 16)].append(i) + i.Spec["mmmmm"] = None + elif d["__TYPE__"] == "opcode": + # Opcode redirection, add the next opcode to the hash, and remove it from the spec. + if int(i.Spec["opcodes"][0], 16) not in d: + d[int(i.Spec["opcodes"][0], 16)] = [i] + else: + d[int(i.Spec["opcodes"][0], 16)].append(i) + # Remove the opcode for this instruction. + del i.Spec["opcodes"][0] + elif d["__TYPE__"] == "modrmmod": + if not i.Spec["modrm"]["mod"]: + if "mem" not in d: + d["mem"] = [i] + else: + d["mem"].append(i) + + if "reg" not in d: + d["reg"] = [copy.deepcopy(i)] + else: + d["reg"].append(copy.deepcopy(i)) + else: + if i.Spec["modrm"]["mod"] not in d: + d[i.Spec["modrm"]["mod"]] = [i] + else: + d[i.Spec["modrm"]["mod"]].append(i) + # Remove the mod specifier. + i.Spec["modrm"]["mod"] = None + elif d["__TYPE__"] == "modrmreg": + if int(i.Spec["modrm"]["reg"]) not in d: + d[int(i.Spec["modrm"]["reg"])] = [i] + else: + d[int(i.Spec["modrm"]["reg"])].append(i) + # Remove the reg specifier + i.Spec["modrm"]["reg"] = None + elif d["__TYPE__"] == "modrmmodpost": + if not i.Spec["modrm"]["modpost"]: + if "mem" not in d: + d["mem"] = [i] + else: + d["mem"].append(i) + + if "reg" not in d: + d["reg"] = [copy.deepcopy(i)] + else: + d["reg"].append(copy.deepcopy(i)) + else: + if i.Spec["modrm"]["modpost"] not in d: + d[i.Spec["modrm"]["modpost"]] = [i] + else: + d[i.Spec["modrm"]["modpost"]].append(i) + # Remove the modpost specifier. + i.Spec["modrm"]["modpost"] = None + elif d["__TYPE__"] == "modrmrm": + if int(i.Spec["modrm"]["rm"]) not in d: + d[int(i.Spec["modrm"]["rm"])] = [i] + else: + d[int(i.Spec["modrm"]["rm"])].append(i) + # Remove the reg specifier + i.Spec["modrm"]["rm"] = None + elif d["__TYPE__"] == "pp": + p = int(i.Spec["pp"]) + if p not in d: + d[p] = [i] + else: + d[p].append(i) + # Remove the prefix from the list. + i.Spec["pp"] = None + elif d["__TYPE__"] == "l": + p = int(i.Spec["l"]) + if p not in d: + d[p] = [i] + else: + d[p].append(i) + # Remove the prefix from the list. + i.Spec["l"] = None + elif d["__TYPE__"] == "w": + p = int(i.Spec["w"]) + if p not in d: + d[p] = [i] + else: + d[p].append(i) + # Remove the prefix from the list. + i.Spec["w"] = None + else: + print("Don't know what to do!") + raise Exception("WTF???") + + return d + + +def build_hash_tree2(t, cbk): + for k in t: + if type(disasmlib.Instruction) == type(t[k]): + # Instruction, leaf, we're done. + continue + elif type([]) == type(t[k]): + # List, group the instructions, and recurse. + t[k] = cbk(t[k]) + + if type({}) == type(t[k]): + build_hash_tree2(t[k], cbk) + + +def dump_hash_tree2(t, level = 0): + if type(t) == type({}): + for h in t: + if h == "__TYPE__": + continue + print("%s %s (type: %s)" % (" " * level, h, t["__TYPE__"])) + dump_hash_tree2(t[h], level + 1) + else: + print(" " * level, t) + + +# +# +# +def generate_translations2(instructions): + table_st = [] + table_xop = [] + table_vex = [] + table_evex = [] + + hash_st = {} + hash_vex = {} + hash_xop = {} + hash_evex = {} + + # Distribute each instruction type into its own table. + for i in instructions: + if i.Vex: + table_vex.append(i) + elif i.Xop: + table_xop.append(i) + elif i.Evex: + table_evex.append(i) + else: + table_st.append(i) + + hash_st["__TYPE__"] = "root" + hash_st["root"] = table_st + build_hash_tree2(hash_st, group_instructions) + + hash_vex["__TYPE__"] = "root" + hash_vex["root"] = table_vex + build_hash_tree2(hash_vex, group_instructions_vex_xop_evex) + + hash_xop["__TYPE__"] = "root" + hash_xop["root"] = table_xop + build_hash_tree2(hash_xop, group_instructions_vex_xop_evex) + + hash_evex["__TYPE__"] = "root" + hash_evex["root"] = table_evex + build_hash_tree2(hash_evex, group_instructions_vex_xop_evex) + + # Dump'em! + #print "###########################################################################################################" + #dump_hash_tree2(hash_st) + print('Writing the table_root.h file...') + f = open(r'../bddisasm/include/table_root.h', 'wt') + f.write("#ifndef _TABLE_ROOT_H_\n") + f.write("#define _TABLE_ROOT_H_\n\n") + dump_translation_tree_c(hash_st, 'gRootTable', f) + f.write("\n#endif\n\n") + f.close() + #print "###########################################################################################################" + #dump_hash_tree2(hash_vex) + print('Writing the table_vex.h file...') + f = open(r'../bddisasm/include/table_vex.h', 'wt') + f.write("#ifndef _TABLE_VEX_H_\n") + f.write("#define _TABLE_VEX_H_\n\n") + dump_translation_tree_c(hash_vex, 'gVexTable', f) + f.write("\n#endif\n\n") + f.close() + #print "###########################################################################################################" + #dump_hash_tree2(hash_xop) + print('Writing the table_xop.h file...') + f = open(r'../bddisasm/include/table_xop.h', 'wt') + f.write("#ifndef _TABLE_XOP_H_\n") + f.write("#define _TABLE_XOP_H_\n\n") + dump_translation_tree_c(hash_xop, 'gXopTable', f) + f.write("\n#endif\n\n") + f.close() + #print "###########################################################################################################" + #dump_hash_tree2(hash_evex) + print('Writing the table_evex.h file...') + f = open(r'../bddisasm/include/table_evex.h', 'wt') + f.write("#ifndef _TABLE_EVEX_H_\n") + f.write("#define _TABLE_EVEX_H_\n\n") + dump_translation_tree_c(hash_evex, 'gEvexTable', f) + f.write("\n#endif\n\n") + f.close() + #print "###########################################################################################################" + + return [hash_st, hash_vex, hash_xop, hash_evex] + + +def generate_mnemonics(instructions): + mnemonics = [] + + for i in instructions: + mnemonics.append(i.Mnemonic) + + return sorted(set(mnemonics)) + +def generate_constants(lst, pre = False): + constants = [] + + for i in lst: + if pre: + constants.append('ND_PRE_' + i.Mnemonic) + else: + constants.append('ND_INS_' + i.Class) + + return sorted(set(constants)) + +def generate_constants2(instructions): + constants_sets, constants_types = [], [] + + for i in instructions: + constants_sets.append('ND_SET_' + i.Set) + constants_types.append('ND_CAT_' + i.Category) + + return sorted(set(constants_sets)), sorted(set(constants_types)) + +def dump_mnemonics(mnemonics, prefixes, fname): + f = open(fname, 'wt') + f.write('#ifndef _MNEMONICS_H_\n') + f.write('#define _MNEMONICS_H_\n') + f.write('\n') + f.write('const char *gMnemonics[%d] = \n' % len(mnemonics)) + f.write('{\n') + f.write(' ') + + i = 0 + ln = 0 + for m in mnemonics: + f.write('"%s", ' % m) + ln += len(m) + 4 + i += 1 + if ln > 60: + ln = 0 + f.write('\n ') + + f.write('\n};\n\n\n') + + f.write('const char *gPrefixes[%d] = \n' % len(prefixes)) + f.write('{\n') + f.write(' ') + + i = 0 + for p in prefixes: + f.write('"%s", ' % p) + i += 1 + if i % 8 == 0: + f.write('\n ') + + f.write('\n};\n\n#endif\n\n') + f.close() + +def dump_constants(constants, prefixes, constants_sets, constants_types, fname): + f = open(fname, 'wt') + f.write('//\n') + f.write('// This file was auto-generated by generate_tables.py from defs.dat. DO NOT MODIFY!\n') + f.write('//\n\n') + f.write('#ifndef _CONSTANTS_H_\n') + f.write('#define _CONSTANTS_H_\n\n') + f.write('\n') + f.write('typedef enum _ND_INS_CLASS\n') + f.write('{\n') + f.write(' ND_INS_INVALID = 0,\n') + + for c in constants: + f.write(' %s,\n' % c) + + f.write('\n} ND_INS_CLASS;\n\n\n') + + # Now the instruction sets. + f.write('typedef enum _ND_INS_SET\n') + f.write('{\n') + f.write(' ND_SET_INVALID = 0,\n') + for c in constants_sets: + f.write(' %s,\n' % c) + f.write('\n} ND_INS_SET;\n\n\n') + + # Now the instruction types. + f.write('typedef enum _ND_INS_TYPE\n') + f.write('{\n') + f.write(' ND_CAT_INVALID = 0,\n') + for c in constants_types: + f.write(' %s,\n' % c) + f.write('\n} ND_INS_CATEGORY;\n\n\n') + + # Done! + f.write('\n#endif\n') + + f.close() + +def dump_tree(translations, level = 0): + if type(translations) != type([]): + print('%s%s' % (level * ' ', translations)) + else: + for i in range(0, len(translations), 1): + if len(translations) == 1: + dump_tree(translations[i], level + 1) + else: + dump_tree(translations[i], level + 2) + +def generate_master_table(instructions, fname): + f = open(fname, 'wt') + f.write('//\n') + f.write('// This file was auto-generated by generate_tables.py from defs.dat. DO NOT MODIFY!\n') + f.write('//\n\n') + f.write('#ifndef _INSTRUCTIONS_H_\n') + f.write('#define _INSTRUCTIONS_H_\n') + f.write('\n') + flags = [] + f.write('const ND_INSTRUCTION gInstructions[%s] = \n' % len(instructions)) + f.write('{\n') + for i in instructions: + f.write('%s, \n\n' % i.cdef()) + f.write('\n};\n') + f.write('\n#endif\n') + f.close() + + +def dump_translation_tree_c(t, hname, f): + if type(t) == type({}): + pointers = [] + + ttype = t["__TYPE__"] + + for x in range(0, ilut[ttype][1]): pointers.append(None) + + tname = '%s_%s' % (hname, ttype) + + res = 'const %s %s = \n' % (ilut[ttype][2], tname) + res += '{\n' + res += ' %s,\n' % ilut[ttype][0] + res += ' { \n' + + for h in t: + if h == "__TYPE__": + continue + + if type(0) == type(h): + name = dump_translation_tree_c(t[h], hname + '_%02x' % h, f) + else: + name = dump_translation_tree_c(t[h], hname + '_%s' % h, f) + + if ttype in ["opcode", "opcode_3dnow", "mmmmm", "pp", "l", "w", "modrmreg", "modrmrm"]: + index = h + else: + index = indexes[h] + + try: + pointers[index] = name + except: + print(index, name) + print("fail fail fail", index) + + i = 0 + for p in pointers: + if not p: + res += ' /* %02x */ NULL,\n' % i + else: + res += ' /* %02x */ (const void *)&%s,\n' % (i, p) + i += 1 + + res += ' }\n' + res += '};\n\n' + + if ttype == "root": + f.write("const PND_TABLE %s = (const PND_TABLE)&%s;\n\n" % (hname, name)) + else: + f.write(res) + + return tname + else: + # Instruction, construct a dummy table that directly points to the instruction. + name = '%s_leaf' % hname + res = 'const ND_TABLE_INSTRUCTION %s = \n' % name + res += '{\n' + res += ' ND_ILUT_INSTRUCTION,\n' + res += ' (const void *)&gInstructions[%d]\n' % t.Icount + res += '};\n\n' + f.write(res) + return name + +def generate_features(features, fname): + f = open(fname, 'wt') + f.write('#ifndef _CPUID_FLAGS_H_\n') + f.write('#define _CPUID_FLAGS_H_\n') + + f.write('\n') + f.write('#define ND_CFF_NO_LEAF 0xFFFFFFFF\n') + f.write('#define ND_CFF_NO_SUBLEAF 0x00FFFFFF\n') + f.write('\n') + f.write('\n') + f.write('#define ND_CFF(leaf, subleaf, reg, bit) ((uint64_t)(leaf) | ((uint64_t)((subleaf) & 0xFFFFFF) << 32) | ((uint64_t)(reg) << 56) | ((uint64_t)(bit) << 59))\n') + f.write('\n') + + for c in features: + f.write('#define ND_CFF_%s%sND_CFF(%s, %s, %s, %s)\n' % (c.Name, ' ' * (25 - len(c.Name)), c.Leaf, c.SubLeaf, 'REG_' + c.Reg, c.Bit)) + + f.write('\n') + + f.write('#endif // _CPUID_FLAGS_H_\n') + +# +# ============================================================================= +# Main +# ============================================================================= +# +if __name__ == "__main__": + if len(sys.argv) < 2: + print('Usage: %s defs-file' % os.path.basename(sys.argv[0])) + sys.exit(-1) + + # Extract the flags. + print('Loading flags access templates...') + flagsaccess = disasmlib.parse_flags_file('%s/flags.dat' % sys.argv[1]) + + # Extact the CPUID features. + print('Loading CPUID feature flags templates...') + features = disasmlib.parse_cff_file('%s/cpuid.dat' % sys.argv[1]) + + # Extract the prefixes. + print('Loading prefixes...') + prefixes = disasmlib.parse_pre_file('%s/prefixes.dat' % sys.argv[1]) + + # Extract the valid modes. + print('Loading CPU operating modes templates...') + insmodes = disasmlib.parse_modess_file('%s/modes.dat' % sys.argv[1]) + + # Extract the instructions. + for fn in glob.glob('%s/table*.dat' % sys.argv[1]): + print('Loading instructions from %s...' % fn) + instructions = instructions + disasmlib.parse_ins_file(fn, flagsaccess, features, insmodes) + + # Sort the instructions. + instructions = sorted(instructions, key = lambda x: x.Mnemonic) + for i in range(0, len(instructions)): + instructions[i].Icount = i + + # Generate the translation tree + translations = generate_translations2(instructions) + + # Generate the mnemonics + mnemonics = generate_mnemonics(instructions) + mnemonics_prefixes = generate_mnemonics(prefixes) + + # Generate the constants + constants = generate_constants(instructions) + constants_prefixes = generate_constants(prefixes, True) + constants_sets, constants_types = generate_constants2(instructions) + + # + # Dump all data to files. + # + + # Dump the mnemonics + print('Writing the mnemonics.h file...') + dump_mnemonics(mnemonics, mnemonics_prefixes, r'../bddisasm/include/mnemonics.h') + + # Dump the instruction constants + print('Writing the constants.h (instruction definitions) file...') + dump_constants(constants, constants_prefixes, constants_sets, constants_types, r'../inc/constants.h') + + print('Writing the instructions.h (main instruction database) file...') + generate_master_table(instructions, r'../bddisasm/include/instructions.h') + + print('Writing the cpuidflags.h (CPUID feature flags) file...') + generate_features(features, r'../inc/cpuidflags.h') + + print('Instruction succesfully parsed & header files generated!') diff --git a/isagenerator/instructions/cpuid.dat b/isagenerator/instructions/cpuid.dat new file mode 100644 index 0000000..bbbaeb6 --- /dev/null +++ b/isagenerator/instructions/cpuid.dat @@ -0,0 +1,112 @@ +# CPUID feature flags. +# Synthax: NAME : leaf, subleaf, register, bit +# NAME can be anything, but it should match an ISA extension type. +# leaf - CPUID leaf value (eax input value) +# subleaf - CPUID subleaf (ecx input value). Use 0xFFFFFFFF if not used. +# register - CPUID output register containing the bit +# bit - the bit inside the register which indicates if the instruction is present or not + +FPU : 0x00000001, 0xFFFFFFFF, EDX, 0 +MSR : 0x00000001, 0xFFFFFFFF, EDX, 5 +CX8 : 0x00000001, 0xFFFFFFFF, EDX, 8 +SEP : 0x00000001, 0xFFFFFFFF, EDX, 11 +CMOV : 0x00000001, 0xFFFFFFFF, EDX, 15 +CLFSH : 0x00000001, 0xFFFFFFFF, EDX, 19 +MMX : 0x00000001, 0xFFFFFFFF, EDX, 23 +FXSAVE : 0x00000001, 0xFFFFFFFF, EDX, 24 +SSE : 0x00000001, 0xFFFFFFFF, EDX, 25 +SSE2 : 0x00000001, 0xFFFFFFFF, EDX, 26 +SSE3 : 0x00000001, 0xFFFFFFFF, ECX, 0 +PCLMULQDQ : 0x00000001, 0xFFFFFFFF, ECX, 1 +MONITOR : 0x00000001, 0xFFFFFFFF, ECX, 3 +VTX : 0x00000001, 0xFFFFFFFF, ECX, 5 +SMX : 0x00000001, 0xFFFFFFFF, ECX, 6 +SSSE3 : 0x00000001, 0xFFFFFFFF, ECX, 9 +FMA : 0x00000001, 0xFFFFFFFF, ECX, 12 +SSE4 : 0x00000001, 0xFFFFFFFF, ECX, 19 +SSE42 : 0x00000001, 0xFFFFFFFF, ECX, 20 +MOVBE : 0x00000001, 0xFFFFFFFF, ECX, 22 +POPCNT : 0x00000001, 0xFFFFFFFF, ECX, 23 +AES : 0x00000001, 0xFFFFFFFF, ECX, 25 +XSAVE : 0x00000001, 0xFFFFFFFF, ECX, 26 +AVX : 0x00000001, 0xFFFFFFFF, ECX, 28 +F16C : 0x00000001, 0xFFFFFFFF, ECX, 29 +RDRAND : 0x00000001, 0xFFFFFFFF, ECX, 30 + +RDWRFSGS : 0x00000007, 0x00000000, EBX, 0 +SGX : 0x00000007, 0x00000000, EBX, 2 +BMI1 : 0x00000007, 0x00000000, EBX, 3 +HLE : 0x00000007, 0x00000000, EBX, 4 +AVX2 : 0x00000007, 0x00000000, EBX, 5 +BMI2 : 0x00000007, 0x00000000, EBX, 8 +INVPCID : 0x00000007, 0x00000000, EBX, 10 +RTM : 0x00000007, 0x00000000, EBX, 11 +MPX : 0x00000007, 0x00000000, EBX, 14 +AVX512F : 0x00000007, 0x00000000, EBX, 16 +AVX512DQ : 0x00000007, 0x00000000, EBX, 17 +RDSEED : 0x00000007, 0x00000000, EBX, 18 +ADX : 0x00000007, 0x00000000, EBX, 19 +SMAP : 0x00000007, 0x00000000, EBX, 20 +AVX512IFMA : 0x00000007, 0x00000000, EBX, 21 +PCOMMIT : 0x00000007, 0x00000000, EBX, 22 +CLFSHOPT : 0x00000007, 0x00000000, EBX, 23 +CLWB : 0x00000007, 0x00000000, EBX, 24 +AVX512PF : 0x00000007, 0x00000000, EBX, 26 +AVX512ER : 0x00000007, 0x00000000, EBX, 27 +AVX512CD : 0x00000007, 0x00000000, EBX, 28 +SHA : 0x00000007, 0x00000000, EBX, 29 +AVX512BW : 0x00000007, 0x00000000, EBX, 30 +PREFETCHWT1 : 0x00000007, 0x00000000, ECX, 0 +AVX512VBMI : 0x00000007, 0x00000000, ECX, 1 +PKU : 0x00000007, 0x00000000, ECX, 3 +WAITPKG : 0x00000007, 0x00000000, ECX, 5 +AVX512VBMI2 : 0x00000007, 0x00000000, ECX, 6 +CET : 0x00000007, 0x00000000, ECX, 7 +GFNI : 0x00000007, 0x00000000, ECX, 8 +VAES : 0x00000007, 0x00000000, ECX, 9 +VPCLMULQDQ : 0x00000007, 0x00000000, ECX, 10 +AVX512VNNI : 0x00000007, 0x00000000, ECX, 11 +AVX512BITALG : 0x00000007, 0x00000000, ECX, 12 +AVX512VPOPCNTDQ : 0x00000007, 0x00000000, ECX, 14 +RDPID : 0x00000007, 0x00000000, ECX, 22 +CLDEMOTE : 0x00000007, 0x00000000, ECX, 25 +MOVDIRI : 0x00000007, 0x00000000, ECX, 27 +MOVDIR64B : 0x00000007, 0x00000000, ECX, 28 +ENQCMD : 0x00000007, 0x00000000, ECX, 29 +AVX5124VNNIW : 0x00000007, 0x00000000, EDX, 2 +AVX5124FMAPS : 0x00000007, 0x00000000, EDX, 3 +AVX512VP2INTERSECT : 0x00000007, 0x00000000, EDX, 8 +SERIALIZE : 0x00000007, 0x00000000, EDX, 14 +TSXLDTRK : 0x00000007, 0x00000000, EDX, 16 +PCONFIG : 0x00000007, 0x00000000, EDX, 18 +AMXBF16 : 0x00000007, 0x00000000, EDX, 22 +AMXTILE : 0x00000007, 0x00000000, EDX, 24 +AMXINT8 : 0x00000007, 0x00000000, EDX, 25 + + +AVX512BF16 : 0x00000007, 0x00000001, EAX, 5 + +XSAVEOPT : 0x0000000D, 0x00000001, EAX, 0 +XSAVEC : 0x0000000D, 0x00000001, EAX, 1 +XSAVES : 0x0000000D, 0x00000001, EAX, 3 + +PTWRITE : 0x00000014, 0x00000000, EBX, 4 + +SVM : 0x80000001, 0xFFFFFFFF, ECX, 2 +LZCNT : 0x80000001, 0xFFFFFFFF, ECX, 5 +SSE4A : 0x80000001, 0xFFFFFFFF, ECX, 6 +PREFETCHW : 0x80000001, 0xFFFFFFFF, ECX, 8 +FSC : 0x80000001, 0xFFFFFFFF, ECX, 11 +XOP : 0x80000001, 0xFFFFFFFF, ECX, 11 +LWP : 0x80000001, 0xFFFFFFFF, ECX, 15 +FMA4 : 0x80000001, 0xFFFFFFFF, ECX, 16 +TBM : 0x80000001, 0xFFFFFFFF, ECX, 21 +INVLPGB : 0x80000001, 0xFFFFFFFF, EDX, 24 +RDTSCP : 0x80000001, 0xFFFFFFFF, ECX, 27 +3DNOW : 0x80000001, 0xFFFFFFFF, EDX, 31 + +WBNOINVD : 0x80000008, 0xFFFFFFFF, EBX, 9 +RDPRU : 0x80000008, 0xFFFFFFFF, EBX, 4 +MCOMMIT : 0x80000008, 0xFFFFFFFF, EBX, 8 + +SNP : 0x8000001F, 0xFFFFFFFF, EAX, 4 diff --git a/isagenerator/instructions/flags.dat b/isagenerator/instructions/flags.dat new file mode 100644 index 0000000..fd88eb2 --- /dev/null +++ b/isagenerator/instructions/flags.dat @@ -0,0 +1,95 @@ +# Flags access templates; many instructions have the same flag usage, so define them here. +# Synthax: NAME: FLAG=modifier|FLAG=modifier|.... See the definitions for some examples. +# Accepted flags: CF, PF, AF, ZF, TF, IF, OF, DF, AC, IOPL, RF, NT, VIF, VIP, VM +# Accepted modifiers: t (tested), m (modified according to the result), 0 (cleared), 1 (set), u (undefined) + +# All airthmetic instructions: ADD, SUB, CMP, XADD +ARITH : CF=m|PF=m|AF=m|ZF=m|SF=m|OF=m + +# Airthmetic with carry instructions: ADC, SBB +ARITHC : CF=t|CF=m|PF=m|AF=m|ZF=m|SF=m|OF=m + +# Logic instructions: OR, AND, XOR, TEST +LOGIC : CF=0|PF=m|AF=u|ZF=m|SF=m|OF=0 + +# Rotate instructions. +ROT : CF=m|OF=m + +# Rotate carry instructions. +ROTC : CF=t|CF=m|OF=m + +# Shift instructions. +SHIFT : CF=m|PF=m|AF=u|ZF=m|SF=m|OF=m + +# Shidft double instructions. +SHIFTD : CF=u|PF=m|AF=u|ZF=m|SF=m|OF=u + +# Multiply instructions. +MUL : CF=m|PF=u|AF=u|ZF=u|SF=u|OF=m + +# Division instructions. +DIV : CF=u|PF=u|AF=u|ZF=u|SF=u|OF=u + +# AAD/AAM +AADM : CF=u|PF=m|AF=u|ZF=m|SF=m|OF=u + +# AAA/AAS +AAAS : CF=m|PF=u|AF=t|AF=m|ZF=u|SF=u|OF=u + +# DAA/DAS +DAAS : CF=t|CF=m|PF=m|AF=t|AF=m|ZF=m|OF=u + +# I/O instructions. +IO : IOPL=t|VM=t + +# I/O string operations +IOS : DF=t|IOPL=t|VM=t + +# INT instructions. +INT : VM=t|VM=m|IF=m|NT=m|AC=m|RF=m|TF=m + +# Used by CMPS/SCAS and REP CMPS/REP SCAS +CMPS : CF=m|PF=m|AF=m|ZF=m|SF=m|OF=m|DF=t +REPCMPS : CF=m|PF=m|AF=m|ZF=t|ZF=m|SF=m|OF=m|DF=t + +# Used by PCMPESTRM, PCMPESTRI, PCMPISTRM, PCMPISTRI +PCMPSTR : CF=m|PF=0|AF=0|ZF=m|SF=m|OF=m + +# Used by VMX instructions. +VMX : CF=m|PF=0|AF=0|ZF=m|SF=0|OF=0 + +# Used by BT, BTS, BTR, BTC instructions. +BT : CF=m|PF=u|AF=u|SF=u|OF=u + +# COMIS instructions. +COMIS : CF=m|PF=m|ZF=m + +# VPTEST instructions. +VPTEST : CF=m|PF=0|AF=0|ZF=m|SF=0|OF=0 + +# UMWAIT, TPAUSE instructions. +WAITPKG : CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0 + +# ENQCMD instructions. +ENQCMD : CF=0|PF=0|AF=0|ZF=m|SF=0|OF=0 + +# KORTEST instructions. +KORTEST : CF=m|PF=0|AF=0|ZF=m|SF=0|OF=0 + +# Conditional codes. +CO : OF=t +CNO : OF=t +CC : CF=t +CNC : CF=t +CZ : ZF=t +CNZ : ZF=t +CBE : CF=t|ZF=t +CNBE : CF=t|ZF=t +CS : SF=t +CNS : SF=t +CP : PF=t +CNP : PF=t +CL : SF=t|OF=t +CNL : SF=t|OF=t +CLE : SF=t|ZF=t|OF=t +CNLE : SF=t|ZF=t|OF=t diff --git a/isagenerator/instructions/modes.dat b/isagenerator/instructions/modes.dat new file mode 100644 index 0000000..269ed68 --- /dev/null +++ b/isagenerator/instructions/modes.dat @@ -0,0 +1,78 @@ +# Valid operating modes for instructions. Please use these templates and not inline definitions. If a template does +# not exist already, create a new one. +# Synthax: NAME : group1:mode11[+mode12[|group2:!mode21+!mode22]] etc. +# +# NAME cam be anything and can be used as a placeholder when defining the instruction. +# group - can be one of the 4 operating groups: +# ring - specify the needed privilege level for the instruction +# mode - specify the needed operating mode +# vmx - specify the VMX operation mode +# other- specify other misc operating modes/special cases +# +# ring - can be any of: +# r0 - instruction is valid in ring 0 +# r1 - instruction is valid in ring 1 +# r2 - instruction is valid in ring 2 +# r3 - instruction is valid in ring 3 +# +# mode - can be any of: +# real - instruction valid in real mode (16 bit) +# v8086 - instruction valid in virtual 8086 mode (16 bit inside 32 bit mode) +# prot - instruction valid in protected mode (32 bit) +# compat- instruction valid in compatibility mode (32 inside 64 bit mode) +# long - instruction valid in long mode (64 bit) +# smm - instruction valid in System Management Mode +# +# other - can be any of: +# sgx - instruction is valid inside a Software Guard Extensions enclave +# tsx - instruction is valid inside a Transactional Syncronization Extensions region +# +# vmx - can be any of: +# vmxr - instruction valid in VMX root mode +# vmxn - instruction valid in VMX non-root mode +# vmxo - instruction valid outside VMX operation +# +# If a group is not specified, all modes for that group will be considered valid. +# If only some modes are specified for a group, only they will be considered valid, and all the others invalid. +# If only some modes are specified negated (!), the instruction will be considered valid in all but the specified modes. +# +# For SGX and TSX, the most restrictive rule is applied: an instruction is listed as valid in any of these modes if +# it will always execute successfully; instructions that may be valid or invalid depending on microarchitectural +# design/conditions are listed as invalid in these modes. +# + +# Instruction that are valid ONLY in VMX root operation; this also implies ring0, and only protected or long mode. +VMXROOT : ring=r0|vmx=vmxr|mode=prot+long|other=!sgx+!tsx + +# Instructions valid only in VMX operation, be it VMX root or VMX non-root. +VMX : vmx=!vmxo + +# Instructions valid only in r0. SGX enclaves exist only in r3, so a 0 instruction will not be valid in SGX mode. +KERNEL : ring=r0|other=!sgx + +# Instructions valid only in r3. +USER : ring=r3 + +# Instructions invalid in real mode. If an instruction is invalid in real mode, it will be invalid in v8086 as well. +NOREAL : mode=!real+!v8086 + +# Instructions invalid in v8086 mode. They may be, however, valid in real mode. +NOV86 : mode=!v8086 + +# Instructions valid only in long mode (64 bit). +O64 : mode=long + +# Instructions invalid in long mode. +NO64 : mode=!long + +# Instructions invalid in transactional regions. +NOTSX : other=!tsx + +# Instructions invalid in SGX mode. +NOSGX : other=!sgx + +# Instructions valid only in SMM. Note that while in SMM, one can transition in protected/long mode. +SMM : mode=prot+compat+long+smm + +# Instructions invalid inside SMM, real-mode or V8086. +NOSMM : mode=!real+!v8086+!smm diff --git a/isagenerator/instructions/prefixes.dat b/isagenerator/instructions/prefixes.dat new file mode 100644 index 0000000..95fed61 --- /dev/null +++ b/isagenerator/instructions/prefixes.dat @@ -0,0 +1,35 @@ +# Segment overrides +es [0x26] +cs [0x2E] +ss [0x36] +ds [0x3E] +fs [0x64] +gs [0x65] + +# Operand size overrides +size [0x66] + +# Address size override +addr [0x67] + +# LOCK prefix +LOCK [0xF0] + +# REP prefixes +REPNZ [0xF2] +REPZ [0xF3] + +# Branch hints +BHNT [0x2E] +BHT [0x3E] +BHALT [0x64] + +# HLE prefixes +XACQUIRE [0xF2] +XRELEASE [0xF3] + +# BND prefix +BND [0xF2] + +# CET prefix; improvised name until a better one is published. +DNT [0x3E] \ No newline at end of file diff --git a/isagenerator/instructions/table_0F.dat b/isagenerator/instructions/table_0F.dat new file mode 100644 index 0000000..93e54e9 --- /dev/null +++ b/isagenerator/instructions/table_0F.dat @@ -0,0 +1,668 @@ +# Mnemonic Explicit Implicit Encoding Fags, Prefixes, Set, Category, Class, RW map, Additional ops +#------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +# 0x00 - 0x0F +SLDT Mw LDTR [ 0x0F 0x00 /0:mem] s:I286PROT, t:SYSTEM, w:W|R, m:NOREAL|NOSGX +SLDT Rv LDTR [ 0x0F 0x00 /0:reg] s:I286PROT, t:SYSTEM, w:W|R, m:NOREAL|NOSGX +STR Mw TR [ 0x0F 0x00 /1:mem] s:I286PROT, t:SYSTEM, w:W|R, m:NOREAL|NOSGX +STR Rv TR [ 0x0F 0x00 /1:reg] s:I286PROT, t:SYSTEM, w:W|R, m:NOREAL|NOSGX +LLDT Ew LDTR [ 0x0F 0x00 /2] s:I286PROT, t:SYSTEM, w:R|W, a:SERIAL, m:KERNEL|NOREAL +LTR Ew TR [ 0x0F 0x00 /3] s:I286PROT, t:SYSTEM, w:R|W, a:SERIAL, m:KERNEL|NOREAL +VERR Ew Fv [ 0x0F 0x00 /4] s:I286PROT, t:SYSTEM, w:R|W, f:ZF=m, m:NOREAL +VERW Ew Fv [ 0x0F 0x00 /5] s:I286PROT, t:SYSTEM, w:R|W, f:ZF=m, m:NOREAL +JMPE Ev rIP [ 0x0F 0x00 /6] s:I64, t:SYSTEM, w:R|W, m:NO64 +SGDT Ms GDTR [ 0x0F 0x01 /0:mem] s:I286REAL, t:SYSTEM, w:W|R, m:NOSGX +SIDT Ms IDTR [ 0x0F 0x01 /1:mem] s:I286REAL, t:SYSTEM, w:W|R, m:NOSGX +LGDT Ms GDTR [ 0x0F 0x01 /2:mem] s:I286REAL, t:SYSTEM, w:R|W, a:SERIAL, m:KERNEL +LIDT Ms IDTR [ 0x0F 0x01 /3:mem] s:I286REAL, t:SYSTEM, w:R|W, a:SERIAL, m:KERNEL +SMSW Mw CR0 [ 0x0F 0x01 /4:mem] s:I286REAL, t:SYSTEM, w:W|R, m:NOSGX +SMSW Rv CR0 [ 0x0F 0x01 /4:reg] s:I286REAL, t:SYSTEM, w:W|R, m:NOSGX +LMSW Ew CR0 [ 0x0F 0x01 /6] s:I286REAL, t:SYSTEM, w:R|W, a:SERIAL, m:KERNEL +INVLPG Mb nil [ 0x0F 0x01 /7:mem] s:I486REAL, t:SYSTEM, w:R, a:AG, m:KERNEL|NOV86 +RSTORSSP Mq nil [ 0xF3 0x0F 0x01 /5:mem] s:CET, t:CET, a:SHS, w:RW +ENCLV nil EAX,RBX,RCX,RDX [ NP 0x0F 0x01 /0xC0] s:SGX, t:SGX, w:R|CRW|CRW|CRW, m:KERNEL|NOSMM|NOTSX|VMX +VMCALL nil nil [ 0x0F 0x01 /0xC1] s:VTX, t:VTX, m:VMX|NOSGX +VMLAUNCH nil Fv [ 0x0F 0x01 /0xC2] s:VTX, t:VTX, w:W, f:VMX, m:VMXROOT +VMRESUME nil Fv [ 0x0F 0x01 /0xC3] s:VTX, t:VTX, w:W, f:VMX, m:VMXROOT +VMXOFF nil Fv [ 0x0F 0x01 /0xC4] s:VTX, t:VTX, w:W, f:VMX, m:VMXROOT +PCONFIG nil EAX,RBX,RCX,RDX [ NP 0x0F 0x01 /0xC5] s:PCONFIG, t:PCONFIG, w:R|RW|RW|RW, m:NOV86 +MONITOR nil EAX,ECX,EDX [ NP 0x0F 0x01 /0xC8] s:SSE3, t:MISC, w:R|R|R, i:MONITOR, m:KERNEL|NOV86 +MWAIT nil EAX,ECX [ NP 0x0F 0x01 /0xC9] s:SSE3, t:MISC, w:RW|R, i:MONITOR, m:KERNEL|NOV86 +CLAC nil Fv [ NP 0x0F 0x01 /0xCA] s:SMAP, t:SMAP, w:W, f:AC=0, m:KERNEL|NOV86 +STAC nil Fv [ NP 0x0F 0x01 /0xCB] s:SMAP, t:SMAP, w:W, f:AC=1, m:KERNEL|NOV86 +ENCLS nil EAX,RBX,RCX,RDX [ NP 0x0F 0x01 /0xCF] s:SGX, t:SGX, w:R|CRW|CRW|CRW, m:KERNEL|NOSMM|NOTSX +XGETBV nil ECX,EDX,EAX,XCR [ NP 0x0F 0x01 /0xD0] s:XSAVE, t:XSAVE, w:R|W|W|R +XSETBV nil ECX,EDX,EAX,XCR [ NP 0x0F 0x01 /0xD1] s:XSAVE, t:XSAVE, w:R|R|R|W, m:KERNEL +VMFUNC nil nil [ NP 0x0F 0x01 /0xD4] s:VTX, t:VTX, m:VMX|NOSGX +XEND nil nil [ NP 0x0F 0x01 /0xD5] s:TSX, t:COND_BR, i:RTM +XTEST nil Fv [ NP 0x0F 0x01 /0xD6] s:TSX, t:LOGIC, w:W, i:RTM, f:CF=0|PF=0|AF=0|ZF=m|SF=0|OF=0 +ENCLU nil EAX,RBX,RCX,RDX [ NP 0x0F 0x01 /0xD7] s:SGX, t:SGX, w:R|CRW|CRW|CRW, m:USER|NOSMM|NOTSX +SERIALIZE nil nil [ NP 0x0F 0x01 /0xE8] s:SERIALIZE, t:MISC +XSUSLDTRK nil nil [ 0xF2 0x0F 0x01 /0xE8] s:TSXLDTRK, t:MISC +XRESLDTRK nil nil [ 0xF2 0x0F 0x01 /0xE9] s:TSXLDTRK, t:MISC +SAVEPREVSSP nil SHS,SSP [ 0xF3 0x0F 0x01 /0xEA] s:CET, t:CET, w:W|RW +RDPKRU nil EDX,EAX,ECX,PKRU [ NP 0x0F 0x01 /0xEE] s:PKU, t:MISC, w:W|W|R|R +WRPKRU nil EDX,EAX,ECX,PKRU [ NP 0x0F 0x01 /0xEF] s:PKU, t:MISC, w:R|R|R|W +SWAPGS nil GSBASE,KGSBASE [ 0x0F 0x01 /0xF8] s:LONGMODE, t:SYSTEM, w:RW|RW, m:KERNEL|O64 +RDTSCP nil EAX,EDX,ECX,TSC,TSCAUX [ 0x0F 0x01 /0xF9] s:RDTSCP, t:SYSTEM, w:W|W|W|R|R +MONITORX nil EAX,ECX,EDX [ NP 0x0F 0x01 /0xFA] s:MWAITT, t:SYSTEM, w:R|R|R, m:KERNEL|NOV86 +MCOMMIT nil Fv [ 0xF3 0x0F 0x01 /0xFA] s:MCOMMIT, t:MISC, w:W, f:CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0 +MWAITX nil EAX,ECX,EBX [ NP 0x0F 0x01 /0xFB] s:MWAITT, t:SYSTEM, w:R|R|R, m:KERNEL|NOV86 +CLZERO nil rAX [ 0x0F 0x01 /0xFC] s:CLZERO, t:MISC, w:R +RDPRU nil EAX,EDX,ECX,Fv [ 0x0F 0x01 /0xFD] s:RDPRU, t:MISC, w:W|W|R|W, f:CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0 +VMRUN nil rAX [ 0x0F 0x01 /0xD8] s:SVM, t:SYSTEM, w:R, m:VMXROOT +VMMCALL nil nil [ 0x0F 0x01 /0xD9] s:SVM, t:SYSTEM, m:VMX +VMGEXIT nil nil [ 0xF3 0x0F 0x01 /0xD9] s:SVM, t:SYSTEM, m:VMX +VMGEXIT nil nil [ 0xF2 0x0F 0x01 /0xD9] s:SVM, t:SYSTEM, m:VMX +VMLOAD nil rAX [ 0x0F 0x01 /0xDA] s:SVM, t:SYSTEM, w:R, m:VMXROOT +VMSAVE nil nil [ 0x0F 0x01 /0xDB] s:SVM, t:SYSTEM, m:VMXROOT +STGI nil nil [ 0x0F 0x01 /0xDC] s:SVM, t:SYSTEM, m:VMXROOT +CLGI nil nil [ 0x0F 0x01 /0xDD] s:SVM, t:SYSTEM, m:VMXROOT +SKINIT nil EAX [ 0x0F 0x01 /0xDE] s:SVM, t:SYSTEM, w:R, m:VMXROOT +INVLPGA nil rAX,ECX [ 0x0F 0x01 /0xDF] s:SVM, t:SYSTEM, w:R|R, m:VMXROOT +SETSSBSY nil nil [ 0xF3 0x0F 0x01 /0xE8] s:CET, t:CET, a:SHS +INVLPGB nil rAX,ECX,EDX [ 0x0F 0x01 /0xFE] s:INVLPGB, t:SYSTEM, w:R|R|R, m:NOREAL|KERNEL +RMPADJUST nil RAX,RCX,RDX,Fv [ 0xF3 0x0F 0x01 /0xFE] s:SNP, t:SYSTEM, w:RW|R|R|W, f:OF=m|ZF=m|AF=m|PF=m|SF=m, m:O64|KERNEL +RMPUPDATE nil RAX,RCX,Fv [ 0xF2 0x0F 0x01 /0xFE] s:SNP, t:SYSTEM, w:RW|R|W, f:OF=m|ZF=m|AF=m|PF=m|SF=m, m:O64|KERNEL +TLBSYNC nil nil [ 0x0F 0x01 /0xFF] s:INVLPGB, t:SYSTEM, m:NOREAL|KERNEL +PSMASH nil RAX,Fv [ 0xF3 0x0F 0x01 /0xFF] s:SNP, t:SYSTEM, w:RW|W, f:OF=m|ZF=m|AF=m|PF=m|SF=m, m:O64|KERNEL +PVALIDATE nil rAX,ECX,EDX,Fv [ 0xF2 0x0F 0x01 /0xFF] s:SNP, t:SYSTEM, w:RW|R|R|W, f:OF=m|ZF=m|AF=m|PF=m|SF=m|CF=m, m:KERNEL +LAR Gv,Mw Fv [ 0x0F 0x02 /r:mem] s:I286PROT, t:SYSTEM, w:CW|R|W, f:ZF=m, m:NOREAL +LAR Gv,Rz Fv [ 0x0F 0x02 /r:reg] s:I286PROT, t:SYSTEM, w:CW|R|W, f:ZF=m, m:NOREAL +LSL Gv,Mw Fv [ 0x0F 0x03 /r:mem] s:I286PROT, t:SYSTEM, w:RW|R|W, f:ZF=m, m:NOREAL +LSL Gv,Rz Fv [ 0x0F 0x03 /r:reg] s:I286PROT, t:SYSTEM, w:RW|R|W, f:ZF=m, m:NOREAL +LOADALL nil BANK [ 0x0F 0x05] s:I486REAL, t:UNDOC, w:R +SYSCALL nil STAR,LSTAR,FMASK,SS,RCX,R11,CS,rIP,Fv [ o64 0x0F 0x05] s:AMD, t:SYSCALL, w:R|R|R|W|W|W|W|W|RW, i:FSC, m:O64|NOSGX +CLTS nil CR0 [ 0x0F 0x06] s:I286REAL, t:SYSTEM, w:W, m:KERNEL|NOV86 +LOADALLD nil BANK [ 0x0F 0x07] s:I486REAL, t:UNDOC, w:R +SYSRET nil STAR,SS,rCX,R11,CS,rIP,Fv [ o64 0x0F 0x07] s:AMD, t:SYSRET, w:R|W|R|R|W|W|W, i:FSC, m:KERNEL|O64 +INVD nil nil [ 0x0F 0x08] s:I486REAL, t:SYSTEM, a:SERIAL, m:KERNEL|NOV86 +WBINVD nil nil [ NP 0x0F 0x09] s:I486REAL, t:SYSTEM, a:SERIAL, m:KERNEL|NOV86 +WBNOINVD nil nil [ 0xF3 0x0F 0x09] s:WBNOINVD, t:WBNOINVD, m:KERNEL|NOV86 +CL1INVMB nil nil [ 0x0F 0x0A] s:SCC, t:SYSTEM +UD2 nil nil [ 0x0F 0x0B] s:PPRO, t:MISC +PREFETCHE Mcl nil [ 0x0F 0x0D /0:mem] s:PREFETCH_NOP, t:PREFETCH, w:R +NOP Ev,Gv nil [ 0x0F 0x0D /0:reg] s:PPRO, t:NOP, w:R|R +PREFETCHW Mcl nil [ 0x0F 0x0D /1:mem] s:PREFETCH_NOP, t:PREFETCH, w:R +NOP Ev,Gv nil [ 0x0F 0x0D /1:reg] s:PPRO, t:NOP, w:R|R +PREFETCHWT1 Mcl nil [ 0x0F 0x0D /2:mem] s:PREFETCH_NOP, t:PREFETCH, w:R +NOP Ev,Gv nil [ 0x0F 0x0D /2:reg] s:PPRO, t:NOP, w:R|R +PREFETCHM Mcl nil [ 0x0F 0x0D /3:mem] s:PREFETCH_NOP, t:PREFETCH, w:R +NOP Ev,Gv nil [ 0x0F 0x0D /3:reg] s:PPRO, t:NOP, w:R|R +PREFETCH Mcl nil [ 0x0F 0x0D /4:mem] s:PREFETCH_NOP, t:PREFETCH, w:R +NOP Ev,Gv nil [ 0x0F 0x0D /4:reg] s:PPRO, t:NOP, w:R|R +PREFETCH Mcl nil [ 0x0F 0x0D /5:mem] s:PREFETCH_NOP, t:PREFETCH, w:R +NOP Ev,Gv nil [ 0x0F 0x0D /5:reg] s:PPRO, t:NOP, w:R|R +PREFETCH Mcl nil [ 0x0F 0x0D /6:mem] s:PREFETCH_NOP, t:PREFETCH, w:R +NOP Ev,Gv nil [ 0x0F 0x0D /6:reg] s:PPRO, t:NOP, w:R|R +PREFETCH Mcl nil [ 0x0F 0x0D /7:mem] s:PREFETCH_NOP, t:PREFETCH, w:R +NOP Ev,Gv nil [ 0x0F 0x0D /7:reg] s:PPRO, t:NOP, w:R|R + +FEMMS nil nil [ 0x0F 0x0E] s:3DNOW, t:MMX, c:FEMMS + +# 0x10 - 0x1F +MOVUPS Vps,Wps nil [ NP 0x0F 0x10 /r] s:SSE, t:DATAXFER, w:W|R, e:4 +MOVUPD Vpd,Wpd nil [ 0x66 0x0F 0x10 /r] s:SSE2, t:DATAXFER, w:W|R, e:4 +MOVSS Vss,Wss nil [ 0xF3 0x0F 0x10 /r] s:SSE, t:DATAXFER, w:W|R, e:5 +MOVSD Vsd,Wsd nil [ 0xF2 0x0F 0x10 /r] s:SSE2, t:DATAXFER, w:W|R, e:5 +MOVUPS Wps,Vps nil [ NP 0x0F 0x11 /r] s:SSE, t:DATAXFER, w:W|R, e:4 +MOVUPD Wpd,Vpd nil [ 0x66 0x0F 0x11 /r] s:SSE2, t:DATAXFER, w:W|R, e:4 +MOVSS Wss,Vss nil [ 0xF3 0x0F 0x11 /r] s:SSE, t:DATAXFER, w:W|R, e:5 +MOVSD Wsd,Vsd nil [ 0xF2 0x0F 0x11 /r] s:SSE2, t:DATAXFER, w:W|R, e:5 +MOVLPS Vq,Wq nil [ NP 0x0F 0x12 /r] s:SSE, t:DATAXFER, w:W|R, e:5 +MOVLPD Vsd,Mq nil [ 0x66 0x0F 0x12 /r:mem] s:SSE2, t:DATAXFER, w:W|R, e:5 +MOVSLDUP Vx,Wx nil [ 0xF3 0x0F 0x12 /r] s:SSE3, t:DATAXFER, w:W|R, e:4 +MOVDDUP Vdq,Wq nil [ 0xF2 0x0F 0x12 /r] s:SSE3, t:DATAXFER, w:W|R, e:5 +MOVLPS Mq,Vps nil [ NP 0x0F 0x13 /r:mem] s:SSE, t:DATAXFER, w:W|R, e:5 +MOVLPD Mq,Vpd nil [ 0x66 0x0F 0x13 /r:mem] s:SSE2, t:DATAXFER, w:W|R, e:5 +UNPCKLPS Vx,Wx nil [ NP 0x0F 0x14 /r] s:SSE, t:SSE, w:RW|R, e:4 +UNPCKLPD Vx,Wx nil [ 0x66 0x0F 0x14 /r] s:SSE2, t:SSE, w:RW|R, e:4 +UNPCKHPS Vx,Wx nil [ NP 0x0F 0x15 /r] s:SSE, t:SSE, w:RW|R, e:4 +UNPCKHPD Vx,Wx nil [ 0x66 0x0F 0x15 /r] s:SSE2, t:SSE, w:RW|R, e:4 +MOVHPS Vq,Mq nil [ NP 0x0F 0x16 /r:mem] s:SSE, t:DATAXFER, w:W|R, e:5 +MOVLHPS Vq,Uq nil [ NP 0x0F 0x16 /r:reg] s:SSE, t:DATAXFER, w:W|R, e:7 +MOVHPD Vq,Mq nil [ 0x66 0x0F 0x16 /r:mem] s:SSE2, t:DATAXFER, w:W|R, e:5 +MOVSHDUP Vx,Wx nil [ 0xF3 0x0F 0x16 /r] s:SSE3, t:DATAXFER, w:W|R, e:4 +MOVHPS Mq,Vq nil [ NP 0x0F 0x17 /r:mem] s:SSE, t:DATAXFER, w:W|R, e:5 +MOVHPD Mq,Vq nil [ 0x66 0x0F 0x17 /r:mem] s:SSE2, t:DATAXFER, w:W|R, e:5 +PREFETCHNTA Mcl nil [ 0x0F 0x18 /0:mem] s:SSE, t:PREFETCH, w:R +NOP Ev nil [ 0x0F 0x18 /0:reg] s:PPRO, t:WIDENOP, w:R +PREFETCHT0 Mcl nil [ 0x0F 0x18 /1:mem] s:SSE, t:PREFETCH, w:R +NOP Ev nil [ 0x0F 0x18 /1:reg] s:PPRO, t:WIDENOP, w:R +PREFETCHT1 Mcl nil [ 0x0F 0x18 /2:mem] s:SSE, t:PREFETCH, w:R +NOP Ev nil [ 0x0F 0x18 /2:reg] s:PPRO, t:WIDENOP, w:R +PREFETCHT2 Mcl nil [ 0x0F 0x18 /3:mem] s:SSE, t:PREFETCH, w:R +NOP Ev nil [ 0x0F 0x18 /3:reg] s:PPRO, t:WIDENOP, w:R +NOP Ev nil [ 0x0F 0x18 /4] s:PPRO, t:WIDENOP, w:R +NOP Ev nil [ 0x0F 0x18 /5] s:PPRO, t:WIDENOP, w:R +NOP Ev nil [ 0x0F 0x18 /6] s:PPRO, t:WIDENOP, w:R +NOP Ev nil [ 0x0F 0x18 /7] s:PPRO, t:WIDENOP, w:R +NOP Ev nil [ 0x0F 0x19 /r] s:PPRO, t:WIDENOP, w:R + +# MPX instructions. According to the SDM, MPX instructions have 64 bit op & address size in 64 bit mode, no matter +# if 0x66 or 0x67 prefixes are used. 16 bit addressing cause #UD. However, these checks are not handled here (note +# that Xed doesn't do those checks either). +BNDLDX rBl,Mmib nil [ 0x0F 0x1A /r:mem mib] s:MPX, t:MPX, w:W|R, a:AG|NOA16|NORIPREL +NOP Gv,Ev nil [ 0x0F 0x1A /r:reg] s:PPRO, t:WIDENOP, w:R|R +BNDMOV rBl,mBl nil [ 0x66 0x0F 0x1A /r] s:MPX, t:MPX, w:W|R, a:NOA16 +BNDCL rBl,Ey nil [ 0xF3 0x0F 0x1A /r] s:MPX, t:MPX, w:R|R, a:AG|F64 +BNDCU rBl,Ey nil [ 0xF2 0x0F 0x1A /r] s:MPX, t:MPX, w:R|R, a:AG|F64 + +BNDSTX Mmib,rBl nil [ 0x0F 0x1B /r:mem mib] s:MPX, t:MPX, w:W|R, a:AG|NOA16|NORIPREL +NOP Gv,Ev nil [ 0x0F 0x1B /r:reg] s:PPRO, t:WIDENOP, w:R|R +BNDMOV mBl,rBl nil [ 0x66 0x0F 0x1B /r] s:MPX, t:MPX, w:W|R, a:NOA16 +BNDMK rBl,My nil [ 0xF3 0x0F 0x1B /r:mem] s:MPX, t:MPX, w:W|R, a:F64|NOA16|NORIPREL +NOP Gv,Ev nil [ 0xF3 0x0F 0x1B /r:reg] s:PPRO, t:WIDENOP, w:R|R +BNDCN rBl,Ey nil [ 0xF2 0x0F 0x1B /r] s:MPX, t:MPX, w:R|R, a:AG|F64 + +CLDEMOTE Mcl nil [ NP 0x0F 0x1C /0:mem] s:CLDEMOTE, t:CLDEMOTE, w:W +NOP Ev,Gv nil [ 0x66 0x0F 0x1C /0:mem] s:PPRO, t:WIDENOP, w:R|R +NOP Ev,Gv nil [ 0xF3 0x0F 0x1C /0:mem] s:PPRO, t:WIDENOP, w:R|R +NOP Ev,Gv nil [ 0xF2 0x0F 0x1C /0:mem] s:PPRO, t:WIDENOP, w:R|R +NOP Ev,Gv nil [ 0x0F 0x1C /0:reg] s:PPRO, t:WIDENOP, w:R|R +NOP Ev,Gv nil [ 0x0F 0x1C /1] s:PPRO, t:WIDENOP, w:R|R +NOP Ev,Gv nil [ 0x0F 0x1C /2] s:PPRO, t:WIDENOP, w:R|R +NOP Ev,Gv nil [ 0x0F 0x1C /3] s:PPRO, t:WIDENOP, w:R|R +NOP Ev,Gv nil [ 0x0F 0x1C /4] s:PPRO, t:WIDENOP, w:R|R +NOP Ev,Gv nil [ 0x0F 0x1C /5] s:PPRO, t:WIDENOP, w:R|R +NOP Ev,Gv nil [ 0x0F 0x1C /6] s:PPRO, t:WIDENOP, w:R|R +NOP Ev,Gv nil [ 0x0F 0x1C /7] s:PPRO, t:WIDENOP, w:R|R +NOP Ev,Gv nil [ 0x0F 0x1D /r] s:PPRO, t:WIDENOP, w:R|R + +NOP Mv,Gv nil [ 0x0F 0x1E /r:mem] s:PPRO, t:WIDENOP, w:R|R +NOP Rv,Gv nil [ 0x0F 0x1E /0:reg] s:PPRO, t:WIDENOP, w:R|R +NOP Rv,Gv nil [ 0x0F 0x1E /1:reg] s:PPRO, t:WIDENOP, w:R|R +NOP Rv,Gv nil [ rexw 0x0F 0x1E /1:reg] s:PPRO, t:WIDENOP, w:R|R +RDSSPD Rd SSP [ a0xF3 0x0F 0x1E /1:reg] s:CET, t:CET, c:RSSSP, w:W|R +RDSSPQ Rq SSP [ a0xF3 rexw 0x0F 0x1E /1:reg] s:CET, t:CET, c:RSSSP, w:W|R +NOP Rv,Gv nil [ 0x0F 0x1E /2:reg] s:PPRO, t:WIDENOP, w:R|R +NOP Rv,Gv nil [ 0x0F 0x1E /3:reg] s:PPRO, t:WIDENOP, w:R|R +NOP Rv,Gv nil [ 0x0F 0x1E /4:reg] s:PPRO, t:WIDENOP, w:R|R +NOP Rv,Gv nil [ 0x0F 0x1E /5:reg] s:PPRO, t:WIDENOP, w:R|R +NOP Rv,Gv nil [ 0x0F 0x1E /6:reg] s:PPRO, t:WIDENOP, w:R|R +NOP Rv,Gv nil [ 0x0F 0x1E /0xF8] s:PPRO, t:WIDENOP, w:R|R +NOP Rv,Gv nil [ 0x0F 0x1E /0xF9] s:PPRO, t:WIDENOP, w:R|R +NOP Rv,Gv nil [ 0x0F 0x1E /0xFA] s:PPRO, t:WIDENOP, w:R|R +NOP Rv,Gv nil [ 0x0F 0x1E /0xFB] s:PPRO, t:WIDENOP, w:R|R +NOP Rv,Gv nil [ 0x0F 0x1E /0xFC] s:PPRO, t:WIDENOP, w:R|R +NOP Rv,Gv nil [ 0x0F 0x1E /0xFD] s:PPRO, t:WIDENOP, w:R|R +NOP Rv,Gv nil [ 0x0F 0x1E /0xFE] s:PPRO, t:WIDENOP, w:R|R +NOP Rv,Gv nil [ 0x0F 0x1E /0xFF] s:PPRO, t:WIDENOP, w:R|R +ENDBR64 nil nil [ a0xF3 0x0F 0x1E /0xFA] s:CET, t:CET, c:ENDBR +ENDBR32 nil nil [ a0xF3 0x0F 0x1E /0xFB] s:CET, t:CET, c:ENDBR + +NOP Ev,Gv nil [ 0x0F 0x1F /r] s:PPRO, t:WIDENOP, w:R|R + +# 0x20 - 0x2F +MOV Ry,Cy nil [ 0x0F 0x20 /r] s:I86, t:DATAXFER, c:MOV_CR, w:W|R, a:LOCKSP|MFR|F64, m:KERNEL|NOV86 +MOV Ry,Dy nil [ 0x0F 0x21 /r] s:I86, t:DATAXFER, c:MOV_DR, w:W|R, a:MFR|F64, m:KERNEL|NOV86 +MOV Cy,Ry nil [ 0x0F 0x22 /r] s:I86, t:DATAXFER, c:MOV_CR, w:W|R, a:LOCKSP|MFR|F64|SERIAL, m:KERNEL|NOV86 +MOV Dy,Ry nil [ 0x0F 0x23 /r] s:I86, t:DATAXFER, c:MOV_DR, w:W|R, a:MFR|F64|SERIAL, m:KERNEL|NOV86 +MOV Ry,Ty nil [ 0x0F 0x24 /r] s:I86, t:DATAXFER, c:MOV_TR, w:W|R, a:MFR|F64, m:KERNEL|NOV86 +MOV Ty,Ry nil [ 0x0F 0x26 /r] s:I86, t:DATAXFER, c:MOV_TR, w:W|R, a:MFR|F64, m:KERNEL|NOV86 +MOVAPS Vps,Wps nil [ NP 0x0F 0x28 /r] s:SSE, t:DATAXFER, w:W|R, e:1 +MOVAPD Vpd,Wpd nil [ 0x66 0x0F 0x28 /r] s:SSE2, t:DATAXFER, w:W|R, e:1 +MOVAPS Wps,Vps nil [ NP 0x0F 0x29 /r] s:SSE, t:DATAXFER, w:W|R, e:1 +MOVAPD Wpd,Vpd nil [ 0x66 0x0F 0x29 /r] s:SSE2, t:DATAXFER, w:W|R, e:1 +CVTPI2PS Vq,Qq nil [ NP 0x0F 0x2A /r] s:SSE, t:CONVERT, w:W|R +CVTPI2PD Vpd,Qq nil [ 0x66 0x0F 0x2A /r] s:SSE2, t:CONVERT, w:W|R +CVTSI2SS Vss,Ey nil [ 0xF3 0x0F 0x2A /r] s:SSE, t:CONVERT, w:W|R, e:3 +CVTSI2SD Vsd,Ey nil [ 0xF2 0x0F 0x2A /r] s:SSE2, t:CONVERT, w:W|R, e:3 +MOVNTPS Mps,Vps nil [ NP 0x0F 0x2B /r:mem] s:SSE, t:DATAXFER, w:W|R, e:1 +MOVNTPD Mpd,Vpd nil [ 0x66 0x0F 0x2B /r:mem] s:SSE2, t:DATAXFER, w:W|R, e:1 +MOVNTSS Mss,Vss nil [ 0xF3 0x0F 0x2B /r:mem] s:SSE4A, t:DATAXFER, w:W|R +MOVNTSD Msd,Vsd nil [ 0xF2 0x0F 0x2B /r:mem] s:SSE4A, t:DATAXFER, w:W|R +CVTTPS2PI Pq,Wq nil [ NP 0x0F 0x2C /r] s:SSE, t:CONVERT, w:W|R +CVTTPD2PI Pq,Wpd nil [ 0x66 0x0F 0x2C /r] s:SSE2, t:CONVERT, w:W|R +CVTTSS2SI Gy,Wss nil [ 0xF3 0x0F 0x2C /r] s:SSE, t:CONVERT, w:W|R, e:3 +CVTTSD2SI Gy,Wsd nil [ 0xF2 0x0F 0x2C /r] s:SSE2, t:CONVERT, w:W|R, e:3 +CVTPS2PI Pq,Wq nil [ NP 0x0F 0x2D /r] s:SSE, t:CONVERT, w:W|R +CVTPD2PI Pq,Wpd nil [ 0x66 0x0F 0x2D /r] s:SSE2, t:CONVERT, w:W|R +CVTSS2SI Gy,Wss nil [ 0xF3 0x0F 0x2D /r] s:SSE, t:CONVERT, w:W|R, e:3 +CVTSD2SI Gy,Wsd nil [ 0xF2 0x0F 0x2D /r] s:SSE2, t:CONVERT, w:W|R, e:3 +UCOMISS Vss,Wss Fv [ NP 0x0F 0x2E /r] s:SSE, t:SSE, w:R|R|W, f:COMIS +UCOMISD Vsd,Wsd Fv [ 0x66 0x0F 0x2E /r] s:SSE2, t:SSE2, w:R|R|W, f:COMIS, e:3 +COMISS Vss,Wss Fv [ NP 0x0F 0x2F /r] s:SSE, t:SSE, w:R|R|W, f:COMIS, e:3 +COMISD Vsd,Wsd Fv [ 0x66 0x0F 0x2F /r] s:SSE2, t:SSE2, w:R|R|W, f:COMIS, e:3 + +# 0x30 - 0x3F +WRMSR nil EAX,EDX,ECX,MSR [ 0x0F 0x30] s:PENTIUMREAL, t:SYSTEM, w:R|R|R|W, a:SERIAL, m:KERNEL|NOV86, i:MSR +RDTSC nil EAX,EDX,TSC [ 0x0F 0x31] s:PENTIUMREAL, t:SYSTEM, w:W|W|R +RDMSR nil EAX,EDX,ECX,MSR [ 0x0F 0x32] s:PENTIUMREAL, t:SYSTEM, w:W|W|R|R, m:KERNEL|NOV86, i:MSR +RDPMC nil EAX,EDX,ECX,MSR [ 0x0F 0x33] s:RDPMC, t:SYSTEM, w:W|W|R|R, m:NOSGX +SYSENTER nil SCS,SESP,SEIP,SS,sSP,CS,rIP,Fv [ 0x0F 0x34] s:PPRO, t:SYSCALL, w:R|R|R|W|W|W|W|W, i:SEP, f:IF=0, m:NOREAL|NOSGX +SYSEXIT nil SS,sSP,CS,rIP [ 0x0F 0x35] s:PPRO, t:SYSRET, w:W|W|W|W, i:SEP, m:KERNEL|NOREAL +RDSHR Ed nil [ cyrix 0x0F 0x36 /r] s:CYRIX, t:SYSTEM, w:R +GETSEC nil EAX,EBX [ NP 0x0F 0x37] s:SMX, t:SYSTEM, w:RCW|R, m:KERNEL|NOREAL|NOSGX +WRSHR Ed nil [ cyrix 0x0F 0x37 /r] s:CYRIX, t:SYSTEM, w:W +DMINT nil nil [ 0x0F 0x39] s:CYRIX, t:SYSTEM +CPU_WRITE nil nil [ 0x0F 0x3C] s:CYRIX, t:SYSTEM +CPU_READ nil nil [ 0x0F 0x3D] s:CYRIX, t:SYSTEM +ALTINST nil nil [ 0x0F 0x3F] s:CYRIX, t:SYSTEM + +# 0x40 - 0x4F +CMOVO Gv,Ev Fv [ 0x0F 0x40 /r] s:PPRO, t:CMOV, c:CMOVcc, w:CW|R|R, i:CMOV, f:CO, a:COND +CMOVNO Gv,Ev Fv [ 0x0F 0x41 /r] s:PPRO, t:CMOV, c:CMOVcc, w:CW|R|R, i:CMOV, f:CNO, a:COND +CMOVC Gv,Ev Fv [ 0x0F 0x42 /r] s:PPRO, t:CMOV, c:CMOVcc, w:CW|R|R, i:CMOV, f:CC, a:COND +CMOVNC Gv,Ev Fv [ 0x0F 0x43 /r] s:PPRO, t:CMOV, c:CMOVcc, w:CW|R|R, i:CMOV, f:CNC, a:COND +CMOVZ Gv,Ev Fv [ 0x0F 0x44 /r] s:PPRO, t:CMOV, c:CMOVcc, w:CW|R|R, i:CMOV, f:CZ, a:COND +CMOVNZ Gv,Ev Fv [ 0x0F 0x45 /r] s:PPRO, t:CMOV, c:CMOVcc, w:CW|R|R, i:CMOV, f:CNZ, a:COND +CMOVBE Gv,Ev Fv [ 0x0F 0x46 /r] s:PPRO, t:CMOV, c:CMOVcc, w:CW|R|R, i:CMOV, f:CBE, a:COND +CMOVNBE Gv,Ev Fv [ 0x0F 0x47 /r] s:PPRO, t:CMOV, c:CMOVcc, w:CW|R|R, i:CMOV, f:CNBE, a:COND +CMOVS Gv,Ev Fv [ 0x0F 0x48 /r] s:PPRO, t:CMOV, c:CMOVcc, w:CW|R|R, i:CMOV, f:CS, a:COND +CMOVNS Gv,Ev Fv [ 0x0F 0x49 /r] s:PPRO, t:CMOV, c:CMOVcc, w:CW|R|R, i:CMOV, f:CNS, a:COND +CMOVP Gv,Ev Fv [ 0x0F 0x4A /r] s:PPRO, t:CMOV, c:CMOVcc, w:CW|R|R, i:CMOV, f:CP, a:COND +CMOVNP Gv,Ev Fv [ 0x0F 0x4B /r] s:PPRO, t:CMOV, c:CMOVcc, w:CW|R|R, i:CMOV, f:CNP, a:COND +CMOVL Gv,Ev Fv [ 0x0F 0x4C /r] s:PPRO, t:CMOV, c:CMOVcc, w:CW|R|R, i:CMOV, f:CL, a:COND +CMOVNL Gv,Ev Fv [ 0x0F 0x4D /r] s:PPRO, t:CMOV, c:CMOVcc, w:CW|R|R, i:CMOV, f:CNL, a:COND +CMOVLE Gv,Ev Fv [ 0x0F 0x4E /r] s:PPRO, t:CMOV, c:CMOVcc, w:CW|R|R, i:CMOV, f:CLE, a:COND +CMOVNLE Gv,Ev Fv [ 0x0F 0x4F /r] s:PPRO, t:CMOV, c:CMOVcc, w:CW|R|R, i:CMOV, f:CNLE, a:COND + +# 0x50 - 0x5F +# Note: for MOVMSKPS & MOVMSKPD, the Intel doc says the destination reg is y (32 or 64 bit) but XED says it must be d (only 32 bits). +MOVMSKPS Gd,Ups nil [ NP 0x0F 0x50 /r:reg] s:SSE, t:DATAXFER, w:W|R, e:7 +MOVMSKPD Gd,Upd nil [ 0x66 0x0F 0x50 /r:reg] s:SSE2, t:DATAXFER, w:W|R, e:7 +SQRTPS Vps,Wps nil [ NP 0x0F 0x51 /r] s:SSE, t:SSE, w:W|R, e:2 +SQRTPD Vpd,Wpd nil [ 0x66 0x0F 0x51 /r] s:SSE2, t:SSE, w:W|R, e:2 +SQRTSS Vss,Wss nil [ 0xF3 0x0F 0x51 /r] s:SSE, t:SSE, w:W|R, e:3 +SQRTSD Vsd,Wsd nil [ 0xF2 0x0F 0x51 /r] s:SSE2, t:SSE, w:W|R, e:3 +RSQRTPS Vps,Wps nil [ NP 0x0F 0x52 /r] s:SSE, t:SSE, w:W|R, e:4 +RSQRTSS Vss,Wss nil [ 0xF3 0x0F 0x52 /r] s:SSE, t:SSE, w:W|R, e:5 +RCPPS Vps,Wps nil [ NP 0x0F 0x53 /r] s:SSE, t:SSE, w:W|R, e:4 +RCPSS Vss,Wss nil [ 0xF3 0x0F 0x53 /r] s:SSE, t:SSE, w:W|R, e:5 +ANDPS Vps,Wps nil [ NP 0x0F 0x54 /r] s:SSE, t:LOGICAL_FP, w:RW|R, e:4 +ANDPD Vpd,Wpd nil [ 0x66 0x0F 0x54 /r] s:SSE2, t:LOGICAL_FP, w:RW|R, e:4 +ANDNPS Vps,Wps nil [ NP 0x0F 0x55 /r] s:SSE, t:LOGICAL_FP, w:RW|R, e:4 +ANDNPD Vpd,Wpd nil [ 0x66 0x0F 0x55 /r] s:SSE2, t:LOGICAL_FP, w:RW|R, e:4 +ORPS Vps,Wps nil [ NP 0x0F 0x56 /r] s:SSE, t:LOGICAL_FP, w:RW|R, e:4 +ORPD Vpd,Wpd nil [ 0x66 0x0F 0x56 /r] s:SSE2, t:LOGICAL_FP, w:RW|R, e:4 +XORPS Vps,Wps nil [ NP 0x0F 0x57 /r] s:SSE, t:LOGICAL_FP, w:RW|R, e:4 +XORPD Vpd,Wpd nil [ 0x66 0x0F 0x57 /r] s:SSE2, t:LOGICAL_FP, w:RW|R, e:4 +ADDPS Vps,Wps nil [ NP 0x0F 0x58 /r] s:SSE, t:SSE, w:RW|R, e:2 +ADDPD Vpd,Wpd nil [ 0x66 0x0F 0x58 /r] s:SSE2, t:SSE, w:RW|R, e:2 +ADDSS Vss,Wss nil [ 0xF3 0x0F 0x58 /r] s:SSE, t:SSE, w:RW|R, e:3 +ADDSD Vsd,Wsd nil [ 0xF2 0x0F 0x58 /r] s:SSE2, t:SSE, w:RW|R, e:3 +MULPS Vps,Wps nil [ NP 0x0F 0x59 /r] s:SSE, t:SSE, w:RW|R, e:2 +MULPD Vpd,Wpd nil [ 0x66 0x0F 0x59 /r] s:SSE2, t:SSE, w:RW|R, e:2 +MULSS Vss,Wss nil [ 0xF3 0x0F 0x59 /r] s:SSE, t:SSE, w:RW|R, e:3 +MULSD Vsd,Wsd nil [ 0xF2 0x0F 0x59 /r] s:SSE2, t:SSE, w:RW|R, e:3 +CVTPS2PD Vpd,Wq nil [ NP 0x0F 0x5A /r] s:SSE2, t:CONVERT, w:W|R, e:3 +CVTPD2PS Vps,Wpd nil [ 0x66 0x0F 0x5A /r] s:SSE2, t:CONVERT, w:W|R, e:2 +CVTSS2SD Vsd,Wss nil [ 0xF3 0x0F 0x5A /r] s:SSE2, t:CONVERT, w:W|R, e:3 +CVTSD2SS Vss,Wsd nil [ 0xF2 0x0F 0x5A /r] s:SSE2, t:CONVERT, w:W|R, e:3 +CVTDQ2PS Vps,Wdq nil [ NP 0x0F 0x5B /r] s:SSE2, t:CONVERT, w:W|R, e:2 +CVTPS2DQ Vdq,Wps nil [ 0x66 0x0F 0x5B /r] s:SSE2, t:CONVERT, w:W|R, e:2 +CVTTPS2DQ Vdq,Wps nil [ 0xF3 0x0F 0x5B /r] s:SSE2, t:CONVERT, w:W|R, e:2 +SUBPS Vps,Wps nil [ NP 0x0F 0x5C /r] s:SSE, t:SSE, w:RW|R, e:2 +SUBPD Vpd,Wpd nil [ 0x66 0x0F 0x5C /r] s:SSE2, t:SSE, w:RW|R, e:2 +SUBSS Vss,Wss nil [ 0xF3 0x0F 0x5C /r] s:SSE, t:SSE, w:RW|R, e:3 +SUBSD Vsd,Wsd nil [ 0xF2 0x0F 0x5C /r] s:SSE2, t:SSE, w:RW|R, e:3 +MINPS Vps,Wps nil [ NP 0x0F 0x5D /r] s:SSE, t:SSE, w:RW|R, e:2 +MINPD Vpd,Wpd nil [ 0x66 0x0F 0x5D /r] s:SSE2, t:SSE, w:RW|R, e:2 +MINSS Vss,Wss nil [ 0xF3 0x0F 0x5D /r] s:SSE, t:SSE, w:RW|R, e:3 +MINSD Vsd,Wsd nil [ 0xF2 0x0F 0x5D /r] s:SSE2, t:SSE, w:RW|R, e:3 +DIVPS Vps,Wps nil [ NP 0x0F 0x5E /r] s:SSE, t:SSE, w:RW|R, e:2 +DIVPD Vpd,Wpd nil [ 0x66 0x0F 0x5E /r] s:SSE2, t:SSE, w:RW|R, e:2 +DIVSS Vss,Wss nil [ 0xF3 0x0F 0x5E /r] s:SSE, t:SSE, w:RW|R, e:3 +DIVSD Vsd,Wsd nil [ 0xF2 0x0F 0x5E /r] s:SSE2, t:SSE, w:RW|R, e:3 +MAXPS Vps,Wps nil [ NP 0x0F 0x5F /r] s:SSE, t:SSE, w:RW|R, e:2 +MAXPD Vpd,Wpd nil [ 0x66 0x0F 0x5F /r] s:SSE2, t:SSE, w:RW|R, e:2 +MAXSS Vss,Wss nil [ 0xF3 0x0F 0x5F /r] s:SSE, t:SSE, w:RW|R, e:3 +MAXSD Vsd,Wsd nil [ 0xF2 0x0F 0x5F /r] s:SSE2, t:SSE, w:RW|R, e:3 + +# 0x60 - 0x6F +PUNPCKLBW Pq,Qd nil [ NP 0x0F 0x60 /r] s:MMX, t:MMX, w:RW|R +PUNPCKLBW Vx,Wx nil [ 0x66 0x0F 0x60 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PUNPCKLWD Pq,Qd nil [ NP 0x0F 0x61 /r] s:MMX, t:MMX, w:RW|R +PUNPCKLWD Vx,Wx nil [ 0x66 0x0F 0x61 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PUNPCKLDQ Pq,Qd nil [ NP 0x0F 0x62 /r] s:MMX, t:MMX, w:RW|R +PUNPCKLDQ Vx,Wx nil [ 0x66 0x0F 0x62 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PACKSSWB Pq,Qq nil [ NP 0x0F 0x63 /r] s:MMX, t:MMX, w:RW|R +PACKSSWB Vx,Wx nil [ 0x66 0x0F 0x63 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PCMPGTB Pq,Qq nil [ NP 0x0F 0x64 /r] s:MMX, t:MMX, w:RW|R +PCMPGTB Vx,Wx nil [ 0x66 0x0F 0x64 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PCMPGTW Pq,Qq nil [ NP 0x0F 0x65 /r] s:MMX, t:MMX, w:RW|R +PCMPGTW Vx,Wx nil [ 0x66 0x0F 0x65 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PCMPGTD Pq,Qq nil [ NP 0x0F 0x66 /r] s:MMX, t:MMX, w:RW|R +PCMPGTD Vx,Wx nil [ 0x66 0x0F 0x66 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PACKUSWB Pq,Qq nil [ NP 0x0F 0x67 /r] s:MMX, t:MMX, w:RW|R +PACKUSWB Vx,Wx nil [ 0x66 0x0F 0x67 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PUNPCKHBW Pq,Qq nil [ NP 0x0F 0x68 /r] s:MMX, t:MMX, w:RW|R +PUNPCKHBW Vx,Wx nil [ 0x66 0x0F 0x68 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PUNPCKHWD Pq,Qq nil [ NP 0x0F 0x69 /r] s:MMX, t:MMX, w:RW|R +PUNPCKHWD Vx,Wx nil [ 0x66 0x0F 0x69 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PUNPCKHDQ Pq,Qq nil [ NP 0x0F 0x6A /r] s:MMX, t:MMX, w:RW|R +PUNPCKHDQ Vx,Wx nil [ 0x66 0x0F 0x6A /r] s:SSE2, t:SSE, w:RW|R, e:4 +PACKSSDW Pq,Qq nil [ NP 0x0F 0x6B /r] s:MMX, t:MMX, w:RW|R +PACKSSDW Vx,Wx nil [ 0x66 0x0F 0x6B /r] s:SSE2, t:SSE, w:RW|R, e:4 +PUNPCKLQDQ Vx,Wx nil [ 0x66 0x0F 0x6C /r] s:SSE2, t:SSE, w:RW|R, e:4 +PUNPCKHQDQ Vx,Wx nil [ 0x66 0x0F 0x6D /r] s:SSE2, t:SSE, w:RW|R, e:4 +MOVD Pq,Ey nil [ NP 0x0F 0x6E /r] s:MMX, t:DATAXFER, w:W|R +MOVQ Pq,Ey nil [ rexw NP 0x0F 0x6E /r] s:SSE2, t:DATAXFER, w:W|R, e:5 +MOVD Vdq,Ey nil [ 0x66 0x0F 0x6E /r] s:SSE2, t:DATAXFER, w:W|R, e:5 +MOVQ Vdq,Ey nil [ 0x66 rexw 0x0F 0x6E /r] s:SSE2, t:DATAXFER, w:W|R, e:5 +MOVQ Pq,Qq nil [ NP 0x0F 0x6F /r] s:MMX, t:DATAXFER, w:W|R +MOVDQA Vx,Wx nil [ 0x66 0x0F 0x6F /r] s:SSE2, t:DATAXFER, w:W|R, e:1 +MOVDQU Vx,Wx nil [ 0xF3 0x0F 0x6F /r] s:SSE2, t:DATAXFER, w:W|R, e:4 + +# 0x70 - 0x7F +PSHUFW Pq,Qq,Ib nil [ NP 0x0F 0x70 /r ib] s:MMX, t:MMX, w:W|R|R +PSHUFD Vx,Wx,Ib nil [ 0x66 0x0F 0x70 /r ib] s:SSE2, t:SSE, w:W|R|R, e:4 +PSHUFHW Vx,Wx,Ib nil [ 0xF3 0x0F 0x70 /r ib] s:SSE2, t:SSE, w:W|R|R, e:4 +PSHUFLW Vx,Wx,Ib nil [ 0xF2 0x0F 0x70 /r ib] s:SSE2, t:SSE, w:W|R|R, e:4 +PSRLW Nq,Ib nil [ NP 0x0F 0x71 /2:reg ib] s:MMX, t:MMX, w:RW|R +PSRLW Ux,Ib nil [ 0x66 0x0F 0x71 /2:reg ib] s:SSE2, t:SSE, w:RW|R, e:4 +PSRAW Nq,Ib nil [ NP 0x0F 0x71 /4:reg ib] s:MMX, t:MMX, w:RW|R +PSRAW Ux,Ib nil [ 0x66 0x0F 0x71 /4:reg ib] s:SSE2, t:SSE, w:RW|R, e:4 +PSLLW Nq,Ib nil [ NP 0x0F 0x71 /6:reg ib] s:MMX, t:MMX, w:RW|R +PSLLW Ux,Ib nil [ 0x66 0x0F 0x71 /6:reg ib] s:SSE2, t:SSE, w:RW|R, e:4 +PSRLD Nq,Ib nil [ NP 0x0F 0x72 /2:reg ib] s:MMX, t:MMX, w:RW|R +PSRLD Ux,Ib nil [ 0x66 0x0F 0x72 /2:reg ib] s:SSE2, t:SSE, w:RW|R, e:4 +PSRAD Nq,Ib nil [ NP 0x0F 0x72 /4:reg ib] s:MMX, t:MMX, w:RW|R +PSRAD Ux,Ib nil [ 0x66 0x0F 0x72 /4:reg ib] s:SSE2, t:SSE, w:RW|R, e:4 +PSLLD Nq,Ib nil [ NP 0x0F 0x72 /6:reg ib] s:MMX, t:MMX, w:RW|R +PSLLD Ux,Ib nil [ 0x66 0x0F 0x72 /6:reg ib] s:SSE2, t:SSE, w:RW|R, e:4 +PSRLQ Nq,Ib nil [ NP 0x0F 0x73 /2:reg ib] s:MMX, t:MMX, w:RW|R +PSRLQ Ux,Ib nil [ 0x66 0x0F 0x73 /2:reg ib] s:SSE2, t:SSE, w:RW|R, e:4 +PSRLDQ Ux,Ib nil [ 0x66 0x0F 0x73 /3:reg ib] s:SSE2, t:SSE, w:RW|R, e:7 +PSLLQ Nq,Ib nil [ NP 0x0F 0x73 /6:reg ib] s:MMX, t:MMX, w:RW|R +PSLLQ Ux,Ib nil [ 0x66 0x0F 0x73 /6:reg ib] s:SSE2, t:SSE, w:RW|R, e:4 +PSLLDQ Ux,Ib nil [ 0x66 0x0F 0x73 /7:reg ib] s:SSE2, t:SSE, w:RW|R, e:7 +PCMPEQB Pq,Qq nil [ NP 0x0F 0x74 /r] s:MMX, t:MMX, w:RW|R +PCMPEQB Vx,Wx nil [ 0x66 0x0F 0x74 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PCMPEQW Pq,Qq nil [ NP 0x0F 0x75 /r] s:MMX, t:MMX, w:RW|R +PCMPEQW Vx,Wx nil [ 0x66 0x0F 0x75 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PCMPEQD Pq,Qq nil [ NP 0x0F 0x76 /r] s:MMX, t:MMX, w:RW|R +PCMPEQD Vx,Wx nil [ 0x66 0x0F 0x76 /r] s:SSE2, t:SSE, w:RW|R, e:4 +EMMS nil nil [ NP 0x0F 0x77] s:MMX, t:MMX +VMREAD Ey,Gy Fv [ NP 0x0F 0x78 /r] s:VTX, t:VTX, w:RW|R|W, f:VMX, a:F64, m:VMXROOT +INSERTQ Vdq,Udq,Ib,Ib nil [ 0xF2 0x0F 0x78 /r ib ib] s:SSE4A, t:BITBYTE, w:W|R|R|R +EXTRQ Uq,Ib,Ib nil [ 0x66 0x0F 0x78 /0 modrmpmp ib ib] s:SSE4A, t:BITBYTE, w:W|R|R +VMWRITE Gy,Ey Fv [ NP 0x0F 0x79 /r] s:VTX, t:VTX, w:R|R|W, f:VMX, a:F64, m:VMXROOT +EXTRQ Vdq,Uq nil [ 0x66 0x0F 0x79 /r:reg] s:SSE4A, t:BITBYTE, w:W|R +INSERTQ Vdq,Udq nil [ 0xF2 0x0F 0x79 /r:reg] s:SSE4A, t:BITBYTE, w:W|R +HADDPD Vpd,Wpd nil [ 0x66 0x0F 0x7C /r] s:SSE3, t:SSE, w:RW|R, e:2 +HADDPS Vps,Wps nil [ 0xF2 0x0F 0x7C /r] s:SSE3, t:SSE, w:RW|R, e:2 +HSUBPD Vpd,Wpd nil [ 0x66 0x0F 0x7D /r] s:SSE3, t:SSE, w:RW|R, e:2 +HSUBPS Vps,Wps nil [ 0xF2 0x0F 0x7D /r] s:SSE3, t:SSE, w:RW|R, e:2 +MOVD Ey,Pd nil [ NP 0x0F 0x7E /r] s:MMX, t:DATAXFER, w:W|R +MOVQ Ey,Pq nil [ rexw NP 0x0F 0x7E /r] s:MMX, t:DATAXFER, w:W|R +MOVD Ey,Vdq nil [ 0x66 0x0F 0x7E /r] s:SSE2, t:DATAXFER, w:W|R, e:5 +MOVQ Ey,Vdq nil [ 0x66 rexw 0x0F 0x7E /r] s:SSE2, t:DATAXFER, w:W|R, e:5 +MOVQ Vdq,Wq nil [ 0xF3 0x0F 0x7E /r] s:SSE2, t:DATAXFER, w:W|R, e:5 +MOVQ Qq,Pq nil [ NP 0x0F 0x7F /r] s:MMX, t:DATAXFER, w:W|R +MOVDQA Wx,Vx nil [ 0x66 0x0F 0x7F /r] s:SSE2, t:DATAXFER, w:W|R, e:1 +MOVDQU Wx,Vx nil [ 0xF3 0x0F 0x7F /r] s:SSE2, t:DATAXFER, w:W|R, e:4 + +# SMM instructions on Cyrix CPUs. +SVDC Ms,Sw nil [ cyrix 0x0F 0x78 /r:mem] s:CYRIX_SMM, t:SEGOP, w:W|R +RSDC Sw,Ms nil [ cyrix 0x0F 0x79 /r:mem] s:CYRIX_SMM, t:SEGOP, w:R|R +SVLDT Ms nil [ cyrix 0x0F 0x7A /r:mem] s:CYRIX_SMM, t:SEGOP, w:W +RSLDT Ms nil [ cyrix 0x0F 0x7B /r:mem] s:CYRIX_SMM, t:SEGOP, w:R +SVTS Ms nil [ cyrix 0x0F 0x7C /r:mem] s:CYRIX_SMM, t:SEGOP, w:W +RSTS Ms nil [ cyrix 0x0F 0x7D /r:mem] s:CYRIX_SMM, t:SEGOP, w:R +SMINT nil nil [ cyrix 0x0F 0x7E] s:CYRIX_SMM, t:SEGOP + +# 0x80 - 0x8F +JO Jz rIP,Fv [ 0x0F 0x80 cz] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CO, a:F64|COND, p:BND|BH +JNO Jz rIP,Fv [ 0x0F 0x81 cz] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CNO, a:F64|COND, p:BND|BH +JC Jz rIP,Fv [ 0x0F 0x82 cz] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CC, a:F64|COND, p:BND|BH +JNC Jz rIP,Fv [ 0x0F 0x83 cz] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CNC, a:F64|COND, p:BND|BH +JZ Jz rIP,Fv [ 0x0F 0x84 cz] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CZ, a:F64|COND, p:BND|BH +JNZ Jz rIP,Fv [ 0x0F 0x85 cz] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CNZ, a:F64|COND, p:BND|BH +JBE Jz rIP,Fv [ 0x0F 0x86 cz] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CBE, a:F64|COND, p:BND|BH +JNBE Jz rIP,Fv [ 0x0F 0x87 cz] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CNBE, a:F64|COND, p:BND|BH +JS Jz rIP,Fv [ 0x0F 0x88 cz] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CS, a:F64|COND, p:BND|BH +JNS Jz rIP,Fv [ 0x0F 0x89 cz] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CNS, a:F64|COND, p:BND|BH +JP Jz rIP,Fv [ 0x0F 0x8A cz] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CP, a:F64|COND, p:BND|BH +JNP Jz rIP,Fv [ 0x0F 0x8B cz] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CNP, a:F64|COND, p:BND|BH +JL Jz rIP,Fv [ 0x0F 0x8C cz] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CL, a:F64|COND, p:BND|BH +JNL Jz rIP,Fv [ 0x0F 0x8D cz] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CNL, a:F64|COND, p:BND|BH +JLE Jz rIP,Fv [ 0x0F 0x8E cz] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CLE, a:F64|COND, p:BND|BH +JNLE Jz rIP,Fv [ 0x0F 0x8F cz] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CNLE, a:F64|COND, p:BND|BH + +# 0x90 - 0x9F +SETO Eb Fv [ 0x0F 0x90 /r] s:I386, t:BITBYTE, c:SETcc, w:W|R, f:CO, a:COND +SETNO Eb Fv [ 0x0F 0x91 /r] s:I386, t:BITBYTE, c:SETcc, w:W|R, f:CNO, a:COND +SETC Eb Fv [ 0x0F 0x92 /r] s:I386, t:BITBYTE, c:SETcc, w:W|R, f:CC, a:COND +SETNC Eb Fv [ 0x0F 0x93 /r] s:I386, t:BITBYTE, c:SETcc, w:W|R, f:CNC, a:COND +SETZ Eb Fv [ 0x0F 0x94 /r] s:I386, t:BITBYTE, c:SETcc, w:W|R, f:CZ, a:COND +SETNZ Eb Fv [ 0x0F 0x95 /r] s:I386, t:BITBYTE, c:SETcc, w:W|R, f:CNZ, a:COND +SETBE Eb Fv [ 0x0F 0x96 /r] s:I386, t:BITBYTE, c:SETcc, w:W|R, f:CBE, a:COND +SETNB Eb Fv [ 0x0F 0x97 /r] s:I386, t:BITBYTE, c:SETcc, w:W|R, f:CNBE, a:COND +SETS Eb Fv [ 0x0F 0x98 /r] s:I386, t:BITBYTE, c:SETcc, w:W|R, f:CS, a:COND +SETNS Eb Fv [ 0x0F 0x99 /r] s:I386, t:BITBYTE, c:SETcc, w:W|R, f:CNS, a:COND +SETP Eb Fv [ 0x0F 0x9A /r] s:I386, t:BITBYTE, c:SETcc, w:W|R, f:CP, a:COND +SETNP Eb Fv [ 0x0F 0x9B /r] s:I386, t:BITBYTE, c:SETcc, w:W|R, f:CNP, a:COND +SETL Eb Fv [ 0x0F 0x9C /r] s:I386, t:BITBYTE, c:SETcc, w:W|R, f:CL, a:COND +SETNL Eb Fv [ 0x0F 0x9D /r] s:I386, t:BITBYTE, c:SETcc, w:W|R, f:CNL, a:COND +SETLE Eb Fv [ 0x0F 0x9E /r] s:I386, t:BITBYTE, c:SETcc, w:W|R, f:CLE, a:COND +SETNLE Eb Fv [ 0x0F 0x9F /r] s:I386, t:BITBYTE, c:SETcc, w:W|R, f:CNLE, a:COND + +# 0xA0 - 0xAF +PUSH FS Kv [ 0x0F 0xA0] s:I86, t:PUSH, w:R|W, a:D64, m:NOSGX +POP FS Kv [ 0x0F 0xA1] s:I86, t:POP, w:W|R, a:D64, m:NOSGX +CPUID nil EAX,EBX,ECX,EDX [ 0x0F 0xA2] s:I486REAL, t:MISC, w:RW|W|CRW|W, a:SERIAL, m:NOSGX|NOTSX +BT Ev,Gv Fv [ 0x0F 0xA3 /r bitbase] s:I386, t:BITBYTE, w:R|R|W, f:BT +SHLD Ev,Gv,Ib Fv [ 0x0F 0xA4 /r ib] s:I386, t:SHIFT, w:RCW|R|R|W, f:SHIFTD +SHLD Ev,Gv,CL Fv [ 0x0F 0xA5 /r] s:I386, t:SHIFT, w:RCW|R|R|W, f:SHIFTD + +# Cyrix 'security' instructions. +MONTMUL nil nil [ 0xF3 0x0F 0xA6 /0xC0] s:CYRIX, t:PADLOCK, p:REP +XSHA1 nil nil [ 0xF3 0x0F 0xA6 /0xC8] s:CYRIX, t:PADLOCK, p:REP +XSHA256 nil nil [ 0xF3 0x0F 0xA6 /0xD0] s:CYRIX, t:PADLOCK, p:REP +XSTORE nil nil [ 0x0F 0xA7 /0xC0] s:CYRIX, t:PADLOCK, p:REP +XCRYPTECB nil nil [ 0xF3 0x0F 0xA7 /0xC8] s:CYRIX, t:PADLOCK, p:REP +XCRYPTCBC nil nil [ 0xF3 0x0F 0xA7 /0xD0] s:CYRIX, t:PADLOCK, p:REP +XCRYPTCTR nil nil [ 0xF3 0x0F 0xA7 /0xD8] s:CYRIX, t:PADLOCK, p:REP +XCRYPTCFB nil nil [ 0xF3 0x0F 0xA7 /0xE0] s:CYRIX, t:PADLOCK, p:REP +XCRYPTOFB nil nil [ 0xF3 0x0F 0xA7 /0xE8] s:CYRIX, t:PADLOCK, p:REP + +PUSH GS Kv [ 0x0F 0xA8] s:I86, t:PUSH, w:R|W, a:D64, m:NOSGX +POP GS Kv [ 0x0F 0xA9] s:I86, t:POP, w:W|R, a:D64, m:NOSGX +RSM nil CS,rIP,Fv [ 0x0F 0xAA] s:I486, t:SYSRET, w:W|W|W, a:SERIAL, m:SMM +BTS Ev,Gv Fv [ 0x0F 0xAB /r bitbase] s:I386, t:BITBYTE, w:RW|R|W, f:BT, p:HLE|LOCK +SHRD Ev,Gv,Ib Fv [ 0x0F 0xAC /r ib] s:I386, t:SHIFT, w:RCW|R|R|W, f:SHIFTD +SHRD Ev,Gv,CL Fv [ 0x0F 0xAD /r] s:I386, t:SHIFT, w:RCW|R|R|W, f:SHIFTD + +FXSAVE Mrx BANK [ NP 0x0F 0xAE /0:mem] s:FXSAVE, t:SSE, w:W|R +FXRSTOR Mrx BANK [ NP 0x0F 0xAE /1:mem] s:FXSAVE, t:SSE, w:R|W +LDMXCSR Md MXCSR [ NP 0x0F 0xAE /2:mem] s:SSE, t:SSE, w:R|W +STMXCSR Md MXCSR [ NP 0x0F 0xAE /3:mem] s:SSE, t:SSE, w:W|R +XSAVE M? EDX,EAX,XCR0,BANK [ NP 0x0F 0xAE /4:mem] s:XSAVE, t:XSAVE, c:XSAVE, w:W|R|R|R|R +XSAVE64 M? EDX,EAX,XCR0,BANK [ rexw NP 0x0F 0xAE /4:mem] s:XSAVE, t:XSAVE, c:XSAVE, w:W|R|R|R|R +XRSTOR M? EDX,EAX,XCR0,BANK [ NP 0x0F 0xAE /5:mem] s:XSAVE, t:XSAVE, c:XRSTOR, w:R|R|R|R|W +XRSTOR64 M? EDX,EAX,XCR0,BANK [ rexw NP 0x0F 0xAE /5:mem] s:XSAVE, t:XSAVE, c:XRSTOR, w:R|R|R|R|W +XSAVEOPT M? EDX,EAX,XCR0,BANK [ NP 0x0F 0xAE /6:mem] s:XSAVE, t:XSAVE, c:XSAVEOPT, w:W|R|R|R|R +XSAVEOPT64 M? EDX,EAX,XCR0,BANK [ rexw NP 0x0F 0xAE /6:mem] s:XSAVE, t:XSAVE, c:XSAVEOPT, w:W|R|R|R|R +CLWB Mcl nil [ 0x66 0x0F 0xAE /6:mem] s:CLWB, t:MISC, w:W +CLRSSBSY Mq nil [ 0xF3 0x0F 0xAE /6:mem] s:CET, t:CET, a:SHS, w:RW +CLFLUSH Mcl nil [ NP 0x0F 0xAE /7:mem] s:CLFSH, t:MISC, w:R +CLFLUSHOPT Mcl nil [ 0x66 0x0F 0xAE /7:mem] s:CLFSHOPT, t:MISC, w:R + +PTWRITE Ey nil [ 0xF3 0x0F 0xAE /4] s:PTWRITE, t:PTWRITE, w:R, a:NO66 + +RDFSBASE Ry FSBASE [ o64 0xF3 0x0F 0xAE /0:reg] s:RDWRFSGS, t:RDWRFSGS, w:W|R, m:O64 +RDGSBASE Ry GSBASE [ o64 0xF3 0x0F 0xAE /1:reg] s:RDWRFSGS, t:RDWRFSGS, w:W|R, m:O64 +WRFSBASE Ry FSBASE [ o64 0xF3 0x0F 0xAE /2:reg] s:RDWRFSGS, t:RDWRFSGS, w:R|W, m:O64 +WRGSBASE Ry GSBASE [ o64 0xF3 0x0F 0xAE /3:reg] s:RDWRFSGS, t:RDWRFSGS, w:R|W, m:O64 +INCSSPD Rd SHS,SSP [ 0xF3 0x0F 0xAE /5:reg] s:CET, t:CET, c:INCSSP, w:R|R|RW +INCSSPQ Rq SHS,SSP [ 0xF3 rexw 0x0F 0xAE /5:reg] s:CET, t:CET, c:INCSSP, w:R|R|RW +LFENCE nil nil [ NP 0x0F 0xAE /5:reg] s:SSE2, t:MISC +UMONITOR mMb Fv [ 0xF3 0x0F 0xAE /6:reg] s:WAITPKG, t:WAITPKG, w:R|W, f:WAITPKG, m:NOTSX +UMWAIT Ry EDX,EAX [ 0xF2 0x0F 0xAE /6:reg] s:WAITPKG, t:WAITPKG, w:R|R|R, m:NOTSX +TPAUSE Ry EDX,EAX,Fv [ 0x66 0x0F 0xAE /6:reg] s:WAITPKG, t:WAITPKG, w:R|R|R|W, f:WAITPKG +MFENCE nil nil [ NP 0x0F 0xAE /6:reg] s:SSE2, t:MISC +SFENCE nil nil [ NP 0x0F 0xAE /7:reg] s:SSE2, t:MISC +# Intel dropped support for the PCOMMIT instruction before it was shipped in any CPU. The following instruction wil ALWAYS cause a #UD from now on. +PCOMMIT nil nil [ 0x66 0x0F 0xAE /7:reg] s:PCOMMIT, t:MISC + +IMUL Gv,Ev Fv [ 0x0F 0xAF /r] s:I86, t:ARITH, w:RW|R|W, f:MUL + +# 0xB0 - 0xBF +CMPXCHG Eb,Gb AL,Fv [ 0x0F 0xB0 /r] s:I486REAL, t:SEMAPHORE, w:RCW|R|RCW|W, f:ARITH, p:LOCK|HLE +CMPXCHG Ev,Gv rAX,Fv [ 0x0F 0xB1 /r] s:I486REAL, t:SEMAPHORE, w:RCW|R|RCW|W, f:ARITH, p:LOCK|HLE +LSS Gv,Mp SS [ 0x0F 0xB2 /r:mem] s:I386, t:SEGOP, w:W|R|W, m:NOSGX +BTR Ev,Gv Fv [ 0x0F 0xB3 /r bitbase] s:I386, t:BITBYTE, w:RW|R|W, f:BT, p:LOCK|HLE +LFS Gv,Mp FS [ 0x0F 0xB4 /r:mem] s:I386, t:SEGOP, w:W|R|W, m:NOSGX +LGS Gv,Mp GS [ 0x0F 0xB5 /r:mem] s:I386, t:SEGOP, w:W|R|W, m:NOSGX +MOVZX Gv,Eb nil [ 0x0F 0xB6 /r] s:I386, t:DATAXFER, w:W|R +MOVZX Gv,Ew nil [ 0x0F 0xB7 /r] s:I386, t:DATAXFER, w:W|R +JMPE Jz rIP [ 0x0F 0xB8 cz] s:I64, t:UNCOND_BR, w:R|W, m:NO64 +POPCNT Gv,Ev Fv [ a0xF3 0x0F 0xB8 /r] s:POPCNT, t:SSE, w:W|R|W, f:CF=0|PF=0|AF=0|ZF=m|SF=0|OF=0 +UD1 Gd,Ed nil [ 0x0F 0xB9 /r] s:UD, t:UD, w:R|R +BT Ev,Ib Fv [ 0x0F 0xBA /4 ib] s:I386, t:BITBYTE, w:R|R|W, f:BT +BTS Ev,Ib Fv [ 0x0F 0xBA /5 ib] s:I386, t:BITBYTE, w:RW|R|W, f:BT, p:LOCK|HLE +BTR Ev,Ib Fv [ 0x0F 0xBA /6 ib] s:I386, t:BITBYTE, w:RW|R|W, f:BT, p:LOCK|HLE +BTC Ev,Ib Fv [ 0x0F 0xBA /7 ib] s:I386, t:BITBYTE, w:RW|R|W, f:BT, p:LOCK|HLE +BTC Ev,Gv Fv [ 0x0F 0xBB /r bitbase] s:I386, t:I386, w:RW|R|W, f:BT, p:LOCK|HLE +BSF Gv,Ev Fv [ 0x0F 0xBC /r] s:I386, t:I386, w:CW|R|W, f:CF=u|PF=u|AF=u|ZF=m|SF=u|OF=u +TZCNT Gv,Ev Fv [ a0xF3 0x0F 0xBC /r] s:BMI1, t:BMI1, w:W|R|W, f:CF=m|PF=u|AF=u|ZF=m|SF=u|OF=u +BSR Gv,Ev Fv [ 0x0F 0xBD /r] s:I386, t:BITBYTE, w:CW|R|W, f:CF=u|PF=u|AF=u|ZF=m|SF=u|OF=u +LZCNT Gv,Ev Fv [ a0xF3 0x0F 0xBD /r] s:LZCNT, t:LZCNT, w:W|R|W, f:CF=m|PF=u|AF=u|ZF=m|SF=u|OF=u +MOVSX Gv,Eb nil [ 0x0F 0xBE /r] s:I386, t:DATAXFER, w:W|R +MOVSX Gv,Ew nil [ 0x0F 0xBF /r] s:I386, t:DATAXFER, w:W|R + +# 0xC0 - 0xCF +XADD Eb,Gb Fv [ 0x0F 0xC0 /r] s:I486REAL, t:SEMAPHORE, w:RW|RW|W, f:ARITH, p:LOCK|HLE +XADD Ev,Gv Fv [ 0x0F 0xC1 /r] s:I486REAL, t:SEMAPHORE, w:RW|RW|W, f:ARITH, p:LOCK|HLE +CMPPS Vps,Wps,Ib nil [ NP 0x0F 0xC2 /r ib] s:SSE, t:SSE, w:RW|R|R, e:2 +CMPPD Vpd,Wpd,Ib nil [ 0x66 0x0F 0xC2 /r ib] s:SSE2, t:SSE, w:RW|R|R, e:2 +CMPSS Vss,Wss,Ib nil [ 0xF3 0x0F 0xC2 /r ib] s:SSE, t:SSE, w:RW|R|R, e:3 +CMPSD Vsd,Wsd,Ib nil [ 0xF2 0x0F 0xC2 /r ib] s:SSE2, t:SSE, w:RW|R|R, e:3 +MOVNTI My,Gy nil [ NP 0x0F 0xC3 /r:mem] s:SSE2, t:DATAXFER, w:W|R +PINSRW Pq,Rd,Ib nil [ NP 0x0F 0xC4 /r:reg ib] s:MMX, t:MMX, w:RW|R|R +PINSRW Pq,Mw,Ib nil [ NP 0x0F 0xC4 /r:mem ib] s:MMX, t:MMX, w:RW|R|R +PINSRW Vdq,Rd,Ib nil [ 0x66 0x0F 0xC4 /r:reg ib] s:SSE2, t:SSE, w:RW|R|R, e:5 +PINSRW Vdq,Mw,Ib nil [ 0x66 0x0F 0xC4 /r:mem ib] s:SSE2, t:SSE, w:RW|R|R, e:5 +PEXTRW Gy,Nq,Ib nil [ NP 0x0F 0xC5 /r:reg ib] s:MMX, t:MMX, w:W|R|R +PEXTRW Gy,Udq,Ib nil [ 0x66 0x0F 0xC5 /r:reg ib] s:SSE2, t:SSE, w:W|R|R, e:5 +SHUFPS Vps,Wps,Ib nil [ NP 0x0F 0xC6 /r ib] s:SSE, t:SSE, w:RW|R|R, e:4 +SHUFPD Vpd,Wpd,Ib nil [ 0x66 0x0F 0xC6 /r ib] s:SSE2, t:SSE, w:RW|R|R, e:4 +CMPXCHG8B Mq EDX,EAX,ECX,EBX,Fv [ 0x0F 0xC7 /1:mem] s:PENTIUMREAL, t:SEMAPHORE, w:RCW|RCW|RCW|R|R|W, i:CX8, f:ZF=m, p:LOCK|HLE +CMPXCHG16B Mdq RDX,RAX,RCX,RBX,Fv [ rexw 0x0F 0xC7 /1:mem] s:CMPXCHG16B, t:SEMAPHORE, w:RCW|RCW|RCW|R|R|W, i:CX8, f:ZF=m, p:LOCK|HLE +XRSTORS M? EDX,EAX,XCR0,BANK [ NP 0x0F 0xC7 /3:mem] s:XSAVES, t:XSAVE, c:XRSTORS, w:R|R|R|R|W +XRSTORS64 M? EDX,EAX,XCR0,BANK [ rexw NP 0x0F 0xC7 /3:mem] s:XSAVES, t:XSAVE, c:XRSTORS, w:R|R|R|R|W +XSAVEC M? EDX,EAX,XCR0,BANK [ NP 0x0F 0xC7 /4:mem] s:XSAVEC, t:XSAVE, c:XSAVEC, w:W|R|R|R|R +XSAVEC64 M? EDX,EAX,XCR0,BANK [ rexw NP 0x0F 0xC7 /4:mem] s:XSAVEC, t:XSAVE, c:XSAVEC, w:W|R|R|R|R +XSAVES M? EDX,EAX,XCR0,BANK [ NP 0x0F 0xC7 /5:mem] s:XSAVES, t:XSAVE, c:XSAVES, w:W|R|R|R|R +XSAVES64 M? EDX,EAX,XCR0,BANK [ rexw NP 0x0F 0xC7 /5:mem] s:XSAVES, t:XSAVE, c:XSAVES, w:W|R|R|R|R +VMPTRLD Mq Fv [ NP 0x0F 0xC7 /6:mem] s:VTX, t:VTX, w:R|W, f:VMX, m:VMXROOT +VMCLEAR Mq Fv [ 0x66 0x0F 0xC7 /6:mem] s:VTX, t:VTX, w:R|W, f:VMX, m:VMXROOT +VMXON Mq Fv [ 0xF3 0x0F 0xC7 /6:mem] s:VTX, t:VTX, w:R|W, f:VMX, m:VMXROOT +VMPTRST Mq Fv [ NP 0x0F 0xC7 /7:mem] s:VTX, t:VTX, w:W|W, f:VMX, m:VMXROOT +RDRAND Rv Fv [ 0x0F 0xC7 /6:reg] s:RDRAND, t:RDRAND, w:W|W, f:CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0 +RDRAND Rv Fv [ 0x66 0x0F 0xC7 /6:reg] s:RDRAND, t:RDRAND, a:S66, w:W|W, f:CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0 +RDSEED Rv Fv [ 0x0F 0xC7 /7:reg] s:RDSEED, t:RDSEED, w:W|W, f:CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0 +RDSEED Rv Fv [ 0x66 0x0F 0xC7 /7:reg] s:RDSEED, t:RDSEED, a:S66, w:W|W, f:CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0 +RDPID Rv TSCAUX [ 0xF3 0x0F 0xC7 /7:reg] s:RDPID, t:RDPID, w:W|R + +BSWAP Zv nil [ 0x0F 0xC8] s:I486REAL, t:DATAXFER, w:RW +BSWAP Zv nil [ 0x0F 0xC9] s:I486REAL, t:DATAXFER, w:RW +BSWAP Zv nil [ 0x0F 0xCA] s:I486REAL, t:DATAXFER, w:RW +BSWAP Zv nil [ 0x0F 0xCB] s:I486REAL, t:DATAXFER, w:RW +BSWAP Zv nil [ 0x0F 0xCC] s:I486REAL, t:DATAXFER, w:RW +BSWAP Zv nil [ 0x0F 0xCD] s:I486REAL, t:DATAXFER, w:RW +BSWAP Zv nil [ 0x0F 0xCE] s:I486REAL, t:DATAXFER, w:RW +BSWAP Zv nil [ 0x0F 0xCF] s:I486REAL, t:DATAXFER, w:RW + +# 0xD0 - 0xDF +ADDSUBPD Vpd,Wpd nil [ 0x66 0x0F 0xD0 /r] s:SSE3, t:SSE, w:RW|R, e:2 +ADDSUBPS Vps,Wps nil [ 0xF2 0x0F 0xD0 /r] s:SSE3, t:SSE, w:RW|R, e:2 +PSRLW Pq,Qq nil [ NP 0x0F 0xD1 /r] s:MMX, t:MMX, w:RW|R +PSRLW Vx,Wx nil [ 0x66 0x0F 0xD1 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PSRLD Pq,Qq nil [ NP 0x0F 0xD2 /r] s:MMX, t:MMX, w:RW|R +PSRLD Vx,Wx nil [ 0x66 0x0F 0xD2 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PSRLQ Pq,Qq nil [ NP 0x0F 0xD3 /r] s:MMX, t:MMX, w:RW|R +PSRLQ Vx,Wx nil [ 0x66 0x0F 0xD3 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PADDQ Pq,Qq nil [ NP 0x0F 0xD4 /r] s:SSE2, t:MMX, w:RW|R, e:4 +PADDQ Vx,Wx nil [ 0x66 0x0F 0xD4 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PMULLW Pq,Qq nil [ NP 0x0F 0xD5 /r] s:MMX, t:MMX, w:RW|R +PMULLW Vx,Wx nil [ 0x66 0x0F 0xD5 /r] s:SSE2, t:SSE, w:RW|R, e:4 +MOVQ Wq,Vq nil [ 0x66 0x0F 0xD6 /r] s:SSE2, t:DATAXFER, w:W|R, e:5 +MOVQ2DQ Vdq,Nq nil [ 0xF3 0x0F 0xD6 /r:reg] s:SSE2, t:DATAXFER, w:W|R +MOVDQ2Q Pq,Uq nil [ 0xF2 0x0F 0xD6 /r:reg] s:SSE2, t:DATAXFER, w:W|R +PMOVMSKB Gd,Nq nil [ NP 0x0F 0xD7 /r:reg] s:SSE, t:MMX, w:W|R, e:7 +PMOVMSKB Gd,Ux nil [ 0x66 0x0F 0xD7 /r:reg] s:SSE2, t:SSE, w:W|R, e:7 +PSUBUSB Pq,Qq nil [ NP 0x0F 0xD8 /r] s:MMX, t:MMX, w:RW|R +PSUBUSB Vx,Wx nil [ 0x66 0x0F 0xD8 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PSUBUSW Pq,Qq nil [ NP 0x0F 0xD9 /r] s:MMX, t:MMX, w:RW|R +PSUBUSW Vx,Wx nil [ 0x66 0x0F 0xD9 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PMINUB Pq,Qq nil [ NP 0x0F 0xDA /r] s:MMX, t:MMX, w:RW|R +PMINUB Vx,Wx nil [ 0x66 0x0F 0xDA /r] s:SSE2, t:SSE, w:RW|R, e:4 +PAND Pq,Qq nil [ NP 0x0F 0xDB /r] s:MMX, t:LOGICAL, w:RW|R +PAND Vx,Wx nil [ 0x66 0x0F 0xDB /r] s:SSE2, t:LOGICAL, w:RW|R, e:4 +PADDUSB Pq,Qq nil [ NP 0x0F 0xDC /r] s:MMX, t:MMX, w:RW|R +PADDUSB Vx,Wx nil [ 0x66 0x0F 0xDC /r] s:SSE2, t:SSE, w:RW|R, e:4 +PADDUSW Pq,Qq nil [ NP 0x0F 0xDD /r] s:MMX, t:MMX, w:RW|R +PADDUSW Vx,Wx nil [ 0x66 0x0F 0xDD /r] s:SSE2, t:SSE, w:RW|R, e:4 +PMAXUB Pq,Qq nil [ NP 0x0F 0xDE /r] s:MMX, t:MMX, w:RW|R +PMAXUB Vx,Wx nil [ 0x66 0x0F 0xDE /r] s:SSE2, t:SSE, w:RW|R, e:4 +PANDN Pq,Qq nil [ NP 0x0F 0xDF /r] s:MMX, t:LOGICAL, w:RW|R +PANDN Vx,Wx nil [ 0x66 0x0F 0xDF /r] s:SSE2, t:LOGICAL, w:RW|R, e:4 + +# 0xE0 - 0xEF +PAVGB Pq,Qq nil [ NP 0x0F 0xE0 /r] s:MMX, t:MMX, w:RW|R +PAVGB Vx,Wx nil [ 0x66 0x0F 0xE0 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PSRAW Pq,Qq nil [ NP 0x0F 0xE1 /r] s:MMX, t:MMX, w:RW|R +PSRAW Vx,Wx nil [ 0x66 0x0F 0xE1 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PSRAD Pq,Qq nil [ NP 0x0F 0xE2 /r] s:MMX, t:MMX, w:RW|R +PSRAD Vx,Wx nil [ 0x66 0x0F 0xE2 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PAVGW Pq,Qq nil [ NP 0x0F 0xE3 /r] s:MMX, t:MMX, w:RW|R +PAVGW Vx,Wx nil [ 0x66 0x0F 0xE3 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PMULHUW Pq,Qq nil [ NP 0x0F 0xE4 /r] s:MMX, t:MMX, w:RW|R +PMULHUW Vx,Wx nil [ 0x66 0x0F 0xE4 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PMULHW Pq,Qq nil [ NP 0x0F 0xE5 /r] s:MMX, t:MMX, w:RW|R +PMULHW Vx,Wx nil [ 0x66 0x0F 0xE5 /r] s:SSE2, t:SSE, w:RW|R, e:4 +CVTTPD2DQ Vx,Wpd nil [ 0x66 0x0F 0xE6 /r] s:SSE2, t:CONVERT, w:W|R, e:2 +CVTDQ2PD Vx,Wpd nil [ 0xF3 0x0F 0xE6 /r] s:SSE2, t:CONVERT, w:W|R, e:5 +CVTPD2DQ Vx,Wpd nil [ 0xF2 0x0F 0xE6 /r] s:SSE2, t:CONVERT, w:W|R, e:2 +MOVNTQ Mq,Pq nil [ NP 0x0F 0xE7 /r:mem] s:MMX, t:DATAXFER, w:W|R +MOVNTDQ Mx,Vx nil [ 0x66 0x0F 0xE7 /r:mem] s:SSE2, t:DATAXFER, w:W|R, e:1 +PSUBSB Pq,Qq nil [ NP 0x0F 0xE8 /r] s:MMX, t:MMX, w:RW|R +PSUBSB Vx,Wx nil [ 0x66 0x0F 0xE8 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PSUBSW Pq,Qq nil [ NP 0x0F 0xE9 /r] s:MMX, t:MMX, w:RW|R +PSUBSW Vx,Wx nil [ 0x66 0x0F 0xE9 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PMINSW Pq,Qq nil [ NP 0x0F 0xEA /r] s:MMX, t:MMX, w:RW|R +PMINSW Vx,Wx nil [ 0x66 0x0F 0xEA /r] s:SSE2, t:SSE, w:RW|R, e:4 +POR Pq,Qq nil [ NP 0x0F 0xEB /r] s:MMX, t:LOGICAL, w:RW|R +POR Vx,Wx nil [ 0x66 0x0F 0xEB /r] s:SSE2, t:LOGICAL, w:RW|R, e:4 +PADDSB Pq,Qq nil [ NP 0x0F 0xEC /r] s:MMX, t:MMX, w:RW|R +PADDSB Vx,Wx nil [ 0x66 0x0F 0xEC /r] s:SSE2, t:SSE, w:RW|R, e:4 +PADDSW Pq,Qq nil [ NP 0x0F 0xED /r] s:MMX, t:MMX, w:RW|R +PADDSW Vx,Wx nil [ 0x66 0x0F 0xED /r] s:SSE2, t:SSE, w:RW|R, e:4 +PMAXSW Pq,Qq nil [ NP 0x0F 0xEE /r] s:MMX, t:MMX, w:RW|R +PMAXSW Vx,Wx nil [ 0x66 0x0F 0xEE /r] s:SSE2, t:SSE, w:RW|R, e:4 +PXOR Pq,Qq nil [ NP 0x0F 0xEF /r] s:MMX, t:LOGICAL, w:RW|R +PXOR Vx,Wx nil [ 0x66 0x0F 0xEF /r] s:SSE2, t:LOGICAL, w:RW|R, e:4 + +# 0xF0 - 0xFF +LDDQU Vx,Mx nil [ 0xF2 0x0F 0xF0 /r:mem] s:SSE3, t:SSE, w:W|R, e:4 +PSLLW Pq,Qq nil [ NP 0x0F 0xF1 /r] s:MMX, t:MMX, w:RW|R +PSLLW Vx,Wx nil [ 0x66 0x0F 0xF1 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PSLLD Pq,Qq nil [ NP 0x0F 0xF2 /r] s:MMX, t:MMX, w:RW|R +PSLLD Vx,Wx nil [ 0x66 0x0F 0xF2 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PSLLQ Pq,Qq nil [ NP 0x0F 0xF3 /r] s:MMX, t:MMX, w:RW|R +PSLLQ Vx,Wx nil [ 0x66 0x0F 0xF3 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PMULUDQ Pq,Qq nil [ NP 0x0F 0xF4 /r] s:SSE2, t:MMX, w:RW|R, e:4 +PMULUDQ Vx,Wx nil [ 0x66 0x0F 0xF4 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PMADDWD Pq,Qq nil [ NP 0x0F 0xF5 /r] s:MMX, t:MMX, w:RW|R +PMADDWD Vx,Wx nil [ 0x66 0x0F 0xF5 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PSADBW Pq,Qq nil [ NP 0x0F 0xF6 /r] s:MMX, t:MMX, w:RW|R +PSADBW Vx,Wx nil [ 0x66 0x0F 0xF6 /r] s:SSE2, t:SSE, w:RW|R, e:4 +MASKMOVQ Pq,Nq pDIq [ NP 0x0F 0xF7 /r:reg] s:MMX, t:DATAXFER, w:R|R|W +MASKMOVDQU Vdq,Udq pDIdq [ 0x66 0x0F 0xF7 /r:reg] s:SSE2, t:DATAXFER, w:R|R|W, e:4 +PSUBB Pq,Qq nil [ NP 0x0F 0xF8 /r] s:MMX, t:MMX, w:RW|R +PSUBB Vx,Wx nil [ 0x66 0x0F 0xF8 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PSUBW Pq,Qq nil [ NP 0x0F 0xF9 /r] s:MMX, t:MMX, w:RW|R +PSUBW Vx,Wx nil [ 0x66 0x0F 0xF9 /r] s:SSE2, t:SSE, w:RW|R, e:4 +PSUBD Pq,Qq nil [ NP 0x0F 0xFA /r] s:MMX, t:MMX, w:RW|R +PSUBD Vx,Wx nil [ 0x66 0x0F 0xFA /r] s:SSE2, t:SSE, w:RW|R, e:4 +PSUBQ Pq,Qq nil [ NP 0x0F 0xFB /r] s:MMX, t:MMX, w:RW|R +PSUBQ Vx,Wx nil [ 0x66 0x0F 0xFB /r] s:SSE2, t:SSE, w:RW|R, e:4 +PADDB Pq,Qq nil [ NP 0x0F 0xFC /r] s:MMX, t:MMX, w:RW|R +PADDB Vx,Wx nil [ 0x66 0x0F 0xFC /r] s:SSE2, t:SSE, w:RW|R, e:4 +PADDW Pq,Qq nil [ NP 0x0F 0xFD /r] s:MMX, t:MMX, w:RW|R +PADDW Vx,Wx nil [ 0x66 0x0F 0xFD /r] s:SSE2, t:SSE, w:RW|R, e:4 +PADDD Pq,Qq nil [ NP 0x0F 0xFE /r] s:MMX, t:MMX, w:RW|R +PADDD Vx,Wx nil [ 0x66 0x0F 0xFE /r] s:SSE2, t:SSE, w:RW|R, e:4 +UD0 Gd,Ed nil [ 0x0F 0xFF /r] s:UD, t:UD, w:R|R diff --git a/isagenerator/instructions/table_0F_38.dat b/isagenerator/instructions/table_0F_38.dat new file mode 100644 index 0000000..f03a93a --- /dev/null +++ b/isagenerator/instructions/table_0F_38.dat @@ -0,0 +1,128 @@ +# Mnemonic Explicit Operands Implicit Encoding Fags, Prefixes, Set, Category, Class, RW map, Additional ops +#------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +# 0x00 - 0x0F +PSHUFB Pq,Qq nil [ NP 0x0F 0x38 0x00 /r] s:SSSE3, t:MMX, w:RW|R +PSHUFB Vx,Wx nil [ 0x66 0x0F 0x38 0x00 /r] s:SSSE3, t:SSE, w:RW|R, e:4 +PHADDW Pq,Qq nil [ NP 0x0F 0x38 0x01 /r] s:SSSE3, t:MMX, w:RW|R +PHADDW Vx,Wx nil [ 0x66 0x0F 0x38 0x01 /r] s:SSSE3, t:SSE, w:RW|R, e:4 +PHADDD Pq,Qq nil [ NP 0x0F 0x38 0x02 /r] s:SSSE3, t:MMX, w:RW|R +PHADDD Vx,Wx nil [ 0x66 0x0F 0x38 0x02 /r] s:SSSE3, t:SSE, w:RW|R, e:4 +PHADDSW Pq,Qq nil [ NP 0x0F 0x38 0x03 /r] s:SSSE3, t:MMX, w:RW|R +PHADDSW Vx,Wx nil [ 0x66 0x0F 0x38 0x03 /r] s:SSSE3, t:SSE, w:RW|R, e:4 +PMADDUBSW Pq,Qq nil [ NP 0x0F 0x38 0x04 /r] s:SSSE3, t:MMX, w:RW|R +PMADDUBSW Vx,Wx nil [ 0x66 0x0F 0x38 0x04 /r] s:SSSE3, t:SSE, w:RW|R, e:4 +PHSUBW Pq,Qq nil [ NP 0x0F 0x38 0x05 /r] s:SSSE3, t:MMX, w:RW|R +PHSUBW Vx,Wx nil [ 0x66 0x0F 0x38 0x05 /r] s:SSSE3, t:SSE, w:RW|R, e:4 +PHSUBD Pq,Qq nil [ NP 0x0F 0x38 0x06 /r] s:SSSE3, t:MMX, w:RW|R +PHSUBD Vx,Wx nil [ 0x66 0x0F 0x38 0x06 /r] s:SSSE3, t:SSE, w:RW|R, e:4 +PHSUBSW Pq,Qq nil [ NP 0x0F 0x38 0x07 /r] s:SSSE3, t:MMX, w:RW|R +PHSUBSW Vx,Wx nil [ 0x66 0x0F 0x38 0x07 /r] s:SSSE3, t:SSE, w:RW|R, e:4 +PSIGNB Pq,Qq nil [ NP 0x0F 0x38 0x08 /r] s:SSSE3, t:MMX, w:RW|R +PSIGNB Vx,Wx nil [ 0x66 0x0F 0x38 0x08 /r] s:SSSE3, t:SSE, w:RW|R, e:4 +PSIGNW Pq,Qq nil [ NP 0x0F 0x38 0x09 /r] s:SSSE3, t:MMX, w:RW|R +PSIGNW Vx,Wx nil [ 0x66 0x0F 0x38 0x09 /r] s:SSSE3, t:SSE, w:RW|R, e:4 +PSIGND Pq,Qq nil [ NP 0x0F 0x38 0x0A /r] s:SSSE3, t:MMX, w:RW|R +PSIGND Vx,Wx nil [ 0x66 0x0F 0x38 0x0A /r] s:SSSE3, t:SSE, w:RW|R, e:4 +PMULHRSW Pq,Qq nil [ NP 0x0F 0x38 0x0B /r] s:SSSE3, t:MMX, w:RW|R +PMULHRSW Vx,Wx nil [ 0x66 0x0F 0x38 0x0B /r] s:SSSE3, t:SSE, w:RW|R, e:4 + +# 0x10 - 0x1F +PBLENDVB Vdq,Wdq XMM0 [ 0x66 0x0F 0x38 0x10 /r] s:SSE4, t:SSE, w:RW|R|R, e:4 +BLENDVPS Vdq,Wdq XMM0 [ 0x66 0x0F 0x38 0x14 /r] s:SSE4, t:SSE, w:RW|R|R, e:4 +BLENDVPD Vdq,Wdq XMM0 [ 0x66 0x0F 0x38 0x15 /r] s:SSE4, t:SSE, w:RW|R|R, e:4 +PTEST Vdq,Wdq Fv [ 0x66 0x0F 0x38 0x17 /r] s:SSE4, t:SSE, w:R|R|W, f:CF=m|PF=0|AF=0|ZF=m|SF=0|OF=0, e:4 +PABSB Pq,Qq nil [ NP 0x0F 0x38 0x1C /r] s:SSSE3, t:MMX, w:W|R +PABSB Vx,Wx nil [ 0x66 0x0F 0x38 0x1C /r] s:SSSE3, t:SSE, w:W|R, e:4 +PABSW Pq,Qq nil [ NP 0x0F 0x38 0x1D /r] s:SSSE3, t:MMX, w:W|R +PABSW Vx,Wx nil [ 0x66 0x0F 0x38 0x1D /r] s:SSSE3, t:SSE, w:W|R, e:4 +PABSD Pq,Qq nil [ NP 0x0F 0x38 0x1E /r] s:SSSE3, t:MMX, w:W|R +PABSD Vx,Wx nil [ 0x66 0x0F 0x38 0x1E /r] s:SSSE3, t:SSE, w:W|R, e:4 + +# 0x20 - 0x2F +PMOVSXBW Vdq,Wq nil [ 0x66 0x0F 0x38 0x20 /r] s:SSE4, t:SSE, w:W|R, e:5 +PMOVSXBD Vdq,Wd nil [ 0x66 0x0F 0x38 0x21 /r] s:SSE4, t:SSE, w:W|R, e:5 +PMOVSXBQ Vdq,Ww nil [ 0x66 0x0F 0x38 0x22 /r] s:SSE4, t:SSE, w:W|R, e:5 +PMOVSXWD Vdq,Wq nil [ 0x66 0x0F 0x38 0x23 /r] s:SSE4, t:SSE, w:W|R, e:5 +PMOVSXWQ Vdq,Wd nil [ 0x66 0x0F 0x38 0x24 /r] s:SSE4, t:SSE, w:W|R, e:5 +PMOVSXDQ Vdq,Wq nil [ 0x66 0x0F 0x38 0x25 /r] s:SSE4, t:SSE, w:W|R, e:5 +PMULDQ Vx,Wx nil [ 0x66 0x0F 0x38 0x28 /r] s:SSE4, t:SSE, w:RW|R, e:4 +PCMPEQQ Vx,Wx nil [ 0x66 0x0F 0x38 0x29 /r] s:SSE4, t:SSE, w:RW|R, e:4 +MOVNTDQA Vx,Mx nil [ 0x66 0x0F 0x38 0x2A /r:mem] s:SSE4, t:SSE, w:W|R, e:1 +PACKUSDW Vx,Wx nil [ 0x66 0x0F 0x38 0x2B /r] s:SSE4, t:SSE, w:RW|R, e:4 + + +# 0x30 - 0x3F +PMOVZXBW Vdq,Wq nil [ 0x66 0x0F 0x38 0x30 /r] s:SSE4, t:SSE, w:W|R, e:5 +PMOVZXBD Vdq,Wd nil [ 0x66 0x0F 0x38 0x31 /r] s:SSE4, t:SSE, w:W|R, e:5 +PMOVZXBQ Vdq,Ww nil [ 0x66 0x0F 0x38 0x32 /r] s:SSE4, t:SSE, w:W|R, e:5 +PMOVZXWD Vdq,Wq nil [ 0x66 0x0F 0x38 0x33 /r] s:SSE4, t:SSE, w:W|R, e:5 +PMOVZXWQ Vdq,Wd nil [ 0x66 0x0F 0x38 0x34 /r] s:SSE4, t:SSE, w:W|R, e:5 +PMOVZXDQ Vdq,Wq nil [ 0x66 0x0F 0x38 0x35 /r] s:SSE4, t:SSE, w:W|R, e:5 +PCMPGTQ Vx,Wx nil [ 0x66 0x0F 0x38 0x37 /r] s:SSE42, t:SSE, w:RW|R, e:4 +PMINSB Vx,Wx nil [ 0x66 0x0F 0x38 0x38 /r] s:SSE4, t:SSE, w:RW|R, e:4 +PMINSD Vx,Wx nil [ 0x66 0x0F 0x38 0x39 /r] s:SSE4, t:SSE, w:RW|R, e:4 +PMINUW Vx,Wx nil [ 0x66 0x0F 0x38 0x3A /r] s:SSE4, t:SSE, w:RW|R, e:4 +PMINUD Vx,Wx nil [ 0x66 0x0F 0x38 0x3B /r] s:SSE4, t:SSE, w:RW|R, e:4 +PMAXSB Vx,Wx nil [ 0x66 0x0F 0x38 0x3C /r] s:SSE4, t:SSE, w:RW|R, e:4 +PMAXSD Vx,Wx nil [ 0x66 0x0F 0x38 0x3D /r] s:SSE4, t:SSE, w:RW|R, e:4 +PMAXUW Vx,Wx nil [ 0x66 0x0F 0x38 0x3E /r] s:SSE4, t:SSE, w:RW|R, e:4 +PMAXUD Vx,Wx nil [ 0x66 0x0F 0x38 0x3F /r] s:SSE4, t:SSE, w:RW|R, e:4 + +# 0x40 - 0x4F +PMULLD Vx,Wx nil [ 0x66 0x0F 0x38 0x40 /r] s:SSE4, t:SSE, w:RW|R, e:4 +PHMINPOSUW Vdq,Wdq nil [ 0x66 0x0F 0x38 0x41 /r] s:SSE4, t:SSE, w:W|R, e:4 + +# 0x50 - 0x5F + +# 0x60 - 0x6F + +# 0x70 - 0x7F + +# 0x80 - 0x8F +INVEPT Gy,Mdq Fv [ 0x66 0x0F 0x38 0x80 /r:mem] s:VTX, t:VTX, w:R|R|W, f:VMX, a:F64|SERIAL, m:VMXROOT +INVVPID Gy,Mdq Fv [ 0x66 0x0F 0x38 0x81 /r:mem] s:VTX, t:VTX, w:R|R|W, f:VMX, a:F64|SERIAL, m:VMXROOT +INVPCID Gy,Mdq nil [ 0x66 0x0F 0x38 0x82 /r:mem] s:INVPCID, t:MISC, w:R|R, a:F64, m:KERNEL|NOV86 + +# 0x90 - 0x9F + +# 0xA0 - 0xAF + +# 0xB0 - 0xBF + +# 0xC0 - 0xCF +SHA1NEXTE Vdq,Wdq nil [ NP 0x0F 0x38 0xC8 /r] s:SHA, t:SHA, w:RW|R, e:4 +SHA1MSG1 Vdq,Wdq nil [ NP 0x0F 0x38 0xC9 /r] s:SHA, t:SHA, w:RW|R, e:4 +SHA1MSG2 Vdq,Wdq nil [ NP 0x0F 0x38 0xCA /r] s:SHA, t:SHA, w:RW|R, e:4 +SHA256RNDS2 Vdq,Wdq XMM0 [ NP 0x0F 0x38 0xCB /r] s:SHA, t:SHA, w:RW|R|R, e:4 +SHA256MSG1 Vdq,Wdq nil [ NP 0x0F 0x38 0xCC /r] s:SHA, t:SHA, w:RW|R, e:4 +SHA256MSG2 Vdq,Wdq nil [ NP 0x0F 0x38 0xCD /r] s:SHA, t:SHA, w:RW|R, e:4 +GF2P8MULB Vdq,Wdq nil [ 0x66 0x0F 0x38 0xCF /r] s:GFNI, t:GFNI, w:RW|R, e:4 + +# 0xD0 - 0xDF +AESIMC Vdq,Wdq nil [ 0x66 0x0F 0x38 0xDB /r] s:AES, t:AES, w:W|R, e:4 +AESENC Vdq,Wdq nil [ 0x66 0x0F 0x38 0xDC /r] s:AES, t:AES, w:RW|R, e:4 +AESENCLAST Vdq,Wdq nil [ 0x66 0x0F 0x38 0xDD /r] s:AES, t:AES, w:RW|R, e:4 +AESDEC Vdq,Wdq nil [ 0x66 0x0F 0x38 0xDE /r] s:AES, t:AES, w:RW|R, e:4 +AESDECLAST Vdq,Wdq nil [ 0x66 0x0F 0x38 0xDF /r] s:AES, t:AES, w:RW|R, e:4 + +# 0xE0 - 0xEF + +# 0xF0 - 0xFF +MOVBE Gv,Mv nil [ 0x0F 0x38 0xF0 /r:mem] s:MOVBE, t:DATAXFER, w:W|R +MOVBE Gv,Mv nil [ 0x66 0x0F 0x38 0xF0 /r:mem] s:MOVBE, t:DATAXFER, w:W|R, a:S66 +CRC32 Gy,Eb nil [ 0xF2 0x0F 0x38 0xF0 /r] s:SSE42, t:SSE, w:RW|R +CRC32 Gy,Eb nil [ 0x66 0xF2 0x0F 0x38 0xF0 /r] s:SSE42, t:SSE, w:RW|R, a:S66 +MOVBE Mv,Gv nil [ 0x0F 0x38 0xF1 /r:mem] s:MOVBE, t:DATAXFER, w:W|R +MOVBE Mv,Gv nil [ 0x66 0x0F 0x38 0xF1 /r:mem] s:MOVBE, t:DATAXFER, w:W|R, a:S66 +CRC32 Gy,Ev nil [ 0xF2 0x0F 0x38 0xF1 /r] s:SSE42, t:SSE, w:RW|R +CRC32 Gy,Ev nil [ 0x66 0xF2 0x0F 0x38 0xF1 /r] s:SSE42, t:SSE, w:RW|R, a:S66 +WRUSSD My,Gy nil [ 0x66 0x0F 0x38 0xF5 /r:mem] s:CET, t:CET, c:WRUSS, a:SHS, w:W|R +WRUSSQ My,Gy nil [ rexw 0x66 0x0F 0x38 0xF5 /r:mem] s:CET, t:CET, c:WRUSS, a:SHS, w:W|R +WRSSD My,Gy nil [ NP 0x0F 0x38 0xF6 /r:mem] s:CET, t:CET, c:WRSS, a:SHS, w:W|R +WRSSQ My,Gy nil [ rexw NP 0x0F 0x38 0xF6 /r:mem] s:CET, t:CET, c:WRSS, a:SHS, w:W|R +ADCX Gy,Ey Fv [ 0x66 0x0F 0x38 0xF6 /r] s:ADX, t:ARITH, w:RW|R|RW, f:CF=m +ADOX Gy,Ey Fv [ 0xF3 0x0F 0x38 0xF6 /r] s:ADX, t:ARITH, w:RW|R|RW, f:OF=m +MOVDIR64B rMoq,Moq nil [ 0x66 0x0F 0x38 0xF8 /r:mem] s:MOVDIR64B, t:MOVDIR64B, w:W|R +ENQCMD rM?,Moq Fv [ 0xF2 0x0F 0x38 0xF8 /r:mem] s:ENQCMD, t:ENQCMD, w:W|R|W, f:ENQCMD +ENQCMDS rM?,Moq Fv [ 0xF3 0x0F 0x38 0xF8 /r:mem] s:ENQCMD, t:ENQCMD, w:W|R|W, f:ENQCMD +MOVDIRI My,Gy nil [ NP 0x0F 0x38 0xF9 /r:mem] s:MOVDIRI, t:MOVDIRI, w:W|R diff --git a/isagenerator/instructions/table_0F_3A.dat b/isagenerator/instructions/table_0F_3A.dat new file mode 100644 index 0000000..266c2a5 --- /dev/null +++ b/isagenerator/instructions/table_0F_3A.dat @@ -0,0 +1,68 @@ +# Mnemonic Explicit Operands Implicit Encoding Fags, Prefixes, Set, Category, Class, RW map, Additional ops +#------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +# 0x00 - 0x0F +ROUNDPS Vx,Wx,Ib nil [ 0x66 0x0F 0x3A 0x08 /r ib] s:SSE4, t:SSE, w:W|R|R, e:2 +ROUNDPD Vx,Wx,Ib nil [ 0x66 0x0F 0x3A 0x09 /r ib] s:SSE4, t:SSE, w:W|R|R, e:2 +ROUNDSS Vss,Wss,Ib nil [ 0x66 0x0F 0x3A 0x0A /r ib] s:SSE4, t:SSE, w:W|R|R, e:3 +ROUNDSD Vsd,Wsd,Ib nil [ 0x66 0x0F 0x3A 0x0B /r ib] s:SSE4, t:SSE, w:W|R|R, e:3 +BLENDPS Vx,Wx,Ib nil [ 0x66 0x0F 0x3A 0x0C /r ib] s:SSE4, t:SSE, w:RW|R|R, e:4 +BLENDPD Vx,Wx,Ib nil [ 0x66 0x0F 0x3A 0x0D /r ib] s:SSE4, t:SSE, w:RW|R|R, e:4 +PBLENDW Vx,Wx,Ib nil [ 0x66 0x0F 0x3A 0x0E /r ib] s:SSE4, t:SSE, w:RW|R|R, e:4 +PALIGNR Pq,Qq,Ib nil [ NP 0x0F 0x3A 0x0F /r ib] s:SSSE3, t:MMX, w:RW|R|R +PALIGNR Vx,Wx,Ib nil [ 0x66 0x0F 0x3A 0x0F /r ib] s:SSSE3, t:SSE, w:RW|R|R, e:4 + +# 0x10 - 0x1F +# TODO: for PEXTRx, a smaller size is accessed, in fact. +PEXTRB Mb,Vdq,Ib nil [ 0x66 0x0F 0x3A 0x14 /r:mem ib] s:SSE4, t:SSE, w:W|R|R, e:5 +PEXTRB Rd,Vdq,Ib nil [ 0x66 0x0F 0x3A 0x14 /r:reg ib] s:SSE4, t:SSE, w:W|R|R, e:5 +PEXTRW Mw,Vdq,Ib nil [ 0x66 0x0F 0x3A 0x15 /r:mem ib] s:SSE4, t:SSE, w:W|R|R, e:5 +PEXTRW Rd,Vdq,Ib nil [ 0x66 0x0F 0x3A 0x15 /r:reg ib] s:SSE4, t:SSE, w:W|R|R, e:5 +PEXTRD Ey,Vdq,Ib nil [ 0x66 0x0F 0x3A 0x16 /r ib] s:SSE4, t:SSE, w:W|R|R, e:5 +PEXTRQ Ey,Vdq,Ib nil [ rexw 0x66 0x0F 0x3A 0x16 /r ib] s:SSE4, t:SSE, w:W|R|R, e:5 +EXTRACTPS Ed,Vdq,Ib nil [ 0x66 0x0F 0x3A 0x17 /r ib] s:SSE4, t:SSE, w:W|R|R, e:5 + +# 0x20 - 0x2F +PINSRB Vdq,Mb,Ib nil [ 0x66 0x0F 0x3A 0x20 /r:mem ib] s:SSE4, t:SSE, w:RW|R|R, e:5 +PINSRB Vdq,Ry,Ib nil [ 0x66 0x0F 0x3A 0x20 /r:reg ib] s:SSE4, t:SSE, w:RW|R|R, e:5 +INSERTPS Vdq,Md,Ib nil [ 0x66 0x0F 0x3A 0x21 /r:mem ib] s:SSE4, t:SSE, w:RW|R|R, e:5 +INSERTPS Vdq,Udq,Ib nil [ 0x66 0x0F 0x3A 0x21 /r:reg ib] s:SSE4, t:SSE, w:RW|R|R, e:5 +PINSRD Vdq,Ed,Ib nil [ 0x66 0x0F 0x3A 0x22 /r ib] s:SSE4, t:SSE, w:RW|R|R, e:5 +PINSRQ Vdq,Eq,Ib nil [ rexw 0x66 0x0F 0x3A 0x22 /r ib] s:SSE4, t:SSE, w:RW|R|R, e:5 + +# 0x30 - 0x3F + +# 0x40 - 0x4F +DPPS Vx,Wx,Ib nil [ 0x66 0x0F 0x3A 0x40 /r ib] s:SSE4, t:SSE, w:RW|R|R, e:2 +DPPD Vdq,Wdq,Ib nil [ 0x66 0x0F 0x3A 0x41 /r ib] s:SSE4, t:SSE, w:RW|R|R, e:2 +MPSADBW Vdq,Wdq,Ib nil [ 0x66 0x0F 0x3A 0x42 /r ib] s:SSE4, t:SSE, w:RW|R|R, e:4 +PCLMULQDQ Vdq,Wdq,Ib nil [ 0x66 0x0F 0x3A 0x44 /r ib] s:PCLMULQDQ, t:PCLMULQDQ, w:RW|R|R, e:4 + +# 0x50 - 0x5F + +# 0x60 - 0x6F +PCMPESTRM Vdq,Wdq,Ib yAX,yDX,XMM0,Fv [ 0x66 0x0F 0x3A 0x60 /r ib] s:SSE42, t:SSE, w:R|R|R|R|R|W|W, f:PCMPSTR, e:4 +PCMPESTRI Vdq,Wdq,Ib yAX,yDX,yCX,Fv [ 0x66 0x0F 0x3A 0x61 /r ib] s:SSE42, t:SSE, w:R|R|R|R|R|W|W, f:PCMPSTR, e:4 +PCMPISTRM Vdq,Wdq,Ib XMM0,Fv [ 0x66 0x0F 0x3A 0x62 /r ib] s:SSE42, t:SSE, w:R|R|R|W|W, f:PCMPSTR, e:4 +PCMPISTRI Vdq,Wdq,Ib yCX,Fv [ 0x66 0x0F 0x3A 0x63 /r ib] s:SSE42, t:SSE, w:R|R|R|W|W, f:PCMPSTR, e:4 + +# 0x70 - 0x7F + +# 0x80 - 0x8F + +# 0x90 - 0x9F + +# 0xA0 - 0xAF + +# 0xB0 - 0xBF + +# 0xC0 - 0xCF +SHA1RNDS4 Vdq,Wdq,Ib nil [ NP 0x0F 0x3A 0xCC /r ib] s:SHA, t:SHA, w:RW|R|R, e:4 +GF2P8AFFINEQB Vdq,Wdq,Ib nil [ 0x66 0x0F 0x3A 0xCE /r ib] s:GFNI, t:GFNI, w:RW|R|R, e:4 +GF2P8AFFINEINVQB Vdq,Wdq,Ib nil [ 0x66 0x0F 0x3A 0xCF /r ib] s:GFNI, t:GFNI, w:RW|R|R, e:4 + +# 0xD0 - 0xDF +AESKEYGENASSIST Vdq,Wdq,Ib nil [ 0x66 0x0F 0x3A 0xDF /r ib] s:AES, t:AES, w:W|R|R, e:4 + +# 0xE0 - 0xEF + +# 0xF0 - 0xFF diff --git a/isagenerator/instructions/table_3dnow.dat b/isagenerator/instructions/table_3dnow.dat new file mode 100644 index 0000000..131ebe7 --- /dev/null +++ b/isagenerator/instructions/table_3dnow.dat @@ -0,0 +1,28 @@ +# Mnemonic Explicit Implicit Encoding Flags, Prefixes, Set, Category, Class, RW map, Additional ops +#------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +PI2FW Pq,Qq nil [0x0F 0x0F /r 0x0C] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PI2FD Pq,Qq nil [0x0F 0x0F /r 0x0D] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PF2IW Pq,Qq nil [0x0F 0x0F /r 0x1C] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PF2ID Pq,Qq nil [0x0F 0x0F /r 0x1D] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFRCPV Pq,Qq nil [0x0F 0x0F /r 0x86] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFRSQRTV Pq,Qq nil [0x0F 0x0F /r 0x87] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFNACC Pq,Qq nil [0x0F 0x0F /r 0x8A] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFPNACC Pq,Qq nil [0x0F 0x0F /r 0x8E] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFCMPGE Pq,Qq nil [0x0F 0x0F /r 0x90] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFMIN Pq,Qq nil [0x0F 0x0F /r 0x94] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFMIN Pq,Qq nil [0x0F 0x0F /r 0x96] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFRSQRT Pq,Qq nil [0x0F 0x0F /r 0x97] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFSUB Pq,Qq nil [0x0F 0x0F /r 0x9A] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFADD Pq,Qq nil [0x0F 0x0F /r 0x9E] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFCMPGT Pq,Qq nil [0x0F 0x0F /r 0xA0] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFMAX Pq,Qq nil [0x0F 0x0F /r 0xA4] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFRCPIT1 Pq,Qq nil [0x0F 0x0F /r 0xA6] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFRSQIT1 Pq,Qq nil [0x0F 0x0F /r 0xA7] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFSUBR Pq,Qq nil [0x0F 0x0F /r 0xAA] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFACC Pq,Qq nil [0x0F 0x0F /r 0xAE] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFCMPEQ Pq,Qq nil [0x0F 0x0F /r 0xB0] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFMUL Pq,Qq nil [0x0F 0x0F /r 0xB4] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFRCPIT2 Pq,Qq nil [0x0F 0x0F /r 0xB6] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PMULHRW Pq,Qq nil [0x0F 0x0F /r 0xB7] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PSWAPD Pq,Qq nil [0x0F 0x0F /r 0xBB] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PAVGUSB Pq,Qq nil [0x0F 0x0F /r 0xBF] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW diff --git a/isagenerator/instructions/table_base.dat b/isagenerator/instructions/table_base.dat new file mode 100644 index 0000000..15bef1c --- /dev/null +++ b/isagenerator/instructions/table_base.dat @@ -0,0 +1,445 @@ +# Mnemonic Explicit Implicit Encoding s:set, t:type, c:class, a:flags, p:prefixes, w:operands access, f:flags access, i:cpuid, m:valid cpu modes +#------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +# 0x00 - 0x0F +ADD Eb,Gb Fv [ 0x00 /r] s:I86, t:ARITH, w:RW|R|W, f:ARITH, p:HLE|LOCK +ADD Ev,Gv Fv [ 0x01 /r] s:I86, t:ARITH, w:RW|R|W, f:ARITH, p:HLE|LOCK +ADD Gb,Eb Fv [ 0x02 /r] s:I86, t:ARITH, w:RW|R|W, f:ARITH +ADD Gv,Ev Fv [ 0x03 /r] s:I86, t:ARITH, w:RW|R|W, f:ARITH +ADD AL,Ib Fv [ 0x04 ib] s:I86, t:ARITH, w:RW|R|W, f:ARITH +ADD rAX,Iz Fv [ 0x05 iz] s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SEXO1 +PUSH ES Kv [ 0x06] s:I86, t:PUSH, w:R|W, m:NO64|NOSGX +POP ES Kv [ 0x07] s:I86, t:POP, w:W|R, m:NO64|NOSGX +OR Eb,Gb Fv [ 0x08 /r] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, p:HLE|LOCK +OR Ev,Gv Fv [ 0x09 /r] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, p:HLE|LOCK +OR Gb,Eb Fv [ 0x0A /r] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC +OR Gv,Ev Fv [ 0x0B /r] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC +OR AL,Ib Fv [ 0x0C ib] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC +OR rAX,Iz Fv [ 0x0D iz] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1 +PUSH CS Kv [ 0x0E] s:I86, t:PUSH, w:R|R, m:NO64|NOSGX + +# 0x10 - 0x1F +ADC Eb,Gb Fv [ 0x10 /r] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, p:HLE|LOCK +ADC Ev,Gv Fv [ 0x11 /r] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, p:HLE|LOCK +ADC Gb,Eb Fv [ 0x12 /r] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC +ADC Gv,Ev Fv [ 0x13 /r] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC +ADC AL,Ib Fv [ 0x14 ib] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC +ADC rAX,Iz Fv [ 0x15 iz] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SEXO1 +PUSH SS Kv [ 0x16] s:I86, t:PUSH, w:R|W, m:NO64|NOSGX +POP SS Kv [ 0x17] s:I86, t:POP, w:W|R, m:NO64|NOSGX +SBB Eb,Gb Fv [ 0x18 /r] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, p:HLE|LOCK +SBB Ev,Gv Fv [ 0x19 /r] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, p:HLE|LOCK +SBB Gb,Eb Fv [ 0x1A /r] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC +SBB Gv,Ev Fv [ 0x1B /r] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC +SBB AL,Ib Fv [ 0x1C ib] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC +SBB rAX,Iz Fv [ 0x1D iz] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SEXO1 +PUSH DS Kv [ 0x1E] s:I86, t:PUSH, w:R|W, m:NO64|NOSGX +POP DS Kv [ 0x1F] s:I86, t:POP, w:W|R, m:NO64|NOSGX + +# 0x20 - 0x2F +AND Eb,Gb Fv [ 0x20 /r] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, p:HLE|LOCK +AND Ev,Gv Fv [ 0x21 /r] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, p:HLE|LOCK +AND Gb,Eb Fv [ 0x22 /r] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC +AND Gv,Ev Fv [ 0x23 /r] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC +AND AL,Ib Fv [ 0x24 ib] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC +AND rAX,Iz Fv [ 0x25 iz] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1 +es nil nil [ 0x26] s:UNKNOWN, t:UNKNOWN, a:PREFIX +DAA nil AL,Fv [ 0x27] s:I86, t:DECIMAL, w:RW|RW, f:DAAS, m:NO64 +SUB Eb,Gb Fv [ 0x28 /r] s:I86, t:ARITH, w:RW|R|W, f:ARITH, p:HLE|LOCK +SUB Ev,Gv Fv [ 0x29 /r] s:I86, t:ARITH, w:RW|R|W, f:ARITH, p:HLE|LOCK +SUB Gb,Eb Fv [ 0x2A /r] s:I86, t:ARITH, w:RW|R|W, f:ARITH +SUB Gv,Ev Fv [ 0x2B /r] s:I86, t:ARITH, w:RW|R|W, f:ARITH +SUB AL,Ib Fv [ 0x2C ib] s:I86, t:ARITH, w:RW|R|W, f:ARITH +SUB rAX,Iz Fv [ 0x2D iz] s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SEXO1 +cs nil nil [ 0x2E] s:UNKNOWN, t:UNKNOWN, a:PREFIX +BHNT nil nil [ 0x2E] s:UNKNOWN, t:UNKNOWN, a:PREFIX +DAS nil AL,Fv [ 0x2F] s:I86, t:DECIMAL, w:RW|RW, f:DAAS|SF=m, m:NO64 + +# 0x30 - 0x3F +XOR Eb,Gb Fv [ 0x30 /r] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, p:HLE|LOCK +XOR Ev,Gv Fv [ 0x31 /r] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, p:HLE|LOCK +XOR Gb,Eb Fv [ 0x32 /r] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC +XOR Gv,Ev Fv [ 0x33 /r] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC +XOR AL,Ib Fv [ 0x34 ib] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC +XOR rAX,Iz Fv [ 0x35 iz] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1 +ss nil nil [ 0x36] s:UNKNOWN, t:UNKNOWN, a:PREFIX +AAA nil AH,AL,Fv [ 0x37] s:I86, t:DECIMAL, w:RW|RW|RW, f:AAAS, m:NO64 +CMP Eb,Gb Fv [ 0x38 /r] s:I86, t:ARITH, w:R|R|W, f:ARITH +CMP Ev,Gv Fv [ 0x39 /r] s:I86, t:ARITH, w:R|R|W, f:ARITH +CMP Gb,Eb Fv [ 0x3A /r] s:I86, t:ARITH, w:R|R|W, f:ARITH +CMP Gv,Ev Fv [ 0x3B /r] s:I86, t:ARITH, w:R|R|W, f:ARITH +CMP AL,Ib Fv [ 0x3C ib] s:I86, t:ARITH, w:R|R|W, f:ARITH +CMP rAX,Iz Fv [ 0x3D iz] s:I86, t:ARITH, w:R|R|W, f:ARITH, a:OP2SEXO1 +ds nil nil [ 0x3E] s:UNKNOWN, t:UNKNOWN, a:PREFIX +BHT nil nil [ 0x3E] s:UNKNOWN, t:UNKNOWN, a:PREFIX +AAS nil AH,AL,Fv [ 0x3F] s:I86, t:DECIMAL, w:RW|RW|RW, f:AAAS, m:NO64 + +# 0x40 - 0x4F +INC Zv Fv [ 0x40] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 +INC Zv Fv [ 0x41] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 +INC Zv Fv [ 0x42] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 +INC Zv Fv [ 0x43] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 +INC Zv Fv [ 0x44] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 +INC Zv Fv [ 0x45] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 +INC Zv Fv [ 0x46] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 +INC Zv Fv [ 0x47] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 +DEC Zv Fv [ 0x48] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 +DEC Zv Fv [ 0x49] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 +DEC Zv Fv [ 0x4A] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 +DEC Zv Fv [ 0x4B] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 +DEC Zv Fv [ 0x4C] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 +DEC Zv Fv [ 0x4D] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 +DEC Zv Fv [ 0x4E] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 +DEC Zv Fv [ 0x4F] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 + +# 0x50 - 0x5F +PUSH Zv Kv [ 0x50] s:I86, t:PUSH, w:R|W, a:D64 +PUSH Zv Kv [ 0x51] s:I86, t:PUSH, w:R|W, a:D64 +PUSH Zv Kv [ 0x52] s:I86, t:PUSH, w:R|W, a:D64 +PUSH Zv Kv [ 0x53] s:I86, t:PUSH, w:R|W, a:D64 +PUSH Zv Kv [ 0x54] s:I86, t:PUSH, w:R|W, a:D64 +PUSH Zv Kv [ 0x55] s:I86, t:PUSH, w:R|W, a:D64 +PUSH Zv Kv [ 0x56] s:I86, t:PUSH, w:R|W, a:D64 +PUSH Zv Kv [ 0x57] s:I86, t:PUSH, w:R|W, a:D64 +POP Zv Kv [ 0x58] s:I86, t:POP, w:W|R, a:D64 +POP Zv Kv [ 0x59] s:I86, t:POP, w:W|R, a:D64 +POP Zv Kv [ 0x5A] s:I86, t:POP, w:W|R, a:D64 +POP Zv Kv [ 0x5B] s:I86, t:POP, w:W|R, a:D64 +POP Zv Kv [ 0x5C] s:I86, t:POP, w:W|R, a:D64 +POP Zv Kv [ 0x5D] s:I86, t:POP, w:W|R, a:D64 +POP Zv Kv [ 0x5E] s:I86, t:POP, w:W|R, a:D64 +POP Zv Kv [ 0x5F] s:I86, t:POP, w:W|R, a:D64 + +# 0x60 - 0x6F +PUSHA nil BANK,Kv8 [ 0x60] s:I386, t:PUSH, w:R|W, m:NO64 +POPA nil BANK,Kv8 [ 0x61] s:I386, t:POP, w:W|R, m:NO64 +BOUND Gv,Ma nil [ 0x62 /r:mem] s:I186, t:INTERRUPT, w:R|R, m:NO64 +ARPL Ew,Gw Fv [ 0x63 /r] s:I286PROT, t:SYSTEM, w:RW|R|W, f:ZF=m, m:NOREAL|NO64 +MOVSXD Gv,Ez nil [ o64 0x63 /r] s:LONGMODE, t:DATAXFER, w:W|R, m:O64 +fs nil nil [ 0x64] s:UNKNOWN, t:UNKNOWN, a:PREFIX +BHALT nil nil [ 0x64] s:UNKNOWN, t:UNKNOWN, a:PREFIX +gs nil nil [ 0x65] s:UNKNOWN, t:UNKNOWN, a:PREFIX +size nil nil [ 0x66] s:UNKNOWN, t:UNKNOWN, a:PREFIX +addr nil nil [ 0x67] s:UNKNOWN, t:UNKNOWN, a:PREFIX +PUSH Iz Kv [ 0x68 iz] s:I86, t:PUSH, w:R|W, a:D64|OP1SEXDW +IMUL Gv,Ev,Iz Fv [ 0x69 /r iz] s:I86, t:ARITH, w:W|R|R|W, f:MUL, a:OP3SEXO1 +PUSH Ib Kv [ 0x6A ib] s:I86, t:PUSH, w:R|W, a:D64|OP1SEXDW +IMUL Gv,Ev,Ib Fv [ 0x6B /r ib] s:I86, t:ARITH, w:W|R|R|W, f:MUL, a:OP3SEXO1 +INSB Yb,DX aDI,Fv [ 0x6C] s:I86, t:IOSTRINGOP, c:INS, w:W|R|RW|R, f:IOS, a:OP1DEF|OP2DEF, p:REP, m:NOSGX +INSB Yb,DX aCX,aDI,Fv [ rep 0x6C] s:I86, t:IOSTRINGOP, c:INS, w:CW|R|RCW|RCW|R, f:IOS, a:OP1DEF|OP2DEF, p:REP, m:NOSGX +INSW Yz,DX aDI,Fv [ ds16 0x6D] s:I86, t:IOSTRINGOP, c:INS, w:W|R|RW|R, f:IOS, a:OP1DEF|OP2DEF, p:REP, m:NOSGX +INSW Yz,DX aCX,aDI,Fv [ rep ds16 0x6D] s:I86, t:IOSTRINGOP, c:INS, w:CW|R|RCW|RCW|R, f:IOS, a:OP1DEF|OP2DEF, p:REP, m:NOSGX +INSD Yz,DX aDI,Fv [ 0x6D] s:I86, t:IOSTRINGOP, c:INS, w:W|R|RW|R, f:IOS, a:OP1DEF|OP2DEF, p:REP, m:NOSGX +INSD Yz,DX aCX,aDI,Fv [ rep 0x6D] s:I86, t:IOSTRINGOP, c:INS, w:CW|R|RCW|RCW|R, f:IOS, a:OP1DEF|OP2DEF, p:REP, m:NOSGX +OUTSB DX,Xb aSI,Fv [ 0x6E] s:I86, t:IOSTRINGOP, c:OUTS, w:R|R|RW|R, f:IOS, a:OP1DEF|OP2DEF|SERIAL, p:REP, m:NOSGX +OUTSB DX,Xb aCX,aSI,Fv [ rep 0x6E] s:I86, t:IOSTRINGOP, c:OUTS, w:R|CR|RCW|RCW|R, f:IOS, a:OP1DEF|OP2DEF|SERIAL, p:REP, m:NOSGX +OUTSW DX,Xz aSI,Fv [ ds16 0x6F] s:I86, t:IOSTRINGOP, c:OUTS, w:R|R|RW|R, f:IOS, a:OP1DEF|OP2DEF|SERIAL, p:REP, m:NOSGX +OUTSW DX,Xz aCX,aSI,Fv [ rep ds16 0x6F] s:I86, t:IOSTRINGOP, c:OUTS, w:R|CR|RCW|RCW|R, f:IOS, a:OP1DEF|OP2DEF|SERIAL, p:REP, m:NOSGX +OUTSD DX,Xz aSI,Fv [ 0x6F] s:I86, t:IOSTRINGOP, c:OUTS, w:R|R|RW|R, f:IOS, a:OP1DEF|OP2DEF|SERIAL, p:REP, m:NOSGX +OUTSD DX,Xz aCX,aSI,Fv [ rep 0x6F] s:I86, t:IOSTRINGOP, c:OUTS, w:R|CR|RCW|RCW|R, f:IOS, a:OP1DEF|OP2DEF|SERIAL, p:REP, m:NOSGX + +# 0x70 - 0x7F +JO Jb rIP,Fv [ 0x70 cb] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CO, a:F64|COND, p:BND|BH +JNO Jb rIP,Fv [ 0x71 cb] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CNO, a:F64|COND, p:BND|BH +JC Jb rIP,Fv [ 0x72 cb] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CC, a:F64|COND, p:BND|BH +JNC Jb rIP,Fv [ 0x73 cb] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CNC, a:F64|COND, p:BND|BH +JZ Jb rIP,Fv [ 0x74 cb] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CZ, a:F64|COND, p:BND|BH +JNZ Jb rIP,Fv [ 0x75 cb] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CNZ, a:F64|COND, p:BND|BH +JBE Jb rIP,Fv [ 0x76 cb] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CBE, a:F64|COND, p:BND|BH +JNBE Jb rIP,Fv [ 0x77 cb] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CNBE, a:F64|COND, p:BND|BH +JS Jb rIP,Fv [ 0x78 cb] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CS, a:F64|COND, p:BND|BH +JNS Jb rIP,Fv [ 0x79 cb] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CNS, a:F64|COND, p:BND|BH +JP Jb rIP,Fv [ 0x7A cb] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CP, a:F64|COND, p:BND|BH +JNP Jb rIP,Fv [ 0x7B cb] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CNP, a:F64|COND, p:BND|BH +JL Jb rIP,Fv [ 0x7C cb] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CL, a:F64|COND, p:BND|BH +JNL Jb rIP,Fv [ 0x7D cb] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CNL, a:F64|COND, p:BND|BH +JLE Jb rIP,Fv [ 0x7E cb] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CLE, a:F64|COND, p:BND|BH +JNLE Jb rIP,Fv [ 0x7F cb] s:I86, t:COND_BR, c:Jcc, w:R|RW|R, f:CNLE, a:F64|COND, p:BND|BH + +# 0x80 - 0x8F +ADD Eb,Ib Fv [ 0x80 /0 ib] s:I86, t:ARITH, w:RW|R|W, f:ARITH, p:HLE|LOCK +OR Eb,Ib Fv [ 0x80 /1 ib] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, p:HLE|LOCK +ADC Eb,Ib Fv [ 0x80 /2 ib] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, p:HLE|LOCK +SBB Eb,Ib Fv [ 0x80 /3 ib] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, p:HLE|LOCK +AND Eb,Ib Fv [ 0x80 /4 ib] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, p:HLE|LOCK +SUB Eb,Ib Fv [ 0x80 /5 ib] s:I86, t:ARITH, w:RW|R|W, f:ARITH, p:HLE|LOCK +XOR Eb,Ib Fv [ 0x80 /6 ib] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, p:HLE|LOCK +CMP Eb,Ib Fv [ 0x80 /7 ib] s:I86, t:ARITH, w:R|R|W, f:ARITH + +ADD Ev,Iz Fv [ 0x81 /0 iz] s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SEXO1, p:HLE|LOCK +OR Ev,Iz Fv [ 0x81 /1 iz] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1, p:HLE|LOCK +ADC Ev,Iz Fv [ 0x81 /2 iz] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SEXO1, p:HLE|LOCK +SBB Ev,Iz Fv [ 0x81 /3 iz] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SEXO1, p:HLE|LOCK +AND Ev,Iz Fv [ 0x81 /4 iz] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1, p:HLE|LOCK +SUB Ev,Iz Fv [ 0x81 /5 iz] s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SEXO1, p:HLE|LOCK +XOR Ev,Iz Fv [ 0x81 /6 iz] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1, p:HLE|LOCK +CMP Ev,Iz Fv [ 0x81 /7 iz] s:I86, t:ARITH, w:R|R|W, f:ARITH, a:OP2SEXO1 + +ADD Ev,Iz Fv [ 0x82 /0 iz] s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SEXO1, m:NO64, p:HLE|LOCK +OR Ev,Iz Fv [ 0x82 /1 iz] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1, m:NO64, p:HLE|LOCK +ADC Ev,Iz Fv [ 0x82 /2 iz] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SEXO1, m:NO64, p:HLE|LOCK +SBB Ev,Iz Fv [ 0x82 /3 iz] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SEXO1, m:NO64, p:HLE|LOCK +AND Ev,Iz Fv [ 0x82 /4 iz] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1, m:NO64, p:HLE|LOCK +SUB Ev,Iz Fv [ 0x82 /5 iz] s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SEXO1, m:NO64, p:HLE|LOCK +XOR Ev,Iz Fv [ 0x82 /6 iz] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1, m:NO64, p:HLE|LOCK +CMP Ev,Iz Fv [ 0x82 /7 iz] s:I86, t:ARITH, w:R|R|W, f:ARITH, a:OP2SEXO1, m:NO64 + +ADD Ev,Ib Fv [ 0x83 /0 ib] s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SEXO1, p:HLE|LOCK +OR Ev,Ib Fv [ 0x83 /1 ib] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1, p:HLE|LOCK +ADC Ev,Ib Fv [ 0x83 /2 ib] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SEXO1, p:HLE|LOCK +SBB Ev,Ib Fv [ 0x83 /3 ib] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SEXO1, p:HLE|LOCK +AND Ev,Ib Fv [ 0x83 /4 ib] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1, p:HLE|LOCK +SUB Ev,Ib Fv [ 0x83 /5 ib] s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SEXO1, p:HLE|LOCK +XOR Ev,Ib Fv [ 0x83 /6 ib] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1, p:HLE|LOCK +CMP Ev,Ib Fv [ 0x83 /7 ib] s:I86, t:ARITH, w:R|R|W, f:ARITH, a:OP2SEXO1 + +TEST Eb,Gb Fv [ 0x84 /r] s:I86, t:LOGIC, w:R|R|W, f:LOGIC +TEST Ev,Gv Fv [ 0x85 /r] s:I86, t:LOGIC, w:R|R|W, f:LOGIC +XCHG Eb,Gb nil [ 0x86 /r] s:I86, t:DATAXFER, w:RW|RW, p:HLE|LOCK|HLEWOL +XCHG Ev,Gv nil [ 0x87 /r] s:I86, t:DATAXFER, w:RW|RW, p:HLE|LOCK|HLEWOL +MOV Eb,Gb nil [ 0x88 /r] s:I86, t:DATAXFER, w:W|R, p:XRELEASE|HLEWOL +MOV Ev,Gv nil [ 0x89 /r] s:I86, t:DATAXFER, w:W|R, p:XRELEASE|HLEWOL +MOV Gb,Eb nil [ 0x8A /r] s:I86, t:DATAXFER, w:W|R +MOV Gv,Ev nil [ 0x8B /r] s:I86, t:DATAXFER, w:W|R +MOV Mw,Sw nil [ 0x8C /r:mem] s:I86, t:DATAXFER, w:W|R +MOV Rv,Sw nil [ 0x8C /r:reg] s:I86, t:DATAXFER, w:W|R +LEA Gv,M0 nil [ 0x8D /r:mem] s:I86, t:MISC, w:W|N, a:AG +MOV Sw,Mw nil [ 0x8E /r:mem] s:I86, t:DATAXFER, w:W|R +MOV Sw,Rv nil [ 0x8E /r:reg] s:I86, t:DATAXFER, w:W|R +POP Ev Kv [ 0x8F /0] s:I86, t:POP, w:W|R, a:D64 + +# 0x90 - 0x9F +NOP nil nil [ 0x90] s:I86, t:NOP, +PAUSE nil nil [ a0xF3 0x90] s:PAUSE, t:MISC, m:NOTSX +XCHG rAX,Zv nil [ rex 0x90] s:I86, t:DATAXFER, w:RW|RW +XCHG rAX,Zv nil [ 0x91] s:I86, t:DATAXFER, w:RW|RW +XCHG rAX,Zv nil [ 0x92] s:I86, t:DATAXFER, w:RW|RW +XCHG rAX,Zv nil [ 0x93] s:I86, t:DATAXFER, w:RW|RW +XCHG rAX,Zv nil [ 0x94] s:I86, t:DATAXFER, w:RW|RW +XCHG rAX,Zv nil [ 0x95] s:I86, t:DATAXFER, w:RW|RW +XCHG rAX,Zv nil [ 0x96] s:I86, t:DATAXFER, w:RW|RW +XCHG rAX,Zv nil [ 0x97] s:I86, t:DATAXFER, w:RW|RW +CBW nil AX,AL [ ds16 0x98] s:I386, t:CONVERT, w:W|R +CWDE nil EAX,AX [ ds32 0x98] s:I386, t:CONVERT, w:W|R +CDQE nil RAX,EAX [ ds64 0x98] s:I386, t:CONVERT, w:W|R +CWD nil DX,AX [ ds16 0x99] s:I386, t:CONVERT, w:W|R +CDQ nil EDX,EAX [ ds32 0x99] s:I386, t:CONVERT, w:W|R +CQO nil RDX,RAX [ ds64 0x99] s:I386, t:CONVERT, w:W|R +CALLF Ap CS,rIP,Kv2,SHS2 [ 0x9A cp] s:I86, t:CALL, c:CALLFD, w:R|RW|W|W|W, m:NO64|NOSGX +WAIT nil nil [ 0x9B] s:X87, t:X87_ALU +PUSHFW Fv Kv [ ds16 0x9C] s:I86, t:PUSH, c:PUSHF, w:R|W, a:D64 +PUSHFD Fv Kv [ ds32 0x9C] s:I86, t:PUSH, c:PUSHF, w:R|W, a:D64 +PUSHFQ Fv Kv [ dds64 0x9C] s:I86, t:PUSH, c:PUSHF, w:R|W, a:D64 +POPFW Fv Kv [ ds16 0x9D] s:I86, t:POP, c:POPF, w:W|R , a:D64 +POPFD Fv Kv [ ds32 0x9D] s:I86, t:POP, c:POPF, w:W|R , a:D64 +POPFQ Fv Kv [ dds64 0x9D] s:I86, t:POP, c:POPF, w:W|R , a:D64 +SAHF nil AH,Fv [ 0x9E] s:I86, t:FLAGOP, w:R|W, f:CF=m|PF=m|AF=m|ZF=m|SF=m +LAHF nil AH,Fv [ 0x9F] s:I86, t:FLAGOP, w:W|R, f:CF=t|PF=t|AF=t|ZF=t|SF=t + +# 0xA0 - 0xAF +MOV AL,Ob nil [ 0xA0] s:I86, t:DATAXFER, w:W|R +MOV rAX,Ov nil [ 0xA1] s:I86, t:DATAXFER, w:W|R +MOV Ob,AL nil [ 0xA2] s:I86, t:DATAXFER, w:W|R +MOV Ov,rAX nil [ 0xA3] s:I86, t:DATAXFER, w:W|R + +MOVSB Yb,Xb aSI,aDI,Fv [ 0xA4] s:I86, t:STRINGOP, c:MOVS, w:W|R|RW|RW|R, f:DF=t, a:OP1DEF|OP2DEF, p:REP +MOVSB Yb,Xb aCX,aSI,aDI,Fv [ rep 0xA4] s:I86, t:STRINGOP, c:MOVS, w:CW|CR|RCW|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF, p:REP +MOVSW Yv,Xv aSI,aDI,Fv [ ds16 0xA5] s:I86, t:STRINGOP, c:MOVS, w:W|R|RW|RW|R, f:DF=t, a:OP1DEF|OP2DEF, p:REP +MOVSW Yv,Xv aCX,aSI,aDI,Fv [ rep ds16 0xA5] s:I86, t:STRINGOP, c:MOVS, w:CW|CR|RCW|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF, p:REP +MOVSD Yv,Xv aSI,aDI,Fv [ ds32 0xA5] s:I86, t:STRINGOP, c:MOVS, w:W|R|RW|RW|R, f:DF=t, a:OP1DEF|OP2DEF, p:REP +MOVSD Yv,Xv aCX,aSI,aDI,Fv [ rep ds32 0xA5] s:I86, t:STRINGOP, c:MOVS, w:CW|CR|RCW|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF, p:REP +MOVSQ Yv,Xv aSI,aDI,Fv [ ds64 0xA5] s:I86, t:STRINGOP, c:MOVS, w:W|R|RW|RW|R, f:DF=t, a:OP1DEF|OP2DEF, p:REP +MOVSQ Yv,Xv aCX,aSI,aDI,Fv [ rep ds64 0xA5] s:I86, t:STRINGOP, c:MOVS, w:CW|CR|RCW|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF, p:REP + +CMPSB Xb,Yb aSI,aDI,Fv [ 0xA6] s:I86, t:STRINGOP, c:CMPS, w:R|R|RW|RW|R, f:CMPS, a:OP1DEF|OP2DEF, p:REPC +CMPSB Xb,Yb aCX,aSI,aDI,Fv [ rep 0xA6] s:I86, t:STRINGOP, c:CMPS, w:CR|CR|RCW|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF, p:REPC +CMPSW Xv,Yv aSI,aDI,Fv [ ds16 0xA7] s:I86, t:STRINGOP, c:CMPS, w:R|R|RW|RW|R, f:CMPS, a:OP1DEF|OP2DEF, p:REPC +CMPSW Xv,Yv aCX,aSI,aDI,Fv [ rep ds16 0xA7] s:I86, t:STRINGOP, c:CMPS, w:CR|CR|RCW|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF, p:REPC +CMPSD Xv,Yv aSI,aDI,Fv [ ds32 0xA7] s:I86, t:STRINGOP, c:CMPS, w:R|R|RW|RW|R, f:CMPS, a:OP1DEF|OP2DEF, p:REPC +CMPSD Xv,Yv aCX,aSI,aDI,Fv [ rep ds32 0xA7] s:I86, t:STRINGOP, c:CMPS, w:CR|CR|RCW|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF, p:REPC +CMPSQ Xv,Yv aSI,aDI,Fv [ ds64 0xA7] s:I86, t:STRINGOP, c:CMPS, w:R|R|RW|RW|R, f:CMPS, a:OP1DEF|OP2DEF, p:REPC +CMPSQ Xv,Yv aCX,aSI,aDI,Fv [ rep ds64 0xA7] s:I86, t:STRINGOP, c:CMPS, w:CR|CR|RCW|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF, p:REPC + +TEST AL,Ib Fv [ 0xA8 ib] s:I86, t:LOGIC, w:R|R|W, f:LOGIC +TEST rAX,Iz Fv [ 0xA9 iz] s:I86, t:LOGIC, w:R|R|W, f:LOGIC, a:OP2SEXO1 + +STOSB Yb,AL aDI,Fv [ 0xAA] s:I86, t:STRINGOP, c:STOS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF, p:REP +STOSB Yb,AL aCX,aDI,Fv [ rep 0xAA] s:I86, t:STRINGOP, c:STOS, w:CW|R|RCW|RCW|RW, f:DF=t , a:OP1DEF|OP2DEF, p:REP +STOSW Yv,AX aDI,Fv [ ds16 0xAB] s:I86, t:STRINGOP, c:STOS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF, p:REP +STOSW Yv,AX aCX,aDI,Fv [ rep ds16 0xAB] s:I86, t:STRINGOP, c:STOS, w:CW|R|RCW|RCW|RW, f:DF=t , a:OP1DEF|OP2DEF, p:REP +STOSD Yv,EAX aDI,Fv [ ds32 0xAB] s:I86, t:STRINGOP, c:STOS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF, p:REP +STOSD Yv,EAX aCX,aDI,Fv [ rep ds32 0xAB] s:I86, t:STRINGOP, c:STOS, w:CW|R|RCW|RCW|RW, f:DF=t , a:OP1DEF|OP2DEF, p:REP +STOSQ Yv,RAX aDI,Fv [ ds64 0xAB] s:I86, t:STRINGOP, c:STOS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF, p:REP +STOSQ Yv,RAX aCX,aDI,Fv [ rep ds64 0xAB] s:I86, t:STRINGOP, c:STOS, w:CW|R|RCW|RCW|RW, f:DF=t , a:OP1DEF|OP2DEF, p:REP + +LODSB AL,Xb aSI,Fv [ 0xAC] s:I86, t:STRINGOP, c:LODS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF, p:REP +LODSB AL,Xb aCX,aSI,Fv [ rep 0xAC] s:I86, t:STRINGOP, c:LODS, w:CW|CR|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF, p:REP +LODSW AX,Xv aSI,Fv [ ds16 0xAD] s:I86, t:STRINGOP, c:LODS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF, p:REP +LODSW AX,Xv aCX,aSI,Fv [ rep ds16 0xAD] s:I86, t:STRINGOP, c:LODS, w:CW|CR|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF, p:REP +LODSD EAX,Xv aSI,Fv [ ds32 0xAD] s:I86, t:STRINGOP, c:LODS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF, p:REP +LODSD EAX,Xv aCX,aSI,Fv [ rep ds32 0xAD] s:I86, t:STRINGOP, c:LODS, w:CW|CR|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF, p:REP +LODSQ RAX,Xv aSI,Fv [ ds64 0xAD] s:I86, t:STRINGOP, c:LODS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF, p:REP +LODSQ RAX,Xv aCX,aSI,Fv [ rep ds64 0xAD] s:I86, t:STRINGOP, c:LODS, w:CW|CR|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF, p:REP + +SCASB AL,Yb aDI,Fv [ 0xAE] s:I86, t:STRINGOP, c:SCAS, w:R|R|RW|RW, f:CMPS, a:OP1DEF|OP2DEF, p:REPC +SCASB AL,Yb aCX,aDI,Fv [ rep 0xAE] s:I86, t:STRINGOP, c:SCAS, w:R|CR|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF, p:REPC +SCASW AX,Yv aDI,Fv [ ds16 0xAF] s:I86, t:STRINGOP, c:SCAS, w:R|R|RW|RW, f:CMPS, a:OP1DEF|OP2DEF, p:REPC +SCASW AX,Yv aCX,aDI,Fv [ rep ds16 0xAF] s:I86, t:STRINGOP, c:SCAS, w:R|CR|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF, p:REPC +SCASD EAX,Yv aDI,Fv [ ds32 0xAF] s:I86, t:STRINGOP, c:SCAS, w:R|R|RW|RW, f:CMPS, a:OP1DEF|OP2DEF, p:REPC +SCASD EAX,Yv aCX,aDI,Fv [ rep ds32 0xAF] s:I86, t:STRINGOP, c:SCAS, w:R|CR|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF, p:REPC +SCASQ RAX,Yv aDI,Fv [ ds64 0xAF] s:I86, t:STRINGOP, c:SCAS, w:R|R|RW|RW, f:CMPS, a:OP1DEF|OP2DEF, p:REPC +SCASQ RAX,Yv aCX,aDI,Fv [ rep ds64 0xAF] s:I86, t:STRINGOP, c:SCAS, w:R|CR|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF, p:REPC + +# 0xB0 - 0xBF +MOV Zb,Ib nil [ 0xB0 ib] s:I86, t:DATAXFER, w:W|R +MOV Zb,Ib nil [ 0xB1 ib] s:I86, t:DATAXFER, w:W|R +MOV Zb,Ib nil [ 0xB2 ib] s:I86, t:DATAXFER, w:W|R +MOV Zb,Ib nil [ 0xB3 ib] s:I86, t:DATAXFER, w:W|R +MOV Zb,Ib nil [ 0xB4 ib] s:I86, t:DATAXFER, w:W|R +MOV Zb,Ib nil [ 0xB5 ib] s:I86, t:DATAXFER, w:W|R +MOV Zb,Ib nil [ 0xB6 ib] s:I86, t:DATAXFER, w:W|R +MOV Zb,Ib nil [ 0xB7 ib] s:I86, t:DATAXFER, w:W|R +MOV Zv,Iv nil [ 0xB8 iv] s:I86, t:DATAXFER, w:W|R +MOV Zv,Iv nil [ 0xB9 iv] s:I86, t:DATAXFER, w:W|R +MOV Zv,Iv nil [ 0xBA iv] s:I86, t:DATAXFER, w:W|R +MOV Zv,Iv nil [ 0xBB iv] s:I86, t:DATAXFER, w:W|R +MOV Zv,Iv nil [ 0xBC iv] s:I86, t:DATAXFER, w:W|R +MOV Zv,Iv nil [ 0xBD iv] s:I86, t:DATAXFER, w:W|R +MOV Zv,Iv nil [ 0xBE iv] s:I86, t:DATAXFER, w:W|R +MOV Zv,Iv nil [ 0xBF iv] s:I86, t:DATAXFER, w:W|R + +# 0xC0 - 0xCF +ROL Eb,Ib Fv [ 0xC0 /0 ib] s:I86, t:ROTATE, w:RW|R|W, f:ROT +ROR Eb,Ib Fv [ 0xC0 /1 ib] s:I86, t:ROTATE, w:RW|R|W, f:ROT +RCL Eb,Ib Fv [ 0xC0 /2 ib] s:I86, t:ROTATE, w:RW|R|RW, f:ROTC +RCR Eb,Ib Fv [ 0xC0 /3 ib] s:I86, t:ROTATE, w:RW|R|RW, f:ROTC +SHL Eb,Ib Fv [ 0xC0 /4 ib] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT +SHR Eb,Ib Fv [ 0xC0 /5 ib] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT +SAL Eb,Ib Fv [ 0xC0 /6 ib] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT +SAR Eb,Ib Fv [ 0xC0 /7 ib] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT +ROL Ev,Ib Fv [ 0xC1 /0 ib] s:I86, t:ROTATE, w:RW|R|W, f:ROT +ROR Ev,Ib Fv [ 0xC1 /1 ib] s:I86, t:ROTATE, w:RW|R|W, f:ROT +RCL Ev,Ib Fv [ 0xC1 /2 ib] s:I86, t:ROTATE, w:RW|R|RW, f:ROTC +RCR Ev,Ib Fv [ 0xC1 /3 ib] s:I86, t:ROTATE, w:RW|R|RW, f:ROTC +SHL Ev,Ib Fv [ 0xC1 /4 ib] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT +SHR Ev,Ib Fv [ 0xC1 /5 ib] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT +SAL Ev,Ib Fv [ 0xC1 /6 ib] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT +SAR Ev,Ib Fv [ 0xC1 /7 ib] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT +RETN Iw rIP,sSP,Kv,SHS [ 0xC2 iw] s:I86, t:RET, w:R|W|W|R|R, a:F64|OP1SEXDW, p:BND +RETN nil rIP,Kv,SHS [ 0xC3] s:I86, t:RET, w:W|R|R, a:F64, p:BND +LES Gz,Mp ES [ 0xC4 /r:mem] s:I86, t:SEGOP, w:W|R|W, m:NO64|NOSGX +LDS Gz,Mp DS [ 0xC5 /r:mem] s:I86, t:SEGOP, w:W|R|W, m:NO64|NOSGX +MOV Eb,Ib nil [ 0xC6 /0 ib] s:I86, t:DATAXFER, w:W|R, p:XRELEASE|HLEWOL +XABORT Ib EAX [ 0xC6 /0xF8 ib] s:TSX, t:UNCOND_BR, w:R|RCW, i:RTM, m:NOTSX +MOV Ev,Iz nil [ 0xC7 /0 iz] s:I86, t:DATAXFER, w:W|R, a:OP2SEXO1, p:XRELEASE|HLEWOL +XBEGIN Jz rIP,EAX [ 0xC7 /0xF8 cz] s:TSX, t:COND_BR, w:R|RW|CW, i:RTM +ENTER Iw,Ib rBP,sSP,Kv [ 0xC8 iw ib] s:I186, t:MISC, w:R|R|RW|RW|W +LEAVE nil sBP,rBP,rSP,Kv [ 0xC9] s:I186, t:MISC, w:R|RW|RW|R, a:D64 +RETF Iw CS,rIP,Kv2,SHS2 [ 0xCA iw] s:I86, t:RET, a:OP1SEXDW, w:R|W|W|R|R +RETF nil CS,rIP,Kv2,SHS2 [ 0xCB] s:I86, t:RET, w:W|W|R|R +INT3 nil CS,rIP,Kv3,Fv,SHS3 [ 0xCC] s:I86, t:INTERRUPT, w:RW|RW|RW|W|W, f:INT, m:NOSGX +INT Ib CS,rIP,Kv3,Fv,SHS3 [ 0xCD ib] s:I86, t:INTERRUPT, w:R|RW|RW|RW|W|W, f:INT, m:NOSGX +INTO nil CS,rIP,Kv3,Fv,SHS3 [ 0xCE] s:I86, t:INTERRUPT, w:RW|RW|RW|W|W, f:INT, m:NO64, m:NOSGX +IRETW nil CS,rIP,Kv3,Fv,SHS3 [ ds16 0xCF] s:I86, t:RET, c:IRET, w:RW|W|R|RW|RW, a:SERIAL +IRETD nil CS,rIP,Kv3,Fv,SHS3 [ ds32 0xCF] s:I86, t:RET, c:IRET, w:RW|W|R|RW|RW, a:SERIAL +IRETQ nil CS,rIP,Kv3,Fv,SHS3 [ ds64 0xCF] s:I86, t:RET, c:IRET, w:RW|W|R|RW|RW, a:SERIAL + +# 0xD0 - 0xDF +ROL Eb,1 Fv [ 0xD0 /0] s:I86, t:ROTATE, w:RW|R|W, f:ROT +ROR Eb,1 Fv [ 0xD0 /1] s:I86, t:ROTATE, w:RW|R|W, f:ROT +RCL Eb,1 Fv [ 0xD0 /2] s:I86, t:ROTATE, w:RW|R|RW, f:ROTC +RCR Eb,1 Fv [ 0xD0 /3] s:I86, t:ROTATE, w:RW|R|RW, f:ROTC +SHL Eb,1 Fv [ 0xD0 /4] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT +SHR Eb,1 Fv [ 0xD0 /5] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT +SAL Eb,1 Fv [ 0xD0 /6] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT +SAR Eb,1 Fv [ 0xD0 /7] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT +ROL Ev,1 Fv [ 0xD1 /0] s:I86, t:ROTATE, w:RW|R|W, f:ROT +ROR Ev,1 Fv [ 0xD1 /1] s:I86, t:ROTATE, w:RW|R|W, f:ROT +RCL Ev,1 Fv [ 0xD1 /2] s:I86, t:ROTATE, w:RW|R|RW, f:ROTC +RCR Ev,1 Fv [ 0xD1 /3] s:I86, t:ROTATE, w:RW|R|RW, f:ROTC +SHL Ev,1 Fv [ 0xD1 /4] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT +SHR Ev,1 Fv [ 0xD1 /5] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT +SAL Ev,1 Fv [ 0xD1 /6] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT +SAR Ev,1 Fv [ 0xD1 /7] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT +ROL Eb,CL Fv [ 0xD2 /0] s:I86, t:ROTATE, w:RW|R|W, f:ROT +ROR Eb,CL Fv [ 0xD2 /1] s:I86, t:ROTATE, w:RW|R|W, f:ROT +RCL Eb,CL Fv [ 0xD2 /2] s:I86, t:ROTATE, w:RW|R|RW, f:ROTC +RCR Eb,CL Fv [ 0xD2 /3] s:I86, t:ROTATE, w:RW|R|RW, f:ROTC +SHL Eb,CL Fv [ 0xD2 /4] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT +SHR Eb,CL Fv [ 0xD2 /5] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT +SAL Eb,CL Fv [ 0xD2 /6] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT +SAR Eb,CL Fv [ 0xD2 /7] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT +ROL Ev,CL Fv [ 0xD3 /0] s:I86, t:ROTATE, w:RW|R|W, f:ROT +ROR Ev,CL Fv [ 0xD3 /1] s:I86, t:ROTATE, w:RW|R|W, f:ROT +RCL Ev,CL Fv [ 0xD3 /2] s:I86, t:ROTATE, w:RW|R|RW, f:ROTC +RCR Ev,CL Fv [ 0xD3 /3] s:I86, t:ROTATE, w:RW|R|RW, f:ROTC +SHL Ev,CL Fv [ 0xD3 /4] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT +SHR Ev,CL Fv [ 0xD3 /5] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT +SAL Ev,CL Fv [ 0xD3 /6] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT +SAR Ev,CL Fv [ 0xD3 /7] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT +AAM Ib AL,AH,Fv [ 0xD4 ib] s:I86, t:DECIMAL, w:R|RW|W|W, f:AADM, m:NO64 +AAD Ib AL,AH,Fv [ 0xD5 ib] s:I86, t:DECIMAL, w:R|RW|RW|W, f:AADM, m:NO64 +SALC nil AL,Fv [ 0xD6] s:I86, t:FLAGOP, w:W|R, f:CF=t +XLATB nil AL,pBXALb [ 0xD7] s:I86, t:MISC, w:W|R + +# 0xE0 - 0xEF +LOOPNZ Jb aCX,rIP,Fv [ 0xE0 cb] s:I86, t:COND_BR, w:R|RW|RW|R, f:ZF=t, a:F64 +LOOPZ Jb aCX,rIP,Fv [ 0xE1 cb] s:I86, t:COND_BR, w:R|RW|RW|R, f:ZF=t, a:F64 +LOOP Jb aCX,rIP,Fv [ 0xE2 cb] s:I86, t:COND_BR, w:R|RW|RW|R, a:F64 +JCXZ Jb aCX,rIP [ as16 0xE3 cb] s:I86, t:COND_BR, c:JrCXZ, w:R|R|RW, a:F64 +JECXZ Jb aCX,rIP [ as32 0xE3 cb] s:I86, t:COND_BR, c:JrCXZ, w:R|R|RW, a:F64 +JRCXZ Jb aCX,rIP [ as64 0xE3 cb] s:I86, t:COND_BR, c:JrCXZ, w:R|R|RW, a:F64 +IN AL,Ib Fv [ 0xE4 ib] s:I86, t:IO, w:W|R|R, f:IO, m:NOSGX +IN eAX,Ib Fv [ 0xE5 ib] s:I86, t:IO, w:W|R|R, f:IO, m:NOSGX +OUT Ib,AL Fv [ 0xE6 ib] s:I86, t:IO, w:R|R|R, f:IO, a:SERIAL, m:NOSGX +OUT Ib,eAX Fv [ 0xE7 ib] s:I86, t:IO, w:R|R|R, f:IO, a:SERIAL, m:NOSGX +CALL Jz rIP,Kv,SHS [ 0xE8 cz] s:I86, t:CALL, c:CALLNR, w:R|RW|W|W, a:F64, p:BND +JMP Jz rIP [ 0xE9 cz] s:I86, t:UNCOND_BR, c:JMPNR, w:R|RW, a:F64, p:BND +JMPF Ap CS,rIP [ 0xEA cp] s:I86, t:UNCOND_BR, c:JMPFD, w:R|W|W, m:NO64|NOSGX +JMP Jb rIP [ 0xEB cb] s:I86, t:UNCOND_BR, c:JMPNR, w:R|RW, a:F64, p:BND +IN AL,DX Fv [ 0xEC] s:I86, t:IO, w:W|R|R, f:IO, m:NOSGX +IN eAX,DX Fv [ 0xED] s:I86, t:IO, w:W|R|R, f:IO, m:NOSGX +OUT DX,AL Fv [ 0xEE] s:I86, t:IO, w:R|R|R, f:IO, a:SERIAL, m:NOSGX +OUT DX,eAX Fv [ 0xEF] s:I86, t:IO, w:R|R|R, f:IO, a:SERIAL, m:NOSGX + +# 0xF0 - 0xFF +LOCK nil nil [ 0xF0] s:UNKNOWN, t:UNKNOWN, a:PREFIX +REPNZ nil nil [ 0xF2] s:UNKNOWN, t:UNKNOWN, a:PREFIX +XACQUIRE nil nil [ 0xF2] s:UNKNOWN, t:UNKNOWN, a:PREFIX +BND nil nil [ 0xF2] s:UNKNOWN, t:UNKNOWN, a:PREFIX +REPZ nil nil [ 0xF3] s:UNKNOWN, t:UNKNOWN, a:PREFIX +XRELEASE nil nil [ 0xF2] s:UNKNOWN, t:UNKNOWN, a:PREFIX + +INT1 nil CS,rIP,Kv3,Fv [ 0xF1] s:I86, t:INTERRUPT, w:RW|RW|RW|W, f:INT, m:NOSGX +HLT nil nil [ 0xF4] s:I86, t:SYSTEM, m:KERNEL +CMC nil Fv [ 0xF5] s:I86, t:FLAGOP, w:RW, f:CF=m +TEST Eb,Ib Fv [ 0xF6 /0 ib] s:I86, t:LOGIC, w:R|R|W, f:LOGIC +TEST Eb,Ib Fv [ 0xF6 /1 ib] s:I86, t:LOGIC, w:R|R|W, f:LOGIC +NOT Eb nil [ 0xF6 /2] s:I86, t:LOGIC, w:RW|W, p:HLE|LOCK +NEG Eb Fv [ 0xF6 /3] s:I86, t:LOGIC, w:RW|W, f:ARITH, p:HLE|LOCK +MUL Eb AL,AX,Fv [ 0xF6 /4] s:I86, t:ARITH, w:R|R|W|W, f:MUL +IMUL Eb AL,AX,Fv [ 0xF6 /5] s:I86, t:ARITH, w:R|R|W|W, f:MUL +DIV Eb AX,AL,AH,Fv [ 0xF6 /6] s:I86, t:ARITH, w:R|R|W|W|W, f:DIV +IDIV Eb AX,AL,AH,Fv [ 0xF6 /7] s:I86, t:ARITH, w:R|R|W|W|W, f:DIV +TEST Ev,Iz Fv [ 0xF7 /0 iz] s:I86, t:LOGIC, w:R|R|W, f:LOGIC, a:OP2SEXO1 +TEST Ev,Iz Fv [ 0xF7 /1 iz] s:I86, t:LOGIC, w:R|R|W, f:LOGIC, a:OP2SEXO1 +NOT Ev nil [ 0xF7 /2] s:I86, t:LOGIC, w:RW|W, p:HLE|LOCK +NEG Ev Fv [ 0xF7 /3] s:I86, t:LOGIC, w:RW|W, f:ARITH, p:HLE|LOCK +MUL Ev rAX,rDX,Fv [ 0xF7 /4] s:I86, t:ARITH, w:R|RW|W|W, f:MUL +IMUL Ev rAX,rDX,Fv [ 0xF7 /5] s:I86, t:ARITH, w:R|RW|W|W, f:MUL +DIV Ev rAX,rDX,Fv [ 0xF7 /6] s:I86, t:ARITH, w:R|RW|RW|W, f:DIV +IDIV Ev rAX,rDX,Fv [ 0xF7 /7] s:I86, t:ARITH, w:R|RW|RW|W, f:DIV +CLC nil Fv [ 0xF8] s:I86, t:FLAGOP, w:W, f:CF=0 +STC nil Fv [ 0xF9] s:I86, t:FLAGOP, w:W, f:CF=1 +CLI nil Fv [ 0xFA] s:I86, t:FLAGOP, w:RW, f:IF=0 +STI nil Fv [ 0xFB] s:I86, t:FLAGOP, w:RW, f:IF=1 +CLD nil Fv [ 0xFC] s:I86, t:FLAGOP, w:W, f:DF=0 +STD nil Fv [ 0xFD] s:I86, t:FLAGOP, w:W, f:DF=1 +INC Eb Fv [ 0xFE /0] s:I86, t:ARITH, w:RW|W, f:ARITH, p:HLE|LOCK +DEC Eb Fv [ 0xFE /1] s:I86, t:ARITH, w:RW|W, f:ARITH, p:HLE|LOCK +INC Ev Fv [ 0xFF /0] s:I86, t:ARITH, w:RW|W, f:ARITH, p:HLE|LOCK +DEC Ev Fv [ 0xFF /1] s:I86, t:ARITH, w:RW|W, f:ARITH, p:HLE|LOCK +CALL Ev rIP,Kv,SHS [ 0xFF /2] s:I86, t:CALL, c:CALLNI, w:R|W|W|W, a:F64|CETT, p:BND|DNT +CALLF Mp CS,rIP,Kv2,SHS2 [ 0xFF /3:mem] s:I86, t:CALL, c:CALLFI, w:R|W|W|W|W, a:CETT, m:NOSGX +JMP Ev rIP [ 0xFF /4] s:I86, t:UNCOND_BR, c:JMPNI, w:R|W, a:F64|CETT, p:BND|DNT +JMPF Mp CS,rIP [ 0xFF /5:mem] s:I86, t:UNCOND_BR, c:JMPFI, w:R|W|W, a:CETT, m:NOSGX +PUSH Ev Kv [ 0xFF /6] s:I86, t:PUSH, w:R|W, a:D64 diff --git a/isagenerator/instructions/table_evex1.dat b/isagenerator/instructions/table_evex1.dat new file mode 100644 index 0000000..30ad5eb --- /dev/null +++ b/isagenerator/instructions/table_evex1.dat @@ -0,0 +1,254 @@ +# Mnemonic Explicit Operands Implicit Encoding Flags, Prefixes, Set, Category, Class, RW map, Additional ops +#------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +# 0x10 - 0x1F +VMOVUPS Vn{K}{z},Wn nil [evex m:1 p:0 l:x w:0 0x10 /r] s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R +VMOVUPD Vn{K}{z},Wn nil [evex m:1 p:1 l:x w:1 0x10 /r] s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R +VMOVSS Vdq{K}{z},Mss nil [evex m:1 p:2 l:i w:0 0x10 /r:mem] s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R +VMOVSS Vdq{K}{z},Hdq,Udq nil [evex m:1 p:2 l:i w:0 0x10 /r:reg] s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R|R +VMOVSD Vdq{K}{z},Msd nil [evex m:1 p:3 l:i w:1 0x10 /r:mem] s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R +VMOVSD Vdq{K}{z},Hdq,Udq nil [evex m:1 p:3 l:i w:1 0x10 /r:reg] s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R|R +VMOVUPS Wn{K}{z},Vn nil [evex m:1 p:0 l:x w:0 0x11 /r] s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R +VMOVUPD Wn{K}{z},Vn nil [evex m:1 p:1 l:x w:1 0x11 /r] s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R +VMOVSS Mss{K},Vdq nil [evex m:1 p:2 l:i w:0 0x11 /r:mem] s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R +VMOVSS Udq{K}{z},Hdq,Vdq nil [evex m:1 p:2 l:i w:0 0x11 /r:reg] s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R|R +VMOVSD Msd{K},Vdq nil [evex m:1 p:3 l:i w:1 0x11 /r:mem] s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R +VMOVSD Udq{K}{z},Hdq,Vdq nil [evex m:1 p:3 l:i w:1 0x11 /r:reg] s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R|R +VMOVLPS Vdq,Hdq,Mq nil [evex m:1 p:0 l:0 w:0 0x12 /r:mem] s:AVX512F, t:DATAXFER, l:t2, e:E9NF, w:W|R|R +VMOVHLPS Vdq,Hdq,Udq nil [evex m:1 p:0 l:0 w:0 0x12 /r:reg] s:AVX512F, t:DATAXFER, e:E7NM, w:W|R|R +VMOVLPD Vdq,Hdq,Mq nil [evex m:1 p:1 l:0 w:1 0x12 /r:mem] s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R|R +VMOVSLDUP Vn{K}{z},Wn nil [evex m:1 p:2 l:x w:0 0x12 /r] s:AVX512F, t:DATAXFER, l:fvm, e:E4NFnb, w:W|R|R +VMOVDDUP Vdq{K}{z},Wq nil [evex m:1 p:3 l:0 w:1 0x12 /r] s:AVX512F, t:DATAXFER, l:dup, e:E5NF, w:W|R|R +VMOVDDUP Vqq{K}{z},Wqq nil [evex m:1 p:3 l:1 w:1 0x12 /r] s:AVX512F, t:DATAXFER, l:dup, e:E5NF, w:W|R|R +VMOVDDUP Voq{K}{z},Woq nil [evex m:1 p:3 l:2 w:1 0x12 /r] s:AVX512F, t:DATAXFER, l:dup, e:E5NF, w:W|R|R +VMOVLPS Mq,Vdq nil [evex m:1 p:0 l:0 w:0 0x13 /r:mem] s:AVX512F, t:DATAXFER, l:t2, e:E9NF, w:W|R +VMOVLPD Mq,Vdq nil [evex m:1 p:1 l:0 w:1 0x13 /r:mem] s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R +VUNPCKLPS Vn{K}{z},Hn,Wn|B32 nil [evex m:1 p:0 l:x w:0 0x14 /r] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VUNPCKLPD Vn{K}{z},Hn,Wn|B64 nil [evex m:1 p:1 l:x w:1 0x14 /r] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VUNPCKHPS Vn{K}{z},Hn,Wn|B32 nil [evex m:1 p:0 l:x w:0 0x15 /r] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VUNPCKHPD Vn{K}{z},Hn,Wn|B64 nil [evex m:1 p:1 l:x w:1 0x15 /r] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VMOVHPS Vdq,Hdq,Mq nil [evex m:1 p:0 l:0 w:0 0x16 /r:mem] s:AVX512F, t:DATAXFER, l:t2, e:E9NF, w:W|R|R +VMOVLHPS Vdq,Hdq,Udq nil [evex m:1 p:0 l:0 w:0 0x16 /r:reg] s:AVX512F, t:DATAXFER, e:E7NM, w:W|R|R +VMOVHPD Vdq,Hdq,Mq nil [evex m:1 p:1 l:0 w:1 0x16 /r:mem] s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R|R +VMOVSHDUP Vn{K}{z},Wn nil [evex m:1 p:2 l:x w:0 0x16 /r] s:AVX512F, t:DATAXFER, l:fvm, e:E4NFnb, w:W|R|R +VMOVHPS Mq,Vdq nil [evex m:1 p:0 l:0 w:0 0x17 /r:mem] s:AVX512F, t:DATAXFER, l:t2, e:E9NF, w:W|R +VMOVHPD Mq,Vdq nil [evex m:1 p:1 l:0 w:1 0x17 /r:mem] s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R + +# 0x20 - 0x2F +VMOVAPS Vn{K}{z},Wn nil [evex m:1 p:0 l:x w:0 0x28 /r] s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R +VMOVAPD Vn{K}{z},Wn nil [evex m:1 p:1 l:x w:1 0x28 /r] s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R +VMOVAPS Wn{K}{z},Vn nil [evex m:1 p:0 l:x w:0 0x29 /r] s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R +VMOVAPD Wn{K}{z},Vn nil [evex m:1 p:1 l:x w:1 0x29 /r] s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R +VCVTSI2SS Vdq,Hdq{er},Ey nil [evex m:1 p:2 l:i w:x 0x2A /r] s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R +VCVTSI2SD Vdq,Hdq{er},Ey nil [evex m:1 p:3 l:i w:0 0x2A /r] s:AVX512F, t:CONVERT, l:t1s, e:E10NF, w:W|R|R +VCVTSI2SD Vdq,Hdq{er},Ey nil [evex m:1 p:3 l:i w:1 0x2A /r] s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R +VMOVNTPS Mn,Vn nil [evex m:1 p:0 l:x w:0 0x2B /r:mem] s:AVX512F, t:DATAXFER, l:fvm, e:E1NF, w:W|R +VMOVNTPD Mn,Vn nil [evex m:1 p:1 l:x w:1 0x2B /r:mem] s:AVX512F, t:DATAXFER, l:fvm, e:E1NF, w:W|R +VCVTTSS2SI Gy,Wss{sae} nil [evex m:1 p:2 l:i w:x 0x2C /r] s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R +VCVTTSD2SI Gy,Wsd{sae} nil [evex m:1 p:3 l:i w:x 0x2C /r] s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R +VCVTSS2SI Gy,Wss{er} nil [evex m:1 p:2 l:i w:x 0x2D /r] s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R +VCVTSD2SI Gy,Wsd{er} nil [evex m:1 p:3 l:i w:x 0x2D /r] s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R +VUCOMISS Vdq,Wss{sae} Fv [evex m:1 p:0 l:i w:0 0x2E /r] s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS +VUCOMISD Vdq,Wsd{sae} Fv [evex m:1 p:1 l:i w:1 0x2E /r] s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS +VCOMISS Vdq,Wss{sae} Fv [evex m:1 p:0 l:i w:0 0x2F /r] s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS +VCOMISD Vdq,Wsd{sae} Fv [evex m:1 p:1 l:i w:1 0x2F /r] s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS + +# 0x50 - 0x5F +VSQRTPS Vn{K}{z},Wn|B32{er} nil [evex m:1 p:0 l:x w:0 0x51 /r] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R +VSQRTPD Vn{K}{z},Wn|B64{er} nil [evex m:1 p:1 l:x w:1 0x51 /r] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R +VSQRTSS Vdq{K}{z},Hdq,Wss{er} nil [evex m:1 p:2 l:i w:0 0x51 /r] s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VSQRTSD Vdq{K}{z},Hdq,Wsd{er} nil [evex m:1 p:3 l:i w:1 0x51 /r] s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VANDPS Vn{K}{z},Hn,Wn|B32 nil [evex m:1 p:0 l:x w:0 0x54 /r] s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R +VANDPD Vn{K}{z},Hn,Wn|B64 nil [evex m:1 p:1 l:x w:1 0x54 /r] s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R +VANDNPS Vn{K}{z},Hn,Wn|B32 nil [evex m:1 p:0 l:x w:0 0x55 /r] s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R +VANDNPD Vn{K}{z},Hn,Wn|B64 nil [evex m:1 p:1 l:x w:1 0x55 /r] s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R +VORPS Vn{K}{z},Hn,Wn|B32 nil [evex m:1 p:0 l:x w:0 0x56 /r] s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R +VORPD Vn{K}{z},Hn,Wn|B64 nil [evex m:1 p:1 l:x w:1 0x56 /r] s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R +VXORPS Vn{K}{z},Hn,Wn|B32 nil [evex m:1 p:0 l:x w:0 0x57 /r] s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R +VXORPD Vn{K}{z},Hn,Wn|B64 nil [evex m:1 p:1 l:x w:1 0x57 /r] s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R +VADDPS Vn{K}{z},Hn,Wn|B32{er} nil [evex m:1 p:0 l:x w:0 0x58 /r] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VADDPD Vn{K}{z},Hn,Wn|B64{er} nil [evex m:1 p:1 l:x w:1 0x58 /r] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VADDSS Vdq{K}{z},Hdq,Wss{er} nil [evex m:1 p:2 l:i w:0 0x58 /r] s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VADDSD Vdq{K}{z},Hdq,Wsd{er} nil [evex m:1 p:3 l:i w:1 0x58 /r] s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VMULPS Vn{K}{z},Hn,Wn|B32{er} nil [evex m:1 p:0 l:x w:0 0x59 /r] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VMULPD Vn{K}{z},Hn,Wn|B64{er} nil [evex m:1 p:1 l:x w:1 0x59 /r] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VMULSS Vdq{K}{z},Hdq,Wss{er} nil [evex m:1 p:2 l:i w:0 0x59 /r] s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VMULSD Vdq{K}{z},Hdq,Wsd{er} nil [evex m:1 p:3 l:i w:1 0x59 /r] s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VCVTPS2PD Vn{K}{z},Wh|B32{sae} nil [evex m:1 p:0 l:x w:0 0x5A /r] s:AVX512F, t:CONVERT, l:hv, e:E3, w:W|R|R +VCVTPD2PS Vh{K}{z},Wn|B64{er} nil [evex m:1 p:1 l:x w:1 0x5A /r] s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTSS2SD Vdq{K}{z},Hdq,Wss{sae} nil [evex m:1 p:2 l:i w:0 0x5A /r] s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R|R +VCVTSD2SS Vdq{K}{z},Hdq,Wsd{er} nil [evex m:1 p:3 l:i w:1 0x5A /r] s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R|R +VCVTDQ2PS Vn{K}{z},Wn|B32{er} nil [evex m:1 p:0 l:x w:0 0x5B /r] s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTQQ2PS Vh{K}{z},Wn|B64{er} nil [evex m:1 p:0 l:x w:1 0x5B /r] s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTPS2DQ Vn{K}{z},Wn|B32{er} nil [evex m:1 p:1 l:x w:0 0x5B /r] s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTTPS2DQ Vn{K}{z},Wn|B32{sae} nil [evex m:1 p:2 l:x w:0 0x5B /r] s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R +VSUBPS Vn{K}{z},Hn,Wn|B32{er} nil [evex m:1 p:0 l:x w:0 0x5C /r] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VSUBPD Vn{K}{z},Hn,Wn|B64{er} nil [evex m:1 p:1 l:x w:1 0x5C /r] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VSUBSS Vdq{K}{z},Hdq,Wss{er} nil [evex m:1 p:2 l:i w:0 0x5C /r] s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VSUBSD Vdq{K}{z},Hdq,Wsd{er} nil [evex m:1 p:3 l:i w:1 0x5C /r] s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VMINPS Vn{K}{z},Hn,Wn|B32{sae} nil [evex m:1 p:0 l:x w:0 0x5D /r] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VMINPD Vn{K}{z},Hn,Wn|B64{sae} nil [evex m:1 p:1 l:x w:1 0x5D /r] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VMINSS Vdq{K}{z},Hdq,Wss{sae} nil [evex m:1 p:2 l:i w:0 0x5D /r] s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VMINSD Vdq{K}{z},Hdq,Wsd{sae} nil [evex m:1 p:3 l:i w:1 0x5D /r] s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VDIVPS Vn{K}{z},Hn,Wn|B32{er} nil [evex m:1 p:0 l:x w:0 0x5E /r] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VDIVPD Vn{K}{z},Hn,Wn|B64{er} nil [evex m:1 p:1 l:x w:1 0x5E /r] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VDIVSS Vdq{K}{z},Hdq,Wss{er} nil [evex m:1 p:2 l:i w:0 0x5E /r] s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VDIVSD Vdq{K}{z},Hdq,Wsd{er} nil [evex m:1 p:3 l:i w:1 0x5E /r] s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VMAXPS Vn{K}{z},Hn,Wn|B32{sae} nil [evex m:1 p:0 l:x w:0 0x5F /r] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VMAXPD Vn{K}{z},Hn,Wn|B64{sae} nil [evex m:1 p:1 l:x w:1 0x5F /r] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VMAXSS Vdq{K}{z},Hdq,Wss{sae} nil [evex m:1 p:2 l:i w:0 0x5F /r] s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VMAXSD Vdq{K}{z},Hdq,Wsd{sae} nil [evex m:1 p:3 l:i w:1 0x5F /r] s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R + +# 0x60 - 0x6F +VPUNPCKLBW Vn{K}{z},Hn,Wn nil [evex m:1 p:1 l:x w:x 0x60 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R +VPUNPCKLWD Vn{K}{z},Hn,Wn nil [evex m:1 p:1 l:x w:x 0x61 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R +VPUNPCKLDQ Vn{K}{z},Hn,Wn|B32 nil [evex m:1 p:1 l:x w:0 0x62 /r] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VPACKSSWB Vn{K}{z},Hn,Wn nil [evex m:1 p:1 l:x w:i 0x63 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R +VPCMPGTB rKq{K},Hn,Wn nil [evex m:1 p:1 l:x w:i 0x64 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPCMPGTW rKq{K},Hn,Wn nil [evex m:1 p:1 l:x w:i 0x65 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPCMPGTD rKq{K},Hn,Wn|B32 nil [evex m:1 p:1 l:x w:0 0x66 /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPACKUSWB Vn{K}{z},Hn,Wn nil [evex m:1 p:1 l:x w:i 0x67 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R +VPUNPCKHBW Vn{K}{z},Hn,Wn nil [evex m:1 p:1 l:x w:i 0x68 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R +VPUNPCKHWD Vn{K}{z},Hn,Wn nil [evex m:1 p:1 l:x w:i 0x69 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R +VPUNPCKHDQ Vn{K}{z},Hn,Wn|B32 nil [evex m:1 p:1 l:x w:0 0x6A /r] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VPACKSSDW Vn{K}{z},Hn,Wn|B32 nil [evex m:1 p:1 l:x w:0 0x6B /r] s:AVX512BW, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VPUNPCKLQDQ Vn{K}{z},Hn,Wn|B64 nil [evex m:1 p:1 l:x w:1 0x6C /r] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VPUNPCKHQDQ Vn{K}{z},Hn,Wn|B64 nil [evex m:1 p:1 l:x w:1 0x6D /r] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VMOVD Vdq,Ed nil [evex m:1 p:1 l:0 w:0 0x6E /r] s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R +VMOVQ Vdq,Eq nil [evex m:1 p:1 l:0 w:1 0x6E /r] s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R +VMOVDQA32 Vn{K}{z},Wn nil [evex m:1 p:1 l:x w:0 0x6F /r] s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R +VMOVDQA64 Vn{K}{z},Wn nil [evex m:1 p:1 l:x w:1 0x6F /r] s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R +VMOVDQU32 Vn{K}{z},Wn nil [evex m:1 p:2 l:x w:0 0x6F /r] s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R +VMOVDQU64 Vn{K}{z},Wn nil [evex m:1 p:2 l:x w:1 0x6F /r] s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R +VMOVDQU8 Vn{K}{z},Wn nil [evex m:1 p:3 l:x w:0 0x6F /r] s:AVX512BW, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R +VMOVDQU16 Vn{K}{z},Wn nil [evex m:1 p:3 l:x w:1 0x6F /r] s:AVX512BW, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R + +# 0x70 - 0x7F +VPSHUFD Vn{K}{z},Wn|B32,Ib nil [evex m:1 p:1 l:x w:0 0x70 /r ib] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VPSHUFHW Vn{K}{z},Wn,Ib nil [evex m:1 p:2 l:x w:i 0x70 /r ib] s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R +VPSHUFLW Vn{K}{z},Wn,Ib nil [evex m:1 p:3 l:x w:i 0x70 /r ib] s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R +VPSRLW Hn{K}{z},Wn,Ib nil [evex m:1 p:1 l:x w:i 0x71 /2 ib] s:AVX512BW, t:AVX512, l:m128, e:E4nb, w:W|R|R|R +VPSRAW Hn{K}{z},Wn,Ib nil [evex m:1 p:1 l:x w:i 0x71 /4 ib] s:AVX512BW, t:AVX512, l:m128, e:E4nb, w:W|R|R|R +VPSLLW Hn{K}{z},Wn,Ib nil [evex m:1 p:1 l:x w:i 0x71 /6 ib] s:AVX512BW, t:AVX512, l:m128, e:E4nb, w:W|R|R|R +VPRORD Hn{K}{z},Wn|B32,Ib nil [evex m:1 p:1 l:x w:0 0x72 /0 ib] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPRORQ Hn{K}{z},Wn|B64,Ib nil [evex m:1 p:1 l:x w:1 0x72 /0 ib] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPROLD Hn{K}{z},Wn|B32,Ib nil [evex m:1 p:1 l:x w:0 0x72 /1 ib] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPROLQ Hn{K}{z},Wn|B64,Ib nil [evex m:1 p:1 l:x w:1 0x72 /1 ib] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPSRLD Hn{K}{z},Wn|B32,Ib nil [evex m:1 p:1 l:x w:0 0x72 /2 ib] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPSRAD Hn{K}{z},Wn|B32,Ib nil [evex m:1 p:1 l:x w:0 0x72 /4 ib] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPSRAQ Hn{K}{z},Wn|B64,Ib nil [evex m:1 p:1 l:x w:1 0x72 /4 ib] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPSLLD Hn{K}{z},Wn|B32,Ib nil [evex m:1 p:1 l:x w:0 0x72 /6 ib] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPSRLQ Hn{K}{z},Wn|B64,Ib nil [evex m:1 p:1 l:x w:1 0x73 /2 ib] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPSRLDQ Hn,Wn,Ib nil [evex m:1 p:1 l:x w:i 0x73 /3 ib] s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R +VPSLLQ Hn{K}{z},Wn|B64,Ib nil [evex m:1 p:1 l:x w:1 0x73 /6 ib] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPSLLDQ Hn,Wn,Ib nil [evex m:1 p:1 l:x w:i 0x73 /7 ib] s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R +VPCMPEQB rKq{K},Hn,Wn nil [evex m:1 p:1 l:x w:i 0x74 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPCMPEQW rKq{K},Hn,Wn nil [evex m:1 p:1 l:x w:i 0x75 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPCMPEQD rKq{K},Hn,Wn|B32 nil [evex m:1 p:1 l:x w:i 0x76 /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VCVTTPS2UDQ Vn{K}{z},Wn|B32{sae} nil [evex m:1 p:0 l:x w:0 0x78 /r] s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTTPD2UDQ Vh{K}{z},Wn|B64{sae} nil [evex m:1 p:0 l:x w:1 0x78 /r] s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTTPS2UQQ Vn{K}{z},Wh|B32{sae} nil [evex m:1 p:1 l:x w:0 0x78 /r] s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R +VCVTTPD2UQQ Vn{K}{z},Wn|B64{sae} nil [evex m:1 p:1 l:x w:1 0x78 /r] s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTTSS2USI Gy,Wss{sae} nil [evex m:1 p:2 l:i w:x 0x78 /r] s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R +VCVTTSD2USI Gy,Wsd{sae} nil [evex m:1 p:3 l:i w:x 0x78 /r] s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R +VCVTPS2UDQ Vn{K}{z},Wn|B32{er} nil [evex m:1 p:0 l:x w:0 0x79 /r] s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTPD2UDQ Vh{K}{z},Wn|B64{er} nil [evex m:1 p:0 l:x w:1 0x79 /r] s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTPS2UQQ Vn{K}{z},Wh|B32{er} nil [evex m:1 p:1 l:x w:0 0x79 /r] s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R +VCVTPD2UQQ Vn{K}{z},Wn|B64{er} nil [evex m:1 p:1 l:x w:1 0x79 /r] s:AVX512DQ, t:CONVERT, l:hv, e:E2, w:W|R|R +VCVTSS2USI Gy,Wss{er} nil [evex m:1 p:2 l:i w:x 0x79 /r] s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R +VCVTSD2USI Gy,Wsd{er} nil [evex m:1 p:3 l:i w:x 0x79 /r] s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R +VCVTTPS2QQ Vn{K}{z},Wh|B32{sae} nil [evex m:1 p:1 l:x w:0 0x7A /r] s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R +VCVTTPD2QQ Vn{K}{z},Wn|B64{sae} nil [evex m:1 p:1 l:x w:1 0x7A /r] s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTUDQ2PD Vn{K}{z},Wh|B32 nil [evex m:1 p:2 l:x w:0 0x7A /r] s:AVX512F, t:CONVERT, l:hv, e:E5, w:W|R|R +VCVTUQQ2PD Vn{K}{z},Wn|B64{er} nil [evex m:1 p:2 l:x w:1 0x7A /r] s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTUDQ2PS Vn{K}{z},Wn|B32{er} nil [evex m:1 p:3 l:x w:0 0x7A /r] s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTUQQ2PS Vh{K}{z},Wn|B64{er} nil [evex m:1 p:3 l:x w:1 0x7A /r] s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTPS2QQ Vn{K}{z},Wh|B32{er} nil [evex m:1 p:1 l:x w:0 0x7B /r] s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R +VCVTPD2QQ Vn{K}{z},Wn|B64{er} nil [evex m:1 p:1 l:x w:1 0x7B /r] s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTUSI2SS Vss,Hss{er},Ey nil [evex m:1 p:2 l:i w:x 0x7B /r] s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R +VCVTUSI2SD Vdq,Hdq{er},Ey nil [evex m:1 p:3 l:i w:0 0x7B /r] s:AVX512F, t:CONVERT, l:t1s, e:E10NF, w:W|R|R +VCVTUSI2SD Vdq,Hdq{er},Ey nil [evex m:1 p:3 l:i w:1 0x7B /r] s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R +VMOVD Ey,Vdq nil [evex m:1 p:1 l:0 w:0 0x7E /r] s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R +VMOVQ Ey,Vdq nil [evex m:1 p:1 l:0 w:1 0x7E /r] s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R +VMOVQ Vdq,Wq nil [evex m:1 p:2 l:0 w:1 0x7E /r] s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R +VMOVDQA32 Wn{K}{z},Vn nil [evex m:1 p:1 l:x w:0 0x7F /r] s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R +VMOVDQA64 Wn{K}{z},Vn nil [evex m:1 p:1 l:x w:1 0x7F /r] s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R +VMOVDQU32 Wn{K}{z},Vn nil [evex m:1 p:2 l:x w:0 0x7F /r] s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R +VMOVDQU64 Wn{K}{z},Vn nil [evex m:1 p:2 l:x w:1 0x7F /r] s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R +VMOVDQU8 Wn{K}{z},Vn nil [evex m:1 p:3 l:x w:0 0x7F /r] s:AVX512BW, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R +VMOVDQU16 Wn{K}{z},Vn nil [evex m:1 p:3 l:x w:1 0x7F /r] s:AVX512BW, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R + +# 0x80 - 0x8F + +# 0x90 - 0x9F + +# 0xA0 - 0xAF + +# 0xB0 - 0xBF + +# 0xC0 - 0xCF +VCMPPS rKq{K},Hn,Wn|B32{sae},Ib nil [evex m:1 p:0 l:x w:0 0xC2 /r ib] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R|R +VCMPPD rKq{K},Hn,Wn|B64{sae},Ib nil [evex m:1 p:1 l:x w:1 0xC2 /r ib] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R|R +VCMPSS rKq{K},Hdq,Wss{sae},Ib nil [evex m:1 p:2 l:x w:0 0xC2 /r ib] s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R +VCMPSD rKq{K},Hdq,Wsd{sae},Ib nil [evex m:1 p:3 l:x w:1 0xC2 /r ib] s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R +VPINSRW Vdq,Hdq,Mw,Ib nil [evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib] s:AVX512BW, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R +VPINSRW Vdq,Hdq,Rv,Ib nil [evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib] s:AVX512BW, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R +VPEXTRW Gy,Udq,Ib nil [evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib] s:AVX512BW, t:AVX512, l:t1s, e:E9NF, w:W|R|R +VSHUFPS Vn{K}{z},Hn,Wn|B32,Ib nil [evex m:1 p:0 l:x w:0 0xC6 /r ib] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R|R +VSHUFPD Vn{K}{z},Hn,Wn|B64,Ib nil [evex m:1 p:1 l:x w:1 0xC6 /r ib] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R|R + +# 0xD0 - 0xDF +VPSRLW Vn{K}{z},Hn,Wdq nil [evex m:1 p:1 l:x w:i 0xD1 /r] s:AVX512BW, t:AVX512, l:m128, e:E4nb, w:W|R|R|R +VPSRLD Vn{K}{z},Hn,Wdq nil [evex m:1 p:1 l:x w:0 0xD2 /r] s:AVX512F, t:AVX512, l:m128, e:E4NFnb, w:W|R|R|R +VPSRLQ Vn{K}{z},Hn,Wdq nil [evex m:1 p:1 l:x w:1 0xD3 /r] s:AVX512F, t:AVX512, l:m128, e:E4NFnb, w:W|R|R|R +VPADDQ Vn{K}{z},Hn,Wn|B64 nil [evex m:1 p:1 l:x w:1 0xD4 /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPMULLW Vn{K}{z},Hn,Wn nil [evex m:1 p:1 l:x w:i 0xD5 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VMOVQ Wq,Vdq nil [evex m:1 p:1 l:0 w:1 0xD6 /r] s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R +VPSUBUSB Vn{K}{z},Hn,Wn nil [evex m:1 p:1 l:x w:i 0xD8 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4, w:W|R|R|R +VPSUBUSW Vn{K}{z},Hn,Wn nil [evex m:1 p:1 l:x w:i 0xD9 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4, w:W|R|R|R +VPMINUB Vn{K}{z},Hn,Wn nil [evex m:1 p:1 l:x w:i 0xDA /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPANDQ Vn{K}{z},Hn,Wn|B64 nil [evex m:1 p:1 l:x w:1 0xDB /r] s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R +VPANDD Vn{K}{z},Hn,Wn|B32 nil [evex m:1 p:1 l:x w:0 0xDB /r] s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R +VPADDUSB Vn{K}{z},Hn,Wn nil [evex m:1 p:1 l:x w:i 0xDC /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPADDUSW Vn{K}{z},Hn,Wn nil [evex m:1 p:1 l:x w:i 0xDD /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPMAXUB Vn{K}{z},Hn,Wn nil [evex m:1 p:1 l:x w:i 0xDE /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPANDND Vn{K}{z},Hn,Wn|B32 nil [evex m:1 p:1 l:x w:0 0xDF /r] s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R +VPANDNQ Vn{K}{z},Hn,Wn|B64 nil [evex m:1 p:1 l:x w:1 0xDF /r] s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R + +# 0xE0 - 0xEF +VPAVGB Vn{K}{z},Hn,Wn nil [evex m:1 p:1 l:x w:i 0xE0 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPSRAW Vn{K}{z},Hn,Wdq nil [evex m:1 p:1 l:x w:i 0xE1 /r] s:AVX512BW, t:AVX512, l:m128, e:E4nb, w:W|R|R|R +VPSRAD Vn{K}{z},Hn,Wdq nil [evex m:1 p:1 l:x w:0 0xE2 /r] s:AVX512F, t:AVX512, l:m128, e:E4NFnb, w:W|R|R|R +VPSRAQ Vn{K}{z},Hn,Wdq nil [evex m:1 p:1 l:x w:1 0xE2 /r] s:AVX512F, t:AVX512, l:m128, e:E4NFnb, w:W|R|R|R +VPAVGW Vn{K}{z},Hn,Wn nil [evex m:1 p:1 l:x w:i 0xE3 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPMULHUW Vn{K}{z},Hn,Wn nil [evex m:1 p:1 l:x w:i 0xE4 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPMULHW Vn{K}{z},Hn,Wn nil [evex m:1 p:1 l:x w:i 0xE5 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VCVTTPD2DQ Vh{K}{z},Wn|B64{sae} nil [evex m:1 p:1 l:x w:1 0xE6 /r] s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTDQ2PD Vn{K}{z},Wh|B32 nil [evex m:1 p:2 l:x w:0 0xE6 /r] s:AVX512F, t:CONVERT, l:hv, e:E5, w:W|R|R +VCVTQQ2PD Vn{K}{z},Wn|B64{er} nil [evex m:1 p:2 l:x w:1 0xE6 /r] s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTPD2DQ Vh{K}{z},Wn|B64{er} nil [evex m:1 p:3 l:x w:1 0xE6 /r] s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R +VMOVNTDQ Mn,Vn nil [evex m:1 p:1 l:x w:0 0xE7 /r:mem] s:AVX512F, t:DATAXFER, l:fvm, e:E1NF, w:W|R +VPSUBSB Vn{K}{z},Hn,Wn nil [evex m:1 p:1 l:x w:i 0xE8 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPSUBSW Vn{K}{z},Hn,Wn nil [evex m:1 p:1 l:x w:i 0xE9 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPMINSW Vn{K}{z},Hn,Wn nil [evex m:1 p:1 l:x w:i 0xEA /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPORD Vn{K}{z},Hn,Wn|B32 nil [evex m:1 p:1 l:x w:0 0xEB /r] s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R +VPORQ Vn{K}{z},Hn,Wn|B64 nil [evex m:1 p:1 l:x w:1 0xEB /r] s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R +VPADDSB Vn{K}{z},Hn,Wn nil [evex m:1 p:1 l:x w:i 0xEC /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPADDSW Vn{K}{z},Hn,Wn nil [evex m:1 p:1 l:x w:i 0xED /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPMAXSW Vn{K}{z},Hn,Wn nil [evex m:1 p:1 l:x w:i 0xEE /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPXORD Vn{K}{z},Hn,Wn|B32 nil [evex m:1 p:1 l:x w:0 0xEF /r] s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R +VPXORQ Vn{K}{z},Hn,Wn|B64 nil [evex m:1 p:1 l:x w:1 0xEF /r] s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R + +# 0xF0 - 0xFF +VPSLLW Vn{K}{z},Hn,Wdq nil [evex m:1 p:1 l:x w:i 0xF1 /r] s:AVX512BW, t:AVX512, l:m128, e:E4nb, w:W|R|R|R +VPSLLD Vn{K}{z},Hn,Wdq nil [evex m:1 p:1 l:x w:0 0xF2 /r] s:AVX512F, t:AVX512, l:m128, e:E4NFnb, w:W|R|R|R +VPSLLQ Vn{K}{z},Hn,Wdq nil [evex m:1 p:1 l:x w:1 0xF3 /r] s:AVX512F, t:AVX512, l:m128, e:E4NFnb, w:W|R|R|R +VPMULUDQ Vn{K}{z},Hn,Wn|B64 nil [evex m:1 p:1 l:x w:1 0xF4 /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPMADDWD Vn{K}{z},Hn,Wn nil [evex m:1 p:1 l:x w:i 0xF5 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPSADBW Vn,Hn,Wn nil [evex m:1 p:1 l:x w:i 0xF6 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R +VPSUBB Vn{K}{z},Hn,Wn nil [evex m:1 p:1 l:x w:i 0xF8 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPSUBW Vn{K}{z},Hn,Wn nil [evex m:1 p:1 l:x w:i 0xF9 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPSUBD Vn{K}{z},Hn,Wn|B32 nil [evex m:1 p:1 l:x w:0 0xFA /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPSUBQ Vn{K}{z},Hn,Wn|B64 nil [evex m:1 p:1 l:x w:1 0xFB /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPADDB Vn{K}{z},Hn,Wn nil [evex m:1 p:1 l:x w:i 0xFC /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPADDW Vn{K}{z},Hn,Wn nil [evex m:1 p:1 l:x w:i 0xFD /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPADDD Vn{K}{z},Hn,Wn|B32 nil [evex m:1 p:1 l:x w:0 0xFE /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R diff --git a/isagenerator/instructions/table_evex2.dat b/isagenerator/instructions/table_evex2.dat new file mode 100644 index 0000000..270736d --- /dev/null +++ b/isagenerator/instructions/table_evex2.dat @@ -0,0 +1,343 @@ +# Mnemonic Explicit Operands Implicit Encoding Fags, Prefixes, Set, Category, Class, RW map, Additional ops +#------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +# 0x00 - 0x0F +VPSHUFB Vn{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:i 0x00 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R +VPMADDUBSW Vn{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:i 0x04 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R +VPMULHRSW Vn{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:i 0x0B /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPERMILPS Vn{K}{z},Hn,Wn|B32 nil [evex m:2 p:1 l:x w:0 0x0C /r] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VPERMILPD Vn{K}{z},Hn,Wn|B64 nil [evex m:2 p:1 l:x w:1 0x0D /r] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R + +# 0x10 - 0x1F +VPSRLVW Vn{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:1 0x10 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPSRAVW Vn{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:1 0x11 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4, w:W|R|R|R +VPSLLVW Vn{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:1 0x12 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VCVTPH2PS Vn{K}{z},Wh{sae} nil [evex m:2 p:1 l:x w:0 0x13 /r] s:AVX512F, t:CONVERT, l:hvm, e:E11, w:W|R|R +VPRORVD Vn{K}{z},Hn,Wn|B32 nil [evex m:2 p:1 l:x w:0 0x14 /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPRORVQ Vn{K}{z},Hn,Wn|B64 nil [evex m:2 p:1 l:x w:1 0x14 /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPROLVD Vn{K}{z},Hn,Wn|B32 nil [evex m:2 p:1 l:x w:0 0x15 /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPROLVQ Vn{K}{z},Hn,Wn|B64 nil [evex m:2 p:1 l:x w:1 0x15 /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPERMPS Vu{K}{z},Hu,Wu|B32 nil [evex m:2 p:1 l:1 w:0 0x16 /r] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VPERMPS Vu{K}{z},Hu,Wu|B32 nil [evex m:2 p:1 l:2 w:0 0x16 /r] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VPERMPD Vu{K}{z},Hu,Wu|B64 nil [evex m:2 p:1 l:1 w:1 0x16 /r] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VPERMPD Vu{K}{z},Hu,Wu|B64 nil [evex m:2 p:1 l:2 w:1 0x16 /r] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VPMOVUSWB Wh{K}{z},Vn nil [evex m:2 p:2 l:x w:0 0x10 /r] s:AVX512BW, t:DATAXFER, l:hvm, e:E6, w:W|R|R +VPMOVUSDB Wf{K}{z},Vn nil [evex m:2 p:2 l:x w:0 0x11 /r] s:AVX512F, t:DATAXFER, l:qvm, e:E6, w:W|R|R +VPMOVUSQB We{K}{z},Vn nil [evex m:2 p:2 l:x w:0 0x12 /r] s:AVX512F, t:DATAXFER, l:ovm, e:E6, w:W|R|R +VPMOVUSDW Wh{K}{z},Vn nil [evex m:2 p:2 l:x w:0 0x13 /r] s:AVX512F, t:DATAXFER, l:hv, l:hvm, e:E6, w:W|R|R +VPMOVUSQW Wf{K}{z},Vn nil [evex m:2 p:2 l:x w:0 0x14 /r] s:AVX512F, t:DATAXFER, l:qvm, e:E6, w:W|R|R +VPMOVUSQD Wh{K}{z},Vn nil [evex m:2 p:2 l:x w:0 0x15 /r] s:AVX512F, t:DATAXFER, l:hvm, e:E6, w:W|R|R +VBROADCASTSS Vn{K}{z},Wss nil [evex m:2 p:1 l:x w:0 0x18 /r] s:AVX512F, t:BROADCAST, l:t1s, e:E6, w:W|R|R +VBROADCASTF32X2 Vu{K}{z},Wq nil [evex m:2 p:1 l:x w:0 0x19 /r] s:AVX512DQ, t:BROADCAST, a:NOL0, l:t2, e:E6, w:W|R|R +VBROADCASTSD Vu{K}{z},Wsd nil [evex m:2 p:1 l:x w:1 0x19 /r] s:AVX512F, t:BROADCAST, a:NOL0, l:t1s, e:E6, w:W|R|R +VBROADCASTF32X4 Vu{K}{z},Mdq nil [evex m:2 p:1 l:x w:0 0x1A /r:mem] s:AVX512F, t:BROADCAST, a:NOL0, l:t4, e:E6, w:W|R|R +VBROADCASTF64X2 Vu{K}{z},Mdq nil [evex m:2 p:1 l:x w:1 0x1A /r:mem] s:AVX512DQ, t:BROADCAST, a:NOL0, l:t2, e:E6, w:W|R|R +VBROADCASTF32X8 Voq{K}{z},Mqq nil [evex m:2 p:1 l:2 w:0 0x1B /r:mem] s:AVX512DQ, t:BROADCAST, l:t8, e:E6, w:W|R|R +VBROADCASTF64X4 Voq{K}{z},Mqq nil [evex m:2 p:1 l:2 w:1 0x1B /r:mem] s:AVX512F, t:BROADCAST, l:t4, e:E6, w:W|R|R +VPABSB Vn{K}{z},Wn nil [evex m:2 p:1 l:x w:x 0x1C /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R +VPABSW Vn{K}{z},Wn nil [evex m:2 p:1 l:x w:x 0x1D /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R +VPABSD Vn{K}{z},Wn|B32 nil [evex m:2 p:1 l:x w:0 0x1E /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R +VPABSQ Vn{K}{z},Wn|B64 nil [evex m:2 p:1 l:x w:1 0x1F /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R + +# 0x20 - 0x2F +VPMOVSXBW Vn{K}{z},Wh nil [evex m:2 p:1 l:x w:i 0x20 /r] s:AVX512BW, t:DATAXFER, l:hvm, e:E5, w:W|R|R +VPMOVSXBD Vn{K}{z},Wf nil [evex m:2 p:1 l:x w:i 0x21 /r] s:AVX512F, t:DATAXFER, l:qvm, e:E5, w:W|R|R +VPMOVSXBQ Vn{K}{z},We nil [evex m:2 p:1 l:x w:i 0x22 /r] s:AVX512F, t:DATAXFER, l:ovm, e:E5, w:W|R|R +VPMOVSXWD Vn{K}{z},Wh nil [evex m:2 p:1 l:x w:i 0x23 /r] s:AVX512F, t:DATAXFER, l:hvm, e:E5, w:W|R|R +VPMOVSXWQ Vn{K}{z},Wf nil [evex m:2 p:1 l:x w:i 0x24 /r] s:AVX512F, t:DATAXFER, l:qvm, e:E5, w:W|R|R +VPMOVSXDQ Vn{K}{z},Wh nil [evex m:2 p:1 l:x w:0 0x25 /r] s:AVX512F, t:DATAXFER, l:hvm, e:E5, w:W|R|R +VPTESTMB rKq{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:0 0x26 /r] s:AVX512BW, t:LOGICAL, l:fvm, e:E4nb, w:W|R|R|R +VPTESTMW rKq{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:1 0x26 /r] s:AVX512BW, t:LOGICAL, l:fvm, e:E4nb, w:W|R|R|R +VPTESTMD rKq{K}{z},Hn,Wn|B32 nil [evex m:2 p:1 l:x w:0 0x27 /r] s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R +VPTESTMQ rKq{K}{z},Hn,Wn|B64 nil [evex m:2 p:1 l:x w:1 0x27 /r] s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R +VPMOVSWB Wh{K}{z},Vn nil [evex m:2 p:2 l:x w:0 0x20 /r] s:AVX512BW, t:DATAXFER, l:hvm, e:E6, w:W|R|R +VPMOVSDB Wf{K}{z},Vn nil [evex m:2 p:2 l:x w:0 0x21 /r] s:AVX512F, t:DATAXFER, l:qvm, e:E6, w:W|R|R +VPMOVSQB We{K}{z},Vn nil [evex m:2 p:2 l:x w:0 0x22 /r] s:AVX512F, t:DATAXFER, l:ovm, e:E6, w:W|R|R +VPMOVSDW Wh{K}{z},Vn nil [evex m:2 p:2 l:x w:0 0x23 /r] s:AVX512F, t:DATAXFER, l:hvm, e:E6, w:W|R|R +VPMOVSQW Wf{K}{z},Vn nil [evex m:2 p:2 l:x w:0 0x24 /r] s:AVX512F, t:DATAXFER, l:qvm, e:E6, w:W|R|R +VPMOVSQD Wh{K}{z},Vn nil [evex m:2 p:2 l:x w:0 0x25 /r] s:AVX512F, t:DATAXFER, l:hvm, e:E6, w:W|R|R +VPTESTNMB rKq{K},Hn,Wn nil [evex m:2 p:2 l:x w:0 0x26 /r] s:AVX512BW, t:LOGICAL, l:fvm, e:E4nb, w:W|R|R|R +VPTESTNMW rKq{K},Hn,Wn nil [evex m:2 p:2 l:x w:1 0x26 /r] s:AVX512BW, t:LOGICAL, l:fvm, e:E4nb, w:W|R|R|R +VPTESTNMD rKq{K},Hn,Wn|B32 nil [evex m:2 p:2 l:x w:0 0x27 /r] s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R +VPTESTNMQ rKq{K},Hn,Wn|B64 nil [evex m:2 p:2 l:x w:1 0x27 /r] s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R +VPMULDQ Vn{K}{z},Hn,Wn|B64 nil [evex m:2 p:1 l:x w:1 0x28 /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPCMPEQQ rKq{K},Hn,Wn|B64 nil [evex m:2 p:1 l:x w:1 0x29 /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VMOVNTDQA Vn,Mn nil [evex m:2 p:1 l:x w:0 0x2A /r:mem] s:AVX512F, t:DATAXFER, l:fvm, e:E1NF, w:W|R +VPACKUSDW Vn{K}{z},Hn,Wn|B32 nil [evex m:2 p:1 l:x w:0 0x2B /r] s:AVX512BW, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VSCALEFPS Vn{K}{z},Hn,Wn|B32{er} nil [evex m:2 p:1 l:x w:0 0x2C /r] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VSCALEFPD Vn{K}{z},Hn,Wn|B64{er} nil [evex m:2 p:1 l:x w:1 0x2C /r] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VSCALEFSS Vss{K}{z},Hss,Wss{er} nil [evex m:2 p:1 l:i w:0 0x2D /r] s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VSCALEFSD Vsd{K}{z},Hsd,Wsd{er} nil [evex m:2 p:1 l:i w:1 0x2D /r] s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VPMOVM2B Vn,mKq nil [evex m:2 p:2 l:x w:0 0x28 /r:reg] s:AVX512BW, t:DATAXFER, e:E7NM, w:W|R +VPMOVM2W Vn,mKq nil [evex m:2 p:2 l:x w:1 0x28 /r:reg] s:AVX512BW, t:DATAXFER, e:E7NM, w:W|R +VPMOVB2M rKq,Un nil [evex m:2 p:2 l:x w:0 0x29 /r:reg] s:AVX512BW, t:DATAXFER, e:E7NM, w:W|R +VPMOVW2M rKq,Un nil [evex m:2 p:2 l:x w:1 0x29 /r:reg] s:AVX512BW, t:DATAXFER, e:E7NM, w:W|R +VPBROADCASTMB2Q Vn,mKq nil [evex m:2 p:2 l:x w:1 0x2A /r:reg] s:AVX512CD, t:BROADCAST, e:E6NF, w:W|R + +# 0x30 - 0x3F +VPMOVZXBW Vn{K}{z},Wh nil [evex m:2 p:1 l:x w:i 0x30 /r] s:AVX512BW, t:DATAXFER, l:hvm, e:E5, w:W|R|R +VPMOVZXBD Vn{K}{z},Wf nil [evex m:2 p:1 l:x w:i 0x31 /r] s:AVX512F, t:DATAXFER, l:qvm, e:E5, w:W|R|R +VPMOVZXBQ Vn{K}{z},We nil [evex m:2 p:1 l:x w:i 0x32 /r] s:AVX512F, t:DATAXFER, l:ovm, e:E5, w:W|R|R +VPMOVZXWD Vn{K}{z},Wh nil [evex m:2 p:1 l:x w:i 0x33 /r] s:AVX512F, t:DATAXFER, l:hvm, e:E5, w:W|R|R +VPMOVZXWQ Vn{K}{z},Wf nil [evex m:2 p:1 l:x w:i 0x34 /r] s:AVX512F, t:DATAXFER, l:qvm, e:E5, w:W|R|R +VPMOVZXDQ Vn{K}{z},Wh nil [evex m:2 p:1 l:x w:0 0x35 /r] s:AVX512F, t:DATAXFER, l:hvm, e:E5, w:W|R|R +VPERMD Vu{K}{z},Hu,Wu|B32 nil [evex m:2 p:1 l:x w:0 0x36 /r] s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R +VPERMQ Vu{K}{z},Hu,Wu|B64 nil [evex m:2 p:1 l:x w:1 0x36 /r] s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R +VPCMPGTQ rKq{K},Hn,Wn|B64 nil [evex m:2 p:1 l:x w:1 0x37 /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPMOVWB Wh{K}{z},Vn nil [evex m:2 p:2 l:x w:0 0x30 /r] s:AVX512BW, t:DATAXFER, l:hvm, e:E6, w:W|R|R +VPMOVDB Wf{K}{z},Vn nil [evex m:2 p:2 l:x w:0 0x31 /r] s:AVX512F, t:DATAXFER, l:qvm, e:E6, w:W|R|R +VPMOVQB We{K}{z},Vn nil [evex m:2 p:2 l:x w:0 0x32 /r] s:AVX512F, t:DATAXFER, l:ovm, e:E6, w:W|R|R +VPMOVDW Wh{K}{z},Vn nil [evex m:2 p:2 l:x w:0 0x33 /r] s:AVX512F, t:DATAXFER, l:hvm, e:E6, w:W|R|R +VPMOVQW Wf{K}{z},Vn nil [evex m:2 p:2 l:x w:0 0x34 /r] s:AVX512F, t:DATAXFER, l:qvm, e:E6, w:W|R|R +VPMOVQD Wh{K}{z},Vn nil [evex m:2 p:2 l:x w:0 0x35 /r] s:AVX512F, t:DATAXFER, l:hvm, e:E6, w:W|R|R +VPMINSB Vn{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:i 0x38 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPMINSD Vn{K}{z},Hn,Wn|B32 nil [evex m:2 p:1 l:x w:0 0x39 /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPMINSQ Vn{K}{z},Hn,Wn|B64 nil [evex m:2 p:1 l:x w:1 0x39 /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPMINUW Vn{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:i 0x3A /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPMINUD Vn{K}{z},Hn,Wn|B32 nil [evex m:2 p:1 l:x w:0 0x3B /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPMINUQ Vn{K}{z},Hn,Wn|B64 nil [evex m:2 p:1 l:x w:1 0x3B /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPMAXSB Vn{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:i 0x3C /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPMAXSD Vn{K}{z},Hn,Wn|B32 nil [evex m:2 p:1 l:x w:0 0x3D /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPMAXSQ Vn{K}{z},Hn,Wn|B64 nil [evex m:2 p:1 l:x w:1 0x3D /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPMAXUW Vn{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:i 0x3E /r] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPMAXUD Vn{K}{z},Hn,Wn|B32 nil [evex m:2 p:1 l:x w:0 0x3F /r] s:AVX512F, t:AVX512, l:fv, e:E4nb, w:W|R|R|R +VPMAXUQ Vn{K}{z},Hn,Wn|B64 nil [evex m:2 p:1 l:x w:1 0x3F /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPMOVM2D Vn,mKq nil [evex m:2 p:2 l:x w:0 0x38 /r:reg] s:AVX512DQ, t:DATAXFER, e:E7NM, w:W|R +VPMOVM2Q Vn,mKq nil [evex m:2 p:2 l:x w:1 0x38 /r:reg] s:AVX512DQ, t:DATAXFER, e:E7NM, w:W|R +VPMOVD2M rKq,Un nil [evex m:2 p:2 l:x w:0 0x39 /r:reg] s:AVX512DQ, t:DATAXFER, e:E7NM, w:W|R +VPMOVQ2M rKq,Un nil [evex m:2 p:2 l:x w:1 0x39 /r:reg] s:AVX512DQ, t:DATAXFER, e:E7NM, w:W|R +VPBROADCASTMW2D Vn,mKq nil [evex m:2 p:2 l:x w:0 0x3A /r:reg] s:AVX512CD, t:BROADCAST, e:E6NF, w:W|R + +# 0x40 - 0x4F +VPMULLD Vn{K}{z},Hn,Wn|B32 nil [evex m:2 p:1 l:x w:0 0x40 /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPMULLQ Vn{K}{z},Hn,Wn|B64 nil [evex m:2 p:1 l:x w:1 0x40 /r] s:AVX512DQ, t:AVX512, l:fv, e:E4, w:W|R|R|R +VGETEXPPS Vn{K}{z},Wn|B32{sae} nil [evex m:2 p:1 l:x w:0 0x42 /r] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R +VGETEXPPD Vn{K}{z},Wn|B64{sae} nil [evex m:2 p:1 l:x w:1 0x42 /r] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R +VGETEXPSS Vdq{K}{z},Hdq,Wss{sae} nil [evex m:2 p:1 l:x w:0 0x43 /r] s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VGETEXPSD Vdq{K}{z},Hdq,Wsd{sae} nil [evex m:2 p:1 l:x w:1 0x43 /r] s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VPLZCNTD Vn{K}{z},Wn|B32 nil [evex m:2 p:1 l:x w:0 0x44 /r] s:AVX512CD, t:CONFLICT, l:fv, e:E4, w:W|R|R +VPLZCNTQ Vn{K}{z},Wn|B64 nil [evex m:2 p:1 l:x w:1 0x44 /r] s:AVX512CD, t:CONFLICT, l:fv, e:E4, w:W|R|R +VPSRLVD Vn{K}{z},Hn,Wn|B32 nil [evex m:2 p:1 l:x w:0 0x45 /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPSRLVQ Vn{K}{z},Hn,Wn|B64 nil [evex m:2 p:1 l:x w:1 0x45 /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPSRAVD Vn{K}{z},Hn,Wn|B32 nil [evex m:2 p:1 l:x w:0 0x46 /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPSRAVQ Vn{K}{z},Hn,Wn|B64 nil [evex m:2 p:1 l:x w:1 0x46 /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPSLLVD Vn{K}{z},Hn,Wn|B32 nil [evex m:2 p:1 l:x w:0 0x47 /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPSLLVQ Vn{K}{z},Hn,Wn|B64 nil [evex m:2 p:1 l:x w:1 0x47 /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VRCP14PS Vn{K}{z},Wn|B32 nil [evex m:2 p:1 l:x w:0 0x4C /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R +VRCP14PD Vn{K}{z},Wn|B64 nil [evex m:2 p:1 l:x w:1 0x4C /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R +VRCP14SS Vdq{K}{z},Hdq,Wss nil [evex m:2 p:1 l:x w:0 0x4D /r] s:AVX512F, t:AVX512, l:t1s, e:E10, w:W|R|R|R +VRCP14SD Vdq{K}{z},Hdq,Wsd nil [evex m:2 p:1 l:x w:1 0x4D /r] s:AVX512F, t:AVX512, l:t1s, e:E10, w:W|R|R|R +VRSQRT14PS Vn{K}{z},Wn|B32 nil [evex m:2 p:1 l:x w:0 0x4E /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R +VRSQRT14PD Vn{K}{z},Wn|B64 nil [evex m:2 p:1 l:x w:1 0x4E /r] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R +VRSQRT14SS Vdq{K}{z},Hdq,Wss nil [evex m:2 p:1 l:x w:0 0x4F /r] s:AVX512F, t:AVX512, l:t1s, e:E10, w:W|R|R|R +VRSQRT14SD Vdq{K}{z},Hdq,Wsd nil [evex m:2 p:1 l:x w:1 0x4F /r] s:AVX512F, t:AVX512, l:t1s, e:E10, w:W|R|R|R + +# 0x50 - 0x5F +VPDPBUSD Vn{K}{z},Hn,Wn|B32 nil [evex m:2 p:1 l:x w:0 0x50 /r] s:AVX512VNNI, t:VNNI, l:fv, e:E4, w:RW|R|R|R +VPDPBUSDS Vn{K}{z},Hn,Wn|B32 nil [evex m:2 p:1 l:x w:0 0x51 /r] s:AVX512VNNI, t:VNNI, l:fv, e:E4, w:RW|R|R|R +VPDPWSSD Vn{K}{z},Hn,Wn|B32 nil [evex m:2 p:1 l:x w:0 0x52 /r] s:AVX512VNNI, t:VNNI, l:fv, e:E4, w:RW|R|R|R +VDPBF16PS Vn{K}{z},Hn,Wn|B32 nil [evex m:2 p:2 l:x w:0 0x52 /r] s:AVX512BF16, t:AVX512BF16, l:fv, e:E4, w:W|R|R|R +VP4DPWSSD Voq{K}{z},Hoq+3,Mdq nil [evex m:2 p:3 l:2 w:0 0x52 /r:mem] s:AVX5124VNNIW, t:VNNIW, l:t1_4x, e:E4, w:RW|R|R|R +VPDPWSSDS Vn{K}{z},Hn,Wn|B32 nil [evex m:2 p:1 l:x w:0 0x53 /r] s:AVX512VNNI, t:VNNI, l:fv, e:E4, w:RW|R|R|R +VP4DPWSSDS Voq{K}{z},Hoq+3,Mdq nil [evex m:2 p:3 l:2 w:0 0x53 /r:mem] s:AVX5124VNNIW, t:VNNIW, l:t1_4x, e:E4, w:RW|R|R|R +VPOPCNTB Vn{K}{z},Wn nil [evex m:2 p:1 l:x w:0 0x54 /r] s:AVX512BITALG, t:VPOPCNT, l:fvm, e:E4, w:W|R|R +VPOPCNTW Vn{K}{z},Wn nil [evex m:2 p:1 l:x w:1 0x54 /r] s:AVX512BITALG, t:VPOPCNT, l:fvm, e:E4, w:W|R|R +VPOPCNTD Vn{K}{z},Wn|B32 nil [evex m:2 p:1 l:x w:0 0x55 /r] s:AVX512VPOPCNTDQ, t:VPOPCNT, l:fv, e:E4, w:W|R|R +VPOPCNTQ Vn{K}{z},Wn|B64 nil [evex m:2 p:1 l:x w:1 0x55 /r] s:AVX512VPOPCNTDQ, t:VPOPCNT, l:fv, e:E4, w:W|R|R +VPBROADCASTD Vn{K}{z},Wd nil [evex m:2 p:1 l:x w:0 0x58 /r] s:AVX512F, t:BROADCAST, l:t1s, e:E6, w:W|R|R +VBROADCASTI32X2 Vn{K}{z},Wq nil [evex m:2 p:1 l:x w:0 0x59 /r] s:AVX512DQ, t:BROADCAST, l:t2, e:E6, w:W|R|R +VPBROADCASTQ Vn{K}{z},Wq nil [evex m:2 p:1 l:x w:1 0x59 /r] s:AVX512F, t:BROADCAST, l:t1s, e:E6, w:W|R|R +VBROADCASTI32X4 Vu{K}{z},Mdq nil [evex m:2 p:1 l:x w:0 0x5A /r:mem] s:AVX512F, t:BROADCAST, a:NOL0, l:t4, e:E6, w:W|R|R +VBROADCASTI64X2 Vu{K}{z},Mdq nil [evex m:2 p:1 l:x w:1 0x5A /r:mem] s:AVX512DQ, t:BROADCAST, a:NOL0, l:t2, e:E6, w:W|R|R +VBROADCASTI32X8 Voq{K}{z},Mqq nil [evex m:2 p:1 l:2 w:0 0x5B /r:mem] s:AVX512DQ, t:BROADCAST, l:t8, e:E6, w:W|R|R +VBROADCASTI64X4 Voq{K}{z},Mqq nil [evex m:2 p:1 l:2 w:1 0x5B /r:mem] s:AVX512F, t:BROADCAST, l:t4, e:E6, w:W|R|R + +# 0x60 - 0x6F +VPEXPANDB Vn{K}{z},Wn nil [evex m:2 p:1 l:x w:0 0x62 /r] s:AVX512VBMI2, t:AVX512VBMI, l:t1s, e:E4, w:W|R|R +VPEXPANDW Vn{K}{z},Wn nil [evex m:2 p:1 l:x w:1 0x62 /r] s:AVX512VBMI2, t:AVX512VBMI, l:t1s, e:E4, w:W|R|R +VPCOMPRESSB Wn{K}{z},Vn nil [evex m:2 p:1 l:x w:0 0x63 /r] s:AVX512VBMI2, t:AVX512VBMI, l:t1s, a:NOMZ, e:E4, w:W|R|R +VPCOMPRESSW Wn{K}{z},Vn nil [evex m:2 p:1 l:x w:1 0x63 /r] s:AVX512VBMI2, t:AVX512VBMI, l:t1s, a:NOMZ, e:E4, w:W|R|R +VPBLENDMD Vn{K}{z},Hn,Wn|B32 nil [evex m:2 p:1 l:x w:0 0x64 /r] s:AVX512F, t:BLEND, l:fv, e:E4, w:W|R|R|R +VPBLENDMQ Vn{K}{z},Hn,Wn|B64 nil [evex m:2 p:1 l:x w:1 0x64 /r] s:AVX512F, t:BLEND, l:fv, e:E4, w:W|R|R|R +VBLENDMPS Vn{K}{z},Hn,Wn|B32 nil [evex m:2 p:1 l:x w:0 0x65 /r] s:AVX512F, t:BLEND, l:fv, e:E4, w:W|R|R|R +VBLENDMPD Vn{K}{z},Hn,Wn|B64 nil [evex m:2 p:1 l:x w:1 0x65 /r] s:AVX512F, t:BLEND, l:fv, e:E4, w:W|R|R|R +VPBLENDMB Vn{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:0 0x66 /r] s:AVX512BW, t:BLEND, l:fvm, e:E4, w:W|R|R|R +VPBLENDMW Vn{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:1 0x66 /r] s:AVX512BW, t:BLEND, l:fvm, e:E4, w:W|R|R|R + +VP2INTERSECTD rKq+1,Hn,Wn|B32 nil [evex m:2 p:3 l:x w:0 0x68 /r] s:AVX512VP2INTERSECT, t:AVX512VP2INTERSECT, l:fv, e:E4NF, w:W|R|R +VP2INTERSECTQ rKq+1,Hn,Wn|B64 nil [evex m:2 p:3 l:x w:1 0x68 /r] s:AVX512VP2INTERSECT, t:AVX512VP2INTERSECT, l:fv, e:E4NF, w:W|R|R + +# 0x70 - 0x7F +VPSHLDVW Vn{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:1 0x70 /r] s:AVX512VBMI2, t:AVX512VBMI, l:fvm, e:E4, w:RW|R|R|R +VPSHLDVD Vn{K}{z},Hn,Wn|B32 nil [evex m:2 p:1 l:x w:0 0x71 /r] s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R +VPSHLDVQ Vn{K}{z},Hn,Wn|B64 nil [evex m:2 p:1 l:x w:1 0x71 /r] s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R +VPSHRDVW Vn{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:1 0x72 /r] s:AVX512VBMI2, t:AVX512VBMI, l:fvm, e:E4, w:RW|R|R|R +VCVTNEPS2BF16 Vh{K}{z},Wn nil [evex m:2 p:2 l:x w:0 0x72 /r] s:AVX512BF16, t:AVX512BF16, l:fv, e:E4, w:W|R|R +VCVTNE2PS2BF16 Vn{K}{z},Hn,Wn|B32 nil [evex m:2 p:3 l:x w:0 0x72 /r] s:AVX512BF16, t:AVX512BF16, l:fv, e:E4NF, w:W|R|R|R +VPSHRDVD Vn{K}{z},Hn,Wn|B32 nil [evex m:2 p:1 l:x w:0 0x73 /r] s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R +VPSHRDVQ Vn{K}{z},Hn,Wn|B64 nil [evex m:2 p:1 l:x w:1 0x73 /r] s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R + +VPERMI2B Vn{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:0 0x75 /r] s:AVX512VBMI, t:AVX512VBMI, l:fvm, e:E4NFnb, w:RW|R|R|R +VPERMI2W Vn{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:1 0x75 /r] s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:RW|R|R|R +VPERMI2D Vn{K}{z},Hn,Wn|B32 nil [evex m:2 p:1 l:x w:0 0x76 /r] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:RW|R|R|R +VPERMI2Q Vn{K}{z},Hn,Wn|B64 nil [evex m:2 p:1 l:x w:1 0x76 /r] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:RW|R|R|R +VPERMI2PS Vn{K}{z},Hn,Wn|B32 nil [evex m:2 p:1 l:x w:0 0x77 /r] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:RW|R|R|R +VPERMI2PD Vn{K}{z},Hn,Wn|B64 nil [evex m:2 p:1 l:x w:1 0x77 /r] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:RW|R|R|R +VPBROADCASTB Vn{K}{z},Wb nil [evex m:2 p:1 l:x w:0 0x78 /r] s:AVX512BW, t:BROADCAST, l:t1s8, e:E6, w:W|R|R +VPBROADCASTW Vn{K}{z},Ww nil [evex m:2 p:1 l:x w:0 0x79 /r] s:AVX512BW, t:BROADCAST, l:t1s16, e:E6, w:W|R|R +VPBROADCASTB Vn{K}{z},Rb nil [evex m:2 p:1 l:x w:0 0x7A /r:reg] s:AVX512BW, t:BROADCAST, l:t1s8, e:E7NM, w:W|R|R +VPBROADCASTW Vn{K}{z},Rw nil [evex m:2 p:1 l:x w:0 0x7B /r:reg] s:AVX512BW, t:BROADCAST, l:t1s16, e:E7NM, w:W|R|R +VPBROADCASTD Vn{K}{z},Rd nil [evex m:2 p:1 l:x w:0 0x7C /r:reg] s:AVX512F, t:BROADCAST, l:t1s, e:E7NM, w:W|R|R +VPBROADCASTQ Vn{K}{z},Rq nil [evex m:2 p:1 l:x w:1 0x7C /r:reg] s:AVX512F, t:BROADCAST, l:t1s, e:E7NM, w:W|R|R +VPERMT2B Vn{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:0 0x7D /r] s:AVX512VBMI, t:AVX512VBMI, l:fvm, e:E4NFnb, w:RW|R|R|R +VPERMT2W Vn{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:1 0x7D /r] s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:RW|R|R|R +VPERMT2D Vn{K}{z},Hn,Wn|B32 nil [evex m:2 p:1 l:x w:0 0x7E /r] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:RW|R|R|R +VPERMT2Q Vn{K}{z},Hn,Wn|B64 nil [evex m:2 p:1 l:x w:1 0x7E /r] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:RW|R|R|R +VPERMT2PS Vn{K}{z},Hn,Wn|B32 nil [evex m:2 p:1 l:x w:0 0x7F /r] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:RW|R|R|R +VPERMT2PD Vn{K}{z},Hn,Wn|B64 nil [evex m:2 p:1 l:x w:1 0x7F /r] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:RW|R|R|R + +# 0x80 - 0x8F +VPMULTISHIFTQB Vn{K}{z},Hn,Wn|B64 nil [evex m:2 p:1 l:x w:1 0x83 /r] s:AVX512VBMI, t:AVX512VBMI, l:fv, e:E4NF, w:W|R|R|R +VEXPANDPS Vn{K}{z},Wn nil [evex m:2 p:1 l:x w:0 0x88 /r] s:AVX512F, t:EXPAND, l:t1s, e:E4nb, w:W|R|R +VEXPANDPD Vn{K}{z},Wn nil [evex m:2 p:1 l:x w:1 0x88 /r] s:AVX512F, t:EXPAND, l:t1s, e:E4nb, w:W|R|R +VPEXPANDD Vn{K}{z},Wn nil [evex m:2 p:1 l:x w:0 0x89 /r] s:AVX512F, t:EXPAND, l:t1s, e:E4nb, w:W|R|R +VPEXPANDQ Vn{K}{z},Wn nil [evex m:2 p:1 l:x w:1 0x89 /r] s:AVX512F, t:EXPAND, l:t1s, e:E4nb, w:W|R|R +VCOMPRESSPS Wn{K}{z},Vn nil [evex m:2 p:1 l:x w:0 0x8A /r] s:AVX512F, t:COMPRESS, a:NOMZ, l:t1s, e:E4nb, w:W|R|R +VCOMPRESSPD Wn{K}{z},Vn nil [evex m:2 p:1 l:x w:1 0x8A /r] s:AVX512F, t:COMPRESS, a:NOMZ, l:t1s, e:E4nb, w:W|R|R +VPCOMPRESSD Wn{K}{z},Vn nil [evex m:2 p:1 l:x w:0 0x8B /r] s:AVX512F, t:COMPRESS, a:NOMZ, l:t1s, e:E4nb, w:W|R|R +VPCOMPRESSQ Wn{K}{z},Vn nil [evex m:2 p:1 l:x w:1 0x8B /r] s:AVX512F, t:COMPRESS, a:NOMZ, l:t1s, e:E4nb, w:W|R|R +VPERMB Vn{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:0 0x8D /r] s:AVX512VBMI, t:AVX512VBMI, a:NOMZ, l:fvm, e:E4NFnb, w:W|R|R|R +VPERMW Vn{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:1 0x8D /r] s:AVX512BW, t:AVX512, l:fv, a:NOMZ, l:fvm, e:E4NFnb, w:W|R|R|R +VPSHUFBITQMB rK{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:0 0x8F /r] s:AVX512BITALG, t:AVX512VBMI, l:fvm, w:W|R|R|R + + +# 0x90 - 0x9F +VPGATHERDD Vn{K},Mvm32n nil [evex m:2 p:1 l:x w:0 0x90 /r:mem vsib] s:AVX512F, t:GATHER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VPGATHERDQ Vn{K},Mvm32h nil [evex m:2 p:1 l:x w:1 0x90 /r:mem vsib] s:AVX512F, t:GATHER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VPGATHERQD Vh{K},Mvm64n nil [evex m:2 p:1 l:x w:0 0x91 /r:mem vsib] s:AVX512F, t:GATHER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VPGATHERQQ Vn{K},Mvm64n nil [evex m:2 p:1 l:x w:1 0x91 /r:mem vsib] s:AVX512F, t:GATHER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VGATHERDPS Vn{K},Mvm32n nil [evex m:2 p:1 l:x w:0 0x92 /r:mem vsib] s:AVX512F, t:GATHER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VGATHERDPD Vn{K},Mvm32h nil [evex m:2 p:1 l:x w:1 0x92 /r:mem vsib] s:AVX512F, t:GATHER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VGATHERQPS Vh{K},Mvm64n nil [evex m:2 p:1 l:x w:0 0x93 /r:mem vsib] s:AVX512F, t:GATHER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VGATHERQPD Vn{K},Mvm64n nil [evex m:2 p:1 l:x w:1 0x93 /r:mem vsib] s:AVX512F, t:GATHER, a:MMASK, l:t1s, e:E12, w:W|R|RW + +VFMADDSUB132PS Vn{K}{z},Hn,Wn|B32{er} nil [evex m:2 p:1 l:x w:0 0x96 /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMADDSUB132PD Vn{K}{z},Hn,Wn|B64{er} nil [evex m:2 p:1 l:x w:1 0x96 /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMSUBADD132PS Vn{K}{z},Hn,Wn|B32{er} nil [evex m:2 p:1 l:x w:0 0x97 /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMSUBADD132PD Vn{K}{z},Hn,Wn|B64{er} nil [evex m:2 p:1 l:x w:1 0x97 /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMADD132PS Vn{K}{z},Hn,Wn|B32{er} nil [evex m:2 p:1 l:x w:0 0x98 /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMADD132PD Vn{K}{z},Hn,Wn|B64{er} nil [evex m:2 p:1 l:x w:1 0x98 /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMADD132SS Vdq{K}{z},Hdq,Wss{er} nil [evex m:2 p:1 l:i w:0 0x99 /r] s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFMADD132SD Vdq{K}{z},Hdq,Wsd{er} nil [evex m:2 p:1 l:i w:1 0x99 /r] s:AVX512F, t:VFMA, l:t1s, e:E2, w:RW|R|R|R +VFMSUB132PS Vn{K}{z},Hn,Wn|B32{er} nil [evex m:2 p:1 l:x w:0 0x9A /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMSUB132PD Vn{K}{z},Hn,Wn|B64{er} nil [evex m:2 p:1 l:x w:1 0x9A /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +V4FMADDPS Voq{K}{z},Hoq+3,Mdq nil [evex m:2 p:3 l:2 w:0 0x9A /r:mem] s:AVX5124FMAPS, t:VFMAPS, l:t1_4x, e:E2, w:RW|R|R|R +VFMSUB132SS Vdq{K}{z},Hdq,Wss{er} nil [evex m:2 p:1 l:i w:0 0x9B /r] s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFMSUB132SD Vdq{K}{z},Hdq,Wsd{er} nil [evex m:2 p:1 l:i w:1 0x9B /r] s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +V4FMADDSS Vdq{K}{z},Hdq+3,Mdq nil [evex m:2 p:3 l:i w:0 0x9B /r:mem] s:AVX5124FMAPS, t:VFMAPS, e:E3, l:t1_4x, w:RW|R|R|R +VFNMADD132PS Vn{K}{z},Hn,Wn|B32{er} nil [evex m:2 p:1 l:x w:0 0x9C /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFNMADD132PD Vn{K}{z},Hn,Wn|B64{er} nil [evex m:2 p:1 l:x w:1 0x9C /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFNMADD132SS Vdq{K}{z},Hdq,Wss{er} nil [evex m:2 p:1 l:i w:0 0x9D /r] s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFNMADD132SD Vdq{K}{z},Hdq,Wsd{er} nil [evex m:2 p:1 l:i w:1 0x9D /r] s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFNMSUB132PS Vn{K}{z},Hn,Wn|B32{er} nil [evex m:2 p:1 l:x w:0 0x9E /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFNMSUB132PD Vn{K}{z},Hn,Wn|B64{er} nil [evex m:2 p:1 l:x w:1 0x9E /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFNMSUB132SS Vdq{K}{z},Hdq,Wss{er} nil [evex m:2 p:1 l:i w:0 0x9F /r] s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFNMSUB132SD Vdq{K}{z},Hdq,Wsd{er} nil [evex m:2 p:1 l:i w:1 0x9F /r] s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R + +# 0xA0 - 0xAF +VPSCATTERDD Mvm32n{K},Vn nil [evex m:2 p:1 l:x w:0 0xA0 /r:mem vsib] s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VPSCATTERDQ Mvm32h{K},Vn nil [evex m:2 p:1 l:x w:1 0xA0 /r:mem vsib] s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VPSCATTERQD Mvm64n{K},Vh nil [evex m:2 p:1 l:x w:0 0xA1 /r:mem vsib] s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VPSCATTERQQ Mvm64n{K},Vn nil [evex m:2 p:1 l:x w:1 0xA1 /r:mem vsib] s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VSCATTERDPS Mvm32n{K},Vn nil [evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib] s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VSCATTERDPD Mvm32h{K},Vn nil [evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib] s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VSCATTERQPS Mvm64n{K},Vh nil [evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib] s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VSCATTERQPD Mvm64n{K},Vn nil [evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib] s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW + +VFMADDSUB213PS Vn{K}{z},Hn,Wn|B32{er} nil [evex m:2 p:1 l:x w:0 0xA6 /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMADDSUB213PD Vn{K}{z},Hn,Wn|B64{er} nil [evex m:2 p:1 l:x w:1 0xA6 /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMSUBADD213PS Vn{K}{z},Hn,Wn|B32{er} nil [evex m:2 p:1 l:x w:0 0xA7 /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMSUBADD213PD Vn{K}{z},Hn,Wn|B64{er} nil [evex m:2 p:1 l:x w:1 0xA7 /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMADD213PS Vn{K}{z},Hn,Wn|B32{er} nil [evex m:2 p:1 l:x w:0 0xA8 /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMADD213PD Vn{K}{z},Hn,Wn|B64{er} nil [evex m:2 p:1 l:x w:1 0xA8 /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMADD213SS Vdq{K}{z},Hdq,Wss{er} nil [evex m:2 p:1 l:i w:0 0xA9 /r] s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFMADD213SD Vdq{K}{z},Hdq,Wsd{er} nil [evex m:2 p:1 l:i w:1 0xA9 /r] s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFMSUB213PS Vn{K}{z},Hn,Wn|B32{er} nil [evex m:2 p:1 l:x w:0 0xAA /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMSUB213PD Vn{K}{z},Hn,Wn|B64{er} nil [evex m:2 p:1 l:x w:1 0xAA /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +V4FNMADDPS Voq{K}{z},Hoq+3,Mdq nil [evex m:2 p:3 l:2 w:0 0xAA /r:mem] s:AVX5124FMAPS, t:VFMAPS, l:t1_4x, e:E2, w:RW|R|R|R +VFMSUB213SS Vdq{K}{z},Hdq,Wss{er} nil [evex m:2 p:1 l:i w:0 0xAB /r] s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFMSUB213SD Vdq{K}{z},Hdq,Wsd{er} nil [evex m:2 p:1 l:i w:1 0xAB /r] s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +V4FNMADDSS Vdq{K}{z},Hdq+3,Mdq nil [evex m:2 p:3 l:i w:0 0xAB /r:mem] s:AVX5124FMAPS, t:VFMAPS, l:t1_4x, e:E2, w:RW|R|R|R +VFNMADD213PS Vn{K}{z},Hn,Wn|B32{er} nil [evex m:2 p:1 l:x w:0 0xAC /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFNMADD213PD Vn{K}{z},Hn,Wn|B64{er} nil [evex m:2 p:1 l:x w:1 0xAC /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFNMADD213SS Vdq{K}{z},Hdq,Wss{er} nil [evex m:2 p:1 l:i w:0 0xAD /r] s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFNMADD213SD Vdq{K}{z},Hdq,Wsd{er} nil [evex m:2 p:1 l:i w:1 0xAD /r] s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFNMSUB213PS Vn{K}{z},Hn,Wn|B32{er} nil [evex m:2 p:1 l:x w:0 0xAE /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFNMSUB213PD Vn{K}{z},Hn,Wn|B64{er} nil [evex m:2 p:1 l:x w:1 0xAE /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFNMSUB213SS Vdq{K}{z},Hdq,Wss{er} nil [evex m:2 p:1 l:i w:0 0xAF /r] s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFNMSUB213SD Vdq{K}{z},Hdq,Wsd{er} nil [evex m:2 p:1 l:i w:1 0xAF /r] s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R + +# 0xB0 - 0xBF +VPMADD52LUQ Vn{K}{z},Hn,Wn|B64 nil [evex m:2 p:1 l:x w:1 0xB4 /r] s:AVX512IFMA, t:IFMA, l:fv, e:E4, w:RW|R|R|R +VPMADD52HUQ Vn{K}{z},Hn,Wn|B64 nil [evex m:2 p:1 l:x w:1 0xB5 /r] s:AVX512IFMA, t:IFMA, l:fv, e:E4, w:RW|R|R|R +VFMADDSUB231PS Vn{K}{z},Hn,Wn|B32{er} nil [evex m:2 p:1 l:x w:0 0xB6 /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMADDSUB231PD Vn{K}{z},Hn,Wn|B64{er} nil [evex m:2 p:1 l:x w:1 0xB6 /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMSUBADD231PS Vn{K}{z},Hn,Wn|B32{er} nil [evex m:2 p:1 l:x w:0 0xB7 /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMSUBADD231PD Vn{K}{z},Hn,Wn|B64{er} nil [evex m:2 p:1 l:x w:1 0xB7 /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMADD231PS Vn{K}{z},Hn,Wn|B32{er} nil [evex m:2 p:1 l:x w:0 0xB8 /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMADD231PD Vn{K}{z},Hn,Wn|B64{er} nil [evex m:2 p:1 l:x w:1 0xB8 /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMADD231SS Vdq{K}{z},Hdq,Wss{er} nil [evex m:2 p:1 l:i w:0 0xB9 /r] s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFMADD231SD Vdq{K}{z},Hdq,Wsd{er} nil [evex m:2 p:1 l:i w:1 0xB9 /r] s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFMSUB231PS Vn{K}{z},Hn,Wn|B32{er} nil [evex m:2 p:1 l:x w:0 0xBA /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMSUB231PD Vn{K}{z},Hn,Wn|B64{er} nil [evex m:2 p:1 l:x w:1 0xBA /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMSUB231SS Vdq{K}{z},Hdq,Wss{er} nil [evex m:2 p:1 l:i w:0 0xBB /r] s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFMSUB231SD Vdq{K}{z},Hdq,Wsd{er} nil [evex m:2 p:1 l:i w:1 0xBB /r] s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFNMADD231PS Vn{K}{z},Hn,Wn|B32{er} nil [evex m:2 p:1 l:x w:0 0xBC /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFNMADD231PD Vn{K}{z},Hn,Wn|B64{er} nil [evex m:2 p:1 l:x w:1 0xBC /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFNMADD231SS Vdq{K}{z},Hdq,Wss{er} nil [evex m:2 p:1 l:i w:0 0xBD /r] s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFNMADD231SD Vdq{K}{z},Hdq,Wsd{er} nil [evex m:2 p:1 l:i w:1 0xBD /r] s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFNMSUB231PS Vn{K}{z},Hn,Wn|B32{er} nil [evex m:2 p:1 l:x w:0 0xBE /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFNMSUB231PD Vn{K}{z},Hn,Wn|B64{er} nil [evex m:2 p:1 l:x w:1 0xBE /r] s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFNMSUB231SS Vdq{K}{z},Hdq,Wss{er} nil [evex m:2 p:1 l:i w:0 0xBF /r] s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFNMSUB231SD Vdq{K}{z},Hdq,Wsd{er} nil [evex m:2 p:1 l:i w:1 0xBF /r] s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R + +# 0xC0 - 0xCF +VPCONFLICTD Vn{K}{z},Wn|B32 nil [evex m:2 p:1 l:x w:0 0xC4 /r] s:AVX512CD, t:CONFLICT, l:fv, e:E4NF, w:W|R|R +VPCONFLICTQ Vn{K}{z},Wn|B64 nil [evex m:2 p:1 l:x w:1 0xC4 /r] s:AVX512CD, t:CONFLICT, l:fv, e:E4NF, w:W|R|R +VGATHERPF0DPS Mvm32n{K} nil [evex m:2 p:1 l:2 w:0 0xC6 /1:mem vsib] s:AVX512PF, t:GATHER, a:MMASK, l:t1s, e:E12NP, w:R|R +VGATHERPF0DPD Mvm32h{K} nil [evex m:2 p:1 l:2 w:1 0xC6 /1:mem vsib] s:AVX512PF, t:GATHER, a:MMASK, l:t1s, e:E12NP, w:R|R +VGATHERPF1DPS Mvm32n{K} nil [evex m:2 p:1 l:2 w:0 0xC6 /2:mem vsib] s:AVX512PF, t:GATHER, a:MMASK, l:t1s, e:E12NP, w:R|R +VGATHERPF1DPD Mvm32h{K} nil [evex m:2 p:1 l:2 w:1 0xC6 /2:mem vsib] s:AVX512PF, t:GATHER, a:MMASK, l:t1s, e:E12NP, w:R|R +VSCATTERPF0DPS Mvm32n{K} nil [evex m:2 p:1 l:2 w:0 0xC6 /5:mem vsib] s:AVX512PF, t:SCATTER, a:MMASK, l:t1s, e:E12NP, w:R|R +VSCATTERPF0DPD Mvm32h{K} nil [evex m:2 p:1 l:2 w:1 0xC6 /5:mem vsib] s:AVX512PF, t:SCATTER, a:MMASK, l:t1s, e:E12NP, w:R|R +VSCATTERPF1DPS Mvm32n{K} nil [evex m:2 p:1 l:2 w:0 0xC6 /6:mem vsib] s:AVX512PF, t:SCATTER, a:MMASK, l:t1s, e:E12NP, w:R|R +VSCATTERPF1DPD Mvm32h{K} nil [evex m:2 p:1 l:2 w:1 0xC6 /6:mem vsib] s:AVX512PF, t:SCATTER, a:MMASK, l:t1s, e:E12NP, w:R|R +VGATHERPF0QPS Mvm64n{K} nil [evex m:2 p:1 l:2 w:0 0xC7 /1:mem vsib] s:AVX512PF, t:GATHER, a:MMASK, l:t1s, e:E12NP, w:R|R +VGATHERPF0QPD Mvm64n{K} nil [evex m:2 p:1 l:2 w:1 0xC7 /1:mem vsib] s:AVX512PF, t:GATHER, a:MMASK, l:t1s, e:E12NP, w:R|R +VGATHERPF1QPS Mvm64n{K} nil [evex m:2 p:1 l:2 w:0 0xC7 /2:mem vsib] s:AVX512PF, t:GATHER, a:MMASK, l:t1s, e:E12NP, w:R|R +VGATHERPF1QPD Mvm64n{K} nil [evex m:2 p:1 l:2 w:1 0xC7 /2:mem vsib] s:AVX512PF, t:GATHER, a:MMASK, l:t1s, e:E12NP, w:R|R +VSCATTERPF0QPS Mvm64n{K} nil [evex m:2 p:1 l:2 w:0 0xC7 /5:mem vsib] s:AVX512PF, t:SCATTER, a:MMASK, l:t1s, e:E12NP, w:R|R +VSCATTERPF0QPD Mvm64n{K} nil [evex m:2 p:1 l:2 w:1 0xC7 /5:mem vsib] s:AVX512PF, t:SCATTER, a:MMASK, l:t1s, e:E12NP, w:R|R +VSCATTERPF1QPS Mvm64n{K} nil [evex m:2 p:1 l:2 w:0 0xC7 /6:mem vsib] s:AVX512PF, t:SCATTER, a:MMASK, l:t1s, e:E12NP, w:R|R +VSCATTERPF1QPD Mvm64n{K} nil [evex m:2 p:1 l:2 w:1 0xC7 /6:mem vsib] s:AVX512PF, t:SCATTER, a:MMASK, l:t1s, e:E12NP, w:R|R + +VEXP2PS Voq{K}{z},Woq|B32{sae} nil [evex m:2 p:1 l:2 w:0 0xC8 /r] s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R +VEXP2PD Voq{K}{z},Woq|B64{sae} nil [evex m:2 p:1 l:2 w:1 0xC8 /r] s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R +VRCP28PS Voq{K}{z},Woq|B32{sae} nil [evex m:2 p:1 l:2 w:0 0xCA /r] s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R +VRCP28PD Voq{K}{z},Woq|B64{sae} nil [evex m:2 p:1 l:2 w:1 0xCA /r] s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R +VRCP28SS Vdq{K}{z},Hdq,Wss{sae} nil [evex m:2 p:1 l:i w:0 0xCB /r] s:AVX512ER, t:KNL, l:t1s, e:E3, w:W|R|R|R +VRCP28SD Vdq{K}{z},Hdq,Wsd{sae} nil [evex m:2 p:1 l:i w:1 0xCB /r] s:AVX512ER, t:KNL, l:t1s, e:E3, w:W|R|R|R +VRSQRT28PS Voq{K}{z},Woq|B32{sae} nil [evex m:2 p:1 l:2 w:0 0xCC /r] s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R +VRSQRT28PD Voq{K}{z},Woq|B64{sae} nil [evex m:2 p:1 l:2 w:1 0xCC /r] s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R +VRSQRT28SS Vdq{K}{z},Hdq,Wss{sae} nil [evex m:2 p:1 l:i w:0 0xCD /r] s:AVX512ER, t:KNL, l:t1s, e:E3, w:W|R|R|R +VRSQRT28SD Vdq{K}{z},Hdq,Wsd{sae} nil [evex m:2 p:1 l:i w:1 0xCD /r] s:AVX512ER, t:KNL, l:t1s, e:E3, w:W|R|R|R +VGF2P8MULB Vn{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:0 0xCF /r] s:GFNI, t:GFNI, l:fvm, e:E4, w:W|R|R|R + +# 0xD0 - 0xDF +VAESENC Vn,Hn,Wn nil [evex m:2 p:1 l:x w:i 0xDC /r] s:VAES, t:VAES, l:fvm, e:E4NF, w:W|R|R +VAESENCLAST Vn,Hn,Wn nil [evex m:2 p:1 l:x w:i 0xDD /r] s:VAES, t:VAES, l:fvm, e:E4NF, w:W|R|R +VAESDEC Vn,Hn,Wn nil [evex m:2 p:1 l:x w:i 0xDE /r] s:VAES, t:VAES, l:fvm, e:E4NF, w:W|R|R +VAESDECLAST Vn,Hn,Wn nil [evex m:2 p:1 l:x w:i 0xDF /r] s:VAES, t:VAES, l:fvm, e:E4NF, w:W|R|R + +# 0xE0 - 0xEF + +# 0xF0 - 0xFF diff --git a/isagenerator/instructions/table_evex3.dat b/isagenerator/instructions/table_evex3.dat new file mode 100644 index 0000000..6212e46 --- /dev/null +++ b/isagenerator/instructions/table_evex3.dat @@ -0,0 +1,120 @@ +# Mnemonic Explicit Operands Implicit Encoding Fags, Prefixes, Set, Category, Class, RW map, Additional ops +#------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +# 0x00 - 0x0F +VPERMQ Vu{K}{z},Wu|B64,Ib nil [evex m:3 p:1 l:x w:1 0x00 /r ib] s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R +VPERMPD Vu{K}{z},Wu|B64,Ib nil [evex m:3 p:1 l:x w:1 0x01 /r ib] s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R +VALIGND Vn{K}{z},Hn,Wn|B32,Ib nil [evex m:3 p:1 l:x w:0 0x03 /r ib] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R|R +VALIGNQ Vn{K}{z},Hn,Wn|B64,Ib nil [evex m:3 p:1 l:x w:1 0x03 /r ib] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R|R +VPERMILPS Vn{K}{z},Wn|B32,Ib nil [evex m:3 p:1 l:x w:0 0x04 /r ib] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VPERMILPD Vn{K}{z},Wn|B64,Ib nil [evex m:3 p:1 l:x w:1 0x05 /r ib] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VRNDSCALEPS Vn{K}{z},Wn|B32{sae},Ib nil [evex m:3 p:1 l:x w:0 0x08 /r ib] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VRNDSCALEPD Vn{K}{z},Wn|B64{sae},Ib nil [evex m:3 p:1 l:x w:1 0x09 /r ib] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VRNDSCALESS Vdq{K}{z},Hdq,Wss{sae},Ib nil [evex m:3 p:1 l:i w:0 0x0A /r ib] s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R +VRNDSCALESD Vdq{K}{z},Hdq,Wsd{sae},Ib nil [evex m:3 p:1 l:i w:1 0x0B /r ib] s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R +VPALIGNR Vn{K}{z},Hn,Wn,Ib nil [evex m:3 p:1 l:x w:i 0x0F /r ib] s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R|R + +# 0x10 - 0x1F +VPEXTRB Mb,Vdq,Ib nil [evex m:3 p:1 l:0 w:i 0x14 /r:mem ib] s:AVX512BW, t:AVX512, l:t1s, e:E9NF, w:W|R|R +VPEXTRB Ry,Vdq,Ib nil [evex m:3 p:1 l:0 w:i 0x14 /r:reg ib] s:AVX512BW, t:AVX512, l:t1s, e:E9NF, w:W|R|R +VPEXTRW Mw,Vdq,Ib nil [evex m:3 p:1 l:0 w:i 0x15 /r:mem ib] s:AVX512BW, t:AVX512, l:t1s, e:E9NF, w:W|R|R +VPEXTRW Ry,Vdq,Ib nil [evex m:3 p:1 l:0 w:i 0x15 /r:reg ib] s:AVX512BW, t:AVX512, l:t1s, e:E9NF, w:W|R|R +VPEXTRD Ed,Vdq,Ib nil [evex m:3 p:1 l:0 w:0 0x16 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R +VPEXTRQ Eq,Vdq,Ib nil [evex m:3 p:1 l:0 w:1 0x16 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R +VEXTRACTPS Md,Vdq,Ib nil [evex m:3 p:1 l:0 w:i 0x17 /r:mem ib] s:AVX512F, t:AVX512, l:t1s, e:E9NF, w:W|R|R +VEXTRACTPS Ry,Vdq,Ib nil [evex m:3 p:1 l:0 w:i 0x17 /r:reg ib] s:AVX512F, t:AVX512, l:t1s, e:E9NF, w:W|R|R +VINSERTF32X4 Vu{K}{z},Hu,Wdq,Ib nil [evex m:3 p:1 l:x w:0 0x18 /r ib] s:AVX512F, t:AVX512, a:NOL0, l:t4, e:E6NF, w:W|R|R|R|R +VINSERTF64X2 Vu{K}{z},Hu,Wdq,Ib nil [evex m:3 p:1 l:x w:1 0x18 /r ib] s:AVX512DQ, t:AVX512, a:NOL0, l:t2, e:E6NF, w:W|R|R|R|R +VEXTRACTF32X4 Wdq{K}{z},Vu,Ib nil [evex m:3 p:1 l:x w:0 0x19 /r ib] s:AVX512F, t:AVX512, a:NOL0, l:t4, e:E6NF, w:W|R|R|R +VEXTRACTF64X2 Wdq{K}{z},Vu,Ib nil [evex m:3 p:1 l:x w:1 0x19 /r ib] s:AVX512DQ, t:AVX512, a:NOL0, l:t2, e:E6NF, w:W|R|R|R +VINSERTF32X8 Voq{K}{z},Hoq,Wqq,Ib nil [evex m:3 p:1 l:2 w:0 0x1A /r ib] s:AVX512DQ, t:AVX512, l:t8, e:E6NF, w:W|R|R|R|R +VINSERTF64X4 Voq{K}{z},Hoq,Wqq,Ib nil [evex m:3 p:1 l:2 w:1 0x1A /r ib] s:AVX512F, t:AVX512, l:t4, e:E6NF, w:W|R|R|R|R +VEXTRACTF32X8 Wqq{K}{z},Voq,Ib nil [evex m:3 p:1 l:2 w:0 0x1B /r ib] s:AVX512DQ, t:AVX512, l:t8, e:E6NF, w:W|R|R|R +VEXTRACTF64X4 Wqq{K}{z},Voq,Ib nil [evex m:3 p:1 l:2 w:1 0x1B /r ib] s:AVX512F, t:AVX512, l:t4, e:E6NF, w:W|R|R|R +VCVTPS2PH Wh{K}{z},Vn{sae},Ib nil [evex m:3 p:1 l:x w:0 0x1D /r ib] s:AVX512F, t:CONVERT, l:hvm, e:E11, w:W|R|R|R +VPCMPUD rKq{K},Hn,Wn|B32,Ib nil [evex m:3 p:1 l:x w:0 0x1E /r ib] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R|R +VPCMPUQ rKq{K},Hn,Wn|B64,Ib nil [evex m:3 p:1 l:x w:1 0x1E /r ib] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R|R +VPCMPD rKq{K},Hn,Wn|B32,Ib nil [evex m:3 p:1 l:x w:0 0x1F /r ib] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R|R +VPCMPQ rKq{K},Hn,Wn|B64,Ib nil [evex m:3 p:1 l:x w:1 0x1F /r ib] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R|R + +# 0x20 - 0x2F +VPINSRB Vdq,Hdq,Mb,Ib nil [evex m:3 p:1 l:0 w:i 0x20 /r:mem ib] s:AVX512BW, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R +VPINSRB Vdq,Hdq,Rd,Ib nil [evex m:3 p:1 l:0 w:i 0x20 /r:reg ib] s:AVX512BW, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R +VINSERTPS Vdq,Hdq,Md,Ib nil [evex m:3 p:1 l:0 w:i 0x21 /r:mem ib] s:AVX512F, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R +VINSERTPS Vdq,Hdq,Udq,Ib nil [evex m:3 p:1 l:0 w:i 0x21 /r:reg ib] s:AVX512F, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R +VPINSRD Vdq,Hdq,Ed,Ib nil [evex m:3 p:1 l:0 w:0 0x22 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R +VPINSRQ Vdq,Hdq,Eq,Ib nil [evex m:3 p:1 l:0 w:1 0x22 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R +VSHUFF32X4 Vu{K}{z},Hu,Wu|B32,Ib nil [evex m:3 p:1 l:x w:0 0x23 /r ib] s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R|R +VSHUFF64X2 Vu{K}{z},Hu,Wu|B64,Ib nil [evex m:3 p:1 l:x w:1 0x23 /r ib] s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R|R +VPTERNLOGD Vn{K}{z},Hn,Wn|B32,Ib nil [evex m:3 p:1 l:x w:0 0x25 /r ib] s:AVX512F, t:LOGICAL, l:fv, e:E4, w:RW|R|R|R|R +VPTERNLOGQ Vn{K}{z},Hn,Wn|B64,Ib nil [evex m:3 p:1 l:x w:1 0x25 /r ib] s:AVX512F, t:LOGICAL, l:fv, e:E4, w:RW|R|R|R|R +VGETMANTPS Vn{K}{z},Wn|B32{sae},Ib nil [evex m:3 p:1 l:x w:0 0x26 /r ib] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VGETMANTPD Vn{K}{z},Wn|B64{sae},Ib nil [evex m:3 p:1 l:x w:1 0x26 /r ib] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VGETMANTSS Vdq{K}{z},Hdq,Wss{sae},Ib nil [evex m:3 p:1 l:i w:0 0x27 /r ib] s:AVX512F, t:AVX512, l:t1s, e:E2, w:W|R|R|R|R +VGETMANTSD Vdq{K}{z},Hdq,Wsd{sae},Ib nil [evex m:3 p:1 l:i w:1 0x27 /r ib] s:AVX512F, t:AVX512, l:t1s, e:E2, w:W|R|R|R|R + +# 0x30 - 0x3F +VINSERTI32X4 Vu{K}{z},Hu,Wdq,Ib nil [evex m:3 p:1 l:x w:0 0x38 /r ib] s:AVX512F, t:AVX512, a:NOL0, l:t4, e:E6NF, w:W|R|R|R|R +VINSERTI64X2 Vu{K}{z},Hu,Wdq,Ib nil [evex m:3 p:1 l:x w:1 0x38 /r ib] s:AVX512DQ, t:AVX512, a:NOL0, l:t2, e:E6NF, w:W|R|R|R|R +VEXTRACTI32X4 Wdq{K}{z},Vu,Ib nil [evex m:3 p:1 l:x w:0 0x39 /r ib] s:AVX512F, t:AVX512, a:NOL0, l:t4, e:E6NF, w:W|R|R|R +VEXTRACTI64X2 Wdq{K}{z},Vu,Ib nil [evex m:3 p:1 l:x w:1 0x39 /r ib] s:AVX512DQ, t:AVX512, a:NOL0, l:t2, e:E6NF, w:W|R|R|R +VINSERTI32X8 Voq{K}{z},Hoq,Wqq,Ib nil [evex m:3 p:1 l:2 w:0 0x3A /r ib] s:AVX512DQ, t:AVX512, l:t8, e:E6NF, w:W|R|R|R|R +VINSERTI64X4 Voq{K}{z},Hoq,Wqq,Ib nil [evex m:3 p:1 l:2 w:1 0x3A /r ib] s:AVX512F, t:AVX512, l:t4, e:E6NF, w:W|R|R|R|R +VEXTRACTI32X8 Wqq{K}{z},Voq,Ib nil [evex m:3 p:1 l:2 w:0 0x3B /r ib] s:AVX512DQ, t:AVX512, l:t8, e:E6NF, w:W|R|R|R +VEXTRACTI64X4 Wqq{K}{z},Voq,Ib nil [evex m:3 p:1 l:2 w:1 0x3B /r ib] s:AVX512F, t:AVX512, l:t4, e:E6NF, w:W|R|R|R +VPCMPUB rKq{K},Hn,Wn,Ib nil [evex m:3 p:1 l:x w:0 0x3E /r ib] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R|R +VPCMPUW rKq{K},Hn,Wn,Ib nil [evex m:3 p:1 l:x w:1 0x3E /r ib] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R|R +VPCMPB rKq{K},Hn,Wn,Ib nil [evex m:3 p:1 l:x w:0 0x3F /r ib] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R|R +VPCMPW rKq{K},Hn,Wn,Ib nil [evex m:3 p:1 l:x w:1 0x3F /r ib] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R|R + +# 0x40 - 0x4F +VDBPSADBW Vn{K}{z},Hn,Wn,Ib nil [evex m:3 p:1 l:x w:0 0x42 /r ib] s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R|R +VSHUFI32X4 Vu{K}{z},Hu,Wu|B32,Ib nil [evex m:3 p:1 l:x w:0 0x43 /r ib] s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R|R +VSHUFI64X2 Vu{K}{z},Hu,Wu|B64,Ib nil [evex m:3 p:1 l:x w:1 0x43 /r ib] s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R|R +VPCLMULQDQ Vn,Hn,Wn,Ib nil [evex m:3 p:1 l:x w:i 0x44 /r ib] s:VPCLMULQDQ, t:VPCLMULQDQ, l:fvm, e:E4NF, w:W|R|R|R + +# 0x50 - 0x5F +VRANGEPS Vn{K}{z},Hn,Wn|B32{sae},Ib nil [evex m:3 p:1 l:x w:0 0x50 /r ib] s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R|R +VRANGEPD Vn{K}{z},Hn,Wn|B64{sae},Ib nil [evex m:3 p:1 l:x w:1 0x50 /r ib] s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R|R +VRANGESS Vdq{K}{z},Hdq,Wss{sae},Ib nil [evex m:3 p:1 l:i w:0 0x51 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R +VRANGESD Vdq{K}{z},Hdq,Wsd{sae},Ib nil [evex m:3 p:1 l:i w:1 0x51 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R +VFIXUPIMMPS Vn{K}{z},Hn,Wn|B32{sae},Ib nil [evex m:3 p:1 l:x w:0 0x54 /r ib] s:AVX512F, t:AVX512, l:fv, e:E2, w:RW|R|R|R|R +VFIXUPIMMPD Vn{K}{z},Hn,Wn|B64{sae},Ib nil [evex m:3 p:1 l:x w:1 0x54 /r ib] s:AVX512F, t:AVX512, l:fv, e:E2, w:RW|R|R|R|R +VFIXUPIMMSS Vdq{K}{z},Hdq,Wss{sae},Ib nil [evex m:3 p:1 l:i w:0 0x55 /r ib] s:AVX512F, t:AVX512, l:t1s, e:E3, w:RW|R|R|R|R +VFIXUPIMMSD Vdq{K}{z},Hdq,Wsd{sae},Ib nil [evex m:3 p:1 l:i w:1 0x55 /r ib] s:AVX512F, t:AVX512, l:t1s, e:E3, w:RW|R|R|R|R +VREDUCEPS Vn{K}{z},Wn|B32{sae},Ib nil [evex m:3 p:1 l:x w:0 0x56 /r ib] s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R +VREDUCEPD Vn{K}{z},Wn|B64{sae},Ib nil [evex m:3 p:1 l:x w:1 0x56 /r ib] s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R +VREDUCESS Vdq{K}{z},Hdq,Wss{sae},Ib nil [evex m:3 p:1 l:i w:0 0x57 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R +VREDUCESD Vdq{K}{z},Hdq,Wsd{sae},Ib nil [evex m:3 p:1 l:i w:1 0x57 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R + +# 0x60 - 0x6F +VFPCLASSPS rKq{K},Wn|B32,Ib nil [evex m:3 p:1 l:x w:0 0x66 /r ib] s:AVX512DQ, t:AVX512, l:fv, e:E4, w:W|R|R|R +VFPCLASSPD rKq{K},Wn|B64,Ib nil [evex m:3 p:1 l:x w:1 0x66 /r ib] s:AVX512DQ, t:AVX512, l:fv, e:E4, w:W|R|R|R +VFPCLASSSS rKq{K},Wss,Ib nil [evex m:3 p:1 l:i w:0 0x67 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E6, w:W|R|R|R +VFPCLASSSD rKq{K},Wsd,Ib nil [evex m:3 p:1 l:i w:1 0x67 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E6, w:W|R|R|R + +# 0x70 - 0x7F +VPSHLDW Vn{K}{z},Hn,Wn,Ib nil [evex m:3 p:1 l:x w:1 0x70 /r ib] s:AVX512VBMI2, t:AVX512VBMI, l:fvm, e:E4, w:RW|R|R|R|R +VPSHLDD Vn{K}{z},Hn,Wn|B32,Ib nil [evex m:3 p:1 l:x w:0 0x71 /r ib] s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R|R +VPSHLDQ Vn{K}{z},Hn,Wn|B64,Ib nil [evex m:3 p:1 l:x w:1 0x71 /r ib] s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R|R +VPSHRDW Vn{K}{z},Hn,Wn,Ib nil [evex m:3 p:1 l:x w:1 0x72 /r ib] s:AVX512VBMI2, t:AVX512VBMI, l:fvm, e:E4, w:RW|R|R|R|R +VPSHRDD Vn{K}{z},Hn,Wn|B32,Ib nil [evex m:3 p:1 l:x w:0 0x73 /r ib] s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R|R +VPSHRDQ Vn{K}{z},Hn,Wn|B64,Ib nil [evex m:3 p:1 l:x w:1 0x73 /r ib] s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R|R + + +# 0x80 - 0x8F + +# 0x90 - 0x9F + +# 0xA0 - 0xAF + +# 0xB0 - 0xBF + +# 0xC0 - 0xCF +VGF2P8AFFINEQB Vn{K}{z},Hn,Wn|B64,Ib nil [evex m:3 p:1 l:x w:1 0xCE /r ib] s:GFNI, t:GFNI, l:fv, e:E4NF, w:W|R|R|R|R +VGF2P8AFFINEINVQB Vn{K}{z},Hn,Wn|B64,Ib nil [evex m:3 p:1 l:x w:1 0xCF /r ib] s:GFNI, t:GFNI, l:fv, e:E4NF, w:W|R|R|R|R + +# 0xD0 - 0xDF + +# 0xE0 - 0xEF + +# 0xF0 - 0xFF diff --git a/isagenerator/instructions/table_fpu.dat b/isagenerator/instructions/table_fpu.dat new file mode 100644 index 0000000..8cb6864 --- /dev/null +++ b/isagenerator/instructions/table_fpu.dat @@ -0,0 +1,175 @@ +# Mnemonic Explicit Implicit Operands Encoding Flags, Prefixes, Set, Category, Class, RW map, Additional ops +#------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +# 0xD8 FPU instructions, mod mem +FADD ST(0),Mfd X87STATUS [0xD8 /0:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FMUL ST(0),Mfd X87STATUS [0xD8 /1:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FCOM ST(0),Mfd X87STATUS [0xD8 /2:mem] s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=0|C2=m|C3=m +FCOMP ST(0),Mfd X87STATUS [0xD8 /3:mem] s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=0|C2=m|C3=m +FSUB ST(0),Mfd X87STATUS [0xD8 /4:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FSUBR ST(0),Mfd X87STATUS [0xD8 /5:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FDIV ST(0),Mfd X87STATUS [0xD8 /6:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FDIVR ST(0),Mfd X87STATUS [0xD8 /7:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FADD ST(0),ST(i) X87STATUS [0xD8 /0:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FMUL ST(0),ST(i) X87STATUS [0xD8 /1:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FCOM ST(0),ST(i) X87STATUS [0xD8 /2:reg] s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=0|C2=m|C3=m +FCOMP ST(0),ST(i) X87STATUS [0xD8 /3:reg] s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=0|C2=m|C3=m +FSUB ST(0),ST(i) X87STATUS [0xD8 /4:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FSUBR ST(0),ST(i) X87STATUS [0xD8 /5:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FDIV ST(0),ST(i) X87STATUS [0xD8 /6:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FDIVR ST(0),ST(i) X87STATUS [0xD8 /7:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m + +# 0xD9 +FLD ST(0),Mfd X87STATUS [0xD9 /0:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m +FST Mfd,ST(0) X87STATUS [0xD9 /2:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m +FSTP Mfd,ST(0) X87STATUS [0xD9 /3:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m +FLDENV Mfe X87STATUS [0xD9 /4:mem] s:X87, t:X87_ALU, w:R|W, u:C0=m|C1=m|C2=m|C3=m +FLDCW Mw X87CONTROL,X87STATUS [0xD9 /5:mem] s:X87, t:X87_ALU, w:R|W|W, u:C0=u|C1=u|C2=u|C3=u +FNSTENV Mfe X87STATUS [0xD9 /6:mem] s:X87, t:X87_ALU, w:W|W, u:C0=u|C1=u|C2=u|C3=u +FNSTCW Mw X87CONTROL,X87STATUS [0xD9 /7:mem] s:X87, t:X87_ALU, w:W|R|W, u:C0=u|C1=u|C2=u|C3=u + +FNOP nil nil [0xD9 /0xD0] s:X87, t:X87_ALU, w:W, u:C0=u|C1=u|C2=u|C3=u +FCHS nil X87STATUS [0xD9 /0xE0] s:X87, t:X87_ALU, w:W, u:C1=0 +FABS nil X87STATUS [0xD9 /0xE1] s:X87, t:X87_ALU, w:W, u:C1=0 +FTST nil X87STATUS [0xD9 /0xE4] s:X87, t:X87_ALU, w:W, u:C0=m|C1=0|C2=m|C3=m +FXAM nil X87STATUS [0xD9 /0xE5] s:X87, t:X87_ALU, w:W, u:C0=m|C1=m|C2=m|C3=m +FLD1 nil X87STATUS [0xD9 /0xE8] s:X87, t:X87_ALU, w:W, u:C1=m +FLDL2T nil X87STATUS [0xD9 /0xE9] s:X87, t:X87_ALU, w:W, u:C1=m +FLDL2E nil X87STATUS [0xD9 /0xEA] s:X87, t:X87_ALU, w:W, u:C1=m +FLDPI nil X87STATUS [0xD9 /0xEB] s:X87, t:X87_ALU, w:W, u:C1=m +FLDLG2 nil X87STATUS [0xD9 /0xEC] s:X87, t:X87_ALU, w:W, u:C1=m +FLDLN2 nil X87STATUS [0xD9 /0xED] s:X87, t:X87_ALU, w:W, u:C1=m +FLDZ nil X87STATUS [0xD9 /0xEE] s:X87, t:X87_ALU, w:W, u:C1=m +F2XM1 nil X87STATUS [0xD9 /0xF0] s:X87, t:X87_ALU, w:W, u:C1=m +FYL2X nil X87STATUS [0xD9 /0xF1] s:X87, t:X87_ALU, w:W, u:C1=m +FPTAN nil X87STATUS [0xD9 /0xF2] s:X87, t:X87_ALU, w:W, u:C1=m|C2=m +FPATAN nil X87STATUS [0xD9 /0xF3] s:X87, t:X87_ALU, w:W, u:C1=m +FXTRACT nil X87STATUS [0xD9 /0xF4] s:X87, t:X87_ALU, w:W, u:C1=m +FPREM1 nil X87STATUS [0xD9 /0xF5] s:X87, t:X87_ALU, w:W, u:C0=m|C1=m|C2=m|C3=m +FDECSTP nil X87STATUS [0xD9 /0xF6] s:X87, t:X87_ALU, w:W, u:C1=0 +FINCSTP nil X87STATUS [0xD9 /0xF7] s:X87, t:X87_ALU, w:W, u:C1=0 +FPREM nil X87STATUS [0xD9 /0xF8] s:X87, t:X87_ALU, w:W, u:C0=m|C1=m|C2=m|C3=m +FYL2XP1 nil X87STATUS [0xD9 /0xF9] s:X87, t:X87_ALU, w:W, u:C1=m +FSQRT nil X87STATUS [0xD9 /0xFA] s:X87, t:X87_ALU, w:W, u:C1=m +FSINCOS nil X87STATUS [0xD9 /0xFB] s:X87, t:X87_ALU, w:W, u:C1=m|C2=m +FRNDINT nil X87STATUS [0xD9 /0xFC] s:X87, t:X87_ALU, w:W, u:C1=m +FSCALE nil X87STATUS [0xD9 /0xFD] s:X87, t:X87_ALU, w:W, u:C1=m +FSIN nil X87STATUS [0xD9 /0xFE] s:X87, t:X87_ALU, w:W, u:C1=m|C2=m +FCOS nil X87STATUS [0xD9 /0xFF] s:X87, t:X87_ALU, w:W, u:C1=m|C2=m +FLD ST(0),ST(i) X87STATUS [0xD9 /0:reg] s:X87, t:X87_ALU, w:W|R|W, u:C1=m +FXCH ST(0),ST(i) X87STATUS [0xD9 /1:reg] s:X87, t:X87_ALU, w:RW|RW|W, u:C1=0 +FSTPNCE ST(i),ST(0) X87STATUS [0xD9 /3:reg] s:X87, t:X87_ALU, w:W|R|W + +# 0xDA +FIADD ST(0),Md X87STATUS [0xDA /0:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FIMUL ST(0),Md X87STATUS [0xDA /1:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FICOM ST(0),Md X87STATUS [0xDA /2:mem] s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=m|C2=m|C3=m +FICOMP ST(0),Md X87STATUS [0xDA /3:mem] s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=m|C2=m|C3=m +FISUB ST(0),Md X87STATUS [0xDA /4:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FISUBR ST(0),Md X87STATUS [0xDA /5:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FIDIV ST(0),Md X87STATUS [0xDA /6:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FIDIVR ST(0),Md X87STATUS [0xDA /7:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m + + +FUCOMPP nil X87STATUS [0xDA /0xE9] s:X87, t:X87_ALU, w:W, u:C0=m|C1=m|C2=m|C3=m +FCMOVB ST(0),ST(i) X87STATUS,Fv [0xDA /0:reg] s:X87, t:X87_ALU, w:CW|R|RW|W, f:CF=t, u:C1=m +FCMOVE ST(0),ST(i) X87STATUS,Fv [0xDA /1:reg] s:X87, t:X87_ALU, w:CW|R|RW|W, f:ZF=t, u:C1=m +FCMOVBE ST(0),ST(i) X87STATUS,Fv [0xDA /2:reg] s:X87, t:X87_ALU, w:CW|R|RW|W, f:CF=t|ZF=t, u:C1=m +FCMOVU ST(0),ST(i) X87STATUS,Fv [0xDA /3:reg] s:X87, t:X87_ALU, w:CW|R|RW|W, f:PF=t, u:C1=m + + +# 0xDB +FILD ST(0),Md X87STATUS [0xDB /0:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m +FISTTP Md,ST(0) X87STATUS [0xDB /1:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=0 +FIST Md,ST(0) X87STATUS [0xDB /2:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m +FISTP Md,ST(0) X87STATUS [0xDB /3:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m +FLD ST(0),Mft X87STATUS [0xDB /5:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m +FSTP Mft,ST(0) X87STATUS [0xDB /7:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m +FNOP nil nil [0xDB /0xE0] s:X87, t:X87_ALU, u:C0=u|C1=u|C2=u|C3=u +FNDISI nil nil [0xDB /0xE1] s:X87, t:X87_ALU, w:W +FNCLEX nil X87STATUS [0xDB /0xE2] s:X87, t:X87_ALU, w:W +FNINIT nil X87CONTROL,X87TAG,X87STATUS [0xDB /0xE3] s:X87, t:X87_ALU, w:W|W|W, u:C0=0|C1=0|C2=0|C3=0 +FNOP nil nil [0xDB /0xE4] s:X87, t:X87_ALU, u:C0=u|C1=u|C2=u|C3=u +FCMOVNB ST(0),ST(i) X87STATUS,Fv [0xDB /0:reg] s:X87, t:X87_ALU, w:CW|R|RW|W, f:CF=t, u:C1=m +FCMOVNE ST(0),ST(i) X87STATUS,Fv [0xDB /1:reg] s:X87, t:X87_ALU, w:CW|R|RW|W, f:ZF=t, u:C1=m +FCMOVNBE ST(0),ST(i) X87STATUS,Fv [0xDB /2:reg] s:X87, t:X87_ALU, w:CW|R|RW|W, f:CF=t|ZF=t, u:C1=m +FCMOVNU ST(0),ST(i) X87STATUS,Fv [0xDB /3:reg] s:X87, t:X87_ALU, w:CW|R|RW|W, f:PF=t, u:C1=m +FUCOMI ST(0),ST(i) X87STATUS,Fv [0xDB /5:reg] s:X87, t:X87_ALU, w:R|R|RW|W, f:CF=m|PF=m|ZF=m|OF=0, u:C0=m|C1=0|C2=m|C3=m +FCOMI ST(0),ST(i) X87STATUS,Fv [0xDB /6:reg] s:X87, t:X87_ALU, w:R|R|RW|W, f:CF=m|PF=m|ZF=m|OF=0, u:C0=m|C1=0|C2=m|C3=m + + +# 0xDC +FADD ST(0),Mfq X87STATUS [0xDC /0:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FMUL ST(0),Mfq X87STATUS [0xDC /1:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FCOM ST(0),Mfq X87STATUS [0xDC /2:mem] s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=0|C2=m|C3=m +FCOMP ST(0),Mfq X87STATUS [0xDC /3:mem] s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=0|C2=m|C3=m +FSUB ST(0),Mfq X87STATUS [0xDC /4:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FSUBR ST(0),Mfq X87STATUS [0xDC /5:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FDIV ST(0),Mfq X87STATUS [0xDC /6:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FDIVR ST(0),Mfq X87STATUS [0xDC /7:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FADD ST(i),ST(0) X87STATUS [0xDC /0:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FMUL ST(i),ST(0) X87STATUS [0xDC /1:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FCOM ST(i),ST(0) X87STATUS [0xDC /2:reg] s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=0|C2=m|C3=m +FCOMP ST(i),ST(0) X87STATUS [0xDC /3:reg] s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=0|C2=m|C3=m +FSUBR ST(i),ST(0) X87STATUS [0xDC /4:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FSUB ST(i),ST(0) X87STATUS [0xDC /5:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FDIVR ST(i),ST(0) X87STATUS [0xDC /6:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FDIV ST(i),ST(0) X87STATUS [0xDC /7:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m + + +# 0xDD +FLD ST(0),Mfq X87STATUS [0xDD /0:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m +FISTTP Mq,ST(0) X87STATUS [0xDD /1:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=0 +FST Mfq,ST(0) X87STATUS [0xDD /2:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m +FSTP Mfq,ST(0) X87STATUS [0xDD /3:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m +FRSTOR Mfs X87CONTROL [0xDD /4:mem] s:X87, t:X87_ALU, w:R|W, u:C0=m|C1=m|C2=m|C3=m +FNSAVE Mfs X87CONTROL,X87TAG,X87STATUS [0xDD /6:mem] s:X87, t:X87_ALU, w:W|RW|RW|W, u:C0=0|C1=0|C2=0|C3=0 +FNSTSW Mw X87STATUS [0xDD /7:mem] s:X87, t:X87_ALU, w:W|W, u:C0=u|C1=u|C2=u|C3=u +FFREE ST(i) X87TAG [0xDD /0:reg] s:X87, t:X87_ALU, w:R|W, u:C0=u|C1=u|C2=u|C3=u +FXCH ST(0),ST(i) X87STATUS [0xDD /1:reg] s:X87, t:X87_ALU, w:W|R|W, u:C1=0 +FST ST(0),ST(i) X87STATUS [0xDD /2:reg] s:X87, t:X87_ALU, w:W|R|W, u:C1=m +FSTP ST(0),ST(i) X87STATUS [0xDD /3:reg] s:X87, t:X87_ALU, w:W|R|W, u:C1=m +FUCOM ST(0),ST(i) X87STATUS [0xDD /4:reg] s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=m|C2=m|C3=m +FUCOMP ST(0),ST(i) X87STATUS [0xDD /5:reg] s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=m|C2=m|C3=m + + +# 0xDE +FIADD ST(0),Mw X87STATUS [0xDE /0:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FIMUL ST(0),Mw X87STATUS [0xDE /1:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FICOM ST(0),Mw X87STATUS [0xDE /2:mem] s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=m|C2=m|C3=m +FICOMP ST(0),Mw X87STATUS [0xDE /3:mem] s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=m|C2=m|C3=m +FISUB ST(0),Mw X87STATUS [0xDE /4:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FISUBR ST(0),Mw X87STATUS [0xDE /5:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FIDIV ST(0),Mw X87STATUS [0xDE /6:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FIDIVR ST(0),Mw X87STATUS [0xDE /7:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m + +FCOMPP nil X87STATUS [0xDE /0xD9] s:X87, t:X87_ALU, w:W, u:C0=m|C1=0|C2=m|C3=m +FADDP ST(i),ST(0) X87STATUS [0xDE /0:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FMULP ST(i),ST(0) X87STATUS [0xDE /1:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FCOMP ST(0),ST(i) X87STATUS [0xDE /2:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C0=m|C1=0|C2=m|C3=m +FSUBRP ST(i),ST(0) X87STATUS [0xDE /4:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FSUBP ST(i),ST(0) X87STATUS [0xDE /5:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FDIVRP ST(i),ST(0) X87STATUS [0xDE /6:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m +FDIVP ST(i),ST(0) X87STATUS [0xDE /7:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m + + +# 0xDF +FILD ST(0),Mw X87STATUS [0xDF /0:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m +FISTTP Mw,ST(0) X87STATUS [0xDF /1:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=0 +FIST Mw,ST(0) X87STATUS [0xDF /2:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m +FISTP Mw,ST(0) X87STATUS [0xDF /3:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m +FBLD ST(0),Mfa X87STATUS [0xDF /4:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m +FILD ST(0),Mq X87STATUS [0xDF /5:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m +FBSTP Mfa,ST(0) X87STATUS [0xDF /6:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m +FISTP Mq,ST(0) X87STATUS [0xDF /7:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m + + +FFREEP ST(i) X87TAG [0xDF /0:reg] s:X87, t:X87_ALU, w:R|W +FXCH ST(0),ST(i) X87TAG [0xDF /1:reg] s:X87, t:X87_ALU, w:R|W|W, u:C1=0 +FSTP ST(i),ST(0) X87STATUS [0xDF /2:reg] s:X87, t:X87_ALU, w:R|W|W, u:C1=m +FSTP ST(i),ST(0) X87STATUS [0xDF /3:reg] s:X87, t:X87_ALU, w:R|W|W, u:C1=m +FNSTSW AX X87STATUS [0xDF /0xE0] s:X87, t:X87_ALU, w:W|W, u:C0=u|C1=u|C2=u|C3=u +FSTDW AX nil [0xDF /0xE1] s:X87, t:X87_ALU, w:W, u:C0=u|C1=u|C2=u|C3=u +FSTSG AX nil [0xDF /0xE2] s:X87, t:X87_ALU, w:W, u:C0=u|C1=u|C2=u|C3=u +FUCOMIP ST(0),ST(i) X87STATUS,Fv [0xDF /5:reg] s:X87, t:X87_ALU, w:R|R|W|W, f:CF=m|PF=m|ZF=m|OF=0, u:C0=m|C1=0|C2=m|C3=m +FCOMIP ST(0),ST(i) X87STATUS,Fv [0xDF /6:reg] s:X87, t:X87_ALU, w:R|R|W|W, f:CF=m|PF=m|ZF=m|OF=0, u:C0=m|C1=0|C2=m|C3=m +FRINEAR nil nil [0xDF /0xFC] s:X87, t:X87_ALU diff --git a/isagenerator/instructions/table_vex1.dat b/isagenerator/instructions/table_vex1.dat new file mode 100644 index 0000000..098f9c8 --- /dev/null +++ b/isagenerator/instructions/table_vex1.dat @@ -0,0 +1,306 @@ +# Mnemonic Explicit Operands Implicit Operands Encoding Fags, Prefixes, Set, Category, Class, RW map, Additional ops +#------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +# 0x00 - 0x0F + +# 0x10 - 0x1F +VMOVUPS Vx,Wx nil [vex m:1 p:0 l:x w:i 0x10 /r] s:AVX, t:DATAXFER, w:W|R, e:4 +VMOVUPD Vx,Wx nil [vex m:1 p:1 l:x w:i 0x10 /r] s:AVX, t:DATAXFER, w:W|R, e:4 +VMOVSS Vdq,Hdq,Uss nil [vex m:1 p:2 l:i w:i 0x10 /r:reg] s:AVX, t:DATAXFER, w:W|R|R, e:5 +VMOVSS Vdq,Md nil [vex m:1 p:2 l:i w:i 0x10 /r:mem] s:AVX, t:DATAXFER, w:W|R, e:5 +VMOVSD Vdq,Hdq,Usd nil [vex m:1 p:3 l:i w:i 0x10 /r:reg] s:AVX, t:DATAXFER, w:W|R|R, e:5 +VMOVSD Vdq,Mq nil [vex m:1 p:3 l:i w:i 0x10 /r:mem] s:AVX, t:DATAXFER, w:W|R, e:5 +VMOVUPS Wx,Vx nil [vex m:1 p:0 l:x w:i 0x11 /r] s:AVX, t:DATAXFER, w:W|R, e:4 +VMOVUPD Wx,Vx nil [vex m:1 p:1 l:x w:i 0x11 /r] s:AVX, t:DATAXFER, w:W|R, e:4 +VMOVSS Uss,Hss,Vss nil [vex m:1 p:2 l:i w:i 0x11 /r:reg] s:AVX, t:DATAXFER, w:W|R|R, e:5 +VMOVSS Md,Vss nil [vex m:1 p:2 l:i w:i 0x11 /r:mem] s:AVX, t:DATAXFER, w:W|R, e:5 +VMOVSD Usd,Hsd,Vsd nil [vex m:1 p:3 l:i w:i 0x11 /r:reg] s:AVX, t:DATAXFER, w:W|R|R, e:5 +VMOVSD Mq,Vsd nil [vex m:1 p:3 l:i w:i 0x11 /r:mem] s:AVX, t:DATAXFER, w:W|R|R, e:5 +VMOVLPS Vdq,Hdq,Mq nil [vex m:1 p:0 l:0 w:i 0x12 /r:mem] s:AVX, t:DATAXFER, w:W|R|R, e:5 +VMOVHLPS Vdq,Hdq,Udq nil [vex m:1 p:0 l:0 w:i 0x12 /r:reg] s:AVX, t:AVX, w:W|R|R, e:7 +VMOVLPD Vdq,Hdq,Mq nil [vex m:1 p:1 l:0 w:i 0x12 /r:mem] s:AVX, t:DATAXFER, w:W|R|R, e:5 +VMOVSLDUP Vx,Wx nil [vex m:1 p:2 l:x w:i 0x12 /r] s:AVX, t:AVX, w:W|R, e:4 +VMOVDDUP Vdq,Wq nil [vex m:1 p:3 l:0 w:i 0x12 /r] s:AVX, t:DATAXFER, w:W|R, e:5 +VMOVDDUP Vqq,Wqq nil [vex m:1 p:3 l:1 w:i 0x12 /r] s:AVX, t:DATAXFER, w:W|R, e:5 +VMOVLPS Mq,Vdq nil [vex m:1 p:0 l:0 w:i 0x13 /r:mem] s:AVX, t:DATAXFER, w:W|R, e:5 +VMOVLPD Mq,Vdq nil [vex m:1 p:1 l:0 w:i 0x13 /r:mem] s:AVX, t:DATAXFER, w:W|R, e:5 +VUNPCKLPS Vx,Hx,Wx nil [vex m:1 p:0 l:x w:i 0x14 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VUNPCKLPD Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x14 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VUNPCKHPS Vx,Hx,Wx nil [vex m:1 p:0 l:x w:i 0x15 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VUNPCKHPD Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x15 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VMOVHPS Vdq,Hdq,Mq nil [vex m:1 p:0 l:0 w:i 0x16 /r:mem] s:AVX, t:DATAXFER, w:W|R|R, e:5 +VMOVLHPS Vdq,Hdq,Udq nil [vex m:1 p:0 l:0 w:i 0x16 /r:reg] s:AVX, t:AVX, w:W|R|R, e:7 +VMOVHPD Vdq,Hdq,Mq nil [vex m:1 p:1 l:0 w:i 0x16 /r:mem] s:AVX, t:DATAXFER, w:W|R|R, e:5 +VMOVSHDUP Vx,Wx nil [vex m:1 p:2 l:x w:i 0x16 /r] s:AVX, t:AVX, w:W|R, e:4 +VMOVHPS Mq,Vdq nil [vex m:1 p:0 l:0 w:i 0x17 /r:mem] s:AVX, t:DATAXFER, w:W|R, e:5 +VMOVHPD Mq,Vdq nil [vex m:1 p:1 l:0 w:i 0x17 /r:mem] s:AVX, t:DATAXFER, w:W|R, e:5 + +# 0x20 - 0x2F +VMOVAPS Vx,Wx nil [vex m:1 p:0 l:x w:i 0x28 /r] s:AVX, t:DATAXFER, w:W|R, e:1 +VMOVAPD Vx,Wx nil [vex m:1 p:1 l:x w:i 0x28 /r] s:AVX, t:DATAXFER, w:W|R, e:1 +VMOVAPS Wx,Vx nil [vex m:1 p:0 l:x w:i 0x29 /r] s:AVX, t:DATAXFER, w:W|R, e:1 +VMOVAPD Wx,Vx nil [vex m:1 p:1 l:x w:i 0x29 /r] s:AVX, t:DATAXFER, w:W|R, e:1 +VCVTSI2SS Vss,Hss,Ey nil [vex m:1 p:2 l:i w:x 0x2A /r] s:AVX, t:CONVERT, w:W|R|R, e:3 +VCVTSI2SD Vsd,Hsd,Ey nil [vex m:1 p:3 l:i w:x 0x2A /r] s:AVX, t:CONVERT, w:W|R|R, e:3 +VMOVNTPS Mx,Vx nil [vex m:1 p:0 l:x w:i 0x2B /r:mem] s:AVX, t:AVX, w:W|R, e:1 +VMOVNTPD Mx,Vx nil [vex m:1 p:1 l:x w:i 0x2B /r:mem] s:AVX, t:AVX, w:W|R, e:1 +VCVTTSS2SI Gy,Wss nil [vex m:1 p:2 l:i w:x 0x2C /r] s:AVX, t:CONVERT, w:W|R, e:3 +VCVTTSD2SI Gy,Wsd nil [vex m:1 p:3 l:i w:x 0x2C /r] s:AVX, t:CONVERT, w:W|R, e:3 +VCVTSS2SI Gy,Wss nil [vex m:1 p:2 l:i w:x 0x2D /r] s:AVX, t:CONVERT, w:W|R, e:3 +VCVTSD2SI Gy,Wsd nil [vex m:1 p:3 l:i w:x 0x2D /r] s:AVX, t:CONVERT, w:W|R, e:3 +VUCOMISS Vss,Wss Fv [vex m:1 p:0 l:i w:i 0x2E /r] s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3 +VUCOMISD Vsd,Wsd Fv [vex m:1 p:1 l:i w:i 0x2E /r] s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3 +VCOMISS Vss,Wss Fv [vex m:1 p:0 l:i w:i 0x2F /r] s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3 +VCOMISD Vsd,Wsd Fv [vex m:1 p:1 l:i w:i 0x2F /r] s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3 + +# 0x30 - 0x3F + +# 0x40 - 0x4F +# Note: ALL these instructions will zero-extend the result into the destination, up to the max length of the mask reg. +KANDW rKw,vKw,mKw nil [vex m:1 p:0 l:1 w:0 0x41 /r:reg] s:AVX512F, t:KMASK, c:KAND, w:W|R|R, e:K20 +KANDB rKb,vKb,mKb nil [vex m:1 p:1 l:1 w:0 0x41 /r:reg] s:AVX512DQ, t:KMASK, c:KAND, w:W|R|R, e:K20 +KANDQ rKq,vKq,mKq nil [vex m:1 p:0 l:1 w:1 0x41 /r:reg] s:AVX512BW, t:KMASK, c:KAND, w:W|R|R, e:K20 +KANDD rKd,vKd,mKd nil [vex m:1 p:1 l:1 w:1 0x41 /r:reg] s:AVX512BW, t:KMASK, c:KAND, w:W|R|R, e:K20 +KANDNW rKw,vKw,mKw nil [vex m:1 p:0 l:1 w:0 0x42 /r:reg] s:AVX512F, t:KMASK, c:KANDN, w:W|R|R, e:K20 +KANDNB rKb,vKb,mKb nil [vex m:1 p:1 l:1 w:0 0x42 /r:reg] s:AVX512DQ, t:KMASK, c:KANDN, w:W|R|R, e:K20 +KANDNQ rKq,vKq,mKq nil [vex m:1 p:0 l:1 w:1 0x42 /r:reg] s:AVX512BW, t:KMASK, c:KANDN, w:W|R|R, e:K20 +KANDND rKd,vKd,mKd nil [vex m:1 p:1 l:1 w:1 0x42 /r:reg] s:AVX512BW, t:KMASK, c:KANDN, w:W|R|R, e:K20 +KORW rKw,vKw,mKw nil [vex m:1 p:0 l:1 w:0 0x45 /r:reg] s:AVX512F, t:KMASK, c:KOR, w:W|R|R, e:K20 +KORB rKb,vKb,mKb nil [vex m:1 p:1 l:1 w:0 0x45 /r:reg] s:AVX512DQ, t:KMASK, c:KOR, w:W|R|R, e:K20 +KORQ rKq,vKq,mKq nil [vex m:1 p:0 l:1 w:1 0x45 /r:reg] s:AVX512BW, t:KMASK, c:KOR, w:W|R|R, e:K20 +KORD rKd,vKd,mKd nil [vex m:1 p:1 l:1 w:1 0x45 /r:reg] s:AVX512BW, t:KMASK, c:KOR, w:W|R|R, e:K20 +KXNORW rKw,vKw,mKw nil [vex m:1 p:0 l:1 w:0 0x46 /r:reg] s:AVX512F, t:KMASK, c:KXNOR, w:W|R|R, e:K20 +KXNORB rKb,vKb,mKb nil [vex m:1 p:1 l:1 w:0 0x46 /r:reg] s:AVX512DQ, t:KMASK, c:KXNOR, w:W|R|R, e:K20 +KXNORQ rKq,vKq,mKq nil [vex m:1 p:0 l:1 w:1 0x46 /r:reg] s:AVX512BW, t:KMASK, c:KXNOR, w:W|R|R, e:K20 +KXNORD rKd,vKd,mKd nil [vex m:1 p:1 l:1 w:1 0x46 /r:reg] s:AVX512BW, t:KMASK, c:KXNOR, w:W|R|R, e:K20 +KXORW rKw,vKw,mKw nil [vex m:1 p:0 l:1 w:0 0x47 /r:reg] s:AVX512F, t:KMASK, c:KXOR, w:W|R|R, e:K20 +KXORB rKb,vKb,mKb nil [vex m:1 p:1 l:1 w:0 0x47 /r:reg] s:AVX512DQ, t:KMASK, c:KXOR, w:W|R|R, e:K20 +KXORQ rKq,vKq,mKq nil [vex m:1 p:0 l:1 w:1 0x47 /r:reg] s:AVX512BW, t:KMASK, c:KXOR, w:W|R|R, e:K20 +KXORD rKd,vKd,mKd nil [vex m:1 p:1 l:1 w:1 0x47 /r:reg] s:AVX512BW, t:KMASK, c:KXOR, w:W|R|R, e:K20 +KADDW rKw,vKw,mKw nil [vex m:1 p:0 l:1 w:0 0x4A /r:reg] s:AVX512DQ, t:KMASK, c:KADD, w:W|R|R, e:K20 +KADDB rKb,vKb,mKb nil [vex m:1 p:1 l:1 w:0 0x4A /r:reg] s:AVX512DQ, t:KMASK, c:KADD, w:W|R|R, e:K20 +KADDQ rKq,vKq,mKq nil [vex m:1 p:0 l:1 w:1 0x4A /r:reg] s:AVX512BW, t:KMASK, c:KADD, w:W|R|R, e:K20 +KADDD rKd,vKd,mKd nil [vex m:1 p:1 l:1 w:1 0x4A /r:reg] s:AVX512BW, t:KMASK, c:KADD, w:W|R|R, e:K20 +KMOVW rKw,Mw nil [vex m:1 p:0 l:0 w:0 0x90 /r:mem] s:AVX512F, t:KMASK, c:KMOV, w:W|R, e:K21 +KMOVB rKb,Mb nil [vex m:1 p:1 l:0 w:0 0x90 /r:mem] s:AVX512DQ, t:KMASK, c:KMOV, w:W|R, e:K21 +KMOVQ rKq,Mq nil [vex m:1 p:0 l:0 w:1 0x90 /r:mem] s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K21 +KMOVD rKd,Md nil [vex m:1 p:1 l:0 w:1 0x90 /r:mem] s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K21 +KMOVW rKw,mKw nil [vex m:1 p:0 l:0 w:0 0x90 /r:reg] s:AVX512F, t:KMASK, c:KMOV, w:W|R, e:K20 +KMOVB rKb,mKb nil [vex m:1 p:1 l:0 w:0 0x90 /r:reg] s:AVX512DQ, t:KMASK, c:KMOV, w:W|R, e:K20 +KMOVQ rKq,mKq nil [vex m:1 p:0 l:0 w:1 0x90 /r:reg] s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K20 +KMOVD rKd,mKd nil [vex m:1 p:1 l:0 w:1 0x90 /r:reg] s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K20 +KMOVW Mw,rKw nil [vex m:1 p:0 l:0 w:0 0x91 /r:mem] s:AVX512F, t:KMASK, c:KMOV, w:W|R, e:K21 +KMOVB Mb,rKb nil [vex m:1 p:1 l:0 w:0 0x91 /r:mem] s:AVX512DQ, t:KMASK, c:KMOV, w:W|R, e:K21 +KMOVQ Mq,rKq nil [vex m:1 p:0 l:0 w:1 0x91 /r:mem] s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K21 +KMOVD Md,rKd nil [vex m:1 p:1 l:0 w:1 0x91 /r:mem] s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K21 +KMOVW rKw,Ry nil [vex m:1 p:0 l:0 w:0 0x92 /r:reg] s:AVX512F, t:KMASK, c:KMOV, w:W|R, e:K20 +KMOVB rKb,Ry nil [vex m:1 p:1 l:0 w:0 0x92 /r:reg] s:AVX512DQ, t:KMASK, c:KMOV, w:W|R, e:K20 +KMOVQ rKq,Ry nil [vex m:1 p:3 l:0 w:1 0x92 /r:reg] s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K20 +KMOVD rKd,Ry nil [vex m:1 p:3 l:0 w:0 0x92 /r:reg] s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K20 +KMOVW Gy,mKw nil [vex m:1 p:0 l:0 w:0 0x93 /r:reg] s:AVX512F, t:KMASK, c:KMOV, w:W|R, e:K20 +KMOVB Gy,mKb nil [vex m:1 p:1 l:0 w:0 0x93 /r:reg] s:AVX512DQ, t:KMASK, c:KMOV, w:W|R, e:K20 +KMOVQ Gy,mKq nil [vex m:1 p:3 l:0 w:1 0x93 /r:reg] s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K20 +KMOVD Gy,mKd nil [vex m:1 p:3 l:0 w:0 0x93 /r:reg] s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K20 +KMERGE2L1H rKw,mKw nil [vex m:1 p:0 l:0 w:0 0x48 /r:reg] s:UNKNOWN, t:UNKNOWN, c:KMERGE2L1H, w:W|R, e:K20 +KMERGE2L1L rKw,mKw nil [vex m:1 p:0 l:0 w:0 0x49 /r:reg] s:UNKNOWN, t:UNKNOWN, c:KMERGE2L1L, w:W|R, e:K20 +KUNPCKBW rKw,vKb,mKb nil [vex m:1 p:1 l:1 w:0 0x4B /r:reg] s:AVX512F, t:KMASK, c:KUNPCKBW, w:W|R|R, e:K20 +KUNPCKWD rKd,vKw,mKw nil [vex m:1 p:0 l:1 w:0 0x4B /r:reg] s:AVX512BW, t:KMASK, c:KUNPCKWD, w:W|R|R, e:K20 +KUNPCKDQ rKq,vKd,mKd nil [vex m:1 p:0 l:1 w:1 0x4B /r:reg] s:AVX512BW, t:KMASK, c:KUNPCKDQ, w:W|R|R, e:K20 +KNOTW rKw,mKw nil [vex m:1 p:0 l:0 w:0 0x44 /r:reg] s:AVX512F, t:KMASK, c:KNOT, w:W|R, e:K20 +KNOTB rKb,mKb nil [vex m:1 p:1 l:0 w:0 0x44 /r:reg] s:AVX512DQ, t:KMASK, c:KNOT, w:W|R, e:K20 +KNOTQ rKq,mKq nil [vex m:1 p:0 l:0 w:1 0x44 /r:reg] s:AVX512BW, t:KMASK, c:KNOT, w:W|R, e:K20 +KNOTD rKd,mKd nil [vex m:1 p:1 l:0 w:1 0x44 /r:reg] s:AVX512BW, t:KMASK, c:KNOT, w:W|R, e:K20 +KORTESTW rKw,mKw Fv [vex m:1 p:0 l:0 w:0 0x98 /r:reg] s:AVX512F, t:KMASK, c:KORTEST, w:R|R|W, f:KORTEST, e:K20 +KORTESTB rKb,mKb Fv [vex m:1 p:1 l:0 w:0 0x98 /r:reg] s:AVX512DQ, t:KMASK, c:KORTEST, w:R|R|W, f:KORTEST, e:K20 +KORTESTQ rKq,mKq Fv [vex m:1 p:0 l:0 w:1 0x98 /r:reg] s:AVX512BW, t:KMASK, c:KORTEST, w:R|R|W, f:KORTEST, e:K20 +KORTESTD rKd,mKd Fv [vex m:1 p:1 l:0 w:1 0x98 /r:reg] s:AVX512BW, t:KMASK, c:KORTEST, w:R|R|W, f:KORTEST, e:K20 +KTESTW rKw,mKw nil [vex m:1 p:0 l:0 w:0 0x99 /r:reg] s:AVX512DQ, t:KMASK, c:KTEST, w:W|R, e:K20 +KTESTB rKb,mKb nil [vex m:1 p:1 l:0 w:0 0x99 /r:reg] s:AVX512DQ, t:KMASK, c:KTEST, w:W|R, e:K20 +KTESTQ rKq,mKq nil [vex m:1 p:0 l:0 w:1 0x99 /r:reg] s:AVX512BW, t:KMASK, c:KTEST, w:W|R, e:K20 +KTESTD rKd,mKd nil [vex m:1 p:1 l:0 w:1 0x99 /r:reg] s:AVX512BW, t:KMASK, c:KTEST, w:W|R, e:K20 + +# 0x50 - 0x5F +VMOVMSKPS Gy,Ux nil [vex m:1 p:0 l:x w:i 0x50 /r:reg] s:AVX, t:DATAXFER, w:W|R, e:7 +VMOVMSKPD Gy,Ux nil [vex m:1 p:1 l:x w:i 0x50 /r:reg] s:AVX, t:DATAXFER, w:W|R, e:7 +VSQRTPS Vx,Wx nil [vex m:1 p:0 l:x w:i 0x51 /r] s:AVX, t:AVX, w:W|R, e:2 +VSQRTPD Vx,Wx nil [vex m:1 p:1 l:x w:i 0x51 /r] s:AVX, t:AVX, w:W|R, e:2 +VSQRTSS Vss,Hss,Wss nil [vex m:1 p:2 l:i w:i 0x51 /r] s:AVX, t:AVX, w:W|R|R, e:3 +VSQRTSD Vsd,Hsd,Wsd nil [vex m:1 p:3 l:i w:i 0x51 /r] s:AVX, t:AVX, w:W|R|R, e:3 +VRSQRTPS Vx,Wx nil [vex m:1 p:0 l:x w:i 0x52 /r] s:AVX, t:AVX, w:W|R, e:4 +VRSQRTSS Vss,Hss,Wss nil [vex m:1 p:2 l:i w:i 0x52 /r] s:AVX, t:AVX, w:W|R|R, e:5 +VRCPPS Vps,Wps nil [vex m:1 p:0 l:x w:i 0x53 /r] s:AVX, t:AVX, w:W|R, e:4 +VRCPSS Vss,Hss,Wss nil [vex m:1 p:2 l:i w:i 0x53 /r] s:AVX, t:AVX, w:W|R|R, e:5 +VANDPS Vps,Hps,Wps nil [vex m:1 p:0 l:x w:i 0x54 /r] s:AVX, t:LOGICAL_FP, w:W|R|R, e:4 +VANDPD Vpd,Hpd,Wpd nil [vex m:1 p:1 l:x w:i 0x54 /r] s:AVX, t:LOGICAL_FP, w:W|R|R, e:4 +VANDNPS Vps,Hps,Wps nil [vex m:1 p:0 l:x w:i 0x55 /r] s:AVX, t:LOGICAL_FP, w:W|R|R, e:4 +VANDNPD Vpd,Hpd,Wpd nil [vex m:1 p:1 l:x w:i 0x55 /r] s:AVX, t:LOGICAL_FP, w:W|R|R, e:4 +VORPS Vps,Hps,Wps nil [vex m:1 p:0 l:x w:i 0x56 /r] s:AVX, t:LOGICAL_FP, w:W|R|R, e:4 +VORPD Vpd,Hpd,Wpd nil [vex m:1 p:1 l:x w:i 0x56 /r] s:AVX, t:LOGICAL_FP, w:W|R|R, e:4 +VXORPS Vps,Hps,Wps nil [vex m:1 p:0 l:x w:i 0x57 /r] s:AVX, t:LOGICAL_FP, w:W|R|R, e:4 +VXORPD Vpd,Hpd,Wpd nil [vex m:1 p:1 l:x w:i 0x57 /r] s:AVX, t:LOGICAL_FP, w:W|R|R, e:4 +VADDPS Vps,Hps,Wps nil [vex m:1 p:0 l:x w:i 0x58 /r] s:AVX, t:AVX, w:W|R|R, e:2 +VADDPD Vpd,Hpd,Wpd nil [vex m:1 p:1 l:x w:i 0x58 /r] s:AVX, t:AVX, w:W|R|R, e:2 +VADDSS Vss,Hss,Wss nil [vex m:1 p:2 l:i w:i 0x58 /r] s:AVX, t:AVX, w:W|R|R, e:2 +VADDSD Vsd,Hsd,Wsd nil [vex m:1 p:3 l:i w:i 0x58 /r] s:AVX, t:AVX, w:W|R|R, e:2 +VMULPS Vps,Hps,Wps nil [vex m:1 p:0 l:x w:i 0x59 /r] s:AVX, t:AVX, w:W|R|R, e:2 +VMULPD Vpd,Hpd,Wpd nil [vex m:1 p:1 l:x w:i 0x59 /r] s:AVX, t:AVX, w:W|R|R, e:2 +VMULSS Vss,Hss,Wss nil [vex m:1 p:2 l:i w:i 0x59 /r] s:AVX, t:AVX, w:W|R|R, e:2 +VMULSD Vsd,Hsd,Wsd nil [vex m:1 p:3 l:i w:i 0x59 /r] s:AVX, t:AVX, w:W|R|R, e:2 +VCVTPS2PD Vpd,Wq nil [vex m:1 p:0 l:0 w:i 0x5A /r] s:AVX, t:CONVERT, w:W|R, e:2 +VCVTPS2PD Vqq,Wdq nil [vex m:1 p:0 l:1 w:i 0x5A /r] s:AVX, t:CONVERT, w:W|R, e:2 +VCVTPD2PS Vdq,Wdq nil [vex m:1 p:1 l:0 w:i 0x5A /r] s:AVX, t:CONVERT, w:W|R, e:2 +VCVTPD2PS Vdq,Wqq nil [vex m:1 p:1 l:1 w:i 0x5A /r] s:AVX, t:CONVERT, w:W|R, e:2 +VCVTSS2SD Vsd,Hx,Wss nil [vex m:1 p:2 l:i w:i 0x5A /r] s:AVX, t:CONVERT, w:W|R|R, e:3 +VCVTSD2SS Vss,Hx,Wsd nil [vex m:1 p:3 l:i w:i 0x5A /r] s:AVX, t:CONVERT, w:W|R|R, e:3 +VCVTDQ2PS Vps,Wps nil [vex m:1 p:0 l:x w:i 0x5B /r] s:AVX, t:CONVERT, w:W|R, e:2 +VCVTPS2DQ Vps,Wps nil [vex m:1 p:1 l:x w:i 0x5B /r] s:AVX, t:CONVERT, w:W|R, e:2 +VCVTTPS2DQ Vps,Wps nil [vex m:1 p:2 l:x w:i 0x5B /r] s:AVX, t:CONVERT, w:W|R, e:2 +VSUBPS Vps,Hps,Wps nil [vex m:1 p:0 l:x w:i 0x5C /r] s:AVX, t:AVX, w:W|R|R, e:2 +VSUBPD Vpd,Hpd,Wpd nil [vex m:1 p:1 l:x w:i 0x5C /r] s:AVX, t:AVX, w:W|R|R, e:2 +VSUBSS Vss,Hss,Wss nil [vex m:1 p:2 l:i w:i 0x5C /r] s:AVX, t:AVX, w:W|R|R, e:2 +VSUBSD Vsd,Hsd,Wsd nil [vex m:1 p:3 l:i w:i 0x5C /r] s:AVX, t:AVX, w:W|R|R, e:2 +VMINPS Vps,Hps,Wps nil [vex m:1 p:0 l:x w:i 0x5D /r] s:AVX, t:AVX, w:W|R|R, e:2 +VMINPD Vpd,Hpd,Wpd nil [vex m:1 p:1 l:x w:i 0x5D /r] s:AVX, t:AVX, w:W|R|R, e:2 +VMINSS Vss,Hss,Wss nil [vex m:1 p:2 l:i w:i 0x5D /r] s:AVX, t:AVX, w:W|R|R, e:2 +VMINSD Vsd,Hsd,Wsd nil [vex m:1 p:3 l:i w:i 0x5D /r] s:AVX, t:AVX, w:W|R|R, e:2 +VDIVPS Vps,Hps,Wps nil [vex m:1 p:0 l:x w:i 0x5E /r] s:AVX, t:AVX, w:W|R|R, e:2 +VDIVPD Vpd,Hpd,Wpd nil [vex m:1 p:1 l:x w:i 0x5E /r] s:AVX, t:AVX, w:W|R|R, e:2 +VDIVSS Vss,Hss,Wss nil [vex m:1 p:2 l:i w:i 0x5E /r] s:AVX, t:AVX, w:W|R|R, e:2 +VDIVSD Vsd,Hsd,Wsd nil [vex m:1 p:3 l:i w:i 0x5E /r] s:AVX, t:AVX, w:W|R|R, e:2 +VMAXPS Vps,Hps,Wps nil [vex m:1 p:0 l:x w:i 0x5F /r] s:AVX, t:AVX, w:W|R|R, e:2 +VMAXPD Vpd,Hpd,Wpd nil [vex m:1 p:1 l:x w:i 0x5F /r] s:AVX, t:AVX, w:W|R|R, e:2 +VMAXSS Vss,Hss,Wss nil [vex m:1 p:2 l:i w:i 0x5F /r] s:AVX, t:AVX, w:W|R|R, e:2 +VMAXSD Vsd,Hsd,Wsd nil [vex m:1 p:3 l:i w:i 0x5F /r] s:AVX, t:AVX, w:W|R|R, e:2 + + +# 0x60 - 0x6F +VPUNPCKLBW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x60 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPUNPCKLWD Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x61 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPUNPCKLDQ Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x62 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPACKSSWB Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x63 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPCMPGTB Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x64 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPCMPGTW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x65 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPCMPGTD Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x66 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPACKUSWB Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x67 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPUNPCKHBW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x68 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPUNPCKHWD Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x69 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPUNPCKHDQ Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x6A /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPACKSSDW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x6B /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPUNPCKLQDQ Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x6C /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPUNPCKHQDQ Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x6D /r] s:AVX, t:AVX, w:W|R|R, e:4 +VMOVD Vdq,Ey nil [vex m:1 p:1 l:0 w:0 0x6E /r] s:AVX, t:DATAXFER, w:W|R, e:5 +VMOVQ Vdq,Ey nil [vex m:1 p:1 l:0 w:1 0x6E /r] s:AVX, t:DATAXFER, w:W|R, e:5 +VMOVDQA Vx,Wx nil [vex m:1 p:1 l:x w:i 0x6F /r] s:AVX, t:DATAXFER, w:W|R, e:1 +VMOVDQU Vx,Wx nil [vex m:1 p:2 l:x w:i 0x6F /r] s:AVX, t:DATAXFER, w:W|R, e:4 + + + +# 0x70 - 0x7F +VPSHUFD Vx,Wx,Ib nil [vex m:1 p:1 l:x w:i 0x70 /r ib] s:AVX, t:AVX, w:W|R|R, e:4 +VPSHUFHW Vx,Wx,Ib nil [vex m:1 p:2 l:x w:i 0x70 /r ib] s:AVX, t:AVX, w:W|R|R, e:4 +VPSHUFLW Vx,Wx,Ib nil [vex m:1 p:3 l:x w:i 0x70 /r ib] s:AVX, t:AVX, w:W|R|R, e:4 +VPCMPEQB Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x74 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPCMPEQW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x75 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPCMPEQD Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x76 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VZEROUPPER nil BANK [vex m:1 p:0 l:0 0x77] s:AVX, t:AVX, w:W, e:8 +VZEROALL nil BANK [vex m:1 p:0 l:1 0x77] s:AVX, t:AVX, w:W, e:8 +VHADDPD Vpd,Hpd,Wpd nil [vex m:1 p:1 l:x w:i 0x7C /r] s:AVX, t:AVX, w:W|R|R, e:2 +VHADDPS Vps,Hps,Wps nil [vex m:1 p:3 l:x w:i 0x7C /r] s:AVX, t:AVX, w:W|R|R, e:2 +VHSUBPD Vpd,Hpd,Wpd nil [vex m:1 p:1 l:x w:i 0x7D /r] s:AVX, t:AVX, w:W|R|R, e:2 +VHSUBPS Vps,Hps,Wps nil [vex m:1 p:3 l:x w:i 0x7D /r] s:AVX, t:AVX, w:W|R|R, e:2 +VMOVD Ey,Vd nil [vex m:1 p:1 l:0 w:0 0x7E /r] s:AVX, t:DATAXFER, w:W|R, e:5 +VMOVQ Ey,Vq nil [vex m:1 p:1 l:0 w:1 0x7E /r] s:AVX, t:DATAXFER, w:W|R, e:5 +VMOVQ Vdq,Wq nil [vex m:1 p:2 l:0 w:i 0x7E /r] s:AVX, t:DATAXFER, w:W|R, e:5 +VMOVDQA Wx,Vx nil [vex m:1 p:1 l:x w:i 0x7F /r] s:AVX, t:DATAXFER, w:W|R, e:1 +VMOVDQU Wx,Vx nil [vex m:1 p:2 l:x w:i 0x7F /r] s:AVX, t:DATAXFER, w:W|R, e:4 +VPSRLW Hx,Ux,Ib nil [vex m:1 p:1 l:x w:i 0x71 /2:reg ib] s:AVX, t:AVX, w:W|R|R, e:7 +VPSRAW Hx,Ux,Ib nil [vex m:1 p:1 l:x w:i 0x71 /4:reg ib] s:AVX, t:AVX, w:W|R|R, e:7 +VPSLLW Hx,Ux,Ib nil [vex m:1 p:1 l:x w:i 0x71 /6:reg ib] s:AVX, t:AVX, w:W|R|R, e:7 +VPSRLD Hx,Ux,Ib nil [vex m:1 p:1 l:x w:i 0x72 /2:reg ib] s:AVX, t:AVX, w:W|R|R, e:7 +VPSRAD Hx,Ux,Ib nil [vex m:1 p:1 l:x w:i 0x72 /4:reg ib] s:AVX, t:AVX, w:W|R|R, e:7 +VPSLLD Hx,Ux,Ib nil [vex m:1 p:1 l:x w:i 0x72 /6:reg ib] s:AVX, t:AVX, w:W|R|R, e:7 +VPSRLQ Hx,Ux,Ib nil [vex m:1 p:1 l:x w:i 0x73 /2:reg ib] s:AVX, t:AVX, w:W|R|R, e:7 +VPSRLDQ Hx,Ux,Ib nil [vex m:1 p:1 l:x w:i 0x73 /3:reg ib] s:AVX, t:AVX, w:W|R|R, e:7 +VPSLLQ Hx,Ux,Ib nil [vex m:1 p:1 l:x w:i 0x73 /6:reg ib] s:AVX, t:AVX, w:W|R|R, e:7 +VPSLLDQ Hx,Ux,Ib nil [vex m:1 p:1 l:x w:i 0x73 /7:reg ib] s:AVX, t:AVX, w:W|R|R, e:7 + +# 0x80 - 0x8F + +# 0x90 - 0x9F + +# 0xA0 - 0xAF +VLDMXCSR Md MXCSR [vex m:1 p:0 0xAE /2:mem] s:AVX, t:AVX, w:R|W, e:5 +VSTMXCSR Md MXCSR [vex m:1 p:0 0xAE /3:mem] s:AVX, t:AVX, w:W|R, e:5 +SPFLT Ry nil [vex m:1 p:3 0xAE /6:reg] s:UNKNOWN, t:UNKNOWN, w:R +DELAY Ry nil [vex m:1 p:2 0xAE /6:reg] s:UNKNOWN, t:UNKNOWN, w:R +CLEVICT0 M? nil [vex m:1 p:3 0xAE /7:mem] s:UNKNOWN, t:UNKNOWN, w:N +CLEVICT1 M? nil [vex m:1 p:2 0xAE /7:mem] s:UNKNOWN, t:UNKNOWN, w:N + +# 0xB0 - 0xBF + +# 0xC0 - 0xCF +VCMPSS Vss,Hss,Wss,Ib nil [vex m:1 p:0 l:i w:i 0xC2 /r ib] s:AVX, t:AVX, w:W|R|R|R, e:3 +VCMPPD Vpd,Hpd,Wpd,Ib nil [vex m:1 p:1 l:x w:i 0xC2 /r ib] s:AVX, t:AVX, w:W|R|R|R, e:3 +VCMPSS Vss,Hss,Wss,Ib nil [vex m:1 p:2 l:i w:i 0xC2 /r ib] s:AVX, t:AVX, w:W|R|R|R, e:3 +VCMPSD Vsd,Hsd,Wsd,Ib nil [vex m:1 p:3 l:i w:i 0xC2 /r ib] s:AVX, t:AVX, w:W|R|R|R, e:3 +VPINSRW Vdq,Hdq,Mw,Ib nil [vex m:1 p:1 l:0 w:0 0xC4 /r:mem ib] s:AVX, t:AVX, w:W|R|R|R, e:5 +VPINSRW Vdq,Hdq,Ry,Ib nil [vex m:1 p:1 l:0 w:0 0xC4 /r:reg ib] s:AVX, t:AVX, w:W|R|R|R, e:5 +VPEXTRW Gy,Udq,Ib nil [vex m:1 p:1 l:0 w:0 0xC5 /r:reg ib] s:AVX, t:AVX, w:W|R|R, e:5 +VSHUFPS Vps,Hps,Wps,Ib nil [vex m:1 p:0 l:x w:i 0xC6 /r ib] s:AVX, t:AVX, w:W|R|R|R, e:4 +VSHUFPD Vpd,Hpd,Wpd,Ib nil [vex m:1 p:1 l:x w:i 0xC6 /r ib] s:AVX, t:AVX, w:W|R|R|R, e:4 + +# 0xD0 - 0xDF +VADDSUBPD Vpd,Hpd,Wpd nil [vex m:1 p:1 l:x w:i 0xD0 /r] s:AVX, t:AVX, w:W|R|R, e:2 +VADDSUBPS Vps,Hps,Wps nil [vex m:1 p:3 l:x w:i 0xD0 /r] s:AVX, t:AVX, w:W|R|R, e:2 +VPSRLW Vx,Hx,Wdq nil [vex m:1 p:1 l:x w:i 0xD1 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPSRLD Vx,Hx,Wdq nil [vex m:1 p:1 l:x w:i 0xD2 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPSRLQ Vx,Hx,Wdq nil [vex m:1 p:1 l:x w:i 0xD3 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPADDQ Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xD4 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPMULLW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xD5 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VMOVQ Wq,Vdq nil [vex m:1 p:1 l:0 w:i 0xD6 /r] s:AVX, t:DATAXFER, w:W|R, e:5 +VPMOVMSKB Gy,Ux nil [vex m:1 p:1 l:x w:i 0xD7 /r:reg] s:AVX, t:DATAXFER, w:W|R, e:7 +VPSUBUSB Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xD8 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPSUBUSW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xD9 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPMINUB Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xDA /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPAND Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xDB /r] s:AVX, t:LOGICAL, w:W|R|R, e:4 +VPADDUSB Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xDC /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPADDUSW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xDD /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPMAXUB Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xDE /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPANDN Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xDF /r] s:AVX, t:LOGICAL, w:W|R|R, e:4 + +# 0xE0 - 0xEF +VPAVGB Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xE0 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPSRAW Vx,Hx,Wdq nil [vex m:1 p:1 l:x w:i 0xE1 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPSRAD Vx,Hx,Wdq nil [vex m:1 p:1 l:x w:i 0xE2 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPAVGW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xE3 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPMULHUW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xE4 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPMULHW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xE5 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VCVTTPD2DQ Vdq,Wx nil [vex m:1 p:1 l:x w:i 0xE6 /r] s:AVX, t:CONVERT, w:W|R, e:2 +VCVTDQ2PD Vdq,Wq nil [vex m:1 p:2 l:0 w:i 0xE6 /r] s:AVX, t:CONVERT, w:W|R, e:5 +VCVTDQ2PD Vqq,Wdq nil [vex m:1 p:2 l:1 w:i 0xE6 /r] s:AVX, t:CONVERT, w:W|R, e:5 +VCVTPD2DQ Vdq,Wx nil [vex m:1 p:3 l:x w:i 0xE6 /r] s:AVX, t:CONVERT, w:W|R, e:2 +VMOVNTDQ Mx,Vx nil [vex m:1 p:1 l:x w:i 0xE7 /r:mem] s:AVX, t:AVX, w:W|R, e:1 +VPSUBSB Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xE8 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPSUBSW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xE9 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPMINSW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xEA /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPOR Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xEB /r] s:AVX, t:LOGICAL, w:W|R|R, e:4 +VPADDSB Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xEC /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPADDSW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xED /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPMAXSW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xEE /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPXOR Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xEF /r] s:AVX, t:LOGICAL, w:W|R|R, e:4 + +# 0xF0 - 0xFF +VLDDQU Vx,Mx nil [vex m:1 p:3 l:x w:i 0xF0 /r:mem] s:AVX, t:AVX, w:W|R, e:4 +VPSLLW Vx,Hx,Wdq nil [vex m:1 p:1 l:x w:i 0xF1 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPSLLD Vx,Hx,Wdq nil [vex m:1 p:1 l:x w:i 0xF2 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPSLLQ Vx,Hx,Wdq nil [vex m:1 p:1 l:x w:i 0xF3 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPMULUDQ Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xF4 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPMADDWD Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xF5 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPSADBW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xF6 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VMASKMOVDQU Vdq,Udq pDIdq [vex m:1 p:1 l:0 w:i 0xF7 /r:reg] s:AVX, t:AVX, w:R|R|W, e:4 +VPSUBB Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xF8 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPSUBW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xF9 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPSUBD Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xFA /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPSUBQ Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xFB /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPADDB Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xFC /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPADDW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xFD /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPADDD Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xFE /r] s:AVX, t:AVX, w:W|R|R, e:4 diff --git a/isagenerator/instructions/table_vex2.dat b/isagenerator/instructions/table_vex2.dat new file mode 100644 index 0000000..e0c09ed --- /dev/null +++ b/isagenerator/instructions/table_vex2.dat @@ -0,0 +1,212 @@ +# Mnemonic Explicit Operands Implicit Operands Encoding Fags, Prefixes, Set, Category, Class, RW map, Additional ops +#------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +# 0x00 - 0x0F +VPSHUFB Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x00 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPHADDW Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x01 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPHADDD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x02 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPHADDSW Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x03 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPMADDUBSW Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x04 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPHSUBW Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x05 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPHSUBD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x06 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPHSUBSW Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x07 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPSIGNB Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x08 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPSIGNW Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x09 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPSIGND Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x0A /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPMULHRSW Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x0B /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPERMILPS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x0C /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPERMILPD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x0D /r] s:AVX, t:AVX, w:W|R|R, e:4 +VTESTPS Vx,Wx Fv [vex m:2 p:1 l:x w:0 0x0E /r] s:AVX, t:LOGICAL_FP, w:R|R|W, f:VPTEST, e:4 +VTESTPD Vx,Wx Fv [vex m:2 p:1 l:x w:0 0x0F /r] s:AVX, t:LOGICAL_FP, w:R|R|W, f:VPTEST, e:4 + +# 0x10 - 0x1F +VCVTPH2PS Vdq,Wq nil [vex m:2 p:1 l:0 w:0 0x13 /r] s:F16C, t:CONVERT, w:W|R, e:11 +VCVTPH2PS Vqq,Wdq nil [vex m:2 p:1 l:1 w:0 0x13 /r] s:F16C, t:CONVERT, w:W|R, e:11 +VPERMPS Vqq,Hqq,Wqq nil [vex m:2 p:1 l:1 w:0 0x16 /r] s:AVX2, t:AVX2, w:W|R|R, e:4 +VPTEST Vx,Wx Fv [vex m:2 p:1 l:x w:i 0x17 /r] s:AVX, t:LOGICAL, w:R|R|W, f:VPTEST, e:4 +VBROADCASTSS Vx,Wss nil [vex m:2 p:1 l:x w:0 0x18 /r] s:AVX, t:BROADCAST, w:W|R, e:6 +VBROADCASTSD Vqq,Wsd nil [vex m:2 p:1 l:x w:0 0x19 /r] s:AVX, t:BROADCAST, w:W|R, e:6 +VBROADCASTF128 Vqq,Mdq nil [vex m:2 p:1 l:1 w:0 0x1A /r:mem] s:AVX, t:BROADCAST, w:W|R, e:6 +VPABSB Vx,Wx nil [vex m:2 p:1 l:x w:i 0x1C /r] s:AVX, t:AVX, w:W|R, e:4 +VPABSW Vx,Wx nil [vex m:2 p:1 l:x w:i 0x1D /r] s:AVX, t:AVX, w:W|R, e:4 +VPABSD Vx,Wx nil [vex m:2 p:1 l:x w:i 0x1E /r] s:AVX, t:AVX, w:W|R, e:4 + +# 0x20 - 0x2F +VPMOVSXBW Vdq,Wq nil [vex m:2 p:1 l:0 w:i 0x20 /r] s:AVX, t:AVX, w:W|R, e:5 +VPMOVSXBW Vqq,Wdq nil [vex m:2 p:1 l:1 w:i 0x20 /r] s:AVX2, t:AVX2, w:W|R, e:5 +VPMOVSXBD Vdq,Wd nil [vex m:2 p:1 l:0 w:i 0x21 /r] s:AVX, t:AVX, w:W|R, e:5 +VPMOVSXBD Vqq,Wq nil [vex m:2 p:1 l:1 w:i 0x21 /r] s:AVX2, t:AVX2, w:W|R, e:5 +VPMOVSXBQ Vdq,Ww nil [vex m:2 p:1 l:0 w:i 0x22 /r] s:AVX, t:AVX, w:W|R, e:5 +VPMOVSXBQ Vqq,Wd nil [vex m:2 p:1 l:1 w:i 0x22 /r] s:AVX2, t:AVX2, w:W|R, e:5 +VPMOVSXWD Vdq,Wq nil [vex m:2 p:1 l:0 w:i 0x23 /r] s:AVX, t:AVX, w:W|R, e:5 +VPMOVSXWD Vqq,Wdq nil [vex m:2 p:1 l:1 w:i 0x23 /r] s:AVX2, t:AVX2, w:W|R, e:5 +VPMOVSXWQ Vdq,Wd nil [vex m:2 p:1 l:0 w:i 0x24 /r] s:AVX, t:AVX, w:W|R, e:5 +VPMOVSXWQ Vqq,Wq nil [vex m:2 p:1 l:1 w:i 0x24 /r] s:AVX2, t:AVX2, w:W|R, e:5 +VPMOVSXDQ Vdq,Wq nil [vex m:2 p:1 l:0 w:i 0x25 /r] s:AVX, t:AVX, w:W|R, e:5 +VPMOVSXDQ Vqq,Wdq nil [vex m:2 p:1 l:1 w:i 0x25 /r] s:AVX2, t:AVX2, w:W|R, e:5 +VPMULDQ Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x28 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPCMPEQQ Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x29 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VMOVNTDQA Vx,Mx nil [vex m:2 p:1 l:x w:i 0x2A /r:mem] s:AVX, t:AVX, w:W|R, e:1 +VPACKUSDW Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x2B /r] s:AVX, t:AVX, w:W|R|R, e:4 +VMASKMOVPS Vx,Hx,Mx nil [vex m:2 p:1 l:x w:0 0x2C /r:mem] s:AVX, t:AVX, w:W|R|R, e:6 +VMASKMOVPD Vx,Hx,Mx nil [vex m:2 p:1 l:x w:0 0x2D /r:mem] s:AVX, t:AVX, w:W|R|R, e:6 +VMASKMOVPS Mx,Hx,Vx nil [vex m:2 p:1 l:x w:0 0x2E /r:mem] s:AVX, t:AVX, w:W|R|R, e:6 +VMASKMOVPD Mx,Hx,Vx nil [vex m:2 p:1 l:x w:0 0x2F /r:mem] s:AVX, t:AVX, w:W|R|R, e:6 + +# 0x30 - 0x3F +VPMOVZXBW Vdq,Wq nil [vex m:2 p:1 l:0 w:i 0x30 /r] s:AVX, t:AVX, w:W|R, e:5 +VPMOVZXBW Vqq,Wdq nil [vex m:2 p:1 l:1 w:i 0x30 /r] s:AVX2, t:AVX2, w:W|R, e:5 +VPMOVZXBD Vdq,Wd nil [vex m:2 p:1 l:0 w:i 0x31 /r] s:AVX, t:AVX, w:W|R, e:5 +VPMOVZXBD Vqq,Wq nil [vex m:2 p:1 l:1 w:i 0x31 /r] s:AVX2, t:AVX2, w:W|R, e:5 +VPMOVZXBQ Vdq,Ww nil [vex m:2 p:1 l:0 w:i 0x32 /r] s:AVX, t:AVX, w:W|R, e:5 +VPMOVZXBQ Vqq,Wd nil [vex m:2 p:1 l:1 w:i 0x32 /r] s:AVX2, t:AVX2, w:W|R, e:5 +VPMOVZXWD Vdq,Wq nil [vex m:2 p:1 l:0 w:i 0x33 /r] s:AVX, t:AVX, w:W|R, e:5 +VPMOVZXWD Vqq,Wdq nil [vex m:2 p:1 l:1 w:i 0x33 /r] s:AVX2, t:AVX2, w:W|R, e:5 +VPMOVZXWQ Vdq,Wd nil [vex m:2 p:1 l:0 w:i 0x34 /r] s:AVX, t:AVX, w:W|R, e:5 +VPMOVZXWQ Vqq,Wq nil [vex m:2 p:1 l:1 w:i 0x34 /r] s:AVX2, t:AVX2, w:W|R, e:5 +VPMOVZXDQ Vdq,Wq nil [vex m:2 p:1 l:0 w:i 0x35 /r] s:AVX, t:AVX, w:W|R, e:5 +VPMOVZXDQ Vqq,Wdq nil [vex m:2 p:1 l:1 w:i 0x35 /r] s:AVX2, t:AVX2, w:W|R, e:5 +VPERMD Vqq,Hqq,Wqq nil [vex m:2 p:1 l:1 w:0 0x36 /r] s:AVX2, t:AVX2, w:W|R|R, e:4 +VPCMPGTQ Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x37 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPMINSB Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x38 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPMINSD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x39 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPMINUW Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x3A /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPMINUD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x3B /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPMAXSB Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x3C /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPMAXSD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x3D /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPMAXUW Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x3E /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPMAXUD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x3F /r] s:AVX, t:AVX, w:W|R|R, e:4 + +# 0x40 - 0x4F +VPMULLD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x40 /r] s:AVX, t:AVX, w:W|R|R, e:4 +VPHMINPOSUW Vdq,Wdq nil [vex m:2 p:1 l:0 w:i 0x41 /r] s:AVX, t:AVX, w:W|R, e:4 +VPSRLVD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x45 /r] s:AVX2, t:AVX2, w:W|R|R, e:4 +VPSRLVQ Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0x45 /r] s:AVX2, t:AVX2, w:W|R|R, e:4 +VPSRAVD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x46 /r] s:AVX2, t:AVX2, w:W|R|R, e:4 +VPSLLVD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x47 /r] s:AVX2, t:AVX2, w:W|R|R, e:4 +VPSLLVQ Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0x47 /r] s:AVX2, t:AVX2, w:W|R|R, e:4 + +LDTILECFG Moq nil [vex m:2 p:0 l:0 w:0 0x49 /0:mem] s:AMXTILE, t:AMX, w:R, m:NOTSX|O64, e:AMX_E1 +STTILECFG Moq nil [vex m:2 p:1 l:0 w:0 0x49 /0:mem] s:AMXTILE, t:AMX, w:W, m:NOTSX|O64, e:AMX_E2 +TILELOADD rTt,Mt nil [vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem] s:AMXTILE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E3 +TILESTORED Mt,rTt nil [vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem] s:AMXTILE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E3 +TILELOADDT1 rTt,Mt nil [vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem] s:AMXTILE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E3 +TILERELEASE nil nil [vex m:2 p:0 l:0 w:0 0x49 /0xC0] s:AMXTILE, t:AMX, m:NOTSX|O64, e:AMX_E6 +TILEZERO rTt nil [vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0] s:AMXTILE, t:AMX, w:W, m:NOTSX|O64, e:AMX_E5 + +# 0x50 - 0x5F +VPBROADCASTD Vx,Wd nil [vex m:2 p:1 l:x w:0 0x58 /r] s:AVX2, t:BROADCAST, w:W|R, e:6 +VPBROADCASTQ Vx,Wq nil [vex m:2 p:1 l:x w:0 0x59 /r] s:AVX2, t:BROADCAST, w:W|R, e:6 +VBROADCASTI128 Vqq,Mdq nil [vex m:2 p:1 l:1 w:0 0x5A /r:mem] s:AVX2, t:BROADCAST, w:W|R, e:6 + +TDPBF16PS rTt,mTt,vTt nil [vex m:2 p:2 l:0 w:0 0x5C /r:reg] s:AMXBF16, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 +TDPBUUD rTt,mTt,vTt nil [vex m:2 p:0 l:0 w:0 0x5E /r:reg] s:AMXINT8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 +TDPBUSD rTt,mTt,vTt nil [vex m:2 p:1 l:0 w:0 0x5E /r:reg] s:AMXINT8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 +TDPBSUD rTt,mTt,vTt nil [vex m:2 p:2 l:0 w:0 0x5E /r:reg] s:AMXINT8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 +TDPBSSD rTt,mTt,vTt nil [vex m:2 p:3 l:0 w:0 0x5E /r:reg] s:AMXINT8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 + +# 0x60 - 0x6F + +# 0x70 - 0x7F +VPBROADCASTB Vx,Wb nil [vex m:2 p:1 l:x w:0 0x78 /r] s:AVX2, t:BROADCAST, w:W|R, e:6 +VPBROADCASTW Vx,Ww nil [vex m:2 p:1 l:x w:0 0x79 /r] s:AVX2, t:BROADCAST, w:W|R, e:6 + +# 0x80 - 0x8F +VPMASKMOVD Vx,Hx,Mx nil [vex m:2 p:1 l:x w:0 0x8C /r:mem] s:AVX2, t:AVX2, w:W|R|R, e:6 +VPMASKMOVQ Vx,Hx,Mx nil [vex m:2 p:1 l:x w:1 0x8C /r:mem] s:AVX2, t:AVX2, w:W|R|R, e:6 +VPMASKMOVD Mx,Hx,Vx nil [vex m:2 p:1 l:x w:0 0x8E /r:mem] s:AVX2, t:AVX2, w:W|R|R, e:6 +VPMASKMOVQ Mx,Hx,Vx nil [vex m:2 p:1 l:x w:1 0x8E /r:mem] s:AVX2, t:AVX2, w:W|R|R, e:6 + +# 0x90 - 0x9F +VPGATHERDD Vx,Mvm32n,Hx nil [vex m:2 p:1 l:x w:0 0x90 /r:mem vsib] s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12 +VPGATHERDQ Vx,Mvm32h,Hx nil [vex m:2 p:1 l:x w:1 0x90 /r:mem vsib] s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12 +VPGATHERQD Vdq,Mvm64n,Hdq nil [vex m:2 p:1 l:x w:0 0x91 /r:mem vsib] s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12 +VPGATHERQQ Vx,Mvm64n,Hx nil [vex m:2 p:1 l:x w:1 0x91 /r:mem vsib] s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12 +VGATHERDPS Vx,Mvm32n,Hx nil [vex m:2 p:1 l:x w:0 0x92 /r:mem vsib] s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12 +VGATHERDPD Vx,Mvm32h,Hx nil [vex m:2 p:1 l:x w:1 0x92 /r:mem vsib] s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12 +VGATHERQPS Vdq,Mvm64n,Hdq nil [vex m:2 p:1 l:x w:0 0x93 /r:mem vsib] s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12 +VGATHERQPD Vx,Mvm64n,Hx nil [vex m:2 p:1 l:x w:1 0x93 /r:mem vsib] s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12 + +VFMADDSUB132PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x96 /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMADDSUB132PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0x96 /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMSUBADD132PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x97 /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMSUBADD132PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0x97 /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMADD132PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x98 /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMADD132PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0x98 /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMADD132SS Vdq,Hdq,Wss nil [vex m:2 p:1 l:x w:0 0x99 /r] s:FMA, t:VFMA, w:RW|R|R, e:3 +VFMADD132SD Vdq,Hdq,Wsd nil [vex m:2 p:1 l:x w:1 0x99 /r] s:FMA, t:VFMA, w:RW|R|R, e:3 +VFMSUB132PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x9A /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMSUB132PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0x9A /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMSUB132SS Vdq,Hdq,Wss nil [vex m:2 p:1 l:x w:0 0x9B /r] s:FMA, t:VFMA, w:RW|R|R, e:3 +VFMSUB132SD Vdq,Hdq,Wsd nil [vex m:2 p:1 l:x w:1 0x9B /r] s:FMA, t:VFMA, w:RW|R|R, e:3 +VFNMADD132PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x9C /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFNMADD132PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0x9C /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFNMADD132SS Vdq,Hdq,Wss nil [vex m:2 p:1 l:i w:0 0x9D /r] s:FMA, t:VFMA, w:RW|R|R, e:3 +VFNMADD132SD Vdq,Hdq,Wsd nil [vex m:2 p:1 l:i w:1 0x9D /r] s:FMA, t:VFMA, w:RW|R|R, e:3 +VFNMSUB132PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x9E /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFNMSUB132PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0x9E /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFNMSUB132SS Vdq,Hdq,Wss nil [vex m:2 p:1 l:0 w:0 0x9F /r] s:FMA, t:VFMA, w:RW|R|R, e:3 +VFNMSUB132SD Vdq,Hdq,Wsd nil [vex m:2 p:1 l:0 w:1 0x9F /r] s:FMA, t:VFMA, w:RW|R|R, e:3 + +# 0xA0 - 0xAF +VFMADDSUB213PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0xA6 /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMADDSUB213PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0xA6 /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMSUBADD213PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0xA7 /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMSUBADD213PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0xA7 /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMADD213PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0xA8 /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMADD213PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0xA8 /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMADD213SS Vdq,Hdq,Wss nil [vex m:2 p:1 l:0 w:0 0xA9 /r] s:FMA, t:VFMA, w:RW|R|R, e:3 +VFMADD213SD Vdq,Hdq,Wsd nil [vex m:2 p:1 l:0 w:1 0xA9 /r] s:FMA, t:VFMA, w:RW|R|R, e:3 +VFMSUB213PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0xAA /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMSUB213PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0xAA /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMSUB213SS Vdq,Hdq,Wss nil [vex m:2 p:1 l:0 w:0 0xAB /r] s:FMA, t:VFMA, w:RW|R|R, e:3 +VFMSUB213SD Vdq,Hdq,Wsd nil [vex m:2 p:1 l:0 w:1 0xAB /r] s:FMA, t:VFMA, w:RW|R|R, e:3 +VFNMADD213PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0xAC /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFNMADD213PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0xAC /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFNMADD213SS Vdq,Hdq,Wss nil [vex m:2 p:1 l:0 w:0 0xAD /r] s:FMA, t:VFMA, w:RW|R|R, e:3 +VFNMADD213SD Vdq,Hdq,Wsd nil [vex m:2 p:1 l:0 w:1 0xAD /r] s:FMA, t:VFMA, w:RW|R|R, e:3 +VFNMSUB213PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0xAE /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFNMSUB213PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0xAE /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFNMSUB213SS Vdq,Hdq,Wss nil [vex m:2 p:1 l:0 w:0 0xAF /r] s:FMA, t:VFMA, w:RW|R|R, e:3 +VFNMSUB213SD Vdq,Hdq,Wsd nil [vex m:2 p:1 l:0 w:1 0xAF /r] s:FMA, t:VFMA, w:RW|R|R, e:3 + +# 0xB0 - 0xBF +VFMADDSUB231PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0xB6 /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMADDSUB231PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0xB6 /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMSUBADD231PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0xB7 /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMSUBADD231PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0xB7 /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMADD231PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0xB8 /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMADD231PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0xB8 /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMADD231SS Vdq,Hdq,Wss nil [vex m:2 p:1 l:0 w:0 0xB9 /r] s:FMA, t:VFMA, w:RW|R|R, e:3 +VFMADD231SD Vdq,Hdq,Wsd nil [vex m:2 p:1 l:0 w:1 0xB9 /r] s:FMA, t:VFMA, w:RW|R|R, e:3 +VFMSUB231PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0xBA /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMSUB231PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0xBA /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMSUB231SS Vdq,Hdq,Wss nil [vex m:2 p:1 l:0 w:0 0xBB /r] s:FMA, t:VFMA, w:RW|R|R, e:3 +VFMSUB231SD Vdq,Hdq,Wsd nil [vex m:2 p:1 l:0 w:1 0xBB /r] s:FMA, t:VFMA, w:RW|R|R, e:3 +VFNMADD231PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0xBC /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFNMADD231PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0xBC /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFNMADD231SS Vdq,Hdq,Wss nil [vex m:2 p:1 l:0 w:0 0xBD /r] s:FMA, t:VFMA, w:RW|R|R, e:3 +VFNMADD231SD Vdq,Hdq,Wsd nil [vex m:2 p:1 l:0 w:1 0xBD /r] s:FMA, t:VFMA, w:RW|R|R, e:3 +VFNMSUB231PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0xBE /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFNMSUB231PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0xBE /r] s:FMA, t:VFMA, w:RW|R|R, e:2 +VFNMSUB231SS Vdq,Hdq,Wss nil [vex m:2 p:1 l:0 w:0 0xBF /r] s:FMA, t:VFMA, w:RW|R|R, e:3 +VFNMSUB231SD Vdq,Hdq,Wsd nil [vex m:2 p:1 l:0 w:1 0xBF /r] s:FMA, t:VFMA, w:RW|R|R, e:3 +VGF2P8MULB Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0xCF /r] s:GFNI, t:GFNI, w:W|R|R +VAESIMC Vdq,Wdq nil [vex m:2 p:1 l:0 w:i 0xDB /r] s:AES, t:AES, w:W|R, e:4 +VAESENC Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0xDC /r] s:AES, t:AES, w:W|R|R, e:4 +VAESENCLAST Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0xDD /r] s:AES, t:AES, w:W|R|R, e:4 +VAESDEC Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0xDE /r] s:AES, t:AES, w:W|R|R, e:4 +VAESDECLAST Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0xDF /r] s:AES, t:AES, w:W|R|R, e:4 + +# 0xF0 - 0xFF +ANDN Gy,By,Ey Fv [vex m:2 p:0 l:0 w:x 0xF2 /r] s:BMI1, t:BMI1, w:W|R|R|W, f:CF=0|PF=u|AF=u|ZF=m|SF=m|OF=0, e:13 +BLSR By,Ey Fv [vex m:2 p:0 l:0 w:x 0xF3 /1] s:BMI1, t:BMI1, w:W|R|W, f:CF=m|PF=u|AF=u|ZF=m|SF=m|OF=0, e:13 +BLSMSK By,Ey Fv [vex m:2 p:0 l:0 w:x 0xF3 /2] s:BMI1, t:BMI1, w:W|R|W, f:CF=m|PF=u|AF=u|ZF=0|SF=m|OF=0, e:13 +BLSI By,Ey Fv [vex m:2 p:0 l:0 w:x 0xF3 /3] s:BMI1, t:BMI1, w:W|R|W, f:CF=m|PF=u|AF=u|ZF=m|SF=m|OF=0, e:13 +BZHI Gy,Ey,By Fv [vex m:2 p:0 l:0 w:x 0xF5 /r] s:BMI2, t:BMI2, w:W|R|R|W, f:CF=m|PF=u|AF=u|ZF=m|SF=m|OF=0, e:13 +PEXT Gy,By,Ey nil [vex m:2 p:2 l:0 w:x 0xF5 /r] s:BMI2, t:BMI2, w:W|R|R|W, e:13 +PDEP Gy,By,Ey nil [vex m:2 p:3 l:0 w:x 0xF5 /r] s:BMI2, t:BMI2, w:W|R|R|W, e:13 +MULX Gy,By,Ey yDX [vex m:2 p:3 l:0 w:x 0xF6 /r] s:BMI2, t:BMI2, w:W|W|R|R, e:13 +BEXTR Gy,Ey,By Fv [vex m:2 p:0 l:0 w:x 0xF7 /r] s:BMI1, t:BMI1, w:W|R|R|W, f:CF=0|PF=u|AF=u|ZF=m|SF=u|OF=0, e:13 +SHLX Gy,Ey,By nil [vex m:2 p:1 l:0 w:x 0xF7 /r] s:BMI2, t:BMI2, w:W|R|R, e:13 +SARX Gy,Ey,By nil [vex m:2 p:2 l:0 w:x 0xF7 /r] s:BMI2, t:BMI2, w:W|R|R, e:13 +SHRX Gy,Ey,By nil [vex m:2 p:3 l:0 w:x 0xF7 /r] s:BMI2, t:BMI2, w:W|R|R, e:13 diff --git a/isagenerator/instructions/table_vex3.dat b/isagenerator/instructions/table_vex3.dat new file mode 100644 index 0000000..6daf0cd --- /dev/null +++ b/isagenerator/instructions/table_vex3.dat @@ -0,0 +1,125 @@ +# Mnemonic Explicit Operands Implicit Operands Encoding Fags, Prefixes, Set, Category, Class, RW map, Additional ops +#------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +# 0x00 - 0x0F +VPERMQ Vqq,Wqq,Ib nil [vex m:3 p:1 l:1 w:1 0x00 /r ib] s:AVX2, t:AVX2, w:W|R|R, e:4 +VPERMPD Vqq,Wqq,Ib nil [vex m:3 p:1 l:1 w:1 0x01 /r ib] s:AVX2, t:AVX2, w:W|R|R, e:4 +VPBLENDD Vx,Hx,Wx,Ib nil [vex m:3 p:1 l:x w:0 0x02 /r ib] s:AVX2, t:AVX2, w:W|R|R|R, e:4 +VPERMILPS Vx,Wx,Ib nil [vex m:3 p:1 l:x w:0 0x04 /r ib] s:AVX, t:AVX, w:W|R|R, e:4 +VPERMILPD Vx,Wx,Ib nil [vex m:3 p:1 l:x w:0 0x05 /r ib] s:AVX, t:AVX, w:W|R|R, e:4 +VPERM2F128 Vqq,Hqq,Wqq,Ib nil [vex m:3 p:1 l:1 w:0 0x06 /r ib] s:AVX, t:AVX, w:W|R|R|R, e:4 +VROUNDPS Vx,Wx,Ib nil [vex m:3 p:1 l:x w:i 0x08 /r ib] s:AVX, t:AVX, w:W|R|R, e:2 +VROUNDPD Vx,Wx,Ib nil [vex m:3 p:1 l:x w:i 0x09 /r ib] s:AVX, t:AVX, w:W|R|R, e:2 +VROUNDSS Vss,Hss,Wss,Ib nil [vex m:3 p:1 l:i w:i 0x0A /r ib] s:AVX, t:AVX, w:W|R|R|R, e:3 +VROUNDSD Vsd,Hsd,Wsd,Ib nil [vex m:3 p:1 l:i w:i 0x0B /r ib] s:AVX, t:AVX, w:W|R|R|R, e:3 +VBLENDPS Vx,Hx,Wx,Ib nil [vex m:3 p:1 l:x w:i 0x0C /r ib] s:AVX, t:AVX, w:W|R|R|R, e:4 +VBLENDPD Vx,Hx,Wx,Ib nil [vex m:3 p:1 l:x w:i 0x0D /r ib] s:AVX, t:AVX, w:W|R|R|R, e:4 +VPBLENDW Vx,Hx,Wx,Ib nil [vex m:3 p:1 l:x w:i 0x0E /r ib] s:AVX, t:AVX, w:W|R|R|R, e:4 +VPALIGNR Vx,Hx,Wx,Ib nil [vex m:3 p:1 l:x w:i 0x0F /r ib] s:AVX, t:AVX, w:W|R|R|R, e:4 + +# 0x10 - 0x1F +VPEXTRB Mb,Vdq,Ib nil [vex m:3 p:1 l:0 w:0 0x14 /r:mem ib] s:AVX, t:AVX, w:W|R|R, e:5 +VPEXTRB Ry,Vdq,Ib nil [vex m:3 p:1 l:0 w:0 0x14 /r:reg ib] s:AVX, t:AVX, w:W|R|R, e:5 +VPEXTRW Mw,Vdq,Ib nil [vex m:3 p:1 l:0 w:0 0x15 /r:mem ib] s:AVX, t:AVX, w:W|R|R, e:5 +VPEXTRW Ry,Vdq,Ib nil [vex m:3 p:1 l:0 w:0 0x15 /r:reg ib] s:AVX, t:AVX, w:W|R|R, e:5 +VPEXTRD Ey,Vdq,Ib nil [vex m:3 p:1 l:0 w:0 0x16 /r ib] s:AVX, t:AVX, w:W|R|R, e:5 +VPEXTRQ Ey,Vdq,Ib nil [vex m:3 p:1 l:0 w:1 0x16 /r ib] s:AVX, t:AVX, w:W|R|R, e:5 +VEXTRACTPS Md,Vdq,Ib nil [vex m:3 p:1 l:0 w:i 0x17 /r:mem ib] s:AVX, t:AVX, w:W|R|R, e:5 +VEXTRACTPS Ry,Vdq,Ib nil [vex m:3 p:1 l:0 w:i 0x17 /r:reg ib] s:AVX, t:AVX, w:W|R|R, e:5 +VINSERTF128 Vqq,Hqq,Wdq,Ib nil [vex m:3 p:1 l:1 w:0 0x18 /r ib] s:AVX, t:AVX, w:W|R|R|R, e:6 +VEXTRACTF128 Wdq,Vqq,Ib nil [vex m:3 p:1 l:1 w:0 0x19 /r ib] s:AVX, t:AVX, w:W|R|R, e:6 +VCVTPS2PH Wq,Vdq,Ib nil [vex m:3 p:1 l:0 w:0 0x1D /r ib] s:F16C, t:CONVERT, w:W|R|R, e:11 +VCVTPS2PH Wdq,Vqq,Ib nil [vex m:3 p:1 l:1 w:0 0x1D /r ib] s:F16C, t:CONVERT, w:W|R|R, e:11 + +# 0x20 - 0x2F +VPINSRB Vdq,Hdq,Mb,Ib nil [vex m:3 p:1 l:0 w:i 0x20 /r:mem ib] s:AVX, t:AVX, w:W|R|R|R, e:5 +VPINSRB Vdq,Hdq,Rd,Ib nil [vex m:3 p:1 l:0 w:i 0x20 /r:reg ib] s:AVX, t:AVX, w:W|R|R|R, e:5 +VINSERTPS Vdq,Hdq,Md,Ib nil [vex m:3 p:1 l:0 w:i 0x21 /r:mem ib] s:AVX, t:AVX, w:W|R|R|R, e:5 +VINSERTPS Vdq,Hdq,Udq,Ib nil [vex m:3 p:1 l:0 w:i 0x21 /r:reg ib] s:AVX, t:AVX, w:W|R|R|R, e:5 +VPINSRD Vdq,Hdq,Ey,Ib nil [vex m:3 p:1 l:0 w:0 0x22 /r ib] s:AVX, t:AVX, w:W|R|R|R, e:5 +VPINSRQ Vdq,Hdq,Ey,Ib nil [vex m:3 p:1 l:0 w:1 0x22 /r ib] s:AVX, t:AVX, w:W|R|R|R, e:5 + +# 0x30 - 0x3F +KSHIFTRW rKw,mKw,Ib nil [vex m:3 p:1 l:0 w:1 0x30 /r:reg ib] s:AVX512F, t:KMASK, c:KSHIFTR, w:W|R|R, e:K20 +KSHIFTRB rKb,mKb,Ib nil [vex m:3 p:1 l:0 w:0 0x30 /r:reg ib] s:AVX512DQ, t:KMASK, c:KSHIFTR, w:W|R|R, e:K20 +KSHIFTRQ rKq,mKq,Ib nil [vex m:3 p:1 l:0 w:1 0x31 /r:reg ib] s:AVX512BW, t:KMASK, c:KSHIFTR, w:W|R|R, e:K20 +KSHIFTRD rKd,mKd,Ib nil [vex m:3 p:1 l:0 w:0 0x31 /r:reg ib] s:AVX512BW, t:KMASK, c:KSHIFTR, w:W|R|R, e:K20 +KSHIFTLW rKw,mKw,Ib nil [vex m:3 p:1 l:0 w:1 0x32 /r:reg ib] s:AVX512F, t:KMASK, c:KSHIFTL, w:W|R|R, e:K20 +KSHIFTLB rKb,mKb,Ib nil [vex m:3 p:1 l:0 w:0 0x32 /r:reg ib] s:AVX512DQ, t:KMASK, c:KSHIFTL, w:W|R|R, e:K20 +KSHIFTLQ rKq,mKq,Ib nil [vex m:3 p:1 l:0 w:1 0x33 /r:reg ib] s:AVX512BW, t:KMASK, c:KSHIFTL, w:W|R|R, e:K20 +KSHIFTLD rKd,mKd,Ib nil [vex m:3 p:1 l:0 w:0 0x33 /r:reg ib] s:AVX512BW, t:KMASK, c:KSHIFTL, w:W|R|R, e:K20 +VINSERTI128 Vqq,Hqq,Wdq,Ib nil [vex m:3 p:1 l:1 w:0 0x38 /r ib] s:AVX2, t:AVX2, w:W|R|R|R, e:6 +VEXTRACTI128 Wdq,Vqq,Ib nil [vex m:3 p:1 l:1 w:0 0x39 /r ib] s:AVX2, t:AVX2, w:W|R|R|R, e:6 + +# 0x40 - 0x4F +VDPPS Vx,Hx,Wx,Ib nil [vex m:3 p:1 l:x w:i 0x40 /r ib] s:AVX, t:AVX, w:W|R|R|R, e:2 +VDPPD Vdq,Hdq,Wdq,Ib nil [vex m:3 p:1 l:0 w:i 0x41 /r ib] s:AVX, t:AVX, w:W|R|R|R, e:2 +VMPSADBW Vx,Hx,Wx,Ib nil [vex m:3 p:1 l:x w:i 0x42 /r ib] s:AVX, t:AVX, w:W|R|R|R, e:4 +VPCLMULQDQ Vdq,Hdq,Wdq,Ib nil [vex m:3 p:1 l:0 w:i 0x44 /r ib] s:VPCLMULQDQ, t:VPCLMULQDQ, w:W|R|R|R, e:4 +VPERM2I128 Vqq,Hqq,Wqq,Ib nil [vex m:3 p:1 l:1 w:0 0x46 /r ib] s:AVX2, t:AVX2, w:W|R|R|R, e:6 +VPERMILzz2PS Vx,Hx,Wx,Lx,Ib nil [vex m:3 p:1 l:x w:0 0x48 /r ib] s:XOP, t:XOP, w:W|R|R|R|R, e:4 +VPERMILzz2PS Vx,Hx,Lx,Wx,Ib nil [vex m:3 p:1 l:x w:1 0x48 /r ib] s:XOP, t:XOP, w:W|R|R|R|R, e:4 +VPERMILzz2PD Vx,Hx,Wx,Lx,Ib nil [vex m:3 p:1 l:x w:0 0x49 /r ib] s:XOP, t:XOP, w:W|R|R|R|R, e:4 +VPERMILzz2PD Vx,Hx,Lx,Wx,Ib nil [vex m:3 p:1 l:x w:1 0x49 /r ib] s:XOP, t:XOP, w:W|R|R|R|R, e:4 +VBLENDVPS Vx,Hx,Wx,Lx nil [vex m:3 p:1 l:x w:0 0x4A /r is4] s:AVX, t:AVX, w:W|R|R|R, e:4 +VBLENDVPD Vx,Hx,Wx,Lx nil [vex m:3 p:1 l:x w:0 0x4B /r is4] s:AVX, t:AVX, w:W|R|R|R, e:4 +VPBLENDVB Vx,Hx,Wx,Lx nil [vex m:3 p:1 l:x w:0 0x4C /r is4] s:AVX, t:AVX, w:W|R|R|R, e:4 + +# 0x50 - 0x5F +VFMADDSUBPS Vx,Hx,Wx,Lx nil [vex m:3 p:1 l:x w:0 0x5C /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFMADDSUBPS Vx,Hx,Lx,Wx nil [vex m:3 p:1 l:x w:1 0x5C /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFMADDSUBPD Vx,Hx,Wx,Lx nil [vex m:3 p:1 l:x w:0 0x5D /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFMADDSUBPD Vx,Hx,Lx,Wx nil [vex m:3 p:1 l:x w:1 0x5D /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFMSUBADDPS Vx,Hx,Wx,Lx nil [vex m:3 p:1 l:x w:0 0x5E /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFMSUBADDPS Vx,Hx,Lx,Wx nil [vex m:3 p:1 l:x w:1 0x5E /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFMSUBADDPD Vx,Hx,Wx,Lx nil [vex m:3 p:1 l:x w:0 0x5F /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFMSUBADDPD Vx,Hx,Lx,Wx nil [vex m:3 p:1 l:x w:1 0x5F /r is4] s:FMA4, t:FMA4, w:W|R|R|R + +# 0x60 - 0x6F +VPCMPESTRM Vdq,Wdq,Ib yAX,yDX,XMM0,Fv [vex m:3 p:1 l:0 w:i 0x60 /r ib] s:AVX, t:STTNI, w:R|R|R|R|R|W|W, f:PCMPSTR, e:4 +VPCMPESTRI Vdq,Wdq,Ib yAX,yDX,yCX,Fv [vex m:3 p:1 l:0 w:i 0x61 /r ib] s:AVX, t:STTNI, w:R|R|R|R|R|W|W, f:PCMPSTR, e:4 +VPCMPISTRM Vdq,Wdq,Ib XMM0,Fv [vex m:3 p:1 l:0 w:i 0x62 /r ib] s:AVX, t:STTNI, w:R|R|R|W|W, f:PCMPSTR, e:4 +VPCMPISTRI Vdq,Wdq,Ib yCX,Fv [vex m:3 p:1 l:0 w:i 0x63 /r ib] s:AVX, t:STTNI, w:R|R|R|W|W, f:PCMPSTR, e:4 +VFMADDPS Vx,Hx,Wx,Lx nil [vex m:3 p:1 l:x w:0 0x68 /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFMADDPS Vx,Hx,Lx,Wx nil [vex m:3 p:1 l:x w:1 0x68 /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFMADDPD Vx,Hx,Wx,Lx nil [vex m:3 p:1 l:x w:0 0x69 /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFMADDPD Vx,Hx,Lx,Wx nil [vex m:3 p:1 l:x w:1 0x69 /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFMADDSS Vdq,Hdq,Wss,Ldq nil [vex m:3 p:1 l:x w:0 0x6A /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFMADDSS Vdq,Hdq,Ldq,Wss nil [vex m:3 p:1 l:x w:1 0x6A /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFMADDSD Vdq,Hdq,Wsd,Ldq nil [vex m:3 p:1 l:x w:0 0x6B /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFMADDSD Vdq,Hdq,Ldq,Wsd nil [vex m:3 p:1 l:x w:1 0x6B /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFMSUBPS Vx,Hx,Wx,Lx nil [vex m:3 p:1 l:x w:0 0x6C /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFMSUBPS Vx,Hx,Lx,Wx nil [vex m:3 p:1 l:x w:1 0x6C /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFMSUBPD Vx,Hx,Wx,Lx nil [vex m:3 p:1 l:x w:0 0x6D /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFMSUBPD Vx,Hx,Lx,Wx nil [vex m:3 p:1 l:x w:1 0x6D /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFMSUBSS Vdq,Hdq,Wss,Ldq nil [vex m:3 p:1 l:x w:0 0x6E /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFMSUBSS Vdq,Hdq,Ldq,Wss nil [vex m:3 p:1 l:x w:1 0x6E /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFMSUBSD Vdq,Hdq,Wsd,Ldq nil [vex m:3 p:1 l:x w:0 0x6F /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFMSUBSD Vdq,Hdq,Ldq,Wsd nil [vex m:3 p:1 l:x w:1 0x6F /r is4] s:FMA4, t:FMA4, w:W|R|R|R + +# 0x70 - 0x7F +VFNMADDPS Vx,Hx,Wx,Lx nil [vex m:3 p:1 l:x w:0 0x78 /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFNMADDPS Vx,Hx,Lx,Wx nil [vex m:3 p:1 l:x w:1 0x78 /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFNMADDPD Vx,Hx,Wx,Lx nil [vex m:3 p:1 l:x w:0 0x79 /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFNMADDPD Vx,Hx,Lx,Wx nil [vex m:3 p:1 l:x w:1 0x79 /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFNMADDSS Vdq,Hdq,Wss,Ldq nil [vex m:3 p:1 l:x w:0 0x7A /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFNMADDSS Vdq,Hdq,Ldq,Wss nil [vex m:3 p:1 l:x w:1 0x7A /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFNMADDSD Vdq,Hdq,Wsd,Ldq nil [vex m:3 p:1 l:x w:0 0x7B /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFNMADDSD Vdq,Hdq,Ldq,Wsd nil [vex m:3 p:1 l:x w:1 0x7B /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFNMSUBPS Vx,Hx,Wx,Lx nil [vex m:3 p:1 l:x w:0 0x7C /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFNMSUBPS Vx,Hx,Lx,Wx nil [vex m:3 p:1 l:x w:1 0x7C /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFNMSUBPD Vx,Hx,Wx,Lx nil [vex m:3 p:1 l:x w:0 0x7D /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFNMSUBPD Vx,Hx,Lx,Wx nil [vex m:3 p:1 l:x w:1 0x7D /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFNMSUBSS Vdq,Hdq,Wss,Ldq nil [vex m:3 p:1 l:x w:0 0x7E /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFNMSUBSS Vdq,Hdq,Ldq,Wss nil [vex m:3 p:1 l:x w:1 0x7E /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFNMSUBSD Vdq,Hdq,Wsd,Ldq nil [vex m:3 p:1 l:x w:0 0x7F /r is4] s:FMA4, t:FMA4, w:W|R|R|R +VFNMSUBSD Vdq,Hdq,Ldq,Wsd nil [vex m:3 p:1 l:x w:1 0x7F /r is4] s:FMA4, t:FMA4, w:W|R|R|R + +# 0xC0 - 0xCF +VGF2P8AFFINEQB Vx,Hx,Wx,Ib nil [vex m:3 p:1 l:x w:1 0xCE /r ib] s:GFNI, t:GFNI, w:W|R|R|R, e:4 +VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib nil [vex m:3 p:1 l:x w:1 0xCF /r ib] s:GFNI, t:GFNI, w:W|R|R|R, e:4 + +# 0xD0 - 0xDF +VAESKEYGENASSIST Vdq,Wdq,Ib nil [vex m:3 p:1 l:0 w:i 0xDF /r ib] s:AES, t:AES, w:W|R|R, e:4 + +# 0xF0 - 0xFF +RORX Gy,Ey,Ib nil [vex m:3 p:3 l:0 w:x 0xF0 /r ib] s:BMI2, t:BMI2, w:W|R|R, e:13 diff --git a/isagenerator/instructions/table_xop.dat b/isagenerator/instructions/table_xop.dat new file mode 100644 index 0000000..88e83b9 --- /dev/null +++ b/isagenerator/instructions/table_xop.dat @@ -0,0 +1,193 @@ +# Mnemonic Explicit Operands Implicit Operands Encoding Fags, Prefixes, Set, Category, Class, RW map, Additional ops +#------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +# XOP.mmmmm = 8 + +# 0x00 - 0x0F + +# 0x10 - 0x1F + +# 0x20 - 0x2F + +# 0x30 - 0x3F + +# 0x40 - 0x4F + +# 0x50 - 0x5F + +# 0x60 - 0x6F + +# 0x70 - 0x7F + +# 0x80 - 0x8F +VPMACSSWW Vdq,Hdq,Wdq,Ldq nil [xop m:8 0x85 /r is4] s:XOP, t:XOP, w:W|R|R|R +VPMACSSWD Vdq,Hdq,Wdq,Ldq nil [xop m:8 0x86 /r is4] s:XOP, t:XOP, w:W|R|R|R +VPMACSSDQL Vdq,Hdq,Wdq,Ldq nil [xop m:8 0x87 /r is4] s:XOP, t:XOP, w:W|R|R|R +VPMACSSDD Vdq,Hdq,Wdq,Ldq nil [xop m:8 0x8E /r is4] s:XOP, t:XOP, w:W|R|R|R +VPMACSSDQH Vdq,Hdq,Wdq,Ldq nil [xop m:8 0x8F /r is4] s:XOP, t:XOP, w:W|R|R|R + +# 0x90 - 0x9F +VPMACSWW Vdq,Hdq,Wdq,Ldq nil [xop m:8 0x95 /r is4] s:XOP, t:XOP, w:W|R|R|R +VPMACSWD Vdq,Hdq,Wdq,Ldq nil [xop m:8 0x96 /r is4] s:XOP, t:XOP, w:W|R|R|R +VPMACSDQL Vdq,Hdq,Wdq,Ldq nil [xop m:8 0x97 /r is4] s:XOP, t:XOP, w:W|R|R|R +VPMACSDD Vdq,Hdq,Wdq,Ldq nil [xop m:8 0x9E /r is4] s:XOP, t:XOP, w:W|R|R|R +VPMACSDQH Vdq,Hdq,Wdq,Ldq nil [xop m:8 0x9F /r is4] s:XOP, t:XOP, w:W|R|R|R + +# 0xA0 - 0xAF +VPCMOV Vx,Hx,Wx,Lx nil [xop m:8 w:0 0xA2 /r is4] s:XOP, t:XOP, w:W|R|R|R +VPCMOV Vx,Hx,Lx,Wx nil [xop m:8 w:1 0xA2 /r is4] s:XOP, t:XOP, w:W|R|R|R +VPPERM Vx,Hx,Wx,Lx nil [xop m:8 w:0 0xA3 /r is4] s:XOP, t:XOP, w:W|R|R|R +VPPERM Vx,Hx,Lx,Wx nil [xop m:8 w:1 0xA3 /r is4] s:XOP, t:XOP, w:W|R|R|R +VPMADCSSWD Vdq,Hdq,Wdq,Ldq nil [xop m:8 0xA6 /r is4] s:XOP, t:XOP, w:W|R|R|R + +# 0xB0 - 0xBF +VPMADCSWD Vdq,Hdq,Wdq,Ldq nil [xop m:8 0xB6 /r is4] s:XOP, t:XOP, w:W|R|R|R + +# 0xC0 - 0xCF +VPROTB Vdq,Wdq,Ib nil [xop m:8 0xC0 /r ib] s:XOP, t:XOP, w:W|R|R +VPROTW Vdq,Wdq,Ib nil [xop m:8 0xC1 /r ib] s:XOP, t:XOP, w:W|R|R +VPROTD Vdq,Wdq,Ib nil [xop m:8 0xC2 /r ib] s:XOP, t:XOP, w:W|R|R +VPROTQ Vdq,Wdq,Ib nil [xop m:8 0xC3 /r ib] s:XOP, t:XOP, w:W|R|R +VPCOMB Vdq,Hdq,Wdq,Ib nil [xop m:8 0xCC /r ib] s:XOP, t:XOP, w:W|R|R|R +VPCOMW Vdq,Hdq,Wdq,Ib nil [xop m:8 0xCD /r ib] s:XOP, t:XOP, w:W|R|R|R +VPCOMD Vdq,Hdq,Wdq,Ib nil [xop m:8 0xCE /r ib] s:XOP, t:XOP, w:W|R|R|R +VPCOMQ Vdq,Hdq,Wdq,Ib nil [xop m:8 0xCF /r ib] s:XOP, t:XOP, w:W|R|R|R + +# 0xD0 - 0xDF + +# 0xE0 - 0xEF +VPCOMUB Vdq,Hdq,Wdq,Ib nil [xop m:8 0xEC /r ib] s:XOP, t:XOP, w:W|R|R|R +VPCOMUW Vdq,Hdq,Wdq,Ib nil [xop m:8 0xED /r ib] s:XOP, t:XOP, w:W|R|R|R +VPCOMUD Vdq,Hdq,Wdq,Ib nil [xop m:8 0xEE /r ib] s:XOP, t:XOP, w:W|R|R|R +VPCOMUQ Vdq,Hdq,Wdq,Ib nil [xop m:8 0xEF /r ib] s:XOP, t:XOP, w:W|R|R|R + +# 0xF0 - 0xFF + + + +# XOP.mmmmm = 9 + +# 0x00 - 0x0F +BLCFILL By,Ey nil [xop m:9 0x01 /1] s:TBM, t:BITBYTE, w:RW|R +BLSFILL By,Ey nil [xop m:9 0x01 /2] s:TBM, t:BITBYTE, w:RW|R +BLCS By,Ey nil [xop m:9 0x01 /3] s:TBM, t:BITBYTE, w:RW|R +TZMSK By,Ey nil [xop m:9 0x01 /4] s:TBM, t:BITBYTE, w:RW|R +BLCIC By,Ey nil [xop m:9 0x01 /5] s:TBM, t:BITBYTE, w:RW|R +BLSIC By,Ey nil [xop m:9 0x01 /6] s:TBM, t:BITBYTE, w:RW|R +T1MSKC By,Ey nil [xop m:9 0x01 /7] s:TBM, t:BITBYTE, w:RW|R +BLCMSK By,Ey nil [xop m:9 0x02 /1] s:TBM, t:BITBYTE, w:RW|R +BLCI By,Ey nil [xop m:9 0x02 /6] s:TBM, t:BITBYTE, w:RW|R + +# 0x10 - 0x1F +LLWPCB Ry nil [xop m:9 0x12 /0:reg] s:LWP, t:LWP, w:R +SLWPCB Ry nil [xop m:9 0x12 /1:reg] s:LWP, t:LWP, w:R + +# 0x20 - 0x2F + +# 0x30 - 0x3F + +# 0x40 - 0x4F + +# 0x50 - 0x5F + +# 0x60 - 0x6F + +# 0x70 - 0x7F + +# 0x80 - 0x8F +VFRCZPS Vx,Wx nil [xop m:9 0x80 /r] s:XOP, t:XOP, w:W|R +VFRCZPD Vx,Wx nil [xop m:9 0x81 /r] s:XOP, t:XOP, w:W|R +VFRCZSS Vdq,Wss nil [xop m:9 0x82 /r] s:XOP, t:XOP, w:W|R +VFRCZSD Vdq,Wsd nil [xop m:9 0x83 /r] s:XOP, t:XOP, w:W|R +VPSHAB Vdq,Wdq,Hdq nil [xop m:9 w:0 0x98 /r] s:XOP, t:XOP, w:W|R|R +VPSHAB Vdq,Hdq,Wdq nil [xop m:9 w:1 0x98 /r] s:XOP, t:XOP, w:W|R|R +VPSHAW Vdq,Wdq,Hdq nil [xop m:9 w:0 0x99 /r] s:XOP, t:XOP, w:W|R|R +VPSHAW Vdq,Hdq,Wdq nil [xop m:9 w:1 0x99 /r] s:XOP, t:XOP, w:W|R|R +VPSHAD Vdq,Wdq,Hdq nil [xop m:9 w:0 0x9A /r] s:XOP, t:XOP, w:W|R|R +VPSHAD Vdq,Hdq,Wdq nil [xop m:9 w:1 0x9A /r] s:XOP, t:XOP, w:W|R|R +VPSHAQ Vdq,Wdq,Hdq nil [xop m:9 w:0 0x9B /r] s:XOP, t:XOP, w:W|R|R +VPSHAQ Vdq,Hdq,Wdq nil [xop m:9 w:1 0x9B /r] s:XOP, t:XOP, w:W|R|R + +# 0x90 - 0x9F +VPROTB Vdq,Wdq,Hdq nil [xop m:9 w:0 0x90 /r] s:XOP, t:XOP, w:W|R|R +VPROTB Vdq,Hdq,Wdq nil [xop m:9 w:1 0x90 /r] s:XOP, t:XOP, w:W|R|R +VPROTW Vdq,Wdq,Hdq nil [xop m:9 w:0 0x91 /r] s:XOP, t:XOP, w:W|R|R +VPROTW Vdq,Hdq,Wdq nil [xop m:9 w:1 0x91 /r] s:XOP, t:XOP, w:W|R|R +VPROTD Vdq,Wdq,Hdq nil [xop m:9 w:0 0x92 /r] s:XOP, t:XOP, w:W|R|R +VPROTD Vdq,Hdq,Wdq nil [xop m:9 w:1 0x92 /r] s:XOP, t:XOP, w:W|R|R +VPROTQ Vdq,Wdq,Hdq nil [xop m:9 w:0 0x93 /r] s:XOP, t:XOP, w:W|R|R +VPROTQ Vdq,Hdq,Wdq nil [xop m:9 w:1 0x93 /r] s:XOP, t:XOP, w:W|R|R +VPSHLB Vdq,Wdq,Hdq nil [xop m:9 w:0 0x94 /r] s:XOP, t:XOP, w:W|R|R +VPSHLB Vdq,Hdq,Wdq nil [xop m:9 w:1 0x94 /r] s:XOP, t:XOP, w:W|R|R +VPSHLB Vdq,Wdq,Hdq nil [xop m:9 w:0 0x95 /r] s:XOP, t:XOP, w:W|R|R +VPSHLB Vdq,Hdq,Wdq nil [xop m:9 w:1 0x95 /r] s:XOP, t:XOP, w:W|R|R +VPSHLB Vdq,Wdq,Hdq nil [xop m:9 w:0 0x96 /r] s:XOP, t:XOP, w:W|R|R +VPSHLB Vdq,Hdq,Wdq nil [xop m:9 w:1 0x96 /r] s:XOP, t:XOP, w:W|R|R +VPSHLQ Vdq,Wdq,Hdq nil [xop m:9 w:0 0x97 /r] s:XOP, t:XOP, w:W|R|R +VPSHLQ Vdq,Hdq,Wdq nil [xop m:9 w:1 0x97 /r] s:XOP, t:XOP, w:W|R|R + +# 0xA0 - 0xAF + +# 0xB0 - 0xBF + +# 0xC0 - 0xCF +VPHADDBW Vdq,Wdq nil [xop m:9 0xC1 /r] s:XOP, t:XOP, w:W|R +VPHADDBD Vdq,Wdq nil [xop m:9 0xC2 /r] s:XOP, t:XOP, w:W|R +VPHADDBQ Vdq,Wdq nil [xop m:9 0xC3 /r] s:XOP, t:XOP, w:W|R +VPHADDWD Vdq,Wdq nil [xop m:9 0xC6 /r] s:XOP, t:XOP, w:W|R +VPHADDWQ Vdq,Wdq nil [xop m:9 0xC7 /r] s:XOP, t:XOP, w:W|R +VPHADDDQ Vdq,Wdq nil [xop m:9 0xCB /r] s:XOP, t:XOP, w:W|R + +# 0xD0 - 0xDF +VPHADDUBW Vdq,Wdq nil [xop m:9 0xD1 /r] s:XOP, t:XOP, w:W|R +VPHADDUBD Vdq,Wdq nil [xop m:9 0xD2 /r] s:XOP, t:XOP, w:W|R +VPHADDUBQ Vdq,Wdq nil [xop m:9 0xD3 /r] s:XOP, t:XOP, w:W|R +VPHADDUWD Vdq,Wdq nil [xop m:9 0xD6 /r] s:XOP, t:XOP, w:W|R +VPHADDUWQ Vdq,Wdq nil [xop m:9 0xD7 /r] s:XOP, t:XOP, w:W|R +VPHADDUDQ Vdq,Wdq nil [xop m:9 0xDB /r] s:XOP, t:XOP, w:W|R + +# 0xE0 - 0xEF +VPHSUBBW Vdq,Wdq nil [xop m:9 0xE1 /r] s:XOP, t:XOP, w:W|R +VPHSUBWD Vdq,Wdq nil [xop m:9 0xE2 /r] s:XOP, t:XOP, w:W|R +VPHSUBDQ Vdq,Wdq nil [xop m:9 0xE3 /r] s:XOP, t:XOP, w:W|R + +# 0xF0 - 0xFF + + +# XOP.mmmmm = 0xA + +# 0x00 - 0x0F + +# 0x10 - 0x1F +BEXTR Gy,Ey,Id nil [xop m:A 0x10 /r id] s:TBM, t:BITBYTE, w:RW|R|R +LWPINS By,Ed,Id nil [xop m:A 0x12 /0 id] s:LWP, t:LWP, w:RW|R|R +LWPVAL By,Ed,Id nil [xop m:A 0x12 /1 id] s:LWP, t:LWP, w:RW|R|R + +# 0x20 - 0x2F + +# 0x30 - 0x3F + +# 0x40 - 0x4F + +# 0x50 - 0x5F + +# 0x60 - 0x6F + +# 0x70 - 0x7F + +# 0x80 - 0x8F + +# 0x90 - 0x9F + +# 0xA0 - 0xAF + +# 0xB0 - 0xBF + +# 0xC0 - 0xCF + +# 0xD0 - 0xDF + +# 0xE0 - 0xEF + +# 0xF0 - 0xFF + + diff --git a/isagenerator/isagenerator.vcxproj b/isagenerator/isagenerator.vcxproj new file mode 100644 index 0000000..e12ae5e --- /dev/null +++ b/isagenerator/isagenerator.vcxproj @@ -0,0 +1,166 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + {0E9D2957-34FA-40EE-B4B2-0D008D2FE317} + isagenerator + 10.0.18362.0 + + + + Application + true + v142 + MultiByte + + + Application + false + v142 + true + MultiByte + + + Application + true + v142 + MultiByte + + + Application + false + v142 + true + MultiByte + + + + + + + + + + + + + + + + + + + + + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + + + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + + + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + + + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + + + + Level3 + Disabled + true + + + generate_tables.py instructions + + + + + Level3 + Disabled + true + + + generate_tables.py instructions + + + + + Level3 + MaxSpeed + true + true + true + + + true + true + + + generate_tables.py instructions + + + + + Level3 + MaxSpeed + true + true + true + + + true + true + + + generate_tables.py instructions + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/isagenerator/isagenerator.vcxproj.filters b/isagenerator/isagenerator.vcxproj.filters new file mode 100644 index 0000000..b201614 --- /dev/null +++ b/isagenerator/isagenerator.vcxproj.filters @@ -0,0 +1,84 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + {8eaf791a-1023-446d-b655-528b2e53c283} + + + + + Source Files + + + Source Files + + + data + + + data + + + data + + + data + + + data + + + data + + + data + + + data + + + data + + + data + + + data + + + data + + + data + + + data + + + data + + + data + + + data + + + + + data + + + \ No newline at end of file diff --git a/pydis/README.md b/pydis/README.md new file mode 100644 index 0000000..46ed99f --- /dev/null +++ b/pydis/README.md @@ -0,0 +1,21 @@ +# The Bitdefender disassembler Python wrapper + +## Build + +Building and installing is easy: + +```bash +python3 setup.py build +python3 setup.py install +``` + +## Usage + +Use it by importing the pydis.disasm module: + +```python +from pydis.disasm import * + +instr = nd_decode_ex2(buff, arch, arch, arch, vendor, current_rip) +``` + diff --git a/pydis/_pydis/_pydis.c b/pydis/_pydis/_pydis.c new file mode 100644 index 0000000..bc7ade7 --- /dev/null +++ b/pydis/_pydis/_pydis.c @@ -0,0 +1,1131 @@ +/* + * Copyright (c) 2020 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +#define _SIGNAL_H +#include +#include "pydis.h" + + +static char module_docstring[] = "This module provides an interface for bddisasm."; + +static char pydis_decode_ex_docstring[] = "Disasemble at the provided address."; +static char pydis_decode_ex2_docstring[] = "Disasemble at the provided address."; +static char pydis_decode_docstring[] = "Disasemble at the provided address."; +static char pydis_to_text_docstring[] = "Disasemble at the provided address and give back only the text."; + + +static char *OperandTypeToString(ND_OPERAND_TYPE Type) +{ + switch (Type) + { + case ND_OP_NOT_PRESENT: return "not_present"; + case ND_OP_REG: return "reg"; + case ND_OP_MEM: return "mem"; + case ND_OP_IMM: return "imm"; + case ND_OP_OFFS: return "offs"; + case ND_OP_ADDR: return "addr"; + case ND_OP_CONST: return "const"; + case ND_OP_BANK: return "bank"; + } + + return "unknown"; +} + + +static char *OperandEncodingToString(ND_OPERAND_ENCODING Encoding) +{ + switch (Encoding) + { + case ND_OPE_NP: return "NP"; + case ND_OPE_R: return "R"; + case ND_OPE_M: return "M"; + case ND_OPE_V: return "V"; + case ND_OPE_D: return "D"; + case ND_OPE_O: return "O"; + case ND_OPE_I: return "I"; + case ND_OPE_C: return "C"; + case ND_OPE_1: return "1"; + case ND_OPE_L: return "L"; + case ND_OPE_A: return "A"; + case ND_OPE_E: return "E"; + case ND_OPE_S: return "S"; + } + + return "unknown"; +} + + +static char *RegTypeToString(ND_REG_TYPE RegType) +{ + switch (RegType) + { + case ND_REG_NOT_PRESENT: return "NOT_PRESENT"; + case ND_REG_GPR: return "GPR"; + case ND_REG_SEG: return "SEG"; + case ND_REG_FPU: return "FPU"; + case ND_REG_MMX: return "MMX"; + case ND_REG_SSE: return "SSE"; + case ND_REG_CR: return "CR"; + case ND_REG_DR: return "DR"; + case ND_REG_TR: return "TR"; + case ND_REG_BND: return "BND"; + case ND_REG_MSK: return "MSK"; + case ND_REG_TILE: return "TILE"; + case ND_REG_MSR: return "MSR"; + case ND_REG_XCR: return "XCR"; + case ND_REG_SYS: return "SYS"; + case ND_REG_X87: return "X87"; + case ND_REG_MXCSR: return "MXCSR"; + case ND_REG_PKRU: return "PKRU"; + case ND_REG_SSP: return "SSP"; + case ND_REG_FLG: return "FLG"; + case ND_REG_RIP: return "RIP"; + } + + return "unknown"; +} + + +static char *TupleTypeToString(ND_TUPLE TupleType) +{ + switch (TupleType) + { + case ND_TUPLE_None: return "None"; + case ND_TUPLE_FV: return "FV"; + case ND_TUPLE_HV: return "HV"; + case ND_TUPLE_T1S8: return "T1S8"; + case ND_TUPLE_T1S16: return "T1S16"; + case ND_TUPLE_T1S: return "T1S"; + case ND_TUPLE_T1F: return "T1F"; + case ND_TUPLE_T2: return "T2"; + case ND_TUPLE_T4: return "T4"; + case ND_TUPLE_T8: return "T8"; + case ND_TUPLE_FVM: return "FVM"; + case ND_TUPLE_HVM: return "HVM"; + case ND_TUPLE_QVM: return "QVM"; + case ND_TUPLE_OVM: return "OVM"; + case ND_TUPLE_M128: return "M128"; + case ND_TUPLE_DUP: return "DUP"; + case ND_TUPLE_T1_4X: return "4X"; + } + + return "unknown"; +} + + +static char *RoundingModeToString(ND_ROUNDING RoundingMode) +{ + switch (RoundingMode) + { + case ND_RND_RNE: return "RNE"; + case ND_RND_RD: return "RD"; + case ND_RND_RU: return "RU"; + case ND_RND_RZ: return "RZ"; + } + + return "unknown"; +} + + +static PyObject *_pydis_build_rex(ND_REX *rex) +{ + return Py_BuildValue("{s,B, s,B, s,B, s,B, s,B}", + "Rex", rex->Rex, + "b", rex->b, + "x", rex->x, + "r", rex->r, + "w", rex->w); +} + + +static PyObject *_pydis_build_modrm(ND_MODRM *modrm) +{ + return Py_BuildValue("{s,B, s,B, s,B, s,B}", + "ModRm", modrm->ModRm, + "rm", modrm->rm, + "reg", modrm->reg, + "mod", modrm->mod); +} + + +static PyObject *_pydis_build_sib(ND_SIB *sib) +{ + return Py_BuildValue("{s,B, s,B, s,B, s,B}", + "Sib", sib->Sib, + "base", sib->base, + "index", sib->index, + "scale", sib->scale); +} + + +static PyObject *_pydis_build_drex(ND_DREX *drex) +{ + return Py_BuildValue("{s,B, s,B, s,B, s,B, s,B, s,B, s,B}", + "Drex", drex->Drex, + "b", drex->b, + "x", drex->x, + "r", drex->r, + "oc0", drex->oc0, + "vd", drex->vd, + "d", drex->d); +} + + +static PyObject *_pydis_build_op_access(ND_OPERAND_ACCESS *access) +{ + return Py_BuildValue("{s,B, s,B, s,B, s,B, s,B}", + "Access", access->Access, + "Read", access->Read, + "Write", access->Write, + "CondRead", access->CondRead, + "CondWrite", access->CondWrite); +} + + +static PyObject *_pydis_build_op_flags(ND_OPERAND_FLAGS *flags) +{ + return Py_BuildValue("{s,B, s,B, s,B, s,B}", + "Flags", flags->Flags, + "IsDefault", flags->IsDefault, + "SignExtendedOp1", flags->SignExtendedOp1, + "SignExtendedDws", flags->SignExtendedDws); +} + + +static PyObject *_pydis_build_op_reg(ND_OPDESC_REGISTER *reg) +{ + return Py_BuildValue("{s,s, s,B, s,I, s,I}", + "Type", RegTypeToString(reg->Type), + "Size", reg->Size, + "Reg", reg->Reg, + "Count", reg->Count); +} + + +static PyObject *_pydis_build_op_memory(ND_OPDESC_MEMORY *mem) +{ + PyObject *nd_vsib = Py_BuildValue("{s,B, s,B, s,B}", + "IndexSize", mem->Vsib.IndexSize, + "ElemSize", mem->Vsib.ElemSize, + "ElemCount", mem->Vsib.ElemCount); + + PyObject *p = Py_BuildValue("{" + "s,B," // HasSeg + "s,B," // HasBase + "s,B," // HasIndex + "s,B," // HasDisp + "s,B," // HasCompDisp + "s,B," // HasBroadcast + + "s,B," // IsRipRel + "s,B," // IsStack + "s,B," // IsShadowStack + "s,B," // IsDirect + "s,B," // IsBitbase + "s,B," // IsAG + "s,B," // IsMib + "s,B," // IsVsib + + "s,B," // BaseSize + "s,B," // IndexSize + "s,B," // DispSize + "s,B," // CompDispSize + + "s,O," // Vsib + + "s,B," // Seg + "s,B," // Base + "s,B," // Index + "s,B," // Scale + + "s,K" // Disp + "}", + + "HasSeg", mem->HasSeg, + "HasBase", mem->HasBase, + "HasIndex", mem->HasIndex, + "HasDisp", mem->HasDisp, + "HasCompDisp", mem->HasCompDisp, + "HasBroadcast", mem->HasBroadcast, + + "IsRipRel", mem->IsRipRel, + "IsStack", mem->IsStack, + "IsShadowStack", mem->IsShadowStack, + "IsDirect", mem->IsDirect, + "IsBitbase", mem->IsBitbase, + "IsAG", mem->IsAG, + "IsMib", mem->IsMib, + "IsVsib", mem->IsVsib, + + "BaseSize", mem->BaseSize, + "IndexSize", mem->IndexSize, + "DispSize", mem->DispSize, + "CompDispSize", mem->CompDispSize, + + "Vsib", nd_vsib, + + "Seg", mem->Seg, + "Base", mem->Base, + "Index", mem->Index, + "Scale", mem->Index, + + "Disp", mem->Disp); + Py_XDECREF(nd_vsib); + + return p; +} + + +static PyObject *_pydis_build_op_immediate(ND_OPDESC_IMMEDIATE *imm) +{ + return Py_BuildValue("{s,K}", "Imm", imm->Imm); +} + + +static PyObject *_pydis_build_op_rel_offset(ND_OPDESC_RELOFFSET *rel_offset) +{ + return Py_BuildValue("{s,K}", "Rel", rel_offset->Rel); +} + + +static PyObject *_pydis_build_op_address(ND_OPDESC_ADDRESS *address) +{ + return Py_BuildValue("{s,H, s,K}", + "BaseSeg", address->BaseSeg, + "Offset", address->Offset); +} + + +static PyObject *_pydis_build_op_const(ND_OPDESC_CONSTANT *constant) +{ + return Py_BuildValue("{s,K}", "Const", constant->Const); +} + + +static PyObject *_pydis_build_operand(ND_OPERAND *operand) +{ + PyObject *nd_access = _pydis_build_op_access(&operand->Access); + PyObject *nd_flags = _pydis_build_op_flags(&operand->Flags); + + PyObject *nd_operand = NULL; + + switch (operand->Type) + { + case ND_OP_REG: + nd_operand = _pydis_build_op_reg(&operand->Info.Register); + break; + case ND_OP_MEM: + nd_operand = _pydis_build_op_memory(&operand->Info.Memory); + break; + case ND_OP_IMM: + nd_operand = _pydis_build_op_immediate(&operand->Info.Immediate); + break; + case ND_OP_OFFS: + nd_operand = _pydis_build_op_rel_offset(&operand->Info.RelativeOffset); + break; + case ND_OP_ADDR: + nd_operand = _pydis_build_op_address(&operand->Info.Address); + break; + case ND_OP_CONST: + nd_operand = _pydis_build_op_const(&operand->Info.Constant); + break; + case ND_OP_BANK: + nd_operand = Py_BuildValue("{}"); + break; + default: + PyErr_SetString(PyExc_RuntimeError, "invalid operand type... Talk with @csirb to update pydis..."); + Py_RETURN_NONE; + } + + PyObject *p = Py_BuildValue("{" + "s,s," // Type + "s,s," // Encoding + "s,I," // Size + "s,I," // RawSize + "s,O," // Access + "s,O," // Flags + "s,O" // Operand + "}", + "Type", OperandTypeToString(operand->Type), + "Encoding", OperandEncodingToString(operand->Encoding), + "Size", operand->Size, + "RawSize", operand->RawSize, + "Access", nd_access, + "Flags", nd_flags, + "Operand", nd_operand); + + Py_XDECREF(nd_access); + Py_XDECREF(nd_flags); + Py_XDECREF(nd_operand); + + return p; +} + + +static PyObject *_pydis_build_operands(ND_OPERAND *operands, size_t count) +{ + char op_str_format[400] = {'[', 0}; + size_t last = 1; + + PyObject *nd_operands[ND_MAX_OPERAND] = {0}; + size_t op; + + for (op = 0; op < count && last < sizeof(op_str_format); op++) + { + if (op > 0) + { + op_str_format[last++] = ','; + } + + op_str_format[last++] = 'O'; + + nd_operands[op] = _pydis_build_operand(&operands[op]); + } + + op_str_format[last] = ']'; + + PyObject *p = Py_BuildValue(op_str_format, + nd_operands[0], + nd_operands[1], + nd_operands[2], + nd_operands[3], + nd_operands[4], + nd_operands[5], + nd_operands[6], + nd_operands[7], + nd_operands[8], + nd_operands[9]); + + for (size_t o = 0; o < op; o++) + { + Py_XDECREF(nd_operands[o]); + } + + return p; +} + + +static PyObject *_pydis_build_exs(INSTRUX *instr) +{ + return Py_BuildValue("{" + "s,B," // w + "s,B," // r + "s,B," // x + "s,B," // b + "s,B," // rp + "s,B," // p + "s,B," // m + "s,B," // l + "s,B," // v + "s,B," // vp + "s,B," // bm + "s,B," // e + "s,B," // z + "s,B," // k + "s,B" // s + "}", + "w", instr->Exs.w, + "r", instr->Exs.r, + "x", instr->Exs.x, + "b", instr->Exs.b, + "rp", instr->Exs.rp, + "p", instr->Exs.p, + "m", instr->Exs.m, + "l", instr->Exs.l, + "v", instr->Exs.v, + "vp", instr->Exs.vp, + "bm", instr->Exs.bm, + "e", instr->Exs.e, + "z", instr->Exs.z, + "k", instr->Exs.k, + "s", instr->Exs.s); +} + + +static PyObject *_pydis_build_address(INSTRUX *instr) +{ + return Py_BuildValue("{s,I, s,H}", + "Ip", instr->Address.Ip, + "Cs", instr->Address.Cs); +} + + +static PyObject *_pydis_build_cpuid_flag(ND_CPUID_FLAG *cpuid_flag) +{ + return Py_BuildValue("{" + "s,K," // Flag + "s,I," // Leaf + "s,I," // SubLeaf + "s,B," // Reg + "s,B" // Bit + "}", + "Flag", cpuid_flag->Flag, + "Leaf", cpuid_flag->Leaf, + "SubLeaf", cpuid_flag->SubLeaf, + "Reg", cpuid_flag->Reg, + "Bit", cpuid_flag->Bit); +} + + +static PyObject *_pydis_build_flags_access(INSTRUX *instr) +{ + return Py_BuildValue("{" + "s,B," // RegAccess + "s,I," // Tested + "s,I," // Modified + "s,I," // Set + "s,I," // Cleared + "s,I" // Undefined + "}", + "RegAccess", instr->FlagsAccess.RegAccess, + "Tested", instr->FlagsAccess.Tested, + "Modified", instr->FlagsAccess.Modified, + "Set", instr->FlagsAccess.Set, + "Cleared", instr->FlagsAccess.Cleared, + "Undefined", instr->FlagsAccess.Undefined); +} + + +static PyObject *_pydis_build_valid_modes(ND_VALID_MODES *valid_modes) +{ + return Py_BuildValue("{" + "s,H," // Raw + + "s,B," // Ring0 + "s,B," // Ring1 + "s,B," // Ring2 + "s,B," // Ring3 + + "s,B," // Real + "s,B," // V8086 + "s,B," // Protected + "s,B," // Compatibility + "s,B," // Long + "s,B," // Smm + + "s,B," // Sgx + "s,B," // Tsx + + "s,B," // VmxRoot + "s,B," // VmxNonRoot + "s,B" // VmxOff + "}", + + "Raw", valid_modes->Raw, + + "Ring0", valid_modes->Ring0, + "Ring1", valid_modes->Ring1, + "Ring2", valid_modes->Ring2, + "Ring3", valid_modes->Ring3, + + "Real", valid_modes->Real, + "V8086", valid_modes->V8086, + "Protected", valid_modes->Protected, + "Compatibility", valid_modes->Compat, + "Long", valid_modes->Long, + "Smm", valid_modes->Smm, + + "Sgx", valid_modes->Sgx, + "Tsx", valid_modes->Tsx, + + "VmxRoot", valid_modes->VmxRoot, + "VmxNonRoot", valid_modes->VmxNonRoot, + "VmxOff", valid_modes->VmxOff); +} + + +static PyObject *_pydis_build_valid_prefixes(ND_VALID_PREFIXES *valid_prefixes) +{ + return Py_BuildValue("{" + "s,H," // Raw + "s,B," // Rep, + "s,B," // RepCond, + "s,B," // Lock, + "s,B," // Hle, + "s,B," // Xacquire, + "s,B," // Xrelease, + "s,B," // Bnd, + "s,B," // Bhint, + "s,B," // HleNoLock, + "s,B" // Dnt, + "}", + + "Raw", valid_prefixes->Raw, + "Rep", valid_prefixes->Rep, + "RepCond", valid_prefixes->RepCond, + "Lock", valid_prefixes->Lock, + "Hle", valid_prefixes->Hle, + "Xacquire", valid_prefixes->Xacquire, + "Xrelease", valid_prefixes->Xrelease, + "Bnd", valid_prefixes->Bnd, + "Bhint", valid_prefixes->Bhint, + "HleNoLock", valid_prefixes->HleNoLock, + "Dnt", valid_prefixes->Dnt); +} + + +static PyObject *_pydis_build_valid_decorators(ND_VALID_DECORATORS *valid_deorators) +{ + return Py_BuildValue("{" + "s,H," // Raw + "s,B," // Er + "s,B," // Sae + "s,B," // Zero + "s,B," // Mask + "s,B" // Broadcast + "}", + + "Raw", valid_deorators->Raw, + "Er", valid_deorators->Er, + "Sae", valid_deorators->Sae, + "Zero", valid_deorators->Zero, + "Mask", valid_deorators->Mask, + "Broadcast", valid_deorators->Broadcast); +} + + +static PyObject *_pydis_build_instr_dict(INSTRUX *instr, uint64_t rip) +{ + PyObject *nd_rex = _pydis_build_rex(&instr->Rex); + + PyObject *nd_modrm = _pydis_build_modrm(&instr->ModRm); + + PyObject *nd_sib = _pydis_build_sib(&instr->Sib); + + PyObject *nd_drex = _pydis_build_drex(&instr->Drex); + + PyObject *nd_op_array = _pydis_build_operands(instr->Operands, instr->OperandsCount); + + PyObject *nd_exs = _pydis_build_exs(instr); + + PyObject *nd_address = _pydis_build_address(instr); + + PyObject *nd_cpuid_flag = _pydis_build_cpuid_flag(&instr->CpuidFlag); + + PyObject *nd_valid_modes = _pydis_build_valid_modes(&instr->ValidModes); + PyObject *nd_valid_prefixes = _pydis_build_valid_prefixes(&instr->ValidPrefixes); + PyObject *nd_valid_decorators = _pydis_build_valid_decorators(&instr->ValidDecorators); + + char instr_text[ND_MIN_BUF_SIZE] = {0}; + NDSTATUS status = nd_to_text(instr, rip, sizeof(instr_text), instr_text); + if (!ND_SUCCESS(status)) + { + strcpy(instr_text, ""); + } + + PyObject *nd_flags_access = _pydis_build_flags_access(instr); + + PyObject *p = Py_BuildValue("{" + "s,B," // DefCode + "s,B," // DefData + "s,B," // DefStack + "s,B," // EncMode + "s,B," // VexMode + "s,B," // AddrMode, + "s,B," // OpMode, + "s,B," // EfOpMode, + "s,B," // VecMode, + "s,B," // EfVecMode, + + "s,B," // HasRex, + "s,B," // HasVex, + "s,B," // HasXop, + "s,B," // HasEvex, + "s,B," // HasOpSize, + "s,B," // HasAddrSize, + "s,B," // HasLock, + "s,B," // HasRepnzXacquireBnd, + "s,B," // HasRepRepzXrelease, + "s,B," // HasSeg, + + "s,B," // IsRepeated, + "s,B," // IsXacquireEnabled, + "s,B," // IsXreleaseEnabled, + "s,B," // IsRipRelative, + "s,B," // IsCetTracked, + + "s,B," // HasModRm, + "s,B," // HasSib, + "s,B," // HasDrex, + "s,B," // HasDisp, + "s,B," // HasAddr, + "s,B," // HasMoffset, + "s,B," // HasImm1, + "s,B," // HasImm2, + "s,B," // HasImm3, + "s,B," // HasRelOffs, + "s,B," // HasSseImm, + "s,B," // HasCompDisp, + "s,B," // HasBroadcast, + "s,B," // HasMask, + "s,B," // HasZero, + "s,B," // HasEr, + "s,B," // HasSae, + + "s,B," // SignDisp, + + "s,B," // HasMandatory66, + "s,B," // HasMandatoryF2, + "s,B," // HasMandatoryF3, + + "s,B," // Length, + + "s,B," // WordLength, + "s,B," // PrefLength, + + "s,B," // OpLength, + "s,B," // DispLength, + "s,B," // AddrLength, + "s,B," // MoffsetLength, + "s,B," // Imm1Length, + "s,B," // Imm2Length, + "s,B," // Imm3Length, + "s,B," // RelOffsLength, + + "s,B," // OpOffset, + "s,B," // MainOpOffset, + "s,B," // DispOffset, + "s,B," // AddrOffset, + "s,B," // MoffsetOffset, + "s,B," // Imm1Offset, + "s,B," // Imm2Offset, + "s,B," // Imm3Offset, + + "s,B," // RelOffsOffset, + "s,B," // SseImmOffset, + "s,B," // ModRmOffset, + + "s,B," // StackWords, + + "s,B," // Rep, + "s,B," // Seg, + + "s,O," // Rex, + "s,O," // ModRm, + "s,O," // Sib, + "s,O," // Drex, + + "s,O," // Exs, + + "s,O," // Address, + + "s,K," // Moffset, + "s,I," // Displacement, + "s,I," // RelativeOffset, + "s,K," // Immediate1, + "s,B," // Immediate2, + "s,B," // Immediate3, + "s,B," // SseImmediate, + "s,B," // SseCondition, + "s,B," // Condition, + "s,B," // Predicate, + + "s,B," // OperandsCount, + "s,B," // ExpOperandsCount, + + "s,H," // OperandsEncodingMap, + "s,O," // Operands, + + "s,B," // RipAccess, + "s,B," // StackAccess, + "s,B," // MemoryAccess, + + "s,O," // FlagsAccess, + + "s,s," // TupleType, + "s,s," // RoundingMode, + + "s,I," // Attributes, + + "s,I," // Iclass, + "s,I," // Category, + "s,I," // IsaSet, + "s,O," // CpuidFlag, + + "s,O," // ValidModes, + "s,O," // ValidPrefixes, + "s,O," // ValidDecorators, + + "s,s," // Mnemonic, + "s,y#," // OpCodeBytes, + "s,B," // PrimaryOpCode, + "s,y#," // InstructionBytes, + "s,s" // NdToText + "}", + + "DefCode", instr->DefCode, + "DefData", instr->DefData, + "DefStack", instr->DefStack, + "EncMode", instr->EncMode, + "VexMode", instr->VexMode, + "AddrMode", instr->AddrMode, + "OpMode", instr->OpMode, + "EfOpMode", instr->EfOpMode, + "VecMode", instr->VecMode, + "EfVecMode", instr->EfVecMode, + + "HasRex", instr->HasRex, + "HasVex", instr->HasVex, + "HasXop", instr->HasXop, + "HasEvex", instr->HasEvex, + "HasOpSize", instr->HasOpSize, + "HasAddrSize", instr->HasAddrSize, + "HasLock", instr->HasLock, + "HasRepnzXacquireBnd", instr->HasRepnzXacquireBnd, + "HasRepRepzXrelease", instr->HasRepRepzXrelease, + "HasSeg", instr->HasSeg, + + "IsRepeated", instr->IsRepeated, + "IsXacquireEnabled", instr->IsXacquireEnabled, + "IsXreleaseEnabled", instr->IsXreleaseEnabled, + "IsRipRelative", instr->IsRipRelative, + "IsCetTracked", instr->IsCetTracked, + + "HasModRm", instr->HasModRm, + "HasSib", instr->HasSib, + "HasDrex", instr->HasDrex, + "HasDisp", instr->HasDisp, + "HasAddr", instr->HasAddr, + "HasMoffset", instr->HasMoffset, + "HasImm1", instr->HasImm1, + "HasImm2", instr->HasImm2, + "HasImm3", instr->HasImm3, + "HasRelOffs", instr->HasRelOffs, + "HasSseImm", instr->HasSseImm, + "HasCompDisp", instr->HasCompDisp, + "HasBroadcast", instr->HasBroadcast, + "HasMask", instr->HasMask, + "HasZero", instr->HasZero, + "HasEr", instr->HasEr, + "HasSae", instr->HasSae, + + "SignDisp", instr->SignDisp, + + "HasMandatory66", instr->HasMandatory66, + "HasMandatoryF2", instr->HasMandatoryF2, + "HasMandatoryF3", instr->HasMandatoryF3, + + "Length", instr->Length, + + "WordLength", instr->WordLength, + "PrefLength", instr->PrefLength, + + "OpLength", instr->OpLength, + "DispLength", instr->DispLength, + "AddrLength", instr->AddrLength, + "MoffsetLength", instr->MoffsetLength, + "Imm1Length", instr->Imm1Length, + "Imm2Length", instr->Imm2Length, + "Imm3Length", instr->Imm3Length, + "RelOffsLength", instr->RelOffsLength, + + "OpOffset", instr->OpOffset, + "MainOpOffset", instr->MainOpOffset, + "DispOffset", instr->DispOffset, + "AddrOffset", instr->AddrOffset, + "MoffsetOffset", instr->MoffsetOffset, + "Imm1Offset", instr->Imm1Offset, + "Imm2Offset", instr->Imm2Offset, + "Imm3Offset", instr->Imm3Offset, + + "RelOffsOffset", instr->RelOffsOffset, + "SseImmOffset", instr->SseImmOffset, + "ModRmOffset", instr->ModRmOffset, + + "StackWords", instr->StackWords, + + "Rep", instr->Rep, + "Seg", instr->Seg, + "Rex", nd_rex, + "ModRm", nd_modrm, + "Sib", nd_sib, + "Drex", nd_drex, + + "Exs", nd_exs, + + "Address", nd_address, + + "Moffset", instr->Moffset, + "Displacement", instr->Displacement, + "RelativeOffset", instr->RelativeOffset, + "Immediate1", instr->Immediate1, + "Immediate2", instr->Immediate2, + "Immediate3", instr->Immediate3, + "SseImmediate", instr->SseImmediate, + "SseCondition", instr->SseCondition, + "Condition", instr->Condition, + "Predicate", instr->Predicate, + + "OperandsCount", instr->OperandsCount, + "ExpOperandsCount", instr->ExpOperandsCount, + + "OperandsEncodingMap", instr->OperandsEncodingMap, + "Operands", nd_op_array, + + "RipAccess", instr->RipAccess, + "StackAccess", instr->StackAccess, + "MemoryAccess", instr->MemoryAccess, + + "FlagsAccess", nd_flags_access, + + "TupleType", TupleTypeToString(instr->TupleType), + "RoundingMode", RoundingModeToString(instr->RoundingMode), + + "Attributes", instr->Attributes, + + "Iclass", instr->Iclass, + "Category", instr->Category, + "IsaSet", instr->IsaSet, + "CpuidFlag", nd_cpuid_flag, + + "ValidModes", nd_valid_modes, + "ValidPrefixes", nd_valid_prefixes, + "ValidDecorators", nd_valid_decorators, + + "Mnemonic", instr->Mnemonic, + "OpCodeBytes", instr->OpCodeBytes, sizeof(instr->OpCodeBytes), + "PrimaryOpCode", instr->PrimaryOpCode, + "InstructionBytes", instr->InstructionBytes, instr->Length, + "Text", instr_text); + + Py_XDECREF(nd_rex); + Py_XDECREF(nd_modrm); + Py_XDECREF(nd_sib); + Py_XDECREF(nd_drex); + Py_XDECREF(nd_op_array); + Py_XDECREF(nd_exs); + Py_XDECREF(nd_address); + Py_XDECREF(nd_cpuid_flag); + Py_XDECREF(nd_valid_modes); + Py_XDECREF(nd_valid_prefixes); + Py_XDECREF(nd_valid_decorators); + Py_XDECREF(nd_flags_access); + + return p; +} + + +static uint8_t _pydis_py_code_to_disasm(uint8_t code) +{ + if (16 == code) + { + return ND_CODE_16; + } + else if (32 == code) + { + return ND_CODE_32; + } + else if (64 == code) + { + return ND_CODE_64; + } + + PyErr_Format(PyExc_ValueError, "Invalid code: %d (expected 16|32|64)\n", code); + return 0; +} + + +static uint8_t _pydis_py_data_to_disasm(uint8_t data) +{ + if (16 == data) + { + return ND_DATA_16; + } + else if (32 == data) + { + return ND_DATA_32; + } + else if (64 == data) + { + return ND_DATA_64; + } + + PyErr_Format(PyExc_ValueError, "Invalid data: %d (expected 16|32|64)\n", data); + return 0; +} + + +static uint8_t _pydis_py_stack_to_disasm(uint8_t stack) +{ + if (16 == stack) + { + return ND_STACK_16; + } + else if (32 == stack) + { + return ND_STACK_32; + } + else if (64 == stack) + { + return ND_STACK_64; + } + + PyErr_Format(PyExc_ValueError, "Invalid stack: %d (expected 16|32|64)\n", stack); + return 0; +} + + +static PyObject *pydis_decode_ex(PyObject *self, PyObject *args) +{ + char *buf = NULL; + Py_ssize_t bufsize = 0; + uint64_t rip = 0; + uint8_t code, data; + + (void)self; + + if (!PyArg_ParseTuple(args, "s#BB|K", &buf, &bufsize, &code, &data, &rip)) + { + PyErr_SetString(PyExc_ValueError, "invalid arguments. expected: "); + Py_RETURN_NONE; + } + + code = _pydis_py_code_to_disasm(code); + data = _pydis_py_data_to_disasm(data); + + if (PyErr_Occurred()) + { + Py_RETURN_NONE; + } + + INSTRUX instr; + + NDSTATUS status = nd_decode_ex(&instr, buf, bufsize, code, data); + if (!ND_SUCCESS(status)) + { + Py_RETURN_NONE; + } + + return _pydis_build_instr_dict(&instr, rip); +} + + +static PyObject *pydis_decode_ex2(PyObject *self, PyObject *args) +{ + char *buf = NULL; + char *str_vend = NULL; + Py_ssize_t bufsize = 0; + uint64_t rip = 0; + uint8_t code, data, stack, vend; + + (void)self; + + if (!PyArg_ParseTuple(args, "s#BBBs|K", &buf, &bufsize, &code, &data, &stack, &str_vend, &rip)) + { + PyErr_SetString(PyExc_ValueError, "invalid arguments. expected: "); + Py_RETURN_NONE; + } + + if (0 == strcmp(str_vend, "any")) + { + vend = ND_VEND_ANY; + } + else if (0 == strcmp(str_vend, "intel")) + { + vend = ND_VEND_INTEL; + } + else if (0 == strcmp(str_vend, "amd")) + { + vend = ND_VEND_AMD; + } + else if (0 == strcmp(str_vend, "geode")) + { + vend = ND_VEND_GEODE; + } + else if (0 == strcmp(str_vend, "cyrix")) + { + vend = ND_VEND_CYRIX; + } + else + { + PyErr_Format(PyExc_ValueError, "invalid vendor: '%s'", str_vend); + Py_RETURN_NONE; + } + + code = _pydis_py_code_to_disasm(code); + data = _pydis_py_data_to_disasm(data); + stack = _pydis_py_stack_to_disasm(stack); + + if (PyErr_Occurred()) + { + Py_RETURN_NONE; + } + + INSTRUX instr; + + NDSTATUS status = nd_decode_ex2(&instr, buf, bufsize, code, data, stack, vend); + if (!ND_SUCCESS(status)) + { + Py_RETURN_NONE; + } + + return _pydis_build_instr_dict(&instr, rip); +} + + +static PyObject *pydis_to_text(PyObject *self, PyObject *args) +{ + char *buf = NULL; + Py_ssize_t bufsize = 0; + uint64_t rip = 0; + uint8_t code, data; + + (void)self; + + if (!PyArg_ParseTuple(args, "s#BB|K", &buf, &bufsize, &code, &data, &rip)) + { + PyErr_SetString(PyExc_ValueError, "invalid arguments. expected: "); + Py_RETURN_NONE; + } + + code = _pydis_py_code_to_disasm(code); + data = _pydis_py_data_to_disasm(data); + + if (PyErr_Occurred()) + { + Py_RETURN_NONE; + } + + INSTRUX instr; + + NDSTATUS status = nd_decode_ex(&instr, buf, bufsize, code, data); + if (!ND_SUCCESS(status)) + { + Py_RETURN_NONE; + } + + char instr_text[ND_MIN_BUF_SIZE] = {0}; + + status = nd_to_text(&instr, rip, sizeof(instr_text), instr_text); + if (!ND_SUCCESS(status)) + { + Py_RETURN_NONE; + } + + return Py_BuildValue("{s,s,s,y#}", "text", instr_text, "bytes", instr.InstructionBytes, instr.Length); +} + + +static PyMethodDef module_methods[] = { + {"nd_decode_ex", pydis_decode_ex, METH_VARARGS, pydis_decode_ex_docstring}, + {"nd_decode_ex2", pydis_decode_ex2, METH_VARARGS, pydis_decode_ex2_docstring}, + {"nd_decode", pydis_decode_ex, METH_VARARGS, pydis_decode_docstring}, + {"nd_to_text", pydis_to_text, METH_VARARGS, pydis_to_text_docstring}, + {NULL, NULL, 0, NULL} +}; + + +static struct PyModuleDef PyDis = +{ + PyModuleDef_HEAD_INIT, + "pydis", // name of module + module_docstring, + -1, // size of per-interpreter state of the module, or -1 if the module keeps state in global variables + module_methods +}; + +PyMODINIT_FUNC PyInit__pydis(void) +{ + return PyModule_Create(&PyDis); +} diff --git a/pydis/_pydis/pydis.c b/pydis/_pydis/pydis.c new file mode 100644 index 0000000..c0474ab --- /dev/null +++ b/pydis/_pydis/pydis.c @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2020 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +#include "pydis.h" +#include + + +int nd_decode_ex(INSTRUX *instrux, void *code, size_t size, int def_code, int def_data) +{ + return NdDecodeEx(instrux, code, size, def_code, def_data); +} + + +int nd_decode_ex2(INSTRUX *instrux, void *code, size_t size, int def_code, int def_data, int def_stack, int prefered_vendor) +{ + return NdDecodeEx2(instrux, code, size, def_code, def_data, def_stack, prefered_vendor); +} + + +int nd_to_text(INSTRUX *instrux, size_t rip, size_t bufsize, char *buf) +{ + return NdToText(instrux, rip, bufsize, buf); +} + + +#include + +int +nd_vsnprintf_s(char *str, size_t sizeOfBuffer, size_t count, const char *format, va_list args) +{ + (void)(sizeOfBuffer); + return vsnprintf(str, count, format, args); +} diff --git a/pydis/_pydis/pydis.h b/pydis/_pydis/pydis.h new file mode 100644 index 0000000..e10c380 --- /dev/null +++ b/pydis/_pydis/pydis.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2020 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _PYDIS_H_ +#define _PYDIS_H_ + +#include +#include +#include + +#include "bddisasm.h" + +int nd_decode_ex(INSTRUX *instrux, void *code, size_t size, int def_code, int def_data); + +int nd_decode_ex2(INSTRUX *instrux, void *code, size_t size, int def_code, int def_data, int def_stack, int prefered_vendor); + +int nd_to_text(INSTRUX *instrux, size_t rip, size_t bufsize, char *buf); + +#endif // _PYDIS_H_ diff --git a/pydis/pydis/__init__.py b/pydis/pydis/__init__.py new file mode 100644 index 0000000..d494aa2 --- /dev/null +++ b/pydis/pydis/__init__.py @@ -0,0 +1,7 @@ +# +# Copyright (c) 2020 Bitdefender +# SPDX-License-Identifier: Apache-2.0 +# +from pydis.disasm import NdInstruction, nd_decode, nd_decode_ex, nd_decode_ex2, nd_to_text + +from pydis.helpers import disassemble_file, disassemble_hexstring, print_instruction diff --git a/pydis/pydis/__main__.py b/pydis/pydis/__main__.py new file mode 100644 index 0000000..080dbd2 --- /dev/null +++ b/pydis/pydis/__main__.py @@ -0,0 +1,11 @@ +# +# Copyright (c) 2020 Bitdefender +# SPDX-License-Identifier: Apache-2.0 +# +"""Early initialization and main entry point.""" + +from pydis.core import main + +if __name__ == "__main__": + main() + diff --git a/pydis/pydis/__version__.py b/pydis/pydis/__version__.py new file mode 100644 index 0000000..5d82b77 --- /dev/null +++ b/pydis/pydis/__version__.py @@ -0,0 +1,9 @@ +# +# Copyright (c) 2020 Bitdefender +# SPDX-License-Identifier: Apache-2.0 +# +VERSION = (0, 0, 1) + +__title__ = 'pydis' +__description__ = 'Python Disassembler' +__version__ = '.'.join(map(str, VERSION)) diff --git a/pydis/pydis/app.py b/pydis/pydis/app.py new file mode 100644 index 0000000..e14e798 --- /dev/null +++ b/pydis/pydis/app.py @@ -0,0 +1,15 @@ +# +# Copyright (c) 2020 Bitdefender +# SPDX-License-Identifier: Apache-2.0 +# +from pydis.disasm import * +from pydis.helpers import * + + +def run(args): + if args.file: + return disassemble_file(args.file, offset=args.offset, size=args.size, rip=args.rip, + arch=args.arch, highlight=args.highlight, ext_info=args.ext_info) + elif args.hexstring: + return disassemble_hexstring(args.hexstring, offset=args.offset, size=args.size, rip=args.rip, + arch=args.arch, highlight=args.highlight, ext_info=args.ext_info) diff --git a/pydis/pydis/core.py b/pydis/pydis/core.py new file mode 100644 index 0000000..ff92e98 --- /dev/null +++ b/pydis/pydis/core.py @@ -0,0 +1,52 @@ +# +# Copyright (c) 2020 Bitdefender +# SPDX-License-Identifier: Apache-2.0 +# +"""Early initialization and main entry point.""" + +import sys +import argparse +import pydis + + +def _auto_int(x): + return int(x, 0) + + +def _get_argparser(): + """Get the argpase parser.""" + parser = argparse.ArgumentParser(prog='pydis') + + parser.add_argument('-b', '--arch', choices=[16, 32, 64], default=64, type=int) + + group = parser.add_mutually_exclusive_group() + group.add_argument('-f', '--file', dest='file') + group.add_argument('--hex', dest='hexstring', nargs='*') + + parser.add_argument('-r', '--rip', dest='rip', default=0, type=_auto_int, + help='Disassemble considering the given RIP.') + parser.add_argument('--offset', dest='offset', default=0, type=_auto_int, + help='Disassemble starting at the given offset. Only valid for --file option.') + parser.add_argument('--size', dest='size', default=0, type=_auto_int, + help='Disassemble only the given size. Only valid for --file option.') + parser.add_argument('-c', '--highlight', dest='highlight', action='store_true', + help='Color the instruction bytes by group (opcode, prefix, etc).') + parser.add_argument('-e', '--ext-info', dest='ext_info', action='store_true') + parser.add_argument('--vendor', dest='vendor', + choices=['intel', 'amd', 'cyrix', 'geode', 'any'], default='any') + + return parser + + +def main(): + """Parse the args and run the app.""" + parser = _get_argparser() + + args = parser.parse_args(sys.argv[1:]) + + if not args.file and not args.hexstring: + parser.print_usage() + return 1 + + from pydis import app + app.run(args) diff --git a/pydis/pydis/disasm.py b/pydis/pydis/disasm.py new file mode 100644 index 0000000..92f20ce --- /dev/null +++ b/pydis/pydis/disasm.py @@ -0,0 +1,71 @@ +# +# Copyright (c) 2020 Bitdefender +# SPDX-License-Identifier: Apache-2.0 +# +"""Interface for disassembling code.""" + +import _pydis + +class NdInstruction(dict): + """Magic wrapper around a dictionary, that makes all the keys available + through dot notation (recursively). Examples: + + instruction['Length'] is now instruction.Length + instruction['InstructionBytes'] is now instruction.InstructionBytes + + You can still access the fileds the old way.""" + def __init__(self, *args, **kwargs): + super(NdInstruction, self).__init__(*args, **kwargs) + self.__dict__ = self + + # now set all the dict children to be the same + for key in self.__dict__: + if not isinstance(self.__dict__[key], dict): + continue + + self.__dict__[key] = NdInstruction(self.__dict__[key]) + + if 'Operands' in self.__dict__ and isinstance(self.Operands, dict): + for op in self.Operands: + self.Operands[op] = NdInstruction(self.Operands[op]) + + +def nd_to_text(code, arch_code_size, arch_data_size=0, rip=0): + if not arch_data_size: + arch_data_size = arch_code_size + + return _pydis.nd_to_text(code, arch_code_size, arch_data_size, rip) + + +def nd_decode(code, arch_code_size, arch_data_size=0, rip=0): + if not arch_data_size: + arch_data_size = arch_code_size + + instruction = _pydis.nd_decode_ex(code, arch_code_size, arch_data_size, rip) + + if not instruction: + return None + + return NdInstruction(instruction) + + +def nd_decode_ex(code, arch_code_size, arch_data_size=0, rip=0): + if not arch_data_size: + arch_data_size = arch_code_size + + instruction = _pydis.nd_decode_ex(code, arch_code_size, arch_data_size, rip) + + if not instruction: + return None + + return NdInstruction(instruction) + + +def nd_decode_ex2(code, arch_code_size, arch_data_size, arch_stack_size, vendor, rip=0): + instruction = _pydis.nd_decode_ex2(code, arch_code_size, arch_data_size, + arch_stack_size, vendor, rip) + + if not instruction: + return None + + return NdInstruction(instruction) diff --git a/pydis/pydis/helpers.py b/pydis/pydis/helpers.py new file mode 100644 index 0000000..32b0164 --- /dev/null +++ b/pydis/pydis/helpers.py @@ -0,0 +1,156 @@ +# +# Copyright (c) 2020 Bitdefender +# SPDX-License-Identifier: Apache-2.0 +# +import os +import sys + +from pydis.disasm import * + +try: + from termcolor import colored +except: + colored = None + + +_SPACES = [ + '', + ' ', + ' ', + ' ', + ' ', + ' ', + ' ', + ' ', + ' ', + ' ', + ' ', + ' ', + ' ', + ' ', + ' ', + ' ', +] + + +def print_internal(string, foreground=None, highlight=True): + no_colors = (foreground is None) or (not highlight) + + if not colored or no_colors: + sys.stdout.write(string) + else: + text = colored(string, foreground) + sys.stdout.write(text) + + +def print_instruction(instruction, rip, highlight=False, ext_info=False): + k = 0 + + print_internal('%016x ' % rip) + + # prefixes + for ibyte in range(0, instruction.PrefLength): + print_internal('%02x' % instruction.InstructionBytes[ibyte]) + + # opcodes + k += instruction.PrefLength + for ibyte in range(k, k + instruction.OpLength): + print_internal('%02x' % instruction.InstructionBytes[ibyte], 'green', highlight) + + # modrm and sib + k += instruction.OpLength + for ibyte in range(k, k + instruction.HasModRm + instruction.HasSib): + print_internal('%02x' % instruction.InstructionBytes[ibyte], 'yellow', highlight) + + # displacement + k += instruction.HasModRm + instruction.HasSib + for ibyte in range(k, k + instruction.DispLength): + print_internal('%02x' % instruction.InstructionBytes[ibyte], 'blue', highlight) + + # relative offset/moffset/immediates + rest = instruction.Imm1Length + instruction.Imm2Length + instruction.RelOffsLength + \ + instruction.MoffsetLength + instruction.HasSseImm + instruction.AddrLength + + k += instruction.DispLength + for ibyte in range(k, k + rest): + print_internal('%02x' % instruction.InstructionBytes[ibyte], 'red', highlight) + + # the rest of the bytes + k += rest + for ibyte in range(k, instruction.Length): + print_internal('%02x' % instruction.InstructionBytes[ibyte]) + + print_internal('%s' % _SPACES[16 - instruction.Length]) + print_internal('%s' % instruction.Text) + + if ext_info: + print_internal('\n') + print_internal('%r' % instruction) + + print_internal('\n') + + +def disassemble_file(filepath, offset=0, size=0, rip=0, arch=64, + highlight=True, vendor='any', ext_info=False): + if not filepath: + return + + with open(filepath, 'rb') as f: + total = 0 + file_size = os.path.getsize(filepath) + + if not size: + size = file_size + + while offset < file_size and total < size: + to_read = file_size - offset + if to_read > 15: + to_read = 15 + + f.seek(offset, 0) + buff = f.read(to_read) + + current_rip = rip + total + + instr = nd_decode_ex2(buff, arch, arch, arch, vendor, current_rip) + if instr: + print_instruction(instr, current_rip, highlight, ext_info) + offset += instr['Length'] + total += instr['Length'] + else: + sys.stdout.write('%016x %02x %s db 0x%02x' % (current_rip, buff[0], + _SPACES[15], buff[0])) + + if str.isalpha(chr(buff[0])): + sys.stdout.write(str(buff[0])) + + sys.stdout.write('\n') + + offset += 1 + total += 1 + + +def disassemble_hexstring(hexstring, offset=0, size=0, rip=0, arch=64, + highlight=True, vendor='any', ext_info=False): + if not hexstring: + return + + buff = bytes.fromhex(''.join(hexstring)) + + total = 0 + if not size: + size = len(buff) + + while total < size: + current_rip = rip + total + + instr = nd_decode_ex2(buff[total:total+16], arch, arch, arch, vendor, current_rip) + if instr: + print_instruction(instr, current_rip, highlight, ext_info) + offset += instr['Length'] + total += instr['Length'] + else: + sys.stdout.write('%016x %02x %s db 0x%02x\n' % (current_rip, buff[offset], + _SPACES[15], buff[offset])) + offset += 1 + total += 1 diff --git a/pydis/setup.py b/pydis/setup.py new file mode 100644 index 0000000..d14e72b --- /dev/null +++ b/pydis/setup.py @@ -0,0 +1,53 @@ +#!/usr/bin/env python +# +# Copyright (c) 2020 Bitdefender +# SPDX-License-Identifier: Apache-2.0 +# + +import os + +from codecs import open + +from setuptools import find_packages, setup, Command, Extension + +here = os.path.abspath(os.path.dirname(__file__)) + +packages = ['pydis'] + +requires = [ + "setuptools" +] + +about = {} +with open(os.path.join(here, 'pydis', '__version__.py'), 'r', 'utf-8') as f: + exec(f.read(), about) + +with open('README.md', 'r', 'utf-8') as f: + readme = f.read() + +setup( + name=about['__title__'], + version=about['__version__'], + packages=packages, + package_data={'': ['LICENSE', 'NOTICE'], 'pydis': ['*.pem']}, + package_dir={'pydis': 'pydis'}, + include_package_data=True, + python_requires=">=3.4", + setup_requires=['wheel'], + install_requires=requires, + zip_safe=False, + classifiers=[ + 'Programming Language :: Python :: 3.4', + 'Programming Language :: Python :: 3.5', + 'Programming Language :: Python :: 3.6', + 'Programming Language :: Python :: 3.7', + 'Programming Language :: Python :: Implementation :: CPython', + 'Programming Language :: Python :: Implementation :: PyPy' + ], + ext_modules = [Extension("_pydis", + sources = ["_pydis/_pydis.c", "_pydis/pydis.c"], + define_macros = [('AMD64', None), ('PYDIS_BUILD', None)], + include_dirs = ['../inc'], + libraries = ['bddisasm'], + library_dirs = ['../bin/x64/Release'])] +)